1 /* 2 * i386 CPUID, CPU class, definitions, models 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/units.h" 22 #include "qemu/cutils.h" 23 #include "qemu/qemu-print.h" 24 #include "qemu/hw-version.h" 25 #include "cpu.h" 26 #include "tcg/helper-tcg.h" 27 #include "sysemu/hvf.h" 28 #include "hvf/hvf-i386.h" 29 #include "kvm/kvm_i386.h" 30 #include "sev.h" 31 #include "qapi/error.h" 32 #include "qemu/error-report.h" 33 #include "qapi/qapi-visit-machine.h" 34 #include "standard-headers/asm-x86/kvm_para.h" 35 #include "hw/qdev-properties.h" 36 #include "hw/i386/topology.h" 37 #ifndef CONFIG_USER_ONLY 38 #include "sysemu/reset.h" 39 #include "qapi/qapi-commands-machine-target.h" 40 #include "exec/address-spaces.h" 41 #include "hw/boards.h" 42 #include "hw/i386/sgx-epc.h" 43 #endif 44 45 #include "disas/capstone.h" 46 #include "cpu-internal.h" 47 48 static void x86_cpu_realizefn(DeviceState *dev, Error **errp); 49 static void x86_cpu_get_supported_cpuid(uint32_t func, uint32_t index, 50 uint32_t *eax, uint32_t *ebx, 51 uint32_t *ecx, uint32_t *edx); 52 53 /* Helpers for building CPUID[2] descriptors: */ 54 55 struct CPUID2CacheDescriptorInfo { 56 enum CacheType type; 57 int level; 58 int size; 59 int line_size; 60 int associativity; 61 }; 62 63 /* 64 * Known CPUID 2 cache descriptors. 65 * From Intel SDM Volume 2A, CPUID instruction 66 */ 67 struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = { 68 [0x06] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 8 * KiB, 69 .associativity = 4, .line_size = 32, }, 70 [0x08] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 16 * KiB, 71 .associativity = 4, .line_size = 32, }, 72 [0x09] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB, 73 .associativity = 4, .line_size = 64, }, 74 [0x0A] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB, 75 .associativity = 2, .line_size = 32, }, 76 [0x0C] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 77 .associativity = 4, .line_size = 32, }, 78 [0x0D] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 79 .associativity = 4, .line_size = 64, }, 80 [0x0E] = { .level = 1, .type = DATA_CACHE, .size = 24 * KiB, 81 .associativity = 6, .line_size = 64, }, 82 [0x1D] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB, 83 .associativity = 2, .line_size = 64, }, 84 [0x21] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 85 .associativity = 8, .line_size = 64, }, 86 /* lines per sector is not supported cpuid2_cache_descriptor(), 87 * so descriptors 0x22, 0x23 are not included 88 */ 89 [0x24] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 90 .associativity = 16, .line_size = 64, }, 91 /* lines per sector is not supported cpuid2_cache_descriptor(), 92 * so descriptors 0x25, 0x20 are not included 93 */ 94 [0x2C] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB, 95 .associativity = 8, .line_size = 64, }, 96 [0x30] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB, 97 .associativity = 8, .line_size = 64, }, 98 [0x41] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB, 99 .associativity = 4, .line_size = 32, }, 100 [0x42] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 101 .associativity = 4, .line_size = 32, }, 102 [0x43] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 103 .associativity = 4, .line_size = 32, }, 104 [0x44] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 105 .associativity = 4, .line_size = 32, }, 106 [0x45] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 107 .associativity = 4, .line_size = 32, }, 108 [0x46] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 109 .associativity = 4, .line_size = 64, }, 110 [0x47] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 111 .associativity = 8, .line_size = 64, }, 112 [0x48] = { .level = 2, .type = UNIFIED_CACHE, .size = 3 * MiB, 113 .associativity = 12, .line_size = 64, }, 114 /* Descriptor 0x49 depends on CPU family/model, so it is not included */ 115 [0x4A] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB, 116 .associativity = 12, .line_size = 64, }, 117 [0x4B] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 118 .associativity = 16, .line_size = 64, }, 119 [0x4C] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB, 120 .associativity = 12, .line_size = 64, }, 121 [0x4D] = { .level = 3, .type = UNIFIED_CACHE, .size = 16 * MiB, 122 .associativity = 16, .line_size = 64, }, 123 [0x4E] = { .level = 2, .type = UNIFIED_CACHE, .size = 6 * MiB, 124 .associativity = 24, .line_size = 64, }, 125 [0x60] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 126 .associativity = 8, .line_size = 64, }, 127 [0x66] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB, 128 .associativity = 4, .line_size = 64, }, 129 [0x67] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 130 .associativity = 4, .line_size = 64, }, 131 [0x68] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB, 132 .associativity = 4, .line_size = 64, }, 133 [0x78] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 134 .associativity = 4, .line_size = 64, }, 135 /* lines per sector is not supported cpuid2_cache_descriptor(), 136 * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included. 137 */ 138 [0x7D] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 139 .associativity = 8, .line_size = 64, }, 140 [0x7F] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 141 .associativity = 2, .line_size = 64, }, 142 [0x80] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 143 .associativity = 8, .line_size = 64, }, 144 [0x82] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 145 .associativity = 8, .line_size = 32, }, 146 [0x83] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 147 .associativity = 8, .line_size = 32, }, 148 [0x84] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 149 .associativity = 8, .line_size = 32, }, 150 [0x85] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 151 .associativity = 8, .line_size = 32, }, 152 [0x86] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 153 .associativity = 4, .line_size = 64, }, 154 [0x87] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 155 .associativity = 8, .line_size = 64, }, 156 [0xD0] = { .level = 3, .type = UNIFIED_CACHE, .size = 512 * KiB, 157 .associativity = 4, .line_size = 64, }, 158 [0xD1] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB, 159 .associativity = 4, .line_size = 64, }, 160 [0xD2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 161 .associativity = 4, .line_size = 64, }, 162 [0xD6] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB, 163 .associativity = 8, .line_size = 64, }, 164 [0xD7] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 165 .associativity = 8, .line_size = 64, }, 166 [0xD8] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 167 .associativity = 8, .line_size = 64, }, 168 [0xDC] = { .level = 3, .type = UNIFIED_CACHE, .size = 1.5 * MiB, 169 .associativity = 12, .line_size = 64, }, 170 [0xDD] = { .level = 3, .type = UNIFIED_CACHE, .size = 3 * MiB, 171 .associativity = 12, .line_size = 64, }, 172 [0xDE] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB, 173 .associativity = 12, .line_size = 64, }, 174 [0xE2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 175 .associativity = 16, .line_size = 64, }, 176 [0xE3] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 177 .associativity = 16, .line_size = 64, }, 178 [0xE4] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 179 .associativity = 16, .line_size = 64, }, 180 [0xEA] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB, 181 .associativity = 24, .line_size = 64, }, 182 [0xEB] = { .level = 3, .type = UNIFIED_CACHE, .size = 18 * MiB, 183 .associativity = 24, .line_size = 64, }, 184 [0xEC] = { .level = 3, .type = UNIFIED_CACHE, .size = 24 * MiB, 185 .associativity = 24, .line_size = 64, }, 186 }; 187 188 /* 189 * "CPUID leaf 2 does not report cache descriptor information, 190 * use CPUID leaf 4 to query cache parameters" 191 */ 192 #define CACHE_DESCRIPTOR_UNAVAILABLE 0xFF 193 194 /* 195 * Return a CPUID 2 cache descriptor for a given cache. 196 * If no known descriptor is found, return CACHE_DESCRIPTOR_UNAVAILABLE 197 */ 198 static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache) 199 { 200 int i; 201 202 assert(cache->size > 0); 203 assert(cache->level > 0); 204 assert(cache->line_size > 0); 205 assert(cache->associativity > 0); 206 for (i = 0; i < ARRAY_SIZE(cpuid2_cache_descriptors); i++) { 207 struct CPUID2CacheDescriptorInfo *d = &cpuid2_cache_descriptors[i]; 208 if (d->level == cache->level && d->type == cache->type && 209 d->size == cache->size && d->line_size == cache->line_size && 210 d->associativity == cache->associativity) { 211 return i; 212 } 213 } 214 215 return CACHE_DESCRIPTOR_UNAVAILABLE; 216 } 217 218 /* CPUID Leaf 4 constants: */ 219 220 /* EAX: */ 221 #define CACHE_TYPE_D 1 222 #define CACHE_TYPE_I 2 223 #define CACHE_TYPE_UNIFIED 3 224 225 #define CACHE_LEVEL(l) (l << 5) 226 227 #define CACHE_SELF_INIT_LEVEL (1 << 8) 228 229 /* EDX: */ 230 #define CACHE_NO_INVD_SHARING (1 << 0) 231 #define CACHE_INCLUSIVE (1 << 1) 232 #define CACHE_COMPLEX_IDX (1 << 2) 233 234 /* Encode CacheType for CPUID[4].EAX */ 235 #define CACHE_TYPE(t) (((t) == DATA_CACHE) ? CACHE_TYPE_D : \ 236 ((t) == INSTRUCTION_CACHE) ? CACHE_TYPE_I : \ 237 ((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \ 238 0 /* Invalid value */) 239 240 static uint32_t max_thread_ids_for_cache(X86CPUTopoInfo *topo_info, 241 enum CpuTopologyLevel share_level) 242 { 243 uint32_t num_ids = 0; 244 245 switch (share_level) { 246 case CPU_TOPOLOGY_LEVEL_CORE: 247 num_ids = 1 << apicid_core_offset(topo_info); 248 break; 249 case CPU_TOPOLOGY_LEVEL_DIE: 250 num_ids = 1 << apicid_die_offset(topo_info); 251 break; 252 case CPU_TOPOLOGY_LEVEL_SOCKET: 253 num_ids = 1 << apicid_pkg_offset(topo_info); 254 break; 255 default: 256 /* 257 * Currently there is no use case for THREAD and MODULE, so use 258 * assert directly to facilitate debugging. 259 */ 260 g_assert_not_reached(); 261 } 262 263 return num_ids - 1; 264 } 265 266 static uint32_t max_core_ids_in_package(X86CPUTopoInfo *topo_info) 267 { 268 uint32_t num_cores = 1 << (apicid_pkg_offset(topo_info) - 269 apicid_core_offset(topo_info)); 270 return num_cores - 1; 271 } 272 273 /* Encode cache info for CPUID[4] */ 274 static void encode_cache_cpuid4(CPUCacheInfo *cache, 275 X86CPUTopoInfo *topo_info, 276 uint32_t *eax, uint32_t *ebx, 277 uint32_t *ecx, uint32_t *edx) 278 { 279 assert(cache->size == cache->line_size * cache->associativity * 280 cache->partitions * cache->sets); 281 282 *eax = CACHE_TYPE(cache->type) | 283 CACHE_LEVEL(cache->level) | 284 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) | 285 (max_core_ids_in_package(topo_info) << 26) | 286 (max_thread_ids_for_cache(topo_info, cache->share_level) << 14); 287 288 assert(cache->line_size > 0); 289 assert(cache->partitions > 0); 290 assert(cache->associativity > 0); 291 /* We don't implement fully-associative caches */ 292 assert(cache->associativity < cache->sets); 293 *ebx = (cache->line_size - 1) | 294 ((cache->partitions - 1) << 12) | 295 ((cache->associativity - 1) << 22); 296 297 assert(cache->sets > 0); 298 *ecx = cache->sets - 1; 299 300 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) | 301 (cache->inclusive ? CACHE_INCLUSIVE : 0) | 302 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); 303 } 304 305 static uint32_t num_threads_by_topo_level(X86CPUTopoInfo *topo_info, 306 enum CpuTopologyLevel topo_level) 307 { 308 switch (topo_level) { 309 case CPU_TOPOLOGY_LEVEL_THREAD: 310 return 1; 311 case CPU_TOPOLOGY_LEVEL_CORE: 312 return topo_info->threads_per_core; 313 case CPU_TOPOLOGY_LEVEL_MODULE: 314 return topo_info->threads_per_core * topo_info->cores_per_module; 315 case CPU_TOPOLOGY_LEVEL_DIE: 316 return topo_info->threads_per_core * topo_info->cores_per_module * 317 topo_info->modules_per_die; 318 case CPU_TOPOLOGY_LEVEL_SOCKET: 319 return topo_info->threads_per_core * topo_info->cores_per_module * 320 topo_info->modules_per_die * topo_info->dies_per_pkg; 321 default: 322 g_assert_not_reached(); 323 } 324 return 0; 325 } 326 327 static uint32_t apicid_offset_by_topo_level(X86CPUTopoInfo *topo_info, 328 enum CpuTopologyLevel topo_level) 329 { 330 switch (topo_level) { 331 case CPU_TOPOLOGY_LEVEL_THREAD: 332 return 0; 333 case CPU_TOPOLOGY_LEVEL_CORE: 334 return apicid_core_offset(topo_info); 335 case CPU_TOPOLOGY_LEVEL_MODULE: 336 return apicid_module_offset(topo_info); 337 case CPU_TOPOLOGY_LEVEL_DIE: 338 return apicid_die_offset(topo_info); 339 case CPU_TOPOLOGY_LEVEL_SOCKET: 340 return apicid_pkg_offset(topo_info); 341 default: 342 g_assert_not_reached(); 343 } 344 return 0; 345 } 346 347 static uint32_t cpuid1f_topo_type(enum CpuTopologyLevel topo_level) 348 { 349 switch (topo_level) { 350 case CPU_TOPOLOGY_LEVEL_INVALID: 351 return CPUID_1F_ECX_TOPO_LEVEL_INVALID; 352 case CPU_TOPOLOGY_LEVEL_THREAD: 353 return CPUID_1F_ECX_TOPO_LEVEL_SMT; 354 case CPU_TOPOLOGY_LEVEL_CORE: 355 return CPUID_1F_ECX_TOPO_LEVEL_CORE; 356 case CPU_TOPOLOGY_LEVEL_MODULE: 357 return CPUID_1F_ECX_TOPO_LEVEL_MODULE; 358 case CPU_TOPOLOGY_LEVEL_DIE: 359 return CPUID_1F_ECX_TOPO_LEVEL_DIE; 360 default: 361 /* Other types are not supported in QEMU. */ 362 g_assert_not_reached(); 363 } 364 return 0; 365 } 366 367 static void encode_topo_cpuid1f(CPUX86State *env, uint32_t count, 368 X86CPUTopoInfo *topo_info, 369 uint32_t *eax, uint32_t *ebx, 370 uint32_t *ecx, uint32_t *edx) 371 { 372 X86CPU *cpu = env_archcpu(env); 373 unsigned long level, base_level, next_level; 374 uint32_t num_threads_next_level, offset_next_level; 375 376 assert(count <= CPU_TOPOLOGY_LEVEL_SOCKET); 377 378 /* 379 * Find the No.(count + 1) topology level in avail_cpu_topo bitmap. 380 * The search starts from bit 0 (CPU_TOPOLOGY_LEVEL_THREAD). 381 */ 382 level = CPU_TOPOLOGY_LEVEL_THREAD; 383 base_level = level; 384 for (int i = 0; i <= count; i++) { 385 level = find_next_bit(env->avail_cpu_topo, 386 CPU_TOPOLOGY_LEVEL_SOCKET, 387 base_level); 388 389 /* 390 * CPUID[0x1f] doesn't explicitly encode the package level, 391 * and it just encodes the invalid level (all fields are 0) 392 * into the last subleaf of 0x1f. 393 */ 394 if (level == CPU_TOPOLOGY_LEVEL_SOCKET) { 395 level = CPU_TOPOLOGY_LEVEL_INVALID; 396 break; 397 } 398 /* Search the next level. */ 399 base_level = level + 1; 400 } 401 402 if (level == CPU_TOPOLOGY_LEVEL_INVALID) { 403 num_threads_next_level = 0; 404 offset_next_level = 0; 405 } else { 406 next_level = find_next_bit(env->avail_cpu_topo, 407 CPU_TOPOLOGY_LEVEL_SOCKET, 408 level + 1); 409 num_threads_next_level = num_threads_by_topo_level(topo_info, 410 next_level); 411 offset_next_level = apicid_offset_by_topo_level(topo_info, 412 next_level); 413 } 414 415 *eax = offset_next_level; 416 /* The count (bits 15-00) doesn't need to be reliable. */ 417 *ebx = num_threads_next_level & 0xffff; 418 *ecx = (count & 0xff) | (cpuid1f_topo_type(level) << 8); 419 *edx = cpu->apic_id; 420 421 assert(!(*eax & ~0x1f)); 422 } 423 424 /* Encode cache info for CPUID[0x80000005].ECX or CPUID[0x80000005].EDX */ 425 static uint32_t encode_cache_cpuid80000005(CPUCacheInfo *cache) 426 { 427 assert(cache->size % 1024 == 0); 428 assert(cache->lines_per_tag > 0); 429 assert(cache->associativity > 0); 430 assert(cache->line_size > 0); 431 return ((cache->size / 1024) << 24) | (cache->associativity << 16) | 432 (cache->lines_per_tag << 8) | (cache->line_size); 433 } 434 435 #define ASSOC_FULL 0xFF 436 437 /* AMD associativity encoding used on CPUID Leaf 0x80000006: */ 438 #define AMD_ENC_ASSOC(a) (a <= 1 ? a : \ 439 a == 2 ? 0x2 : \ 440 a == 4 ? 0x4 : \ 441 a == 8 ? 0x6 : \ 442 a == 16 ? 0x8 : \ 443 a == 32 ? 0xA : \ 444 a == 48 ? 0xB : \ 445 a == 64 ? 0xC : \ 446 a == 96 ? 0xD : \ 447 a == 128 ? 0xE : \ 448 a == ASSOC_FULL ? 0xF : \ 449 0 /* invalid value */) 450 451 /* 452 * Encode cache info for CPUID[0x80000006].ECX and CPUID[0x80000006].EDX 453 * @l3 can be NULL. 454 */ 455 static void encode_cache_cpuid80000006(CPUCacheInfo *l2, 456 CPUCacheInfo *l3, 457 uint32_t *ecx, uint32_t *edx) 458 { 459 assert(l2->size % 1024 == 0); 460 assert(l2->associativity > 0); 461 assert(l2->lines_per_tag > 0); 462 assert(l2->line_size > 0); 463 *ecx = ((l2->size / 1024) << 16) | 464 (AMD_ENC_ASSOC(l2->associativity) << 12) | 465 (l2->lines_per_tag << 8) | (l2->line_size); 466 467 if (l3) { 468 assert(l3->size % (512 * 1024) == 0); 469 assert(l3->associativity > 0); 470 assert(l3->lines_per_tag > 0); 471 assert(l3->line_size > 0); 472 *edx = ((l3->size / (512 * 1024)) << 18) | 473 (AMD_ENC_ASSOC(l3->associativity) << 12) | 474 (l3->lines_per_tag << 8) | (l3->line_size); 475 } else { 476 *edx = 0; 477 } 478 } 479 480 /* Encode cache info for CPUID[8000001D] */ 481 static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, 482 X86CPUTopoInfo *topo_info, 483 uint32_t *eax, uint32_t *ebx, 484 uint32_t *ecx, uint32_t *edx) 485 { 486 assert(cache->size == cache->line_size * cache->associativity * 487 cache->partitions * cache->sets); 488 489 *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) | 490 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0); 491 *eax |= max_thread_ids_for_cache(topo_info, cache->share_level) << 14; 492 493 assert(cache->line_size > 0); 494 assert(cache->partitions > 0); 495 assert(cache->associativity > 0); 496 /* We don't implement fully-associative caches */ 497 assert(cache->associativity < cache->sets); 498 *ebx = (cache->line_size - 1) | 499 ((cache->partitions - 1) << 12) | 500 ((cache->associativity - 1) << 22); 501 502 assert(cache->sets > 0); 503 *ecx = cache->sets - 1; 504 505 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) | 506 (cache->inclusive ? CACHE_INCLUSIVE : 0) | 507 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); 508 } 509 510 /* Encode cache info for CPUID[8000001E] */ 511 static void encode_topo_cpuid8000001e(X86CPU *cpu, X86CPUTopoInfo *topo_info, 512 uint32_t *eax, uint32_t *ebx, 513 uint32_t *ecx, uint32_t *edx) 514 { 515 X86CPUTopoIDs topo_ids; 516 517 x86_topo_ids_from_apicid(cpu->apic_id, topo_info, &topo_ids); 518 519 *eax = cpu->apic_id; 520 521 /* 522 * CPUID_Fn8000001E_EBX [Core Identifiers] (CoreId) 523 * Read-only. Reset: 0000_XXXXh. 524 * See Core::X86::Cpuid::ExtApicId. 525 * Core::X86::Cpuid::CoreId_lthree[1:0]_core[3:0]_thread[1:0]; 526 * Bits Description 527 * 31:16 Reserved. 528 * 15:8 ThreadsPerCore: threads per core. Read-only. Reset: XXh. 529 * The number of threads per core is ThreadsPerCore+1. 530 * 7:0 CoreId: core ID. Read-only. Reset: XXh. 531 * 532 * NOTE: CoreId is already part of apic_id. Just use it. We can 533 * use all the 8 bits to represent the core_id here. 534 */ 535 *ebx = ((topo_info->threads_per_core - 1) << 8) | (topo_ids.core_id & 0xFF); 536 537 /* 538 * CPUID_Fn8000001E_ECX [Node Identifiers] (NodeId) 539 * Read-only. Reset: 0000_0XXXh. 540 * Core::X86::Cpuid::NodeId_lthree[1:0]_core[3:0]_thread[1:0]; 541 * Bits Description 542 * 31:11 Reserved. 543 * 10:8 NodesPerProcessor: Node per processor. Read-only. Reset: XXXb. 544 * ValidValues: 545 * Value Description 546 * 0h 1 node per processor. 547 * 7h-1h Reserved. 548 * 7:0 NodeId: Node ID. Read-only. Reset: XXh. 549 * 550 * NOTE: Hardware reserves 3 bits for number of nodes per processor. 551 * But users can create more nodes than the actual hardware can 552 * support. To genaralize we can use all the upper 8 bits for nodes. 553 * NodeId is combination of node and socket_id which is already decoded 554 * in apic_id. Just use it by shifting. 555 */ 556 if (cpu->legacy_multi_node) { 557 *ecx = ((topo_info->dies_per_pkg - 1) << 8) | 558 ((cpu->apic_id >> apicid_die_offset(topo_info)) & 0xFF); 559 } else { 560 *ecx = (cpu->apic_id >> apicid_pkg_offset(topo_info)) & 0xFF; 561 } 562 563 *edx = 0; 564 } 565 566 /* 567 * Definitions of the hardcoded cache entries we expose: 568 * These are legacy cache values. If there is a need to change any 569 * of these values please use builtin_x86_defs 570 */ 571 572 /* L1 data cache: */ 573 static CPUCacheInfo legacy_l1d_cache = { 574 .type = DATA_CACHE, 575 .level = 1, 576 .size = 32 * KiB, 577 .self_init = 1, 578 .line_size = 64, 579 .associativity = 8, 580 .sets = 64, 581 .partitions = 1, 582 .no_invd_sharing = true, 583 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 584 }; 585 586 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ 587 static CPUCacheInfo legacy_l1d_cache_amd = { 588 .type = DATA_CACHE, 589 .level = 1, 590 .size = 64 * KiB, 591 .self_init = 1, 592 .line_size = 64, 593 .associativity = 2, 594 .sets = 512, 595 .partitions = 1, 596 .lines_per_tag = 1, 597 .no_invd_sharing = true, 598 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 599 }; 600 601 /* L1 instruction cache: */ 602 static CPUCacheInfo legacy_l1i_cache = { 603 .type = INSTRUCTION_CACHE, 604 .level = 1, 605 .size = 32 * KiB, 606 .self_init = 1, 607 .line_size = 64, 608 .associativity = 8, 609 .sets = 64, 610 .partitions = 1, 611 .no_invd_sharing = true, 612 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 613 }; 614 615 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ 616 static CPUCacheInfo legacy_l1i_cache_amd = { 617 .type = INSTRUCTION_CACHE, 618 .level = 1, 619 .size = 64 * KiB, 620 .self_init = 1, 621 .line_size = 64, 622 .associativity = 2, 623 .sets = 512, 624 .partitions = 1, 625 .lines_per_tag = 1, 626 .no_invd_sharing = true, 627 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 628 }; 629 630 /* Level 2 unified cache: */ 631 static CPUCacheInfo legacy_l2_cache = { 632 .type = UNIFIED_CACHE, 633 .level = 2, 634 .size = 4 * MiB, 635 .self_init = 1, 636 .line_size = 64, 637 .associativity = 16, 638 .sets = 4096, 639 .partitions = 1, 640 .no_invd_sharing = true, 641 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 642 }; 643 644 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */ 645 static CPUCacheInfo legacy_l2_cache_cpuid2 = { 646 .type = UNIFIED_CACHE, 647 .level = 2, 648 .size = 2 * MiB, 649 .line_size = 64, 650 .associativity = 8, 651 .share_level = CPU_TOPOLOGY_LEVEL_INVALID, 652 }; 653 654 655 /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */ 656 static CPUCacheInfo legacy_l2_cache_amd = { 657 .type = UNIFIED_CACHE, 658 .level = 2, 659 .size = 512 * KiB, 660 .line_size = 64, 661 .lines_per_tag = 1, 662 .associativity = 16, 663 .sets = 512, 664 .partitions = 1, 665 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 666 }; 667 668 /* Level 3 unified cache: */ 669 static CPUCacheInfo legacy_l3_cache = { 670 .type = UNIFIED_CACHE, 671 .level = 3, 672 .size = 16 * MiB, 673 .line_size = 64, 674 .associativity = 16, 675 .sets = 16384, 676 .partitions = 1, 677 .lines_per_tag = 1, 678 .self_init = true, 679 .inclusive = true, 680 .complex_indexing = true, 681 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 682 }; 683 684 /* TLB definitions: */ 685 686 #define L1_DTLB_2M_ASSOC 1 687 #define L1_DTLB_2M_ENTRIES 255 688 #define L1_DTLB_4K_ASSOC 1 689 #define L1_DTLB_4K_ENTRIES 255 690 691 #define L1_ITLB_2M_ASSOC 1 692 #define L1_ITLB_2M_ENTRIES 255 693 #define L1_ITLB_4K_ASSOC 1 694 #define L1_ITLB_4K_ENTRIES 255 695 696 #define L2_DTLB_2M_ASSOC 0 /* disabled */ 697 #define L2_DTLB_2M_ENTRIES 0 /* disabled */ 698 #define L2_DTLB_4K_ASSOC 4 699 #define L2_DTLB_4K_ENTRIES 512 700 701 #define L2_ITLB_2M_ASSOC 0 /* disabled */ 702 #define L2_ITLB_2M_ENTRIES 0 /* disabled */ 703 #define L2_ITLB_4K_ASSOC 4 704 #define L2_ITLB_4K_ENTRIES 512 705 706 /* CPUID Leaf 0x14 constants: */ 707 #define INTEL_PT_MAX_SUBLEAF 0x1 708 /* 709 * bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MATCH 710 * MSR can be accessed; 711 * bit[01]: Support Configurable PSB and Cycle-Accurate Mode; 712 * bit[02]: Support IP Filtering, TraceStop filtering, and preservation 713 * of Intel PT MSRs across warm reset; 714 * bit[03]: Support MTC timing packet and suppression of COFI-based packets; 715 */ 716 #define INTEL_PT_MINIMAL_EBX 0xf 717 /* 718 * bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 and 719 * IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be 720 * accessed; 721 * bit[01]: ToPA tables can hold any number of output entries, up to the 722 * maximum allowed by the MaskOrTableOffset field of 723 * IA32_RTIT_OUTPUT_MASK_PTRS; 724 * bit[02]: Support Single-Range Output scheme; 725 */ 726 #define INTEL_PT_MINIMAL_ECX 0x7 727 /* generated packets which contain IP payloads have LIP values */ 728 #define INTEL_PT_IP_LIP (1 << 31) 729 #define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */ 730 #define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3 731 #define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */ 732 #define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */ 733 #define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */ 734 735 /* CPUID Leaf 0x1D constants: */ 736 #define INTEL_AMX_TILE_MAX_SUBLEAF 0x1 737 #define INTEL_AMX_TOTAL_TILE_BYTES 0x2000 738 #define INTEL_AMX_BYTES_PER_TILE 0x400 739 #define INTEL_AMX_BYTES_PER_ROW 0x40 740 #define INTEL_AMX_TILE_MAX_NAMES 0x8 741 #define INTEL_AMX_TILE_MAX_ROWS 0x10 742 743 /* CPUID Leaf 0x1E constants: */ 744 #define INTEL_AMX_TMUL_MAX_K 0x10 745 #define INTEL_AMX_TMUL_MAX_N 0x40 746 747 void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1, 748 uint32_t vendor2, uint32_t vendor3) 749 { 750 int i; 751 for (i = 0; i < 4; i++) { 752 dst[i] = vendor1 >> (8 * i); 753 dst[i + 4] = vendor2 >> (8 * i); 754 dst[i + 8] = vendor3 >> (8 * i); 755 } 756 dst[CPUID_VENDOR_SZ] = '\0'; 757 } 758 759 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE) 760 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \ 761 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC) 762 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \ 763 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ 764 CPUID_PSE36 | CPUID_FXSR) 765 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE) 766 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \ 767 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \ 768 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \ 769 CPUID_PAE | CPUID_SEP | CPUID_APIC) 770 771 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \ 772 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \ 773 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ 774 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \ 775 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE) 776 /* partly implemented: 777 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */ 778 /* missing: 779 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */ 780 781 /* 782 * Kernel-only features that can be shown to usermode programs even if 783 * they aren't actually supported by TCG, because qemu-user only runs 784 * in CPL=3; remove them if they are ever implemented for system emulation. 785 */ 786 #if defined CONFIG_USER_ONLY 787 #define CPUID_EXT_KERNEL_FEATURES \ 788 (CPUID_EXT_PCID | CPUID_EXT_TSC_DEADLINE_TIMER) 789 #else 790 #define CPUID_EXT_KERNEL_FEATURES 0 791 #endif 792 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \ 793 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \ 794 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \ 795 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \ 796 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR | \ 797 CPUID_EXT_RDRAND | CPUID_EXT_AVX | CPUID_EXT_F16C | \ 798 CPUID_EXT_FMA | CPUID_EXT_X2APIC | CPUID_EXT_KERNEL_FEATURES) 799 /* missing: 800 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX, 801 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, 802 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA, 803 CPUID_EXT_TSC_DEADLINE_TIMER 804 */ 805 806 #ifdef TARGET_X86_64 807 #define TCG_EXT2_X86_64_FEATURES CPUID_EXT2_LM 808 #else 809 #define TCG_EXT2_X86_64_FEATURES 0 810 #endif 811 812 /* 813 * CPUID_*_KERNEL_FEATURES denotes bits and features that are not usable 814 * in usermode or by 32-bit programs. Those are added to supported 815 * TCG features unconditionally in user-mode emulation mode. This may 816 * indeed seem strange or incorrect, but it works because code running 817 * under usermode emulation cannot access them. 818 * 819 * Even for long mode, qemu-i386 is not running "a userspace program on a 820 * 32-bit CPU"; it's running "a userspace program with a 32-bit code segment" 821 * and therefore using the 32-bit ABI; the CPU itself might be 64-bit 822 * but again the difference is only visible in kernel mode. 823 */ 824 #if defined CONFIG_LINUX_USER 825 #define CPUID_EXT2_KERNEL_FEATURES (CPUID_EXT2_LM | CPUID_EXT2_FFXSR) 826 #elif defined CONFIG_USER_ONLY 827 /* FIXME: Long mode not yet supported for i386 bsd-user */ 828 #define CPUID_EXT2_KERNEL_FEATURES CPUID_EXT2_FFXSR 829 #else 830 #define CPUID_EXT2_KERNEL_FEATURES 0 831 #endif 832 833 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \ 834 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \ 835 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \ 836 CPUID_EXT2_SYSCALL | TCG_EXT2_X86_64_FEATURES | \ 837 CPUID_EXT2_KERNEL_FEATURES) 838 839 #if defined CONFIG_USER_ONLY 840 #define CPUID_EXT3_KERNEL_FEATURES CPUID_EXT3_OSVW 841 #else 842 #define CPUID_EXT3_KERNEL_FEATURES 0 843 #endif 844 845 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \ 846 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A | \ 847 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_KERNEL_FEATURES) 848 849 #define TCG_EXT4_FEATURES 0 850 851 #if defined CONFIG_USER_ONLY 852 #define CPUID_SVM_KERNEL_FEATURES (CPUID_SVM_NRIPSAVE | CPUID_SVM_VNMI) 853 #else 854 #define CPUID_SVM_KERNEL_FEATURES 0 855 #endif 856 #define TCG_SVM_FEATURES (CPUID_SVM_NPT | CPUID_SVM_VGIF | \ 857 CPUID_SVM_SVME_ADDR_CHK | CPUID_SVM_KERNEL_FEATURES) 858 859 #define TCG_KVM_FEATURES 0 860 861 #if defined CONFIG_USER_ONLY 862 #define CPUID_7_0_EBX_KERNEL_FEATURES CPUID_7_0_EBX_INVPCID 863 #else 864 #define CPUID_7_0_EBX_KERNEL_FEATURES 0 865 #endif 866 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \ 867 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \ 868 CPUID_7_0_EBX_CLFLUSHOPT | \ 869 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \ 870 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_RDSEED | \ 871 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_KERNEL_FEATURES) 872 /* missing: 873 CPUID_7_0_EBX_HLE 874 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM */ 875 876 #if !defined CONFIG_USER_ONLY || defined CONFIG_LINUX 877 #define TCG_7_0_ECX_RDPID CPUID_7_0_ECX_RDPID 878 #else 879 #define TCG_7_0_ECX_RDPID 0 880 #endif 881 #define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | \ 882 /* CPUID_7_0_ECX_OSPKE is dynamic */ \ 883 CPUID_7_0_ECX_LA57 | CPUID_7_0_ECX_PKS | CPUID_7_0_ECX_VAES | \ 884 TCG_7_0_ECX_RDPID) 885 886 #if defined CONFIG_USER_ONLY 887 #define CPUID_7_0_EDX_KERNEL_FEATURES (CPUID_7_0_EDX_SPEC_CTRL | \ 888 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD) 889 #else 890 #define CPUID_7_0_EDX_KERNEL_FEATURES 0 891 #endif 892 #define TCG_7_0_EDX_FEATURES (CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_KERNEL_FEATURES) 893 894 #define TCG_7_1_EAX_FEATURES (CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | \ 895 CPUID_7_1_EAX_FSRC | CPUID_7_1_EAX_CMPCCXADD) 896 #define TCG_7_1_EDX_FEATURES 0 897 #define TCG_7_2_EDX_FEATURES 0 898 #define TCG_APM_FEATURES 0 899 #define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT 900 #define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1) 901 /* missing: 902 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */ 903 #define TCG_14_0_ECX_FEATURES 0 904 #define TCG_SGX_12_0_EAX_FEATURES 0 905 #define TCG_SGX_12_0_EBX_FEATURES 0 906 #define TCG_SGX_12_1_EAX_FEATURES 0 907 #define TCG_24_0_EBX_FEATURES 0 908 909 #if defined CONFIG_USER_ONLY 910 #define CPUID_8000_0008_EBX_KERNEL_FEATURES (CPUID_8000_0008_EBX_IBPB | \ 911 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | \ 912 CPUID_8000_0008_EBX_STIBP_ALWAYS_ON | CPUID_8000_0008_EBX_AMD_SSBD | \ 913 CPUID_8000_0008_EBX_AMD_PSFD) 914 #else 915 #define CPUID_8000_0008_EBX_KERNEL_FEATURES 0 916 #endif 917 918 #define TCG_8000_0008_EBX (CPUID_8000_0008_EBX_XSAVEERPTR | \ 919 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_KERNEL_FEATURES) 920 921 FeatureWordInfo feature_word_info[FEATURE_WORDS] = { 922 [FEAT_1_EDX] = { 923 .type = CPUID_FEATURE_WORD, 924 .feat_names = { 925 "fpu", "vme", "de", "pse", 926 "tsc", "msr", "pae", "mce", 927 "cx8", "apic", NULL, "sep", 928 "mtrr", "pge", "mca", "cmov", 929 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */, 930 NULL, "ds" /* Intel dts */, "acpi", "mmx", 931 "fxsr", "sse", "sse2", "ss", 932 "ht" /* Intel htt */, "tm", "ia64", "pbe", 933 }, 934 .cpuid = {.eax = 1, .reg = R_EDX, }, 935 .tcg_features = TCG_FEATURES, 936 .no_autoenable_flags = CPUID_HT, 937 }, 938 [FEAT_1_ECX] = { 939 .type = CPUID_FEATURE_WORD, 940 .feat_names = { 941 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor", 942 "ds-cpl", "vmx", "smx", "est", 943 "tm2", "ssse3", "cid", NULL, 944 "fma", "cx16", "xtpr", "pdcm", 945 NULL, "pcid", "dca", "sse4.1", 946 "sse4.2", "x2apic", "movbe", "popcnt", 947 "tsc-deadline", "aes", "xsave", NULL /* osxsave */, 948 "avx", "f16c", "rdrand", "hypervisor", 949 }, 950 .cpuid = { .eax = 1, .reg = R_ECX, }, 951 .tcg_features = TCG_EXT_FEATURES, 952 }, 953 /* Feature names that are already defined on feature_name[] but 954 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their 955 * names on feat_names below. They are copied automatically 956 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD. 957 */ 958 [FEAT_8000_0001_EDX] = { 959 .type = CPUID_FEATURE_WORD, 960 .feat_names = { 961 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */, 962 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */, 963 NULL /* cx8 */, NULL /* apic */, NULL, "syscall", 964 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */, 965 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */, 966 "nx", NULL, "mmxext", NULL /* mmx */, 967 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp", 968 NULL, "lm", "3dnowext", "3dnow", 969 }, 970 .cpuid = { .eax = 0x80000001, .reg = R_EDX, }, 971 .tcg_features = TCG_EXT2_FEATURES, 972 }, 973 [FEAT_8000_0001_ECX] = { 974 .type = CPUID_FEATURE_WORD, 975 .feat_names = { 976 "lahf-lm", "cmp-legacy", "svm", "extapic", 977 "cr8legacy", "abm", "sse4a", "misalignsse", 978 "3dnowprefetch", "osvw", "ibs", "xop", 979 "skinit", "wdt", NULL, "lwp", 980 "fma4", "tce", NULL, "nodeid-msr", 981 NULL, "tbm", "topoext", "perfctr-core", 982 "perfctr-nb", NULL, NULL, NULL, 983 NULL, NULL, NULL, NULL, 984 }, 985 .cpuid = { .eax = 0x80000001, .reg = R_ECX, }, 986 .tcg_features = TCG_EXT3_FEATURES, 987 /* 988 * TOPOEXT is always allowed but can't be enabled blindly by 989 * "-cpu host", as it requires consistent cache topology info 990 * to be provided so it doesn't confuse guests. 991 */ 992 .no_autoenable_flags = CPUID_EXT3_TOPOEXT, 993 }, 994 [FEAT_C000_0001_EDX] = { 995 .type = CPUID_FEATURE_WORD, 996 .feat_names = { 997 NULL, NULL, "xstore", "xstore-en", 998 NULL, NULL, "xcrypt", "xcrypt-en", 999 "ace2", "ace2-en", "phe", "phe-en", 1000 "pmm", "pmm-en", NULL, NULL, 1001 NULL, NULL, NULL, NULL, 1002 NULL, NULL, NULL, NULL, 1003 NULL, NULL, NULL, NULL, 1004 NULL, NULL, NULL, NULL, 1005 }, 1006 .cpuid = { .eax = 0xC0000001, .reg = R_EDX, }, 1007 .tcg_features = TCG_EXT4_FEATURES, 1008 }, 1009 [FEAT_KVM] = { 1010 .type = CPUID_FEATURE_WORD, 1011 .feat_names = { 1012 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock", 1013 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt", 1014 NULL, "kvm-pv-tlb-flush", "kvm-asyncpf-vmexit", "kvm-pv-ipi", 1015 "kvm-poll-control", "kvm-pv-sched-yield", "kvm-asyncpf-int", "kvm-msi-ext-dest-id", 1016 NULL, NULL, NULL, NULL, 1017 NULL, NULL, NULL, NULL, 1018 "kvmclock-stable-bit", NULL, NULL, NULL, 1019 NULL, NULL, NULL, NULL, 1020 }, 1021 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EAX, }, 1022 .tcg_features = TCG_KVM_FEATURES, 1023 }, 1024 [FEAT_KVM_HINTS] = { 1025 .type = CPUID_FEATURE_WORD, 1026 .feat_names = { 1027 "kvm-hint-dedicated", NULL, NULL, NULL, 1028 NULL, NULL, NULL, NULL, 1029 NULL, NULL, NULL, NULL, 1030 NULL, NULL, NULL, NULL, 1031 NULL, NULL, NULL, NULL, 1032 NULL, NULL, NULL, NULL, 1033 NULL, NULL, NULL, NULL, 1034 NULL, NULL, NULL, NULL, 1035 }, 1036 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EDX, }, 1037 .tcg_features = TCG_KVM_FEATURES, 1038 /* 1039 * KVM hints aren't auto-enabled by -cpu host, they need to be 1040 * explicitly enabled in the command-line. 1041 */ 1042 .no_autoenable_flags = ~0U, 1043 }, 1044 [FEAT_SVM] = { 1045 .type = CPUID_FEATURE_WORD, 1046 .feat_names = { 1047 "npt", "lbrv", "svm-lock", "nrip-save", 1048 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists", 1049 NULL, NULL, "pause-filter", NULL, 1050 "pfthreshold", "avic", NULL, "v-vmsave-vmload", 1051 "vgif", NULL, NULL, NULL, 1052 NULL, NULL, NULL, NULL, 1053 NULL, "vnmi", NULL, NULL, 1054 "svme-addr-chk", NULL, NULL, NULL, 1055 }, 1056 .cpuid = { .eax = 0x8000000A, .reg = R_EDX, }, 1057 .tcg_features = TCG_SVM_FEATURES, 1058 }, 1059 [FEAT_7_0_EBX] = { 1060 .type = CPUID_FEATURE_WORD, 1061 .feat_names = { 1062 "fsgsbase", "tsc-adjust", "sgx", "bmi1", 1063 "hle", "avx2", "fdp-excptn-only", "smep", 1064 "bmi2", "erms", "invpcid", "rtm", 1065 NULL, "zero-fcs-fds", "mpx", NULL, 1066 "avx512f", "avx512dq", "rdseed", "adx", 1067 "smap", "avx512ifma", "pcommit", "clflushopt", 1068 "clwb", "intel-pt", "avx512pf", "avx512er", 1069 "avx512cd", "sha-ni", "avx512bw", "avx512vl", 1070 }, 1071 .cpuid = { 1072 .eax = 7, 1073 .needs_ecx = true, .ecx = 0, 1074 .reg = R_EBX, 1075 }, 1076 .tcg_features = TCG_7_0_EBX_FEATURES, 1077 }, 1078 [FEAT_7_0_ECX] = { 1079 .type = CPUID_FEATURE_WORD, 1080 .feat_names = { 1081 NULL, "avx512vbmi", "umip", "pku", 1082 NULL /* ospke */, "waitpkg", "avx512vbmi2", NULL, 1083 "gfni", "vaes", "vpclmulqdq", "avx512vnni", 1084 "avx512bitalg", NULL, "avx512-vpopcntdq", NULL, 1085 "la57", NULL, NULL, NULL, 1086 NULL, NULL, "rdpid", NULL, 1087 "bus-lock-detect", "cldemote", NULL, "movdiri", 1088 "movdir64b", NULL, "sgxlc", "pks", 1089 }, 1090 .cpuid = { 1091 .eax = 7, 1092 .needs_ecx = true, .ecx = 0, 1093 .reg = R_ECX, 1094 }, 1095 .tcg_features = TCG_7_0_ECX_FEATURES, 1096 }, 1097 [FEAT_7_0_EDX] = { 1098 .type = CPUID_FEATURE_WORD, 1099 .feat_names = { 1100 NULL, NULL, "avx512-4vnniw", "avx512-4fmaps", 1101 "fsrm", NULL, NULL, NULL, 1102 "avx512-vp2intersect", NULL, "md-clear", NULL, 1103 NULL, NULL, "serialize", NULL, 1104 "tsx-ldtrk", NULL, NULL /* pconfig */, "arch-lbr", 1105 NULL, NULL, "amx-bf16", "avx512-fp16", 1106 "amx-tile", "amx-int8", "spec-ctrl", "stibp", 1107 "flush-l1d", "arch-capabilities", "core-capability", "ssbd", 1108 }, 1109 .cpuid = { 1110 .eax = 7, 1111 .needs_ecx = true, .ecx = 0, 1112 .reg = R_EDX, 1113 }, 1114 .tcg_features = TCG_7_0_EDX_FEATURES, 1115 }, 1116 [FEAT_7_1_EAX] = { 1117 .type = CPUID_FEATURE_WORD, 1118 .feat_names = { 1119 "sha512", "sm3", "sm4", NULL, 1120 "avx-vnni", "avx512-bf16", NULL, "cmpccxadd", 1121 NULL, NULL, "fzrm", "fsrs", 1122 "fsrc", NULL, NULL, NULL, 1123 NULL, "fred", "lkgs", "wrmsrns", 1124 NULL, "amx-fp16", NULL, "avx-ifma", 1125 NULL, NULL, "lam", NULL, 1126 NULL, NULL, NULL, NULL, 1127 }, 1128 .cpuid = { 1129 .eax = 7, 1130 .needs_ecx = true, .ecx = 1, 1131 .reg = R_EAX, 1132 }, 1133 .tcg_features = TCG_7_1_EAX_FEATURES, 1134 }, 1135 [FEAT_7_1_EDX] = { 1136 .type = CPUID_FEATURE_WORD, 1137 .feat_names = { 1138 NULL, NULL, NULL, NULL, 1139 "avx-vnni-int8", "avx-ne-convert", NULL, NULL, 1140 "amx-complex", NULL, "avx-vnni-int16", NULL, 1141 NULL, NULL, "prefetchiti", NULL, 1142 NULL, NULL, NULL, "avx10", 1143 NULL, NULL, NULL, NULL, 1144 NULL, NULL, NULL, NULL, 1145 NULL, NULL, NULL, NULL, 1146 }, 1147 .cpuid = { 1148 .eax = 7, 1149 .needs_ecx = true, .ecx = 1, 1150 .reg = R_EDX, 1151 }, 1152 .tcg_features = TCG_7_1_EDX_FEATURES, 1153 }, 1154 [FEAT_7_2_EDX] = { 1155 .type = CPUID_FEATURE_WORD, 1156 .feat_names = { 1157 "intel-psfd", "ipred-ctrl", "rrsba-ctrl", "ddpd-u", 1158 "bhi-ctrl", "mcdt-no", NULL, NULL, 1159 NULL, NULL, NULL, NULL, 1160 NULL, NULL, NULL, NULL, 1161 NULL, NULL, NULL, NULL, 1162 NULL, NULL, NULL, NULL, 1163 NULL, NULL, NULL, NULL, 1164 NULL, NULL, NULL, NULL, 1165 }, 1166 .cpuid = { 1167 .eax = 7, 1168 .needs_ecx = true, .ecx = 2, 1169 .reg = R_EDX, 1170 }, 1171 .tcg_features = TCG_7_2_EDX_FEATURES, 1172 }, 1173 [FEAT_24_0_EBX] = { 1174 .type = CPUID_FEATURE_WORD, 1175 .feat_names = { 1176 [16] = "avx10-128", 1177 [17] = "avx10-256", 1178 [18] = "avx10-512", 1179 }, 1180 .cpuid = { 1181 .eax = 0x24, 1182 .needs_ecx = true, .ecx = 0, 1183 .reg = R_EBX, 1184 }, 1185 .tcg_features = TCG_24_0_EBX_FEATURES, 1186 }, 1187 [FEAT_8000_0007_EDX] = { 1188 .type = CPUID_FEATURE_WORD, 1189 .feat_names = { 1190 NULL, NULL, NULL, NULL, 1191 NULL, NULL, NULL, NULL, 1192 "invtsc", NULL, NULL, NULL, 1193 NULL, NULL, NULL, NULL, 1194 NULL, NULL, NULL, NULL, 1195 NULL, NULL, NULL, NULL, 1196 NULL, NULL, NULL, NULL, 1197 NULL, NULL, NULL, NULL, 1198 }, 1199 .cpuid = { .eax = 0x80000007, .reg = R_EDX, }, 1200 .tcg_features = TCG_APM_FEATURES, 1201 .unmigratable_flags = CPUID_APM_INVTSC, 1202 }, 1203 [FEAT_8000_0007_EBX] = { 1204 .type = CPUID_FEATURE_WORD, 1205 .feat_names = { 1206 "overflow-recov", "succor", NULL, NULL, 1207 NULL, NULL, NULL, NULL, 1208 NULL, NULL, NULL, NULL, 1209 NULL, NULL, NULL, NULL, 1210 NULL, NULL, NULL, NULL, 1211 NULL, NULL, NULL, NULL, 1212 NULL, NULL, NULL, NULL, 1213 NULL, NULL, NULL, NULL, 1214 }, 1215 .cpuid = { .eax = 0x80000007, .reg = R_EBX, }, 1216 .tcg_features = 0, 1217 .unmigratable_flags = 0, 1218 }, 1219 [FEAT_8000_0008_EBX] = { 1220 .type = CPUID_FEATURE_WORD, 1221 .feat_names = { 1222 "clzero", NULL, "xsaveerptr", NULL, 1223 NULL, NULL, NULL, NULL, 1224 NULL, "wbnoinvd", NULL, NULL, 1225 "ibpb", NULL, "ibrs", "amd-stibp", 1226 NULL, "stibp-always-on", NULL, NULL, 1227 NULL, NULL, NULL, NULL, 1228 "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL, 1229 "amd-psfd", NULL, NULL, NULL, 1230 }, 1231 .cpuid = { .eax = 0x80000008, .reg = R_EBX, }, 1232 .tcg_features = TCG_8000_0008_EBX, 1233 .unmigratable_flags = 0, 1234 }, 1235 [FEAT_8000_0021_EAX] = { 1236 .type = CPUID_FEATURE_WORD, 1237 .feat_names = { 1238 "no-nested-data-bp", NULL, "lfence-always-serializing", NULL, 1239 NULL, NULL, "null-sel-clr-base", NULL, 1240 "auto-ibrs", NULL, NULL, NULL, 1241 NULL, NULL, NULL, NULL, 1242 NULL, NULL, NULL, NULL, 1243 NULL, NULL, NULL, NULL, 1244 "eraps", NULL, NULL, "sbpb", 1245 "ibpb-brtype", "srso-no", "srso-user-kernel-no", NULL, 1246 }, 1247 .cpuid = { .eax = 0x80000021, .reg = R_EAX, }, 1248 .tcg_features = 0, 1249 .unmigratable_flags = 0, 1250 }, 1251 [FEAT_8000_0021_EBX] = { 1252 .type = CPUID_FEATURE_WORD, 1253 .cpuid = { .eax = 0x80000021, .reg = R_EBX, }, 1254 .tcg_features = 0, 1255 .unmigratable_flags = 0, 1256 }, 1257 [FEAT_8000_0022_EAX] = { 1258 .type = CPUID_FEATURE_WORD, 1259 .feat_names = { 1260 "perfmon-v2", NULL, NULL, NULL, 1261 NULL, NULL, NULL, NULL, 1262 NULL, NULL, NULL, NULL, 1263 NULL, NULL, NULL, NULL, 1264 NULL, NULL, NULL, NULL, 1265 NULL, NULL, NULL, NULL, 1266 NULL, NULL, NULL, NULL, 1267 NULL, NULL, NULL, NULL, 1268 }, 1269 .cpuid = { .eax = 0x80000022, .reg = R_EAX, }, 1270 .tcg_features = 0, 1271 .unmigratable_flags = 0, 1272 }, 1273 [FEAT_XSAVE] = { 1274 .type = CPUID_FEATURE_WORD, 1275 .feat_names = { 1276 "xsaveopt", "xsavec", "xgetbv1", "xsaves", 1277 "xfd", NULL, NULL, NULL, 1278 NULL, NULL, NULL, NULL, 1279 NULL, NULL, NULL, NULL, 1280 NULL, NULL, NULL, NULL, 1281 NULL, NULL, NULL, NULL, 1282 NULL, NULL, NULL, NULL, 1283 NULL, NULL, NULL, NULL, 1284 }, 1285 .cpuid = { 1286 .eax = 0xd, 1287 .needs_ecx = true, .ecx = 1, 1288 .reg = R_EAX, 1289 }, 1290 .tcg_features = TCG_XSAVE_FEATURES, 1291 }, 1292 [FEAT_XSAVE_XSS_LO] = { 1293 .type = CPUID_FEATURE_WORD, 1294 .feat_names = { 1295 NULL, NULL, NULL, NULL, 1296 NULL, NULL, NULL, NULL, 1297 NULL, NULL, NULL, NULL, 1298 NULL, NULL, NULL, NULL, 1299 NULL, NULL, NULL, NULL, 1300 NULL, NULL, NULL, NULL, 1301 NULL, NULL, NULL, NULL, 1302 NULL, NULL, NULL, NULL, 1303 }, 1304 .cpuid = { 1305 .eax = 0xD, 1306 .needs_ecx = true, 1307 .ecx = 1, 1308 .reg = R_ECX, 1309 }, 1310 }, 1311 [FEAT_XSAVE_XSS_HI] = { 1312 .type = CPUID_FEATURE_WORD, 1313 .cpuid = { 1314 .eax = 0xD, 1315 .needs_ecx = true, 1316 .ecx = 1, 1317 .reg = R_EDX 1318 }, 1319 }, 1320 [FEAT_6_EAX] = { 1321 .type = CPUID_FEATURE_WORD, 1322 .feat_names = { 1323 NULL, NULL, "arat", NULL, 1324 NULL, NULL, NULL, NULL, 1325 NULL, NULL, NULL, NULL, 1326 NULL, NULL, NULL, NULL, 1327 NULL, NULL, NULL, NULL, 1328 NULL, NULL, NULL, NULL, 1329 NULL, NULL, NULL, NULL, 1330 NULL, NULL, NULL, NULL, 1331 }, 1332 .cpuid = { .eax = 6, .reg = R_EAX, }, 1333 .tcg_features = TCG_6_EAX_FEATURES, 1334 }, 1335 [FEAT_XSAVE_XCR0_LO] = { 1336 .type = CPUID_FEATURE_WORD, 1337 .cpuid = { 1338 .eax = 0xD, 1339 .needs_ecx = true, .ecx = 0, 1340 .reg = R_EAX, 1341 }, 1342 .tcg_features = XSTATE_FP_MASK | XSTATE_SSE_MASK | 1343 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK | 1344 XSTATE_PKRU_MASK, 1345 .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK | 1346 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK | 1347 XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK | 1348 XSTATE_PKRU_MASK, 1349 }, 1350 [FEAT_XSAVE_XCR0_HI] = { 1351 .type = CPUID_FEATURE_WORD, 1352 .cpuid = { 1353 .eax = 0xD, 1354 .needs_ecx = true, .ecx = 0, 1355 .reg = R_EDX, 1356 }, 1357 .tcg_features = 0U, 1358 }, 1359 /*Below are MSR exposed features*/ 1360 [FEAT_ARCH_CAPABILITIES] = { 1361 .type = MSR_FEATURE_WORD, 1362 .feat_names = { 1363 "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry", 1364 "ssb-no", "mds-no", "pschange-mc-no", "tsx-ctrl", 1365 "taa-no", NULL, NULL, NULL, 1366 NULL, "sbdr-ssdp-no", "fbsdp-no", "psdp-no", 1367 NULL, "fb-clear", NULL, NULL, 1368 NULL, NULL, NULL, NULL, 1369 "pbrsb-no", NULL, "gds-no", "rfds-no", 1370 "rfds-clear", NULL, NULL, NULL, 1371 }, 1372 .msr = { 1373 .index = MSR_IA32_ARCH_CAPABILITIES, 1374 }, 1375 /* 1376 * FEAT_ARCH_CAPABILITIES only affects a read-only MSR, which 1377 * cannot be read from user mode. Therefore, it has no impact 1378 > on any user-mode operation, and warnings about unsupported 1379 * features do not matter. 1380 */ 1381 .tcg_features = ~0U, 1382 }, 1383 [FEAT_CORE_CAPABILITY] = { 1384 .type = MSR_FEATURE_WORD, 1385 .feat_names = { 1386 NULL, NULL, NULL, NULL, 1387 NULL, "split-lock-detect", NULL, NULL, 1388 NULL, NULL, NULL, NULL, 1389 NULL, NULL, NULL, NULL, 1390 NULL, NULL, NULL, NULL, 1391 NULL, NULL, NULL, NULL, 1392 NULL, NULL, NULL, NULL, 1393 NULL, NULL, NULL, NULL, 1394 }, 1395 .msr = { 1396 .index = MSR_IA32_CORE_CAPABILITY, 1397 }, 1398 }, 1399 [FEAT_PERF_CAPABILITIES] = { 1400 .type = MSR_FEATURE_WORD, 1401 .feat_names = { 1402 NULL, NULL, NULL, NULL, 1403 NULL, NULL, NULL, NULL, 1404 NULL, NULL, NULL, NULL, 1405 NULL, "full-width-write", NULL, NULL, 1406 NULL, NULL, NULL, NULL, 1407 NULL, NULL, NULL, NULL, 1408 NULL, NULL, NULL, NULL, 1409 NULL, NULL, NULL, NULL, 1410 }, 1411 .msr = { 1412 .index = MSR_IA32_PERF_CAPABILITIES, 1413 }, 1414 }, 1415 1416 [FEAT_VMX_PROCBASED_CTLS] = { 1417 .type = MSR_FEATURE_WORD, 1418 .feat_names = { 1419 NULL, NULL, "vmx-vintr-pending", "vmx-tsc-offset", 1420 NULL, NULL, NULL, "vmx-hlt-exit", 1421 NULL, "vmx-invlpg-exit", "vmx-mwait-exit", "vmx-rdpmc-exit", 1422 "vmx-rdtsc-exit", NULL, NULL, "vmx-cr3-load-noexit", 1423 "vmx-cr3-store-noexit", NULL, NULL, "vmx-cr8-load-exit", 1424 "vmx-cr8-store-exit", "vmx-flexpriority", "vmx-vnmi-pending", "vmx-movdr-exit", 1425 "vmx-io-exit", "vmx-io-bitmap", NULL, "vmx-mtf", 1426 "vmx-msr-bitmap", "vmx-monitor-exit", "vmx-pause-exit", "vmx-secondary-ctls", 1427 }, 1428 .msr = { 1429 .index = MSR_IA32_VMX_TRUE_PROCBASED_CTLS, 1430 } 1431 }, 1432 1433 [FEAT_VMX_SECONDARY_CTLS] = { 1434 .type = MSR_FEATURE_WORD, 1435 .feat_names = { 1436 "vmx-apicv-xapic", "vmx-ept", "vmx-desc-exit", "vmx-rdtscp-exit", 1437 "vmx-apicv-x2apic", "vmx-vpid", "vmx-wbinvd-exit", "vmx-unrestricted-guest", 1438 "vmx-apicv-register", "vmx-apicv-vid", "vmx-ple", "vmx-rdrand-exit", 1439 "vmx-invpcid-exit", "vmx-vmfunc", "vmx-shadow-vmcs", "vmx-encls-exit", 1440 "vmx-rdseed-exit", "vmx-pml", NULL, NULL, 1441 "vmx-xsaves", NULL, NULL, NULL, 1442 NULL, "vmx-tsc-scaling", "vmx-enable-user-wait-pause", NULL, 1443 NULL, NULL, NULL, NULL, 1444 }, 1445 .msr = { 1446 .index = MSR_IA32_VMX_PROCBASED_CTLS2, 1447 } 1448 }, 1449 1450 [FEAT_VMX_PINBASED_CTLS] = { 1451 .type = MSR_FEATURE_WORD, 1452 .feat_names = { 1453 "vmx-intr-exit", NULL, NULL, "vmx-nmi-exit", 1454 NULL, "vmx-vnmi", "vmx-preemption-timer", "vmx-posted-intr", 1455 NULL, NULL, NULL, NULL, 1456 NULL, NULL, NULL, NULL, 1457 NULL, NULL, NULL, NULL, 1458 NULL, NULL, NULL, NULL, 1459 NULL, NULL, NULL, NULL, 1460 NULL, NULL, NULL, NULL, 1461 }, 1462 .msr = { 1463 .index = MSR_IA32_VMX_TRUE_PINBASED_CTLS, 1464 } 1465 }, 1466 1467 [FEAT_VMX_EXIT_CTLS] = { 1468 .type = MSR_FEATURE_WORD, 1469 /* 1470 * VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE is copied from 1471 * the LM CPUID bit. 1472 */ 1473 .feat_names = { 1474 NULL, NULL, "vmx-exit-nosave-debugctl", NULL, 1475 NULL, NULL, NULL, NULL, 1476 NULL, NULL /* vmx-exit-host-addr-space-size */, NULL, NULL, 1477 "vmx-exit-load-perf-global-ctrl", NULL, NULL, "vmx-exit-ack-intr", 1478 NULL, NULL, "vmx-exit-save-pat", "vmx-exit-load-pat", 1479 "vmx-exit-save-efer", "vmx-exit-load-efer", 1480 "vmx-exit-save-preemption-timer", "vmx-exit-clear-bndcfgs", 1481 NULL, "vmx-exit-clear-rtit-ctl", NULL, NULL, 1482 NULL, "vmx-exit-load-pkrs", NULL, "vmx-exit-secondary-ctls", 1483 }, 1484 .msr = { 1485 .index = MSR_IA32_VMX_TRUE_EXIT_CTLS, 1486 } 1487 }, 1488 1489 [FEAT_VMX_ENTRY_CTLS] = { 1490 .type = MSR_FEATURE_WORD, 1491 .feat_names = { 1492 NULL, NULL, "vmx-entry-noload-debugctl", NULL, 1493 NULL, NULL, NULL, NULL, 1494 NULL, "vmx-entry-ia32e-mode", NULL, NULL, 1495 NULL, "vmx-entry-load-perf-global-ctrl", "vmx-entry-load-pat", "vmx-entry-load-efer", 1496 "vmx-entry-load-bndcfgs", NULL, "vmx-entry-load-rtit-ctl", NULL, 1497 NULL, NULL, "vmx-entry-load-pkrs", "vmx-entry-load-fred", 1498 NULL, NULL, NULL, NULL, 1499 NULL, NULL, NULL, NULL, 1500 }, 1501 .msr = { 1502 .index = MSR_IA32_VMX_TRUE_ENTRY_CTLS, 1503 } 1504 }, 1505 1506 [FEAT_VMX_MISC] = { 1507 .type = MSR_FEATURE_WORD, 1508 .feat_names = { 1509 NULL, NULL, NULL, NULL, 1510 NULL, "vmx-store-lma", "vmx-activity-hlt", "vmx-activity-shutdown", 1511 "vmx-activity-wait-sipi", NULL, NULL, NULL, 1512 NULL, NULL, NULL, NULL, 1513 NULL, NULL, NULL, NULL, 1514 NULL, NULL, NULL, NULL, 1515 NULL, NULL, NULL, NULL, 1516 NULL, "vmx-vmwrite-vmexit-fields", "vmx-zero-len-inject", NULL, 1517 }, 1518 .msr = { 1519 .index = MSR_IA32_VMX_MISC, 1520 } 1521 }, 1522 1523 [FEAT_VMX_EPT_VPID_CAPS] = { 1524 .type = MSR_FEATURE_WORD, 1525 .feat_names = { 1526 "vmx-ept-execonly", NULL, NULL, NULL, 1527 NULL, NULL, "vmx-page-walk-4", "vmx-page-walk-5", 1528 NULL, NULL, NULL, NULL, 1529 NULL, NULL, NULL, NULL, 1530 "vmx-ept-2mb", "vmx-ept-1gb", NULL, NULL, 1531 "vmx-invept", "vmx-eptad", "vmx-ept-advanced-exitinfo", NULL, 1532 NULL, "vmx-invept-single-context", "vmx-invept-all-context", NULL, 1533 NULL, NULL, NULL, NULL, 1534 "vmx-invvpid", NULL, NULL, NULL, 1535 NULL, NULL, NULL, NULL, 1536 "vmx-invvpid-single-addr", "vmx-invept-single-context", 1537 "vmx-invvpid-all-context", "vmx-invept-single-context-noglobals", 1538 NULL, NULL, NULL, NULL, 1539 NULL, NULL, NULL, NULL, 1540 NULL, NULL, NULL, NULL, 1541 NULL, NULL, NULL, NULL, 1542 NULL, NULL, NULL, NULL, 1543 }, 1544 .msr = { 1545 .index = MSR_IA32_VMX_EPT_VPID_CAP, 1546 } 1547 }, 1548 1549 [FEAT_VMX_BASIC] = { 1550 .type = MSR_FEATURE_WORD, 1551 .feat_names = { 1552 [54] = "vmx-ins-outs", 1553 [55] = "vmx-true-ctls", 1554 [56] = "vmx-any-errcode", 1555 [58] = "vmx-nested-exception", 1556 }, 1557 .msr = { 1558 .index = MSR_IA32_VMX_BASIC, 1559 }, 1560 /* Just to be safe - we don't support setting the MSEG version field. */ 1561 .no_autoenable_flags = MSR_VMX_BASIC_DUAL_MONITOR, 1562 }, 1563 1564 [FEAT_VMX_VMFUNC] = { 1565 .type = MSR_FEATURE_WORD, 1566 .feat_names = { 1567 [0] = "vmx-eptp-switching", 1568 }, 1569 .msr = { 1570 .index = MSR_IA32_VMX_VMFUNC, 1571 } 1572 }, 1573 1574 [FEAT_14_0_ECX] = { 1575 .type = CPUID_FEATURE_WORD, 1576 .feat_names = { 1577 NULL, NULL, NULL, NULL, 1578 NULL, NULL, NULL, NULL, 1579 NULL, NULL, NULL, NULL, 1580 NULL, NULL, NULL, NULL, 1581 NULL, NULL, NULL, NULL, 1582 NULL, NULL, NULL, NULL, 1583 NULL, NULL, NULL, NULL, 1584 NULL, NULL, NULL, "intel-pt-lip", 1585 }, 1586 .cpuid = { 1587 .eax = 0x14, 1588 .needs_ecx = true, .ecx = 0, 1589 .reg = R_ECX, 1590 }, 1591 .tcg_features = TCG_14_0_ECX_FEATURES, 1592 }, 1593 1594 [FEAT_SGX_12_0_EAX] = { 1595 .type = CPUID_FEATURE_WORD, 1596 .feat_names = { 1597 "sgx1", "sgx2", NULL, NULL, 1598 NULL, NULL, NULL, NULL, 1599 NULL, NULL, NULL, "sgx-edeccssa", 1600 NULL, NULL, NULL, NULL, 1601 NULL, NULL, NULL, NULL, 1602 NULL, NULL, NULL, NULL, 1603 NULL, NULL, NULL, NULL, 1604 NULL, NULL, NULL, NULL, 1605 }, 1606 .cpuid = { 1607 .eax = 0x12, 1608 .needs_ecx = true, .ecx = 0, 1609 .reg = R_EAX, 1610 }, 1611 .tcg_features = TCG_SGX_12_0_EAX_FEATURES, 1612 }, 1613 1614 [FEAT_SGX_12_0_EBX] = { 1615 .type = CPUID_FEATURE_WORD, 1616 .feat_names = { 1617 "sgx-exinfo" , NULL, NULL, NULL, 1618 NULL, NULL, NULL, NULL, 1619 NULL, NULL, NULL, NULL, 1620 NULL, NULL, NULL, NULL, 1621 NULL, NULL, NULL, NULL, 1622 NULL, NULL, NULL, NULL, 1623 NULL, NULL, NULL, NULL, 1624 NULL, NULL, NULL, NULL, 1625 }, 1626 .cpuid = { 1627 .eax = 0x12, 1628 .needs_ecx = true, .ecx = 0, 1629 .reg = R_EBX, 1630 }, 1631 .tcg_features = TCG_SGX_12_0_EBX_FEATURES, 1632 }, 1633 1634 [FEAT_SGX_12_1_EAX] = { 1635 .type = CPUID_FEATURE_WORD, 1636 .feat_names = { 1637 NULL, "sgx-debug", "sgx-mode64", NULL, 1638 "sgx-provisionkey", "sgx-tokenkey", NULL, "sgx-kss", 1639 NULL, NULL, "sgx-aex-notify", NULL, 1640 NULL, NULL, NULL, NULL, 1641 NULL, NULL, NULL, NULL, 1642 NULL, NULL, NULL, NULL, 1643 NULL, NULL, NULL, NULL, 1644 NULL, NULL, NULL, NULL, 1645 }, 1646 .cpuid = { 1647 .eax = 0x12, 1648 .needs_ecx = true, .ecx = 1, 1649 .reg = R_EAX, 1650 }, 1651 .tcg_features = TCG_SGX_12_1_EAX_FEATURES, 1652 }, 1653 }; 1654 1655 typedef struct FeatureMask { 1656 FeatureWord index; 1657 uint64_t mask; 1658 } FeatureMask; 1659 1660 typedef struct FeatureDep { 1661 FeatureMask from, to; 1662 } FeatureDep; 1663 1664 static FeatureDep feature_dependencies[] = { 1665 { 1666 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_ARCH_CAPABILITIES }, 1667 .to = { FEAT_ARCH_CAPABILITIES, ~0ull }, 1668 }, 1669 { 1670 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_CORE_CAPABILITY }, 1671 .to = { FEAT_CORE_CAPABILITY, ~0ull }, 1672 }, 1673 { 1674 .from = { FEAT_1_ECX, CPUID_EXT_PDCM }, 1675 .to = { FEAT_PERF_CAPABILITIES, ~0ull }, 1676 }, 1677 { 1678 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1679 .to = { FEAT_VMX_PROCBASED_CTLS, ~0ull }, 1680 }, 1681 { 1682 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1683 .to = { FEAT_VMX_PINBASED_CTLS, ~0ull }, 1684 }, 1685 { 1686 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1687 .to = { FEAT_VMX_EXIT_CTLS, ~0ull }, 1688 }, 1689 { 1690 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1691 .to = { FEAT_VMX_ENTRY_CTLS, ~0ull }, 1692 }, 1693 { 1694 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1695 .to = { FEAT_VMX_MISC, ~0ull }, 1696 }, 1697 { 1698 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1699 .to = { FEAT_VMX_BASIC, ~0ull }, 1700 }, 1701 { 1702 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_LM }, 1703 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_IA32E_MODE }, 1704 }, 1705 { 1706 .from = { FEAT_VMX_PROCBASED_CTLS, VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS }, 1707 .to = { FEAT_VMX_SECONDARY_CTLS, ~0ull }, 1708 }, 1709 { 1710 .from = { FEAT_XSAVE, CPUID_XSAVE_XSAVES }, 1711 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_XSAVES }, 1712 }, 1713 { 1714 .from = { FEAT_1_ECX, CPUID_EXT_RDRAND }, 1715 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDRAND_EXITING }, 1716 }, 1717 { 1718 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INVPCID }, 1719 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_INVPCID }, 1720 }, 1721 { 1722 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_MPX }, 1723 .to = { FEAT_VMX_EXIT_CTLS, VMX_VM_EXIT_CLEAR_BNDCFGS }, 1724 }, 1725 { 1726 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_MPX }, 1727 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_LOAD_BNDCFGS }, 1728 }, 1729 { 1730 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_RDSEED }, 1731 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDSEED_EXITING }, 1732 }, 1733 { 1734 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT }, 1735 .to = { FEAT_14_0_ECX, ~0ull }, 1736 }, 1737 { 1738 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_RDTSCP }, 1739 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDTSCP }, 1740 }, 1741 { 1742 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT }, 1743 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull }, 1744 }, 1745 { 1746 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT }, 1747 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST }, 1748 }, 1749 { 1750 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VPID }, 1751 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull << 32 }, 1752 }, 1753 { 1754 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VMFUNC }, 1755 .to = { FEAT_VMX_VMFUNC, ~0ull }, 1756 }, 1757 { 1758 .from = { FEAT_8000_0001_ECX, CPUID_EXT3_SVM }, 1759 .to = { FEAT_SVM, ~0ull }, 1760 }, 1761 { 1762 .from = { FEAT_7_0_ECX, CPUID_7_0_ECX_WAITPKG }, 1763 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_USER_WAIT_PAUSE }, 1764 }, 1765 { 1766 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_LM }, 1767 .to = { FEAT_7_1_EAX, CPUID_7_1_EAX_FRED }, 1768 }, 1769 { 1770 .from = { FEAT_7_1_EAX, CPUID_7_1_EAX_LKGS }, 1771 .to = { FEAT_7_1_EAX, CPUID_7_1_EAX_FRED }, 1772 }, 1773 { 1774 .from = { FEAT_7_1_EAX, CPUID_7_1_EAX_WRMSRNS }, 1775 .to = { FEAT_7_1_EAX, CPUID_7_1_EAX_FRED }, 1776 }, 1777 { 1778 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_SGX }, 1779 .to = { FEAT_7_0_ECX, CPUID_7_0_ECX_SGX_LC }, 1780 }, 1781 { 1782 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_SGX }, 1783 .to = { FEAT_SGX_12_0_EAX, ~0ull }, 1784 }, 1785 { 1786 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_SGX }, 1787 .to = { FEAT_SGX_12_0_EBX, ~0ull }, 1788 }, 1789 { 1790 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_SGX }, 1791 .to = { FEAT_SGX_12_1_EAX, ~0ull }, 1792 }, 1793 { 1794 .from = { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_128 }, 1795 .to = { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_256 }, 1796 }, 1797 { 1798 .from = { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_256 }, 1799 .to = { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_512 }, 1800 }, 1801 { 1802 .from = { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_VL_MASK }, 1803 .to = { FEAT_7_1_EDX, CPUID_7_1_EDX_AVX10 }, 1804 }, 1805 { 1806 .from = { FEAT_7_1_EDX, CPUID_7_1_EDX_AVX10 }, 1807 .to = { FEAT_24_0_EBX, ~0ull }, 1808 }, 1809 }; 1810 1811 typedef struct X86RegisterInfo32 { 1812 /* Name of register */ 1813 const char *name; 1814 /* QAPI enum value register */ 1815 X86CPURegister32 qapi_enum; 1816 } X86RegisterInfo32; 1817 1818 #define REGISTER(reg) \ 1819 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg } 1820 static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = { 1821 REGISTER(EAX), 1822 REGISTER(ECX), 1823 REGISTER(EDX), 1824 REGISTER(EBX), 1825 REGISTER(ESP), 1826 REGISTER(EBP), 1827 REGISTER(ESI), 1828 REGISTER(EDI), 1829 }; 1830 #undef REGISTER 1831 1832 /* CPUID feature bits available in XSS */ 1833 #define CPUID_XSTATE_XSS_MASK (XSTATE_ARCH_LBR_MASK) 1834 1835 ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUNT] = { 1836 [XSTATE_FP_BIT] = { 1837 /* x87 FP state component is always enabled if XSAVE is supported */ 1838 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE, 1839 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader), 1840 }, 1841 [XSTATE_SSE_BIT] = { 1842 /* SSE state component is always enabled if XSAVE is supported */ 1843 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE, 1844 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader), 1845 }, 1846 [XSTATE_YMM_BIT] = 1847 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX, 1848 .size = sizeof(XSaveAVX) }, 1849 [XSTATE_BNDREGS_BIT] = 1850 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX, 1851 .size = sizeof(XSaveBNDREG) }, 1852 [XSTATE_BNDCSR_BIT] = 1853 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX, 1854 .size = sizeof(XSaveBNDCSR) }, 1855 [XSTATE_OPMASK_BIT] = 1856 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1857 .size = sizeof(XSaveOpmask) }, 1858 [XSTATE_ZMM_Hi256_BIT] = 1859 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1860 .size = sizeof(XSaveZMM_Hi256) }, 1861 [XSTATE_Hi16_ZMM_BIT] = 1862 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1863 .size = sizeof(XSaveHi16_ZMM) }, 1864 [XSTATE_PKRU_BIT] = 1865 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU, 1866 .size = sizeof(XSavePKRU) }, 1867 [XSTATE_ARCH_LBR_BIT] = { 1868 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_ARCH_LBR, 1869 .offset = 0 /*supervisor mode component, offset = 0 */, 1870 .size = sizeof(XSavesArchLBR) }, 1871 [XSTATE_XTILE_CFG_BIT] = { 1872 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_AMX_TILE, 1873 .size = sizeof(XSaveXTILECFG), 1874 }, 1875 [XSTATE_XTILE_DATA_BIT] = { 1876 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_AMX_TILE, 1877 .size = sizeof(XSaveXTILEDATA) 1878 }, 1879 }; 1880 1881 uint32_t xsave_area_size(uint64_t mask, bool compacted) 1882 { 1883 uint64_t ret = x86_ext_save_areas[0].size; 1884 const ExtSaveArea *esa; 1885 uint32_t offset = 0; 1886 int i; 1887 1888 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 1889 esa = &x86_ext_save_areas[i]; 1890 if ((mask >> i) & 1) { 1891 offset = compacted ? ret : esa->offset; 1892 ret = MAX(ret, offset + esa->size); 1893 } 1894 } 1895 return ret; 1896 } 1897 1898 static inline bool accel_uses_host_cpuid(void) 1899 { 1900 return kvm_enabled() || hvf_enabled(); 1901 } 1902 1903 static inline uint64_t x86_cpu_xsave_xcr0_components(X86CPU *cpu) 1904 { 1905 return ((uint64_t)cpu->env.features[FEAT_XSAVE_XCR0_HI]) << 32 | 1906 cpu->env.features[FEAT_XSAVE_XCR0_LO]; 1907 } 1908 1909 /* Return name of 32-bit register, from a R_* constant */ 1910 static const char *get_register_name_32(unsigned int reg) 1911 { 1912 if (reg >= CPU_NB_REGS32) { 1913 return NULL; 1914 } 1915 return x86_reg_info_32[reg].name; 1916 } 1917 1918 static inline uint64_t x86_cpu_xsave_xss_components(X86CPU *cpu) 1919 { 1920 return ((uint64_t)cpu->env.features[FEAT_XSAVE_XSS_HI]) << 32 | 1921 cpu->env.features[FEAT_XSAVE_XSS_LO]; 1922 } 1923 1924 /* 1925 * Returns the set of feature flags that are supported and migratable by 1926 * QEMU, for a given FeatureWord. 1927 */ 1928 static uint64_t x86_cpu_get_migratable_flags(X86CPU *cpu, FeatureWord w) 1929 { 1930 FeatureWordInfo *wi = &feature_word_info[w]; 1931 CPUX86State *env = &cpu->env; 1932 uint64_t r = 0; 1933 int i; 1934 1935 for (i = 0; i < 64; i++) { 1936 uint64_t f = 1ULL << i; 1937 1938 /* If the feature name is known, it is implicitly considered migratable, 1939 * unless it is explicitly set in unmigratable_flags */ 1940 if ((wi->migratable_flags & f) || 1941 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) { 1942 r |= f; 1943 } 1944 } 1945 1946 /* when tsc-khz is set explicitly, invtsc is migratable */ 1947 if ((w == FEAT_8000_0007_EDX) && env->user_tsc_khz) { 1948 r |= CPUID_APM_INVTSC; 1949 } 1950 1951 return r; 1952 } 1953 1954 void host_cpuid(uint32_t function, uint32_t count, 1955 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) 1956 { 1957 uint32_t vec[4]; 1958 1959 #ifdef __x86_64__ 1960 asm volatile("cpuid" 1961 : "=a"(vec[0]), "=b"(vec[1]), 1962 "=c"(vec[2]), "=d"(vec[3]) 1963 : "0"(function), "c"(count) : "cc"); 1964 #elif defined(__i386__) 1965 asm volatile("pusha \n\t" 1966 "cpuid \n\t" 1967 "mov %%eax, 0(%2) \n\t" 1968 "mov %%ebx, 4(%2) \n\t" 1969 "mov %%ecx, 8(%2) \n\t" 1970 "mov %%edx, 12(%2) \n\t" 1971 "popa" 1972 : : "a"(function), "c"(count), "S"(vec) 1973 : "memory", "cc"); 1974 #else 1975 abort(); 1976 #endif 1977 1978 if (eax) 1979 *eax = vec[0]; 1980 if (ebx) 1981 *ebx = vec[1]; 1982 if (ecx) 1983 *ecx = vec[2]; 1984 if (edx) 1985 *edx = vec[3]; 1986 } 1987 1988 /* CPU class name definitions: */ 1989 1990 /* Return type name for a given CPU model name 1991 * Caller is responsible for freeing the returned string. 1992 */ 1993 static char *x86_cpu_type_name(const char *model_name) 1994 { 1995 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name); 1996 } 1997 1998 static ObjectClass *x86_cpu_class_by_name(const char *cpu_model) 1999 { 2000 g_autofree char *typename = x86_cpu_type_name(cpu_model); 2001 return object_class_by_name(typename); 2002 } 2003 2004 static char *x86_cpu_class_get_model_name(X86CPUClass *cc) 2005 { 2006 const char *class_name = object_class_get_name(OBJECT_CLASS(cc)); 2007 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX)); 2008 return cpu_model_from_type(class_name); 2009 } 2010 2011 typedef struct X86CPUVersionDefinition { 2012 X86CPUVersion version; 2013 const char *alias; 2014 const char *note; 2015 PropValue *props; 2016 const CPUCaches *const cache_info; 2017 } X86CPUVersionDefinition; 2018 2019 /* Base definition for a CPU model */ 2020 typedef struct X86CPUDefinition { 2021 const char *name; 2022 uint32_t level; 2023 uint32_t xlevel; 2024 /* vendor is zero-terminated, 12 character ASCII string */ 2025 char vendor[CPUID_VENDOR_SZ + 1]; 2026 int family; 2027 int model; 2028 int stepping; 2029 uint8_t avx10_version; 2030 FeatureWordArray features; 2031 const char *model_id; 2032 const CPUCaches *const cache_info; 2033 /* 2034 * Definitions for alternative versions of CPU model. 2035 * List is terminated by item with version == 0. 2036 * If NULL, version 1 will be registered automatically. 2037 */ 2038 const X86CPUVersionDefinition *versions; 2039 const char *deprecation_note; 2040 } X86CPUDefinition; 2041 2042 /* Reference to a specific CPU model version */ 2043 struct X86CPUModel { 2044 /* Base CPU definition */ 2045 const X86CPUDefinition *cpudef; 2046 /* CPU model version */ 2047 X86CPUVersion version; 2048 const char *note; 2049 /* 2050 * If true, this is an alias CPU model. 2051 * This matters only for "-cpu help" and query-cpu-definitions 2052 */ 2053 bool is_alias; 2054 }; 2055 2056 /* Get full model name for CPU version */ 2057 static char *x86_cpu_versioned_model_name(const X86CPUDefinition *cpudef, 2058 X86CPUVersion version) 2059 { 2060 assert(version > 0); 2061 return g_strdup_printf("%s-v%d", cpudef->name, (int)version); 2062 } 2063 2064 static const X86CPUVersionDefinition * 2065 x86_cpu_def_get_versions(const X86CPUDefinition *def) 2066 { 2067 /* When X86CPUDefinition::versions is NULL, we register only v1 */ 2068 static const X86CPUVersionDefinition default_version_list[] = { 2069 { 1 }, 2070 { /* end of list */ } 2071 }; 2072 2073 return def->versions ?: default_version_list; 2074 } 2075 2076 static const CPUCaches epyc_cache_info = { 2077 .l1d_cache = &(CPUCacheInfo) { 2078 .type = DATA_CACHE, 2079 .level = 1, 2080 .size = 32 * KiB, 2081 .line_size = 64, 2082 .associativity = 8, 2083 .partitions = 1, 2084 .sets = 64, 2085 .lines_per_tag = 1, 2086 .self_init = 1, 2087 .no_invd_sharing = true, 2088 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2089 }, 2090 .l1i_cache = &(CPUCacheInfo) { 2091 .type = INSTRUCTION_CACHE, 2092 .level = 1, 2093 .size = 64 * KiB, 2094 .line_size = 64, 2095 .associativity = 4, 2096 .partitions = 1, 2097 .sets = 256, 2098 .lines_per_tag = 1, 2099 .self_init = 1, 2100 .no_invd_sharing = true, 2101 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2102 }, 2103 .l2_cache = &(CPUCacheInfo) { 2104 .type = UNIFIED_CACHE, 2105 .level = 2, 2106 .size = 512 * KiB, 2107 .line_size = 64, 2108 .associativity = 8, 2109 .partitions = 1, 2110 .sets = 1024, 2111 .lines_per_tag = 1, 2112 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2113 }, 2114 .l3_cache = &(CPUCacheInfo) { 2115 .type = UNIFIED_CACHE, 2116 .level = 3, 2117 .size = 8 * MiB, 2118 .line_size = 64, 2119 .associativity = 16, 2120 .partitions = 1, 2121 .sets = 8192, 2122 .lines_per_tag = 1, 2123 .self_init = true, 2124 .inclusive = true, 2125 .complex_indexing = true, 2126 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2127 }, 2128 }; 2129 2130 static CPUCaches epyc_v4_cache_info = { 2131 .l1d_cache = &(CPUCacheInfo) { 2132 .type = DATA_CACHE, 2133 .level = 1, 2134 .size = 32 * KiB, 2135 .line_size = 64, 2136 .associativity = 8, 2137 .partitions = 1, 2138 .sets = 64, 2139 .lines_per_tag = 1, 2140 .self_init = 1, 2141 .no_invd_sharing = true, 2142 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2143 }, 2144 .l1i_cache = &(CPUCacheInfo) { 2145 .type = INSTRUCTION_CACHE, 2146 .level = 1, 2147 .size = 64 * KiB, 2148 .line_size = 64, 2149 .associativity = 4, 2150 .partitions = 1, 2151 .sets = 256, 2152 .lines_per_tag = 1, 2153 .self_init = 1, 2154 .no_invd_sharing = true, 2155 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2156 }, 2157 .l2_cache = &(CPUCacheInfo) { 2158 .type = UNIFIED_CACHE, 2159 .level = 2, 2160 .size = 512 * KiB, 2161 .line_size = 64, 2162 .associativity = 8, 2163 .partitions = 1, 2164 .sets = 1024, 2165 .lines_per_tag = 1, 2166 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2167 }, 2168 .l3_cache = &(CPUCacheInfo) { 2169 .type = UNIFIED_CACHE, 2170 .level = 3, 2171 .size = 8 * MiB, 2172 .line_size = 64, 2173 .associativity = 16, 2174 .partitions = 1, 2175 .sets = 8192, 2176 .lines_per_tag = 1, 2177 .self_init = true, 2178 .inclusive = true, 2179 .complex_indexing = false, 2180 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2181 }, 2182 }; 2183 2184 static const CPUCaches epyc_rome_cache_info = { 2185 .l1d_cache = &(CPUCacheInfo) { 2186 .type = DATA_CACHE, 2187 .level = 1, 2188 .size = 32 * KiB, 2189 .line_size = 64, 2190 .associativity = 8, 2191 .partitions = 1, 2192 .sets = 64, 2193 .lines_per_tag = 1, 2194 .self_init = 1, 2195 .no_invd_sharing = true, 2196 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2197 }, 2198 .l1i_cache = &(CPUCacheInfo) { 2199 .type = INSTRUCTION_CACHE, 2200 .level = 1, 2201 .size = 32 * KiB, 2202 .line_size = 64, 2203 .associativity = 8, 2204 .partitions = 1, 2205 .sets = 64, 2206 .lines_per_tag = 1, 2207 .self_init = 1, 2208 .no_invd_sharing = true, 2209 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2210 }, 2211 .l2_cache = &(CPUCacheInfo) { 2212 .type = UNIFIED_CACHE, 2213 .level = 2, 2214 .size = 512 * KiB, 2215 .line_size = 64, 2216 .associativity = 8, 2217 .partitions = 1, 2218 .sets = 1024, 2219 .lines_per_tag = 1, 2220 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2221 }, 2222 .l3_cache = &(CPUCacheInfo) { 2223 .type = UNIFIED_CACHE, 2224 .level = 3, 2225 .size = 16 * MiB, 2226 .line_size = 64, 2227 .associativity = 16, 2228 .partitions = 1, 2229 .sets = 16384, 2230 .lines_per_tag = 1, 2231 .self_init = true, 2232 .inclusive = true, 2233 .complex_indexing = true, 2234 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2235 }, 2236 }; 2237 2238 static const CPUCaches epyc_rome_v3_cache_info = { 2239 .l1d_cache = &(CPUCacheInfo) { 2240 .type = DATA_CACHE, 2241 .level = 1, 2242 .size = 32 * KiB, 2243 .line_size = 64, 2244 .associativity = 8, 2245 .partitions = 1, 2246 .sets = 64, 2247 .lines_per_tag = 1, 2248 .self_init = 1, 2249 .no_invd_sharing = true, 2250 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2251 }, 2252 .l1i_cache = &(CPUCacheInfo) { 2253 .type = INSTRUCTION_CACHE, 2254 .level = 1, 2255 .size = 32 * KiB, 2256 .line_size = 64, 2257 .associativity = 8, 2258 .partitions = 1, 2259 .sets = 64, 2260 .lines_per_tag = 1, 2261 .self_init = 1, 2262 .no_invd_sharing = true, 2263 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2264 }, 2265 .l2_cache = &(CPUCacheInfo) { 2266 .type = UNIFIED_CACHE, 2267 .level = 2, 2268 .size = 512 * KiB, 2269 .line_size = 64, 2270 .associativity = 8, 2271 .partitions = 1, 2272 .sets = 1024, 2273 .lines_per_tag = 1, 2274 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2275 }, 2276 .l3_cache = &(CPUCacheInfo) { 2277 .type = UNIFIED_CACHE, 2278 .level = 3, 2279 .size = 16 * MiB, 2280 .line_size = 64, 2281 .associativity = 16, 2282 .partitions = 1, 2283 .sets = 16384, 2284 .lines_per_tag = 1, 2285 .self_init = true, 2286 .inclusive = true, 2287 .complex_indexing = false, 2288 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2289 }, 2290 }; 2291 2292 static const CPUCaches epyc_milan_cache_info = { 2293 .l1d_cache = &(CPUCacheInfo) { 2294 .type = DATA_CACHE, 2295 .level = 1, 2296 .size = 32 * KiB, 2297 .line_size = 64, 2298 .associativity = 8, 2299 .partitions = 1, 2300 .sets = 64, 2301 .lines_per_tag = 1, 2302 .self_init = 1, 2303 .no_invd_sharing = true, 2304 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2305 }, 2306 .l1i_cache = &(CPUCacheInfo) { 2307 .type = INSTRUCTION_CACHE, 2308 .level = 1, 2309 .size = 32 * KiB, 2310 .line_size = 64, 2311 .associativity = 8, 2312 .partitions = 1, 2313 .sets = 64, 2314 .lines_per_tag = 1, 2315 .self_init = 1, 2316 .no_invd_sharing = true, 2317 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2318 }, 2319 .l2_cache = &(CPUCacheInfo) { 2320 .type = UNIFIED_CACHE, 2321 .level = 2, 2322 .size = 512 * KiB, 2323 .line_size = 64, 2324 .associativity = 8, 2325 .partitions = 1, 2326 .sets = 1024, 2327 .lines_per_tag = 1, 2328 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2329 }, 2330 .l3_cache = &(CPUCacheInfo) { 2331 .type = UNIFIED_CACHE, 2332 .level = 3, 2333 .size = 32 * MiB, 2334 .line_size = 64, 2335 .associativity = 16, 2336 .partitions = 1, 2337 .sets = 32768, 2338 .lines_per_tag = 1, 2339 .self_init = true, 2340 .inclusive = true, 2341 .complex_indexing = true, 2342 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2343 }, 2344 }; 2345 2346 static const CPUCaches epyc_milan_v2_cache_info = { 2347 .l1d_cache = &(CPUCacheInfo) { 2348 .type = DATA_CACHE, 2349 .level = 1, 2350 .size = 32 * KiB, 2351 .line_size = 64, 2352 .associativity = 8, 2353 .partitions = 1, 2354 .sets = 64, 2355 .lines_per_tag = 1, 2356 .self_init = 1, 2357 .no_invd_sharing = true, 2358 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2359 }, 2360 .l1i_cache = &(CPUCacheInfo) { 2361 .type = INSTRUCTION_CACHE, 2362 .level = 1, 2363 .size = 32 * KiB, 2364 .line_size = 64, 2365 .associativity = 8, 2366 .partitions = 1, 2367 .sets = 64, 2368 .lines_per_tag = 1, 2369 .self_init = 1, 2370 .no_invd_sharing = true, 2371 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2372 }, 2373 .l2_cache = &(CPUCacheInfo) { 2374 .type = UNIFIED_CACHE, 2375 .level = 2, 2376 .size = 512 * KiB, 2377 .line_size = 64, 2378 .associativity = 8, 2379 .partitions = 1, 2380 .sets = 1024, 2381 .lines_per_tag = 1, 2382 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2383 }, 2384 .l3_cache = &(CPUCacheInfo) { 2385 .type = UNIFIED_CACHE, 2386 .level = 3, 2387 .size = 32 * MiB, 2388 .line_size = 64, 2389 .associativity = 16, 2390 .partitions = 1, 2391 .sets = 32768, 2392 .lines_per_tag = 1, 2393 .self_init = true, 2394 .inclusive = true, 2395 .complex_indexing = false, 2396 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2397 }, 2398 }; 2399 2400 static const CPUCaches epyc_genoa_cache_info = { 2401 .l1d_cache = &(CPUCacheInfo) { 2402 .type = DATA_CACHE, 2403 .level = 1, 2404 .size = 32 * KiB, 2405 .line_size = 64, 2406 .associativity = 8, 2407 .partitions = 1, 2408 .sets = 64, 2409 .lines_per_tag = 1, 2410 .self_init = 1, 2411 .no_invd_sharing = true, 2412 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2413 }, 2414 .l1i_cache = &(CPUCacheInfo) { 2415 .type = INSTRUCTION_CACHE, 2416 .level = 1, 2417 .size = 32 * KiB, 2418 .line_size = 64, 2419 .associativity = 8, 2420 .partitions = 1, 2421 .sets = 64, 2422 .lines_per_tag = 1, 2423 .self_init = 1, 2424 .no_invd_sharing = true, 2425 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2426 }, 2427 .l2_cache = &(CPUCacheInfo) { 2428 .type = UNIFIED_CACHE, 2429 .level = 2, 2430 .size = 1 * MiB, 2431 .line_size = 64, 2432 .associativity = 8, 2433 .partitions = 1, 2434 .sets = 2048, 2435 .lines_per_tag = 1, 2436 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2437 }, 2438 .l3_cache = &(CPUCacheInfo) { 2439 .type = UNIFIED_CACHE, 2440 .level = 3, 2441 .size = 32 * MiB, 2442 .line_size = 64, 2443 .associativity = 16, 2444 .partitions = 1, 2445 .sets = 32768, 2446 .lines_per_tag = 1, 2447 .self_init = true, 2448 .inclusive = true, 2449 .complex_indexing = false, 2450 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2451 }, 2452 }; 2453 2454 /* The following VMX features are not supported by KVM and are left out in the 2455 * CPU definitions: 2456 * 2457 * Dual-monitor support (all processors) 2458 * Entry to SMM 2459 * Deactivate dual-monitor treatment 2460 * Number of CR3-target values 2461 * Shutdown activity state 2462 * Wait-for-SIPI activity state 2463 * PAUSE-loop exiting (Westmere and newer) 2464 * EPT-violation #VE (Broadwell and newer) 2465 * Inject event with insn length=0 (Skylake and newer) 2466 * Conceal non-root operation from PT 2467 * Conceal VM exits from PT 2468 * Conceal VM entries from PT 2469 * Enable ENCLS exiting 2470 * Mode-based execute control (XS/XU) 2471 * TSC scaling (Skylake Server and newer) 2472 * GPA translation for PT (IceLake and newer) 2473 * User wait and pause 2474 * ENCLV exiting 2475 * Load IA32_RTIT_CTL 2476 * Clear IA32_RTIT_CTL 2477 * Advanced VM-exit information for EPT violations 2478 * Sub-page write permissions 2479 * PT in VMX operation 2480 */ 2481 2482 static const X86CPUDefinition builtin_x86_defs[] = { 2483 { 2484 .name = "qemu64", 2485 .level = 0xd, 2486 .vendor = CPUID_VENDOR_AMD, 2487 .family = 15, 2488 .model = 107, 2489 .stepping = 1, 2490 .features[FEAT_1_EDX] = 2491 PPRO_FEATURES | 2492 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2493 CPUID_PSE36, 2494 .features[FEAT_1_ECX] = 2495 CPUID_EXT_SSE3 | CPUID_EXT_CX16, 2496 .features[FEAT_8000_0001_EDX] = 2497 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2498 .features[FEAT_8000_0001_ECX] = 2499 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM, 2500 .xlevel = 0x8000000A, 2501 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 2502 }, 2503 { 2504 .name = "phenom", 2505 .level = 5, 2506 .vendor = CPUID_VENDOR_AMD, 2507 .family = 16, 2508 .model = 2, 2509 .stepping = 3, 2510 /* Missing: CPUID_HT */ 2511 .features[FEAT_1_EDX] = 2512 PPRO_FEATURES | 2513 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2514 CPUID_PSE36 | CPUID_VME, 2515 .features[FEAT_1_ECX] = 2516 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 | 2517 CPUID_EXT_POPCNT, 2518 .features[FEAT_8000_0001_EDX] = 2519 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | 2520 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT | 2521 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP, 2522 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, 2523 CPUID_EXT3_CR8LEG, 2524 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, 2525 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */ 2526 .features[FEAT_8000_0001_ECX] = 2527 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | 2528 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A, 2529 /* Missing: CPUID_SVM_LBRV */ 2530 .features[FEAT_SVM] = 2531 CPUID_SVM_NPT, 2532 .xlevel = 0x8000001A, 2533 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor" 2534 }, 2535 { 2536 .name = "core2duo", 2537 .level = 10, 2538 .vendor = CPUID_VENDOR_INTEL, 2539 .family = 6, 2540 .model = 15, 2541 .stepping = 11, 2542 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2543 .features[FEAT_1_EDX] = 2544 PPRO_FEATURES | 2545 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2546 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS, 2547 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST, 2548 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */ 2549 .features[FEAT_1_ECX] = 2550 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | 2551 CPUID_EXT_CX16, 2552 .features[FEAT_8000_0001_EDX] = 2553 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2554 .features[FEAT_8000_0001_ECX] = 2555 CPUID_EXT3_LAHF_LM, 2556 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2557 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2558 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2559 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2560 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2561 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2562 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2563 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2564 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2565 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2566 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2567 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2568 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2569 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2570 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2571 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2572 .features[FEAT_VMX_SECONDARY_CTLS] = 2573 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES, 2574 .xlevel = 0x80000008, 2575 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz", 2576 }, 2577 { 2578 .name = "kvm64", 2579 .level = 0xd, 2580 .vendor = CPUID_VENDOR_INTEL, 2581 .family = 15, 2582 .model = 6, 2583 .stepping = 1, 2584 /* Missing: CPUID_HT */ 2585 .features[FEAT_1_EDX] = 2586 PPRO_FEATURES | CPUID_VME | 2587 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2588 CPUID_PSE36, 2589 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */ 2590 .features[FEAT_1_ECX] = 2591 CPUID_EXT_SSE3 | CPUID_EXT_CX16, 2592 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */ 2593 .features[FEAT_8000_0001_EDX] = 2594 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2595 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, 2596 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A, 2597 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, 2598 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */ 2599 .features[FEAT_8000_0001_ECX] = 2600 0, 2601 /* VMX features from Cedar Mill/Prescott */ 2602 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2603 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2604 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2605 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2606 VMX_PIN_BASED_NMI_EXITING, 2607 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2608 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2609 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2610 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2611 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2612 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2613 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2614 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING, 2615 .xlevel = 0x80000008, 2616 .model_id = "Common KVM processor" 2617 }, 2618 { 2619 .name = "qemu32", 2620 .level = 4, 2621 .vendor = CPUID_VENDOR_INTEL, 2622 .family = 6, 2623 .model = 6, 2624 .stepping = 3, 2625 .features[FEAT_1_EDX] = 2626 PPRO_FEATURES, 2627 .features[FEAT_1_ECX] = 2628 CPUID_EXT_SSE3, 2629 .xlevel = 0x80000004, 2630 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 2631 }, 2632 { 2633 .name = "kvm32", 2634 .level = 5, 2635 .vendor = CPUID_VENDOR_INTEL, 2636 .family = 15, 2637 .model = 6, 2638 .stepping = 1, 2639 .features[FEAT_1_EDX] = 2640 PPRO_FEATURES | CPUID_VME | 2641 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36, 2642 .features[FEAT_1_ECX] = 2643 CPUID_EXT_SSE3, 2644 .features[FEAT_8000_0001_ECX] = 2645 0, 2646 /* VMX features from Yonah */ 2647 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2648 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2649 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2650 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2651 VMX_PIN_BASED_NMI_EXITING, 2652 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2653 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2654 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2655 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2656 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 2657 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 2658 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS, 2659 .xlevel = 0x80000008, 2660 .model_id = "Common 32-bit KVM processor" 2661 }, 2662 { 2663 .name = "coreduo", 2664 .level = 10, 2665 .vendor = CPUID_VENDOR_INTEL, 2666 .family = 6, 2667 .model = 14, 2668 .stepping = 8, 2669 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2670 .features[FEAT_1_EDX] = 2671 PPRO_FEATURES | CPUID_VME | 2672 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI | 2673 CPUID_SS, 2674 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR, 2675 * CPUID_EXT_PDCM, CPUID_EXT_VMX */ 2676 .features[FEAT_1_ECX] = 2677 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR, 2678 .features[FEAT_8000_0001_EDX] = 2679 CPUID_EXT2_NX, 2680 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2681 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2682 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2683 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2684 VMX_PIN_BASED_NMI_EXITING, 2685 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2686 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2687 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2688 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2689 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 2690 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 2691 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS, 2692 .xlevel = 0x80000008, 2693 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz", 2694 }, 2695 { 2696 .name = "486", 2697 .level = 1, 2698 .vendor = CPUID_VENDOR_INTEL, 2699 .family = 4, 2700 .model = 8, 2701 .stepping = 0, 2702 .features[FEAT_1_EDX] = 2703 I486_FEATURES, 2704 .xlevel = 0, 2705 .model_id = "", 2706 }, 2707 { 2708 .name = "pentium", 2709 .level = 1, 2710 .vendor = CPUID_VENDOR_INTEL, 2711 .family = 5, 2712 .model = 4, 2713 .stepping = 3, 2714 .features[FEAT_1_EDX] = 2715 PENTIUM_FEATURES, 2716 .xlevel = 0, 2717 .model_id = "", 2718 }, 2719 { 2720 .name = "pentium2", 2721 .level = 2, 2722 .vendor = CPUID_VENDOR_INTEL, 2723 .family = 6, 2724 .model = 5, 2725 .stepping = 2, 2726 .features[FEAT_1_EDX] = 2727 PENTIUM2_FEATURES, 2728 .xlevel = 0, 2729 .model_id = "", 2730 }, 2731 { 2732 .name = "pentium3", 2733 .level = 3, 2734 .vendor = CPUID_VENDOR_INTEL, 2735 .family = 6, 2736 .model = 7, 2737 .stepping = 3, 2738 .features[FEAT_1_EDX] = 2739 PENTIUM3_FEATURES, 2740 .xlevel = 0, 2741 .model_id = "", 2742 }, 2743 { 2744 .name = "athlon", 2745 .level = 2, 2746 .vendor = CPUID_VENDOR_AMD, 2747 .family = 6, 2748 .model = 2, 2749 .stepping = 3, 2750 .features[FEAT_1_EDX] = 2751 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR | 2752 CPUID_MCA, 2753 .features[FEAT_8000_0001_EDX] = 2754 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT, 2755 .xlevel = 0x80000008, 2756 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 2757 }, 2758 { 2759 .name = "n270", 2760 .level = 10, 2761 .vendor = CPUID_VENDOR_INTEL, 2762 .family = 6, 2763 .model = 28, 2764 .stepping = 2, 2765 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2766 .features[FEAT_1_EDX] = 2767 PPRO_FEATURES | 2768 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | 2769 CPUID_ACPI | CPUID_SS, 2770 /* Some CPUs got no CPUID_SEP */ 2771 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2, 2772 * CPUID_EXT_XTPR */ 2773 .features[FEAT_1_ECX] = 2774 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | 2775 CPUID_EXT_MOVBE, 2776 .features[FEAT_8000_0001_EDX] = 2777 CPUID_EXT2_NX, 2778 .features[FEAT_8000_0001_ECX] = 2779 CPUID_EXT3_LAHF_LM, 2780 .xlevel = 0x80000008, 2781 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz", 2782 }, 2783 { 2784 .name = "Conroe", 2785 .level = 10, 2786 .vendor = CPUID_VENDOR_INTEL, 2787 .family = 6, 2788 .model = 15, 2789 .stepping = 3, 2790 .features[FEAT_1_EDX] = 2791 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2792 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2793 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2794 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2795 CPUID_DE | CPUID_FP87, 2796 .features[FEAT_1_ECX] = 2797 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, 2798 .features[FEAT_8000_0001_EDX] = 2799 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 2800 .features[FEAT_8000_0001_ECX] = 2801 CPUID_EXT3_LAHF_LM, 2802 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2803 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2804 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2805 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2806 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2807 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2808 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2809 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2810 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2811 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2812 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2813 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2814 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2815 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2816 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2817 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2818 .features[FEAT_VMX_SECONDARY_CTLS] = 2819 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES, 2820 .xlevel = 0x80000008, 2821 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)", 2822 }, 2823 { 2824 .name = "Penryn", 2825 .level = 10, 2826 .vendor = CPUID_VENDOR_INTEL, 2827 .family = 6, 2828 .model = 23, 2829 .stepping = 3, 2830 .features[FEAT_1_EDX] = 2831 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2832 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2833 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2834 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2835 CPUID_DE | CPUID_FP87, 2836 .features[FEAT_1_ECX] = 2837 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2838 CPUID_EXT_SSE3, 2839 .features[FEAT_8000_0001_EDX] = 2840 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 2841 .features[FEAT_8000_0001_ECX] = 2842 CPUID_EXT3_LAHF_LM, 2843 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2844 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2845 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, 2846 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT | 2847 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL, 2848 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2849 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2850 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2851 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2852 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2853 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2854 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2855 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2856 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2857 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2858 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2859 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2860 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2861 .features[FEAT_VMX_SECONDARY_CTLS] = 2862 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2863 VMX_SECONDARY_EXEC_WBINVD_EXITING, 2864 .xlevel = 0x80000008, 2865 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)", 2866 }, 2867 { 2868 .name = "Nehalem", 2869 .level = 11, 2870 .vendor = CPUID_VENDOR_INTEL, 2871 .family = 6, 2872 .model = 26, 2873 .stepping = 3, 2874 .features[FEAT_1_EDX] = 2875 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2876 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2877 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2878 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2879 CPUID_DE | CPUID_FP87, 2880 .features[FEAT_1_ECX] = 2881 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 2882 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, 2883 .features[FEAT_8000_0001_EDX] = 2884 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2885 .features[FEAT_8000_0001_ECX] = 2886 CPUID_EXT3_LAHF_LM, 2887 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2888 MSR_VMX_BASIC_TRUE_CTLS, 2889 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2890 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2891 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2892 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2893 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2894 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2895 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2896 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2897 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2898 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2899 .features[FEAT_VMX_EXIT_CTLS] = 2900 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2901 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2902 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2903 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2904 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2905 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2906 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2907 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2908 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2909 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2910 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2911 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2912 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2913 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2914 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2915 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2916 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2917 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2918 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2919 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2920 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2921 .features[FEAT_VMX_SECONDARY_CTLS] = 2922 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2923 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2924 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2925 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2926 VMX_SECONDARY_EXEC_ENABLE_VPID, 2927 .xlevel = 0x80000008, 2928 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)", 2929 .versions = (X86CPUVersionDefinition[]) { 2930 { .version = 1 }, 2931 { 2932 .version = 2, 2933 .alias = "Nehalem-IBRS", 2934 .props = (PropValue[]) { 2935 { "spec-ctrl", "on" }, 2936 { "model-id", 2937 "Intel Core i7 9xx (Nehalem Core i7, IBRS update)" }, 2938 { /* end of list */ } 2939 } 2940 }, 2941 { /* end of list */ } 2942 } 2943 }, 2944 { 2945 .name = "Westmere", 2946 .level = 11, 2947 .vendor = CPUID_VENDOR_INTEL, 2948 .family = 6, 2949 .model = 44, 2950 .stepping = 1, 2951 .features[FEAT_1_EDX] = 2952 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2953 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2954 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2955 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2956 CPUID_DE | CPUID_FP87, 2957 .features[FEAT_1_ECX] = 2958 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | 2959 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2960 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 2961 .features[FEAT_8000_0001_EDX] = 2962 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2963 .features[FEAT_8000_0001_ECX] = 2964 CPUID_EXT3_LAHF_LM, 2965 .features[FEAT_6_EAX] = 2966 CPUID_6_EAX_ARAT, 2967 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2968 MSR_VMX_BASIC_TRUE_CTLS, 2969 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2970 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2971 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2972 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2973 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2974 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2975 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2976 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2977 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2978 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2979 .features[FEAT_VMX_EXIT_CTLS] = 2980 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2981 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2982 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2983 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2984 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2985 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2986 MSR_VMX_MISC_STORE_LMA, 2987 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2988 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2989 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2990 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2991 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2992 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2993 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2994 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2995 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2996 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2997 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2998 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2999 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3000 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3001 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3002 .features[FEAT_VMX_SECONDARY_CTLS] = 3003 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3004 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3005 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3006 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3007 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST, 3008 .xlevel = 0x80000008, 3009 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)", 3010 .versions = (X86CPUVersionDefinition[]) { 3011 { .version = 1 }, 3012 { 3013 .version = 2, 3014 .alias = "Westmere-IBRS", 3015 .props = (PropValue[]) { 3016 { "spec-ctrl", "on" }, 3017 { "model-id", 3018 "Westmere E56xx/L56xx/X56xx (IBRS update)" }, 3019 { /* end of list */ } 3020 } 3021 }, 3022 { /* end of list */ } 3023 } 3024 }, 3025 { 3026 .name = "SandyBridge", 3027 .level = 0xd, 3028 .vendor = CPUID_VENDOR_INTEL, 3029 .family = 6, 3030 .model = 42, 3031 .stepping = 1, 3032 .features[FEAT_1_EDX] = 3033 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3034 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3035 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3036 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3037 CPUID_DE | CPUID_FP87, 3038 .features[FEAT_1_ECX] = 3039 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3040 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | 3041 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 3042 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 3043 CPUID_EXT_SSE3, 3044 .features[FEAT_8000_0001_EDX] = 3045 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3046 CPUID_EXT2_SYSCALL, 3047 .features[FEAT_8000_0001_ECX] = 3048 CPUID_EXT3_LAHF_LM, 3049 .features[FEAT_XSAVE] = 3050 CPUID_XSAVE_XSAVEOPT, 3051 .features[FEAT_6_EAX] = 3052 CPUID_6_EAX_ARAT, 3053 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3054 MSR_VMX_BASIC_TRUE_CTLS, 3055 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3056 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3057 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3058 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3059 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3060 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3061 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3062 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3063 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3064 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 3065 .features[FEAT_VMX_EXIT_CTLS] = 3066 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3067 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3068 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3069 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3070 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3071 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3072 MSR_VMX_MISC_STORE_LMA, 3073 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3074 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3075 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 3076 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3077 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3078 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3079 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3080 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3081 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3082 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3083 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3084 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3085 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3086 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3087 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3088 .features[FEAT_VMX_SECONDARY_CTLS] = 3089 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3090 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3091 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3092 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3093 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST, 3094 .xlevel = 0x80000008, 3095 .model_id = "Intel Xeon E312xx (Sandy Bridge)", 3096 .versions = (X86CPUVersionDefinition[]) { 3097 { .version = 1 }, 3098 { 3099 .version = 2, 3100 .alias = "SandyBridge-IBRS", 3101 .props = (PropValue[]) { 3102 { "spec-ctrl", "on" }, 3103 { "model-id", 3104 "Intel Xeon E312xx (Sandy Bridge, IBRS update)" }, 3105 { /* end of list */ } 3106 } 3107 }, 3108 { /* end of list */ } 3109 } 3110 }, 3111 { 3112 .name = "IvyBridge", 3113 .level = 0xd, 3114 .vendor = CPUID_VENDOR_INTEL, 3115 .family = 6, 3116 .model = 58, 3117 .stepping = 9, 3118 .features[FEAT_1_EDX] = 3119 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3120 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3121 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3122 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3123 CPUID_DE | CPUID_FP87, 3124 .features[FEAT_1_ECX] = 3125 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3126 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | 3127 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 3128 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 3129 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3130 .features[FEAT_7_0_EBX] = 3131 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | 3132 CPUID_7_0_EBX_ERMS, 3133 .features[FEAT_8000_0001_EDX] = 3134 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3135 CPUID_EXT2_SYSCALL, 3136 .features[FEAT_8000_0001_ECX] = 3137 CPUID_EXT3_LAHF_LM, 3138 .features[FEAT_XSAVE] = 3139 CPUID_XSAVE_XSAVEOPT, 3140 .features[FEAT_6_EAX] = 3141 CPUID_6_EAX_ARAT, 3142 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3143 MSR_VMX_BASIC_TRUE_CTLS, 3144 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3145 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3146 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3147 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3148 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3149 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3150 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3151 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3152 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3153 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 3154 .features[FEAT_VMX_EXIT_CTLS] = 3155 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3156 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3157 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3158 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3159 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3160 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3161 MSR_VMX_MISC_STORE_LMA, 3162 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3163 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3164 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3165 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3166 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3167 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3168 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3169 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3170 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3171 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3172 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3173 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3174 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3175 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3176 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3177 .features[FEAT_VMX_SECONDARY_CTLS] = 3178 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3179 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3180 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3181 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3182 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3183 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3184 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3185 VMX_SECONDARY_EXEC_RDRAND_EXITING, 3186 .xlevel = 0x80000008, 3187 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)", 3188 .versions = (X86CPUVersionDefinition[]) { 3189 { .version = 1 }, 3190 { 3191 .version = 2, 3192 .alias = "IvyBridge-IBRS", 3193 .props = (PropValue[]) { 3194 { "spec-ctrl", "on" }, 3195 { "model-id", 3196 "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)" }, 3197 { /* end of list */ } 3198 } 3199 }, 3200 { /* end of list */ } 3201 } 3202 }, 3203 { 3204 .name = "Haswell", 3205 .level = 0xd, 3206 .vendor = CPUID_VENDOR_INTEL, 3207 .family = 6, 3208 .model = 60, 3209 .stepping = 4, 3210 .features[FEAT_1_EDX] = 3211 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3212 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3213 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3214 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3215 CPUID_DE | CPUID_FP87, 3216 .features[FEAT_1_ECX] = 3217 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3218 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3219 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3220 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3221 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3222 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3223 .features[FEAT_8000_0001_EDX] = 3224 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3225 CPUID_EXT2_SYSCALL, 3226 .features[FEAT_8000_0001_ECX] = 3227 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM, 3228 .features[FEAT_7_0_EBX] = 3229 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3230 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3231 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3232 CPUID_7_0_EBX_RTM, 3233 .features[FEAT_XSAVE] = 3234 CPUID_XSAVE_XSAVEOPT, 3235 .features[FEAT_6_EAX] = 3236 CPUID_6_EAX_ARAT, 3237 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3238 MSR_VMX_BASIC_TRUE_CTLS, 3239 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3240 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3241 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3242 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3243 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3244 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3245 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3246 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3247 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3248 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3249 .features[FEAT_VMX_EXIT_CTLS] = 3250 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3251 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3252 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3253 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3254 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3255 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3256 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3257 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3258 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3259 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3260 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3261 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3262 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3263 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3264 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3265 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3266 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3267 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3268 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3269 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3270 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3271 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3272 .features[FEAT_VMX_SECONDARY_CTLS] = 3273 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3274 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3275 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3276 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3277 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3278 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3279 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3280 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3281 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS, 3282 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3283 .xlevel = 0x80000008, 3284 .model_id = "Intel Core Processor (Haswell)", 3285 .versions = (X86CPUVersionDefinition[]) { 3286 { .version = 1 }, 3287 { 3288 .version = 2, 3289 .alias = "Haswell-noTSX", 3290 .props = (PropValue[]) { 3291 { "hle", "off" }, 3292 { "rtm", "off" }, 3293 { "stepping", "1" }, 3294 { "model-id", "Intel Core Processor (Haswell, no TSX)", }, 3295 { /* end of list */ } 3296 }, 3297 }, 3298 { 3299 .version = 3, 3300 .alias = "Haswell-IBRS", 3301 .props = (PropValue[]) { 3302 /* Restore TSX features removed by -v2 above */ 3303 { "hle", "on" }, 3304 { "rtm", "on" }, 3305 /* 3306 * Haswell and Haswell-IBRS had stepping=4 in 3307 * QEMU 4.0 and older 3308 */ 3309 { "stepping", "4" }, 3310 { "spec-ctrl", "on" }, 3311 { "model-id", 3312 "Intel Core Processor (Haswell, IBRS)" }, 3313 { /* end of list */ } 3314 } 3315 }, 3316 { 3317 .version = 4, 3318 .alias = "Haswell-noTSX-IBRS", 3319 .props = (PropValue[]) { 3320 { "hle", "off" }, 3321 { "rtm", "off" }, 3322 /* spec-ctrl was already enabled by -v3 above */ 3323 { "stepping", "1" }, 3324 { "model-id", 3325 "Intel Core Processor (Haswell, no TSX, IBRS)" }, 3326 { /* end of list */ } 3327 } 3328 }, 3329 { /* end of list */ } 3330 } 3331 }, 3332 { 3333 .name = "Broadwell", 3334 .level = 0xd, 3335 .vendor = CPUID_VENDOR_INTEL, 3336 .family = 6, 3337 .model = 61, 3338 .stepping = 2, 3339 .features[FEAT_1_EDX] = 3340 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3341 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3342 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3343 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3344 CPUID_DE | CPUID_FP87, 3345 .features[FEAT_1_ECX] = 3346 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3347 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3348 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3349 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3350 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3351 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3352 .features[FEAT_8000_0001_EDX] = 3353 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3354 CPUID_EXT2_SYSCALL, 3355 .features[FEAT_8000_0001_ECX] = 3356 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3357 .features[FEAT_7_0_EBX] = 3358 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3359 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3360 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3361 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3362 CPUID_7_0_EBX_SMAP, 3363 .features[FEAT_XSAVE] = 3364 CPUID_XSAVE_XSAVEOPT, 3365 .features[FEAT_6_EAX] = 3366 CPUID_6_EAX_ARAT, 3367 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3368 MSR_VMX_BASIC_TRUE_CTLS, 3369 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3370 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3371 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3372 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3373 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3374 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3375 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3376 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3377 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3378 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3379 .features[FEAT_VMX_EXIT_CTLS] = 3380 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3381 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3382 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3383 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3384 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3385 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3386 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3387 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3388 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3389 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3390 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3391 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3392 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3393 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3394 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3395 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3396 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3397 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3398 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3399 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3400 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3401 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3402 .features[FEAT_VMX_SECONDARY_CTLS] = 3403 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3404 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3405 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3406 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3407 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3408 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3409 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3410 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3411 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3412 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3413 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3414 .xlevel = 0x80000008, 3415 .model_id = "Intel Core Processor (Broadwell)", 3416 .versions = (X86CPUVersionDefinition[]) { 3417 { .version = 1 }, 3418 { 3419 .version = 2, 3420 .alias = "Broadwell-noTSX", 3421 .props = (PropValue[]) { 3422 { "hle", "off" }, 3423 { "rtm", "off" }, 3424 { "model-id", "Intel Core Processor (Broadwell, no TSX)", }, 3425 { /* end of list */ } 3426 }, 3427 }, 3428 { 3429 .version = 3, 3430 .alias = "Broadwell-IBRS", 3431 .props = (PropValue[]) { 3432 /* Restore TSX features removed by -v2 above */ 3433 { "hle", "on" }, 3434 { "rtm", "on" }, 3435 { "spec-ctrl", "on" }, 3436 { "model-id", 3437 "Intel Core Processor (Broadwell, IBRS)" }, 3438 { /* end of list */ } 3439 } 3440 }, 3441 { 3442 .version = 4, 3443 .alias = "Broadwell-noTSX-IBRS", 3444 .props = (PropValue[]) { 3445 { "hle", "off" }, 3446 { "rtm", "off" }, 3447 /* spec-ctrl was already enabled by -v3 above */ 3448 { "model-id", 3449 "Intel Core Processor (Broadwell, no TSX, IBRS)" }, 3450 { /* end of list */ } 3451 } 3452 }, 3453 { /* end of list */ } 3454 } 3455 }, 3456 { 3457 .name = "Skylake-Client", 3458 .level = 0xd, 3459 .vendor = CPUID_VENDOR_INTEL, 3460 .family = 6, 3461 .model = 94, 3462 .stepping = 3, 3463 .features[FEAT_1_EDX] = 3464 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3465 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3466 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3467 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3468 CPUID_DE | CPUID_FP87, 3469 .features[FEAT_1_ECX] = 3470 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3471 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3472 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3473 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3474 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3475 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3476 .features[FEAT_8000_0001_EDX] = 3477 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3478 CPUID_EXT2_SYSCALL, 3479 .features[FEAT_8000_0001_ECX] = 3480 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3481 .features[FEAT_7_0_EBX] = 3482 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3483 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3484 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3485 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3486 CPUID_7_0_EBX_SMAP, 3487 /* XSAVES is added in version 4 */ 3488 .features[FEAT_XSAVE] = 3489 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3490 CPUID_XSAVE_XGETBV1, 3491 .features[FEAT_6_EAX] = 3492 CPUID_6_EAX_ARAT, 3493 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3494 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3495 MSR_VMX_BASIC_TRUE_CTLS, 3496 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3497 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3498 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3499 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3500 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3501 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3502 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3503 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3504 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3505 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3506 .features[FEAT_VMX_EXIT_CTLS] = 3507 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3508 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3509 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3510 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3511 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3512 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3513 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3514 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3515 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3516 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 3517 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3518 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3519 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3520 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3521 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3522 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3523 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3524 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3525 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3526 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3527 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3528 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3529 .features[FEAT_VMX_SECONDARY_CTLS] = 3530 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3531 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3532 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3533 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3534 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3535 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3536 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3537 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3538 .xlevel = 0x80000008, 3539 .model_id = "Intel Core Processor (Skylake)", 3540 .versions = (X86CPUVersionDefinition[]) { 3541 { .version = 1 }, 3542 { 3543 .version = 2, 3544 .alias = "Skylake-Client-IBRS", 3545 .props = (PropValue[]) { 3546 { "spec-ctrl", "on" }, 3547 { "model-id", 3548 "Intel Core Processor (Skylake, IBRS)" }, 3549 { /* end of list */ } 3550 } 3551 }, 3552 { 3553 .version = 3, 3554 .alias = "Skylake-Client-noTSX-IBRS", 3555 .props = (PropValue[]) { 3556 { "hle", "off" }, 3557 { "rtm", "off" }, 3558 { "model-id", 3559 "Intel Core Processor (Skylake, IBRS, no TSX)" }, 3560 { /* end of list */ } 3561 } 3562 }, 3563 { 3564 .version = 4, 3565 .note = "IBRS, XSAVES, no TSX", 3566 .props = (PropValue[]) { 3567 { "xsaves", "on" }, 3568 { "vmx-xsaves", "on" }, 3569 { /* end of list */ } 3570 } 3571 }, 3572 { /* end of list */ } 3573 } 3574 }, 3575 { 3576 .name = "Skylake-Server", 3577 .level = 0xd, 3578 .vendor = CPUID_VENDOR_INTEL, 3579 .family = 6, 3580 .model = 85, 3581 .stepping = 4, 3582 .features[FEAT_1_EDX] = 3583 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3584 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3585 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3586 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3587 CPUID_DE | CPUID_FP87, 3588 .features[FEAT_1_ECX] = 3589 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3590 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3591 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3592 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3593 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3594 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3595 .features[FEAT_8000_0001_EDX] = 3596 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3597 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3598 .features[FEAT_8000_0001_ECX] = 3599 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3600 .features[FEAT_7_0_EBX] = 3601 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3602 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3603 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3604 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3605 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3606 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3607 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3608 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3609 .features[FEAT_7_0_ECX] = 3610 CPUID_7_0_ECX_PKU, 3611 /* XSAVES is added in version 5 */ 3612 .features[FEAT_XSAVE] = 3613 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3614 CPUID_XSAVE_XGETBV1, 3615 .features[FEAT_6_EAX] = 3616 CPUID_6_EAX_ARAT, 3617 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3618 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3619 MSR_VMX_BASIC_TRUE_CTLS, 3620 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3621 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3622 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3623 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3624 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3625 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3626 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3627 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3628 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3629 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3630 .features[FEAT_VMX_EXIT_CTLS] = 3631 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3632 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3633 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3634 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3635 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3636 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3637 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3638 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3639 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3640 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3641 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3642 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3643 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3644 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3645 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3646 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3647 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3648 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3649 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3650 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3651 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3652 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3653 .features[FEAT_VMX_SECONDARY_CTLS] = 3654 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3655 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3656 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3657 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3658 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3659 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3660 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3661 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3662 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3663 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3664 .xlevel = 0x80000008, 3665 .model_id = "Intel Xeon Processor (Skylake)", 3666 .versions = (X86CPUVersionDefinition[]) { 3667 { .version = 1 }, 3668 { 3669 .version = 2, 3670 .alias = "Skylake-Server-IBRS", 3671 .props = (PropValue[]) { 3672 /* clflushopt was not added to Skylake-Server-IBRS */ 3673 /* TODO: add -v3 including clflushopt */ 3674 { "clflushopt", "off" }, 3675 { "spec-ctrl", "on" }, 3676 { "model-id", 3677 "Intel Xeon Processor (Skylake, IBRS)" }, 3678 { /* end of list */ } 3679 } 3680 }, 3681 { 3682 .version = 3, 3683 .alias = "Skylake-Server-noTSX-IBRS", 3684 .props = (PropValue[]) { 3685 { "hle", "off" }, 3686 { "rtm", "off" }, 3687 { "model-id", 3688 "Intel Xeon Processor (Skylake, IBRS, no TSX)" }, 3689 { /* end of list */ } 3690 } 3691 }, 3692 { 3693 .version = 4, 3694 .props = (PropValue[]) { 3695 { "vmx-eptp-switching", "on" }, 3696 { /* end of list */ } 3697 } 3698 }, 3699 { 3700 .version = 5, 3701 .note = "IBRS, XSAVES, EPT switching, no TSX", 3702 .props = (PropValue[]) { 3703 { "xsaves", "on" }, 3704 { "vmx-xsaves", "on" }, 3705 { /* end of list */ } 3706 } 3707 }, 3708 { /* end of list */ } 3709 } 3710 }, 3711 { 3712 .name = "Cascadelake-Server", 3713 .level = 0xd, 3714 .vendor = CPUID_VENDOR_INTEL, 3715 .family = 6, 3716 .model = 85, 3717 .stepping = 6, 3718 .features[FEAT_1_EDX] = 3719 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3720 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3721 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3722 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3723 CPUID_DE | CPUID_FP87, 3724 .features[FEAT_1_ECX] = 3725 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3726 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3727 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3728 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3729 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3730 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3731 .features[FEAT_8000_0001_EDX] = 3732 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3733 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3734 .features[FEAT_8000_0001_ECX] = 3735 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3736 .features[FEAT_7_0_EBX] = 3737 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3738 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3739 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3740 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3741 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3742 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3743 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3744 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3745 .features[FEAT_7_0_ECX] = 3746 CPUID_7_0_ECX_PKU | 3747 CPUID_7_0_ECX_AVX512VNNI, 3748 .features[FEAT_7_0_EDX] = 3749 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 3750 /* XSAVES is added in version 5 */ 3751 .features[FEAT_XSAVE] = 3752 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3753 CPUID_XSAVE_XGETBV1, 3754 .features[FEAT_6_EAX] = 3755 CPUID_6_EAX_ARAT, 3756 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3757 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3758 MSR_VMX_BASIC_TRUE_CTLS, 3759 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3760 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3761 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3762 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3763 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3764 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3765 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3766 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3767 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3768 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3769 .features[FEAT_VMX_EXIT_CTLS] = 3770 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3771 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3772 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3773 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3774 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3775 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3776 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3777 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3778 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3779 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3780 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3781 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3782 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3783 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3784 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3785 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3786 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3787 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3788 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3789 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3790 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3791 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3792 .features[FEAT_VMX_SECONDARY_CTLS] = 3793 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3794 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3795 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3796 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3797 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3798 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3799 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3800 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3801 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3802 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3803 .xlevel = 0x80000008, 3804 .model_id = "Intel Xeon Processor (Cascadelake)", 3805 .versions = (X86CPUVersionDefinition[]) { 3806 { .version = 1 }, 3807 { .version = 2, 3808 .note = "ARCH_CAPABILITIES", 3809 .props = (PropValue[]) { 3810 { "arch-capabilities", "on" }, 3811 { "rdctl-no", "on" }, 3812 { "ibrs-all", "on" }, 3813 { "skip-l1dfl-vmentry", "on" }, 3814 { "mds-no", "on" }, 3815 { /* end of list */ } 3816 }, 3817 }, 3818 { .version = 3, 3819 .alias = "Cascadelake-Server-noTSX", 3820 .note = "ARCH_CAPABILITIES, no TSX", 3821 .props = (PropValue[]) { 3822 { "hle", "off" }, 3823 { "rtm", "off" }, 3824 { /* end of list */ } 3825 }, 3826 }, 3827 { .version = 4, 3828 .note = "ARCH_CAPABILITIES, no TSX", 3829 .props = (PropValue[]) { 3830 { "vmx-eptp-switching", "on" }, 3831 { /* end of list */ } 3832 }, 3833 }, 3834 { .version = 5, 3835 .note = "ARCH_CAPABILITIES, EPT switching, XSAVES, no TSX", 3836 .props = (PropValue[]) { 3837 { "xsaves", "on" }, 3838 { "vmx-xsaves", "on" }, 3839 { /* end of list */ } 3840 }, 3841 }, 3842 { /* end of list */ } 3843 } 3844 }, 3845 { 3846 .name = "Cooperlake", 3847 .level = 0xd, 3848 .vendor = CPUID_VENDOR_INTEL, 3849 .family = 6, 3850 .model = 85, 3851 .stepping = 10, 3852 .features[FEAT_1_EDX] = 3853 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3854 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3855 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3856 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3857 CPUID_DE | CPUID_FP87, 3858 .features[FEAT_1_ECX] = 3859 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3860 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3861 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3862 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3863 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3864 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3865 .features[FEAT_8000_0001_EDX] = 3866 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3867 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3868 .features[FEAT_8000_0001_ECX] = 3869 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3870 .features[FEAT_7_0_EBX] = 3871 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3872 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3873 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3874 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3875 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3876 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3877 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3878 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3879 .features[FEAT_7_0_ECX] = 3880 CPUID_7_0_ECX_PKU | 3881 CPUID_7_0_ECX_AVX512VNNI, 3882 .features[FEAT_7_0_EDX] = 3883 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_STIBP | 3884 CPUID_7_0_EDX_SPEC_CTRL_SSBD | CPUID_7_0_EDX_ARCH_CAPABILITIES, 3885 .features[FEAT_ARCH_CAPABILITIES] = 3886 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 3887 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 3888 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO, 3889 .features[FEAT_7_1_EAX] = 3890 CPUID_7_1_EAX_AVX512_BF16, 3891 /* XSAVES is added in version 2 */ 3892 .features[FEAT_XSAVE] = 3893 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3894 CPUID_XSAVE_XGETBV1, 3895 .features[FEAT_6_EAX] = 3896 CPUID_6_EAX_ARAT, 3897 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3898 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3899 MSR_VMX_BASIC_TRUE_CTLS, 3900 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3901 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3902 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3903 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3904 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3905 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3906 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3907 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3908 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3909 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3910 .features[FEAT_VMX_EXIT_CTLS] = 3911 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3912 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3913 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3914 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3915 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3916 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3917 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3918 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3919 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3920 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3921 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3922 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3923 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3924 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3925 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3926 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3927 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3928 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3929 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3930 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3931 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3932 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3933 .features[FEAT_VMX_SECONDARY_CTLS] = 3934 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3935 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3936 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3937 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3938 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3939 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3940 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3941 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3942 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3943 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3944 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3945 .xlevel = 0x80000008, 3946 .model_id = "Intel Xeon Processor (Cooperlake)", 3947 .versions = (X86CPUVersionDefinition[]) { 3948 { .version = 1 }, 3949 { .version = 2, 3950 .note = "XSAVES", 3951 .props = (PropValue[]) { 3952 { "xsaves", "on" }, 3953 { "vmx-xsaves", "on" }, 3954 { /* end of list */ } 3955 }, 3956 }, 3957 { /* end of list */ } 3958 } 3959 }, 3960 { 3961 .name = "Icelake-Server", 3962 .level = 0xd, 3963 .vendor = CPUID_VENDOR_INTEL, 3964 .family = 6, 3965 .model = 134, 3966 .stepping = 0, 3967 .features[FEAT_1_EDX] = 3968 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3969 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3970 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3971 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3972 CPUID_DE | CPUID_FP87, 3973 .features[FEAT_1_ECX] = 3974 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3975 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3976 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3977 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3978 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3979 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3980 .features[FEAT_8000_0001_EDX] = 3981 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3982 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3983 .features[FEAT_8000_0001_ECX] = 3984 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3985 .features[FEAT_8000_0008_EBX] = 3986 CPUID_8000_0008_EBX_WBNOINVD, 3987 .features[FEAT_7_0_EBX] = 3988 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3989 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3990 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3991 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3992 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3993 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3994 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3995 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3996 .features[FEAT_7_0_ECX] = 3997 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 3998 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 3999 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4000 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 4001 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57, 4002 .features[FEAT_7_0_EDX] = 4003 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4004 /* XSAVES is added in version 5 */ 4005 .features[FEAT_XSAVE] = 4006 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4007 CPUID_XSAVE_XGETBV1, 4008 .features[FEAT_6_EAX] = 4009 CPUID_6_EAX_ARAT, 4010 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 4011 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 4012 MSR_VMX_BASIC_TRUE_CTLS, 4013 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 4014 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 4015 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 4016 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 4017 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 4018 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 4019 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4020 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4021 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4022 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 4023 .features[FEAT_VMX_EXIT_CTLS] = 4024 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4025 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4026 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 4027 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4028 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4029 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 4030 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 4031 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 4032 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 4033 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 4034 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4035 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4036 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4037 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4038 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4039 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 4040 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 4041 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 4042 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 4043 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4044 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4045 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4046 .features[FEAT_VMX_SECONDARY_CTLS] = 4047 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4048 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 4049 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 4050 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4051 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4052 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4053 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4054 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4055 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS, 4056 .xlevel = 0x80000008, 4057 .model_id = "Intel Xeon Processor (Icelake)", 4058 .versions = (X86CPUVersionDefinition[]) { 4059 { .version = 1 }, 4060 { 4061 .version = 2, 4062 .note = "no TSX", 4063 .alias = "Icelake-Server-noTSX", 4064 .props = (PropValue[]) { 4065 { "hle", "off" }, 4066 { "rtm", "off" }, 4067 { /* end of list */ } 4068 }, 4069 }, 4070 { 4071 .version = 3, 4072 .props = (PropValue[]) { 4073 { "arch-capabilities", "on" }, 4074 { "rdctl-no", "on" }, 4075 { "ibrs-all", "on" }, 4076 { "skip-l1dfl-vmentry", "on" }, 4077 { "mds-no", "on" }, 4078 { "pschange-mc-no", "on" }, 4079 { "taa-no", "on" }, 4080 { /* end of list */ } 4081 }, 4082 }, 4083 { 4084 .version = 4, 4085 .props = (PropValue[]) { 4086 { "sha-ni", "on" }, 4087 { "avx512ifma", "on" }, 4088 { "rdpid", "on" }, 4089 { "fsrm", "on" }, 4090 { "vmx-rdseed-exit", "on" }, 4091 { "vmx-pml", "on" }, 4092 { "vmx-eptp-switching", "on" }, 4093 { "model", "106" }, 4094 { /* end of list */ } 4095 }, 4096 }, 4097 { 4098 .version = 5, 4099 .note = "XSAVES", 4100 .props = (PropValue[]) { 4101 { "xsaves", "on" }, 4102 { "vmx-xsaves", "on" }, 4103 { /* end of list */ } 4104 }, 4105 }, 4106 { 4107 .version = 6, 4108 .note = "5-level EPT", 4109 .props = (PropValue[]) { 4110 { "vmx-page-walk-5", "on" }, 4111 { /* end of list */ } 4112 }, 4113 }, 4114 { 4115 .version = 7, 4116 .note = "TSX, taa-no", 4117 .props = (PropValue[]) { 4118 /* Restore TSX features removed by -v2 above */ 4119 { "hle", "on" }, 4120 { "rtm", "on" }, 4121 { /* end of list */ } 4122 }, 4123 }, 4124 { /* end of list */ } 4125 } 4126 }, 4127 { 4128 .name = "SapphireRapids", 4129 .level = 0x20, 4130 .vendor = CPUID_VENDOR_INTEL, 4131 .family = 6, 4132 .model = 143, 4133 .stepping = 4, 4134 /* 4135 * please keep the ascending order so that we can have a clear view of 4136 * bit position of each feature. 4137 */ 4138 .features[FEAT_1_EDX] = 4139 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4140 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4141 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4142 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4143 CPUID_SSE | CPUID_SSE2, 4144 .features[FEAT_1_ECX] = 4145 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 4146 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 4147 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4148 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 4149 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4150 .features[FEAT_8000_0001_EDX] = 4151 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4152 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4153 .features[FEAT_8000_0001_ECX] = 4154 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 4155 .features[FEAT_8000_0008_EBX] = 4156 CPUID_8000_0008_EBX_WBNOINVD, 4157 .features[FEAT_7_0_EBX] = 4158 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_HLE | 4159 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | 4160 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RTM | 4161 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 4162 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | 4163 CPUID_7_0_EBX_AVX512IFMA | CPUID_7_0_EBX_CLFLUSHOPT | 4164 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | 4165 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, 4166 .features[FEAT_7_0_ECX] = 4167 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 4168 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 4169 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4170 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 4171 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | 4172 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT, 4173 .features[FEAT_7_0_EDX] = 4174 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 4175 CPUID_7_0_EDX_TSX_LDTRK | CPUID_7_0_EDX_AMX_BF16 | 4176 CPUID_7_0_EDX_AVX512_FP16 | CPUID_7_0_EDX_AMX_TILE | 4177 CPUID_7_0_EDX_AMX_INT8 | CPUID_7_0_EDX_SPEC_CTRL | 4178 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4179 .features[FEAT_ARCH_CAPABILITIES] = 4180 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 4181 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 4182 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO, 4183 .features[FEAT_XSAVE] = 4184 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4185 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES | CPUID_D_1_EAX_XFD, 4186 .features[FEAT_6_EAX] = 4187 CPUID_6_EAX_ARAT, 4188 .features[FEAT_7_1_EAX] = 4189 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_AVX512_BF16 | 4190 CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC, 4191 .features[FEAT_VMX_BASIC] = 4192 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 4193 .features[FEAT_VMX_ENTRY_CTLS] = 4194 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 4195 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 4196 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 4197 .features[FEAT_VMX_EPT_VPID_CAPS] = 4198 MSR_VMX_EPT_EXECONLY | 4199 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_PAGE_WALK_LENGTH_5 | 4200 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 4201 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 4202 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4203 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4204 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 4205 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4206 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 4207 .features[FEAT_VMX_EXIT_CTLS] = 4208 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4209 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4210 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 4211 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4212 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4213 .features[FEAT_VMX_MISC] = 4214 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 4215 MSR_VMX_MISC_VMWRITE_VMEXIT, 4216 .features[FEAT_VMX_PINBASED_CTLS] = 4217 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 4218 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 4219 VMX_PIN_BASED_POSTED_INTR, 4220 .features[FEAT_VMX_PROCBASED_CTLS] = 4221 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4222 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4223 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4224 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4225 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4226 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4227 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 4228 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 4229 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4230 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 4231 VMX_CPU_BASED_PAUSE_EXITING | 4232 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4233 .features[FEAT_VMX_SECONDARY_CTLS] = 4234 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4235 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 4236 VMX_SECONDARY_EXEC_RDTSCP | 4237 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4238 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 4239 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4240 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4241 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4242 VMX_SECONDARY_EXEC_RDRAND_EXITING | 4243 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4244 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4245 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 4246 VMX_SECONDARY_EXEC_XSAVES, 4247 .features[FEAT_VMX_VMFUNC] = 4248 MSR_VMX_VMFUNC_EPT_SWITCHING, 4249 .xlevel = 0x80000008, 4250 .model_id = "Intel Xeon Processor (SapphireRapids)", 4251 .versions = (X86CPUVersionDefinition[]) { 4252 { .version = 1 }, 4253 { 4254 .version = 2, 4255 .props = (PropValue[]) { 4256 { "sbdr-ssdp-no", "on" }, 4257 { "fbsdp-no", "on" }, 4258 { "psdp-no", "on" }, 4259 { /* end of list */ } 4260 } 4261 }, 4262 { 4263 .version = 3, 4264 .props = (PropValue[]) { 4265 { "ss", "on" }, 4266 { "tsc-adjust", "on" }, 4267 { "cldemote", "on" }, 4268 { "movdiri", "on" }, 4269 { "movdir64b", "on" }, 4270 { /* end of list */ } 4271 } 4272 }, 4273 { /* end of list */ } 4274 } 4275 }, 4276 { 4277 .name = "GraniteRapids", 4278 .level = 0x20, 4279 .vendor = CPUID_VENDOR_INTEL, 4280 .family = 6, 4281 .model = 173, 4282 .stepping = 0, 4283 /* 4284 * please keep the ascending order so that we can have a clear view of 4285 * bit position of each feature. 4286 */ 4287 .features[FEAT_1_EDX] = 4288 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4289 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4290 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4291 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4292 CPUID_SSE | CPUID_SSE2, 4293 .features[FEAT_1_ECX] = 4294 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 4295 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 4296 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4297 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 4298 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4299 .features[FEAT_8000_0001_EDX] = 4300 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4301 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4302 .features[FEAT_8000_0001_ECX] = 4303 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 4304 .features[FEAT_8000_0008_EBX] = 4305 CPUID_8000_0008_EBX_WBNOINVD, 4306 .features[FEAT_7_0_EBX] = 4307 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_HLE | 4308 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | 4309 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RTM | 4310 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 4311 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | 4312 CPUID_7_0_EBX_AVX512IFMA | CPUID_7_0_EBX_CLFLUSHOPT | 4313 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | 4314 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, 4315 .features[FEAT_7_0_ECX] = 4316 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 4317 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 4318 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4319 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 4320 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | 4321 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT, 4322 .features[FEAT_7_0_EDX] = 4323 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 4324 CPUID_7_0_EDX_TSX_LDTRK | CPUID_7_0_EDX_AMX_BF16 | 4325 CPUID_7_0_EDX_AVX512_FP16 | CPUID_7_0_EDX_AMX_TILE | 4326 CPUID_7_0_EDX_AMX_INT8 | CPUID_7_0_EDX_SPEC_CTRL | 4327 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4328 .features[FEAT_ARCH_CAPABILITIES] = 4329 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 4330 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 4331 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO | 4332 MSR_ARCH_CAP_SBDR_SSDP_NO | MSR_ARCH_CAP_FBSDP_NO | 4333 MSR_ARCH_CAP_PSDP_NO | MSR_ARCH_CAP_PBRSB_NO, 4334 .features[FEAT_XSAVE] = 4335 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4336 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES | CPUID_D_1_EAX_XFD, 4337 .features[FEAT_6_EAX] = 4338 CPUID_6_EAX_ARAT, 4339 .features[FEAT_7_1_EAX] = 4340 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_AVX512_BF16 | 4341 CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC | 4342 CPUID_7_1_EAX_AMX_FP16, 4343 .features[FEAT_7_1_EDX] = 4344 CPUID_7_1_EDX_PREFETCHITI, 4345 .features[FEAT_7_2_EDX] = 4346 CPUID_7_2_EDX_MCDT_NO, 4347 .features[FEAT_VMX_BASIC] = 4348 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 4349 .features[FEAT_VMX_ENTRY_CTLS] = 4350 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 4351 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 4352 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 4353 .features[FEAT_VMX_EPT_VPID_CAPS] = 4354 MSR_VMX_EPT_EXECONLY | 4355 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_PAGE_WALK_LENGTH_5 | 4356 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 4357 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 4358 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4359 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4360 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 4361 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4362 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 4363 .features[FEAT_VMX_EXIT_CTLS] = 4364 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4365 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4366 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 4367 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4368 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4369 .features[FEAT_VMX_MISC] = 4370 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 4371 MSR_VMX_MISC_VMWRITE_VMEXIT, 4372 .features[FEAT_VMX_PINBASED_CTLS] = 4373 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 4374 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 4375 VMX_PIN_BASED_POSTED_INTR, 4376 .features[FEAT_VMX_PROCBASED_CTLS] = 4377 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4378 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4379 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4380 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4381 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4382 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4383 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 4384 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 4385 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4386 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 4387 VMX_CPU_BASED_PAUSE_EXITING | 4388 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4389 .features[FEAT_VMX_SECONDARY_CTLS] = 4390 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4391 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 4392 VMX_SECONDARY_EXEC_RDTSCP | 4393 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4394 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 4395 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4396 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4397 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4398 VMX_SECONDARY_EXEC_RDRAND_EXITING | 4399 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4400 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4401 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 4402 VMX_SECONDARY_EXEC_XSAVES, 4403 .features[FEAT_VMX_VMFUNC] = 4404 MSR_VMX_VMFUNC_EPT_SWITCHING, 4405 .xlevel = 0x80000008, 4406 .model_id = "Intel Xeon Processor (GraniteRapids)", 4407 .versions = (X86CPUVersionDefinition[]) { 4408 { .version = 1 }, 4409 { 4410 .version = 2, 4411 .props = (PropValue[]) { 4412 { "ss", "on" }, 4413 { "tsc-adjust", "on" }, 4414 { "cldemote", "on" }, 4415 { "movdiri", "on" }, 4416 { "movdir64b", "on" }, 4417 { "avx10", "on" }, 4418 { "avx10-128", "on" }, 4419 { "avx10-256", "on" }, 4420 { "avx10-512", "on" }, 4421 { "avx10-version", "1" }, 4422 { "stepping", "1" }, 4423 { /* end of list */ } 4424 } 4425 }, 4426 { /* end of list */ }, 4427 }, 4428 }, 4429 { 4430 .name = "SierraForest", 4431 .level = 0x23, 4432 .vendor = CPUID_VENDOR_INTEL, 4433 .family = 6, 4434 .model = 175, 4435 .stepping = 0, 4436 /* 4437 * please keep the ascending order so that we can have a clear view of 4438 * bit position of each feature. 4439 */ 4440 .features[FEAT_1_EDX] = 4441 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4442 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4443 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4444 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4445 CPUID_SSE | CPUID_SSE2, 4446 .features[FEAT_1_ECX] = 4447 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 4448 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 4449 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4450 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 4451 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4452 .features[FEAT_8000_0001_EDX] = 4453 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4454 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4455 .features[FEAT_8000_0001_ECX] = 4456 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 4457 .features[FEAT_8000_0008_EBX] = 4458 CPUID_8000_0008_EBX_WBNOINVD, 4459 .features[FEAT_7_0_EBX] = 4460 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4461 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 4462 CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 4463 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB | 4464 CPUID_7_0_EBX_SHA_NI, 4465 .features[FEAT_7_0_ECX] = 4466 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_GFNI | 4467 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4468 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT, 4469 .features[FEAT_7_0_EDX] = 4470 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 4471 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES | 4472 CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4473 .features[FEAT_ARCH_CAPABILITIES] = 4474 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 4475 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 4476 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_SBDR_SSDP_NO | 4477 MSR_ARCH_CAP_FBSDP_NO | MSR_ARCH_CAP_PSDP_NO | 4478 MSR_ARCH_CAP_PBRSB_NO, 4479 .features[FEAT_XSAVE] = 4480 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4481 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 4482 .features[FEAT_6_EAX] = 4483 CPUID_6_EAX_ARAT, 4484 .features[FEAT_7_1_EAX] = 4485 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_CMPCCXADD | 4486 CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_AVX_IFMA, 4487 .features[FEAT_7_1_EDX] = 4488 CPUID_7_1_EDX_AVX_VNNI_INT8 | CPUID_7_1_EDX_AVX_NE_CONVERT, 4489 .features[FEAT_7_2_EDX] = 4490 CPUID_7_2_EDX_MCDT_NO, 4491 .features[FEAT_VMX_BASIC] = 4492 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 4493 .features[FEAT_VMX_ENTRY_CTLS] = 4494 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 4495 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 4496 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 4497 .features[FEAT_VMX_EPT_VPID_CAPS] = 4498 MSR_VMX_EPT_EXECONLY | MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | 4499 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 4500 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 4501 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4502 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4503 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 4504 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4505 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 4506 .features[FEAT_VMX_EXIT_CTLS] = 4507 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4508 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4509 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 4510 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4511 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4512 .features[FEAT_VMX_MISC] = 4513 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 4514 MSR_VMX_MISC_VMWRITE_VMEXIT, 4515 .features[FEAT_VMX_PINBASED_CTLS] = 4516 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 4517 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 4518 VMX_PIN_BASED_POSTED_INTR, 4519 .features[FEAT_VMX_PROCBASED_CTLS] = 4520 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4521 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4522 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4523 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4524 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4525 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4526 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 4527 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 4528 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4529 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 4530 VMX_CPU_BASED_PAUSE_EXITING | 4531 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4532 .features[FEAT_VMX_SECONDARY_CTLS] = 4533 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4534 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 4535 VMX_SECONDARY_EXEC_RDTSCP | 4536 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4537 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 4538 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4539 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4540 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4541 VMX_SECONDARY_EXEC_RDRAND_EXITING | 4542 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4543 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4544 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 4545 VMX_SECONDARY_EXEC_XSAVES, 4546 .features[FEAT_VMX_VMFUNC] = 4547 MSR_VMX_VMFUNC_EPT_SWITCHING, 4548 .xlevel = 0x80000008, 4549 .model_id = "Intel Xeon Processor (SierraForest)", 4550 .versions = (X86CPUVersionDefinition[]) { 4551 { .version = 1 }, 4552 { /* end of list */ }, 4553 }, 4554 }, 4555 { 4556 .name = "Denverton", 4557 .level = 21, 4558 .vendor = CPUID_VENDOR_INTEL, 4559 .family = 6, 4560 .model = 95, 4561 .stepping = 1, 4562 .features[FEAT_1_EDX] = 4563 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4564 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4565 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4566 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4567 CPUID_SSE | CPUID_SSE2, 4568 .features[FEAT_1_ECX] = 4569 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR | 4570 CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_SSE41 | 4571 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4572 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | 4573 CPUID_EXT_AES | CPUID_EXT_XSAVE | CPUID_EXT_RDRAND, 4574 .features[FEAT_8000_0001_EDX] = 4575 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4576 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4577 .features[FEAT_8000_0001_ECX] = 4578 CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 4579 .features[FEAT_7_0_EBX] = 4580 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_ERMS | 4581 CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_SMAP | 4582 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_SHA_NI, 4583 .features[FEAT_7_0_EDX] = 4584 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES | 4585 CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4586 /* XSAVES is added in version 3 */ 4587 .features[FEAT_XSAVE] = 4588 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | CPUID_XSAVE_XGETBV1, 4589 .features[FEAT_6_EAX] = 4590 CPUID_6_EAX_ARAT, 4591 .features[FEAT_ARCH_CAPABILITIES] = 4592 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY, 4593 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 4594 MSR_VMX_BASIC_TRUE_CTLS, 4595 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 4596 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 4597 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 4598 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 4599 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 4600 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 4601 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4602 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4603 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4604 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 4605 .features[FEAT_VMX_EXIT_CTLS] = 4606 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4607 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4608 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 4609 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4610 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4611 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 4612 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 4613 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 4614 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 4615 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 4616 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4617 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4618 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4619 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4620 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4621 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 4622 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 4623 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 4624 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 4625 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4626 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4627 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4628 .features[FEAT_VMX_SECONDARY_CTLS] = 4629 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4630 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 4631 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 4632 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4633 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4634 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4635 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4636 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4637 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4638 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 4639 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 4640 .xlevel = 0x80000008, 4641 .model_id = "Intel Atom Processor (Denverton)", 4642 .versions = (X86CPUVersionDefinition[]) { 4643 { .version = 1 }, 4644 { 4645 .version = 2, 4646 .note = "no MPX, no MONITOR", 4647 .props = (PropValue[]) { 4648 { "monitor", "off" }, 4649 { "mpx", "off" }, 4650 { /* end of list */ }, 4651 }, 4652 }, 4653 { 4654 .version = 3, 4655 .note = "XSAVES, no MPX, no MONITOR", 4656 .props = (PropValue[]) { 4657 { "xsaves", "on" }, 4658 { "vmx-xsaves", "on" }, 4659 { /* end of list */ }, 4660 }, 4661 }, 4662 { /* end of list */ }, 4663 }, 4664 }, 4665 { 4666 .name = "Snowridge", 4667 .level = 27, 4668 .vendor = CPUID_VENDOR_INTEL, 4669 .family = 6, 4670 .model = 134, 4671 .stepping = 1, 4672 .features[FEAT_1_EDX] = 4673 /* missing: CPUID_PN CPUID_IA64 */ 4674 /* missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 4675 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | 4676 CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_MCE | 4677 CPUID_CX8 | CPUID_APIC | CPUID_SEP | 4678 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4679 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | 4680 CPUID_MMX | 4681 CPUID_FXSR | CPUID_SSE | CPUID_SSE2, 4682 .features[FEAT_1_ECX] = 4683 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR | 4684 CPUID_EXT_SSSE3 | 4685 CPUID_EXT_CX16 | 4686 CPUID_EXT_SSE41 | 4687 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4688 CPUID_EXT_POPCNT | 4689 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | CPUID_EXT_XSAVE | 4690 CPUID_EXT_RDRAND, 4691 .features[FEAT_8000_0001_EDX] = 4692 CPUID_EXT2_SYSCALL | 4693 CPUID_EXT2_NX | 4694 CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 4695 CPUID_EXT2_LM, 4696 .features[FEAT_8000_0001_ECX] = 4697 CPUID_EXT3_LAHF_LM | 4698 CPUID_EXT3_3DNOWPREFETCH, 4699 .features[FEAT_7_0_EBX] = 4700 CPUID_7_0_EBX_FSGSBASE | 4701 CPUID_7_0_EBX_SMEP | 4702 CPUID_7_0_EBX_ERMS | 4703 CPUID_7_0_EBX_MPX | /* missing bits 13, 15 */ 4704 CPUID_7_0_EBX_RDSEED | 4705 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 4706 CPUID_7_0_EBX_CLWB | 4707 CPUID_7_0_EBX_SHA_NI, 4708 .features[FEAT_7_0_ECX] = 4709 CPUID_7_0_ECX_UMIP | 4710 /* missing bit 5 */ 4711 CPUID_7_0_ECX_GFNI | 4712 CPUID_7_0_ECX_MOVDIRI | CPUID_7_0_ECX_CLDEMOTE | 4713 CPUID_7_0_ECX_MOVDIR64B, 4714 .features[FEAT_7_0_EDX] = 4715 CPUID_7_0_EDX_SPEC_CTRL | 4716 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD | 4717 CPUID_7_0_EDX_CORE_CAPABILITY, 4718 .features[FEAT_CORE_CAPABILITY] = 4719 MSR_CORE_CAP_SPLIT_LOCK_DETECT, 4720 /* XSAVES is added in version 3 */ 4721 .features[FEAT_XSAVE] = 4722 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4723 CPUID_XSAVE_XGETBV1, 4724 .features[FEAT_6_EAX] = 4725 CPUID_6_EAX_ARAT, 4726 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 4727 MSR_VMX_BASIC_TRUE_CTLS, 4728 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 4729 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 4730 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 4731 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 4732 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 4733 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 4734 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4735 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4736 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4737 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 4738 .features[FEAT_VMX_EXIT_CTLS] = 4739 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4740 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4741 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 4742 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4743 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4744 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 4745 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 4746 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 4747 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 4748 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 4749 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4750 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4751 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4752 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4753 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4754 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 4755 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 4756 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 4757 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 4758 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4759 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4760 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4761 .features[FEAT_VMX_SECONDARY_CTLS] = 4762 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4763 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 4764 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 4765 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4766 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4767 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4768 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4769 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4770 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4771 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 4772 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 4773 .xlevel = 0x80000008, 4774 .model_id = "Intel Atom Processor (SnowRidge)", 4775 .versions = (X86CPUVersionDefinition[]) { 4776 { .version = 1 }, 4777 { 4778 .version = 2, 4779 .props = (PropValue[]) { 4780 { "mpx", "off" }, 4781 { "model-id", "Intel Atom Processor (Snowridge, no MPX)" }, 4782 { /* end of list */ }, 4783 }, 4784 }, 4785 { 4786 .version = 3, 4787 .note = "XSAVES, no MPX", 4788 .props = (PropValue[]) { 4789 { "xsaves", "on" }, 4790 { "vmx-xsaves", "on" }, 4791 { /* end of list */ }, 4792 }, 4793 }, 4794 { 4795 .version = 4, 4796 .note = "no split lock detect, no core-capability", 4797 .props = (PropValue[]) { 4798 { "split-lock-detect", "off" }, 4799 { "core-capability", "off" }, 4800 { /* end of list */ }, 4801 }, 4802 }, 4803 { /* end of list */ }, 4804 }, 4805 }, 4806 { 4807 .name = "KnightsMill", 4808 .level = 0xd, 4809 .vendor = CPUID_VENDOR_INTEL, 4810 .family = 6, 4811 .model = 133, 4812 .stepping = 0, 4813 .features[FEAT_1_EDX] = 4814 CPUID_VME | CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | 4815 CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | 4816 CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | 4817 CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | 4818 CPUID_PSE | CPUID_DE | CPUID_FP87, 4819 .features[FEAT_1_ECX] = 4820 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 4821 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 4822 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 4823 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 4824 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 4825 CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4826 .features[FEAT_8000_0001_EDX] = 4827 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 4828 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 4829 .features[FEAT_8000_0001_ECX] = 4830 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 4831 .features[FEAT_7_0_EBX] = 4832 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4833 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 4834 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_AVX512F | 4835 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_AVX512PF | 4836 CPUID_7_0_EBX_AVX512ER, 4837 .features[FEAT_7_0_ECX] = 4838 CPUID_7_0_ECX_AVX512_VPOPCNTDQ, 4839 .features[FEAT_7_0_EDX] = 4840 CPUID_7_0_EDX_AVX512_4VNNIW | CPUID_7_0_EDX_AVX512_4FMAPS, 4841 .features[FEAT_XSAVE] = 4842 CPUID_XSAVE_XSAVEOPT, 4843 .features[FEAT_6_EAX] = 4844 CPUID_6_EAX_ARAT, 4845 .xlevel = 0x80000008, 4846 .model_id = "Intel Xeon Phi Processor (Knights Mill)", 4847 }, 4848 { 4849 .name = "Opteron_G1", 4850 .level = 5, 4851 .vendor = CPUID_VENDOR_AMD, 4852 .family = 15, 4853 .model = 6, 4854 .stepping = 1, 4855 .features[FEAT_1_EDX] = 4856 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4857 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4858 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4859 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4860 CPUID_DE | CPUID_FP87, 4861 .features[FEAT_1_ECX] = 4862 CPUID_EXT_SSE3, 4863 .features[FEAT_8000_0001_EDX] = 4864 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 4865 .xlevel = 0x80000008, 4866 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)", 4867 }, 4868 { 4869 .name = "Opteron_G2", 4870 .level = 5, 4871 .vendor = CPUID_VENDOR_AMD, 4872 .family = 15, 4873 .model = 6, 4874 .stepping = 1, 4875 .features[FEAT_1_EDX] = 4876 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4877 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4878 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4879 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4880 CPUID_DE | CPUID_FP87, 4881 .features[FEAT_1_ECX] = 4882 CPUID_EXT_CX16 | CPUID_EXT_SSE3, 4883 .features[FEAT_8000_0001_EDX] = 4884 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 4885 .features[FEAT_8000_0001_ECX] = 4886 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, 4887 .xlevel = 0x80000008, 4888 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)", 4889 }, 4890 { 4891 .name = "Opteron_G3", 4892 .level = 5, 4893 .vendor = CPUID_VENDOR_AMD, 4894 .family = 16, 4895 .model = 2, 4896 .stepping = 3, 4897 .features[FEAT_1_EDX] = 4898 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4899 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4900 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4901 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4902 CPUID_DE | CPUID_FP87, 4903 .features[FEAT_1_ECX] = 4904 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR | 4905 CPUID_EXT_SSE3, 4906 .features[FEAT_8000_0001_EDX] = 4907 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL | 4908 CPUID_EXT2_RDTSCP, 4909 .features[FEAT_8000_0001_ECX] = 4910 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | 4911 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, 4912 .xlevel = 0x80000008, 4913 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)", 4914 }, 4915 { 4916 .name = "Opteron_G4", 4917 .level = 0xd, 4918 .vendor = CPUID_VENDOR_AMD, 4919 .family = 21, 4920 .model = 1, 4921 .stepping = 2, 4922 .features[FEAT_1_EDX] = 4923 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4924 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4925 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4926 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4927 CPUID_DE | CPUID_FP87, 4928 .features[FEAT_1_ECX] = 4929 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 4930 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 4931 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 4932 CPUID_EXT_SSE3, 4933 .features[FEAT_8000_0001_EDX] = 4934 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX | 4935 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP, 4936 .features[FEAT_8000_0001_ECX] = 4937 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP | 4938 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | 4939 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | 4940 CPUID_EXT3_LAHF_LM, 4941 .features[FEAT_SVM] = 4942 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 4943 /* no xsaveopt! */ 4944 .xlevel = 0x8000001A, 4945 .model_id = "AMD Opteron 62xx class CPU", 4946 }, 4947 { 4948 .name = "Opteron_G5", 4949 .level = 0xd, 4950 .vendor = CPUID_VENDOR_AMD, 4951 .family = 21, 4952 .model = 2, 4953 .stepping = 0, 4954 .features[FEAT_1_EDX] = 4955 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4956 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4957 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4958 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4959 CPUID_DE | CPUID_FP87, 4960 .features[FEAT_1_ECX] = 4961 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE | 4962 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | 4963 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA | 4964 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 4965 .features[FEAT_8000_0001_EDX] = 4966 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX | 4967 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP, 4968 .features[FEAT_8000_0001_ECX] = 4969 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP | 4970 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | 4971 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | 4972 CPUID_EXT3_LAHF_LM, 4973 .features[FEAT_SVM] = 4974 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 4975 /* no xsaveopt! */ 4976 .xlevel = 0x8000001A, 4977 .model_id = "AMD Opteron 63xx class CPU", 4978 }, 4979 { 4980 .name = "EPYC", 4981 .level = 0xd, 4982 .vendor = CPUID_VENDOR_AMD, 4983 .family = 23, 4984 .model = 1, 4985 .stepping = 2, 4986 .features[FEAT_1_EDX] = 4987 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 4988 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 4989 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 4990 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 4991 CPUID_VME | CPUID_FP87, 4992 .features[FEAT_1_ECX] = 4993 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 4994 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 4995 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 4996 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 4997 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 4998 .features[FEAT_8000_0001_EDX] = 4999 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5000 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5001 CPUID_EXT2_SYSCALL, 5002 .features[FEAT_8000_0001_ECX] = 5003 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5004 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5005 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5006 CPUID_EXT3_TOPOEXT, 5007 .features[FEAT_7_0_EBX] = 5008 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5009 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 5010 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 5011 CPUID_7_0_EBX_SHA_NI, 5012 .features[FEAT_XSAVE] = 5013 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5014 CPUID_XSAVE_XGETBV1, 5015 .features[FEAT_6_EAX] = 5016 CPUID_6_EAX_ARAT, 5017 .features[FEAT_SVM] = 5018 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 5019 .xlevel = 0x8000001E, 5020 .model_id = "AMD EPYC Processor", 5021 .cache_info = &epyc_cache_info, 5022 .versions = (X86CPUVersionDefinition[]) { 5023 { .version = 1 }, 5024 { 5025 .version = 2, 5026 .alias = "EPYC-IBPB", 5027 .props = (PropValue[]) { 5028 { "ibpb", "on" }, 5029 { "model-id", 5030 "AMD EPYC Processor (with IBPB)" }, 5031 { /* end of list */ } 5032 } 5033 }, 5034 { 5035 .version = 3, 5036 .props = (PropValue[]) { 5037 { "ibpb", "on" }, 5038 { "perfctr-core", "on" }, 5039 { "clzero", "on" }, 5040 { "xsaveerptr", "on" }, 5041 { "xsaves", "on" }, 5042 { "model-id", 5043 "AMD EPYC Processor" }, 5044 { /* end of list */ } 5045 } 5046 }, 5047 { 5048 .version = 4, 5049 .props = (PropValue[]) { 5050 { "model-id", 5051 "AMD EPYC-v4 Processor" }, 5052 { /* end of list */ } 5053 }, 5054 .cache_info = &epyc_v4_cache_info 5055 }, 5056 { /* end of list */ } 5057 } 5058 }, 5059 { 5060 .name = "Dhyana", 5061 .level = 0xd, 5062 .vendor = CPUID_VENDOR_HYGON, 5063 .family = 24, 5064 .model = 0, 5065 .stepping = 1, 5066 .features[FEAT_1_EDX] = 5067 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 5068 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 5069 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 5070 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 5071 CPUID_VME | CPUID_FP87, 5072 .features[FEAT_1_ECX] = 5073 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5074 CPUID_EXT_XSAVE | CPUID_EXT_POPCNT | 5075 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5076 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 5077 CPUID_EXT_MONITOR | CPUID_EXT_SSE3, 5078 .features[FEAT_8000_0001_EDX] = 5079 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5080 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5081 CPUID_EXT2_SYSCALL, 5082 .features[FEAT_8000_0001_ECX] = 5083 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5084 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5085 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5086 CPUID_EXT3_TOPOEXT, 5087 .features[FEAT_8000_0008_EBX] = 5088 CPUID_8000_0008_EBX_IBPB, 5089 .features[FEAT_7_0_EBX] = 5090 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5091 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 5092 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT, 5093 /* XSAVES is added in version 2 */ 5094 .features[FEAT_XSAVE] = 5095 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5096 CPUID_XSAVE_XGETBV1, 5097 .features[FEAT_6_EAX] = 5098 CPUID_6_EAX_ARAT, 5099 .features[FEAT_SVM] = 5100 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 5101 .xlevel = 0x8000001E, 5102 .model_id = "Hygon Dhyana Processor", 5103 .cache_info = &epyc_cache_info, 5104 .versions = (X86CPUVersionDefinition[]) { 5105 { .version = 1 }, 5106 { .version = 2, 5107 .note = "XSAVES", 5108 .props = (PropValue[]) { 5109 { "xsaves", "on" }, 5110 { /* end of list */ } 5111 }, 5112 }, 5113 { /* end of list */ } 5114 } 5115 }, 5116 { 5117 .name = "EPYC-Rome", 5118 .level = 0xd, 5119 .vendor = CPUID_VENDOR_AMD, 5120 .family = 23, 5121 .model = 49, 5122 .stepping = 0, 5123 .features[FEAT_1_EDX] = 5124 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 5125 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 5126 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 5127 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 5128 CPUID_VME | CPUID_FP87, 5129 .features[FEAT_1_ECX] = 5130 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5131 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 5132 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5133 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 5134 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 5135 .features[FEAT_8000_0001_EDX] = 5136 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5137 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5138 CPUID_EXT2_SYSCALL, 5139 .features[FEAT_8000_0001_ECX] = 5140 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5141 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5142 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5143 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 5144 .features[FEAT_8000_0008_EBX] = 5145 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 5146 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 5147 CPUID_8000_0008_EBX_STIBP, 5148 .features[FEAT_7_0_EBX] = 5149 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5150 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 5151 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 5152 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB, 5153 .features[FEAT_7_0_ECX] = 5154 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID, 5155 .features[FEAT_XSAVE] = 5156 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5157 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 5158 .features[FEAT_6_EAX] = 5159 CPUID_6_EAX_ARAT, 5160 .features[FEAT_SVM] = 5161 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 5162 .xlevel = 0x8000001E, 5163 .model_id = "AMD EPYC-Rome Processor", 5164 .cache_info = &epyc_rome_cache_info, 5165 .versions = (X86CPUVersionDefinition[]) { 5166 { .version = 1 }, 5167 { 5168 .version = 2, 5169 .props = (PropValue[]) { 5170 { "ibrs", "on" }, 5171 { "amd-ssbd", "on" }, 5172 { /* end of list */ } 5173 } 5174 }, 5175 { 5176 .version = 3, 5177 .props = (PropValue[]) { 5178 { "model-id", 5179 "AMD EPYC-Rome-v3 Processor" }, 5180 { /* end of list */ } 5181 }, 5182 .cache_info = &epyc_rome_v3_cache_info 5183 }, 5184 { 5185 .version = 4, 5186 .props = (PropValue[]) { 5187 /* Erratum 1386 */ 5188 { "model-id", 5189 "AMD EPYC-Rome-v4 Processor (no XSAVES)" }, 5190 { "xsaves", "off" }, 5191 { /* end of list */ } 5192 }, 5193 }, 5194 { /* end of list */ } 5195 } 5196 }, 5197 { 5198 .name = "EPYC-Milan", 5199 .level = 0xd, 5200 .vendor = CPUID_VENDOR_AMD, 5201 .family = 25, 5202 .model = 1, 5203 .stepping = 1, 5204 .features[FEAT_1_EDX] = 5205 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 5206 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 5207 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 5208 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 5209 CPUID_VME | CPUID_FP87, 5210 .features[FEAT_1_ECX] = 5211 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5212 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 5213 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5214 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 5215 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 5216 CPUID_EXT_PCID, 5217 .features[FEAT_8000_0001_EDX] = 5218 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5219 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5220 CPUID_EXT2_SYSCALL, 5221 .features[FEAT_8000_0001_ECX] = 5222 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5223 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5224 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5225 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 5226 .features[FEAT_8000_0008_EBX] = 5227 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 5228 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 5229 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | 5230 CPUID_8000_0008_EBX_AMD_SSBD, 5231 .features[FEAT_7_0_EBX] = 5232 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5233 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 5234 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 5235 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_ERMS | 5236 CPUID_7_0_EBX_INVPCID, 5237 .features[FEAT_7_0_ECX] = 5238 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_PKU, 5239 .features[FEAT_7_0_EDX] = 5240 CPUID_7_0_EDX_FSRM, 5241 .features[FEAT_XSAVE] = 5242 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5243 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 5244 .features[FEAT_6_EAX] = 5245 CPUID_6_EAX_ARAT, 5246 .features[FEAT_SVM] = 5247 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE | CPUID_SVM_SVME_ADDR_CHK, 5248 .xlevel = 0x8000001E, 5249 .model_id = "AMD EPYC-Milan Processor", 5250 .cache_info = &epyc_milan_cache_info, 5251 .versions = (X86CPUVersionDefinition[]) { 5252 { .version = 1 }, 5253 { 5254 .version = 2, 5255 .props = (PropValue[]) { 5256 { "model-id", 5257 "AMD EPYC-Milan-v2 Processor" }, 5258 { "vaes", "on" }, 5259 { "vpclmulqdq", "on" }, 5260 { "stibp-always-on", "on" }, 5261 { "amd-psfd", "on" }, 5262 { "no-nested-data-bp", "on" }, 5263 { "lfence-always-serializing", "on" }, 5264 { "null-sel-clr-base", "on" }, 5265 { /* end of list */ } 5266 }, 5267 .cache_info = &epyc_milan_v2_cache_info 5268 }, 5269 { /* end of list */ } 5270 } 5271 }, 5272 { 5273 .name = "EPYC-Genoa", 5274 .level = 0xd, 5275 .vendor = CPUID_VENDOR_AMD, 5276 .family = 25, 5277 .model = 17, 5278 .stepping = 0, 5279 .features[FEAT_1_EDX] = 5280 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 5281 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 5282 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 5283 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 5284 CPUID_VME | CPUID_FP87, 5285 .features[FEAT_1_ECX] = 5286 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5287 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 5288 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5289 CPUID_EXT_PCID | CPUID_EXT_CX16 | CPUID_EXT_FMA | 5290 CPUID_EXT_SSSE3 | CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | 5291 CPUID_EXT_SSE3, 5292 .features[FEAT_8000_0001_EDX] = 5293 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5294 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5295 CPUID_EXT2_SYSCALL, 5296 .features[FEAT_8000_0001_ECX] = 5297 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5298 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5299 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5300 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 5301 .features[FEAT_8000_0008_EBX] = 5302 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 5303 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 5304 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | 5305 CPUID_8000_0008_EBX_STIBP_ALWAYS_ON | 5306 CPUID_8000_0008_EBX_AMD_SSBD | CPUID_8000_0008_EBX_AMD_PSFD, 5307 .features[FEAT_8000_0021_EAX] = 5308 CPUID_8000_0021_EAX_NO_NESTED_DATA_BP | 5309 CPUID_8000_0021_EAX_LFENCE_ALWAYS_SERIALIZING | 5310 CPUID_8000_0021_EAX_NULL_SEL_CLR_BASE | 5311 CPUID_8000_0021_EAX_AUTO_IBRS, 5312 .features[FEAT_7_0_EBX] = 5313 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5314 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 5315 CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_AVX512F | 5316 CPUID_7_0_EBX_AVX512DQ | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 5317 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_AVX512IFMA | 5318 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB | 5319 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | 5320 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, 5321 .features[FEAT_7_0_ECX] = 5322 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 5323 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 5324 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 5325 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 5326 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | 5327 CPUID_7_0_ECX_RDPID, 5328 .features[FEAT_7_0_EDX] = 5329 CPUID_7_0_EDX_FSRM, 5330 .features[FEAT_7_1_EAX] = 5331 CPUID_7_1_EAX_AVX512_BF16, 5332 .features[FEAT_XSAVE] = 5333 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5334 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 5335 .features[FEAT_6_EAX] = 5336 CPUID_6_EAX_ARAT, 5337 .features[FEAT_SVM] = 5338 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE | CPUID_SVM_VNMI | 5339 CPUID_SVM_SVME_ADDR_CHK, 5340 .xlevel = 0x80000022, 5341 .model_id = "AMD EPYC-Genoa Processor", 5342 .cache_info = &epyc_genoa_cache_info, 5343 }, 5344 }; 5345 5346 /* 5347 * We resolve CPU model aliases using -v1 when using "-machine 5348 * none", but this is just for compatibility while libvirt isn't 5349 * adapted to resolve CPU model versions before creating VMs. 5350 * See "Runnability guarantee of CPU models" at 5351 * docs/about/deprecated.rst. 5352 */ 5353 X86CPUVersion default_cpu_version = 1; 5354 5355 void x86_cpu_set_default_version(X86CPUVersion version) 5356 { 5357 /* Translating CPU_VERSION_AUTO to CPU_VERSION_AUTO doesn't make sense */ 5358 assert(version != CPU_VERSION_AUTO); 5359 default_cpu_version = version; 5360 } 5361 5362 static X86CPUVersion x86_cpu_model_last_version(const X86CPUModel *model) 5363 { 5364 int v = 0; 5365 const X86CPUVersionDefinition *vdef = 5366 x86_cpu_def_get_versions(model->cpudef); 5367 while (vdef->version) { 5368 v = vdef->version; 5369 vdef++; 5370 } 5371 return v; 5372 } 5373 5374 /* Return the actual version being used for a specific CPU model */ 5375 static X86CPUVersion x86_cpu_model_resolve_version(const X86CPUModel *model) 5376 { 5377 X86CPUVersion v = model->version; 5378 if (v == CPU_VERSION_AUTO) { 5379 v = default_cpu_version; 5380 } 5381 if (v == CPU_VERSION_LATEST) { 5382 return x86_cpu_model_last_version(model); 5383 } 5384 return v; 5385 } 5386 5387 static Property max_x86_cpu_properties[] = { 5388 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true), 5389 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false), 5390 DEFINE_PROP_END_OF_LIST() 5391 }; 5392 5393 static void max_x86_cpu_realize(DeviceState *dev, Error **errp) 5394 { 5395 Object *obj = OBJECT(dev); 5396 5397 if (!object_property_get_int(obj, "family", &error_abort)) { 5398 if (X86_CPU(obj)->env.features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 5399 object_property_set_int(obj, "family", 15, &error_abort); 5400 object_property_set_int(obj, "model", 107, &error_abort); 5401 object_property_set_int(obj, "stepping", 1, &error_abort); 5402 } else { 5403 object_property_set_int(obj, "family", 6, &error_abort); 5404 object_property_set_int(obj, "model", 6, &error_abort); 5405 object_property_set_int(obj, "stepping", 3, &error_abort); 5406 } 5407 } 5408 5409 x86_cpu_realizefn(dev, errp); 5410 } 5411 5412 static void max_x86_cpu_class_init(ObjectClass *oc, void *data) 5413 { 5414 DeviceClass *dc = DEVICE_CLASS(oc); 5415 X86CPUClass *xcc = X86_CPU_CLASS(oc); 5416 5417 xcc->ordering = 9; 5418 5419 xcc->model_description = 5420 "Enables all features supported by the accelerator in the current host"; 5421 5422 device_class_set_props(dc, max_x86_cpu_properties); 5423 dc->realize = max_x86_cpu_realize; 5424 } 5425 5426 static void max_x86_cpu_initfn(Object *obj) 5427 { 5428 X86CPU *cpu = X86_CPU(obj); 5429 5430 /* We can't fill the features array here because we don't know yet if 5431 * "migratable" is true or false. 5432 */ 5433 cpu->max_features = true; 5434 object_property_set_bool(OBJECT(cpu), "pmu", true, &error_abort); 5435 5436 /* 5437 * these defaults are used for TCG and all other accelerators 5438 * besides KVM and HVF, which overwrite these values 5439 */ 5440 object_property_set_str(OBJECT(cpu), "vendor", CPUID_VENDOR_AMD, 5441 &error_abort); 5442 object_property_set_str(OBJECT(cpu), "model-id", 5443 "QEMU TCG CPU version " QEMU_HW_VERSION, 5444 &error_abort); 5445 } 5446 5447 static const TypeInfo max_x86_cpu_type_info = { 5448 .name = X86_CPU_TYPE_NAME("max"), 5449 .parent = TYPE_X86_CPU, 5450 .instance_init = max_x86_cpu_initfn, 5451 .class_init = max_x86_cpu_class_init, 5452 }; 5453 5454 static char *feature_word_description(FeatureWordInfo *f, uint32_t bit) 5455 { 5456 assert(f->type == CPUID_FEATURE_WORD || f->type == MSR_FEATURE_WORD); 5457 5458 switch (f->type) { 5459 case CPUID_FEATURE_WORD: 5460 { 5461 const char *reg = get_register_name_32(f->cpuid.reg); 5462 assert(reg); 5463 return g_strdup_printf("CPUID.%02XH:%s", 5464 f->cpuid.eax, reg); 5465 } 5466 case MSR_FEATURE_WORD: 5467 return g_strdup_printf("MSR(%02XH)", 5468 f->msr.index); 5469 } 5470 5471 return NULL; 5472 } 5473 5474 static bool x86_cpu_have_filtered_features(X86CPU *cpu) 5475 { 5476 FeatureWord w; 5477 5478 for (w = 0; w < FEATURE_WORDS; w++) { 5479 if (cpu->filtered_features[w]) { 5480 return true; 5481 } 5482 } 5483 5484 return false; 5485 } 5486 5487 static void mark_unavailable_features(X86CPU *cpu, FeatureWord w, uint64_t mask, 5488 const char *verbose_prefix) 5489 { 5490 CPUX86State *env = &cpu->env; 5491 FeatureWordInfo *f = &feature_word_info[w]; 5492 int i; 5493 5494 if (!cpu->force_features) { 5495 env->features[w] &= ~mask; 5496 } 5497 cpu->filtered_features[w] |= mask; 5498 5499 if (!verbose_prefix) { 5500 return; 5501 } 5502 5503 for (i = 0; i < 64; ++i) { 5504 if ((1ULL << i) & mask) { 5505 g_autofree char *feat_word_str = feature_word_description(f, i); 5506 warn_report("%s: %s%s%s [bit %d]", 5507 verbose_prefix, 5508 feat_word_str, 5509 f->feat_names[i] ? "." : "", 5510 f->feat_names[i] ? f->feat_names[i] : "", i); 5511 } 5512 } 5513 } 5514 5515 static void x86_cpuid_version_get_family(Object *obj, Visitor *v, 5516 const char *name, void *opaque, 5517 Error **errp) 5518 { 5519 X86CPU *cpu = X86_CPU(obj); 5520 CPUX86State *env = &cpu->env; 5521 uint64_t value; 5522 5523 value = (env->cpuid_version >> 8) & 0xf; 5524 if (value == 0xf) { 5525 value += (env->cpuid_version >> 20) & 0xff; 5526 } 5527 visit_type_uint64(v, name, &value, errp); 5528 } 5529 5530 static void x86_cpuid_version_set_family(Object *obj, Visitor *v, 5531 const char *name, void *opaque, 5532 Error **errp) 5533 { 5534 X86CPU *cpu = X86_CPU(obj); 5535 CPUX86State *env = &cpu->env; 5536 const uint64_t max = 0xff + 0xf; 5537 uint64_t value; 5538 5539 if (!visit_type_uint64(v, name, &value, errp)) { 5540 return; 5541 } 5542 if (value > max) { 5543 error_setg(errp, "parameter '%s' can be at most %" PRIu64, 5544 name ? name : "null", max); 5545 return; 5546 } 5547 5548 env->cpuid_version &= ~0xff00f00; 5549 if (value > 0x0f) { 5550 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20); 5551 } else { 5552 env->cpuid_version |= value << 8; 5553 } 5554 } 5555 5556 static void x86_cpuid_version_get_model(Object *obj, Visitor *v, 5557 const char *name, void *opaque, 5558 Error **errp) 5559 { 5560 X86CPU *cpu = X86_CPU(obj); 5561 CPUX86State *env = &cpu->env; 5562 uint64_t value; 5563 5564 value = (env->cpuid_version >> 4) & 0xf; 5565 value |= ((env->cpuid_version >> 16) & 0xf) << 4; 5566 visit_type_uint64(v, name, &value, errp); 5567 } 5568 5569 static void x86_cpuid_version_set_model(Object *obj, Visitor *v, 5570 const char *name, void *opaque, 5571 Error **errp) 5572 { 5573 X86CPU *cpu = X86_CPU(obj); 5574 CPUX86State *env = &cpu->env; 5575 const uint64_t max = 0xff; 5576 uint64_t value; 5577 5578 if (!visit_type_uint64(v, name, &value, errp)) { 5579 return; 5580 } 5581 if (value > max) { 5582 error_setg(errp, "parameter '%s' can be at most %" PRIu64, 5583 name ? name : "null", max); 5584 return; 5585 } 5586 5587 env->cpuid_version &= ~0xf00f0; 5588 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16); 5589 } 5590 5591 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v, 5592 const char *name, void *opaque, 5593 Error **errp) 5594 { 5595 X86CPU *cpu = X86_CPU(obj); 5596 CPUX86State *env = &cpu->env; 5597 uint64_t value; 5598 5599 value = env->cpuid_version & 0xf; 5600 visit_type_uint64(v, name, &value, errp); 5601 } 5602 5603 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v, 5604 const char *name, void *opaque, 5605 Error **errp) 5606 { 5607 X86CPU *cpu = X86_CPU(obj); 5608 CPUX86State *env = &cpu->env; 5609 const uint64_t max = 0xf; 5610 uint64_t value; 5611 5612 if (!visit_type_uint64(v, name, &value, errp)) { 5613 return; 5614 } 5615 if (value > max) { 5616 error_setg(errp, "parameter '%s' can be at most %" PRIu64, 5617 name ? name : "null", max); 5618 return; 5619 } 5620 5621 env->cpuid_version &= ~0xf; 5622 env->cpuid_version |= value & 0xf; 5623 } 5624 5625 static char *x86_cpuid_get_vendor(Object *obj, Error **errp) 5626 { 5627 X86CPU *cpu = X86_CPU(obj); 5628 CPUX86State *env = &cpu->env; 5629 char *value; 5630 5631 value = g_malloc(CPUID_VENDOR_SZ + 1); 5632 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2, 5633 env->cpuid_vendor3); 5634 return value; 5635 } 5636 5637 static void x86_cpuid_set_vendor(Object *obj, const char *value, 5638 Error **errp) 5639 { 5640 X86CPU *cpu = X86_CPU(obj); 5641 CPUX86State *env = &cpu->env; 5642 int i; 5643 5644 if (strlen(value) != CPUID_VENDOR_SZ) { 5645 error_setg(errp, "value of property 'vendor' must consist of" 5646 " exactly " stringify(CPUID_VENDOR_SZ) " characters"); 5647 return; 5648 } 5649 5650 env->cpuid_vendor1 = 0; 5651 env->cpuid_vendor2 = 0; 5652 env->cpuid_vendor3 = 0; 5653 for (i = 0; i < 4; i++) { 5654 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i); 5655 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i); 5656 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i); 5657 } 5658 } 5659 5660 static char *x86_cpuid_get_model_id(Object *obj, Error **errp) 5661 { 5662 X86CPU *cpu = X86_CPU(obj); 5663 CPUX86State *env = &cpu->env; 5664 char *value; 5665 int i; 5666 5667 value = g_malloc(48 + 1); 5668 for (i = 0; i < 48; i++) { 5669 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3)); 5670 } 5671 value[48] = '\0'; 5672 return value; 5673 } 5674 5675 static void x86_cpuid_set_model_id(Object *obj, const char *model_id, 5676 Error **errp) 5677 { 5678 X86CPU *cpu = X86_CPU(obj); 5679 CPUX86State *env = &cpu->env; 5680 int c, len, i; 5681 5682 if (model_id == NULL) { 5683 model_id = ""; 5684 } 5685 len = strlen(model_id); 5686 memset(env->cpuid_model, 0, 48); 5687 for (i = 0; i < 48; i++) { 5688 if (i >= len) { 5689 c = '\0'; 5690 } else { 5691 c = (uint8_t)model_id[i]; 5692 } 5693 env->cpuid_model[i >> 2] |= c << (8 * (i & 3)); 5694 } 5695 } 5696 5697 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name, 5698 void *opaque, Error **errp) 5699 { 5700 X86CPU *cpu = X86_CPU(obj); 5701 int64_t value; 5702 5703 value = cpu->env.tsc_khz * 1000; 5704 visit_type_int(v, name, &value, errp); 5705 } 5706 5707 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name, 5708 void *opaque, Error **errp) 5709 { 5710 X86CPU *cpu = X86_CPU(obj); 5711 const int64_t max = INT64_MAX; 5712 int64_t value; 5713 5714 if (!visit_type_int(v, name, &value, errp)) { 5715 return; 5716 } 5717 if (value < 0 || value > max) { 5718 error_setg(errp, "parameter '%s' can be at most %" PRId64, 5719 name ? name : "null", max); 5720 return; 5721 } 5722 5723 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000; 5724 } 5725 5726 /* Generic getter for "feature-words" and "filtered-features" properties */ 5727 static void x86_cpu_get_feature_words(Object *obj, Visitor *v, 5728 const char *name, void *opaque, 5729 Error **errp) 5730 { 5731 uint64_t *array = (uint64_t *)opaque; 5732 FeatureWord w; 5733 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { }; 5734 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { }; 5735 X86CPUFeatureWordInfoList *list = NULL; 5736 5737 for (w = 0; w < FEATURE_WORDS; w++) { 5738 FeatureWordInfo *wi = &feature_word_info[w]; 5739 /* 5740 * We didn't have MSR features when "feature-words" was 5741 * introduced. Therefore skipped other type entries. 5742 */ 5743 if (wi->type != CPUID_FEATURE_WORD) { 5744 continue; 5745 } 5746 X86CPUFeatureWordInfo *qwi = &word_infos[w]; 5747 qwi->cpuid_input_eax = wi->cpuid.eax; 5748 qwi->has_cpuid_input_ecx = wi->cpuid.needs_ecx; 5749 qwi->cpuid_input_ecx = wi->cpuid.ecx; 5750 qwi->cpuid_register = x86_reg_info_32[wi->cpuid.reg].qapi_enum; 5751 qwi->features = array[w]; 5752 5753 /* List will be in reverse order, but order shouldn't matter */ 5754 list_entries[w].next = list; 5755 list_entries[w].value = &word_infos[w]; 5756 list = &list_entries[w]; 5757 } 5758 5759 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp); 5760 } 5761 5762 /* Convert all '_' in a feature string option name to '-', to make feature 5763 * name conform to QOM property naming rule, which uses '-' instead of '_'. 5764 */ 5765 static inline void feat2prop(char *s) 5766 { 5767 while ((s = strchr(s, '_'))) { 5768 *s = '-'; 5769 } 5770 } 5771 5772 /* Return the feature property name for a feature flag bit */ 5773 static const char *x86_cpu_feature_name(FeatureWord w, int bitnr) 5774 { 5775 const char *name; 5776 /* XSAVE components are automatically enabled by other features, 5777 * so return the original feature name instead 5778 */ 5779 if (w == FEAT_XSAVE_XCR0_LO || w == FEAT_XSAVE_XCR0_HI) { 5780 int comp = (w == FEAT_XSAVE_XCR0_HI) ? bitnr + 32 : bitnr; 5781 5782 if (comp < ARRAY_SIZE(x86_ext_save_areas) && 5783 x86_ext_save_areas[comp].bits) { 5784 w = x86_ext_save_areas[comp].feature; 5785 bitnr = ctz32(x86_ext_save_areas[comp].bits); 5786 } 5787 } 5788 5789 assert(bitnr < 64); 5790 assert(w < FEATURE_WORDS); 5791 name = feature_word_info[w].feat_names[bitnr]; 5792 assert(bitnr < 32 || !(name && feature_word_info[w].type == CPUID_FEATURE_WORD)); 5793 return name; 5794 } 5795 5796 /* Compatibility hack to maintain legacy +-feat semantic, 5797 * where +-feat overwrites any feature set by 5798 * feat=on|feat even if the later is parsed after +-feat 5799 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled) 5800 */ 5801 static GList *plus_features, *minus_features; 5802 5803 static gint compare_string(gconstpointer a, gconstpointer b) 5804 { 5805 return g_strcmp0(a, b); 5806 } 5807 5808 /* Parse "+feature,-feature,feature=foo" CPU feature string 5809 */ 5810 static void x86_cpu_parse_featurestr(const char *typename, char *features, 5811 Error **errp) 5812 { 5813 char *featurestr; /* Single 'key=value" string being parsed */ 5814 static bool cpu_globals_initialized; 5815 bool ambiguous = false; 5816 5817 if (cpu_globals_initialized) { 5818 return; 5819 } 5820 cpu_globals_initialized = true; 5821 5822 if (!features) { 5823 return; 5824 } 5825 5826 for (featurestr = strtok(features, ","); 5827 featurestr; 5828 featurestr = strtok(NULL, ",")) { 5829 const char *name; 5830 const char *val = NULL; 5831 char *eq = NULL; 5832 char num[32]; 5833 GlobalProperty *prop; 5834 5835 /* Compatibility syntax: */ 5836 if (featurestr[0] == '+') { 5837 plus_features = g_list_append(plus_features, 5838 g_strdup(featurestr + 1)); 5839 continue; 5840 } else if (featurestr[0] == '-') { 5841 minus_features = g_list_append(minus_features, 5842 g_strdup(featurestr + 1)); 5843 continue; 5844 } 5845 5846 eq = strchr(featurestr, '='); 5847 if (eq) { 5848 *eq++ = 0; 5849 val = eq; 5850 } else { 5851 val = "on"; 5852 } 5853 5854 feat2prop(featurestr); 5855 name = featurestr; 5856 5857 if (g_list_find_custom(plus_features, name, compare_string)) { 5858 warn_report("Ambiguous CPU model string. " 5859 "Don't mix both \"+%s\" and \"%s=%s\"", 5860 name, name, val); 5861 ambiguous = true; 5862 } 5863 if (g_list_find_custom(minus_features, name, compare_string)) { 5864 warn_report("Ambiguous CPU model string. " 5865 "Don't mix both \"-%s\" and \"%s=%s\"", 5866 name, name, val); 5867 ambiguous = true; 5868 } 5869 5870 /* Special case: */ 5871 if (!strcmp(name, "tsc-freq")) { 5872 int ret; 5873 uint64_t tsc_freq; 5874 5875 ret = qemu_strtosz_metric(val, NULL, &tsc_freq); 5876 if (ret < 0 || tsc_freq > INT64_MAX) { 5877 error_setg(errp, "bad numerical value %s", val); 5878 return; 5879 } 5880 snprintf(num, sizeof(num), "%" PRId64, tsc_freq); 5881 val = num; 5882 name = "tsc-frequency"; 5883 } 5884 5885 prop = g_new0(typeof(*prop), 1); 5886 prop->driver = typename; 5887 prop->property = g_strdup(name); 5888 prop->value = g_strdup(val); 5889 qdev_prop_register_global(prop); 5890 } 5891 5892 if (ambiguous) { 5893 warn_report("Compatibility of ambiguous CPU model " 5894 "strings won't be kept on future QEMU versions"); 5895 } 5896 } 5897 5898 static bool x86_cpu_filter_features(X86CPU *cpu, bool verbose); 5899 5900 /* Build a list with the name of all features on a feature word array */ 5901 static void x86_cpu_list_feature_names(FeatureWordArray features, 5902 strList **list) 5903 { 5904 strList **tail = list; 5905 FeatureWord w; 5906 5907 for (w = 0; w < FEATURE_WORDS; w++) { 5908 uint64_t filtered = features[w]; 5909 int i; 5910 for (i = 0; i < 64; i++) { 5911 if (filtered & (1ULL << i)) { 5912 QAPI_LIST_APPEND(tail, g_strdup(x86_cpu_feature_name(w, i))); 5913 } 5914 } 5915 } 5916 } 5917 5918 static void x86_cpu_get_unavailable_features(Object *obj, Visitor *v, 5919 const char *name, void *opaque, 5920 Error **errp) 5921 { 5922 X86CPU *xc = X86_CPU(obj); 5923 strList *result = NULL; 5924 5925 x86_cpu_list_feature_names(xc->filtered_features, &result); 5926 visit_type_strList(v, "unavailable-features", &result, errp); 5927 } 5928 5929 /* Print all cpuid feature names in featureset 5930 */ 5931 static void listflags(GList *features) 5932 { 5933 size_t len = 0; 5934 GList *tmp; 5935 5936 for (tmp = features; tmp; tmp = tmp->next) { 5937 const char *name = tmp->data; 5938 if ((len + strlen(name) + 1) >= 75) { 5939 qemu_printf("\n"); 5940 len = 0; 5941 } 5942 qemu_printf("%s%s", len == 0 ? " " : " ", name); 5943 len += strlen(name) + 1; 5944 } 5945 qemu_printf("\n"); 5946 } 5947 5948 /* Sort alphabetically by type name, respecting X86CPUClass::ordering. */ 5949 static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b) 5950 { 5951 ObjectClass *class_a = (ObjectClass *)a; 5952 ObjectClass *class_b = (ObjectClass *)b; 5953 X86CPUClass *cc_a = X86_CPU_CLASS(class_a); 5954 X86CPUClass *cc_b = X86_CPU_CLASS(class_b); 5955 int ret; 5956 5957 if (cc_a->ordering != cc_b->ordering) { 5958 ret = cc_a->ordering - cc_b->ordering; 5959 } else { 5960 g_autofree char *name_a = x86_cpu_class_get_model_name(cc_a); 5961 g_autofree char *name_b = x86_cpu_class_get_model_name(cc_b); 5962 ret = strcmp(name_a, name_b); 5963 } 5964 return ret; 5965 } 5966 5967 static GSList *get_sorted_cpu_model_list(void) 5968 { 5969 GSList *list = object_class_get_list(TYPE_X86_CPU, false); 5970 list = g_slist_sort(list, x86_cpu_list_compare); 5971 return list; 5972 } 5973 5974 static char *x86_cpu_class_get_model_id(X86CPUClass *xc) 5975 { 5976 Object *obj = object_new_with_class(OBJECT_CLASS(xc)); 5977 char *r = object_property_get_str(obj, "model-id", &error_abort); 5978 object_unref(obj); 5979 return r; 5980 } 5981 5982 static char *x86_cpu_class_get_alias_of(X86CPUClass *cc) 5983 { 5984 X86CPUVersion version; 5985 5986 if (!cc->model || !cc->model->is_alias) { 5987 return NULL; 5988 } 5989 version = x86_cpu_model_resolve_version(cc->model); 5990 if (version <= 0) { 5991 return NULL; 5992 } 5993 return x86_cpu_versioned_model_name(cc->model->cpudef, version); 5994 } 5995 5996 static void x86_cpu_list_entry(gpointer data, gpointer user_data) 5997 { 5998 ObjectClass *oc = data; 5999 X86CPUClass *cc = X86_CPU_CLASS(oc); 6000 g_autofree char *name = x86_cpu_class_get_model_name(cc); 6001 g_autofree char *desc = g_strdup(cc->model_description); 6002 g_autofree char *alias_of = x86_cpu_class_get_alias_of(cc); 6003 g_autofree char *model_id = x86_cpu_class_get_model_id(cc); 6004 6005 if (!desc && alias_of) { 6006 if (cc->model && cc->model->version == CPU_VERSION_AUTO) { 6007 desc = g_strdup("(alias configured by machine type)"); 6008 } else { 6009 desc = g_strdup_printf("(alias of %s)", alias_of); 6010 } 6011 } 6012 if (!desc && cc->model && cc->model->note) { 6013 desc = g_strdup_printf("%s [%s]", model_id, cc->model->note); 6014 } 6015 if (!desc) { 6016 desc = g_strdup_printf("%s", model_id); 6017 } 6018 6019 if (cc->model && cc->model->cpudef->deprecation_note) { 6020 g_autofree char *olddesc = desc; 6021 desc = g_strdup_printf("%s (deprecated)", olddesc); 6022 } 6023 6024 qemu_printf(" %-20s %s\n", name, desc); 6025 } 6026 6027 /* list available CPU models and flags */ 6028 void x86_cpu_list(void) 6029 { 6030 int i, j; 6031 GSList *list; 6032 GList *names = NULL; 6033 6034 qemu_printf("Available CPUs:\n"); 6035 list = get_sorted_cpu_model_list(); 6036 g_slist_foreach(list, x86_cpu_list_entry, NULL); 6037 g_slist_free(list); 6038 6039 names = NULL; 6040 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) { 6041 FeatureWordInfo *fw = &feature_word_info[i]; 6042 for (j = 0; j < 64; j++) { 6043 if (fw->feat_names[j]) { 6044 names = g_list_append(names, (gpointer)fw->feat_names[j]); 6045 } 6046 } 6047 } 6048 6049 names = g_list_sort(names, (GCompareFunc)strcmp); 6050 6051 qemu_printf("\nRecognized CPUID flags:\n"); 6052 listflags(names); 6053 qemu_printf("\n"); 6054 g_list_free(names); 6055 } 6056 6057 #ifndef CONFIG_USER_ONLY 6058 6059 /* Check for missing features that may prevent the CPU class from 6060 * running using the current machine and accelerator. 6061 */ 6062 static void x86_cpu_class_check_missing_features(X86CPUClass *xcc, 6063 strList **list) 6064 { 6065 strList **tail = list; 6066 X86CPU *xc; 6067 Error *err = NULL; 6068 6069 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) { 6070 QAPI_LIST_APPEND(tail, g_strdup("kvm")); 6071 return; 6072 } 6073 6074 xc = X86_CPU(object_new_with_class(OBJECT_CLASS(xcc))); 6075 6076 x86_cpu_expand_features(xc, &err); 6077 if (err) { 6078 /* Errors at x86_cpu_expand_features should never happen, 6079 * but in case it does, just report the model as not 6080 * runnable at all using the "type" property. 6081 */ 6082 QAPI_LIST_APPEND(tail, g_strdup("type")); 6083 error_free(err); 6084 } 6085 6086 x86_cpu_filter_features(xc, false); 6087 6088 x86_cpu_list_feature_names(xc->filtered_features, tail); 6089 6090 object_unref(OBJECT(xc)); 6091 } 6092 6093 static void x86_cpu_definition_entry(gpointer data, gpointer user_data) 6094 { 6095 ObjectClass *oc = data; 6096 X86CPUClass *cc = X86_CPU_CLASS(oc); 6097 CpuDefinitionInfoList **cpu_list = user_data; 6098 CpuDefinitionInfo *info; 6099 6100 info = g_malloc0(sizeof(*info)); 6101 info->name = x86_cpu_class_get_model_name(cc); 6102 x86_cpu_class_check_missing_features(cc, &info->unavailable_features); 6103 info->has_unavailable_features = true; 6104 info->q_typename = g_strdup(object_class_get_name(oc)); 6105 info->migration_safe = cc->migration_safe; 6106 info->has_migration_safe = true; 6107 info->q_static = cc->static_model; 6108 if (cc->model && cc->model->cpudef->deprecation_note) { 6109 info->deprecated = true; 6110 } else { 6111 info->deprecated = false; 6112 } 6113 /* 6114 * Old machine types won't report aliases, so that alias translation 6115 * doesn't break compatibility with previous QEMU versions. 6116 */ 6117 if (default_cpu_version != CPU_VERSION_LEGACY) { 6118 info->alias_of = x86_cpu_class_get_alias_of(cc); 6119 } 6120 6121 QAPI_LIST_PREPEND(*cpu_list, info); 6122 } 6123 6124 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) 6125 { 6126 CpuDefinitionInfoList *cpu_list = NULL; 6127 GSList *list = get_sorted_cpu_model_list(); 6128 g_slist_foreach(list, x86_cpu_definition_entry, &cpu_list); 6129 g_slist_free(list); 6130 return cpu_list; 6131 } 6132 6133 #endif /* !CONFIG_USER_ONLY */ 6134 6135 uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w) 6136 { 6137 FeatureWordInfo *wi = &feature_word_info[w]; 6138 uint64_t r = 0; 6139 uint64_t unavail = 0; 6140 6141 if (kvm_enabled()) { 6142 switch (wi->type) { 6143 case CPUID_FEATURE_WORD: 6144 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid.eax, 6145 wi->cpuid.ecx, 6146 wi->cpuid.reg); 6147 break; 6148 case MSR_FEATURE_WORD: 6149 r = kvm_arch_get_supported_msr_feature(kvm_state, 6150 wi->msr.index); 6151 break; 6152 } 6153 } else if (hvf_enabled()) { 6154 if (wi->type != CPUID_FEATURE_WORD) { 6155 return 0; 6156 } 6157 r = hvf_get_supported_cpuid(wi->cpuid.eax, 6158 wi->cpuid.ecx, 6159 wi->cpuid.reg); 6160 } else if (tcg_enabled()) { 6161 r = wi->tcg_features; 6162 } else { 6163 return ~0; 6164 } 6165 6166 switch (w) { 6167 #ifndef TARGET_X86_64 6168 case FEAT_8000_0001_EDX: 6169 /* 6170 * 32-bit TCG can emulate 64-bit compatibility mode. If there is no 6171 * way for userspace to get out of its 32-bit jail, we can leave 6172 * the LM bit set. 6173 */ 6174 unavail = tcg_enabled() 6175 ? CPUID_EXT2_LM & ~CPUID_EXT2_KERNEL_FEATURES 6176 : CPUID_EXT2_LM; 6177 break; 6178 #endif 6179 6180 case FEAT_8000_0007_EBX: 6181 if (cpu && !IS_AMD_CPU(&cpu->env)) { 6182 /* Disable AMD machine check architecture for Intel CPU. */ 6183 unavail = ~0; 6184 } 6185 break; 6186 6187 case FEAT_7_0_EBX: 6188 #ifndef CONFIG_USER_ONLY 6189 if (!check_sgx_support()) { 6190 unavail = CPUID_7_0_EBX_SGX; 6191 } 6192 #endif 6193 break; 6194 case FEAT_7_0_ECX: 6195 #ifndef CONFIG_USER_ONLY 6196 if (!check_sgx_support()) { 6197 unavail = CPUID_7_0_ECX_SGX_LC; 6198 } 6199 #endif 6200 break; 6201 6202 default: 6203 break; 6204 } 6205 6206 r &= ~unavail; 6207 if (cpu && cpu->migratable) { 6208 r &= x86_cpu_get_migratable_flags(cpu, w); 6209 } 6210 return r; 6211 } 6212 6213 static void x86_cpu_get_supported_cpuid(uint32_t func, uint32_t index, 6214 uint32_t *eax, uint32_t *ebx, 6215 uint32_t *ecx, uint32_t *edx) 6216 { 6217 if (kvm_enabled()) { 6218 *eax = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EAX); 6219 *ebx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EBX); 6220 *ecx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_ECX); 6221 *edx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EDX); 6222 } else if (hvf_enabled()) { 6223 *eax = hvf_get_supported_cpuid(func, index, R_EAX); 6224 *ebx = hvf_get_supported_cpuid(func, index, R_EBX); 6225 *ecx = hvf_get_supported_cpuid(func, index, R_ECX); 6226 *edx = hvf_get_supported_cpuid(func, index, R_EDX); 6227 } else { 6228 *eax = 0; 6229 *ebx = 0; 6230 *ecx = 0; 6231 *edx = 0; 6232 } 6233 } 6234 6235 static void x86_cpu_get_cache_cpuid(uint32_t func, uint32_t index, 6236 uint32_t *eax, uint32_t *ebx, 6237 uint32_t *ecx, uint32_t *edx) 6238 { 6239 uint32_t level, unused; 6240 6241 /* Only return valid host leaves. */ 6242 switch (func) { 6243 case 2: 6244 case 4: 6245 host_cpuid(0, 0, &level, &unused, &unused, &unused); 6246 break; 6247 case 0x80000005: 6248 case 0x80000006: 6249 case 0x8000001d: 6250 host_cpuid(0x80000000, 0, &level, &unused, &unused, &unused); 6251 break; 6252 default: 6253 return; 6254 } 6255 6256 if (func > level) { 6257 *eax = 0; 6258 *ebx = 0; 6259 *ecx = 0; 6260 *edx = 0; 6261 } else { 6262 host_cpuid(func, index, eax, ebx, ecx, edx); 6263 } 6264 } 6265 6266 /* 6267 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 6268 */ 6269 void x86_cpu_apply_props(X86CPU *cpu, PropValue *props) 6270 { 6271 PropValue *pv; 6272 for (pv = props; pv->prop; pv++) { 6273 if (!pv->value) { 6274 continue; 6275 } 6276 object_property_parse(OBJECT(cpu), pv->prop, pv->value, 6277 &error_abort); 6278 } 6279 } 6280 6281 /* 6282 * Apply properties for the CPU model version specified in model. 6283 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 6284 */ 6285 6286 static void x86_cpu_apply_version_props(X86CPU *cpu, X86CPUModel *model) 6287 { 6288 const X86CPUVersionDefinition *vdef; 6289 X86CPUVersion version = x86_cpu_model_resolve_version(model); 6290 6291 if (version == CPU_VERSION_LEGACY) { 6292 return; 6293 } 6294 6295 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) { 6296 PropValue *p; 6297 6298 for (p = vdef->props; p && p->prop; p++) { 6299 object_property_parse(OBJECT(cpu), p->prop, p->value, 6300 &error_abort); 6301 } 6302 6303 if (vdef->version == version) { 6304 break; 6305 } 6306 } 6307 6308 /* 6309 * If we reached the end of the list, version number was invalid 6310 */ 6311 assert(vdef->version == version); 6312 } 6313 6314 static const CPUCaches *x86_cpu_get_versioned_cache_info(X86CPU *cpu, 6315 X86CPUModel *model) 6316 { 6317 const X86CPUVersionDefinition *vdef; 6318 X86CPUVersion version = x86_cpu_model_resolve_version(model); 6319 const CPUCaches *cache_info = model->cpudef->cache_info; 6320 6321 if (version == CPU_VERSION_LEGACY) { 6322 return cache_info; 6323 } 6324 6325 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) { 6326 if (vdef->cache_info) { 6327 cache_info = vdef->cache_info; 6328 } 6329 6330 if (vdef->version == version) { 6331 break; 6332 } 6333 } 6334 6335 assert(vdef->version == version); 6336 return cache_info; 6337 } 6338 6339 /* 6340 * Load data from X86CPUDefinition into a X86CPU object. 6341 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 6342 */ 6343 static void x86_cpu_load_model(X86CPU *cpu, X86CPUModel *model) 6344 { 6345 const X86CPUDefinition *def = model->cpudef; 6346 CPUX86State *env = &cpu->env; 6347 FeatureWord w; 6348 6349 /*NOTE: any property set by this function should be returned by 6350 * x86_cpu_static_props(), so static expansion of 6351 * query-cpu-model-expansion is always complete. 6352 */ 6353 6354 /* CPU models only set _minimum_ values for level/xlevel: */ 6355 object_property_set_uint(OBJECT(cpu), "min-level", def->level, 6356 &error_abort); 6357 object_property_set_uint(OBJECT(cpu), "min-xlevel", def->xlevel, 6358 &error_abort); 6359 6360 object_property_set_int(OBJECT(cpu), "family", def->family, &error_abort); 6361 object_property_set_int(OBJECT(cpu), "model", def->model, &error_abort); 6362 object_property_set_int(OBJECT(cpu), "stepping", def->stepping, 6363 &error_abort); 6364 object_property_set_str(OBJECT(cpu), "model-id", def->model_id, 6365 &error_abort); 6366 for (w = 0; w < FEATURE_WORDS; w++) { 6367 env->features[w] = def->features[w]; 6368 } 6369 6370 /* legacy-cache defaults to 'off' if CPU model provides cache info */ 6371 cpu->legacy_cache = !x86_cpu_get_versioned_cache_info(cpu, model); 6372 6373 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR; 6374 6375 /* sysenter isn't supported in compatibility mode on AMD, 6376 * syscall isn't supported in compatibility mode on Intel. 6377 * Normally we advertise the actual CPU vendor, but you can 6378 * override this using the 'vendor' property if you want to use 6379 * KVM's sysenter/syscall emulation in compatibility mode and 6380 * when doing cross vendor migration 6381 */ 6382 6383 /* 6384 * vendor property is set here but then overloaded with the 6385 * host cpu vendor for KVM and HVF. 6386 */ 6387 object_property_set_str(OBJECT(cpu), "vendor", def->vendor, &error_abort); 6388 6389 object_property_set_uint(OBJECT(cpu), "avx10-version", def->avx10_version, 6390 &error_abort); 6391 6392 x86_cpu_apply_version_props(cpu, model); 6393 6394 /* 6395 * Properties in versioned CPU model are not user specified features. 6396 * We can simply clear env->user_features here since it will be filled later 6397 * in x86_cpu_expand_features() based on plus_features and minus_features. 6398 */ 6399 memset(&env->user_features, 0, sizeof(env->user_features)); 6400 } 6401 6402 static const gchar *x86_gdb_arch_name(CPUState *cs) 6403 { 6404 #ifdef TARGET_X86_64 6405 return "i386:x86-64"; 6406 #else 6407 return "i386"; 6408 #endif 6409 } 6410 6411 static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data) 6412 { 6413 X86CPUModel *model = data; 6414 X86CPUClass *xcc = X86_CPU_CLASS(oc); 6415 CPUClass *cc = CPU_CLASS(oc); 6416 6417 xcc->model = model; 6418 xcc->migration_safe = true; 6419 cc->deprecation_note = model->cpudef->deprecation_note; 6420 } 6421 6422 static void x86_register_cpu_model_type(const char *name, X86CPUModel *model) 6423 { 6424 g_autofree char *typename = x86_cpu_type_name(name); 6425 TypeInfo ti = { 6426 .name = typename, 6427 .parent = TYPE_X86_CPU, 6428 .class_init = x86_cpu_cpudef_class_init, 6429 .class_data = model, 6430 }; 6431 6432 type_register(&ti); 6433 } 6434 6435 6436 /* 6437 * register builtin_x86_defs; 6438 * "max", "base" and subclasses ("host") are not registered here. 6439 * See x86_cpu_register_types for all model registrations. 6440 */ 6441 static void x86_register_cpudef_types(const X86CPUDefinition *def) 6442 { 6443 X86CPUModel *m; 6444 const X86CPUVersionDefinition *vdef; 6445 6446 /* AMD aliases are handled at runtime based on CPUID vendor, so 6447 * they shouldn't be set on the CPU model table. 6448 */ 6449 assert(!(def->features[FEAT_8000_0001_EDX] & CPUID_EXT2_AMD_ALIASES)); 6450 /* catch mistakes instead of silently truncating model_id when too long */ 6451 assert(def->model_id && strlen(def->model_id) <= 48); 6452 6453 /* Unversioned model: */ 6454 m = g_new0(X86CPUModel, 1); 6455 m->cpudef = def; 6456 m->version = CPU_VERSION_AUTO; 6457 m->is_alias = true; 6458 x86_register_cpu_model_type(def->name, m); 6459 6460 /* Versioned models: */ 6461 6462 for (vdef = x86_cpu_def_get_versions(def); vdef->version; vdef++) { 6463 g_autofree char *name = 6464 x86_cpu_versioned_model_name(def, vdef->version); 6465 6466 m = g_new0(X86CPUModel, 1); 6467 m->cpudef = def; 6468 m->version = vdef->version; 6469 m->note = vdef->note; 6470 x86_register_cpu_model_type(name, m); 6471 6472 if (vdef->alias) { 6473 X86CPUModel *am = g_new0(X86CPUModel, 1); 6474 am->cpudef = def; 6475 am->version = vdef->version; 6476 am->is_alias = true; 6477 x86_register_cpu_model_type(vdef->alias, am); 6478 } 6479 } 6480 6481 } 6482 6483 uint32_t cpu_x86_virtual_addr_width(CPUX86State *env) 6484 { 6485 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57) { 6486 return 57; /* 57 bits virtual */ 6487 } else { 6488 return 48; /* 48 bits virtual */ 6489 } 6490 } 6491 6492 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, 6493 uint32_t *eax, uint32_t *ebx, 6494 uint32_t *ecx, uint32_t *edx) 6495 { 6496 X86CPU *cpu = env_archcpu(env); 6497 CPUState *cs = env_cpu(env); 6498 uint32_t limit; 6499 uint32_t signature[3]; 6500 X86CPUTopoInfo topo_info; 6501 uint32_t cores_per_pkg; 6502 uint32_t threads_per_pkg; 6503 6504 topo_info.dies_per_pkg = env->nr_dies; 6505 topo_info.modules_per_die = env->nr_modules; 6506 topo_info.cores_per_module = cs->nr_cores / env->nr_dies / env->nr_modules; 6507 topo_info.threads_per_core = cs->nr_threads; 6508 6509 cores_per_pkg = topo_info.cores_per_module * topo_info.modules_per_die * 6510 topo_info.dies_per_pkg; 6511 threads_per_pkg = cores_per_pkg * topo_info.threads_per_core; 6512 6513 /* Calculate & apply limits for different index ranges */ 6514 if (index >= 0xC0000000) { 6515 limit = env->cpuid_xlevel2; 6516 } else if (index >= 0x80000000) { 6517 limit = env->cpuid_xlevel; 6518 } else if (index >= 0x40000000) { 6519 limit = 0x40000001; 6520 } else { 6521 limit = env->cpuid_level; 6522 } 6523 6524 if (index > limit) { 6525 /* Intel documentation states that invalid EAX input will 6526 * return the same information as EAX=cpuid_level 6527 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID) 6528 */ 6529 index = env->cpuid_level; 6530 } 6531 6532 switch(index) { 6533 case 0: 6534 *eax = env->cpuid_level; 6535 *ebx = env->cpuid_vendor1; 6536 *edx = env->cpuid_vendor2; 6537 *ecx = env->cpuid_vendor3; 6538 break; 6539 case 1: 6540 *eax = env->cpuid_version; 6541 *ebx = (cpu->apic_id << 24) | 6542 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */ 6543 *ecx = env->features[FEAT_1_ECX]; 6544 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) { 6545 *ecx |= CPUID_EXT_OSXSAVE; 6546 } 6547 *edx = env->features[FEAT_1_EDX]; 6548 if (threads_per_pkg > 1) { 6549 *ebx |= threads_per_pkg << 16; 6550 *edx |= CPUID_HT; 6551 } 6552 if (!cpu->enable_pmu) { 6553 *ecx &= ~CPUID_EXT_PDCM; 6554 } 6555 break; 6556 case 2: 6557 /* cache info: needed for Pentium Pro compatibility */ 6558 if (cpu->cache_info_passthrough) { 6559 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 6560 break; 6561 } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { 6562 *eax = *ebx = *ecx = *edx = 0; 6563 break; 6564 } 6565 *eax = 1; /* Number of CPUID[EAX=2] calls required */ 6566 *ebx = 0; 6567 if (!cpu->enable_l3_cache) { 6568 *ecx = 0; 6569 } else { 6570 *ecx = cpuid2_cache_descriptor(env->cache_info_cpuid2.l3_cache); 6571 } 6572 *edx = (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1d_cache) << 16) | 6573 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1i_cache) << 8) | 6574 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l2_cache)); 6575 break; 6576 case 4: 6577 /* cache info: needed for Core compatibility */ 6578 if (cpu->cache_info_passthrough) { 6579 x86_cpu_get_cache_cpuid(index, count, eax, ebx, ecx, edx); 6580 /* 6581 * QEMU has its own number of cores/logical cpus, 6582 * set 24..14, 31..26 bit to configured values 6583 */ 6584 if (*eax & 31) { 6585 int host_vcpus_per_cache = 1 + ((*eax & 0x3FFC000) >> 14); 6586 6587 *eax &= ~0xFC000000; 6588 *eax |= max_core_ids_in_package(&topo_info) << 26; 6589 if (host_vcpus_per_cache > threads_per_pkg) { 6590 *eax &= ~0x3FFC000; 6591 6592 /* Share the cache at package level. */ 6593 *eax |= max_thread_ids_for_cache(&topo_info, 6594 CPU_TOPOLOGY_LEVEL_SOCKET) << 14; 6595 } 6596 } 6597 } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { 6598 *eax = *ebx = *ecx = *edx = 0; 6599 } else { 6600 *eax = 0; 6601 6602 switch (count) { 6603 case 0: /* L1 dcache info */ 6604 encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache, 6605 &topo_info, 6606 eax, ebx, ecx, edx); 6607 if (!cpu->l1_cache_per_core) { 6608 *eax &= ~MAKE_64BIT_MASK(14, 12); 6609 } 6610 break; 6611 case 1: /* L1 icache info */ 6612 encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache, 6613 &topo_info, 6614 eax, ebx, ecx, edx); 6615 if (!cpu->l1_cache_per_core) { 6616 *eax &= ~MAKE_64BIT_MASK(14, 12); 6617 } 6618 break; 6619 case 2: /* L2 cache info */ 6620 encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache, 6621 &topo_info, 6622 eax, ebx, ecx, edx); 6623 break; 6624 case 3: /* L3 cache info */ 6625 if (cpu->enable_l3_cache) { 6626 encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache, 6627 &topo_info, 6628 eax, ebx, ecx, edx); 6629 break; 6630 } 6631 /* fall through */ 6632 default: /* end of info */ 6633 *eax = *ebx = *ecx = *edx = 0; 6634 break; 6635 } 6636 } 6637 break; 6638 case 5: 6639 /* MONITOR/MWAIT Leaf */ 6640 *eax = cpu->mwait.eax; /* Smallest monitor-line size in bytes */ 6641 *ebx = cpu->mwait.ebx; /* Largest monitor-line size in bytes */ 6642 *ecx = cpu->mwait.ecx; /* flags */ 6643 *edx = cpu->mwait.edx; /* mwait substates */ 6644 break; 6645 case 6: 6646 /* Thermal and Power Leaf */ 6647 *eax = env->features[FEAT_6_EAX]; 6648 *ebx = 0; 6649 *ecx = 0; 6650 *edx = 0; 6651 break; 6652 case 7: 6653 /* Structured Extended Feature Flags Enumeration Leaf */ 6654 if (count == 0) { 6655 /* Maximum ECX value for sub-leaves */ 6656 *eax = env->cpuid_level_func7; 6657 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */ 6658 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */ 6659 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) { 6660 *ecx |= CPUID_7_0_ECX_OSPKE; 6661 } 6662 *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */ 6663 } else if (count == 1) { 6664 *eax = env->features[FEAT_7_1_EAX]; 6665 *edx = env->features[FEAT_7_1_EDX]; 6666 *ebx = 0; 6667 *ecx = 0; 6668 } else if (count == 2) { 6669 *edx = env->features[FEAT_7_2_EDX]; 6670 *eax = 0; 6671 *ebx = 0; 6672 *ecx = 0; 6673 } else { 6674 *eax = 0; 6675 *ebx = 0; 6676 *ecx = 0; 6677 *edx = 0; 6678 } 6679 break; 6680 case 9: 6681 /* Direct Cache Access Information Leaf */ 6682 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */ 6683 *ebx = 0; 6684 *ecx = 0; 6685 *edx = 0; 6686 break; 6687 case 0xA: 6688 /* Architectural Performance Monitoring Leaf */ 6689 if (cpu->enable_pmu) { 6690 x86_cpu_get_supported_cpuid(0xA, count, eax, ebx, ecx, edx); 6691 } else { 6692 *eax = 0; 6693 *ebx = 0; 6694 *ecx = 0; 6695 *edx = 0; 6696 } 6697 break; 6698 case 0xB: 6699 /* Extended Topology Enumeration Leaf */ 6700 if (!cpu->enable_cpuid_0xb) { 6701 *eax = *ebx = *ecx = *edx = 0; 6702 break; 6703 } 6704 6705 *ecx = count & 0xff; 6706 *edx = cpu->apic_id; 6707 6708 switch (count) { 6709 case 0: 6710 *eax = apicid_core_offset(&topo_info); 6711 *ebx = topo_info.threads_per_core; 6712 *ecx |= CPUID_B_ECX_TOPO_LEVEL_SMT << 8; 6713 break; 6714 case 1: 6715 *eax = apicid_pkg_offset(&topo_info); 6716 *ebx = threads_per_pkg; 6717 *ecx |= CPUID_B_ECX_TOPO_LEVEL_CORE << 8; 6718 break; 6719 default: 6720 *eax = 0; 6721 *ebx = 0; 6722 *ecx |= CPUID_B_ECX_TOPO_LEVEL_INVALID << 8; 6723 } 6724 6725 assert(!(*eax & ~0x1f)); 6726 *ebx &= 0xffff; /* The count doesn't need to be reliable. */ 6727 break; 6728 case 0x1C: 6729 if (cpu->enable_pmu && (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) { 6730 x86_cpu_get_supported_cpuid(0x1C, 0, eax, ebx, ecx, edx); 6731 *edx = 0; 6732 } 6733 break; 6734 case 0x1F: 6735 /* V2 Extended Topology Enumeration Leaf */ 6736 if (!x86_has_extended_topo(env->avail_cpu_topo)) { 6737 *eax = *ebx = *ecx = *edx = 0; 6738 break; 6739 } 6740 6741 encode_topo_cpuid1f(env, count, &topo_info, eax, ebx, ecx, edx); 6742 break; 6743 case 0xD: { 6744 /* Processor Extended State */ 6745 *eax = 0; 6746 *ebx = 0; 6747 *ecx = 0; 6748 *edx = 0; 6749 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { 6750 break; 6751 } 6752 6753 if (count == 0) { 6754 *ecx = xsave_area_size(x86_cpu_xsave_xcr0_components(cpu), false); 6755 *eax = env->features[FEAT_XSAVE_XCR0_LO]; 6756 *edx = env->features[FEAT_XSAVE_XCR0_HI]; 6757 /* 6758 * The initial value of xcr0 and ebx == 0, On host without kvm 6759 * commit 412a3c41(e.g., CentOS 6), the ebx's value always == 0 6760 * even through guest update xcr0, this will crash some legacy guest 6761 * (e.g., CentOS 6), So set ebx == ecx to workaround it. 6762 */ 6763 *ebx = kvm_enabled() ? *ecx : xsave_area_size(env->xcr0, false); 6764 } else if (count == 1) { 6765 uint64_t xstate = x86_cpu_xsave_xcr0_components(cpu) | 6766 x86_cpu_xsave_xss_components(cpu); 6767 6768 *eax = env->features[FEAT_XSAVE]; 6769 *ebx = xsave_area_size(xstate, true); 6770 *ecx = env->features[FEAT_XSAVE_XSS_LO]; 6771 *edx = env->features[FEAT_XSAVE_XSS_HI]; 6772 if (kvm_enabled() && cpu->enable_pmu && 6773 (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR) && 6774 (*eax & CPUID_XSAVE_XSAVES)) { 6775 *ecx |= XSTATE_ARCH_LBR_MASK; 6776 } else { 6777 *ecx &= ~XSTATE_ARCH_LBR_MASK; 6778 } 6779 } else if (count == 0xf && cpu->enable_pmu 6780 && (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) { 6781 x86_cpu_get_supported_cpuid(0xD, count, eax, ebx, ecx, edx); 6782 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) { 6783 const ExtSaveArea *esa = &x86_ext_save_areas[count]; 6784 6785 if (x86_cpu_xsave_xcr0_components(cpu) & (1ULL << count)) { 6786 *eax = esa->size; 6787 *ebx = esa->offset; 6788 *ecx = esa->ecx & 6789 (ESA_FEATURE_ALIGN64_MASK | ESA_FEATURE_XFD_MASK); 6790 } else if (x86_cpu_xsave_xss_components(cpu) & (1ULL << count)) { 6791 *eax = esa->size; 6792 *ebx = 0; 6793 *ecx = 1; 6794 } 6795 } 6796 break; 6797 } 6798 case 0x12: 6799 #ifndef CONFIG_USER_ONLY 6800 if (!kvm_enabled() || 6801 !(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX)) { 6802 *eax = *ebx = *ecx = *edx = 0; 6803 break; 6804 } 6805 6806 /* 6807 * SGX sub-leafs CPUID.0x12.{0x2..N} enumerate EPC sections. Retrieve 6808 * the EPC properties, e.g. confidentiality and integrity, from the 6809 * host's first EPC section, i.e. assume there is one EPC section or 6810 * that all EPC sections have the same security properties. 6811 */ 6812 if (count > 1) { 6813 uint64_t epc_addr, epc_size; 6814 6815 if (sgx_epc_get_section(count - 2, &epc_addr, &epc_size)) { 6816 *eax = *ebx = *ecx = *edx = 0; 6817 break; 6818 } 6819 host_cpuid(index, 2, eax, ebx, ecx, edx); 6820 *eax = (uint32_t)(epc_addr & 0xfffff000) | 0x1; 6821 *ebx = (uint32_t)(epc_addr >> 32); 6822 *ecx = (uint32_t)(epc_size & 0xfffff000) | (*ecx & 0xf); 6823 *edx = (uint32_t)(epc_size >> 32); 6824 break; 6825 } 6826 6827 /* 6828 * SGX sub-leafs CPUID.0x12.{0x0,0x1} are heavily dependent on hardware 6829 * and KVM, i.e. QEMU cannot emulate features to override what KVM 6830 * supports. Features can be further restricted by userspace, but not 6831 * made more permissive. 6832 */ 6833 x86_cpu_get_supported_cpuid(0x12, count, eax, ebx, ecx, edx); 6834 6835 if (count == 0) { 6836 *eax &= env->features[FEAT_SGX_12_0_EAX]; 6837 *ebx &= env->features[FEAT_SGX_12_0_EBX]; 6838 } else { 6839 *eax &= env->features[FEAT_SGX_12_1_EAX]; 6840 *ebx &= 0; /* ebx reserve */ 6841 *ecx &= env->features[FEAT_XSAVE_XCR0_LO]; 6842 *edx &= env->features[FEAT_XSAVE_XCR0_HI]; 6843 6844 /* FP and SSE are always allowed regardless of XSAVE/XCR0. */ 6845 *ecx |= XSTATE_FP_MASK | XSTATE_SSE_MASK; 6846 6847 /* Access to PROVISIONKEY requires additional credentials. */ 6848 if ((*eax & (1U << 4)) && 6849 !kvm_enable_sgx_provisioning(cs->kvm_state)) { 6850 *eax &= ~(1U << 4); 6851 } 6852 } 6853 #endif 6854 break; 6855 case 0x14: { 6856 /* Intel Processor Trace Enumeration */ 6857 *eax = 0; 6858 *ebx = 0; 6859 *ecx = 0; 6860 *edx = 0; 6861 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) || 6862 !kvm_enabled()) { 6863 break; 6864 } 6865 6866 /* 6867 * If these are changed, they should stay in sync with 6868 * x86_cpu_filter_features(). 6869 */ 6870 if (count == 0) { 6871 *eax = INTEL_PT_MAX_SUBLEAF; 6872 *ebx = INTEL_PT_MINIMAL_EBX; 6873 *ecx = INTEL_PT_MINIMAL_ECX; 6874 if (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP) { 6875 *ecx |= CPUID_14_0_ECX_LIP; 6876 } 6877 } else if (count == 1) { 6878 *eax = INTEL_PT_MTC_BITMAP | INTEL_PT_ADDR_RANGES_NUM; 6879 *ebx = INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP; 6880 } 6881 break; 6882 } 6883 case 0x1D: { 6884 /* AMX TILE, for now hardcoded for Sapphire Rapids*/ 6885 *eax = 0; 6886 *ebx = 0; 6887 *ecx = 0; 6888 *edx = 0; 6889 if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) { 6890 break; 6891 } 6892 6893 if (count == 0) { 6894 /* Highest numbered palette subleaf */ 6895 *eax = INTEL_AMX_TILE_MAX_SUBLEAF; 6896 } else if (count == 1) { 6897 *eax = INTEL_AMX_TOTAL_TILE_BYTES | 6898 (INTEL_AMX_BYTES_PER_TILE << 16); 6899 *ebx = INTEL_AMX_BYTES_PER_ROW | (INTEL_AMX_TILE_MAX_NAMES << 16); 6900 *ecx = INTEL_AMX_TILE_MAX_ROWS; 6901 } 6902 break; 6903 } 6904 case 0x1E: { 6905 /* AMX TMUL, for now hardcoded for Sapphire Rapids */ 6906 *eax = 0; 6907 *ebx = 0; 6908 *ecx = 0; 6909 *edx = 0; 6910 if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) { 6911 break; 6912 } 6913 6914 if (count == 0) { 6915 /* Highest numbered palette subleaf */ 6916 *ebx = INTEL_AMX_TMUL_MAX_K | (INTEL_AMX_TMUL_MAX_N << 8); 6917 } 6918 break; 6919 } 6920 case 0x24: { 6921 *eax = 0; 6922 *ebx = 0; 6923 *ecx = 0; 6924 *edx = 0; 6925 if ((env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) && count == 0) { 6926 *ebx = env->features[FEAT_24_0_EBX] | env->avx10_version; 6927 } 6928 break; 6929 } 6930 case 0x40000000: 6931 /* 6932 * CPUID code in kvm_arch_init_vcpu() ignores stuff 6933 * set here, but we restrict to TCG none the less. 6934 */ 6935 if (tcg_enabled() && cpu->expose_tcg) { 6936 memcpy(signature, "TCGTCGTCGTCG", 12); 6937 *eax = 0x40000001; 6938 *ebx = signature[0]; 6939 *ecx = signature[1]; 6940 *edx = signature[2]; 6941 } else { 6942 *eax = 0; 6943 *ebx = 0; 6944 *ecx = 0; 6945 *edx = 0; 6946 } 6947 break; 6948 case 0x40000001: 6949 *eax = 0; 6950 *ebx = 0; 6951 *ecx = 0; 6952 *edx = 0; 6953 break; 6954 case 0x80000000: 6955 *eax = env->cpuid_xlevel; 6956 *ebx = env->cpuid_vendor1; 6957 *edx = env->cpuid_vendor2; 6958 *ecx = env->cpuid_vendor3; 6959 break; 6960 case 0x80000001: 6961 *eax = env->cpuid_version; 6962 *ebx = 0; 6963 *ecx = env->features[FEAT_8000_0001_ECX]; 6964 *edx = env->features[FEAT_8000_0001_EDX]; 6965 6966 /* The Linux kernel checks for the CMPLegacy bit and 6967 * discards multiple thread information if it is set. 6968 * So don't set it here for Intel to make Linux guests happy. 6969 */ 6970 if (threads_per_pkg > 1) { 6971 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 || 6972 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 || 6973 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) { 6974 *ecx |= 1 << 1; /* CmpLegacy bit */ 6975 } 6976 } 6977 if (tcg_enabled() && env->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && 6978 !(env->hflags & HF_LMA_MASK)) { 6979 *edx &= ~CPUID_EXT2_SYSCALL; 6980 } 6981 break; 6982 case 0x80000002: 6983 case 0x80000003: 6984 case 0x80000004: 6985 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0]; 6986 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1]; 6987 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2]; 6988 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3]; 6989 break; 6990 case 0x80000005: 6991 /* cache info (L1 cache) */ 6992 if (cpu->cache_info_passthrough) { 6993 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 6994 break; 6995 } 6996 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | 6997 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES); 6998 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | 6999 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES); 7000 *ecx = encode_cache_cpuid80000005(env->cache_info_amd.l1d_cache); 7001 *edx = encode_cache_cpuid80000005(env->cache_info_amd.l1i_cache); 7002 break; 7003 case 0x80000006: 7004 /* cache info (L2 cache) */ 7005 if (cpu->cache_info_passthrough) { 7006 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 7007 break; 7008 } 7009 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | 7010 (L2_DTLB_2M_ENTRIES << 16) | 7011 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | 7012 (L2_ITLB_2M_ENTRIES); 7013 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | 7014 (L2_DTLB_4K_ENTRIES << 16) | 7015 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | 7016 (L2_ITLB_4K_ENTRIES); 7017 encode_cache_cpuid80000006(env->cache_info_amd.l2_cache, 7018 cpu->enable_l3_cache ? 7019 env->cache_info_amd.l3_cache : NULL, 7020 ecx, edx); 7021 break; 7022 case 0x80000007: 7023 *eax = 0; 7024 *ebx = env->features[FEAT_8000_0007_EBX]; 7025 *ecx = 0; 7026 *edx = env->features[FEAT_8000_0007_EDX]; 7027 break; 7028 case 0x80000008: 7029 /* virtual & phys address size in low 2 bytes. */ 7030 *eax = cpu->phys_bits; 7031 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 7032 /* 64 bit processor */ 7033 *eax |= (cpu_x86_virtual_addr_width(env) << 8); 7034 *eax |= (cpu->guest_phys_bits << 16); 7035 } 7036 *ebx = env->features[FEAT_8000_0008_EBX]; 7037 if (threads_per_pkg > 1) { 7038 /* 7039 * Bits 15:12 is "The number of bits in the initial 7040 * Core::X86::Apic::ApicId[ApicId] value that indicate 7041 * thread ID within a package". 7042 * Bits 7:0 is "The number of threads in the package is NC+1" 7043 */ 7044 *ecx = (apicid_pkg_offset(&topo_info) << 12) | 7045 (threads_per_pkg - 1); 7046 } else { 7047 *ecx = 0; 7048 } 7049 *edx = 0; 7050 break; 7051 case 0x8000000A: 7052 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { 7053 *eax = 0x00000001; /* SVM Revision */ 7054 *ebx = 0x00000010; /* nr of ASIDs */ 7055 *ecx = 0; 7056 *edx = env->features[FEAT_SVM]; /* optional features */ 7057 } else { 7058 *eax = 0; 7059 *ebx = 0; 7060 *ecx = 0; 7061 *edx = 0; 7062 } 7063 break; 7064 case 0x8000001D: 7065 *eax = 0; 7066 if (cpu->cache_info_passthrough) { 7067 x86_cpu_get_cache_cpuid(index, count, eax, ebx, ecx, edx); 7068 break; 7069 } 7070 switch (count) { 7071 case 0: /* L1 dcache info */ 7072 encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache, 7073 &topo_info, eax, ebx, ecx, edx); 7074 break; 7075 case 1: /* L1 icache info */ 7076 encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache, 7077 &topo_info, eax, ebx, ecx, edx); 7078 break; 7079 case 2: /* L2 cache info */ 7080 encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache, 7081 &topo_info, eax, ebx, ecx, edx); 7082 break; 7083 case 3: /* L3 cache info */ 7084 encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache, 7085 &topo_info, eax, ebx, ecx, edx); 7086 break; 7087 default: /* end of info */ 7088 *eax = *ebx = *ecx = *edx = 0; 7089 break; 7090 } 7091 if (cpu->amd_topoext_features_only) { 7092 *edx &= CACHE_NO_INVD_SHARING | CACHE_INCLUSIVE; 7093 } 7094 break; 7095 case 0x8000001E: 7096 if (cpu->core_id <= 255) { 7097 encode_topo_cpuid8000001e(cpu, &topo_info, eax, ebx, ecx, edx); 7098 } else { 7099 *eax = 0; 7100 *ebx = 0; 7101 *ecx = 0; 7102 *edx = 0; 7103 } 7104 break; 7105 case 0x80000022: 7106 *eax = *ebx = *ecx = *edx = 0; 7107 /* AMD Extended Performance Monitoring and Debug */ 7108 if (kvm_enabled() && cpu->enable_pmu && 7109 (env->features[FEAT_8000_0022_EAX] & CPUID_8000_0022_EAX_PERFMON_V2)) { 7110 *eax |= CPUID_8000_0022_EAX_PERFMON_V2; 7111 *ebx |= kvm_arch_get_supported_cpuid(cs->kvm_state, index, count, 7112 R_EBX) & 0xf; 7113 } 7114 break; 7115 case 0xC0000000: 7116 *eax = env->cpuid_xlevel2; 7117 *ebx = 0; 7118 *ecx = 0; 7119 *edx = 0; 7120 break; 7121 case 0xC0000001: 7122 /* Support for VIA CPU's CPUID instruction */ 7123 *eax = env->cpuid_version; 7124 *ebx = 0; 7125 *ecx = 0; 7126 *edx = env->features[FEAT_C000_0001_EDX]; 7127 break; 7128 case 0xC0000002: 7129 case 0xC0000003: 7130 case 0xC0000004: 7131 /* Reserved for the future, and now filled with zero */ 7132 *eax = 0; 7133 *ebx = 0; 7134 *ecx = 0; 7135 *edx = 0; 7136 break; 7137 case 0x8000001F: 7138 *eax = *ebx = *ecx = *edx = 0; 7139 if (sev_enabled()) { 7140 *eax = 0x2; 7141 *eax |= sev_es_enabled() ? 0x8 : 0; 7142 *eax |= sev_snp_enabled() ? 0x10 : 0; 7143 *ebx = sev_get_cbit_position() & 0x3f; /* EBX[5:0] */ 7144 *ebx |= (sev_get_reduced_phys_bits() & 0x3f) << 6; /* EBX[11:6] */ 7145 } 7146 break; 7147 case 0x80000021: 7148 *eax = *ebx = *ecx = *edx = 0; 7149 *eax = env->features[FEAT_8000_0021_EAX]; 7150 *ebx = env->features[FEAT_8000_0021_EBX]; 7151 break; 7152 default: 7153 /* reserved values: zero */ 7154 *eax = 0; 7155 *ebx = 0; 7156 *ecx = 0; 7157 *edx = 0; 7158 break; 7159 } 7160 } 7161 7162 static void x86_cpu_set_sgxlepubkeyhash(CPUX86State *env) 7163 { 7164 #ifndef CONFIG_USER_ONLY 7165 /* Those default values are defined in Skylake HW */ 7166 env->msr_ia32_sgxlepubkeyhash[0] = 0xa6053e051270b7acULL; 7167 env->msr_ia32_sgxlepubkeyhash[1] = 0x6cfbe8ba8b3b413dULL; 7168 env->msr_ia32_sgxlepubkeyhash[2] = 0xc4916d99f2b3735dULL; 7169 env->msr_ia32_sgxlepubkeyhash[3] = 0xd4f8c05909f9bb3bULL; 7170 #endif 7171 } 7172 7173 static bool cpuid_has_xsave_feature(CPUX86State *env, const ExtSaveArea *esa) 7174 { 7175 if (!esa->size) { 7176 return false; 7177 } 7178 7179 if (env->features[esa->feature] & esa->bits) { 7180 return true; 7181 } 7182 if (esa->feature == FEAT_7_0_EBX && esa->bits == CPUID_7_0_EBX_AVX512F 7183 && (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10)) { 7184 return true; 7185 } 7186 7187 return false; 7188 } 7189 7190 static void x86_cpu_reset_hold(Object *obj, ResetType type) 7191 { 7192 CPUState *cs = CPU(obj); 7193 X86CPU *cpu = X86_CPU(cs); 7194 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj); 7195 CPUX86State *env = &cpu->env; 7196 target_ulong cr4; 7197 uint64_t xcr0; 7198 int i; 7199 7200 if (xcc->parent_phases.hold) { 7201 xcc->parent_phases.hold(obj, type); 7202 } 7203 7204 memset(env, 0, offsetof(CPUX86State, end_reset_fields)); 7205 7206 if (tcg_enabled()) { 7207 cpu_init_fp_statuses(env); 7208 } 7209 7210 env->old_exception = -1; 7211 7212 /* init to reset state */ 7213 env->int_ctl = 0; 7214 env->hflags2 |= HF2_GIF_MASK; 7215 env->hflags2 |= HF2_VGIF_MASK; 7216 env->hflags &= ~HF_GUEST_MASK; 7217 7218 cpu_x86_update_cr0(env, 0x60000010); 7219 env->a20_mask = ~0x0; 7220 env->smbase = 0x30000; 7221 env->msr_smi_count = 0; 7222 7223 env->idt.limit = 0xffff; 7224 env->gdt.limit = 0xffff; 7225 env->ldt.limit = 0xffff; 7226 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT); 7227 env->tr.limit = 0xffff; 7228 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT); 7229 7230 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff, 7231 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK | 7232 DESC_R_MASK | DESC_A_MASK); 7233 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff, 7234 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7235 DESC_A_MASK); 7236 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff, 7237 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7238 DESC_A_MASK); 7239 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff, 7240 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7241 DESC_A_MASK); 7242 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff, 7243 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7244 DESC_A_MASK); 7245 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff, 7246 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7247 DESC_A_MASK); 7248 7249 env->eip = 0xfff0; 7250 env->regs[R_EDX] = env->cpuid_version; 7251 7252 env->eflags = 0x2; 7253 7254 /* FPU init */ 7255 for (i = 0; i < 8; i++) { 7256 env->fptags[i] = 1; 7257 } 7258 cpu_set_fpuc(env, 0x37f); 7259 7260 env->mxcsr = 0x1f80; 7261 /* All units are in INIT state. */ 7262 env->xstate_bv = 0; 7263 7264 env->pat = 0x0007040600070406ULL; 7265 7266 if (kvm_enabled()) { 7267 /* 7268 * KVM handles TSC = 0 specially and thinks we are hot-plugging 7269 * a new CPU, use 1 instead to force a reset. 7270 */ 7271 if (env->tsc != 0) { 7272 env->tsc = 1; 7273 } 7274 } else { 7275 env->tsc = 0; 7276 } 7277 7278 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT; 7279 if (env->features[FEAT_1_ECX] & CPUID_EXT_MONITOR) { 7280 env->msr_ia32_misc_enable |= MSR_IA32_MISC_ENABLE_MWAIT; 7281 } 7282 7283 memset(env->dr, 0, sizeof(env->dr)); 7284 env->dr[6] = DR6_FIXED_1; 7285 env->dr[7] = DR7_FIXED_1; 7286 cpu_breakpoint_remove_all(cs, BP_CPU); 7287 cpu_watchpoint_remove_all(cs, BP_CPU); 7288 7289 cr4 = 0; 7290 xcr0 = XSTATE_FP_MASK; 7291 7292 #ifdef CONFIG_USER_ONLY 7293 /* Enable all the features for user-mode. */ 7294 if (env->features[FEAT_1_EDX] & CPUID_SSE) { 7295 xcr0 |= XSTATE_SSE_MASK; 7296 } 7297 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 7298 const ExtSaveArea *esa = &x86_ext_save_areas[i]; 7299 if (!((1 << i) & CPUID_XSTATE_XCR0_MASK)) { 7300 continue; 7301 } 7302 if (cpuid_has_xsave_feature(env, esa)) { 7303 xcr0 |= 1ull << i; 7304 } 7305 } 7306 7307 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) { 7308 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK; 7309 } 7310 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) { 7311 cr4 |= CR4_FSGSBASE_MASK; 7312 } 7313 #endif 7314 7315 env->xcr0 = xcr0; 7316 cpu_x86_update_cr4(env, cr4); 7317 7318 /* 7319 * SDM 11.11.5 requires: 7320 * - IA32_MTRR_DEF_TYPE MSR.E = 0 7321 * - IA32_MTRR_PHYSMASKn.V = 0 7322 * All other bits are undefined. For simplification, zero it all. 7323 */ 7324 env->mtrr_deftype = 0; 7325 memset(env->mtrr_var, 0, sizeof(env->mtrr_var)); 7326 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed)); 7327 7328 env->interrupt_injected = -1; 7329 env->exception_nr = -1; 7330 env->exception_pending = 0; 7331 env->exception_injected = 0; 7332 env->exception_has_payload = false; 7333 env->exception_payload = 0; 7334 env->nmi_injected = false; 7335 env->triple_fault_pending = false; 7336 #if !defined(CONFIG_USER_ONLY) 7337 /* We hard-wire the BSP to the first CPU. */ 7338 apic_designate_bsp(cpu->apic_state, cs->cpu_index == 0); 7339 7340 cs->halted = !cpu_is_bsp(cpu); 7341 7342 if (kvm_enabled()) { 7343 kvm_arch_reset_vcpu(cpu); 7344 } 7345 7346 x86_cpu_set_sgxlepubkeyhash(env); 7347 7348 env->amd_tsc_scale_msr = MSR_AMD64_TSC_RATIO_DEFAULT; 7349 7350 #endif 7351 } 7352 7353 void x86_cpu_after_reset(X86CPU *cpu) 7354 { 7355 #ifndef CONFIG_USER_ONLY 7356 if (kvm_enabled()) { 7357 kvm_arch_after_reset_vcpu(cpu); 7358 } 7359 7360 if (cpu->apic_state) { 7361 device_cold_reset(cpu->apic_state); 7362 } 7363 #endif 7364 } 7365 7366 static void mce_init(X86CPU *cpu) 7367 { 7368 CPUX86State *cenv = &cpu->env; 7369 unsigned int bank; 7370 7371 if (((cenv->cpuid_version >> 8) & 0xf) >= 6 7372 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) == 7373 (CPUID_MCE | CPUID_MCA)) { 7374 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF | 7375 (cpu->enable_lmce ? MCG_LMCE_P : 0); 7376 cenv->mcg_ctl = ~(uint64_t)0; 7377 for (bank = 0; bank < MCE_BANKS_DEF; bank++) { 7378 cenv->mce_banks[bank * 4] = ~(uint64_t)0; 7379 } 7380 } 7381 } 7382 7383 static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value) 7384 { 7385 if (*min < value) { 7386 *min = value; 7387 } 7388 } 7389 7390 /* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */ 7391 static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w) 7392 { 7393 CPUX86State *env = &cpu->env; 7394 FeatureWordInfo *fi = &feature_word_info[w]; 7395 uint32_t eax = fi->cpuid.eax; 7396 uint32_t region = eax & 0xF0000000; 7397 7398 assert(feature_word_info[w].type == CPUID_FEATURE_WORD); 7399 if (!env->features[w]) { 7400 return; 7401 } 7402 7403 switch (region) { 7404 case 0x00000000: 7405 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax); 7406 break; 7407 case 0x80000000: 7408 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax); 7409 break; 7410 case 0xC0000000: 7411 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax); 7412 break; 7413 } 7414 7415 if (eax == 7) { 7416 x86_cpu_adjust_level(cpu, &env->cpuid_min_level_func7, 7417 fi->cpuid.ecx); 7418 } 7419 } 7420 7421 /* Calculate XSAVE components based on the configured CPU feature flags */ 7422 static void x86_cpu_enable_xsave_components(X86CPU *cpu) 7423 { 7424 CPUX86State *env = &cpu->env; 7425 int i; 7426 uint64_t mask; 7427 static bool request_perm; 7428 7429 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { 7430 env->features[FEAT_XSAVE_XCR0_LO] = 0; 7431 env->features[FEAT_XSAVE_XCR0_HI] = 0; 7432 env->features[FEAT_XSAVE_XSS_LO] = 0; 7433 env->features[FEAT_XSAVE_XSS_HI] = 0; 7434 return; 7435 } 7436 7437 mask = 0; 7438 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 7439 const ExtSaveArea *esa = &x86_ext_save_areas[i]; 7440 if (cpuid_has_xsave_feature(env, esa)) { 7441 mask |= (1ULL << i); 7442 } 7443 } 7444 7445 /* Only request permission for first vcpu */ 7446 if (kvm_enabled() && !request_perm) { 7447 kvm_request_xsave_components(cpu, mask); 7448 request_perm = true; 7449 } 7450 7451 env->features[FEAT_XSAVE_XCR0_LO] = mask & CPUID_XSTATE_XCR0_MASK; 7452 env->features[FEAT_XSAVE_XCR0_HI] = (mask & CPUID_XSTATE_XCR0_MASK) >> 32; 7453 env->features[FEAT_XSAVE_XSS_LO] = mask & CPUID_XSTATE_XSS_MASK; 7454 env->features[FEAT_XSAVE_XSS_HI] = (mask & CPUID_XSTATE_XSS_MASK) >> 32; 7455 } 7456 7457 /***** Steps involved on loading and filtering CPUID data 7458 * 7459 * When initializing and realizing a CPU object, the steps 7460 * involved in setting up CPUID data are: 7461 * 7462 * 1) Loading CPU model definition (X86CPUDefinition). This is 7463 * implemented by x86_cpu_load_model() and should be completely 7464 * transparent, as it is done automatically by instance_init. 7465 * No code should need to look at X86CPUDefinition structs 7466 * outside instance_init. 7467 * 7468 * 2) CPU expansion. This is done by realize before CPUID 7469 * filtering, and will make sure host/accelerator data is 7470 * loaded for CPU models that depend on host capabilities 7471 * (e.g. "host"). Done by x86_cpu_expand_features(). 7472 * 7473 * 3) CPUID filtering. This initializes extra data related to 7474 * CPUID, and checks if the host supports all capabilities 7475 * required by the CPU. Runnability of a CPU model is 7476 * determined at this step. Done by x86_cpu_filter_features(). 7477 * 7478 * Some operations don't require all steps to be performed. 7479 * More precisely: 7480 * 7481 * - CPU instance creation (instance_init) will run only CPU 7482 * model loading. CPU expansion can't run at instance_init-time 7483 * because host/accelerator data may be not available yet. 7484 * - CPU realization will perform both CPU model expansion and CPUID 7485 * filtering, and return an error in case one of them fails. 7486 * - query-cpu-definitions needs to run all 3 steps. It needs 7487 * to run CPUID filtering, as the 'unavailable-features' 7488 * field is set based on the filtering results. 7489 * - The query-cpu-model-expansion QMP command only needs to run 7490 * CPU model loading and CPU expansion. It should not filter 7491 * any CPUID data based on host capabilities. 7492 */ 7493 7494 /* Expand CPU configuration data, based on configured features 7495 * and host/accelerator capabilities when appropriate. 7496 */ 7497 void x86_cpu_expand_features(X86CPU *cpu, Error **errp) 7498 { 7499 CPUX86State *env = &cpu->env; 7500 FeatureWord w; 7501 int i; 7502 GList *l; 7503 7504 for (l = plus_features; l; l = l->next) { 7505 const char *prop = l->data; 7506 if (!object_property_set_bool(OBJECT(cpu), prop, true, errp)) { 7507 return; 7508 } 7509 } 7510 7511 for (l = minus_features; l; l = l->next) { 7512 const char *prop = l->data; 7513 if (!object_property_set_bool(OBJECT(cpu), prop, false, errp)) { 7514 return; 7515 } 7516 } 7517 7518 /*TODO: Now cpu->max_features doesn't overwrite features 7519 * set using QOM properties, and we can convert 7520 * plus_features & minus_features to global properties 7521 * inside x86_cpu_parse_featurestr() too. 7522 */ 7523 if (cpu->max_features) { 7524 for (w = 0; w < FEATURE_WORDS; w++) { 7525 /* Override only features that weren't set explicitly 7526 * by the user. 7527 */ 7528 env->features[w] |= 7529 x86_cpu_get_supported_feature_word(cpu, w) & 7530 ~env->user_features[w] & 7531 ~feature_word_info[w].no_autoenable_flags; 7532 } 7533 7534 if ((env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) && !env->avx10_version) { 7535 uint32_t eax, ebx, ecx, edx; 7536 x86_cpu_get_supported_cpuid(0x24, 0, &eax, &ebx, &ecx, &edx); 7537 env->avx10_version = ebx & 0xff; 7538 } 7539 } 7540 7541 for (i = 0; i < ARRAY_SIZE(feature_dependencies); i++) { 7542 FeatureDep *d = &feature_dependencies[i]; 7543 if (!(env->features[d->from.index] & d->from.mask)) { 7544 uint64_t unavailable_features = env->features[d->to.index] & d->to.mask; 7545 7546 /* Not an error unless the dependent feature was added explicitly. */ 7547 mark_unavailable_features(cpu, d->to.index, 7548 unavailable_features & env->user_features[d->to.index], 7549 "This feature depends on other features that were not requested"); 7550 7551 env->features[d->to.index] &= ~unavailable_features; 7552 } 7553 } 7554 7555 if (!kvm_enabled() || !cpu->expose_kvm) { 7556 env->features[FEAT_KVM] = 0; 7557 } 7558 7559 x86_cpu_enable_xsave_components(cpu); 7560 7561 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */ 7562 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX); 7563 if (cpu->full_cpuid_auto_level) { 7564 x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX); 7565 x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX); 7566 x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX); 7567 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX); 7568 x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EAX); 7569 x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EDX); 7570 x86_cpu_adjust_feat_level(cpu, FEAT_7_2_EDX); 7571 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX); 7572 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX); 7573 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX); 7574 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0008_EBX); 7575 x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX); 7576 x86_cpu_adjust_feat_level(cpu, FEAT_SVM); 7577 x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE); 7578 7579 /* Intel Processor Trace requires CPUID[0x14] */ 7580 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT)) { 7581 if (cpu->intel_pt_auto_level) { 7582 x86_cpu_adjust_level(cpu, &cpu->env.cpuid_min_level, 0x14); 7583 } else if (cpu->env.cpuid_min_level < 0x14) { 7584 mark_unavailable_features(cpu, FEAT_7_0_EBX, 7585 CPUID_7_0_EBX_INTEL_PT, 7586 "Intel PT need CPUID leaf 0x14, please set by \"-cpu ...,intel-pt=on,min-level=0x14\""); 7587 } 7588 } 7589 7590 /* 7591 * Intel CPU topology with multi-dies support requires CPUID[0x1F]. 7592 * For AMD Rome/Milan, cpuid level is 0x10, and guest OS should detect 7593 * extended toplogy by leaf 0xB. Only adjust it for Intel CPU, unless 7594 * cpu->vendor_cpuid_only has been unset for compatibility with older 7595 * machine types. 7596 */ 7597 if (x86_has_extended_topo(env->avail_cpu_topo) && 7598 (IS_INTEL_CPU(env) || !cpu->vendor_cpuid_only)) { 7599 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x1F); 7600 } 7601 7602 /* Advanced Vector Extensions 10 (AVX10) requires CPUID[0x24] */ 7603 if (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) { 7604 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x24); 7605 } 7606 7607 /* SVM requires CPUID[0x8000000A] */ 7608 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { 7609 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A); 7610 } 7611 7612 /* SEV requires CPUID[0x8000001F] */ 7613 if (sev_enabled()) { 7614 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F); 7615 } 7616 7617 if (env->features[FEAT_8000_0021_EAX]) { 7618 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x80000021); 7619 } 7620 7621 /* SGX requires CPUID[0x12] for EPC enumeration */ 7622 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX) { 7623 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x12); 7624 } 7625 } 7626 7627 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */ 7628 if (env->cpuid_level_func7 == UINT32_MAX) { 7629 env->cpuid_level_func7 = env->cpuid_min_level_func7; 7630 } 7631 if (env->cpuid_level == UINT32_MAX) { 7632 env->cpuid_level = env->cpuid_min_level; 7633 } 7634 if (env->cpuid_xlevel == UINT32_MAX) { 7635 env->cpuid_xlevel = env->cpuid_min_xlevel; 7636 } 7637 if (env->cpuid_xlevel2 == UINT32_MAX) { 7638 env->cpuid_xlevel2 = env->cpuid_min_xlevel2; 7639 } 7640 7641 if (kvm_enabled() && !kvm_hyperv_expand_features(cpu, errp)) { 7642 return; 7643 } 7644 } 7645 7646 /* 7647 * Finishes initialization of CPUID data, filters CPU feature 7648 * words based on host availability of each feature. 7649 * 7650 * Returns: true if any flag is not supported by the host, false otherwise. 7651 */ 7652 static bool x86_cpu_filter_features(X86CPU *cpu, bool verbose) 7653 { 7654 CPUX86State *env = &cpu->env; 7655 FeatureWord w; 7656 const char *prefix = NULL; 7657 bool have_filtered_features; 7658 7659 uint32_t eax_0, ebx_0, ecx_0, edx_0; 7660 uint32_t eax_1, ebx_1, ecx_1, edx_1; 7661 7662 if (verbose) { 7663 prefix = accel_uses_host_cpuid() 7664 ? "host doesn't support requested feature" 7665 : "TCG doesn't support requested feature"; 7666 } 7667 7668 for (w = 0; w < FEATURE_WORDS; w++) { 7669 uint64_t host_feat = 7670 x86_cpu_get_supported_feature_word(NULL, w); 7671 uint64_t requested_features = env->features[w]; 7672 uint64_t unavailable_features = requested_features & ~host_feat; 7673 mark_unavailable_features(cpu, w, unavailable_features, prefix); 7674 } 7675 7676 /* 7677 * Check that KVM actually allows the processor tracing features that 7678 * are advertised by cpu_x86_cpuid(). Keep these two in sync. 7679 */ 7680 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) && 7681 kvm_enabled()) { 7682 x86_cpu_get_supported_cpuid(0x14, 0, 7683 &eax_0, &ebx_0, &ecx_0, &edx_0); 7684 x86_cpu_get_supported_cpuid(0x14, 1, 7685 &eax_1, &ebx_1, &ecx_1, &edx_1); 7686 7687 if (!eax_0 || 7688 ((ebx_0 & INTEL_PT_MINIMAL_EBX) != INTEL_PT_MINIMAL_EBX) || 7689 ((ecx_0 & INTEL_PT_MINIMAL_ECX) != INTEL_PT_MINIMAL_ECX) || 7690 ((eax_1 & INTEL_PT_MTC_BITMAP) != INTEL_PT_MTC_BITMAP) || 7691 ((eax_1 & INTEL_PT_ADDR_RANGES_NUM_MASK) < 7692 INTEL_PT_ADDR_RANGES_NUM) || 7693 ((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) != 7694 (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) || 7695 ((ecx_0 & CPUID_14_0_ECX_LIP) != 7696 (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP))) { 7697 /* 7698 * Processor Trace capabilities aren't configurable, so if the 7699 * host can't emulate the capabilities we report on 7700 * cpu_x86_cpuid(), intel-pt can't be enabled on the current host. 7701 */ 7702 mark_unavailable_features(cpu, FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT, prefix); 7703 } 7704 } 7705 7706 have_filtered_features = x86_cpu_have_filtered_features(cpu); 7707 7708 if (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) { 7709 x86_cpu_get_supported_cpuid(0x24, 0, 7710 &eax_0, &ebx_0, &ecx_0, &edx_0); 7711 uint8_t version = ebx_0 & 0xff; 7712 7713 if (version < env->avx10_version) { 7714 if (prefix) { 7715 warn_report("%s: avx10.%d. Adjust to avx10.%d", 7716 prefix, env->avx10_version, version); 7717 } 7718 env->avx10_version = version; 7719 have_filtered_features = true; 7720 } 7721 } else if (env->avx10_version && prefix) { 7722 warn_report("%s: avx10.%d.", prefix, env->avx10_version); 7723 have_filtered_features = true; 7724 } 7725 7726 return have_filtered_features; 7727 } 7728 7729 static void x86_cpu_hyperv_realize(X86CPU *cpu) 7730 { 7731 size_t len; 7732 7733 /* Hyper-V vendor id */ 7734 if (!cpu->hyperv_vendor) { 7735 object_property_set_str(OBJECT(cpu), "hv-vendor-id", "Microsoft Hv", 7736 &error_abort); 7737 } 7738 len = strlen(cpu->hyperv_vendor); 7739 if (len > 12) { 7740 warn_report("hv-vendor-id truncated to 12 characters"); 7741 len = 12; 7742 } 7743 memset(cpu->hyperv_vendor_id, 0, 12); 7744 memcpy(cpu->hyperv_vendor_id, cpu->hyperv_vendor, len); 7745 7746 /* 'Hv#1' interface identification*/ 7747 cpu->hyperv_interface_id[0] = 0x31237648; 7748 cpu->hyperv_interface_id[1] = 0; 7749 cpu->hyperv_interface_id[2] = 0; 7750 cpu->hyperv_interface_id[3] = 0; 7751 7752 /* Hypervisor implementation limits */ 7753 cpu->hyperv_limits[0] = 64; 7754 cpu->hyperv_limits[1] = 0; 7755 cpu->hyperv_limits[2] = 0; 7756 } 7757 7758 static void x86_cpu_realizefn(DeviceState *dev, Error **errp) 7759 { 7760 CPUState *cs = CPU(dev); 7761 X86CPU *cpu = X86_CPU(dev); 7762 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev); 7763 CPUX86State *env = &cpu->env; 7764 Error *local_err = NULL; 7765 unsigned requested_lbr_fmt; 7766 7767 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) 7768 /* Use pc-relative instructions in system-mode */ 7769 tcg_cflags_set(cs, CF_PCREL); 7770 #endif 7771 7772 if (cpu->apic_id == UNASSIGNED_APIC_ID) { 7773 error_setg(errp, "apic-id property was not initialized properly"); 7774 return; 7775 } 7776 7777 /* 7778 * Process Hyper-V enlightenments. 7779 * Note: this currently has to happen before the expansion of CPU features. 7780 */ 7781 x86_cpu_hyperv_realize(cpu); 7782 7783 x86_cpu_expand_features(cpu, &local_err); 7784 if (local_err) { 7785 goto out; 7786 } 7787 7788 /* 7789 * Override env->features[FEAT_PERF_CAPABILITIES].LBR_FMT 7790 * with user-provided setting. 7791 */ 7792 if (cpu->lbr_fmt != ~PERF_CAP_LBR_FMT) { 7793 if ((cpu->lbr_fmt & PERF_CAP_LBR_FMT) != cpu->lbr_fmt) { 7794 error_setg(errp, "invalid lbr-fmt"); 7795 return; 7796 } 7797 env->features[FEAT_PERF_CAPABILITIES] &= ~PERF_CAP_LBR_FMT; 7798 env->features[FEAT_PERF_CAPABILITIES] |= cpu->lbr_fmt; 7799 } 7800 7801 /* 7802 * vPMU LBR is supported when 1) KVM is enabled 2) Option pmu=on and 7803 * 3)vPMU LBR format matches that of host setting. 7804 */ 7805 requested_lbr_fmt = 7806 env->features[FEAT_PERF_CAPABILITIES] & PERF_CAP_LBR_FMT; 7807 if (requested_lbr_fmt && kvm_enabled()) { 7808 uint64_t host_perf_cap = 7809 x86_cpu_get_supported_feature_word(NULL, FEAT_PERF_CAPABILITIES); 7810 unsigned host_lbr_fmt = host_perf_cap & PERF_CAP_LBR_FMT; 7811 7812 if (!cpu->enable_pmu) { 7813 error_setg(errp, "vPMU: LBR is unsupported without pmu=on"); 7814 return; 7815 } 7816 if (requested_lbr_fmt != host_lbr_fmt) { 7817 error_setg(errp, "vPMU: the lbr-fmt value (0x%x) does not match " 7818 "the host value (0x%x).", 7819 requested_lbr_fmt, host_lbr_fmt); 7820 return; 7821 } 7822 } 7823 7824 if (x86_cpu_filter_features(cpu, cpu->check_cpuid || cpu->enforce_cpuid)) { 7825 if (cpu->enforce_cpuid) { 7826 error_setg(&local_err, 7827 accel_uses_host_cpuid() ? 7828 "Host doesn't support requested features" : 7829 "TCG doesn't support requested features"); 7830 goto out; 7831 } 7832 } 7833 7834 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on 7835 * CPUID[1].EDX. 7836 */ 7837 if (IS_AMD_CPU(env)) { 7838 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES; 7839 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX] 7840 & CPUID_EXT2_AMD_ALIASES); 7841 } 7842 7843 x86_cpu_set_sgxlepubkeyhash(env); 7844 7845 /* 7846 * note: the call to the framework needs to happen after feature expansion, 7847 * but before the checks/modifications to ucode_rev, mwait, phys_bits. 7848 * These may be set by the accel-specific code, 7849 * and the results are subsequently checked / assumed in this function. 7850 */ 7851 cpu_exec_realizefn(cs, &local_err); 7852 if (local_err != NULL) { 7853 error_propagate(errp, local_err); 7854 return; 7855 } 7856 7857 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) { 7858 g_autofree char *name = x86_cpu_class_get_model_name(xcc); 7859 error_setg(&local_err, "CPU model '%s' requires KVM or HVF", name); 7860 goto out; 7861 } 7862 7863 if (cpu->guest_phys_bits == -1) { 7864 /* 7865 * If it was not set by the user, or by the accelerator via 7866 * cpu_exec_realizefn, clear. 7867 */ 7868 cpu->guest_phys_bits = 0; 7869 } 7870 7871 if (cpu->ucode_rev == 0) { 7872 /* 7873 * The default is the same as KVM's. Note that this check 7874 * needs to happen after the evenual setting of ucode_rev in 7875 * accel-specific code in cpu_exec_realizefn. 7876 */ 7877 if (IS_AMD_CPU(env)) { 7878 cpu->ucode_rev = 0x01000065; 7879 } else { 7880 cpu->ucode_rev = 0x100000000ULL; 7881 } 7882 } 7883 7884 /* 7885 * mwait extended info: needed for Core compatibility 7886 * We always wake on interrupt even if host does not have the capability. 7887 * 7888 * requires the accel-specific code in cpu_exec_realizefn to 7889 * have already acquired the CPUID data into cpu->mwait. 7890 */ 7891 cpu->mwait.ecx |= CPUID_MWAIT_EMX | CPUID_MWAIT_IBE; 7892 7893 /* For 64bit systems think about the number of physical bits to present. 7894 * ideally this should be the same as the host; anything other than matching 7895 * the host can cause incorrect guest behaviour. 7896 * QEMU used to pick the magic value of 40 bits that corresponds to 7897 * consumer AMD devices but nothing else. 7898 * 7899 * Note that this code assumes features expansion has already been done 7900 * (as it checks for CPUID_EXT2_LM), and also assumes that potential 7901 * phys_bits adjustments to match the host have been already done in 7902 * accel-specific code in cpu_exec_realizefn. 7903 */ 7904 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 7905 if (cpu->phys_bits && 7906 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS || 7907 cpu->phys_bits < 32)) { 7908 error_setg(errp, "phys-bits should be between 32 and %u " 7909 " (but is %u)", 7910 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits); 7911 return; 7912 } 7913 /* 7914 * 0 means it was not explicitly set by the user (or by machine 7915 * compat_props or by the host code in host-cpu.c). 7916 * In this case, the default is the value used by TCG (40). 7917 */ 7918 if (cpu->phys_bits == 0) { 7919 cpu->phys_bits = TCG_PHYS_ADDR_BITS; 7920 } 7921 if (cpu->guest_phys_bits && 7922 (cpu->guest_phys_bits > cpu->phys_bits || 7923 cpu->guest_phys_bits < 32)) { 7924 error_setg(errp, "guest-phys-bits should be between 32 and %u " 7925 " (but is %u)", 7926 cpu->phys_bits, cpu->guest_phys_bits); 7927 return; 7928 } 7929 } else { 7930 /* For 32 bit systems don't use the user set value, but keep 7931 * phys_bits consistent with what we tell the guest. 7932 */ 7933 if (cpu->phys_bits != 0) { 7934 error_setg(errp, "phys-bits is not user-configurable in 32 bit"); 7935 return; 7936 } 7937 if (cpu->guest_phys_bits != 0) { 7938 error_setg(errp, "guest-phys-bits is not user-configurable in 32 bit"); 7939 return; 7940 } 7941 7942 if (env->features[FEAT_1_EDX] & (CPUID_PSE36 | CPUID_PAE)) { 7943 cpu->phys_bits = 36; 7944 } else { 7945 cpu->phys_bits = 32; 7946 } 7947 } 7948 7949 /* Cache information initialization */ 7950 if (!cpu->legacy_cache) { 7951 const CPUCaches *cache_info = 7952 x86_cpu_get_versioned_cache_info(cpu, xcc->model); 7953 7954 if (!xcc->model || !cache_info) { 7955 g_autofree char *name = x86_cpu_class_get_model_name(xcc); 7956 error_setg(errp, 7957 "CPU model '%s' doesn't support legacy-cache=off", name); 7958 return; 7959 } 7960 env->cache_info_cpuid2 = env->cache_info_cpuid4 = env->cache_info_amd = 7961 *cache_info; 7962 } else { 7963 /* Build legacy cache information */ 7964 env->cache_info_cpuid2.l1d_cache = &legacy_l1d_cache; 7965 env->cache_info_cpuid2.l1i_cache = &legacy_l1i_cache; 7966 env->cache_info_cpuid2.l2_cache = &legacy_l2_cache_cpuid2; 7967 env->cache_info_cpuid2.l3_cache = &legacy_l3_cache; 7968 7969 env->cache_info_cpuid4.l1d_cache = &legacy_l1d_cache; 7970 env->cache_info_cpuid4.l1i_cache = &legacy_l1i_cache; 7971 env->cache_info_cpuid4.l2_cache = &legacy_l2_cache; 7972 env->cache_info_cpuid4.l3_cache = &legacy_l3_cache; 7973 7974 env->cache_info_amd.l1d_cache = &legacy_l1d_cache_amd; 7975 env->cache_info_amd.l1i_cache = &legacy_l1i_cache_amd; 7976 env->cache_info_amd.l2_cache = &legacy_l2_cache_amd; 7977 env->cache_info_amd.l3_cache = &legacy_l3_cache; 7978 } 7979 7980 #ifndef CONFIG_USER_ONLY 7981 MachineState *ms = MACHINE(qdev_get_machine()); 7982 qemu_register_reset(x86_cpu_machine_reset_cb, cpu); 7983 7984 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || ms->smp.cpus > 1) { 7985 x86_cpu_apic_create(cpu, &local_err); 7986 if (local_err != NULL) { 7987 goto out; 7988 } 7989 } 7990 #endif 7991 7992 mce_init(cpu); 7993 7994 x86_cpu_gdb_init(cs); 7995 qemu_init_vcpu(cs); 7996 7997 /* 7998 * Most Intel and certain AMD CPUs support hyperthreading. Even though QEMU 7999 * fixes this issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX 8000 * based on inputs (sockets,cores,threads), it is still better to give 8001 * users a warning. 8002 * 8003 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise 8004 * cs->nr_threads hasn't be populated yet and the checking is incorrect. 8005 */ 8006 if (IS_AMD_CPU(env) && 8007 !(env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) && 8008 cs->nr_threads > 1) { 8009 warn_report_once("This family of AMD CPU doesn't support " 8010 "hyperthreading(%d). Please configure -smp " 8011 "options properly or try enabling topoext " 8012 "feature.", cs->nr_threads); 8013 } 8014 8015 #ifndef CONFIG_USER_ONLY 8016 x86_cpu_apic_realize(cpu, &local_err); 8017 if (local_err != NULL) { 8018 goto out; 8019 } 8020 #endif /* !CONFIG_USER_ONLY */ 8021 cpu_reset(cs); 8022 8023 xcc->parent_realize(dev, &local_err); 8024 8025 out: 8026 if (local_err != NULL) { 8027 error_propagate(errp, local_err); 8028 return; 8029 } 8030 } 8031 8032 static void x86_cpu_unrealizefn(DeviceState *dev) 8033 { 8034 X86CPU *cpu = X86_CPU(dev); 8035 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev); 8036 8037 #ifndef CONFIG_USER_ONLY 8038 cpu_remove_sync(CPU(dev)); 8039 qemu_unregister_reset(x86_cpu_machine_reset_cb, dev); 8040 #endif 8041 8042 if (cpu->apic_state) { 8043 object_unparent(OBJECT(cpu->apic_state)); 8044 cpu->apic_state = NULL; 8045 } 8046 8047 xcc->parent_unrealize(dev); 8048 } 8049 8050 typedef struct BitProperty { 8051 FeatureWord w; 8052 uint64_t mask; 8053 } BitProperty; 8054 8055 static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name, 8056 void *opaque, Error **errp) 8057 { 8058 X86CPU *cpu = X86_CPU(obj); 8059 BitProperty *fp = opaque; 8060 uint64_t f = cpu->env.features[fp->w]; 8061 bool value = (f & fp->mask) == fp->mask; 8062 visit_type_bool(v, name, &value, errp); 8063 } 8064 8065 static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name, 8066 void *opaque, Error **errp) 8067 { 8068 DeviceState *dev = DEVICE(obj); 8069 X86CPU *cpu = X86_CPU(obj); 8070 BitProperty *fp = opaque; 8071 bool value; 8072 8073 if (dev->realized) { 8074 qdev_prop_set_after_realize(dev, name, errp); 8075 return; 8076 } 8077 8078 if (!visit_type_bool(v, name, &value, errp)) { 8079 return; 8080 } 8081 8082 if (value) { 8083 cpu->env.features[fp->w] |= fp->mask; 8084 } else { 8085 cpu->env.features[fp->w] &= ~fp->mask; 8086 } 8087 cpu->env.user_features[fp->w] |= fp->mask; 8088 } 8089 8090 /* Register a boolean property to get/set a single bit in a uint32_t field. 8091 * 8092 * The same property name can be registered multiple times to make it affect 8093 * multiple bits in the same FeatureWord. In that case, the getter will return 8094 * true only if all bits are set. 8095 */ 8096 static void x86_cpu_register_bit_prop(X86CPUClass *xcc, 8097 const char *prop_name, 8098 FeatureWord w, 8099 int bitnr) 8100 { 8101 ObjectClass *oc = OBJECT_CLASS(xcc); 8102 BitProperty *fp; 8103 ObjectProperty *op; 8104 uint64_t mask = (1ULL << bitnr); 8105 8106 op = object_class_property_find(oc, prop_name); 8107 if (op) { 8108 fp = op->opaque; 8109 assert(fp->w == w); 8110 fp->mask |= mask; 8111 } else { 8112 fp = g_new0(BitProperty, 1); 8113 fp->w = w; 8114 fp->mask = mask; 8115 object_class_property_add(oc, prop_name, "bool", 8116 x86_cpu_get_bit_prop, 8117 x86_cpu_set_bit_prop, 8118 NULL, fp); 8119 } 8120 } 8121 8122 static void x86_cpu_register_feature_bit_props(X86CPUClass *xcc, 8123 FeatureWord w, 8124 int bitnr) 8125 { 8126 FeatureWordInfo *fi = &feature_word_info[w]; 8127 const char *name = fi->feat_names[bitnr]; 8128 8129 if (!name) { 8130 return; 8131 } 8132 8133 /* Property names should use "-" instead of "_". 8134 * Old names containing underscores are registered as aliases 8135 * using object_property_add_alias() 8136 */ 8137 assert(!strchr(name, '_')); 8138 /* aliases don't use "|" delimiters anymore, they are registered 8139 * manually using object_property_add_alias() */ 8140 assert(!strchr(name, '|')); 8141 x86_cpu_register_bit_prop(xcc, name, w, bitnr); 8142 } 8143 8144 static void x86_cpu_post_initfn(Object *obj) 8145 { 8146 static bool first = true; 8147 uint64_t supported_xcr0; 8148 int i; 8149 8150 if (first) { 8151 first = false; 8152 8153 supported_xcr0 = 8154 ((uint64_t) x86_cpu_get_supported_feature_word(NULL, FEAT_XSAVE_XCR0_HI) << 32) | 8155 x86_cpu_get_supported_feature_word(NULL, FEAT_XSAVE_XCR0_LO); 8156 8157 for (i = XSTATE_SSE_BIT + 1; i < XSAVE_STATE_AREA_COUNT; i++) { 8158 ExtSaveArea *esa = &x86_ext_save_areas[i]; 8159 8160 if (!(supported_xcr0 & (1 << i))) { 8161 esa->size = 0; 8162 } 8163 } 8164 } 8165 8166 accel_cpu_instance_init(CPU(obj)); 8167 } 8168 8169 static void x86_cpu_init_default_topo(X86CPU *cpu) 8170 { 8171 CPUX86State *env = &cpu->env; 8172 8173 env->nr_modules = 1; 8174 env->nr_dies = 1; 8175 8176 /* thread, core and socket levels are set by default. */ 8177 set_bit(CPU_TOPOLOGY_LEVEL_THREAD, env->avail_cpu_topo); 8178 set_bit(CPU_TOPOLOGY_LEVEL_CORE, env->avail_cpu_topo); 8179 set_bit(CPU_TOPOLOGY_LEVEL_SOCKET, env->avail_cpu_topo); 8180 } 8181 8182 static void x86_cpu_initfn(Object *obj) 8183 { 8184 X86CPU *cpu = X86_CPU(obj); 8185 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj); 8186 CPUX86State *env = &cpu->env; 8187 8188 x86_cpu_init_default_topo(cpu); 8189 8190 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo", 8191 x86_cpu_get_feature_words, 8192 NULL, NULL, (void *)env->features); 8193 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo", 8194 x86_cpu_get_feature_words, 8195 NULL, NULL, (void *)cpu->filtered_features); 8196 8197 object_property_add_alias(obj, "sse3", obj, "pni"); 8198 object_property_add_alias(obj, "pclmuldq", obj, "pclmulqdq"); 8199 object_property_add_alias(obj, "sse4-1", obj, "sse4.1"); 8200 object_property_add_alias(obj, "sse4-2", obj, "sse4.2"); 8201 object_property_add_alias(obj, "xd", obj, "nx"); 8202 object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt"); 8203 object_property_add_alias(obj, "i64", obj, "lm"); 8204 8205 object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl"); 8206 object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust"); 8207 object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt"); 8208 object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm"); 8209 object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy"); 8210 object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr"); 8211 object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core"); 8212 object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb"); 8213 object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay"); 8214 object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu"); 8215 object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf"); 8216 object_property_add_alias(obj, "kvm_asyncpf_int", obj, "kvm-asyncpf-int"); 8217 object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time"); 8218 object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi"); 8219 object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt"); 8220 object_property_add_alias(obj, "kvm_poll_control", obj, "kvm-poll-control"); 8221 object_property_add_alias(obj, "svm_lock", obj, "svm-lock"); 8222 object_property_add_alias(obj, "nrip_save", obj, "nrip-save"); 8223 object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale"); 8224 object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean"); 8225 object_property_add_alias(obj, "pause_filter", obj, "pause-filter"); 8226 object_property_add_alias(obj, "sse4_1", obj, "sse4.1"); 8227 object_property_add_alias(obj, "sse4_2", obj, "sse4.2"); 8228 8229 object_property_add_alias(obj, "hv-apicv", obj, "hv-avic"); 8230 cpu->lbr_fmt = ~PERF_CAP_LBR_FMT; 8231 object_property_add_alias(obj, "lbr_fmt", obj, "lbr-fmt"); 8232 8233 if (xcc->model) { 8234 x86_cpu_load_model(cpu, xcc->model); 8235 } 8236 } 8237 8238 static int64_t x86_cpu_get_arch_id(CPUState *cs) 8239 { 8240 X86CPU *cpu = X86_CPU(cs); 8241 8242 return cpu->apic_id; 8243 } 8244 8245 #if !defined(CONFIG_USER_ONLY) 8246 static bool x86_cpu_get_paging_enabled(const CPUState *cs) 8247 { 8248 X86CPU *cpu = X86_CPU(cs); 8249 8250 return cpu->env.cr[0] & CR0_PG_MASK; 8251 } 8252 #endif /* !CONFIG_USER_ONLY */ 8253 8254 static void x86_cpu_set_pc(CPUState *cs, vaddr value) 8255 { 8256 X86CPU *cpu = X86_CPU(cs); 8257 8258 cpu->env.eip = value; 8259 } 8260 8261 static vaddr x86_cpu_get_pc(CPUState *cs) 8262 { 8263 X86CPU *cpu = X86_CPU(cs); 8264 8265 /* Match cpu_get_tb_cpu_state. */ 8266 return cpu->env.eip + cpu->env.segs[R_CS].base; 8267 } 8268 8269 int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request) 8270 { 8271 X86CPU *cpu = X86_CPU(cs); 8272 CPUX86State *env = &cpu->env; 8273 8274 #if !defined(CONFIG_USER_ONLY) 8275 if (interrupt_request & CPU_INTERRUPT_POLL) { 8276 return CPU_INTERRUPT_POLL; 8277 } 8278 #endif 8279 if (interrupt_request & CPU_INTERRUPT_SIPI) { 8280 return CPU_INTERRUPT_SIPI; 8281 } 8282 8283 if (env->hflags2 & HF2_GIF_MASK) { 8284 if ((interrupt_request & CPU_INTERRUPT_SMI) && 8285 !(env->hflags & HF_SMM_MASK)) { 8286 return CPU_INTERRUPT_SMI; 8287 } else if ((interrupt_request & CPU_INTERRUPT_NMI) && 8288 !(env->hflags2 & HF2_NMI_MASK)) { 8289 return CPU_INTERRUPT_NMI; 8290 } else if (interrupt_request & CPU_INTERRUPT_MCE) { 8291 return CPU_INTERRUPT_MCE; 8292 } else if ((interrupt_request & CPU_INTERRUPT_HARD) && 8293 (((env->hflags2 & HF2_VINTR_MASK) && 8294 (env->hflags2 & HF2_HIF_MASK)) || 8295 (!(env->hflags2 & HF2_VINTR_MASK) && 8296 (env->eflags & IF_MASK && 8297 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) { 8298 return CPU_INTERRUPT_HARD; 8299 #if !defined(CONFIG_USER_ONLY) 8300 } else if (env->hflags2 & HF2_VGIF_MASK) { 8301 if((interrupt_request & CPU_INTERRUPT_VIRQ) && 8302 (env->eflags & IF_MASK) && 8303 !(env->hflags & HF_INHIBIT_IRQ_MASK)) { 8304 return CPU_INTERRUPT_VIRQ; 8305 } 8306 #endif 8307 } 8308 } 8309 8310 return 0; 8311 } 8312 8313 static bool x86_cpu_has_work(CPUState *cs) 8314 { 8315 return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0; 8316 } 8317 8318 int x86_mmu_index_pl(CPUX86State *env, unsigned pl) 8319 { 8320 int mmu_index_32 = (env->hflags & HF_CS64_MASK) ? 0 : 1; 8321 int mmu_index_base = 8322 pl == 3 ? MMU_USER64_IDX : 8323 !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP64_IDX : 8324 (env->eflags & AC_MASK) ? MMU_KNOSMAP64_IDX : MMU_KSMAP64_IDX; 8325 8326 return mmu_index_base + mmu_index_32; 8327 } 8328 8329 static int x86_cpu_mmu_index(CPUState *cs, bool ifetch) 8330 { 8331 CPUX86State *env = cpu_env(cs); 8332 return x86_mmu_index_pl(env, env->hflags & HF_CPL_MASK); 8333 } 8334 8335 static int x86_mmu_index_kernel_pl(CPUX86State *env, unsigned pl) 8336 { 8337 int mmu_index_32 = (env->hflags & HF_LMA_MASK) ? 0 : 1; 8338 int mmu_index_base = 8339 !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP64_IDX : 8340 (pl < 3 && (env->eflags & AC_MASK) 8341 ? MMU_KNOSMAP64_IDX : MMU_KSMAP64_IDX); 8342 8343 return mmu_index_base + mmu_index_32; 8344 } 8345 8346 int cpu_mmu_index_kernel(CPUX86State *env) 8347 { 8348 return x86_mmu_index_kernel_pl(env, env->hflags & HF_CPL_MASK); 8349 } 8350 8351 static void x86_disas_set_info(CPUState *cs, disassemble_info *info) 8352 { 8353 X86CPU *cpu = X86_CPU(cs); 8354 CPUX86State *env = &cpu->env; 8355 8356 info->mach = (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64 8357 : env->hflags & HF_CS32_MASK ? bfd_mach_i386_i386 8358 : bfd_mach_i386_i8086); 8359 8360 info->cap_arch = CS_ARCH_X86; 8361 info->cap_mode = (env->hflags & HF_CS64_MASK ? CS_MODE_64 8362 : env->hflags & HF_CS32_MASK ? CS_MODE_32 8363 : CS_MODE_16); 8364 info->cap_insn_unit = 1; 8365 info->cap_insn_split = 8; 8366 } 8367 8368 void x86_update_hflags(CPUX86State *env) 8369 { 8370 uint32_t hflags; 8371 #define HFLAG_COPY_MASK \ 8372 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \ 8373 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \ 8374 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \ 8375 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK) 8376 8377 hflags = env->hflags & HFLAG_COPY_MASK; 8378 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK; 8379 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT); 8380 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) & 8381 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK); 8382 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK)); 8383 8384 if (env->cr[4] & CR4_OSFXSR_MASK) { 8385 hflags |= HF_OSFXSR_MASK; 8386 } 8387 8388 if (env->efer & MSR_EFER_LMA) { 8389 hflags |= HF_LMA_MASK; 8390 } 8391 8392 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) { 8393 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; 8394 } else { 8395 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >> 8396 (DESC_B_SHIFT - HF_CS32_SHIFT); 8397 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >> 8398 (DESC_B_SHIFT - HF_SS32_SHIFT); 8399 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) || 8400 !(hflags & HF_CS32_MASK)) { 8401 hflags |= HF_ADDSEG_MASK; 8402 } else { 8403 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base | 8404 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT; 8405 } 8406 } 8407 env->hflags = hflags; 8408 } 8409 8410 static Property x86_cpu_properties[] = { 8411 #ifdef CONFIG_USER_ONLY 8412 /* apic_id = 0 by default for *-user, see commit 9886e834 */ 8413 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0), 8414 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0), 8415 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0), 8416 DEFINE_PROP_INT32("module-id", X86CPU, module_id, 0), 8417 DEFINE_PROP_INT32("die-id", X86CPU, die_id, 0), 8418 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0), 8419 #else 8420 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID), 8421 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1), 8422 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1), 8423 DEFINE_PROP_INT32("module-id", X86CPU, module_id, -1), 8424 DEFINE_PROP_INT32("die-id", X86CPU, die_id, -1), 8425 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1), 8426 #endif 8427 DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID), 8428 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false), 8429 DEFINE_PROP_UINT64_CHECKMASK("lbr-fmt", X86CPU, lbr_fmt, PERF_CAP_LBR_FMT), 8430 8431 DEFINE_PROP_UINT32("hv-spinlocks", X86CPU, hyperv_spinlock_attempts, 8432 HYPERV_SPINLOCK_NEVER_NOTIFY), 8433 DEFINE_PROP_BIT64("hv-relaxed", X86CPU, hyperv_features, 8434 HYPERV_FEAT_RELAXED, 0), 8435 DEFINE_PROP_BIT64("hv-vapic", X86CPU, hyperv_features, 8436 HYPERV_FEAT_VAPIC, 0), 8437 DEFINE_PROP_BIT64("hv-time", X86CPU, hyperv_features, 8438 HYPERV_FEAT_TIME, 0), 8439 DEFINE_PROP_BIT64("hv-crash", X86CPU, hyperv_features, 8440 HYPERV_FEAT_CRASH, 0), 8441 DEFINE_PROP_BIT64("hv-reset", X86CPU, hyperv_features, 8442 HYPERV_FEAT_RESET, 0), 8443 DEFINE_PROP_BIT64("hv-vpindex", X86CPU, hyperv_features, 8444 HYPERV_FEAT_VPINDEX, 0), 8445 DEFINE_PROP_BIT64("hv-runtime", X86CPU, hyperv_features, 8446 HYPERV_FEAT_RUNTIME, 0), 8447 DEFINE_PROP_BIT64("hv-synic", X86CPU, hyperv_features, 8448 HYPERV_FEAT_SYNIC, 0), 8449 DEFINE_PROP_BIT64("hv-stimer", X86CPU, hyperv_features, 8450 HYPERV_FEAT_STIMER, 0), 8451 DEFINE_PROP_BIT64("hv-frequencies", X86CPU, hyperv_features, 8452 HYPERV_FEAT_FREQUENCIES, 0), 8453 DEFINE_PROP_BIT64("hv-reenlightenment", X86CPU, hyperv_features, 8454 HYPERV_FEAT_REENLIGHTENMENT, 0), 8455 DEFINE_PROP_BIT64("hv-tlbflush", X86CPU, hyperv_features, 8456 HYPERV_FEAT_TLBFLUSH, 0), 8457 DEFINE_PROP_BIT64("hv-evmcs", X86CPU, hyperv_features, 8458 HYPERV_FEAT_EVMCS, 0), 8459 DEFINE_PROP_BIT64("hv-ipi", X86CPU, hyperv_features, 8460 HYPERV_FEAT_IPI, 0), 8461 DEFINE_PROP_BIT64("hv-stimer-direct", X86CPU, hyperv_features, 8462 HYPERV_FEAT_STIMER_DIRECT, 0), 8463 DEFINE_PROP_BIT64("hv-avic", X86CPU, hyperv_features, 8464 HYPERV_FEAT_AVIC, 0), 8465 DEFINE_PROP_BIT64("hv-emsr-bitmap", X86CPU, hyperv_features, 8466 HYPERV_FEAT_MSR_BITMAP, 0), 8467 DEFINE_PROP_BIT64("hv-xmm-input", X86CPU, hyperv_features, 8468 HYPERV_FEAT_XMM_INPUT, 0), 8469 DEFINE_PROP_BIT64("hv-tlbflush-ext", X86CPU, hyperv_features, 8470 HYPERV_FEAT_TLBFLUSH_EXT, 0), 8471 DEFINE_PROP_BIT64("hv-tlbflush-direct", X86CPU, hyperv_features, 8472 HYPERV_FEAT_TLBFLUSH_DIRECT, 0), 8473 DEFINE_PROP_ON_OFF_AUTO("hv-no-nonarch-coresharing", X86CPU, 8474 hyperv_no_nonarch_cs, ON_OFF_AUTO_OFF), 8475 #ifdef CONFIG_SYNDBG 8476 DEFINE_PROP_BIT64("hv-syndbg", X86CPU, hyperv_features, 8477 HYPERV_FEAT_SYNDBG, 0), 8478 #endif 8479 DEFINE_PROP_BOOL("hv-passthrough", X86CPU, hyperv_passthrough, false), 8480 DEFINE_PROP_BOOL("hv-enforce-cpuid", X86CPU, hyperv_enforce_cpuid, false), 8481 8482 /* WS2008R2 identify by default */ 8483 DEFINE_PROP_UINT32("hv-version-id-build", X86CPU, hyperv_ver_id_build, 8484 0x3839), 8485 DEFINE_PROP_UINT16("hv-version-id-major", X86CPU, hyperv_ver_id_major, 8486 0x000A), 8487 DEFINE_PROP_UINT16("hv-version-id-minor", X86CPU, hyperv_ver_id_minor, 8488 0x0000), 8489 DEFINE_PROP_UINT32("hv-version-id-spack", X86CPU, hyperv_ver_id_sp, 0), 8490 DEFINE_PROP_UINT8("hv-version-id-sbranch", X86CPU, hyperv_ver_id_sb, 0), 8491 DEFINE_PROP_UINT32("hv-version-id-snumber", X86CPU, hyperv_ver_id_sn, 0), 8492 8493 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true), 8494 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false), 8495 DEFINE_PROP_BOOL("x-force-features", X86CPU, force_features, false), 8496 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true), 8497 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0), 8498 DEFINE_PROP_UINT32("guest-phys-bits", X86CPU, guest_phys_bits, -1), 8499 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false), 8500 DEFINE_PROP_UINT8("host-phys-bits-limit", X86CPU, host_phys_bits_limit, 0), 8501 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true), 8502 DEFINE_PROP_UINT32("level-func7", X86CPU, env.cpuid_level_func7, 8503 UINT32_MAX), 8504 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX), 8505 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX), 8506 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX), 8507 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0), 8508 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0), 8509 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0), 8510 DEFINE_PROP_UINT8("avx10-version", X86CPU, env.avx10_version, 0), 8511 DEFINE_PROP_UINT64("ucode-rev", X86CPU, ucode_rev, 0), 8512 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true), 8513 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor), 8514 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true), 8515 DEFINE_PROP_BOOL("x-vendor-cpuid-only", X86CPU, vendor_cpuid_only, true), 8516 DEFINE_PROP_BOOL("x-amd-topoext-features-only", X86CPU, amd_topoext_features_only, true), 8517 DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false), 8518 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true), 8519 DEFINE_PROP_BOOL("kvm-pv-enforce-cpuid", X86CPU, kvm_pv_enforce_cpuid, 8520 false), 8521 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true), 8522 DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true), 8523 DEFINE_PROP_BOOL("x-migrate-smi-count", X86CPU, migrate_smi_count, 8524 true), 8525 /* 8526 * lecacy_cache defaults to true unless the CPU model provides its 8527 * own cache information (see x86_cpu_load_def()). 8528 */ 8529 DEFINE_PROP_BOOL("legacy-cache", X86CPU, legacy_cache, true), 8530 DEFINE_PROP_BOOL("legacy-multi-node", X86CPU, legacy_multi_node, false), 8531 DEFINE_PROP_BOOL("xen-vapic", X86CPU, xen_vapic, false), 8532 8533 /* 8534 * From "Requirements for Implementing the Microsoft 8535 * Hypervisor Interface": 8536 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs 8537 * 8538 * "Starting with Windows Server 2012 and Windows 8, if 8539 * CPUID.40000005.EAX contains a value of -1, Windows assumes that 8540 * the hypervisor imposes no specific limit to the number of VPs. 8541 * In this case, Windows Server 2012 guest VMs may use more than 8542 * 64 VPs, up to the maximum supported number of processors applicable 8543 * to the specific Windows version being used." 8544 */ 8545 DEFINE_PROP_INT32("x-hv-max-vps", X86CPU, hv_max_vps, -1), 8546 DEFINE_PROP_BOOL("x-hv-synic-kvm-only", X86CPU, hyperv_synic_kvm_only, 8547 false), 8548 DEFINE_PROP_BOOL("x-intel-pt-auto-level", X86CPU, intel_pt_auto_level, 8549 true), 8550 DEFINE_PROP_BOOL("x-l1-cache-per-thread", X86CPU, l1_cache_per_core, true), 8551 DEFINE_PROP_END_OF_LIST() 8552 }; 8553 8554 #ifndef CONFIG_USER_ONLY 8555 #include "hw/core/sysemu-cpu-ops.h" 8556 8557 static const struct SysemuCPUOps i386_sysemu_ops = { 8558 .get_memory_mapping = x86_cpu_get_memory_mapping, 8559 .get_paging_enabled = x86_cpu_get_paging_enabled, 8560 .get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug, 8561 .asidx_from_attrs = x86_asidx_from_attrs, 8562 .get_crash_info = x86_cpu_get_crash_info, 8563 .write_elf32_note = x86_cpu_write_elf32_note, 8564 .write_elf64_note = x86_cpu_write_elf64_note, 8565 .write_elf32_qemunote = x86_cpu_write_elf32_qemunote, 8566 .write_elf64_qemunote = x86_cpu_write_elf64_qemunote, 8567 .legacy_vmsd = &vmstate_x86_cpu, 8568 }; 8569 #endif 8570 8571 static void x86_cpu_common_class_init(ObjectClass *oc, void *data) 8572 { 8573 X86CPUClass *xcc = X86_CPU_CLASS(oc); 8574 CPUClass *cc = CPU_CLASS(oc); 8575 DeviceClass *dc = DEVICE_CLASS(oc); 8576 ResettableClass *rc = RESETTABLE_CLASS(oc); 8577 FeatureWord w; 8578 8579 device_class_set_parent_realize(dc, x86_cpu_realizefn, 8580 &xcc->parent_realize); 8581 device_class_set_parent_unrealize(dc, x86_cpu_unrealizefn, 8582 &xcc->parent_unrealize); 8583 device_class_set_props(dc, x86_cpu_properties); 8584 8585 resettable_class_set_parent_phases(rc, NULL, x86_cpu_reset_hold, NULL, 8586 &xcc->parent_phases); 8587 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP; 8588 8589 cc->class_by_name = x86_cpu_class_by_name; 8590 cc->parse_features = x86_cpu_parse_featurestr; 8591 cc->has_work = x86_cpu_has_work; 8592 cc->mmu_index = x86_cpu_mmu_index; 8593 cc->dump_state = x86_cpu_dump_state; 8594 cc->set_pc = x86_cpu_set_pc; 8595 cc->get_pc = x86_cpu_get_pc; 8596 cc->gdb_read_register = x86_cpu_gdb_read_register; 8597 cc->gdb_write_register = x86_cpu_gdb_write_register; 8598 cc->get_arch_id = x86_cpu_get_arch_id; 8599 8600 #ifndef CONFIG_USER_ONLY 8601 cc->sysemu_ops = &i386_sysemu_ops; 8602 #endif /* !CONFIG_USER_ONLY */ 8603 8604 cc->gdb_arch_name = x86_gdb_arch_name; 8605 #ifdef TARGET_X86_64 8606 cc->gdb_core_xml_file = "i386-64bit.xml"; 8607 #else 8608 cc->gdb_core_xml_file = "i386-32bit.xml"; 8609 #endif 8610 cc->disas_set_info = x86_disas_set_info; 8611 8612 dc->user_creatable = true; 8613 8614 object_class_property_add(oc, "family", "int", 8615 x86_cpuid_version_get_family, 8616 x86_cpuid_version_set_family, NULL, NULL); 8617 object_class_property_add(oc, "model", "int", 8618 x86_cpuid_version_get_model, 8619 x86_cpuid_version_set_model, NULL, NULL); 8620 object_class_property_add(oc, "stepping", "int", 8621 x86_cpuid_version_get_stepping, 8622 x86_cpuid_version_set_stepping, NULL, NULL); 8623 object_class_property_add_str(oc, "vendor", 8624 x86_cpuid_get_vendor, 8625 x86_cpuid_set_vendor); 8626 object_class_property_add_str(oc, "model-id", 8627 x86_cpuid_get_model_id, 8628 x86_cpuid_set_model_id); 8629 object_class_property_add(oc, "tsc-frequency", "int", 8630 x86_cpuid_get_tsc_freq, 8631 x86_cpuid_set_tsc_freq, NULL, NULL); 8632 /* 8633 * The "unavailable-features" property has the same semantics as 8634 * CpuDefinitionInfo.unavailable-features on the "query-cpu-definitions" 8635 * QMP command: they list the features that would have prevented the 8636 * CPU from running if the "enforce" flag was set. 8637 */ 8638 object_class_property_add(oc, "unavailable-features", "strList", 8639 x86_cpu_get_unavailable_features, 8640 NULL, NULL, NULL); 8641 8642 #if !defined(CONFIG_USER_ONLY) 8643 object_class_property_add(oc, "crash-information", "GuestPanicInformation", 8644 x86_cpu_get_crash_info_qom, NULL, NULL, NULL); 8645 #endif 8646 8647 for (w = 0; w < FEATURE_WORDS; w++) { 8648 int bitnr; 8649 for (bitnr = 0; bitnr < 64; bitnr++) { 8650 x86_cpu_register_feature_bit_props(xcc, w, bitnr); 8651 } 8652 } 8653 } 8654 8655 static const TypeInfo x86_cpu_type_info = { 8656 .name = TYPE_X86_CPU, 8657 .parent = TYPE_CPU, 8658 .instance_size = sizeof(X86CPU), 8659 .instance_align = __alignof(X86CPU), 8660 .instance_init = x86_cpu_initfn, 8661 .instance_post_init = x86_cpu_post_initfn, 8662 8663 .abstract = true, 8664 .class_size = sizeof(X86CPUClass), 8665 .class_init = x86_cpu_common_class_init, 8666 }; 8667 8668 /* "base" CPU model, used by query-cpu-model-expansion */ 8669 static void x86_cpu_base_class_init(ObjectClass *oc, void *data) 8670 { 8671 X86CPUClass *xcc = X86_CPU_CLASS(oc); 8672 8673 xcc->static_model = true; 8674 xcc->migration_safe = true; 8675 xcc->model_description = "base CPU model type with no features enabled"; 8676 xcc->ordering = 8; 8677 } 8678 8679 static const TypeInfo x86_base_cpu_type_info = { 8680 .name = X86_CPU_TYPE_NAME("base"), 8681 .parent = TYPE_X86_CPU, 8682 .class_init = x86_cpu_base_class_init, 8683 }; 8684 8685 static void x86_cpu_register_types(void) 8686 { 8687 int i; 8688 8689 type_register_static(&x86_cpu_type_info); 8690 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) { 8691 x86_register_cpudef_types(&builtin_x86_defs[i]); 8692 } 8693 type_register_static(&max_x86_cpu_type_info); 8694 type_register_static(&x86_base_cpu_type_info); 8695 } 8696 8697 type_init(x86_cpu_register_types) 8698