1 /* 2 * i386 CPUID, CPU class, definitions, models 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/units.h" 22 #include "qemu/cutils.h" 23 #include "qemu/qemu-print.h" 24 #include "qemu/hw-version.h" 25 #include "cpu.h" 26 #include "tcg/helper-tcg.h" 27 #include "sysemu/reset.h" 28 #include "sysemu/hvf.h" 29 #include "kvm/kvm_i386.h" 30 #include "sev.h" 31 #include "qapi/error.h" 32 #include "qemu/error-report.h" 33 #include "qapi/qapi-visit-machine.h" 34 #include "qapi/qmp/qerror.h" 35 #include "standard-headers/asm-x86/kvm_para.h" 36 #include "hw/qdev-properties.h" 37 #include "hw/i386/topology.h" 38 #ifndef CONFIG_USER_ONLY 39 #include "qapi/qapi-commands-machine-target.h" 40 #include "exec/address-spaces.h" 41 #include "hw/boards.h" 42 #include "hw/i386/sgx-epc.h" 43 #endif 44 45 #include "disas/capstone.h" 46 #include "cpu-internal.h" 47 48 /* Helpers for building CPUID[2] descriptors: */ 49 50 struct CPUID2CacheDescriptorInfo { 51 enum CacheType type; 52 int level; 53 int size; 54 int line_size; 55 int associativity; 56 }; 57 58 /* 59 * Known CPUID 2 cache descriptors. 60 * From Intel SDM Volume 2A, CPUID instruction 61 */ 62 struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = { 63 [0x06] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 8 * KiB, 64 .associativity = 4, .line_size = 32, }, 65 [0x08] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 16 * KiB, 66 .associativity = 4, .line_size = 32, }, 67 [0x09] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB, 68 .associativity = 4, .line_size = 64, }, 69 [0x0A] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB, 70 .associativity = 2, .line_size = 32, }, 71 [0x0C] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 72 .associativity = 4, .line_size = 32, }, 73 [0x0D] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 74 .associativity = 4, .line_size = 64, }, 75 [0x0E] = { .level = 1, .type = DATA_CACHE, .size = 24 * KiB, 76 .associativity = 6, .line_size = 64, }, 77 [0x1D] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB, 78 .associativity = 2, .line_size = 64, }, 79 [0x21] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 80 .associativity = 8, .line_size = 64, }, 81 /* lines per sector is not supported cpuid2_cache_descriptor(), 82 * so descriptors 0x22, 0x23 are not included 83 */ 84 [0x24] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 85 .associativity = 16, .line_size = 64, }, 86 /* lines per sector is not supported cpuid2_cache_descriptor(), 87 * so descriptors 0x25, 0x20 are not included 88 */ 89 [0x2C] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB, 90 .associativity = 8, .line_size = 64, }, 91 [0x30] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB, 92 .associativity = 8, .line_size = 64, }, 93 [0x41] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB, 94 .associativity = 4, .line_size = 32, }, 95 [0x42] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 96 .associativity = 4, .line_size = 32, }, 97 [0x43] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 98 .associativity = 4, .line_size = 32, }, 99 [0x44] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 100 .associativity = 4, .line_size = 32, }, 101 [0x45] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 102 .associativity = 4, .line_size = 32, }, 103 [0x46] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 104 .associativity = 4, .line_size = 64, }, 105 [0x47] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 106 .associativity = 8, .line_size = 64, }, 107 [0x48] = { .level = 2, .type = UNIFIED_CACHE, .size = 3 * MiB, 108 .associativity = 12, .line_size = 64, }, 109 /* Descriptor 0x49 depends on CPU family/model, so it is not included */ 110 [0x4A] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB, 111 .associativity = 12, .line_size = 64, }, 112 [0x4B] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 113 .associativity = 16, .line_size = 64, }, 114 [0x4C] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB, 115 .associativity = 12, .line_size = 64, }, 116 [0x4D] = { .level = 3, .type = UNIFIED_CACHE, .size = 16 * MiB, 117 .associativity = 16, .line_size = 64, }, 118 [0x4E] = { .level = 2, .type = UNIFIED_CACHE, .size = 6 * MiB, 119 .associativity = 24, .line_size = 64, }, 120 [0x60] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 121 .associativity = 8, .line_size = 64, }, 122 [0x66] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB, 123 .associativity = 4, .line_size = 64, }, 124 [0x67] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 125 .associativity = 4, .line_size = 64, }, 126 [0x68] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB, 127 .associativity = 4, .line_size = 64, }, 128 [0x78] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 129 .associativity = 4, .line_size = 64, }, 130 /* lines per sector is not supported cpuid2_cache_descriptor(), 131 * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included. 132 */ 133 [0x7D] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 134 .associativity = 8, .line_size = 64, }, 135 [0x7F] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 136 .associativity = 2, .line_size = 64, }, 137 [0x80] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 138 .associativity = 8, .line_size = 64, }, 139 [0x82] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 140 .associativity = 8, .line_size = 32, }, 141 [0x83] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 142 .associativity = 8, .line_size = 32, }, 143 [0x84] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 144 .associativity = 8, .line_size = 32, }, 145 [0x85] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 146 .associativity = 8, .line_size = 32, }, 147 [0x86] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 148 .associativity = 4, .line_size = 64, }, 149 [0x87] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 150 .associativity = 8, .line_size = 64, }, 151 [0xD0] = { .level = 3, .type = UNIFIED_CACHE, .size = 512 * KiB, 152 .associativity = 4, .line_size = 64, }, 153 [0xD1] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB, 154 .associativity = 4, .line_size = 64, }, 155 [0xD2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 156 .associativity = 4, .line_size = 64, }, 157 [0xD6] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB, 158 .associativity = 8, .line_size = 64, }, 159 [0xD7] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 160 .associativity = 8, .line_size = 64, }, 161 [0xD8] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 162 .associativity = 8, .line_size = 64, }, 163 [0xDC] = { .level = 3, .type = UNIFIED_CACHE, .size = 1.5 * MiB, 164 .associativity = 12, .line_size = 64, }, 165 [0xDD] = { .level = 3, .type = UNIFIED_CACHE, .size = 3 * MiB, 166 .associativity = 12, .line_size = 64, }, 167 [0xDE] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB, 168 .associativity = 12, .line_size = 64, }, 169 [0xE2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 170 .associativity = 16, .line_size = 64, }, 171 [0xE3] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 172 .associativity = 16, .line_size = 64, }, 173 [0xE4] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 174 .associativity = 16, .line_size = 64, }, 175 [0xEA] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB, 176 .associativity = 24, .line_size = 64, }, 177 [0xEB] = { .level = 3, .type = UNIFIED_CACHE, .size = 18 * MiB, 178 .associativity = 24, .line_size = 64, }, 179 [0xEC] = { .level = 3, .type = UNIFIED_CACHE, .size = 24 * MiB, 180 .associativity = 24, .line_size = 64, }, 181 }; 182 183 /* 184 * "CPUID leaf 2 does not report cache descriptor information, 185 * use CPUID leaf 4 to query cache parameters" 186 */ 187 #define CACHE_DESCRIPTOR_UNAVAILABLE 0xFF 188 189 /* 190 * Return a CPUID 2 cache descriptor for a given cache. 191 * If no known descriptor is found, return CACHE_DESCRIPTOR_UNAVAILABLE 192 */ 193 static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache) 194 { 195 int i; 196 197 assert(cache->size > 0); 198 assert(cache->level > 0); 199 assert(cache->line_size > 0); 200 assert(cache->associativity > 0); 201 for (i = 0; i < ARRAY_SIZE(cpuid2_cache_descriptors); i++) { 202 struct CPUID2CacheDescriptorInfo *d = &cpuid2_cache_descriptors[i]; 203 if (d->level == cache->level && d->type == cache->type && 204 d->size == cache->size && d->line_size == cache->line_size && 205 d->associativity == cache->associativity) { 206 return i; 207 } 208 } 209 210 return CACHE_DESCRIPTOR_UNAVAILABLE; 211 } 212 213 /* CPUID Leaf 4 constants: */ 214 215 /* EAX: */ 216 #define CACHE_TYPE_D 1 217 #define CACHE_TYPE_I 2 218 #define CACHE_TYPE_UNIFIED 3 219 220 #define CACHE_LEVEL(l) (l << 5) 221 222 #define CACHE_SELF_INIT_LEVEL (1 << 8) 223 224 /* EDX: */ 225 #define CACHE_NO_INVD_SHARING (1 << 0) 226 #define CACHE_INCLUSIVE (1 << 1) 227 #define CACHE_COMPLEX_IDX (1 << 2) 228 229 /* Encode CacheType for CPUID[4].EAX */ 230 #define CACHE_TYPE(t) (((t) == DATA_CACHE) ? CACHE_TYPE_D : \ 231 ((t) == INSTRUCTION_CACHE) ? CACHE_TYPE_I : \ 232 ((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \ 233 0 /* Invalid value */) 234 235 236 /* Encode cache info for CPUID[4] */ 237 static void encode_cache_cpuid4(CPUCacheInfo *cache, 238 int num_apic_ids, int num_cores, 239 uint32_t *eax, uint32_t *ebx, 240 uint32_t *ecx, uint32_t *edx) 241 { 242 assert(cache->size == cache->line_size * cache->associativity * 243 cache->partitions * cache->sets); 244 245 assert(num_apic_ids > 0); 246 *eax = CACHE_TYPE(cache->type) | 247 CACHE_LEVEL(cache->level) | 248 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) | 249 ((num_cores - 1) << 26) | 250 ((num_apic_ids - 1) << 14); 251 252 assert(cache->line_size > 0); 253 assert(cache->partitions > 0); 254 assert(cache->associativity > 0); 255 /* We don't implement fully-associative caches */ 256 assert(cache->associativity < cache->sets); 257 *ebx = (cache->line_size - 1) | 258 ((cache->partitions - 1) << 12) | 259 ((cache->associativity - 1) << 22); 260 261 assert(cache->sets > 0); 262 *ecx = cache->sets - 1; 263 264 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) | 265 (cache->inclusive ? CACHE_INCLUSIVE : 0) | 266 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); 267 } 268 269 /* Encode cache info for CPUID[0x80000005].ECX or CPUID[0x80000005].EDX */ 270 static uint32_t encode_cache_cpuid80000005(CPUCacheInfo *cache) 271 { 272 assert(cache->size % 1024 == 0); 273 assert(cache->lines_per_tag > 0); 274 assert(cache->associativity > 0); 275 assert(cache->line_size > 0); 276 return ((cache->size / 1024) << 24) | (cache->associativity << 16) | 277 (cache->lines_per_tag << 8) | (cache->line_size); 278 } 279 280 #define ASSOC_FULL 0xFF 281 282 /* AMD associativity encoding used on CPUID Leaf 0x80000006: */ 283 #define AMD_ENC_ASSOC(a) (a <= 1 ? a : \ 284 a == 2 ? 0x2 : \ 285 a == 4 ? 0x4 : \ 286 a == 8 ? 0x6 : \ 287 a == 16 ? 0x8 : \ 288 a == 32 ? 0xA : \ 289 a == 48 ? 0xB : \ 290 a == 64 ? 0xC : \ 291 a == 96 ? 0xD : \ 292 a == 128 ? 0xE : \ 293 a == ASSOC_FULL ? 0xF : \ 294 0 /* invalid value */) 295 296 /* 297 * Encode cache info for CPUID[0x80000006].ECX and CPUID[0x80000006].EDX 298 * @l3 can be NULL. 299 */ 300 static void encode_cache_cpuid80000006(CPUCacheInfo *l2, 301 CPUCacheInfo *l3, 302 uint32_t *ecx, uint32_t *edx) 303 { 304 assert(l2->size % 1024 == 0); 305 assert(l2->associativity > 0); 306 assert(l2->lines_per_tag > 0); 307 assert(l2->line_size > 0); 308 *ecx = ((l2->size / 1024) << 16) | 309 (AMD_ENC_ASSOC(l2->associativity) << 12) | 310 (l2->lines_per_tag << 8) | (l2->line_size); 311 312 if (l3) { 313 assert(l3->size % (512 * 1024) == 0); 314 assert(l3->associativity > 0); 315 assert(l3->lines_per_tag > 0); 316 assert(l3->line_size > 0); 317 *edx = ((l3->size / (512 * 1024)) << 18) | 318 (AMD_ENC_ASSOC(l3->associativity) << 12) | 319 (l3->lines_per_tag << 8) | (l3->line_size); 320 } else { 321 *edx = 0; 322 } 323 } 324 325 /* Encode cache info for CPUID[8000001D] */ 326 static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, 327 X86CPUTopoInfo *topo_info, 328 uint32_t *eax, uint32_t *ebx, 329 uint32_t *ecx, uint32_t *edx) 330 { 331 uint32_t l3_threads; 332 assert(cache->size == cache->line_size * cache->associativity * 333 cache->partitions * cache->sets); 334 335 *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) | 336 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0); 337 338 /* L3 is shared among multiple cores */ 339 if (cache->level == 3) { 340 l3_threads = topo_info->cores_per_die * topo_info->threads_per_core; 341 *eax |= (l3_threads - 1) << 14; 342 } else { 343 *eax |= ((topo_info->threads_per_core - 1) << 14); 344 } 345 346 assert(cache->line_size > 0); 347 assert(cache->partitions > 0); 348 assert(cache->associativity > 0); 349 /* We don't implement fully-associative caches */ 350 assert(cache->associativity < cache->sets); 351 *ebx = (cache->line_size - 1) | 352 ((cache->partitions - 1) << 12) | 353 ((cache->associativity - 1) << 22); 354 355 assert(cache->sets > 0); 356 *ecx = cache->sets - 1; 357 358 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) | 359 (cache->inclusive ? CACHE_INCLUSIVE : 0) | 360 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); 361 } 362 363 /* Encode cache info for CPUID[8000001E] */ 364 static void encode_topo_cpuid8000001e(X86CPU *cpu, X86CPUTopoInfo *topo_info, 365 uint32_t *eax, uint32_t *ebx, 366 uint32_t *ecx, uint32_t *edx) 367 { 368 X86CPUTopoIDs topo_ids; 369 370 x86_topo_ids_from_apicid(cpu->apic_id, topo_info, &topo_ids); 371 372 *eax = cpu->apic_id; 373 374 /* 375 * CPUID_Fn8000001E_EBX [Core Identifiers] (CoreId) 376 * Read-only. Reset: 0000_XXXXh. 377 * See Core::X86::Cpuid::ExtApicId. 378 * Core::X86::Cpuid::CoreId_lthree[1:0]_core[3:0]_thread[1:0]; 379 * Bits Description 380 * 31:16 Reserved. 381 * 15:8 ThreadsPerCore: threads per core. Read-only. Reset: XXh. 382 * The number of threads per core is ThreadsPerCore+1. 383 * 7:0 CoreId: core ID. Read-only. Reset: XXh. 384 * 385 * NOTE: CoreId is already part of apic_id. Just use it. We can 386 * use all the 8 bits to represent the core_id here. 387 */ 388 *ebx = ((topo_info->threads_per_core - 1) << 8) | (topo_ids.core_id & 0xFF); 389 390 /* 391 * CPUID_Fn8000001E_ECX [Node Identifiers] (NodeId) 392 * Read-only. Reset: 0000_0XXXh. 393 * Core::X86::Cpuid::NodeId_lthree[1:0]_core[3:0]_thread[1:0]; 394 * Bits Description 395 * 31:11 Reserved. 396 * 10:8 NodesPerProcessor: Node per processor. Read-only. Reset: XXXb. 397 * ValidValues: 398 * Value Description 399 * 000b 1 node per processor. 400 * 001b 2 nodes per processor. 401 * 010b Reserved. 402 * 011b 4 nodes per processor. 403 * 111b-100b Reserved. 404 * 7:0 NodeId: Node ID. Read-only. Reset: XXh. 405 * 406 * NOTE: Hardware reserves 3 bits for number of nodes per processor. 407 * But users can create more nodes than the actual hardware can 408 * support. To genaralize we can use all the upper 8 bits for nodes. 409 * NodeId is combination of node and socket_id which is already decoded 410 * in apic_id. Just use it by shifting. 411 */ 412 *ecx = ((topo_info->dies_per_pkg - 1) << 8) | 413 ((cpu->apic_id >> apicid_die_offset(topo_info)) & 0xFF); 414 415 *edx = 0; 416 } 417 418 /* 419 * Definitions of the hardcoded cache entries we expose: 420 * These are legacy cache values. If there is a need to change any 421 * of these values please use builtin_x86_defs 422 */ 423 424 /* L1 data cache: */ 425 static CPUCacheInfo legacy_l1d_cache = { 426 .type = DATA_CACHE, 427 .level = 1, 428 .size = 32 * KiB, 429 .self_init = 1, 430 .line_size = 64, 431 .associativity = 8, 432 .sets = 64, 433 .partitions = 1, 434 .no_invd_sharing = true, 435 }; 436 437 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ 438 static CPUCacheInfo legacy_l1d_cache_amd = { 439 .type = DATA_CACHE, 440 .level = 1, 441 .size = 64 * KiB, 442 .self_init = 1, 443 .line_size = 64, 444 .associativity = 2, 445 .sets = 512, 446 .partitions = 1, 447 .lines_per_tag = 1, 448 .no_invd_sharing = true, 449 }; 450 451 /* L1 instruction cache: */ 452 static CPUCacheInfo legacy_l1i_cache = { 453 .type = INSTRUCTION_CACHE, 454 .level = 1, 455 .size = 32 * KiB, 456 .self_init = 1, 457 .line_size = 64, 458 .associativity = 8, 459 .sets = 64, 460 .partitions = 1, 461 .no_invd_sharing = true, 462 }; 463 464 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ 465 static CPUCacheInfo legacy_l1i_cache_amd = { 466 .type = INSTRUCTION_CACHE, 467 .level = 1, 468 .size = 64 * KiB, 469 .self_init = 1, 470 .line_size = 64, 471 .associativity = 2, 472 .sets = 512, 473 .partitions = 1, 474 .lines_per_tag = 1, 475 .no_invd_sharing = true, 476 }; 477 478 /* Level 2 unified cache: */ 479 static CPUCacheInfo legacy_l2_cache = { 480 .type = UNIFIED_CACHE, 481 .level = 2, 482 .size = 4 * MiB, 483 .self_init = 1, 484 .line_size = 64, 485 .associativity = 16, 486 .sets = 4096, 487 .partitions = 1, 488 .no_invd_sharing = true, 489 }; 490 491 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */ 492 static CPUCacheInfo legacy_l2_cache_cpuid2 = { 493 .type = UNIFIED_CACHE, 494 .level = 2, 495 .size = 2 * MiB, 496 .line_size = 64, 497 .associativity = 8, 498 }; 499 500 501 /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */ 502 static CPUCacheInfo legacy_l2_cache_amd = { 503 .type = UNIFIED_CACHE, 504 .level = 2, 505 .size = 512 * KiB, 506 .line_size = 64, 507 .lines_per_tag = 1, 508 .associativity = 16, 509 .sets = 512, 510 .partitions = 1, 511 }; 512 513 /* Level 3 unified cache: */ 514 static CPUCacheInfo legacy_l3_cache = { 515 .type = UNIFIED_CACHE, 516 .level = 3, 517 .size = 16 * MiB, 518 .line_size = 64, 519 .associativity = 16, 520 .sets = 16384, 521 .partitions = 1, 522 .lines_per_tag = 1, 523 .self_init = true, 524 .inclusive = true, 525 .complex_indexing = true, 526 }; 527 528 /* TLB definitions: */ 529 530 #define L1_DTLB_2M_ASSOC 1 531 #define L1_DTLB_2M_ENTRIES 255 532 #define L1_DTLB_4K_ASSOC 1 533 #define L1_DTLB_4K_ENTRIES 255 534 535 #define L1_ITLB_2M_ASSOC 1 536 #define L1_ITLB_2M_ENTRIES 255 537 #define L1_ITLB_4K_ASSOC 1 538 #define L1_ITLB_4K_ENTRIES 255 539 540 #define L2_DTLB_2M_ASSOC 0 /* disabled */ 541 #define L2_DTLB_2M_ENTRIES 0 /* disabled */ 542 #define L2_DTLB_4K_ASSOC 4 543 #define L2_DTLB_4K_ENTRIES 512 544 545 #define L2_ITLB_2M_ASSOC 0 /* disabled */ 546 #define L2_ITLB_2M_ENTRIES 0 /* disabled */ 547 #define L2_ITLB_4K_ASSOC 4 548 #define L2_ITLB_4K_ENTRIES 512 549 550 /* CPUID Leaf 0x14 constants: */ 551 #define INTEL_PT_MAX_SUBLEAF 0x1 552 /* 553 * bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MATCH 554 * MSR can be accessed; 555 * bit[01]: Support Configurable PSB and Cycle-Accurate Mode; 556 * bit[02]: Support IP Filtering, TraceStop filtering, and preservation 557 * of Intel PT MSRs across warm reset; 558 * bit[03]: Support MTC timing packet and suppression of COFI-based packets; 559 */ 560 #define INTEL_PT_MINIMAL_EBX 0xf 561 /* 562 * bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 and 563 * IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be 564 * accessed; 565 * bit[01]: ToPA tables can hold any number of output entries, up to the 566 * maximum allowed by the MaskOrTableOffset field of 567 * IA32_RTIT_OUTPUT_MASK_PTRS; 568 * bit[02]: Support Single-Range Output scheme; 569 */ 570 #define INTEL_PT_MINIMAL_ECX 0x7 571 /* generated packets which contain IP payloads have LIP values */ 572 #define INTEL_PT_IP_LIP (1 << 31) 573 #define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */ 574 #define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3 575 #define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */ 576 #define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */ 577 #define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */ 578 579 /* CPUID Leaf 0x1D constants: */ 580 #define INTEL_AMX_TILE_MAX_SUBLEAF 0x1 581 #define INTEL_AMX_TOTAL_TILE_BYTES 0x2000 582 #define INTEL_AMX_BYTES_PER_TILE 0x400 583 #define INTEL_AMX_BYTES_PER_ROW 0x40 584 #define INTEL_AMX_TILE_MAX_NAMES 0x8 585 #define INTEL_AMX_TILE_MAX_ROWS 0x10 586 587 /* CPUID Leaf 0x1E constants: */ 588 #define INTEL_AMX_TMUL_MAX_K 0x10 589 #define INTEL_AMX_TMUL_MAX_N 0x40 590 591 void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1, 592 uint32_t vendor2, uint32_t vendor3) 593 { 594 int i; 595 for (i = 0; i < 4; i++) { 596 dst[i] = vendor1 >> (8 * i); 597 dst[i + 4] = vendor2 >> (8 * i); 598 dst[i + 8] = vendor3 >> (8 * i); 599 } 600 dst[CPUID_VENDOR_SZ] = '\0'; 601 } 602 603 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE) 604 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \ 605 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC) 606 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \ 607 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ 608 CPUID_PSE36 | CPUID_FXSR) 609 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE) 610 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \ 611 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \ 612 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \ 613 CPUID_PAE | CPUID_SEP | CPUID_APIC) 614 615 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \ 616 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \ 617 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ 618 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \ 619 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE) 620 /* partly implemented: 621 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */ 622 /* missing: 623 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */ 624 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \ 625 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \ 626 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \ 627 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \ 628 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR | \ 629 CPUID_EXT_RDRAND | CPUID_EXT_AVX | CPUID_EXT_F16C | \ 630 CPUID_EXT_FMA) 631 /* missing: 632 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX, 633 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, 634 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA, 635 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER */ 636 637 #ifdef TARGET_X86_64 638 #define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM) 639 #else 640 #define TCG_EXT2_X86_64_FEATURES 0 641 #endif 642 643 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \ 644 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \ 645 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \ 646 TCG_EXT2_X86_64_FEATURES) 647 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \ 648 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A) 649 #define TCG_EXT4_FEATURES 0 650 #define TCG_SVM_FEATURES (CPUID_SVM_NPT | CPUID_SVM_VGIF | \ 651 CPUID_SVM_SVME_ADDR_CHK) 652 #define TCG_KVM_FEATURES 0 653 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \ 654 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \ 655 CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \ 656 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \ 657 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_AVX2) 658 /* missing: 659 CPUID_7_0_EBX_HLE 660 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM, 661 CPUID_7_0_EBX_RDSEED */ 662 #define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | \ 663 /* CPUID_7_0_ECX_OSPKE is dynamic */ \ 664 CPUID_7_0_ECX_LA57 | CPUID_7_0_ECX_PKS | CPUID_7_0_ECX_VAES) 665 #define TCG_7_0_EDX_FEATURES CPUID_7_0_EDX_FSRM 666 #define TCG_7_1_EAX_FEATURES (CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | \ 667 CPUID_7_1_EAX_FSRC) 668 #define TCG_APM_FEATURES 0 669 #define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT 670 #define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1) 671 /* missing: 672 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */ 673 #define TCG_14_0_ECX_FEATURES 0 674 #define TCG_SGX_12_0_EAX_FEATURES 0 675 #define TCG_SGX_12_0_EBX_FEATURES 0 676 #define TCG_SGX_12_1_EAX_FEATURES 0 677 678 FeatureWordInfo feature_word_info[FEATURE_WORDS] = { 679 [FEAT_1_EDX] = { 680 .type = CPUID_FEATURE_WORD, 681 .feat_names = { 682 "fpu", "vme", "de", "pse", 683 "tsc", "msr", "pae", "mce", 684 "cx8", "apic", NULL, "sep", 685 "mtrr", "pge", "mca", "cmov", 686 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */, 687 NULL, "ds" /* Intel dts */, "acpi", "mmx", 688 "fxsr", "sse", "sse2", "ss", 689 "ht" /* Intel htt */, "tm", "ia64", "pbe", 690 }, 691 .cpuid = {.eax = 1, .reg = R_EDX, }, 692 .tcg_features = TCG_FEATURES, 693 }, 694 [FEAT_1_ECX] = { 695 .type = CPUID_FEATURE_WORD, 696 .feat_names = { 697 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor", 698 "ds-cpl", "vmx", "smx", "est", 699 "tm2", "ssse3", "cid", NULL, 700 "fma", "cx16", "xtpr", "pdcm", 701 NULL, "pcid", "dca", "sse4.1", 702 "sse4.2", "x2apic", "movbe", "popcnt", 703 "tsc-deadline", "aes", "xsave", NULL /* osxsave */, 704 "avx", "f16c", "rdrand", "hypervisor", 705 }, 706 .cpuid = { .eax = 1, .reg = R_ECX, }, 707 .tcg_features = TCG_EXT_FEATURES, 708 }, 709 /* Feature names that are already defined on feature_name[] but 710 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their 711 * names on feat_names below. They are copied automatically 712 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD. 713 */ 714 [FEAT_8000_0001_EDX] = { 715 .type = CPUID_FEATURE_WORD, 716 .feat_names = { 717 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */, 718 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */, 719 NULL /* cx8 */, NULL /* apic */, NULL, "syscall", 720 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */, 721 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */, 722 "nx", NULL, "mmxext", NULL /* mmx */, 723 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp", 724 NULL, "lm", "3dnowext", "3dnow", 725 }, 726 .cpuid = { .eax = 0x80000001, .reg = R_EDX, }, 727 .tcg_features = TCG_EXT2_FEATURES, 728 }, 729 [FEAT_8000_0001_ECX] = { 730 .type = CPUID_FEATURE_WORD, 731 .feat_names = { 732 "lahf-lm", "cmp-legacy", "svm", "extapic", 733 "cr8legacy", "abm", "sse4a", "misalignsse", 734 "3dnowprefetch", "osvw", "ibs", "xop", 735 "skinit", "wdt", NULL, "lwp", 736 "fma4", "tce", NULL, "nodeid-msr", 737 NULL, "tbm", "topoext", "perfctr-core", 738 "perfctr-nb", NULL, NULL, NULL, 739 NULL, NULL, NULL, NULL, 740 }, 741 .cpuid = { .eax = 0x80000001, .reg = R_ECX, }, 742 .tcg_features = TCG_EXT3_FEATURES, 743 /* 744 * TOPOEXT is always allowed but can't be enabled blindly by 745 * "-cpu host", as it requires consistent cache topology info 746 * to be provided so it doesn't confuse guests. 747 */ 748 .no_autoenable_flags = CPUID_EXT3_TOPOEXT, 749 }, 750 [FEAT_C000_0001_EDX] = { 751 .type = CPUID_FEATURE_WORD, 752 .feat_names = { 753 NULL, NULL, "xstore", "xstore-en", 754 NULL, NULL, "xcrypt", "xcrypt-en", 755 "ace2", "ace2-en", "phe", "phe-en", 756 "pmm", "pmm-en", NULL, NULL, 757 NULL, NULL, NULL, NULL, 758 NULL, NULL, NULL, NULL, 759 NULL, NULL, NULL, NULL, 760 NULL, NULL, NULL, NULL, 761 }, 762 .cpuid = { .eax = 0xC0000001, .reg = R_EDX, }, 763 .tcg_features = TCG_EXT4_FEATURES, 764 }, 765 [FEAT_KVM] = { 766 .type = CPUID_FEATURE_WORD, 767 .feat_names = { 768 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock", 769 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt", 770 NULL, "kvm-pv-tlb-flush", NULL, "kvm-pv-ipi", 771 "kvm-poll-control", "kvm-pv-sched-yield", "kvm-asyncpf-int", "kvm-msi-ext-dest-id", 772 NULL, NULL, NULL, NULL, 773 NULL, NULL, NULL, NULL, 774 "kvmclock-stable-bit", NULL, NULL, NULL, 775 NULL, NULL, NULL, NULL, 776 }, 777 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EAX, }, 778 .tcg_features = TCG_KVM_FEATURES, 779 }, 780 [FEAT_KVM_HINTS] = { 781 .type = CPUID_FEATURE_WORD, 782 .feat_names = { 783 "kvm-hint-dedicated", NULL, NULL, NULL, 784 NULL, NULL, NULL, NULL, 785 NULL, NULL, NULL, NULL, 786 NULL, NULL, NULL, NULL, 787 NULL, NULL, NULL, NULL, 788 NULL, NULL, NULL, NULL, 789 NULL, NULL, NULL, NULL, 790 NULL, NULL, NULL, NULL, 791 }, 792 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EDX, }, 793 .tcg_features = TCG_KVM_FEATURES, 794 /* 795 * KVM hints aren't auto-enabled by -cpu host, they need to be 796 * explicitly enabled in the command-line. 797 */ 798 .no_autoenable_flags = ~0U, 799 }, 800 [FEAT_SVM] = { 801 .type = CPUID_FEATURE_WORD, 802 .feat_names = { 803 "npt", "lbrv", "svm-lock", "nrip-save", 804 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists", 805 NULL, NULL, "pause-filter", NULL, 806 "pfthreshold", "avic", NULL, "v-vmsave-vmload", 807 "vgif", NULL, NULL, NULL, 808 NULL, NULL, NULL, NULL, 809 NULL, NULL, NULL, NULL, 810 "svme-addr-chk", NULL, NULL, NULL, 811 }, 812 .cpuid = { .eax = 0x8000000A, .reg = R_EDX, }, 813 .tcg_features = TCG_SVM_FEATURES, 814 }, 815 [FEAT_7_0_EBX] = { 816 .type = CPUID_FEATURE_WORD, 817 .feat_names = { 818 "fsgsbase", "tsc-adjust", "sgx", "bmi1", 819 "hle", "avx2", NULL, "smep", 820 "bmi2", "erms", "invpcid", "rtm", 821 NULL, NULL, "mpx", NULL, 822 "avx512f", "avx512dq", "rdseed", "adx", 823 "smap", "avx512ifma", "pcommit", "clflushopt", 824 "clwb", "intel-pt", "avx512pf", "avx512er", 825 "avx512cd", "sha-ni", "avx512bw", "avx512vl", 826 }, 827 .cpuid = { 828 .eax = 7, 829 .needs_ecx = true, .ecx = 0, 830 .reg = R_EBX, 831 }, 832 .tcg_features = TCG_7_0_EBX_FEATURES, 833 }, 834 [FEAT_7_0_ECX] = { 835 .type = CPUID_FEATURE_WORD, 836 .feat_names = { 837 NULL, "avx512vbmi", "umip", "pku", 838 NULL /* ospke */, "waitpkg", "avx512vbmi2", NULL, 839 "gfni", "vaes", "vpclmulqdq", "avx512vnni", 840 "avx512bitalg", NULL, "avx512-vpopcntdq", NULL, 841 "la57", NULL, NULL, NULL, 842 NULL, NULL, "rdpid", NULL, 843 "bus-lock-detect", "cldemote", NULL, "movdiri", 844 "movdir64b", NULL, "sgxlc", "pks", 845 }, 846 .cpuid = { 847 .eax = 7, 848 .needs_ecx = true, .ecx = 0, 849 .reg = R_ECX, 850 }, 851 .tcg_features = TCG_7_0_ECX_FEATURES, 852 }, 853 [FEAT_7_0_EDX] = { 854 .type = CPUID_FEATURE_WORD, 855 .feat_names = { 856 NULL, NULL, "avx512-4vnniw", "avx512-4fmaps", 857 "fsrm", NULL, NULL, NULL, 858 "avx512-vp2intersect", NULL, "md-clear", NULL, 859 NULL, NULL, "serialize", NULL, 860 "tsx-ldtrk", NULL, NULL /* pconfig */, "arch-lbr", 861 NULL, NULL, "amx-bf16", "avx512-fp16", 862 "amx-tile", "amx-int8", "spec-ctrl", "stibp", 863 NULL, "arch-capabilities", "core-capability", "ssbd", 864 }, 865 .cpuid = { 866 .eax = 7, 867 .needs_ecx = true, .ecx = 0, 868 .reg = R_EDX, 869 }, 870 .tcg_features = TCG_7_0_EDX_FEATURES, 871 }, 872 [FEAT_7_1_EAX] = { 873 .type = CPUID_FEATURE_WORD, 874 .feat_names = { 875 NULL, NULL, NULL, NULL, 876 "avx-vnni", "avx512-bf16", NULL, NULL, 877 NULL, NULL, "fzrm", "fsrs", 878 "fsrc", NULL, NULL, NULL, 879 NULL, NULL, NULL, NULL, 880 NULL, NULL, NULL, NULL, 881 NULL, NULL, NULL, NULL, 882 NULL, NULL, NULL, NULL, 883 }, 884 .cpuid = { 885 .eax = 7, 886 .needs_ecx = true, .ecx = 1, 887 .reg = R_EAX, 888 }, 889 .tcg_features = TCG_7_1_EAX_FEATURES, 890 }, 891 [FEAT_8000_0007_EDX] = { 892 .type = CPUID_FEATURE_WORD, 893 .feat_names = { 894 NULL, NULL, NULL, NULL, 895 NULL, NULL, NULL, NULL, 896 "invtsc", NULL, NULL, NULL, 897 NULL, NULL, NULL, NULL, 898 NULL, NULL, NULL, NULL, 899 NULL, NULL, NULL, NULL, 900 NULL, NULL, NULL, NULL, 901 NULL, NULL, NULL, NULL, 902 }, 903 .cpuid = { .eax = 0x80000007, .reg = R_EDX, }, 904 .tcg_features = TCG_APM_FEATURES, 905 .unmigratable_flags = CPUID_APM_INVTSC, 906 }, 907 [FEAT_8000_0008_EBX] = { 908 .type = CPUID_FEATURE_WORD, 909 .feat_names = { 910 "clzero", NULL, "xsaveerptr", NULL, 911 NULL, NULL, NULL, NULL, 912 NULL, "wbnoinvd", NULL, NULL, 913 "ibpb", NULL, "ibrs", "amd-stibp", 914 NULL, NULL, NULL, NULL, 915 NULL, NULL, NULL, NULL, 916 "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL, 917 NULL, NULL, NULL, NULL, 918 }, 919 .cpuid = { .eax = 0x80000008, .reg = R_EBX, }, 920 .tcg_features = 0, 921 .unmigratable_flags = 0, 922 }, 923 [FEAT_XSAVE] = { 924 .type = CPUID_FEATURE_WORD, 925 .feat_names = { 926 "xsaveopt", "xsavec", "xgetbv1", "xsaves", 927 "xfd", NULL, NULL, NULL, 928 NULL, NULL, NULL, NULL, 929 NULL, NULL, NULL, NULL, 930 NULL, NULL, NULL, NULL, 931 NULL, NULL, NULL, NULL, 932 NULL, NULL, NULL, NULL, 933 NULL, NULL, NULL, NULL, 934 }, 935 .cpuid = { 936 .eax = 0xd, 937 .needs_ecx = true, .ecx = 1, 938 .reg = R_EAX, 939 }, 940 .tcg_features = TCG_XSAVE_FEATURES, 941 }, 942 [FEAT_XSAVE_XSS_LO] = { 943 .type = CPUID_FEATURE_WORD, 944 .feat_names = { 945 NULL, NULL, NULL, NULL, 946 NULL, NULL, NULL, NULL, 947 NULL, NULL, NULL, NULL, 948 NULL, NULL, NULL, NULL, 949 NULL, NULL, NULL, NULL, 950 NULL, NULL, NULL, NULL, 951 NULL, NULL, NULL, NULL, 952 NULL, NULL, NULL, NULL, 953 }, 954 .cpuid = { 955 .eax = 0xD, 956 .needs_ecx = true, 957 .ecx = 1, 958 .reg = R_ECX, 959 }, 960 }, 961 [FEAT_XSAVE_XSS_HI] = { 962 .type = CPUID_FEATURE_WORD, 963 .cpuid = { 964 .eax = 0xD, 965 .needs_ecx = true, 966 .ecx = 1, 967 .reg = R_EDX 968 }, 969 }, 970 [FEAT_6_EAX] = { 971 .type = CPUID_FEATURE_WORD, 972 .feat_names = { 973 NULL, NULL, "arat", NULL, 974 NULL, NULL, NULL, NULL, 975 NULL, NULL, NULL, NULL, 976 NULL, NULL, NULL, NULL, 977 NULL, NULL, NULL, NULL, 978 NULL, NULL, NULL, NULL, 979 NULL, NULL, NULL, NULL, 980 NULL, NULL, NULL, NULL, 981 }, 982 .cpuid = { .eax = 6, .reg = R_EAX, }, 983 .tcg_features = TCG_6_EAX_FEATURES, 984 }, 985 [FEAT_XSAVE_XCR0_LO] = { 986 .type = CPUID_FEATURE_WORD, 987 .cpuid = { 988 .eax = 0xD, 989 .needs_ecx = true, .ecx = 0, 990 .reg = R_EAX, 991 }, 992 .tcg_features = ~0U, 993 .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK | 994 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK | 995 XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK | 996 XSTATE_PKRU_MASK, 997 }, 998 [FEAT_XSAVE_XCR0_HI] = { 999 .type = CPUID_FEATURE_WORD, 1000 .cpuid = { 1001 .eax = 0xD, 1002 .needs_ecx = true, .ecx = 0, 1003 .reg = R_EDX, 1004 }, 1005 .tcg_features = ~0U, 1006 }, 1007 /*Below are MSR exposed features*/ 1008 [FEAT_ARCH_CAPABILITIES] = { 1009 .type = MSR_FEATURE_WORD, 1010 .feat_names = { 1011 "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry", 1012 "ssb-no", "mds-no", "pschange-mc-no", "tsx-ctrl", 1013 "taa-no", NULL, NULL, NULL, 1014 NULL, NULL, NULL, NULL, 1015 NULL, NULL, NULL, NULL, 1016 NULL, NULL, NULL, NULL, 1017 NULL, NULL, NULL, NULL, 1018 NULL, NULL, NULL, NULL, 1019 }, 1020 .msr = { 1021 .index = MSR_IA32_ARCH_CAPABILITIES, 1022 }, 1023 }, 1024 [FEAT_CORE_CAPABILITY] = { 1025 .type = MSR_FEATURE_WORD, 1026 .feat_names = { 1027 NULL, NULL, NULL, NULL, 1028 NULL, "split-lock-detect", NULL, NULL, 1029 NULL, NULL, NULL, NULL, 1030 NULL, NULL, NULL, NULL, 1031 NULL, NULL, NULL, NULL, 1032 NULL, NULL, NULL, NULL, 1033 NULL, NULL, NULL, NULL, 1034 NULL, NULL, NULL, NULL, 1035 }, 1036 .msr = { 1037 .index = MSR_IA32_CORE_CAPABILITY, 1038 }, 1039 }, 1040 [FEAT_PERF_CAPABILITIES] = { 1041 .type = MSR_FEATURE_WORD, 1042 .feat_names = { 1043 NULL, NULL, NULL, NULL, 1044 NULL, NULL, NULL, NULL, 1045 NULL, NULL, NULL, NULL, 1046 NULL, "full-width-write", NULL, NULL, 1047 NULL, NULL, NULL, NULL, 1048 NULL, NULL, NULL, NULL, 1049 NULL, NULL, NULL, NULL, 1050 NULL, NULL, NULL, NULL, 1051 }, 1052 .msr = { 1053 .index = MSR_IA32_PERF_CAPABILITIES, 1054 }, 1055 }, 1056 1057 [FEAT_VMX_PROCBASED_CTLS] = { 1058 .type = MSR_FEATURE_WORD, 1059 .feat_names = { 1060 NULL, NULL, "vmx-vintr-pending", "vmx-tsc-offset", 1061 NULL, NULL, NULL, "vmx-hlt-exit", 1062 NULL, "vmx-invlpg-exit", "vmx-mwait-exit", "vmx-rdpmc-exit", 1063 "vmx-rdtsc-exit", NULL, NULL, "vmx-cr3-load-noexit", 1064 "vmx-cr3-store-noexit", NULL, NULL, "vmx-cr8-load-exit", 1065 "vmx-cr8-store-exit", "vmx-flexpriority", "vmx-vnmi-pending", "vmx-movdr-exit", 1066 "vmx-io-exit", "vmx-io-bitmap", NULL, "vmx-mtf", 1067 "vmx-msr-bitmap", "vmx-monitor-exit", "vmx-pause-exit", "vmx-secondary-ctls", 1068 }, 1069 .msr = { 1070 .index = MSR_IA32_VMX_TRUE_PROCBASED_CTLS, 1071 } 1072 }, 1073 1074 [FEAT_VMX_SECONDARY_CTLS] = { 1075 .type = MSR_FEATURE_WORD, 1076 .feat_names = { 1077 "vmx-apicv-xapic", "vmx-ept", "vmx-desc-exit", "vmx-rdtscp-exit", 1078 "vmx-apicv-x2apic", "vmx-vpid", "vmx-wbinvd-exit", "vmx-unrestricted-guest", 1079 "vmx-apicv-register", "vmx-apicv-vid", "vmx-ple", "vmx-rdrand-exit", 1080 "vmx-invpcid-exit", "vmx-vmfunc", "vmx-shadow-vmcs", "vmx-encls-exit", 1081 "vmx-rdseed-exit", "vmx-pml", NULL, NULL, 1082 "vmx-xsaves", NULL, NULL, NULL, 1083 NULL, "vmx-tsc-scaling", NULL, NULL, 1084 NULL, NULL, NULL, NULL, 1085 }, 1086 .msr = { 1087 .index = MSR_IA32_VMX_PROCBASED_CTLS2, 1088 } 1089 }, 1090 1091 [FEAT_VMX_PINBASED_CTLS] = { 1092 .type = MSR_FEATURE_WORD, 1093 .feat_names = { 1094 "vmx-intr-exit", NULL, NULL, "vmx-nmi-exit", 1095 NULL, "vmx-vnmi", "vmx-preemption-timer", "vmx-posted-intr", 1096 NULL, NULL, NULL, NULL, 1097 NULL, NULL, NULL, NULL, 1098 NULL, NULL, NULL, NULL, 1099 NULL, NULL, NULL, NULL, 1100 NULL, NULL, NULL, NULL, 1101 NULL, NULL, NULL, NULL, 1102 }, 1103 .msr = { 1104 .index = MSR_IA32_VMX_TRUE_PINBASED_CTLS, 1105 } 1106 }, 1107 1108 [FEAT_VMX_EXIT_CTLS] = { 1109 .type = MSR_FEATURE_WORD, 1110 /* 1111 * VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE is copied from 1112 * the LM CPUID bit. 1113 */ 1114 .feat_names = { 1115 NULL, NULL, "vmx-exit-nosave-debugctl", NULL, 1116 NULL, NULL, NULL, NULL, 1117 NULL, NULL /* vmx-exit-host-addr-space-size */, NULL, NULL, 1118 "vmx-exit-load-perf-global-ctrl", NULL, NULL, "vmx-exit-ack-intr", 1119 NULL, NULL, "vmx-exit-save-pat", "vmx-exit-load-pat", 1120 "vmx-exit-save-efer", "vmx-exit-load-efer", 1121 "vmx-exit-save-preemption-timer", "vmx-exit-clear-bndcfgs", 1122 NULL, "vmx-exit-clear-rtit-ctl", NULL, NULL, 1123 NULL, "vmx-exit-load-pkrs", NULL, NULL, 1124 }, 1125 .msr = { 1126 .index = MSR_IA32_VMX_TRUE_EXIT_CTLS, 1127 } 1128 }, 1129 1130 [FEAT_VMX_ENTRY_CTLS] = { 1131 .type = MSR_FEATURE_WORD, 1132 .feat_names = { 1133 NULL, NULL, "vmx-entry-noload-debugctl", NULL, 1134 NULL, NULL, NULL, NULL, 1135 NULL, "vmx-entry-ia32e-mode", NULL, NULL, 1136 NULL, "vmx-entry-load-perf-global-ctrl", "vmx-entry-load-pat", "vmx-entry-load-efer", 1137 "vmx-entry-load-bndcfgs", NULL, "vmx-entry-load-rtit-ctl", NULL, 1138 NULL, NULL, "vmx-entry-load-pkrs", NULL, 1139 NULL, NULL, NULL, NULL, 1140 NULL, NULL, NULL, NULL, 1141 }, 1142 .msr = { 1143 .index = MSR_IA32_VMX_TRUE_ENTRY_CTLS, 1144 } 1145 }, 1146 1147 [FEAT_VMX_MISC] = { 1148 .type = MSR_FEATURE_WORD, 1149 .feat_names = { 1150 NULL, NULL, NULL, NULL, 1151 NULL, "vmx-store-lma", "vmx-activity-hlt", "vmx-activity-shutdown", 1152 "vmx-activity-wait-sipi", NULL, NULL, NULL, 1153 NULL, NULL, NULL, NULL, 1154 NULL, NULL, NULL, NULL, 1155 NULL, NULL, NULL, NULL, 1156 NULL, NULL, NULL, NULL, 1157 NULL, "vmx-vmwrite-vmexit-fields", "vmx-zero-len-inject", NULL, 1158 }, 1159 .msr = { 1160 .index = MSR_IA32_VMX_MISC, 1161 } 1162 }, 1163 1164 [FEAT_VMX_EPT_VPID_CAPS] = { 1165 .type = MSR_FEATURE_WORD, 1166 .feat_names = { 1167 "vmx-ept-execonly", NULL, NULL, NULL, 1168 NULL, NULL, "vmx-page-walk-4", "vmx-page-walk-5", 1169 NULL, NULL, NULL, NULL, 1170 NULL, NULL, NULL, NULL, 1171 "vmx-ept-2mb", "vmx-ept-1gb", NULL, NULL, 1172 "vmx-invept", "vmx-eptad", "vmx-ept-advanced-exitinfo", NULL, 1173 NULL, "vmx-invept-single-context", "vmx-invept-all-context", NULL, 1174 NULL, NULL, NULL, NULL, 1175 "vmx-invvpid", NULL, NULL, NULL, 1176 NULL, NULL, NULL, NULL, 1177 "vmx-invvpid-single-addr", "vmx-invept-single-context", 1178 "vmx-invvpid-all-context", "vmx-invept-single-context-noglobals", 1179 NULL, NULL, NULL, NULL, 1180 NULL, NULL, NULL, NULL, 1181 NULL, NULL, NULL, NULL, 1182 NULL, NULL, NULL, NULL, 1183 NULL, NULL, NULL, NULL, 1184 }, 1185 .msr = { 1186 .index = MSR_IA32_VMX_EPT_VPID_CAP, 1187 } 1188 }, 1189 1190 [FEAT_VMX_BASIC] = { 1191 .type = MSR_FEATURE_WORD, 1192 .feat_names = { 1193 [54] = "vmx-ins-outs", 1194 [55] = "vmx-true-ctls", 1195 }, 1196 .msr = { 1197 .index = MSR_IA32_VMX_BASIC, 1198 }, 1199 /* Just to be safe - we don't support setting the MSEG version field. */ 1200 .no_autoenable_flags = MSR_VMX_BASIC_DUAL_MONITOR, 1201 }, 1202 1203 [FEAT_VMX_VMFUNC] = { 1204 .type = MSR_FEATURE_WORD, 1205 .feat_names = { 1206 [0] = "vmx-eptp-switching", 1207 }, 1208 .msr = { 1209 .index = MSR_IA32_VMX_VMFUNC, 1210 } 1211 }, 1212 1213 [FEAT_14_0_ECX] = { 1214 .type = CPUID_FEATURE_WORD, 1215 .feat_names = { 1216 NULL, NULL, NULL, NULL, 1217 NULL, NULL, NULL, NULL, 1218 NULL, NULL, NULL, NULL, 1219 NULL, NULL, NULL, NULL, 1220 NULL, NULL, NULL, NULL, 1221 NULL, NULL, NULL, NULL, 1222 NULL, NULL, NULL, NULL, 1223 NULL, NULL, NULL, "intel-pt-lip", 1224 }, 1225 .cpuid = { 1226 .eax = 0x14, 1227 .needs_ecx = true, .ecx = 0, 1228 .reg = R_ECX, 1229 }, 1230 .tcg_features = TCG_14_0_ECX_FEATURES, 1231 }, 1232 1233 [FEAT_SGX_12_0_EAX] = { 1234 .type = CPUID_FEATURE_WORD, 1235 .feat_names = { 1236 "sgx1", "sgx2", NULL, NULL, 1237 NULL, NULL, NULL, NULL, 1238 NULL, NULL, NULL, "sgx-edeccssa", 1239 NULL, NULL, NULL, NULL, 1240 NULL, NULL, NULL, NULL, 1241 NULL, NULL, NULL, NULL, 1242 NULL, NULL, NULL, NULL, 1243 NULL, NULL, NULL, NULL, 1244 }, 1245 .cpuid = { 1246 .eax = 0x12, 1247 .needs_ecx = true, .ecx = 0, 1248 .reg = R_EAX, 1249 }, 1250 .tcg_features = TCG_SGX_12_0_EAX_FEATURES, 1251 }, 1252 1253 [FEAT_SGX_12_0_EBX] = { 1254 .type = CPUID_FEATURE_WORD, 1255 .feat_names = { 1256 "sgx-exinfo" , NULL, NULL, NULL, 1257 NULL, NULL, NULL, NULL, 1258 NULL, NULL, NULL, NULL, 1259 NULL, NULL, NULL, NULL, 1260 NULL, NULL, NULL, NULL, 1261 NULL, NULL, NULL, NULL, 1262 NULL, NULL, NULL, NULL, 1263 NULL, NULL, NULL, NULL, 1264 }, 1265 .cpuid = { 1266 .eax = 0x12, 1267 .needs_ecx = true, .ecx = 0, 1268 .reg = R_EBX, 1269 }, 1270 .tcg_features = TCG_SGX_12_0_EBX_FEATURES, 1271 }, 1272 1273 [FEAT_SGX_12_1_EAX] = { 1274 .type = CPUID_FEATURE_WORD, 1275 .feat_names = { 1276 NULL, "sgx-debug", "sgx-mode64", NULL, 1277 "sgx-provisionkey", "sgx-tokenkey", NULL, "sgx-kss", 1278 NULL, NULL, "sgx-aex-notify", NULL, 1279 NULL, NULL, NULL, NULL, 1280 NULL, NULL, NULL, NULL, 1281 NULL, NULL, NULL, NULL, 1282 NULL, NULL, NULL, NULL, 1283 NULL, NULL, NULL, NULL, 1284 }, 1285 .cpuid = { 1286 .eax = 0x12, 1287 .needs_ecx = true, .ecx = 1, 1288 .reg = R_EAX, 1289 }, 1290 .tcg_features = TCG_SGX_12_1_EAX_FEATURES, 1291 }, 1292 }; 1293 1294 typedef struct FeatureMask { 1295 FeatureWord index; 1296 uint64_t mask; 1297 } FeatureMask; 1298 1299 typedef struct FeatureDep { 1300 FeatureMask from, to; 1301 } FeatureDep; 1302 1303 static FeatureDep feature_dependencies[] = { 1304 { 1305 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_ARCH_CAPABILITIES }, 1306 .to = { FEAT_ARCH_CAPABILITIES, ~0ull }, 1307 }, 1308 { 1309 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_CORE_CAPABILITY }, 1310 .to = { FEAT_CORE_CAPABILITY, ~0ull }, 1311 }, 1312 { 1313 .from = { FEAT_1_ECX, CPUID_EXT_PDCM }, 1314 .to = { FEAT_PERF_CAPABILITIES, ~0ull }, 1315 }, 1316 { 1317 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1318 .to = { FEAT_VMX_PROCBASED_CTLS, ~0ull }, 1319 }, 1320 { 1321 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1322 .to = { FEAT_VMX_PINBASED_CTLS, ~0ull }, 1323 }, 1324 { 1325 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1326 .to = { FEAT_VMX_EXIT_CTLS, ~0ull }, 1327 }, 1328 { 1329 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1330 .to = { FEAT_VMX_ENTRY_CTLS, ~0ull }, 1331 }, 1332 { 1333 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1334 .to = { FEAT_VMX_MISC, ~0ull }, 1335 }, 1336 { 1337 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1338 .to = { FEAT_VMX_BASIC, ~0ull }, 1339 }, 1340 { 1341 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_LM }, 1342 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_IA32E_MODE }, 1343 }, 1344 { 1345 .from = { FEAT_VMX_PROCBASED_CTLS, VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS }, 1346 .to = { FEAT_VMX_SECONDARY_CTLS, ~0ull }, 1347 }, 1348 { 1349 .from = { FEAT_XSAVE, CPUID_XSAVE_XSAVES }, 1350 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_XSAVES }, 1351 }, 1352 { 1353 .from = { FEAT_1_ECX, CPUID_EXT_RDRAND }, 1354 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDRAND_EXITING }, 1355 }, 1356 { 1357 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INVPCID }, 1358 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_INVPCID }, 1359 }, 1360 { 1361 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_MPX }, 1362 .to = { FEAT_VMX_EXIT_CTLS, VMX_VM_EXIT_CLEAR_BNDCFGS }, 1363 }, 1364 { 1365 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_MPX }, 1366 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_LOAD_BNDCFGS }, 1367 }, 1368 { 1369 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_RDSEED }, 1370 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDSEED_EXITING }, 1371 }, 1372 { 1373 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT }, 1374 .to = { FEAT_14_0_ECX, ~0ull }, 1375 }, 1376 { 1377 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_RDTSCP }, 1378 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDTSCP }, 1379 }, 1380 { 1381 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT }, 1382 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull }, 1383 }, 1384 { 1385 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT }, 1386 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST }, 1387 }, 1388 { 1389 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VPID }, 1390 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull << 32 }, 1391 }, 1392 { 1393 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VMFUNC }, 1394 .to = { FEAT_VMX_VMFUNC, ~0ull }, 1395 }, 1396 { 1397 .from = { FEAT_8000_0001_ECX, CPUID_EXT3_SVM }, 1398 .to = { FEAT_SVM, ~0ull }, 1399 }, 1400 }; 1401 1402 typedef struct X86RegisterInfo32 { 1403 /* Name of register */ 1404 const char *name; 1405 /* QAPI enum value register */ 1406 X86CPURegister32 qapi_enum; 1407 } X86RegisterInfo32; 1408 1409 #define REGISTER(reg) \ 1410 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg } 1411 static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = { 1412 REGISTER(EAX), 1413 REGISTER(ECX), 1414 REGISTER(EDX), 1415 REGISTER(EBX), 1416 REGISTER(ESP), 1417 REGISTER(EBP), 1418 REGISTER(ESI), 1419 REGISTER(EDI), 1420 }; 1421 #undef REGISTER 1422 1423 /* CPUID feature bits available in XSS */ 1424 #define CPUID_XSTATE_XSS_MASK (XSTATE_ARCH_LBR_MASK) 1425 1426 ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUNT] = { 1427 [XSTATE_FP_BIT] = { 1428 /* x87 FP state component is always enabled if XSAVE is supported */ 1429 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE, 1430 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader), 1431 }, 1432 [XSTATE_SSE_BIT] = { 1433 /* SSE state component is always enabled if XSAVE is supported */ 1434 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE, 1435 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader), 1436 }, 1437 [XSTATE_YMM_BIT] = 1438 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX, 1439 .size = sizeof(XSaveAVX) }, 1440 [XSTATE_BNDREGS_BIT] = 1441 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX, 1442 .size = sizeof(XSaveBNDREG) }, 1443 [XSTATE_BNDCSR_BIT] = 1444 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX, 1445 .size = sizeof(XSaveBNDCSR) }, 1446 [XSTATE_OPMASK_BIT] = 1447 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1448 .size = sizeof(XSaveOpmask) }, 1449 [XSTATE_ZMM_Hi256_BIT] = 1450 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1451 .size = sizeof(XSaveZMM_Hi256) }, 1452 [XSTATE_Hi16_ZMM_BIT] = 1453 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1454 .size = sizeof(XSaveHi16_ZMM) }, 1455 [XSTATE_PKRU_BIT] = 1456 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU, 1457 .size = sizeof(XSavePKRU) }, 1458 [XSTATE_ARCH_LBR_BIT] = { 1459 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_ARCH_LBR, 1460 .offset = 0 /*supervisor mode component, offset = 0 */, 1461 .size = sizeof(XSavesArchLBR) }, 1462 [XSTATE_XTILE_CFG_BIT] = { 1463 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_AMX_TILE, 1464 .size = sizeof(XSaveXTILECFG), 1465 }, 1466 [XSTATE_XTILE_DATA_BIT] = { 1467 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_AMX_TILE, 1468 .size = sizeof(XSaveXTILEDATA) 1469 }, 1470 }; 1471 1472 uint32_t xsave_area_size(uint64_t mask, bool compacted) 1473 { 1474 uint64_t ret = x86_ext_save_areas[0].size; 1475 const ExtSaveArea *esa; 1476 uint32_t offset = 0; 1477 int i; 1478 1479 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 1480 esa = &x86_ext_save_areas[i]; 1481 if ((mask >> i) & 1) { 1482 offset = compacted ? ret : esa->offset; 1483 ret = MAX(ret, offset + esa->size); 1484 } 1485 } 1486 return ret; 1487 } 1488 1489 static inline bool accel_uses_host_cpuid(void) 1490 { 1491 return kvm_enabled() || hvf_enabled(); 1492 } 1493 1494 static inline uint64_t x86_cpu_xsave_xcr0_components(X86CPU *cpu) 1495 { 1496 return ((uint64_t)cpu->env.features[FEAT_XSAVE_XCR0_HI]) << 32 | 1497 cpu->env.features[FEAT_XSAVE_XCR0_LO]; 1498 } 1499 1500 /* Return name of 32-bit register, from a R_* constant */ 1501 static const char *get_register_name_32(unsigned int reg) 1502 { 1503 if (reg >= CPU_NB_REGS32) { 1504 return NULL; 1505 } 1506 return x86_reg_info_32[reg].name; 1507 } 1508 1509 static inline uint64_t x86_cpu_xsave_xss_components(X86CPU *cpu) 1510 { 1511 return ((uint64_t)cpu->env.features[FEAT_XSAVE_XSS_HI]) << 32 | 1512 cpu->env.features[FEAT_XSAVE_XSS_LO]; 1513 } 1514 1515 /* 1516 * Returns the set of feature flags that are supported and migratable by 1517 * QEMU, for a given FeatureWord. 1518 */ 1519 static uint64_t x86_cpu_get_migratable_flags(FeatureWord w) 1520 { 1521 FeatureWordInfo *wi = &feature_word_info[w]; 1522 uint64_t r = 0; 1523 int i; 1524 1525 for (i = 0; i < 64; i++) { 1526 uint64_t f = 1ULL << i; 1527 1528 /* If the feature name is known, it is implicitly considered migratable, 1529 * unless it is explicitly set in unmigratable_flags */ 1530 if ((wi->migratable_flags & f) || 1531 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) { 1532 r |= f; 1533 } 1534 } 1535 return r; 1536 } 1537 1538 void host_cpuid(uint32_t function, uint32_t count, 1539 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) 1540 { 1541 uint32_t vec[4]; 1542 1543 #ifdef __x86_64__ 1544 asm volatile("cpuid" 1545 : "=a"(vec[0]), "=b"(vec[1]), 1546 "=c"(vec[2]), "=d"(vec[3]) 1547 : "0"(function), "c"(count) : "cc"); 1548 #elif defined(__i386__) 1549 asm volatile("pusha \n\t" 1550 "cpuid \n\t" 1551 "mov %%eax, 0(%2) \n\t" 1552 "mov %%ebx, 4(%2) \n\t" 1553 "mov %%ecx, 8(%2) \n\t" 1554 "mov %%edx, 12(%2) \n\t" 1555 "popa" 1556 : : "a"(function), "c"(count), "S"(vec) 1557 : "memory", "cc"); 1558 #else 1559 abort(); 1560 #endif 1561 1562 if (eax) 1563 *eax = vec[0]; 1564 if (ebx) 1565 *ebx = vec[1]; 1566 if (ecx) 1567 *ecx = vec[2]; 1568 if (edx) 1569 *edx = vec[3]; 1570 } 1571 1572 /* CPU class name definitions: */ 1573 1574 /* Return type name for a given CPU model name 1575 * Caller is responsible for freeing the returned string. 1576 */ 1577 static char *x86_cpu_type_name(const char *model_name) 1578 { 1579 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name); 1580 } 1581 1582 static ObjectClass *x86_cpu_class_by_name(const char *cpu_model) 1583 { 1584 g_autofree char *typename = x86_cpu_type_name(cpu_model); 1585 return object_class_by_name(typename); 1586 } 1587 1588 static char *x86_cpu_class_get_model_name(X86CPUClass *cc) 1589 { 1590 const char *class_name = object_class_get_name(OBJECT_CLASS(cc)); 1591 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX)); 1592 return g_strndup(class_name, 1593 strlen(class_name) - strlen(X86_CPU_TYPE_SUFFIX)); 1594 } 1595 1596 typedef struct X86CPUVersionDefinition { 1597 X86CPUVersion version; 1598 const char *alias; 1599 const char *note; 1600 PropValue *props; 1601 } X86CPUVersionDefinition; 1602 1603 /* Base definition for a CPU model */ 1604 typedef struct X86CPUDefinition { 1605 const char *name; 1606 uint32_t level; 1607 uint32_t xlevel; 1608 /* vendor is zero-terminated, 12 character ASCII string */ 1609 char vendor[CPUID_VENDOR_SZ + 1]; 1610 int family; 1611 int model; 1612 int stepping; 1613 FeatureWordArray features; 1614 const char *model_id; 1615 const CPUCaches *const cache_info; 1616 /* 1617 * Definitions for alternative versions of CPU model. 1618 * List is terminated by item with version == 0. 1619 * If NULL, version 1 will be registered automatically. 1620 */ 1621 const X86CPUVersionDefinition *versions; 1622 const char *deprecation_note; 1623 } X86CPUDefinition; 1624 1625 /* Reference to a specific CPU model version */ 1626 struct X86CPUModel { 1627 /* Base CPU definition */ 1628 const X86CPUDefinition *cpudef; 1629 /* CPU model version */ 1630 X86CPUVersion version; 1631 const char *note; 1632 /* 1633 * If true, this is an alias CPU model. 1634 * This matters only for "-cpu help" and query-cpu-definitions 1635 */ 1636 bool is_alias; 1637 }; 1638 1639 /* Get full model name for CPU version */ 1640 static char *x86_cpu_versioned_model_name(const X86CPUDefinition *cpudef, 1641 X86CPUVersion version) 1642 { 1643 assert(version > 0); 1644 return g_strdup_printf("%s-v%d", cpudef->name, (int)version); 1645 } 1646 1647 static const X86CPUVersionDefinition * 1648 x86_cpu_def_get_versions(const X86CPUDefinition *def) 1649 { 1650 /* When X86CPUDefinition::versions is NULL, we register only v1 */ 1651 static const X86CPUVersionDefinition default_version_list[] = { 1652 { 1 }, 1653 { /* end of list */ } 1654 }; 1655 1656 return def->versions ?: default_version_list; 1657 } 1658 1659 static const CPUCaches epyc_cache_info = { 1660 .l1d_cache = &(CPUCacheInfo) { 1661 .type = DATA_CACHE, 1662 .level = 1, 1663 .size = 32 * KiB, 1664 .line_size = 64, 1665 .associativity = 8, 1666 .partitions = 1, 1667 .sets = 64, 1668 .lines_per_tag = 1, 1669 .self_init = 1, 1670 .no_invd_sharing = true, 1671 }, 1672 .l1i_cache = &(CPUCacheInfo) { 1673 .type = INSTRUCTION_CACHE, 1674 .level = 1, 1675 .size = 64 * KiB, 1676 .line_size = 64, 1677 .associativity = 4, 1678 .partitions = 1, 1679 .sets = 256, 1680 .lines_per_tag = 1, 1681 .self_init = 1, 1682 .no_invd_sharing = true, 1683 }, 1684 .l2_cache = &(CPUCacheInfo) { 1685 .type = UNIFIED_CACHE, 1686 .level = 2, 1687 .size = 512 * KiB, 1688 .line_size = 64, 1689 .associativity = 8, 1690 .partitions = 1, 1691 .sets = 1024, 1692 .lines_per_tag = 1, 1693 }, 1694 .l3_cache = &(CPUCacheInfo) { 1695 .type = UNIFIED_CACHE, 1696 .level = 3, 1697 .size = 8 * MiB, 1698 .line_size = 64, 1699 .associativity = 16, 1700 .partitions = 1, 1701 .sets = 8192, 1702 .lines_per_tag = 1, 1703 .self_init = true, 1704 .inclusive = true, 1705 .complex_indexing = true, 1706 }, 1707 }; 1708 1709 static const CPUCaches epyc_rome_cache_info = { 1710 .l1d_cache = &(CPUCacheInfo) { 1711 .type = DATA_CACHE, 1712 .level = 1, 1713 .size = 32 * KiB, 1714 .line_size = 64, 1715 .associativity = 8, 1716 .partitions = 1, 1717 .sets = 64, 1718 .lines_per_tag = 1, 1719 .self_init = 1, 1720 .no_invd_sharing = true, 1721 }, 1722 .l1i_cache = &(CPUCacheInfo) { 1723 .type = INSTRUCTION_CACHE, 1724 .level = 1, 1725 .size = 32 * KiB, 1726 .line_size = 64, 1727 .associativity = 8, 1728 .partitions = 1, 1729 .sets = 64, 1730 .lines_per_tag = 1, 1731 .self_init = 1, 1732 .no_invd_sharing = true, 1733 }, 1734 .l2_cache = &(CPUCacheInfo) { 1735 .type = UNIFIED_CACHE, 1736 .level = 2, 1737 .size = 512 * KiB, 1738 .line_size = 64, 1739 .associativity = 8, 1740 .partitions = 1, 1741 .sets = 1024, 1742 .lines_per_tag = 1, 1743 }, 1744 .l3_cache = &(CPUCacheInfo) { 1745 .type = UNIFIED_CACHE, 1746 .level = 3, 1747 .size = 16 * MiB, 1748 .line_size = 64, 1749 .associativity = 16, 1750 .partitions = 1, 1751 .sets = 16384, 1752 .lines_per_tag = 1, 1753 .self_init = true, 1754 .inclusive = true, 1755 .complex_indexing = true, 1756 }, 1757 }; 1758 1759 static const CPUCaches epyc_milan_cache_info = { 1760 .l1d_cache = &(CPUCacheInfo) { 1761 .type = DATA_CACHE, 1762 .level = 1, 1763 .size = 32 * KiB, 1764 .line_size = 64, 1765 .associativity = 8, 1766 .partitions = 1, 1767 .sets = 64, 1768 .lines_per_tag = 1, 1769 .self_init = 1, 1770 .no_invd_sharing = true, 1771 }, 1772 .l1i_cache = &(CPUCacheInfo) { 1773 .type = INSTRUCTION_CACHE, 1774 .level = 1, 1775 .size = 32 * KiB, 1776 .line_size = 64, 1777 .associativity = 8, 1778 .partitions = 1, 1779 .sets = 64, 1780 .lines_per_tag = 1, 1781 .self_init = 1, 1782 .no_invd_sharing = true, 1783 }, 1784 .l2_cache = &(CPUCacheInfo) { 1785 .type = UNIFIED_CACHE, 1786 .level = 2, 1787 .size = 512 * KiB, 1788 .line_size = 64, 1789 .associativity = 8, 1790 .partitions = 1, 1791 .sets = 1024, 1792 .lines_per_tag = 1, 1793 }, 1794 .l3_cache = &(CPUCacheInfo) { 1795 .type = UNIFIED_CACHE, 1796 .level = 3, 1797 .size = 32 * MiB, 1798 .line_size = 64, 1799 .associativity = 16, 1800 .partitions = 1, 1801 .sets = 32768, 1802 .lines_per_tag = 1, 1803 .self_init = true, 1804 .inclusive = true, 1805 .complex_indexing = true, 1806 }, 1807 }; 1808 1809 /* The following VMX features are not supported by KVM and are left out in the 1810 * CPU definitions: 1811 * 1812 * Dual-monitor support (all processors) 1813 * Entry to SMM 1814 * Deactivate dual-monitor treatment 1815 * Number of CR3-target values 1816 * Shutdown activity state 1817 * Wait-for-SIPI activity state 1818 * PAUSE-loop exiting (Westmere and newer) 1819 * EPT-violation #VE (Broadwell and newer) 1820 * Inject event with insn length=0 (Skylake and newer) 1821 * Conceal non-root operation from PT 1822 * Conceal VM exits from PT 1823 * Conceal VM entries from PT 1824 * Enable ENCLS exiting 1825 * Mode-based execute control (XS/XU) 1826 s TSC scaling (Skylake Server and newer) 1827 * GPA translation for PT (IceLake and newer) 1828 * User wait and pause 1829 * ENCLV exiting 1830 * Load IA32_RTIT_CTL 1831 * Clear IA32_RTIT_CTL 1832 * Advanced VM-exit information for EPT violations 1833 * Sub-page write permissions 1834 * PT in VMX operation 1835 */ 1836 1837 static const X86CPUDefinition builtin_x86_defs[] = { 1838 { 1839 .name = "qemu64", 1840 .level = 0xd, 1841 .vendor = CPUID_VENDOR_AMD, 1842 .family = 15, 1843 .model = 107, 1844 .stepping = 1, 1845 .features[FEAT_1_EDX] = 1846 PPRO_FEATURES | 1847 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 1848 CPUID_PSE36, 1849 .features[FEAT_1_ECX] = 1850 CPUID_EXT_SSE3 | CPUID_EXT_CX16, 1851 .features[FEAT_8000_0001_EDX] = 1852 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 1853 .features[FEAT_8000_0001_ECX] = 1854 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM, 1855 .xlevel = 0x8000000A, 1856 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 1857 }, 1858 { 1859 .name = "phenom", 1860 .level = 5, 1861 .vendor = CPUID_VENDOR_AMD, 1862 .family = 16, 1863 .model = 2, 1864 .stepping = 3, 1865 /* Missing: CPUID_HT */ 1866 .features[FEAT_1_EDX] = 1867 PPRO_FEATURES | 1868 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 1869 CPUID_PSE36 | CPUID_VME, 1870 .features[FEAT_1_ECX] = 1871 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 | 1872 CPUID_EXT_POPCNT, 1873 .features[FEAT_8000_0001_EDX] = 1874 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | 1875 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT | 1876 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP, 1877 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, 1878 CPUID_EXT3_CR8LEG, 1879 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, 1880 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */ 1881 .features[FEAT_8000_0001_ECX] = 1882 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | 1883 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A, 1884 /* Missing: CPUID_SVM_LBRV */ 1885 .features[FEAT_SVM] = 1886 CPUID_SVM_NPT, 1887 .xlevel = 0x8000001A, 1888 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor" 1889 }, 1890 { 1891 .name = "core2duo", 1892 .level = 10, 1893 .vendor = CPUID_VENDOR_INTEL, 1894 .family = 6, 1895 .model = 15, 1896 .stepping = 11, 1897 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 1898 .features[FEAT_1_EDX] = 1899 PPRO_FEATURES | 1900 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 1901 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS, 1902 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST, 1903 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */ 1904 .features[FEAT_1_ECX] = 1905 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | 1906 CPUID_EXT_CX16, 1907 .features[FEAT_8000_0001_EDX] = 1908 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 1909 .features[FEAT_8000_0001_ECX] = 1910 CPUID_EXT3_LAHF_LM, 1911 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 1912 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 1913 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 1914 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 1915 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 1916 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 1917 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 1918 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 1919 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 1920 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 1921 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 1922 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 1923 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 1924 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 1925 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 1926 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 1927 .features[FEAT_VMX_SECONDARY_CTLS] = 1928 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES, 1929 .xlevel = 0x80000008, 1930 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz", 1931 }, 1932 { 1933 .name = "kvm64", 1934 .level = 0xd, 1935 .vendor = CPUID_VENDOR_INTEL, 1936 .family = 15, 1937 .model = 6, 1938 .stepping = 1, 1939 /* Missing: CPUID_HT */ 1940 .features[FEAT_1_EDX] = 1941 PPRO_FEATURES | CPUID_VME | 1942 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 1943 CPUID_PSE36, 1944 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */ 1945 .features[FEAT_1_ECX] = 1946 CPUID_EXT_SSE3 | CPUID_EXT_CX16, 1947 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */ 1948 .features[FEAT_8000_0001_EDX] = 1949 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 1950 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, 1951 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A, 1952 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, 1953 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */ 1954 .features[FEAT_8000_0001_ECX] = 1955 0, 1956 /* VMX features from Cedar Mill/Prescott */ 1957 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 1958 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 1959 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 1960 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 1961 VMX_PIN_BASED_NMI_EXITING, 1962 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 1963 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 1964 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 1965 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 1966 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 1967 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 1968 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 1969 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING, 1970 .xlevel = 0x80000008, 1971 .model_id = "Common KVM processor" 1972 }, 1973 { 1974 .name = "qemu32", 1975 .level = 4, 1976 .vendor = CPUID_VENDOR_INTEL, 1977 .family = 6, 1978 .model = 6, 1979 .stepping = 3, 1980 .features[FEAT_1_EDX] = 1981 PPRO_FEATURES, 1982 .features[FEAT_1_ECX] = 1983 CPUID_EXT_SSE3, 1984 .xlevel = 0x80000004, 1985 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 1986 }, 1987 { 1988 .name = "kvm32", 1989 .level = 5, 1990 .vendor = CPUID_VENDOR_INTEL, 1991 .family = 15, 1992 .model = 6, 1993 .stepping = 1, 1994 .features[FEAT_1_EDX] = 1995 PPRO_FEATURES | CPUID_VME | 1996 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36, 1997 .features[FEAT_1_ECX] = 1998 CPUID_EXT_SSE3, 1999 .features[FEAT_8000_0001_ECX] = 2000 0, 2001 /* VMX features from Yonah */ 2002 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2003 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2004 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2005 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2006 VMX_PIN_BASED_NMI_EXITING, 2007 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2008 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2009 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2010 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2011 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 2012 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 2013 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS, 2014 .xlevel = 0x80000008, 2015 .model_id = "Common 32-bit KVM processor" 2016 }, 2017 { 2018 .name = "coreduo", 2019 .level = 10, 2020 .vendor = CPUID_VENDOR_INTEL, 2021 .family = 6, 2022 .model = 14, 2023 .stepping = 8, 2024 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2025 .features[FEAT_1_EDX] = 2026 PPRO_FEATURES | CPUID_VME | 2027 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI | 2028 CPUID_SS, 2029 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR, 2030 * CPUID_EXT_PDCM, CPUID_EXT_VMX */ 2031 .features[FEAT_1_ECX] = 2032 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR, 2033 .features[FEAT_8000_0001_EDX] = 2034 CPUID_EXT2_NX, 2035 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2036 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2037 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2038 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2039 VMX_PIN_BASED_NMI_EXITING, 2040 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2041 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2042 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2043 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2044 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 2045 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 2046 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS, 2047 .xlevel = 0x80000008, 2048 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz", 2049 }, 2050 { 2051 .name = "486", 2052 .level = 1, 2053 .vendor = CPUID_VENDOR_INTEL, 2054 .family = 4, 2055 .model = 8, 2056 .stepping = 0, 2057 .features[FEAT_1_EDX] = 2058 I486_FEATURES, 2059 .xlevel = 0, 2060 .model_id = "", 2061 }, 2062 { 2063 .name = "pentium", 2064 .level = 1, 2065 .vendor = CPUID_VENDOR_INTEL, 2066 .family = 5, 2067 .model = 4, 2068 .stepping = 3, 2069 .features[FEAT_1_EDX] = 2070 PENTIUM_FEATURES, 2071 .xlevel = 0, 2072 .model_id = "", 2073 }, 2074 { 2075 .name = "pentium2", 2076 .level = 2, 2077 .vendor = CPUID_VENDOR_INTEL, 2078 .family = 6, 2079 .model = 5, 2080 .stepping = 2, 2081 .features[FEAT_1_EDX] = 2082 PENTIUM2_FEATURES, 2083 .xlevel = 0, 2084 .model_id = "", 2085 }, 2086 { 2087 .name = "pentium3", 2088 .level = 3, 2089 .vendor = CPUID_VENDOR_INTEL, 2090 .family = 6, 2091 .model = 7, 2092 .stepping = 3, 2093 .features[FEAT_1_EDX] = 2094 PENTIUM3_FEATURES, 2095 .xlevel = 0, 2096 .model_id = "", 2097 }, 2098 { 2099 .name = "athlon", 2100 .level = 2, 2101 .vendor = CPUID_VENDOR_AMD, 2102 .family = 6, 2103 .model = 2, 2104 .stepping = 3, 2105 .features[FEAT_1_EDX] = 2106 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR | 2107 CPUID_MCA, 2108 .features[FEAT_8000_0001_EDX] = 2109 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT, 2110 .xlevel = 0x80000008, 2111 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 2112 }, 2113 { 2114 .name = "n270", 2115 .level = 10, 2116 .vendor = CPUID_VENDOR_INTEL, 2117 .family = 6, 2118 .model = 28, 2119 .stepping = 2, 2120 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2121 .features[FEAT_1_EDX] = 2122 PPRO_FEATURES | 2123 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | 2124 CPUID_ACPI | CPUID_SS, 2125 /* Some CPUs got no CPUID_SEP */ 2126 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2, 2127 * CPUID_EXT_XTPR */ 2128 .features[FEAT_1_ECX] = 2129 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | 2130 CPUID_EXT_MOVBE, 2131 .features[FEAT_8000_0001_EDX] = 2132 CPUID_EXT2_NX, 2133 .features[FEAT_8000_0001_ECX] = 2134 CPUID_EXT3_LAHF_LM, 2135 .xlevel = 0x80000008, 2136 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz", 2137 }, 2138 { 2139 .name = "Conroe", 2140 .level = 10, 2141 .vendor = CPUID_VENDOR_INTEL, 2142 .family = 6, 2143 .model = 15, 2144 .stepping = 3, 2145 .features[FEAT_1_EDX] = 2146 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2147 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2148 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2149 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2150 CPUID_DE | CPUID_FP87, 2151 .features[FEAT_1_ECX] = 2152 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, 2153 .features[FEAT_8000_0001_EDX] = 2154 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 2155 .features[FEAT_8000_0001_ECX] = 2156 CPUID_EXT3_LAHF_LM, 2157 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2158 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2159 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2160 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2161 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2162 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2163 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2164 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2165 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2166 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2167 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2168 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2169 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2170 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2171 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2172 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2173 .features[FEAT_VMX_SECONDARY_CTLS] = 2174 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES, 2175 .xlevel = 0x80000008, 2176 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)", 2177 }, 2178 { 2179 .name = "Penryn", 2180 .level = 10, 2181 .vendor = CPUID_VENDOR_INTEL, 2182 .family = 6, 2183 .model = 23, 2184 .stepping = 3, 2185 .features[FEAT_1_EDX] = 2186 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2187 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2188 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2189 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2190 CPUID_DE | CPUID_FP87, 2191 .features[FEAT_1_ECX] = 2192 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2193 CPUID_EXT_SSE3, 2194 .features[FEAT_8000_0001_EDX] = 2195 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 2196 .features[FEAT_8000_0001_ECX] = 2197 CPUID_EXT3_LAHF_LM, 2198 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2199 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2200 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, 2201 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT | 2202 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL, 2203 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2204 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2205 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2206 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2207 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2208 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2209 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2210 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2211 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2212 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2213 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2214 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2215 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2216 .features[FEAT_VMX_SECONDARY_CTLS] = 2217 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2218 VMX_SECONDARY_EXEC_WBINVD_EXITING, 2219 .xlevel = 0x80000008, 2220 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)", 2221 }, 2222 { 2223 .name = "Nehalem", 2224 .level = 11, 2225 .vendor = CPUID_VENDOR_INTEL, 2226 .family = 6, 2227 .model = 26, 2228 .stepping = 3, 2229 .features[FEAT_1_EDX] = 2230 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2231 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2232 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2233 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2234 CPUID_DE | CPUID_FP87, 2235 .features[FEAT_1_ECX] = 2236 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 2237 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, 2238 .features[FEAT_8000_0001_EDX] = 2239 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2240 .features[FEAT_8000_0001_ECX] = 2241 CPUID_EXT3_LAHF_LM, 2242 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2243 MSR_VMX_BASIC_TRUE_CTLS, 2244 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2245 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2246 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2247 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2248 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2249 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2250 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2251 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2252 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2253 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2254 .features[FEAT_VMX_EXIT_CTLS] = 2255 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2256 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2257 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2258 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2259 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2260 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2261 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2262 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2263 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2264 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2265 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2266 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2267 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2268 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2269 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2270 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2271 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2272 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2273 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2274 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2275 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2276 .features[FEAT_VMX_SECONDARY_CTLS] = 2277 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2278 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2279 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2280 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2281 VMX_SECONDARY_EXEC_ENABLE_VPID, 2282 .xlevel = 0x80000008, 2283 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)", 2284 .versions = (X86CPUVersionDefinition[]) { 2285 { .version = 1 }, 2286 { 2287 .version = 2, 2288 .alias = "Nehalem-IBRS", 2289 .props = (PropValue[]) { 2290 { "spec-ctrl", "on" }, 2291 { "model-id", 2292 "Intel Core i7 9xx (Nehalem Core i7, IBRS update)" }, 2293 { /* end of list */ } 2294 } 2295 }, 2296 { /* end of list */ } 2297 } 2298 }, 2299 { 2300 .name = "Westmere", 2301 .level = 11, 2302 .vendor = CPUID_VENDOR_INTEL, 2303 .family = 6, 2304 .model = 44, 2305 .stepping = 1, 2306 .features[FEAT_1_EDX] = 2307 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2308 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2309 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2310 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2311 CPUID_DE | CPUID_FP87, 2312 .features[FEAT_1_ECX] = 2313 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | 2314 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2315 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 2316 .features[FEAT_8000_0001_EDX] = 2317 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2318 .features[FEAT_8000_0001_ECX] = 2319 CPUID_EXT3_LAHF_LM, 2320 .features[FEAT_6_EAX] = 2321 CPUID_6_EAX_ARAT, 2322 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2323 MSR_VMX_BASIC_TRUE_CTLS, 2324 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2325 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2326 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2327 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2328 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2329 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2330 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2331 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2332 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2333 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2334 .features[FEAT_VMX_EXIT_CTLS] = 2335 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2336 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2337 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2338 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2339 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2340 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2341 MSR_VMX_MISC_STORE_LMA, 2342 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2343 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2344 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2345 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2346 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2347 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2348 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2349 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2350 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2351 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2352 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2353 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2354 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2355 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2356 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2357 .features[FEAT_VMX_SECONDARY_CTLS] = 2358 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2359 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2360 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2361 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2362 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST, 2363 .xlevel = 0x80000008, 2364 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)", 2365 .versions = (X86CPUVersionDefinition[]) { 2366 { .version = 1 }, 2367 { 2368 .version = 2, 2369 .alias = "Westmere-IBRS", 2370 .props = (PropValue[]) { 2371 { "spec-ctrl", "on" }, 2372 { "model-id", 2373 "Westmere E56xx/L56xx/X56xx (IBRS update)" }, 2374 { /* end of list */ } 2375 } 2376 }, 2377 { /* end of list */ } 2378 } 2379 }, 2380 { 2381 .name = "SandyBridge", 2382 .level = 0xd, 2383 .vendor = CPUID_VENDOR_INTEL, 2384 .family = 6, 2385 .model = 42, 2386 .stepping = 1, 2387 .features[FEAT_1_EDX] = 2388 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2389 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2390 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2391 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2392 CPUID_DE | CPUID_FP87, 2393 .features[FEAT_1_ECX] = 2394 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2395 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | 2396 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 2397 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 2398 CPUID_EXT_SSE3, 2399 .features[FEAT_8000_0001_EDX] = 2400 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 2401 CPUID_EXT2_SYSCALL, 2402 .features[FEAT_8000_0001_ECX] = 2403 CPUID_EXT3_LAHF_LM, 2404 .features[FEAT_XSAVE] = 2405 CPUID_XSAVE_XSAVEOPT, 2406 .features[FEAT_6_EAX] = 2407 CPUID_6_EAX_ARAT, 2408 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2409 MSR_VMX_BASIC_TRUE_CTLS, 2410 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2411 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2412 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2413 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2414 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2415 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2416 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2417 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2418 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2419 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2420 .features[FEAT_VMX_EXIT_CTLS] = 2421 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2422 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2423 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2424 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2425 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2426 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2427 MSR_VMX_MISC_STORE_LMA, 2428 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2429 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2430 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2431 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2432 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2433 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2434 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2435 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2436 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2437 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2438 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2439 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2440 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2441 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2442 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2443 .features[FEAT_VMX_SECONDARY_CTLS] = 2444 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2445 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2446 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2447 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2448 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST, 2449 .xlevel = 0x80000008, 2450 .model_id = "Intel Xeon E312xx (Sandy Bridge)", 2451 .versions = (X86CPUVersionDefinition[]) { 2452 { .version = 1 }, 2453 { 2454 .version = 2, 2455 .alias = "SandyBridge-IBRS", 2456 .props = (PropValue[]) { 2457 { "spec-ctrl", "on" }, 2458 { "model-id", 2459 "Intel Xeon E312xx (Sandy Bridge, IBRS update)" }, 2460 { /* end of list */ } 2461 } 2462 }, 2463 { /* end of list */ } 2464 } 2465 }, 2466 { 2467 .name = "IvyBridge", 2468 .level = 0xd, 2469 .vendor = CPUID_VENDOR_INTEL, 2470 .family = 6, 2471 .model = 58, 2472 .stepping = 9, 2473 .features[FEAT_1_EDX] = 2474 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2475 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2476 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2477 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2478 CPUID_DE | CPUID_FP87, 2479 .features[FEAT_1_ECX] = 2480 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2481 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | 2482 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 2483 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 2484 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 2485 .features[FEAT_7_0_EBX] = 2486 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | 2487 CPUID_7_0_EBX_ERMS, 2488 .features[FEAT_8000_0001_EDX] = 2489 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 2490 CPUID_EXT2_SYSCALL, 2491 .features[FEAT_8000_0001_ECX] = 2492 CPUID_EXT3_LAHF_LM, 2493 .features[FEAT_XSAVE] = 2494 CPUID_XSAVE_XSAVEOPT, 2495 .features[FEAT_6_EAX] = 2496 CPUID_6_EAX_ARAT, 2497 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2498 MSR_VMX_BASIC_TRUE_CTLS, 2499 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2500 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2501 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2502 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2503 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2504 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2505 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2506 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2507 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2508 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2509 .features[FEAT_VMX_EXIT_CTLS] = 2510 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2511 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2512 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2513 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2514 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2515 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2516 MSR_VMX_MISC_STORE_LMA, 2517 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2518 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2519 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 2520 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2521 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2522 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2523 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2524 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2525 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2526 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2527 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2528 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2529 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2530 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2531 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2532 .features[FEAT_VMX_SECONDARY_CTLS] = 2533 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2534 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2535 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2536 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2537 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 2538 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 2539 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 2540 VMX_SECONDARY_EXEC_RDRAND_EXITING, 2541 .xlevel = 0x80000008, 2542 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)", 2543 .versions = (X86CPUVersionDefinition[]) { 2544 { .version = 1 }, 2545 { 2546 .version = 2, 2547 .alias = "IvyBridge-IBRS", 2548 .props = (PropValue[]) { 2549 { "spec-ctrl", "on" }, 2550 { "model-id", 2551 "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)" }, 2552 { /* end of list */ } 2553 } 2554 }, 2555 { /* end of list */ } 2556 } 2557 }, 2558 { 2559 .name = "Haswell", 2560 .level = 0xd, 2561 .vendor = CPUID_VENDOR_INTEL, 2562 .family = 6, 2563 .model = 60, 2564 .stepping = 4, 2565 .features[FEAT_1_EDX] = 2566 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2567 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2568 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2569 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2570 CPUID_DE | CPUID_FP87, 2571 .features[FEAT_1_ECX] = 2572 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2573 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 2574 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2575 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 2576 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 2577 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 2578 .features[FEAT_8000_0001_EDX] = 2579 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 2580 CPUID_EXT2_SYSCALL, 2581 .features[FEAT_8000_0001_ECX] = 2582 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM, 2583 .features[FEAT_7_0_EBX] = 2584 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 2585 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 2586 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 2587 CPUID_7_0_EBX_RTM, 2588 .features[FEAT_XSAVE] = 2589 CPUID_XSAVE_XSAVEOPT, 2590 .features[FEAT_6_EAX] = 2591 CPUID_6_EAX_ARAT, 2592 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2593 MSR_VMX_BASIC_TRUE_CTLS, 2594 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2595 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2596 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2597 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2598 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2599 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2600 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2601 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2602 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2603 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 2604 .features[FEAT_VMX_EXIT_CTLS] = 2605 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2606 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2607 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2608 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2609 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2610 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2611 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 2612 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2613 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2614 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 2615 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2616 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2617 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2618 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2619 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2620 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2621 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2622 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2623 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2624 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2625 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2626 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2627 .features[FEAT_VMX_SECONDARY_CTLS] = 2628 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2629 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2630 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2631 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2632 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 2633 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 2634 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 2635 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 2636 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS, 2637 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 2638 .xlevel = 0x80000008, 2639 .model_id = "Intel Core Processor (Haswell)", 2640 .versions = (X86CPUVersionDefinition[]) { 2641 { .version = 1 }, 2642 { 2643 .version = 2, 2644 .alias = "Haswell-noTSX", 2645 .props = (PropValue[]) { 2646 { "hle", "off" }, 2647 { "rtm", "off" }, 2648 { "stepping", "1" }, 2649 { "model-id", "Intel Core Processor (Haswell, no TSX)", }, 2650 { /* end of list */ } 2651 }, 2652 }, 2653 { 2654 .version = 3, 2655 .alias = "Haswell-IBRS", 2656 .props = (PropValue[]) { 2657 /* Restore TSX features removed by -v2 above */ 2658 { "hle", "on" }, 2659 { "rtm", "on" }, 2660 /* 2661 * Haswell and Haswell-IBRS had stepping=4 in 2662 * QEMU 4.0 and older 2663 */ 2664 { "stepping", "4" }, 2665 { "spec-ctrl", "on" }, 2666 { "model-id", 2667 "Intel Core Processor (Haswell, IBRS)" }, 2668 { /* end of list */ } 2669 } 2670 }, 2671 { 2672 .version = 4, 2673 .alias = "Haswell-noTSX-IBRS", 2674 .props = (PropValue[]) { 2675 { "hle", "off" }, 2676 { "rtm", "off" }, 2677 /* spec-ctrl was already enabled by -v3 above */ 2678 { "stepping", "1" }, 2679 { "model-id", 2680 "Intel Core Processor (Haswell, no TSX, IBRS)" }, 2681 { /* end of list */ } 2682 } 2683 }, 2684 { /* end of list */ } 2685 } 2686 }, 2687 { 2688 .name = "Broadwell", 2689 .level = 0xd, 2690 .vendor = CPUID_VENDOR_INTEL, 2691 .family = 6, 2692 .model = 61, 2693 .stepping = 2, 2694 .features[FEAT_1_EDX] = 2695 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2696 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2697 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2698 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2699 CPUID_DE | CPUID_FP87, 2700 .features[FEAT_1_ECX] = 2701 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2702 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 2703 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2704 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 2705 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 2706 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 2707 .features[FEAT_8000_0001_EDX] = 2708 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 2709 CPUID_EXT2_SYSCALL, 2710 .features[FEAT_8000_0001_ECX] = 2711 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 2712 .features[FEAT_7_0_EBX] = 2713 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 2714 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 2715 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 2716 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 2717 CPUID_7_0_EBX_SMAP, 2718 .features[FEAT_XSAVE] = 2719 CPUID_XSAVE_XSAVEOPT, 2720 .features[FEAT_6_EAX] = 2721 CPUID_6_EAX_ARAT, 2722 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2723 MSR_VMX_BASIC_TRUE_CTLS, 2724 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2725 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2726 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2727 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2728 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2729 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2730 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2731 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2732 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2733 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 2734 .features[FEAT_VMX_EXIT_CTLS] = 2735 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2736 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2737 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2738 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2739 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2740 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2741 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 2742 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2743 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2744 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 2745 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2746 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2747 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2748 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2749 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2750 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2751 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2752 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2753 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2754 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2755 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2756 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2757 .features[FEAT_VMX_SECONDARY_CTLS] = 2758 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2759 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2760 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2761 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2762 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 2763 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 2764 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 2765 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 2766 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 2767 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 2768 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 2769 .xlevel = 0x80000008, 2770 .model_id = "Intel Core Processor (Broadwell)", 2771 .versions = (X86CPUVersionDefinition[]) { 2772 { .version = 1 }, 2773 { 2774 .version = 2, 2775 .alias = "Broadwell-noTSX", 2776 .props = (PropValue[]) { 2777 { "hle", "off" }, 2778 { "rtm", "off" }, 2779 { "model-id", "Intel Core Processor (Broadwell, no TSX)", }, 2780 { /* end of list */ } 2781 }, 2782 }, 2783 { 2784 .version = 3, 2785 .alias = "Broadwell-IBRS", 2786 .props = (PropValue[]) { 2787 /* Restore TSX features removed by -v2 above */ 2788 { "hle", "on" }, 2789 { "rtm", "on" }, 2790 { "spec-ctrl", "on" }, 2791 { "model-id", 2792 "Intel Core Processor (Broadwell, IBRS)" }, 2793 { /* end of list */ } 2794 } 2795 }, 2796 { 2797 .version = 4, 2798 .alias = "Broadwell-noTSX-IBRS", 2799 .props = (PropValue[]) { 2800 { "hle", "off" }, 2801 { "rtm", "off" }, 2802 /* spec-ctrl was already enabled by -v3 above */ 2803 { "model-id", 2804 "Intel Core Processor (Broadwell, no TSX, IBRS)" }, 2805 { /* end of list */ } 2806 } 2807 }, 2808 { /* end of list */ } 2809 } 2810 }, 2811 { 2812 .name = "Skylake-Client", 2813 .level = 0xd, 2814 .vendor = CPUID_VENDOR_INTEL, 2815 .family = 6, 2816 .model = 94, 2817 .stepping = 3, 2818 .features[FEAT_1_EDX] = 2819 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2820 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2821 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2822 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2823 CPUID_DE | CPUID_FP87, 2824 .features[FEAT_1_ECX] = 2825 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2826 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 2827 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2828 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 2829 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 2830 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 2831 .features[FEAT_8000_0001_EDX] = 2832 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 2833 CPUID_EXT2_SYSCALL, 2834 .features[FEAT_8000_0001_ECX] = 2835 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 2836 .features[FEAT_7_0_EBX] = 2837 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 2838 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 2839 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 2840 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 2841 CPUID_7_0_EBX_SMAP, 2842 /* XSAVES is added in version 4 */ 2843 .features[FEAT_XSAVE] = 2844 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 2845 CPUID_XSAVE_XGETBV1, 2846 .features[FEAT_6_EAX] = 2847 CPUID_6_EAX_ARAT, 2848 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 2849 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2850 MSR_VMX_BASIC_TRUE_CTLS, 2851 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2852 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2853 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2854 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2855 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2856 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2857 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2858 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2859 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2860 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 2861 .features[FEAT_VMX_EXIT_CTLS] = 2862 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2863 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2864 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2865 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2866 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2867 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2868 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 2869 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2870 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2871 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2872 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2873 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2874 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2875 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2876 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2877 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2878 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2879 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2880 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2881 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2882 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2883 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2884 .features[FEAT_VMX_SECONDARY_CTLS] = 2885 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2886 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2887 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2888 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 2889 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 2890 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 2891 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 2892 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 2893 .xlevel = 0x80000008, 2894 .model_id = "Intel Core Processor (Skylake)", 2895 .versions = (X86CPUVersionDefinition[]) { 2896 { .version = 1 }, 2897 { 2898 .version = 2, 2899 .alias = "Skylake-Client-IBRS", 2900 .props = (PropValue[]) { 2901 { "spec-ctrl", "on" }, 2902 { "model-id", 2903 "Intel Core Processor (Skylake, IBRS)" }, 2904 { /* end of list */ } 2905 } 2906 }, 2907 { 2908 .version = 3, 2909 .alias = "Skylake-Client-noTSX-IBRS", 2910 .props = (PropValue[]) { 2911 { "hle", "off" }, 2912 { "rtm", "off" }, 2913 { "model-id", 2914 "Intel Core Processor (Skylake, IBRS, no TSX)" }, 2915 { /* end of list */ } 2916 } 2917 }, 2918 { 2919 .version = 4, 2920 .note = "IBRS, XSAVES, no TSX", 2921 .props = (PropValue[]) { 2922 { "xsaves", "on" }, 2923 { "vmx-xsaves", "on" }, 2924 { /* end of list */ } 2925 } 2926 }, 2927 { /* end of list */ } 2928 } 2929 }, 2930 { 2931 .name = "Skylake-Server", 2932 .level = 0xd, 2933 .vendor = CPUID_VENDOR_INTEL, 2934 .family = 6, 2935 .model = 85, 2936 .stepping = 4, 2937 .features[FEAT_1_EDX] = 2938 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2939 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2940 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2941 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2942 CPUID_DE | CPUID_FP87, 2943 .features[FEAT_1_ECX] = 2944 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2945 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 2946 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2947 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 2948 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 2949 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 2950 .features[FEAT_8000_0001_EDX] = 2951 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 2952 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 2953 .features[FEAT_8000_0001_ECX] = 2954 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 2955 .features[FEAT_7_0_EBX] = 2956 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 2957 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 2958 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 2959 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 2960 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 2961 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 2962 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 2963 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 2964 .features[FEAT_7_0_ECX] = 2965 CPUID_7_0_ECX_PKU, 2966 /* XSAVES is added in version 5 */ 2967 .features[FEAT_XSAVE] = 2968 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 2969 CPUID_XSAVE_XGETBV1, 2970 .features[FEAT_6_EAX] = 2971 CPUID_6_EAX_ARAT, 2972 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 2973 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2974 MSR_VMX_BASIC_TRUE_CTLS, 2975 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2976 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2977 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2978 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2979 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2980 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2981 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2982 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2983 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2984 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 2985 .features[FEAT_VMX_EXIT_CTLS] = 2986 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2987 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2988 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2989 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2990 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2991 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2992 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 2993 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2994 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2995 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 2996 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2997 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2998 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2999 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3000 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3001 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3002 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3003 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3004 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3005 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3006 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3007 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3008 .features[FEAT_VMX_SECONDARY_CTLS] = 3009 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3010 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3011 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3012 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3013 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3014 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3015 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3016 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3017 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3018 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3019 .xlevel = 0x80000008, 3020 .model_id = "Intel Xeon Processor (Skylake)", 3021 .versions = (X86CPUVersionDefinition[]) { 3022 { .version = 1 }, 3023 { 3024 .version = 2, 3025 .alias = "Skylake-Server-IBRS", 3026 .props = (PropValue[]) { 3027 /* clflushopt was not added to Skylake-Server-IBRS */ 3028 /* TODO: add -v3 including clflushopt */ 3029 { "clflushopt", "off" }, 3030 { "spec-ctrl", "on" }, 3031 { "model-id", 3032 "Intel Xeon Processor (Skylake, IBRS)" }, 3033 { /* end of list */ } 3034 } 3035 }, 3036 { 3037 .version = 3, 3038 .alias = "Skylake-Server-noTSX-IBRS", 3039 .props = (PropValue[]) { 3040 { "hle", "off" }, 3041 { "rtm", "off" }, 3042 { "model-id", 3043 "Intel Xeon Processor (Skylake, IBRS, no TSX)" }, 3044 { /* end of list */ } 3045 } 3046 }, 3047 { 3048 .version = 4, 3049 .props = (PropValue[]) { 3050 { "vmx-eptp-switching", "on" }, 3051 { /* end of list */ } 3052 } 3053 }, 3054 { 3055 .version = 5, 3056 .note = "IBRS, XSAVES, EPT switching, no TSX", 3057 .props = (PropValue[]) { 3058 { "xsaves", "on" }, 3059 { "vmx-xsaves", "on" }, 3060 { /* end of list */ } 3061 } 3062 }, 3063 { /* end of list */ } 3064 } 3065 }, 3066 { 3067 .name = "Cascadelake-Server", 3068 .level = 0xd, 3069 .vendor = CPUID_VENDOR_INTEL, 3070 .family = 6, 3071 .model = 85, 3072 .stepping = 6, 3073 .features[FEAT_1_EDX] = 3074 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3075 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3076 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3077 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3078 CPUID_DE | CPUID_FP87, 3079 .features[FEAT_1_ECX] = 3080 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3081 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3082 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3083 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3084 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3085 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3086 .features[FEAT_8000_0001_EDX] = 3087 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3088 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3089 .features[FEAT_8000_0001_ECX] = 3090 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3091 .features[FEAT_7_0_EBX] = 3092 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3093 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3094 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3095 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3096 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3097 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3098 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3099 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3100 .features[FEAT_7_0_ECX] = 3101 CPUID_7_0_ECX_PKU | 3102 CPUID_7_0_ECX_AVX512VNNI, 3103 .features[FEAT_7_0_EDX] = 3104 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 3105 /* XSAVES is added in version 5 */ 3106 .features[FEAT_XSAVE] = 3107 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3108 CPUID_XSAVE_XGETBV1, 3109 .features[FEAT_6_EAX] = 3110 CPUID_6_EAX_ARAT, 3111 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3112 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3113 MSR_VMX_BASIC_TRUE_CTLS, 3114 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3115 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3116 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3117 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3118 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3119 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3120 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3121 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3122 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3123 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3124 .features[FEAT_VMX_EXIT_CTLS] = 3125 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3126 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3127 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3128 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3129 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3130 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3131 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3132 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3133 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3134 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3135 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3136 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3137 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3138 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3139 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3140 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3141 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3142 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3143 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3144 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3145 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3146 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3147 .features[FEAT_VMX_SECONDARY_CTLS] = 3148 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3149 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3150 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3151 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3152 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3153 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3154 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3155 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3156 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3157 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3158 .xlevel = 0x80000008, 3159 .model_id = "Intel Xeon Processor (Cascadelake)", 3160 .versions = (X86CPUVersionDefinition[]) { 3161 { .version = 1 }, 3162 { .version = 2, 3163 .note = "ARCH_CAPABILITIES", 3164 .props = (PropValue[]) { 3165 { "arch-capabilities", "on" }, 3166 { "rdctl-no", "on" }, 3167 { "ibrs-all", "on" }, 3168 { "skip-l1dfl-vmentry", "on" }, 3169 { "mds-no", "on" }, 3170 { /* end of list */ } 3171 }, 3172 }, 3173 { .version = 3, 3174 .alias = "Cascadelake-Server-noTSX", 3175 .note = "ARCH_CAPABILITIES, no TSX", 3176 .props = (PropValue[]) { 3177 { "hle", "off" }, 3178 { "rtm", "off" }, 3179 { /* end of list */ } 3180 }, 3181 }, 3182 { .version = 4, 3183 .note = "ARCH_CAPABILITIES, no TSX", 3184 .props = (PropValue[]) { 3185 { "vmx-eptp-switching", "on" }, 3186 { /* end of list */ } 3187 }, 3188 }, 3189 { .version = 5, 3190 .note = "ARCH_CAPABILITIES, EPT switching, XSAVES, no TSX", 3191 .props = (PropValue[]) { 3192 { "xsaves", "on" }, 3193 { "vmx-xsaves", "on" }, 3194 { /* end of list */ } 3195 }, 3196 }, 3197 { /* end of list */ } 3198 } 3199 }, 3200 { 3201 .name = "Cooperlake", 3202 .level = 0xd, 3203 .vendor = CPUID_VENDOR_INTEL, 3204 .family = 6, 3205 .model = 85, 3206 .stepping = 10, 3207 .features[FEAT_1_EDX] = 3208 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3209 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3210 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3211 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3212 CPUID_DE | CPUID_FP87, 3213 .features[FEAT_1_ECX] = 3214 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3215 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3216 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3217 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3218 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3219 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3220 .features[FEAT_8000_0001_EDX] = 3221 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3222 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3223 .features[FEAT_8000_0001_ECX] = 3224 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3225 .features[FEAT_7_0_EBX] = 3226 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3227 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3228 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3229 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3230 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3231 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3232 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3233 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3234 .features[FEAT_7_0_ECX] = 3235 CPUID_7_0_ECX_PKU | 3236 CPUID_7_0_ECX_AVX512VNNI, 3237 .features[FEAT_7_0_EDX] = 3238 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_STIBP | 3239 CPUID_7_0_EDX_SPEC_CTRL_SSBD | CPUID_7_0_EDX_ARCH_CAPABILITIES, 3240 .features[FEAT_ARCH_CAPABILITIES] = 3241 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 3242 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 3243 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO, 3244 .features[FEAT_7_1_EAX] = 3245 CPUID_7_1_EAX_AVX512_BF16, 3246 /* XSAVES is added in version 2 */ 3247 .features[FEAT_XSAVE] = 3248 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3249 CPUID_XSAVE_XGETBV1, 3250 .features[FEAT_6_EAX] = 3251 CPUID_6_EAX_ARAT, 3252 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3253 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3254 MSR_VMX_BASIC_TRUE_CTLS, 3255 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3256 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3257 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3258 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3259 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3260 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3261 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3262 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3263 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3264 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3265 .features[FEAT_VMX_EXIT_CTLS] = 3266 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3267 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3268 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3269 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3270 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3271 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3272 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3273 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3274 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3275 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3276 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3277 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3278 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3279 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3280 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3281 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3282 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3283 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3284 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3285 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3286 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3287 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3288 .features[FEAT_VMX_SECONDARY_CTLS] = 3289 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3290 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3291 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3292 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3293 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3294 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3295 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3296 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3297 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3298 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3299 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3300 .xlevel = 0x80000008, 3301 .model_id = "Intel Xeon Processor (Cooperlake)", 3302 .versions = (X86CPUVersionDefinition[]) { 3303 { .version = 1 }, 3304 { .version = 2, 3305 .note = "XSAVES", 3306 .props = (PropValue[]) { 3307 { "xsaves", "on" }, 3308 { "vmx-xsaves", "on" }, 3309 { /* end of list */ } 3310 }, 3311 }, 3312 { /* end of list */ } 3313 } 3314 }, 3315 { 3316 .name = "Icelake-Server", 3317 .level = 0xd, 3318 .vendor = CPUID_VENDOR_INTEL, 3319 .family = 6, 3320 .model = 134, 3321 .stepping = 0, 3322 .features[FEAT_1_EDX] = 3323 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3324 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3325 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3326 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3327 CPUID_DE | CPUID_FP87, 3328 .features[FEAT_1_ECX] = 3329 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3330 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3331 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3332 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3333 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3334 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3335 .features[FEAT_8000_0001_EDX] = 3336 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3337 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3338 .features[FEAT_8000_0001_ECX] = 3339 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3340 .features[FEAT_8000_0008_EBX] = 3341 CPUID_8000_0008_EBX_WBNOINVD, 3342 .features[FEAT_7_0_EBX] = 3343 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3344 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3345 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3346 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3347 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3348 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3349 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3350 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3351 .features[FEAT_7_0_ECX] = 3352 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 3353 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 3354 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 3355 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 3356 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57, 3357 .features[FEAT_7_0_EDX] = 3358 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 3359 /* XSAVES is added in version 5 */ 3360 .features[FEAT_XSAVE] = 3361 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3362 CPUID_XSAVE_XGETBV1, 3363 .features[FEAT_6_EAX] = 3364 CPUID_6_EAX_ARAT, 3365 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3366 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3367 MSR_VMX_BASIC_TRUE_CTLS, 3368 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3369 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3370 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3371 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3372 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3373 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3374 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3375 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3376 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3377 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3378 .features[FEAT_VMX_EXIT_CTLS] = 3379 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3380 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3381 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3382 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3383 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3384 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3385 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3386 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3387 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3388 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3389 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3390 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3391 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3392 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3393 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3394 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3395 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3396 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3397 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3398 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3399 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3400 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3401 .features[FEAT_VMX_SECONDARY_CTLS] = 3402 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3403 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3404 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3405 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3406 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3407 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3408 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3409 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3410 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS, 3411 .xlevel = 0x80000008, 3412 .model_id = "Intel Xeon Processor (Icelake)", 3413 .versions = (X86CPUVersionDefinition[]) { 3414 { .version = 1 }, 3415 { 3416 .version = 2, 3417 .note = "no TSX", 3418 .alias = "Icelake-Server-noTSX", 3419 .props = (PropValue[]) { 3420 { "hle", "off" }, 3421 { "rtm", "off" }, 3422 { /* end of list */ } 3423 }, 3424 }, 3425 { 3426 .version = 3, 3427 .props = (PropValue[]) { 3428 { "arch-capabilities", "on" }, 3429 { "rdctl-no", "on" }, 3430 { "ibrs-all", "on" }, 3431 { "skip-l1dfl-vmentry", "on" }, 3432 { "mds-no", "on" }, 3433 { "pschange-mc-no", "on" }, 3434 { "taa-no", "on" }, 3435 { /* end of list */ } 3436 }, 3437 }, 3438 { 3439 .version = 4, 3440 .props = (PropValue[]) { 3441 { "sha-ni", "on" }, 3442 { "avx512ifma", "on" }, 3443 { "rdpid", "on" }, 3444 { "fsrm", "on" }, 3445 { "vmx-rdseed-exit", "on" }, 3446 { "vmx-pml", "on" }, 3447 { "vmx-eptp-switching", "on" }, 3448 { "model", "106" }, 3449 { /* end of list */ } 3450 }, 3451 }, 3452 { 3453 .version = 5, 3454 .note = "XSAVES", 3455 .props = (PropValue[]) { 3456 { "xsaves", "on" }, 3457 { "vmx-xsaves", "on" }, 3458 { /* end of list */ } 3459 }, 3460 }, 3461 { 3462 .version = 6, 3463 .note = "5-level EPT", 3464 .props = (PropValue[]) { 3465 { "vmx-page-walk-5", "on" }, 3466 { /* end of list */ } 3467 }, 3468 }, 3469 { /* end of list */ } 3470 } 3471 }, 3472 { 3473 .name = "SapphireRapids", 3474 .level = 0x20, 3475 .vendor = CPUID_VENDOR_INTEL, 3476 .family = 6, 3477 .model = 143, 3478 .stepping = 4, 3479 /* 3480 * please keep the ascending order so that we can have a clear view of 3481 * bit position of each feature. 3482 */ 3483 .features[FEAT_1_EDX] = 3484 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 3485 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 3486 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 3487 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 3488 CPUID_SSE | CPUID_SSE2, 3489 .features[FEAT_1_ECX] = 3490 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 3491 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 3492 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 3493 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 3494 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3495 .features[FEAT_8000_0001_EDX] = 3496 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 3497 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 3498 .features[FEAT_8000_0001_ECX] = 3499 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 3500 .features[FEAT_8000_0008_EBX] = 3501 CPUID_8000_0008_EBX_WBNOINVD, 3502 .features[FEAT_7_0_EBX] = 3503 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_HLE | 3504 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | 3505 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RTM | 3506 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3507 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | 3508 CPUID_7_0_EBX_AVX512IFMA | CPUID_7_0_EBX_CLFLUSHOPT | 3509 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | 3510 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, 3511 .features[FEAT_7_0_ECX] = 3512 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 3513 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 3514 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 3515 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 3516 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | 3517 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT, 3518 .features[FEAT_7_0_EDX] = 3519 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 3520 CPUID_7_0_EDX_TSX_LDTRK | CPUID_7_0_EDX_AMX_BF16 | 3521 CPUID_7_0_EDX_AVX512_FP16 | CPUID_7_0_EDX_AMX_TILE | 3522 CPUID_7_0_EDX_AMX_INT8 | CPUID_7_0_EDX_SPEC_CTRL | 3523 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 3524 .features[FEAT_ARCH_CAPABILITIES] = 3525 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 3526 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 3527 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO, 3528 .features[FEAT_XSAVE] = 3529 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3530 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES | CPUID_D_1_EAX_XFD, 3531 .features[FEAT_6_EAX] = 3532 CPUID_6_EAX_ARAT, 3533 .features[FEAT_7_1_EAX] = 3534 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_AVX512_BF16 | 3535 CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC, 3536 .features[FEAT_VMX_BASIC] = 3537 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 3538 .features[FEAT_VMX_ENTRY_CTLS] = 3539 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 3540 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 3541 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 3542 .features[FEAT_VMX_EPT_VPID_CAPS] = 3543 MSR_VMX_EPT_EXECONLY | 3544 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_PAGE_WALK_LENGTH_5 | 3545 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 3546 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 3547 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3548 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3549 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 3550 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3551 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 3552 .features[FEAT_VMX_EXIT_CTLS] = 3553 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3554 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3555 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 3556 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3557 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3558 .features[FEAT_VMX_MISC] = 3559 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 3560 MSR_VMX_MISC_VMWRITE_VMEXIT, 3561 .features[FEAT_VMX_PINBASED_CTLS] = 3562 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 3563 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 3564 VMX_PIN_BASED_POSTED_INTR, 3565 .features[FEAT_VMX_PROCBASED_CTLS] = 3566 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3567 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3568 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3569 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3570 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3571 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3572 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 3573 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 3574 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3575 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 3576 VMX_CPU_BASED_PAUSE_EXITING | 3577 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3578 .features[FEAT_VMX_SECONDARY_CTLS] = 3579 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3580 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 3581 VMX_SECONDARY_EXEC_RDTSCP | 3582 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3583 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 3584 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3585 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3586 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3587 VMX_SECONDARY_EXEC_RDRAND_EXITING | 3588 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3589 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3590 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 3591 VMX_SECONDARY_EXEC_XSAVES, 3592 .features[FEAT_VMX_VMFUNC] = 3593 MSR_VMX_VMFUNC_EPT_SWITCHING, 3594 .xlevel = 0x80000008, 3595 .model_id = "Intel Xeon Processor (SapphireRapids)", 3596 .versions = (X86CPUVersionDefinition[]) { 3597 { .version = 1 }, 3598 { /* end of list */ }, 3599 }, 3600 }, 3601 { 3602 .name = "Denverton", 3603 .level = 21, 3604 .vendor = CPUID_VENDOR_INTEL, 3605 .family = 6, 3606 .model = 95, 3607 .stepping = 1, 3608 .features[FEAT_1_EDX] = 3609 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 3610 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 3611 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 3612 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 3613 CPUID_SSE | CPUID_SSE2, 3614 .features[FEAT_1_ECX] = 3615 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR | 3616 CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_SSE41 | 3617 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 3618 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | 3619 CPUID_EXT_AES | CPUID_EXT_XSAVE | CPUID_EXT_RDRAND, 3620 .features[FEAT_8000_0001_EDX] = 3621 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 3622 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 3623 .features[FEAT_8000_0001_ECX] = 3624 CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3625 .features[FEAT_7_0_EBX] = 3626 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_ERMS | 3627 CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_SMAP | 3628 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_SHA_NI, 3629 .features[FEAT_7_0_EDX] = 3630 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES | 3631 CPUID_7_0_EDX_SPEC_CTRL_SSBD, 3632 /* XSAVES is added in version 3 */ 3633 .features[FEAT_XSAVE] = 3634 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | CPUID_XSAVE_XGETBV1, 3635 .features[FEAT_6_EAX] = 3636 CPUID_6_EAX_ARAT, 3637 .features[FEAT_ARCH_CAPABILITIES] = 3638 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY, 3639 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3640 MSR_VMX_BASIC_TRUE_CTLS, 3641 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3642 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3643 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3644 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3645 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3646 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3647 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3648 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3649 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3650 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3651 .features[FEAT_VMX_EXIT_CTLS] = 3652 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3653 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3654 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3655 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3656 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3657 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3658 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3659 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3660 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3661 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3662 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3663 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3664 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3665 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3666 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3667 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3668 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3669 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3670 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3671 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3672 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3673 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3674 .features[FEAT_VMX_SECONDARY_CTLS] = 3675 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3676 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3677 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3678 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3679 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3680 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3681 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3682 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3683 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3684 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3685 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3686 .xlevel = 0x80000008, 3687 .model_id = "Intel Atom Processor (Denverton)", 3688 .versions = (X86CPUVersionDefinition[]) { 3689 { .version = 1 }, 3690 { 3691 .version = 2, 3692 .note = "no MPX, no MONITOR", 3693 .props = (PropValue[]) { 3694 { "monitor", "off" }, 3695 { "mpx", "off" }, 3696 { /* end of list */ }, 3697 }, 3698 }, 3699 { 3700 .version = 3, 3701 .note = "XSAVES, no MPX, no MONITOR", 3702 .props = (PropValue[]) { 3703 { "xsaves", "on" }, 3704 { "vmx-xsaves", "on" }, 3705 { /* end of list */ }, 3706 }, 3707 }, 3708 { /* end of list */ }, 3709 }, 3710 }, 3711 { 3712 .name = "Snowridge", 3713 .level = 27, 3714 .vendor = CPUID_VENDOR_INTEL, 3715 .family = 6, 3716 .model = 134, 3717 .stepping = 1, 3718 .features[FEAT_1_EDX] = 3719 /* missing: CPUID_PN CPUID_IA64 */ 3720 /* missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 3721 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | 3722 CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_MCE | 3723 CPUID_CX8 | CPUID_APIC | CPUID_SEP | 3724 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 3725 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | 3726 CPUID_MMX | 3727 CPUID_FXSR | CPUID_SSE | CPUID_SSE2, 3728 .features[FEAT_1_ECX] = 3729 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR | 3730 CPUID_EXT_SSSE3 | 3731 CPUID_EXT_CX16 | 3732 CPUID_EXT_SSE41 | 3733 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 3734 CPUID_EXT_POPCNT | 3735 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | CPUID_EXT_XSAVE | 3736 CPUID_EXT_RDRAND, 3737 .features[FEAT_8000_0001_EDX] = 3738 CPUID_EXT2_SYSCALL | 3739 CPUID_EXT2_NX | 3740 CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3741 CPUID_EXT2_LM, 3742 .features[FEAT_8000_0001_ECX] = 3743 CPUID_EXT3_LAHF_LM | 3744 CPUID_EXT3_3DNOWPREFETCH, 3745 .features[FEAT_7_0_EBX] = 3746 CPUID_7_0_EBX_FSGSBASE | 3747 CPUID_7_0_EBX_SMEP | 3748 CPUID_7_0_EBX_ERMS | 3749 CPUID_7_0_EBX_MPX | /* missing bits 13, 15 */ 3750 CPUID_7_0_EBX_RDSEED | 3751 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 3752 CPUID_7_0_EBX_CLWB | 3753 CPUID_7_0_EBX_SHA_NI, 3754 .features[FEAT_7_0_ECX] = 3755 CPUID_7_0_ECX_UMIP | 3756 /* missing bit 5 */ 3757 CPUID_7_0_ECX_GFNI | 3758 CPUID_7_0_ECX_MOVDIRI | CPUID_7_0_ECX_CLDEMOTE | 3759 CPUID_7_0_ECX_MOVDIR64B, 3760 .features[FEAT_7_0_EDX] = 3761 CPUID_7_0_EDX_SPEC_CTRL | 3762 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD | 3763 CPUID_7_0_EDX_CORE_CAPABILITY, 3764 .features[FEAT_CORE_CAPABILITY] = 3765 MSR_CORE_CAP_SPLIT_LOCK_DETECT, 3766 /* XSAVES is added in version 3 */ 3767 .features[FEAT_XSAVE] = 3768 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3769 CPUID_XSAVE_XGETBV1, 3770 .features[FEAT_6_EAX] = 3771 CPUID_6_EAX_ARAT, 3772 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3773 MSR_VMX_BASIC_TRUE_CTLS, 3774 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3775 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3776 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3777 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3778 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3779 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3780 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3781 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3782 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3783 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3784 .features[FEAT_VMX_EXIT_CTLS] = 3785 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3786 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3787 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3788 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3789 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3790 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3791 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3792 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3793 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3794 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3795 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3796 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3797 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3798 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3799 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3800 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3801 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3802 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3803 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3804 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3805 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3806 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3807 .features[FEAT_VMX_SECONDARY_CTLS] = 3808 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3809 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3810 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3811 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3812 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3813 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3814 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3815 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3816 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3817 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3818 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3819 .xlevel = 0x80000008, 3820 .model_id = "Intel Atom Processor (SnowRidge)", 3821 .versions = (X86CPUVersionDefinition[]) { 3822 { .version = 1 }, 3823 { 3824 .version = 2, 3825 .props = (PropValue[]) { 3826 { "mpx", "off" }, 3827 { "model-id", "Intel Atom Processor (Snowridge, no MPX)" }, 3828 { /* end of list */ }, 3829 }, 3830 }, 3831 { 3832 .version = 3, 3833 .note = "XSAVES, no MPX", 3834 .props = (PropValue[]) { 3835 { "xsaves", "on" }, 3836 { "vmx-xsaves", "on" }, 3837 { /* end of list */ }, 3838 }, 3839 }, 3840 { 3841 .version = 4, 3842 .note = "no split lock detect, no core-capability", 3843 .props = (PropValue[]) { 3844 { "split-lock-detect", "off" }, 3845 { "core-capability", "off" }, 3846 { /* end of list */ }, 3847 }, 3848 }, 3849 { /* end of list */ }, 3850 }, 3851 }, 3852 { 3853 .name = "KnightsMill", 3854 .level = 0xd, 3855 .vendor = CPUID_VENDOR_INTEL, 3856 .family = 6, 3857 .model = 133, 3858 .stepping = 0, 3859 .features[FEAT_1_EDX] = 3860 CPUID_VME | CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | 3861 CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | 3862 CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | 3863 CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | 3864 CPUID_PSE | CPUID_DE | CPUID_FP87, 3865 .features[FEAT_1_ECX] = 3866 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3867 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3868 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3869 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3870 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3871 CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3872 .features[FEAT_8000_0001_EDX] = 3873 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3874 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3875 .features[FEAT_8000_0001_ECX] = 3876 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3877 .features[FEAT_7_0_EBX] = 3878 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 3879 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 3880 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_AVX512F | 3881 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_AVX512PF | 3882 CPUID_7_0_EBX_AVX512ER, 3883 .features[FEAT_7_0_ECX] = 3884 CPUID_7_0_ECX_AVX512_VPOPCNTDQ, 3885 .features[FEAT_7_0_EDX] = 3886 CPUID_7_0_EDX_AVX512_4VNNIW | CPUID_7_0_EDX_AVX512_4FMAPS, 3887 .features[FEAT_XSAVE] = 3888 CPUID_XSAVE_XSAVEOPT, 3889 .features[FEAT_6_EAX] = 3890 CPUID_6_EAX_ARAT, 3891 .xlevel = 0x80000008, 3892 .model_id = "Intel Xeon Phi Processor (Knights Mill)", 3893 }, 3894 { 3895 .name = "Opteron_G1", 3896 .level = 5, 3897 .vendor = CPUID_VENDOR_AMD, 3898 .family = 15, 3899 .model = 6, 3900 .stepping = 1, 3901 .features[FEAT_1_EDX] = 3902 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3903 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3904 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3905 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3906 CPUID_DE | CPUID_FP87, 3907 .features[FEAT_1_ECX] = 3908 CPUID_EXT_SSE3, 3909 .features[FEAT_8000_0001_EDX] = 3910 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3911 .xlevel = 0x80000008, 3912 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)", 3913 }, 3914 { 3915 .name = "Opteron_G2", 3916 .level = 5, 3917 .vendor = CPUID_VENDOR_AMD, 3918 .family = 15, 3919 .model = 6, 3920 .stepping = 1, 3921 .features[FEAT_1_EDX] = 3922 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3923 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3924 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3925 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3926 CPUID_DE | CPUID_FP87, 3927 .features[FEAT_1_ECX] = 3928 CPUID_EXT_CX16 | CPUID_EXT_SSE3, 3929 .features[FEAT_8000_0001_EDX] = 3930 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3931 .features[FEAT_8000_0001_ECX] = 3932 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, 3933 .xlevel = 0x80000008, 3934 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)", 3935 }, 3936 { 3937 .name = "Opteron_G3", 3938 .level = 5, 3939 .vendor = CPUID_VENDOR_AMD, 3940 .family = 16, 3941 .model = 2, 3942 .stepping = 3, 3943 .features[FEAT_1_EDX] = 3944 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3945 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3946 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3947 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3948 CPUID_DE | CPUID_FP87, 3949 .features[FEAT_1_ECX] = 3950 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR | 3951 CPUID_EXT_SSE3, 3952 .features[FEAT_8000_0001_EDX] = 3953 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL | 3954 CPUID_EXT2_RDTSCP, 3955 .features[FEAT_8000_0001_ECX] = 3956 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | 3957 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, 3958 .xlevel = 0x80000008, 3959 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)", 3960 }, 3961 { 3962 .name = "Opteron_G4", 3963 .level = 0xd, 3964 .vendor = CPUID_VENDOR_AMD, 3965 .family = 21, 3966 .model = 1, 3967 .stepping = 2, 3968 .features[FEAT_1_EDX] = 3969 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3970 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3971 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3972 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3973 CPUID_DE | CPUID_FP87, 3974 .features[FEAT_1_ECX] = 3975 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3976 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 3977 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 3978 CPUID_EXT_SSE3, 3979 .features[FEAT_8000_0001_EDX] = 3980 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX | 3981 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP, 3982 .features[FEAT_8000_0001_ECX] = 3983 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP | 3984 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | 3985 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | 3986 CPUID_EXT3_LAHF_LM, 3987 .features[FEAT_SVM] = 3988 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 3989 /* no xsaveopt! */ 3990 .xlevel = 0x8000001A, 3991 .model_id = "AMD Opteron 62xx class CPU", 3992 }, 3993 { 3994 .name = "Opteron_G5", 3995 .level = 0xd, 3996 .vendor = CPUID_VENDOR_AMD, 3997 .family = 21, 3998 .model = 2, 3999 .stepping = 0, 4000 .features[FEAT_1_EDX] = 4001 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4002 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4003 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4004 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4005 CPUID_DE | CPUID_FP87, 4006 .features[FEAT_1_ECX] = 4007 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE | 4008 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | 4009 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA | 4010 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 4011 .features[FEAT_8000_0001_EDX] = 4012 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX | 4013 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP, 4014 .features[FEAT_8000_0001_ECX] = 4015 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP | 4016 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | 4017 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | 4018 CPUID_EXT3_LAHF_LM, 4019 .features[FEAT_SVM] = 4020 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 4021 /* no xsaveopt! */ 4022 .xlevel = 0x8000001A, 4023 .model_id = "AMD Opteron 63xx class CPU", 4024 }, 4025 { 4026 .name = "EPYC", 4027 .level = 0xd, 4028 .vendor = CPUID_VENDOR_AMD, 4029 .family = 23, 4030 .model = 1, 4031 .stepping = 2, 4032 .features[FEAT_1_EDX] = 4033 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 4034 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 4035 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 4036 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 4037 CPUID_VME | CPUID_FP87, 4038 .features[FEAT_1_ECX] = 4039 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 4040 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 4041 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 4042 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 4043 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 4044 .features[FEAT_8000_0001_EDX] = 4045 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 4046 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 4047 CPUID_EXT2_SYSCALL, 4048 .features[FEAT_8000_0001_ECX] = 4049 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 4050 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 4051 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 4052 CPUID_EXT3_TOPOEXT, 4053 .features[FEAT_7_0_EBX] = 4054 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4055 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 4056 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 4057 CPUID_7_0_EBX_SHA_NI, 4058 .features[FEAT_XSAVE] = 4059 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4060 CPUID_XSAVE_XGETBV1, 4061 .features[FEAT_6_EAX] = 4062 CPUID_6_EAX_ARAT, 4063 .features[FEAT_SVM] = 4064 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 4065 .xlevel = 0x8000001E, 4066 .model_id = "AMD EPYC Processor", 4067 .cache_info = &epyc_cache_info, 4068 .versions = (X86CPUVersionDefinition[]) { 4069 { .version = 1 }, 4070 { 4071 .version = 2, 4072 .alias = "EPYC-IBPB", 4073 .props = (PropValue[]) { 4074 { "ibpb", "on" }, 4075 { "model-id", 4076 "AMD EPYC Processor (with IBPB)" }, 4077 { /* end of list */ } 4078 } 4079 }, 4080 { 4081 .version = 3, 4082 .props = (PropValue[]) { 4083 { "ibpb", "on" }, 4084 { "perfctr-core", "on" }, 4085 { "clzero", "on" }, 4086 { "xsaveerptr", "on" }, 4087 { "xsaves", "on" }, 4088 { "model-id", 4089 "AMD EPYC Processor" }, 4090 { /* end of list */ } 4091 } 4092 }, 4093 { /* end of list */ } 4094 } 4095 }, 4096 { 4097 .name = "Dhyana", 4098 .level = 0xd, 4099 .vendor = CPUID_VENDOR_HYGON, 4100 .family = 24, 4101 .model = 0, 4102 .stepping = 1, 4103 .features[FEAT_1_EDX] = 4104 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 4105 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 4106 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 4107 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 4108 CPUID_VME | CPUID_FP87, 4109 .features[FEAT_1_ECX] = 4110 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 4111 CPUID_EXT_XSAVE | CPUID_EXT_POPCNT | 4112 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 4113 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 4114 CPUID_EXT_MONITOR | CPUID_EXT_SSE3, 4115 .features[FEAT_8000_0001_EDX] = 4116 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 4117 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 4118 CPUID_EXT2_SYSCALL, 4119 .features[FEAT_8000_0001_ECX] = 4120 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 4121 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 4122 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 4123 CPUID_EXT3_TOPOEXT, 4124 .features[FEAT_8000_0008_EBX] = 4125 CPUID_8000_0008_EBX_IBPB, 4126 .features[FEAT_7_0_EBX] = 4127 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4128 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 4129 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT, 4130 /* XSAVES is added in version 2 */ 4131 .features[FEAT_XSAVE] = 4132 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4133 CPUID_XSAVE_XGETBV1, 4134 .features[FEAT_6_EAX] = 4135 CPUID_6_EAX_ARAT, 4136 .features[FEAT_SVM] = 4137 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 4138 .xlevel = 0x8000001E, 4139 .model_id = "Hygon Dhyana Processor", 4140 .cache_info = &epyc_cache_info, 4141 .versions = (X86CPUVersionDefinition[]) { 4142 { .version = 1 }, 4143 { .version = 2, 4144 .note = "XSAVES", 4145 .props = (PropValue[]) { 4146 { "xsaves", "on" }, 4147 { /* end of list */ } 4148 }, 4149 }, 4150 { /* end of list */ } 4151 } 4152 }, 4153 { 4154 .name = "EPYC-Rome", 4155 .level = 0xd, 4156 .vendor = CPUID_VENDOR_AMD, 4157 .family = 23, 4158 .model = 49, 4159 .stepping = 0, 4160 .features[FEAT_1_EDX] = 4161 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 4162 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 4163 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 4164 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 4165 CPUID_VME | CPUID_FP87, 4166 .features[FEAT_1_ECX] = 4167 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 4168 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 4169 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 4170 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 4171 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 4172 .features[FEAT_8000_0001_EDX] = 4173 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 4174 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 4175 CPUID_EXT2_SYSCALL, 4176 .features[FEAT_8000_0001_ECX] = 4177 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 4178 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 4179 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 4180 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 4181 .features[FEAT_8000_0008_EBX] = 4182 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 4183 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 4184 CPUID_8000_0008_EBX_STIBP, 4185 .features[FEAT_7_0_EBX] = 4186 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4187 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 4188 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 4189 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB, 4190 .features[FEAT_7_0_ECX] = 4191 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID, 4192 .features[FEAT_XSAVE] = 4193 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4194 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 4195 .features[FEAT_6_EAX] = 4196 CPUID_6_EAX_ARAT, 4197 .features[FEAT_SVM] = 4198 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 4199 .xlevel = 0x8000001E, 4200 .model_id = "AMD EPYC-Rome Processor", 4201 .cache_info = &epyc_rome_cache_info, 4202 .versions = (X86CPUVersionDefinition[]) { 4203 { .version = 1 }, 4204 { 4205 .version = 2, 4206 .props = (PropValue[]) { 4207 { "ibrs", "on" }, 4208 { "amd-ssbd", "on" }, 4209 { /* end of list */ } 4210 } 4211 }, 4212 { /* end of list */ } 4213 } 4214 }, 4215 { 4216 .name = "EPYC-Milan", 4217 .level = 0xd, 4218 .vendor = CPUID_VENDOR_AMD, 4219 .family = 25, 4220 .model = 1, 4221 .stepping = 1, 4222 .features[FEAT_1_EDX] = 4223 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 4224 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 4225 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 4226 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 4227 CPUID_VME | CPUID_FP87, 4228 .features[FEAT_1_ECX] = 4229 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 4230 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 4231 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 4232 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 4233 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 4234 CPUID_EXT_PCID, 4235 .features[FEAT_8000_0001_EDX] = 4236 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 4237 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 4238 CPUID_EXT2_SYSCALL, 4239 .features[FEAT_8000_0001_ECX] = 4240 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 4241 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 4242 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 4243 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 4244 .features[FEAT_8000_0008_EBX] = 4245 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 4246 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 4247 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | 4248 CPUID_8000_0008_EBX_AMD_SSBD, 4249 .features[FEAT_7_0_EBX] = 4250 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4251 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 4252 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 4253 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_ERMS | 4254 CPUID_7_0_EBX_INVPCID, 4255 .features[FEAT_7_0_ECX] = 4256 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_PKU, 4257 .features[FEAT_7_0_EDX] = 4258 CPUID_7_0_EDX_FSRM, 4259 .features[FEAT_XSAVE] = 4260 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4261 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 4262 .features[FEAT_6_EAX] = 4263 CPUID_6_EAX_ARAT, 4264 .features[FEAT_SVM] = 4265 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE | CPUID_SVM_SVME_ADDR_CHK, 4266 .xlevel = 0x8000001E, 4267 .model_id = "AMD EPYC-Milan Processor", 4268 .cache_info = &epyc_milan_cache_info, 4269 }, 4270 }; 4271 4272 /* 4273 * We resolve CPU model aliases using -v1 when using "-machine 4274 * none", but this is just for compatibility while libvirt isn't 4275 * adapted to resolve CPU model versions before creating VMs. 4276 * See "Runnability guarantee of CPU models" at 4277 * docs/about/deprecated.rst. 4278 */ 4279 X86CPUVersion default_cpu_version = 1; 4280 4281 void x86_cpu_set_default_version(X86CPUVersion version) 4282 { 4283 /* Translating CPU_VERSION_AUTO to CPU_VERSION_AUTO doesn't make sense */ 4284 assert(version != CPU_VERSION_AUTO); 4285 default_cpu_version = version; 4286 } 4287 4288 static X86CPUVersion x86_cpu_model_last_version(const X86CPUModel *model) 4289 { 4290 int v = 0; 4291 const X86CPUVersionDefinition *vdef = 4292 x86_cpu_def_get_versions(model->cpudef); 4293 while (vdef->version) { 4294 v = vdef->version; 4295 vdef++; 4296 } 4297 return v; 4298 } 4299 4300 /* Return the actual version being used for a specific CPU model */ 4301 static X86CPUVersion x86_cpu_model_resolve_version(const X86CPUModel *model) 4302 { 4303 X86CPUVersion v = model->version; 4304 if (v == CPU_VERSION_AUTO) { 4305 v = default_cpu_version; 4306 } 4307 if (v == CPU_VERSION_LATEST) { 4308 return x86_cpu_model_last_version(model); 4309 } 4310 return v; 4311 } 4312 4313 static Property max_x86_cpu_properties[] = { 4314 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true), 4315 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false), 4316 DEFINE_PROP_END_OF_LIST() 4317 }; 4318 4319 static void max_x86_cpu_class_init(ObjectClass *oc, void *data) 4320 { 4321 DeviceClass *dc = DEVICE_CLASS(oc); 4322 X86CPUClass *xcc = X86_CPU_CLASS(oc); 4323 4324 xcc->ordering = 9; 4325 4326 xcc->model_description = 4327 "Enables all features supported by the accelerator in the current host"; 4328 4329 device_class_set_props(dc, max_x86_cpu_properties); 4330 } 4331 4332 static void max_x86_cpu_initfn(Object *obj) 4333 { 4334 X86CPU *cpu = X86_CPU(obj); 4335 4336 /* We can't fill the features array here because we don't know yet if 4337 * "migratable" is true or false. 4338 */ 4339 cpu->max_features = true; 4340 object_property_set_bool(OBJECT(cpu), "pmu", true, &error_abort); 4341 4342 /* 4343 * these defaults are used for TCG and all other accelerators 4344 * besides KVM and HVF, which overwrite these values 4345 */ 4346 object_property_set_str(OBJECT(cpu), "vendor", CPUID_VENDOR_AMD, 4347 &error_abort); 4348 #ifdef TARGET_X86_64 4349 object_property_set_int(OBJECT(cpu), "family", 15, &error_abort); 4350 object_property_set_int(OBJECT(cpu), "model", 107, &error_abort); 4351 object_property_set_int(OBJECT(cpu), "stepping", 1, &error_abort); 4352 #else 4353 object_property_set_int(OBJECT(cpu), "family", 6, &error_abort); 4354 object_property_set_int(OBJECT(cpu), "model", 6, &error_abort); 4355 object_property_set_int(OBJECT(cpu), "stepping", 3, &error_abort); 4356 #endif 4357 object_property_set_str(OBJECT(cpu), "model-id", 4358 "QEMU TCG CPU version " QEMU_HW_VERSION, 4359 &error_abort); 4360 } 4361 4362 static const TypeInfo max_x86_cpu_type_info = { 4363 .name = X86_CPU_TYPE_NAME("max"), 4364 .parent = TYPE_X86_CPU, 4365 .instance_init = max_x86_cpu_initfn, 4366 .class_init = max_x86_cpu_class_init, 4367 }; 4368 4369 static char *feature_word_description(FeatureWordInfo *f, uint32_t bit) 4370 { 4371 assert(f->type == CPUID_FEATURE_WORD || f->type == MSR_FEATURE_WORD); 4372 4373 switch (f->type) { 4374 case CPUID_FEATURE_WORD: 4375 { 4376 const char *reg = get_register_name_32(f->cpuid.reg); 4377 assert(reg); 4378 return g_strdup_printf("CPUID.%02XH:%s", 4379 f->cpuid.eax, reg); 4380 } 4381 case MSR_FEATURE_WORD: 4382 return g_strdup_printf("MSR(%02XH)", 4383 f->msr.index); 4384 } 4385 4386 return NULL; 4387 } 4388 4389 static bool x86_cpu_have_filtered_features(X86CPU *cpu) 4390 { 4391 FeatureWord w; 4392 4393 for (w = 0; w < FEATURE_WORDS; w++) { 4394 if (cpu->filtered_features[w]) { 4395 return true; 4396 } 4397 } 4398 4399 return false; 4400 } 4401 4402 static void mark_unavailable_features(X86CPU *cpu, FeatureWord w, uint64_t mask, 4403 const char *verbose_prefix) 4404 { 4405 CPUX86State *env = &cpu->env; 4406 FeatureWordInfo *f = &feature_word_info[w]; 4407 int i; 4408 4409 if (!cpu->force_features) { 4410 env->features[w] &= ~mask; 4411 } 4412 cpu->filtered_features[w] |= mask; 4413 4414 if (!verbose_prefix) { 4415 return; 4416 } 4417 4418 for (i = 0; i < 64; ++i) { 4419 if ((1ULL << i) & mask) { 4420 g_autofree char *feat_word_str = feature_word_description(f, i); 4421 warn_report("%s: %s%s%s [bit %d]", 4422 verbose_prefix, 4423 feat_word_str, 4424 f->feat_names[i] ? "." : "", 4425 f->feat_names[i] ? f->feat_names[i] : "", i); 4426 } 4427 } 4428 } 4429 4430 static void x86_cpuid_version_get_family(Object *obj, Visitor *v, 4431 const char *name, void *opaque, 4432 Error **errp) 4433 { 4434 X86CPU *cpu = X86_CPU(obj); 4435 CPUX86State *env = &cpu->env; 4436 int64_t value; 4437 4438 value = (env->cpuid_version >> 8) & 0xf; 4439 if (value == 0xf) { 4440 value += (env->cpuid_version >> 20) & 0xff; 4441 } 4442 visit_type_int(v, name, &value, errp); 4443 } 4444 4445 static void x86_cpuid_version_set_family(Object *obj, Visitor *v, 4446 const char *name, void *opaque, 4447 Error **errp) 4448 { 4449 X86CPU *cpu = X86_CPU(obj); 4450 CPUX86State *env = &cpu->env; 4451 const int64_t min = 0; 4452 const int64_t max = 0xff + 0xf; 4453 int64_t value; 4454 4455 if (!visit_type_int(v, name, &value, errp)) { 4456 return; 4457 } 4458 if (value < min || value > max) { 4459 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", 4460 name ? name : "null", value, min, max); 4461 return; 4462 } 4463 4464 env->cpuid_version &= ~0xff00f00; 4465 if (value > 0x0f) { 4466 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20); 4467 } else { 4468 env->cpuid_version |= value << 8; 4469 } 4470 } 4471 4472 static void x86_cpuid_version_get_model(Object *obj, Visitor *v, 4473 const char *name, void *opaque, 4474 Error **errp) 4475 { 4476 X86CPU *cpu = X86_CPU(obj); 4477 CPUX86State *env = &cpu->env; 4478 int64_t value; 4479 4480 value = (env->cpuid_version >> 4) & 0xf; 4481 value |= ((env->cpuid_version >> 16) & 0xf) << 4; 4482 visit_type_int(v, name, &value, errp); 4483 } 4484 4485 static void x86_cpuid_version_set_model(Object *obj, Visitor *v, 4486 const char *name, void *opaque, 4487 Error **errp) 4488 { 4489 X86CPU *cpu = X86_CPU(obj); 4490 CPUX86State *env = &cpu->env; 4491 const int64_t min = 0; 4492 const int64_t max = 0xff; 4493 int64_t value; 4494 4495 if (!visit_type_int(v, name, &value, errp)) { 4496 return; 4497 } 4498 if (value < min || value > max) { 4499 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", 4500 name ? name : "null", value, min, max); 4501 return; 4502 } 4503 4504 env->cpuid_version &= ~0xf00f0; 4505 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16); 4506 } 4507 4508 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v, 4509 const char *name, void *opaque, 4510 Error **errp) 4511 { 4512 X86CPU *cpu = X86_CPU(obj); 4513 CPUX86State *env = &cpu->env; 4514 int64_t value; 4515 4516 value = env->cpuid_version & 0xf; 4517 visit_type_int(v, name, &value, errp); 4518 } 4519 4520 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v, 4521 const char *name, void *opaque, 4522 Error **errp) 4523 { 4524 X86CPU *cpu = X86_CPU(obj); 4525 CPUX86State *env = &cpu->env; 4526 const int64_t min = 0; 4527 const int64_t max = 0xf; 4528 int64_t value; 4529 4530 if (!visit_type_int(v, name, &value, errp)) { 4531 return; 4532 } 4533 if (value < min || value > max) { 4534 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", 4535 name ? name : "null", value, min, max); 4536 return; 4537 } 4538 4539 env->cpuid_version &= ~0xf; 4540 env->cpuid_version |= value & 0xf; 4541 } 4542 4543 static char *x86_cpuid_get_vendor(Object *obj, Error **errp) 4544 { 4545 X86CPU *cpu = X86_CPU(obj); 4546 CPUX86State *env = &cpu->env; 4547 char *value; 4548 4549 value = g_malloc(CPUID_VENDOR_SZ + 1); 4550 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2, 4551 env->cpuid_vendor3); 4552 return value; 4553 } 4554 4555 static void x86_cpuid_set_vendor(Object *obj, const char *value, 4556 Error **errp) 4557 { 4558 X86CPU *cpu = X86_CPU(obj); 4559 CPUX86State *env = &cpu->env; 4560 int i; 4561 4562 if (strlen(value) != CPUID_VENDOR_SZ) { 4563 error_setg(errp, QERR_PROPERTY_VALUE_BAD, "", "vendor", value); 4564 return; 4565 } 4566 4567 env->cpuid_vendor1 = 0; 4568 env->cpuid_vendor2 = 0; 4569 env->cpuid_vendor3 = 0; 4570 for (i = 0; i < 4; i++) { 4571 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i); 4572 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i); 4573 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i); 4574 } 4575 } 4576 4577 static char *x86_cpuid_get_model_id(Object *obj, Error **errp) 4578 { 4579 X86CPU *cpu = X86_CPU(obj); 4580 CPUX86State *env = &cpu->env; 4581 char *value; 4582 int i; 4583 4584 value = g_malloc(48 + 1); 4585 for (i = 0; i < 48; i++) { 4586 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3)); 4587 } 4588 value[48] = '\0'; 4589 return value; 4590 } 4591 4592 static void x86_cpuid_set_model_id(Object *obj, const char *model_id, 4593 Error **errp) 4594 { 4595 X86CPU *cpu = X86_CPU(obj); 4596 CPUX86State *env = &cpu->env; 4597 int c, len, i; 4598 4599 if (model_id == NULL) { 4600 model_id = ""; 4601 } 4602 len = strlen(model_id); 4603 memset(env->cpuid_model, 0, 48); 4604 for (i = 0; i < 48; i++) { 4605 if (i >= len) { 4606 c = '\0'; 4607 } else { 4608 c = (uint8_t)model_id[i]; 4609 } 4610 env->cpuid_model[i >> 2] |= c << (8 * (i & 3)); 4611 } 4612 } 4613 4614 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name, 4615 void *opaque, Error **errp) 4616 { 4617 X86CPU *cpu = X86_CPU(obj); 4618 int64_t value; 4619 4620 value = cpu->env.tsc_khz * 1000; 4621 visit_type_int(v, name, &value, errp); 4622 } 4623 4624 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name, 4625 void *opaque, Error **errp) 4626 { 4627 X86CPU *cpu = X86_CPU(obj); 4628 const int64_t min = 0; 4629 const int64_t max = INT64_MAX; 4630 int64_t value; 4631 4632 if (!visit_type_int(v, name, &value, errp)) { 4633 return; 4634 } 4635 if (value < min || value > max) { 4636 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", 4637 name ? name : "null", value, min, max); 4638 return; 4639 } 4640 4641 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000; 4642 } 4643 4644 /* Generic getter for "feature-words" and "filtered-features" properties */ 4645 static void x86_cpu_get_feature_words(Object *obj, Visitor *v, 4646 const char *name, void *opaque, 4647 Error **errp) 4648 { 4649 uint64_t *array = (uint64_t *)opaque; 4650 FeatureWord w; 4651 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { }; 4652 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { }; 4653 X86CPUFeatureWordInfoList *list = NULL; 4654 4655 for (w = 0; w < FEATURE_WORDS; w++) { 4656 FeatureWordInfo *wi = &feature_word_info[w]; 4657 /* 4658 * We didn't have MSR features when "feature-words" was 4659 * introduced. Therefore skipped other type entries. 4660 */ 4661 if (wi->type != CPUID_FEATURE_WORD) { 4662 continue; 4663 } 4664 X86CPUFeatureWordInfo *qwi = &word_infos[w]; 4665 qwi->cpuid_input_eax = wi->cpuid.eax; 4666 qwi->has_cpuid_input_ecx = wi->cpuid.needs_ecx; 4667 qwi->cpuid_input_ecx = wi->cpuid.ecx; 4668 qwi->cpuid_register = x86_reg_info_32[wi->cpuid.reg].qapi_enum; 4669 qwi->features = array[w]; 4670 4671 /* List will be in reverse order, but order shouldn't matter */ 4672 list_entries[w].next = list; 4673 list_entries[w].value = &word_infos[w]; 4674 list = &list_entries[w]; 4675 } 4676 4677 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp); 4678 } 4679 4680 /* Convert all '_' in a feature string option name to '-', to make feature 4681 * name conform to QOM property naming rule, which uses '-' instead of '_'. 4682 */ 4683 static inline void feat2prop(char *s) 4684 { 4685 while ((s = strchr(s, '_'))) { 4686 *s = '-'; 4687 } 4688 } 4689 4690 /* Return the feature property name for a feature flag bit */ 4691 static const char *x86_cpu_feature_name(FeatureWord w, int bitnr) 4692 { 4693 const char *name; 4694 /* XSAVE components are automatically enabled by other features, 4695 * so return the original feature name instead 4696 */ 4697 if (w == FEAT_XSAVE_XCR0_LO || w == FEAT_XSAVE_XCR0_HI) { 4698 int comp = (w == FEAT_XSAVE_XCR0_HI) ? bitnr + 32 : bitnr; 4699 4700 if (comp < ARRAY_SIZE(x86_ext_save_areas) && 4701 x86_ext_save_areas[comp].bits) { 4702 w = x86_ext_save_areas[comp].feature; 4703 bitnr = ctz32(x86_ext_save_areas[comp].bits); 4704 } 4705 } 4706 4707 assert(bitnr < 64); 4708 assert(w < FEATURE_WORDS); 4709 name = feature_word_info[w].feat_names[bitnr]; 4710 assert(bitnr < 32 || !(name && feature_word_info[w].type == CPUID_FEATURE_WORD)); 4711 return name; 4712 } 4713 4714 /* Compatibily hack to maintain legacy +-feat semantic, 4715 * where +-feat overwrites any feature set by 4716 * feat=on|feat even if the later is parsed after +-feat 4717 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled) 4718 */ 4719 static GList *plus_features, *minus_features; 4720 4721 static gint compare_string(gconstpointer a, gconstpointer b) 4722 { 4723 return g_strcmp0(a, b); 4724 } 4725 4726 /* Parse "+feature,-feature,feature=foo" CPU feature string 4727 */ 4728 static void x86_cpu_parse_featurestr(const char *typename, char *features, 4729 Error **errp) 4730 { 4731 char *featurestr; /* Single 'key=value" string being parsed */ 4732 static bool cpu_globals_initialized; 4733 bool ambiguous = false; 4734 4735 if (cpu_globals_initialized) { 4736 return; 4737 } 4738 cpu_globals_initialized = true; 4739 4740 if (!features) { 4741 return; 4742 } 4743 4744 for (featurestr = strtok(features, ","); 4745 featurestr; 4746 featurestr = strtok(NULL, ",")) { 4747 const char *name; 4748 const char *val = NULL; 4749 char *eq = NULL; 4750 char num[32]; 4751 GlobalProperty *prop; 4752 4753 /* Compatibility syntax: */ 4754 if (featurestr[0] == '+') { 4755 plus_features = g_list_append(plus_features, 4756 g_strdup(featurestr + 1)); 4757 continue; 4758 } else if (featurestr[0] == '-') { 4759 minus_features = g_list_append(minus_features, 4760 g_strdup(featurestr + 1)); 4761 continue; 4762 } 4763 4764 eq = strchr(featurestr, '='); 4765 if (eq) { 4766 *eq++ = 0; 4767 val = eq; 4768 } else { 4769 val = "on"; 4770 } 4771 4772 feat2prop(featurestr); 4773 name = featurestr; 4774 4775 if (g_list_find_custom(plus_features, name, compare_string)) { 4776 warn_report("Ambiguous CPU model string. " 4777 "Don't mix both \"+%s\" and \"%s=%s\"", 4778 name, name, val); 4779 ambiguous = true; 4780 } 4781 if (g_list_find_custom(minus_features, name, compare_string)) { 4782 warn_report("Ambiguous CPU model string. " 4783 "Don't mix both \"-%s\" and \"%s=%s\"", 4784 name, name, val); 4785 ambiguous = true; 4786 } 4787 4788 /* Special case: */ 4789 if (!strcmp(name, "tsc-freq")) { 4790 int ret; 4791 uint64_t tsc_freq; 4792 4793 ret = qemu_strtosz_metric(val, NULL, &tsc_freq); 4794 if (ret < 0 || tsc_freq > INT64_MAX) { 4795 error_setg(errp, "bad numerical value %s", val); 4796 return; 4797 } 4798 snprintf(num, sizeof(num), "%" PRId64, tsc_freq); 4799 val = num; 4800 name = "tsc-frequency"; 4801 } 4802 4803 prop = g_new0(typeof(*prop), 1); 4804 prop->driver = typename; 4805 prop->property = g_strdup(name); 4806 prop->value = g_strdup(val); 4807 qdev_prop_register_global(prop); 4808 } 4809 4810 if (ambiguous) { 4811 warn_report("Compatibility of ambiguous CPU model " 4812 "strings won't be kept on future QEMU versions"); 4813 } 4814 } 4815 4816 static void x86_cpu_filter_features(X86CPU *cpu, bool verbose); 4817 4818 /* Build a list with the name of all features on a feature word array */ 4819 static void x86_cpu_list_feature_names(FeatureWordArray features, 4820 strList **list) 4821 { 4822 strList **tail = list; 4823 FeatureWord w; 4824 4825 for (w = 0; w < FEATURE_WORDS; w++) { 4826 uint64_t filtered = features[w]; 4827 int i; 4828 for (i = 0; i < 64; i++) { 4829 if (filtered & (1ULL << i)) { 4830 QAPI_LIST_APPEND(tail, g_strdup(x86_cpu_feature_name(w, i))); 4831 } 4832 } 4833 } 4834 } 4835 4836 static void x86_cpu_get_unavailable_features(Object *obj, Visitor *v, 4837 const char *name, void *opaque, 4838 Error **errp) 4839 { 4840 X86CPU *xc = X86_CPU(obj); 4841 strList *result = NULL; 4842 4843 x86_cpu_list_feature_names(xc->filtered_features, &result); 4844 visit_type_strList(v, "unavailable-features", &result, errp); 4845 } 4846 4847 /* Print all cpuid feature names in featureset 4848 */ 4849 static void listflags(GList *features) 4850 { 4851 size_t len = 0; 4852 GList *tmp; 4853 4854 for (tmp = features; tmp; tmp = tmp->next) { 4855 const char *name = tmp->data; 4856 if ((len + strlen(name) + 1) >= 75) { 4857 qemu_printf("\n"); 4858 len = 0; 4859 } 4860 qemu_printf("%s%s", len == 0 ? " " : " ", name); 4861 len += strlen(name) + 1; 4862 } 4863 qemu_printf("\n"); 4864 } 4865 4866 /* Sort alphabetically by type name, respecting X86CPUClass::ordering. */ 4867 static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b) 4868 { 4869 ObjectClass *class_a = (ObjectClass *)a; 4870 ObjectClass *class_b = (ObjectClass *)b; 4871 X86CPUClass *cc_a = X86_CPU_CLASS(class_a); 4872 X86CPUClass *cc_b = X86_CPU_CLASS(class_b); 4873 int ret; 4874 4875 if (cc_a->ordering != cc_b->ordering) { 4876 ret = cc_a->ordering - cc_b->ordering; 4877 } else { 4878 g_autofree char *name_a = x86_cpu_class_get_model_name(cc_a); 4879 g_autofree char *name_b = x86_cpu_class_get_model_name(cc_b); 4880 ret = strcmp(name_a, name_b); 4881 } 4882 return ret; 4883 } 4884 4885 static GSList *get_sorted_cpu_model_list(void) 4886 { 4887 GSList *list = object_class_get_list(TYPE_X86_CPU, false); 4888 list = g_slist_sort(list, x86_cpu_list_compare); 4889 return list; 4890 } 4891 4892 static char *x86_cpu_class_get_model_id(X86CPUClass *xc) 4893 { 4894 Object *obj = object_new_with_class(OBJECT_CLASS(xc)); 4895 char *r = object_property_get_str(obj, "model-id", &error_abort); 4896 object_unref(obj); 4897 return r; 4898 } 4899 4900 static char *x86_cpu_class_get_alias_of(X86CPUClass *cc) 4901 { 4902 X86CPUVersion version; 4903 4904 if (!cc->model || !cc->model->is_alias) { 4905 return NULL; 4906 } 4907 version = x86_cpu_model_resolve_version(cc->model); 4908 if (version <= 0) { 4909 return NULL; 4910 } 4911 return x86_cpu_versioned_model_name(cc->model->cpudef, version); 4912 } 4913 4914 static void x86_cpu_list_entry(gpointer data, gpointer user_data) 4915 { 4916 ObjectClass *oc = data; 4917 X86CPUClass *cc = X86_CPU_CLASS(oc); 4918 g_autofree char *name = x86_cpu_class_get_model_name(cc); 4919 g_autofree char *desc = g_strdup(cc->model_description); 4920 g_autofree char *alias_of = x86_cpu_class_get_alias_of(cc); 4921 g_autofree char *model_id = x86_cpu_class_get_model_id(cc); 4922 4923 if (!desc && alias_of) { 4924 if (cc->model && cc->model->version == CPU_VERSION_AUTO) { 4925 desc = g_strdup("(alias configured by machine type)"); 4926 } else { 4927 desc = g_strdup_printf("(alias of %s)", alias_of); 4928 } 4929 } 4930 if (!desc && cc->model && cc->model->note) { 4931 desc = g_strdup_printf("%s [%s]", model_id, cc->model->note); 4932 } 4933 if (!desc) { 4934 desc = g_strdup_printf("%s", model_id); 4935 } 4936 4937 if (cc->model && cc->model->cpudef->deprecation_note) { 4938 g_autofree char *olddesc = desc; 4939 desc = g_strdup_printf("%s (deprecated)", olddesc); 4940 } 4941 4942 qemu_printf("x86 %-20s %s\n", name, desc); 4943 } 4944 4945 /* list available CPU models and flags */ 4946 void x86_cpu_list(void) 4947 { 4948 int i, j; 4949 GSList *list; 4950 GList *names = NULL; 4951 4952 qemu_printf("Available CPUs:\n"); 4953 list = get_sorted_cpu_model_list(); 4954 g_slist_foreach(list, x86_cpu_list_entry, NULL); 4955 g_slist_free(list); 4956 4957 names = NULL; 4958 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) { 4959 FeatureWordInfo *fw = &feature_word_info[i]; 4960 for (j = 0; j < 64; j++) { 4961 if (fw->feat_names[j]) { 4962 names = g_list_append(names, (gpointer)fw->feat_names[j]); 4963 } 4964 } 4965 } 4966 4967 names = g_list_sort(names, (GCompareFunc)strcmp); 4968 4969 qemu_printf("\nRecognized CPUID flags:\n"); 4970 listflags(names); 4971 qemu_printf("\n"); 4972 g_list_free(names); 4973 } 4974 4975 #ifndef CONFIG_USER_ONLY 4976 4977 /* Check for missing features that may prevent the CPU class from 4978 * running using the current machine and accelerator. 4979 */ 4980 static void x86_cpu_class_check_missing_features(X86CPUClass *xcc, 4981 strList **list) 4982 { 4983 strList **tail = list; 4984 X86CPU *xc; 4985 Error *err = NULL; 4986 4987 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) { 4988 QAPI_LIST_APPEND(tail, g_strdup("kvm")); 4989 return; 4990 } 4991 4992 xc = X86_CPU(object_new_with_class(OBJECT_CLASS(xcc))); 4993 4994 x86_cpu_expand_features(xc, &err); 4995 if (err) { 4996 /* Errors at x86_cpu_expand_features should never happen, 4997 * but in case it does, just report the model as not 4998 * runnable at all using the "type" property. 4999 */ 5000 QAPI_LIST_APPEND(tail, g_strdup("type")); 5001 error_free(err); 5002 } 5003 5004 x86_cpu_filter_features(xc, false); 5005 5006 x86_cpu_list_feature_names(xc->filtered_features, tail); 5007 5008 object_unref(OBJECT(xc)); 5009 } 5010 5011 static void x86_cpu_definition_entry(gpointer data, gpointer user_data) 5012 { 5013 ObjectClass *oc = data; 5014 X86CPUClass *cc = X86_CPU_CLASS(oc); 5015 CpuDefinitionInfoList **cpu_list = user_data; 5016 CpuDefinitionInfo *info; 5017 5018 info = g_malloc0(sizeof(*info)); 5019 info->name = x86_cpu_class_get_model_name(cc); 5020 x86_cpu_class_check_missing_features(cc, &info->unavailable_features); 5021 info->has_unavailable_features = true; 5022 info->q_typename = g_strdup(object_class_get_name(oc)); 5023 info->migration_safe = cc->migration_safe; 5024 info->has_migration_safe = true; 5025 info->q_static = cc->static_model; 5026 if (cc->model && cc->model->cpudef->deprecation_note) { 5027 info->deprecated = true; 5028 } else { 5029 info->deprecated = false; 5030 } 5031 /* 5032 * Old machine types won't report aliases, so that alias translation 5033 * doesn't break compatibility with previous QEMU versions. 5034 */ 5035 if (default_cpu_version != CPU_VERSION_LEGACY) { 5036 info->alias_of = x86_cpu_class_get_alias_of(cc); 5037 } 5038 5039 QAPI_LIST_PREPEND(*cpu_list, info); 5040 } 5041 5042 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) 5043 { 5044 CpuDefinitionInfoList *cpu_list = NULL; 5045 GSList *list = get_sorted_cpu_model_list(); 5046 g_slist_foreach(list, x86_cpu_definition_entry, &cpu_list); 5047 g_slist_free(list); 5048 return cpu_list; 5049 } 5050 5051 #endif /* !CONFIG_USER_ONLY */ 5052 5053 uint64_t x86_cpu_get_supported_feature_word(FeatureWord w, 5054 bool migratable_only) 5055 { 5056 FeatureWordInfo *wi = &feature_word_info[w]; 5057 uint64_t r = 0; 5058 5059 if (kvm_enabled()) { 5060 switch (wi->type) { 5061 case CPUID_FEATURE_WORD: 5062 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid.eax, 5063 wi->cpuid.ecx, 5064 wi->cpuid.reg); 5065 break; 5066 case MSR_FEATURE_WORD: 5067 r = kvm_arch_get_supported_msr_feature(kvm_state, 5068 wi->msr.index); 5069 break; 5070 } 5071 } else if (hvf_enabled()) { 5072 if (wi->type != CPUID_FEATURE_WORD) { 5073 return 0; 5074 } 5075 r = hvf_get_supported_cpuid(wi->cpuid.eax, 5076 wi->cpuid.ecx, 5077 wi->cpuid.reg); 5078 } else if (tcg_enabled()) { 5079 r = wi->tcg_features; 5080 } else { 5081 return ~0; 5082 } 5083 #ifndef TARGET_X86_64 5084 if (w == FEAT_8000_0001_EDX) { 5085 r &= ~CPUID_EXT2_LM; 5086 } 5087 #endif 5088 if (migratable_only) { 5089 r &= x86_cpu_get_migratable_flags(w); 5090 } 5091 return r; 5092 } 5093 5094 static void x86_cpu_get_supported_cpuid(uint32_t func, uint32_t index, 5095 uint32_t *eax, uint32_t *ebx, 5096 uint32_t *ecx, uint32_t *edx) 5097 { 5098 if (kvm_enabled()) { 5099 *eax = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EAX); 5100 *ebx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EBX); 5101 *ecx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_ECX); 5102 *edx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EDX); 5103 } else if (hvf_enabled()) { 5104 *eax = hvf_get_supported_cpuid(func, index, R_EAX); 5105 *ebx = hvf_get_supported_cpuid(func, index, R_EBX); 5106 *ecx = hvf_get_supported_cpuid(func, index, R_ECX); 5107 *edx = hvf_get_supported_cpuid(func, index, R_EDX); 5108 } else { 5109 *eax = 0; 5110 *ebx = 0; 5111 *ecx = 0; 5112 *edx = 0; 5113 } 5114 } 5115 5116 static void x86_cpu_get_cache_cpuid(uint32_t func, uint32_t index, 5117 uint32_t *eax, uint32_t *ebx, 5118 uint32_t *ecx, uint32_t *edx) 5119 { 5120 uint32_t level, unused; 5121 5122 /* Only return valid host leaves. */ 5123 switch (func) { 5124 case 2: 5125 case 4: 5126 host_cpuid(0, 0, &level, &unused, &unused, &unused); 5127 break; 5128 case 0x80000005: 5129 case 0x80000006: 5130 case 0x8000001d: 5131 host_cpuid(0x80000000, 0, &level, &unused, &unused, &unused); 5132 break; 5133 default: 5134 return; 5135 } 5136 5137 if (func > level) { 5138 *eax = 0; 5139 *ebx = 0; 5140 *ecx = 0; 5141 *edx = 0; 5142 } else { 5143 host_cpuid(func, index, eax, ebx, ecx, edx); 5144 } 5145 } 5146 5147 /* 5148 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 5149 */ 5150 void x86_cpu_apply_props(X86CPU *cpu, PropValue *props) 5151 { 5152 PropValue *pv; 5153 for (pv = props; pv->prop; pv++) { 5154 if (!pv->value) { 5155 continue; 5156 } 5157 object_property_parse(OBJECT(cpu), pv->prop, pv->value, 5158 &error_abort); 5159 } 5160 } 5161 5162 /* 5163 * Apply properties for the CPU model version specified in model. 5164 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 5165 */ 5166 5167 static void x86_cpu_apply_version_props(X86CPU *cpu, X86CPUModel *model) 5168 { 5169 const X86CPUVersionDefinition *vdef; 5170 X86CPUVersion version = x86_cpu_model_resolve_version(model); 5171 5172 if (version == CPU_VERSION_LEGACY) { 5173 return; 5174 } 5175 5176 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) { 5177 PropValue *p; 5178 5179 for (p = vdef->props; p && p->prop; p++) { 5180 object_property_parse(OBJECT(cpu), p->prop, p->value, 5181 &error_abort); 5182 } 5183 5184 if (vdef->version == version) { 5185 break; 5186 } 5187 } 5188 5189 /* 5190 * If we reached the end of the list, version number was invalid 5191 */ 5192 assert(vdef->version == version); 5193 } 5194 5195 /* 5196 * Load data from X86CPUDefinition into a X86CPU object. 5197 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 5198 */ 5199 static void x86_cpu_load_model(X86CPU *cpu, X86CPUModel *model) 5200 { 5201 const X86CPUDefinition *def = model->cpudef; 5202 CPUX86State *env = &cpu->env; 5203 FeatureWord w; 5204 5205 /*NOTE: any property set by this function should be returned by 5206 * x86_cpu_static_props(), so static expansion of 5207 * query-cpu-model-expansion is always complete. 5208 */ 5209 5210 /* CPU models only set _minimum_ values for level/xlevel: */ 5211 object_property_set_uint(OBJECT(cpu), "min-level", def->level, 5212 &error_abort); 5213 object_property_set_uint(OBJECT(cpu), "min-xlevel", def->xlevel, 5214 &error_abort); 5215 5216 object_property_set_int(OBJECT(cpu), "family", def->family, &error_abort); 5217 object_property_set_int(OBJECT(cpu), "model", def->model, &error_abort); 5218 object_property_set_int(OBJECT(cpu), "stepping", def->stepping, 5219 &error_abort); 5220 object_property_set_str(OBJECT(cpu), "model-id", def->model_id, 5221 &error_abort); 5222 for (w = 0; w < FEATURE_WORDS; w++) { 5223 env->features[w] = def->features[w]; 5224 } 5225 5226 /* legacy-cache defaults to 'off' if CPU model provides cache info */ 5227 cpu->legacy_cache = !def->cache_info; 5228 5229 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR; 5230 5231 /* sysenter isn't supported in compatibility mode on AMD, 5232 * syscall isn't supported in compatibility mode on Intel. 5233 * Normally we advertise the actual CPU vendor, but you can 5234 * override this using the 'vendor' property if you want to use 5235 * KVM's sysenter/syscall emulation in compatibility mode and 5236 * when doing cross vendor migration 5237 */ 5238 5239 /* 5240 * vendor property is set here but then overloaded with the 5241 * host cpu vendor for KVM and HVF. 5242 */ 5243 object_property_set_str(OBJECT(cpu), "vendor", def->vendor, &error_abort); 5244 5245 x86_cpu_apply_version_props(cpu, model); 5246 5247 /* 5248 * Properties in versioned CPU model are not user specified features. 5249 * We can simply clear env->user_features here since it will be filled later 5250 * in x86_cpu_expand_features() based on plus_features and minus_features. 5251 */ 5252 memset(&env->user_features, 0, sizeof(env->user_features)); 5253 } 5254 5255 static gchar *x86_gdb_arch_name(CPUState *cs) 5256 { 5257 #ifdef TARGET_X86_64 5258 return g_strdup("i386:x86-64"); 5259 #else 5260 return g_strdup("i386"); 5261 #endif 5262 } 5263 5264 static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data) 5265 { 5266 X86CPUModel *model = data; 5267 X86CPUClass *xcc = X86_CPU_CLASS(oc); 5268 CPUClass *cc = CPU_CLASS(oc); 5269 5270 xcc->model = model; 5271 xcc->migration_safe = true; 5272 cc->deprecation_note = model->cpudef->deprecation_note; 5273 } 5274 5275 static void x86_register_cpu_model_type(const char *name, X86CPUModel *model) 5276 { 5277 g_autofree char *typename = x86_cpu_type_name(name); 5278 TypeInfo ti = { 5279 .name = typename, 5280 .parent = TYPE_X86_CPU, 5281 .class_init = x86_cpu_cpudef_class_init, 5282 .class_data = model, 5283 }; 5284 5285 type_register(&ti); 5286 } 5287 5288 5289 /* 5290 * register builtin_x86_defs; 5291 * "max", "base" and subclasses ("host") are not registered here. 5292 * See x86_cpu_register_types for all model registrations. 5293 */ 5294 static void x86_register_cpudef_types(const X86CPUDefinition *def) 5295 { 5296 X86CPUModel *m; 5297 const X86CPUVersionDefinition *vdef; 5298 5299 /* AMD aliases are handled at runtime based on CPUID vendor, so 5300 * they shouldn't be set on the CPU model table. 5301 */ 5302 assert(!(def->features[FEAT_8000_0001_EDX] & CPUID_EXT2_AMD_ALIASES)); 5303 /* catch mistakes instead of silently truncating model_id when too long */ 5304 assert(def->model_id && strlen(def->model_id) <= 48); 5305 5306 /* Unversioned model: */ 5307 m = g_new0(X86CPUModel, 1); 5308 m->cpudef = def; 5309 m->version = CPU_VERSION_AUTO; 5310 m->is_alias = true; 5311 x86_register_cpu_model_type(def->name, m); 5312 5313 /* Versioned models: */ 5314 5315 for (vdef = x86_cpu_def_get_versions(def); vdef->version; vdef++) { 5316 X86CPUModel *m = g_new0(X86CPUModel, 1); 5317 g_autofree char *name = 5318 x86_cpu_versioned_model_name(def, vdef->version); 5319 m->cpudef = def; 5320 m->version = vdef->version; 5321 m->note = vdef->note; 5322 x86_register_cpu_model_type(name, m); 5323 5324 if (vdef->alias) { 5325 X86CPUModel *am = g_new0(X86CPUModel, 1); 5326 am->cpudef = def; 5327 am->version = vdef->version; 5328 am->is_alias = true; 5329 x86_register_cpu_model_type(vdef->alias, am); 5330 } 5331 } 5332 5333 } 5334 5335 uint32_t cpu_x86_virtual_addr_width(CPUX86State *env) 5336 { 5337 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57) { 5338 return 57; /* 57 bits virtual */ 5339 } else { 5340 return 48; /* 48 bits virtual */ 5341 } 5342 } 5343 5344 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, 5345 uint32_t *eax, uint32_t *ebx, 5346 uint32_t *ecx, uint32_t *edx) 5347 { 5348 X86CPU *cpu = env_archcpu(env); 5349 CPUState *cs = env_cpu(env); 5350 uint32_t die_offset; 5351 uint32_t limit; 5352 uint32_t signature[3]; 5353 X86CPUTopoInfo topo_info; 5354 5355 topo_info.dies_per_pkg = env->nr_dies; 5356 topo_info.cores_per_die = cs->nr_cores; 5357 topo_info.threads_per_core = cs->nr_threads; 5358 5359 /* Calculate & apply limits for different index ranges */ 5360 if (index >= 0xC0000000) { 5361 limit = env->cpuid_xlevel2; 5362 } else if (index >= 0x80000000) { 5363 limit = env->cpuid_xlevel; 5364 } else if (index >= 0x40000000) { 5365 limit = 0x40000001; 5366 } else { 5367 limit = env->cpuid_level; 5368 } 5369 5370 if (index > limit) { 5371 /* Intel documentation states that invalid EAX input will 5372 * return the same information as EAX=cpuid_level 5373 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID) 5374 */ 5375 index = env->cpuid_level; 5376 } 5377 5378 switch(index) { 5379 case 0: 5380 *eax = env->cpuid_level; 5381 *ebx = env->cpuid_vendor1; 5382 *edx = env->cpuid_vendor2; 5383 *ecx = env->cpuid_vendor3; 5384 break; 5385 case 1: 5386 *eax = env->cpuid_version; 5387 *ebx = (cpu->apic_id << 24) | 5388 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */ 5389 *ecx = env->features[FEAT_1_ECX]; 5390 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) { 5391 *ecx |= CPUID_EXT_OSXSAVE; 5392 } 5393 *edx = env->features[FEAT_1_EDX]; 5394 if (cs->nr_cores * cs->nr_threads > 1) { 5395 *ebx |= (cs->nr_cores * cs->nr_threads) << 16; 5396 *edx |= CPUID_HT; 5397 } 5398 if (!cpu->enable_pmu) { 5399 *ecx &= ~CPUID_EXT_PDCM; 5400 } 5401 break; 5402 case 2: 5403 /* cache info: needed for Pentium Pro compatibility */ 5404 if (cpu->cache_info_passthrough) { 5405 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 5406 break; 5407 } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { 5408 *eax = *ebx = *ecx = *edx = 0; 5409 break; 5410 } 5411 *eax = 1; /* Number of CPUID[EAX=2] calls required */ 5412 *ebx = 0; 5413 if (!cpu->enable_l3_cache) { 5414 *ecx = 0; 5415 } else { 5416 *ecx = cpuid2_cache_descriptor(env->cache_info_cpuid2.l3_cache); 5417 } 5418 *edx = (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1d_cache) << 16) | 5419 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1i_cache) << 8) | 5420 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l2_cache)); 5421 break; 5422 case 4: 5423 /* cache info: needed for Core compatibility */ 5424 if (cpu->cache_info_passthrough) { 5425 x86_cpu_get_cache_cpuid(index, count, eax, ebx, ecx, edx); 5426 /* 5427 * QEMU has its own number of cores/logical cpus, 5428 * set 24..14, 31..26 bit to configured values 5429 */ 5430 if (*eax & 31) { 5431 int host_vcpus_per_cache = 1 + ((*eax & 0x3FFC000) >> 14); 5432 int vcpus_per_socket = env->nr_dies * cs->nr_cores * 5433 cs->nr_threads; 5434 if (cs->nr_cores > 1) { 5435 *eax &= ~0xFC000000; 5436 *eax |= (pow2ceil(cs->nr_cores) - 1) << 26; 5437 } 5438 if (host_vcpus_per_cache > vcpus_per_socket) { 5439 *eax &= ~0x3FFC000; 5440 *eax |= (pow2ceil(vcpus_per_socket) - 1) << 14; 5441 } 5442 } 5443 } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { 5444 *eax = *ebx = *ecx = *edx = 0; 5445 } else { 5446 *eax = 0; 5447 switch (count) { 5448 case 0: /* L1 dcache info */ 5449 encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache, 5450 1, cs->nr_cores, 5451 eax, ebx, ecx, edx); 5452 break; 5453 case 1: /* L1 icache info */ 5454 encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache, 5455 1, cs->nr_cores, 5456 eax, ebx, ecx, edx); 5457 break; 5458 case 2: /* L2 cache info */ 5459 encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache, 5460 cs->nr_threads, cs->nr_cores, 5461 eax, ebx, ecx, edx); 5462 break; 5463 case 3: /* L3 cache info */ 5464 die_offset = apicid_die_offset(&topo_info); 5465 if (cpu->enable_l3_cache) { 5466 encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache, 5467 (1 << die_offset), cs->nr_cores, 5468 eax, ebx, ecx, edx); 5469 break; 5470 } 5471 /* fall through */ 5472 default: /* end of info */ 5473 *eax = *ebx = *ecx = *edx = 0; 5474 break; 5475 } 5476 } 5477 break; 5478 case 5: 5479 /* MONITOR/MWAIT Leaf */ 5480 *eax = cpu->mwait.eax; /* Smallest monitor-line size in bytes */ 5481 *ebx = cpu->mwait.ebx; /* Largest monitor-line size in bytes */ 5482 *ecx = cpu->mwait.ecx; /* flags */ 5483 *edx = cpu->mwait.edx; /* mwait substates */ 5484 break; 5485 case 6: 5486 /* Thermal and Power Leaf */ 5487 *eax = env->features[FEAT_6_EAX]; 5488 *ebx = 0; 5489 *ecx = 0; 5490 *edx = 0; 5491 break; 5492 case 7: 5493 /* Structured Extended Feature Flags Enumeration Leaf */ 5494 if (count == 0) { 5495 /* Maximum ECX value for sub-leaves */ 5496 *eax = env->cpuid_level_func7; 5497 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */ 5498 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */ 5499 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) { 5500 *ecx |= CPUID_7_0_ECX_OSPKE; 5501 } 5502 *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */ 5503 5504 /* 5505 * SGX cannot be emulated in software. If hardware does not 5506 * support enabling SGX and/or SGX flexible launch control, 5507 * then we need to update the VM's CPUID values accordingly. 5508 */ 5509 if ((*ebx & CPUID_7_0_EBX_SGX) && 5510 (!kvm_enabled() || 5511 !(kvm_arch_get_supported_cpuid(cs->kvm_state, 0x7, 0, R_EBX) & 5512 CPUID_7_0_EBX_SGX))) { 5513 *ebx &= ~CPUID_7_0_EBX_SGX; 5514 } 5515 5516 if ((*ecx & CPUID_7_0_ECX_SGX_LC) && 5517 (!(*ebx & CPUID_7_0_EBX_SGX) || !kvm_enabled() || 5518 !(kvm_arch_get_supported_cpuid(cs->kvm_state, 0x7, 0, R_ECX) & 5519 CPUID_7_0_ECX_SGX_LC))) { 5520 *ecx &= ~CPUID_7_0_ECX_SGX_LC; 5521 } 5522 } else if (count == 1) { 5523 *eax = env->features[FEAT_7_1_EAX]; 5524 *ebx = 0; 5525 *ecx = 0; 5526 *edx = 0; 5527 } else { 5528 *eax = 0; 5529 *ebx = 0; 5530 *ecx = 0; 5531 *edx = 0; 5532 } 5533 break; 5534 case 9: 5535 /* Direct Cache Access Information Leaf */ 5536 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */ 5537 *ebx = 0; 5538 *ecx = 0; 5539 *edx = 0; 5540 break; 5541 case 0xA: 5542 /* Architectural Performance Monitoring Leaf */ 5543 if (accel_uses_host_cpuid() && cpu->enable_pmu) { 5544 x86_cpu_get_supported_cpuid(0xA, count, eax, ebx, ecx, edx); 5545 } else { 5546 *eax = 0; 5547 *ebx = 0; 5548 *ecx = 0; 5549 *edx = 0; 5550 } 5551 break; 5552 case 0xB: 5553 /* Extended Topology Enumeration Leaf */ 5554 if (!cpu->enable_cpuid_0xb) { 5555 *eax = *ebx = *ecx = *edx = 0; 5556 break; 5557 } 5558 5559 *ecx = count & 0xff; 5560 *edx = cpu->apic_id; 5561 5562 switch (count) { 5563 case 0: 5564 *eax = apicid_core_offset(&topo_info); 5565 *ebx = cs->nr_threads; 5566 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT; 5567 break; 5568 case 1: 5569 *eax = apicid_pkg_offset(&topo_info); 5570 *ebx = cs->nr_cores * cs->nr_threads; 5571 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE; 5572 break; 5573 default: 5574 *eax = 0; 5575 *ebx = 0; 5576 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID; 5577 } 5578 5579 assert(!(*eax & ~0x1f)); 5580 *ebx &= 0xffff; /* The count doesn't need to be reliable. */ 5581 break; 5582 case 0x1C: 5583 if (accel_uses_host_cpuid() && cpu->enable_pmu && 5584 (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) { 5585 x86_cpu_get_supported_cpuid(0x1C, 0, eax, ebx, ecx, edx); 5586 *edx = 0; 5587 } 5588 break; 5589 case 0x1F: 5590 /* V2 Extended Topology Enumeration Leaf */ 5591 if (env->nr_dies < 2) { 5592 *eax = *ebx = *ecx = *edx = 0; 5593 break; 5594 } 5595 5596 *ecx = count & 0xff; 5597 *edx = cpu->apic_id; 5598 switch (count) { 5599 case 0: 5600 *eax = apicid_core_offset(&topo_info); 5601 *ebx = cs->nr_threads; 5602 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT; 5603 break; 5604 case 1: 5605 *eax = apicid_die_offset(&topo_info); 5606 *ebx = cs->nr_cores * cs->nr_threads; 5607 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE; 5608 break; 5609 case 2: 5610 *eax = apicid_pkg_offset(&topo_info); 5611 *ebx = env->nr_dies * cs->nr_cores * cs->nr_threads; 5612 *ecx |= CPUID_TOPOLOGY_LEVEL_DIE; 5613 break; 5614 default: 5615 *eax = 0; 5616 *ebx = 0; 5617 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID; 5618 } 5619 assert(!(*eax & ~0x1f)); 5620 *ebx &= 0xffff; /* The count doesn't need to be reliable. */ 5621 break; 5622 case 0xD: { 5623 /* Processor Extended State */ 5624 *eax = 0; 5625 *ebx = 0; 5626 *ecx = 0; 5627 *edx = 0; 5628 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { 5629 break; 5630 } 5631 5632 if (count == 0) { 5633 *ecx = xsave_area_size(x86_cpu_xsave_xcr0_components(cpu), false); 5634 *eax = env->features[FEAT_XSAVE_XCR0_LO]; 5635 *edx = env->features[FEAT_XSAVE_XCR0_HI]; 5636 /* 5637 * The initial value of xcr0 and ebx == 0, On host without kvm 5638 * commit 412a3c41(e.g., CentOS 6), the ebx's value always == 0 5639 * even through guest update xcr0, this will crash some legacy guest 5640 * (e.g., CentOS 6), So set ebx == ecx to workaroud it. 5641 */ 5642 *ebx = kvm_enabled() ? *ecx : xsave_area_size(env->xcr0, false); 5643 } else if (count == 1) { 5644 uint64_t xstate = x86_cpu_xsave_xcr0_components(cpu) | 5645 x86_cpu_xsave_xss_components(cpu); 5646 5647 *eax = env->features[FEAT_XSAVE]; 5648 *ebx = xsave_area_size(xstate, true); 5649 *ecx = env->features[FEAT_XSAVE_XSS_LO]; 5650 *edx = env->features[FEAT_XSAVE_XSS_HI]; 5651 if (kvm_enabled() && cpu->enable_pmu && 5652 (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR) && 5653 (*eax & CPUID_XSAVE_XSAVES)) { 5654 *ecx |= XSTATE_ARCH_LBR_MASK; 5655 } else { 5656 *ecx &= ~XSTATE_ARCH_LBR_MASK; 5657 } 5658 } else if (count == 0xf && 5659 accel_uses_host_cpuid() && cpu->enable_pmu && 5660 (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) { 5661 x86_cpu_get_supported_cpuid(0xD, count, eax, ebx, ecx, edx); 5662 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) { 5663 const ExtSaveArea *esa = &x86_ext_save_areas[count]; 5664 5665 if (x86_cpu_xsave_xcr0_components(cpu) & (1ULL << count)) { 5666 *eax = esa->size; 5667 *ebx = esa->offset; 5668 *ecx = esa->ecx & 5669 (ESA_FEATURE_ALIGN64_MASK | ESA_FEATURE_XFD_MASK); 5670 } else if (x86_cpu_xsave_xss_components(cpu) & (1ULL << count)) { 5671 *eax = esa->size; 5672 *ebx = 0; 5673 *ecx = 1; 5674 } 5675 } 5676 break; 5677 } 5678 case 0x12: 5679 #ifndef CONFIG_USER_ONLY 5680 if (!kvm_enabled() || 5681 !(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX)) { 5682 *eax = *ebx = *ecx = *edx = 0; 5683 break; 5684 } 5685 5686 /* 5687 * SGX sub-leafs CPUID.0x12.{0x2..N} enumerate EPC sections. Retrieve 5688 * the EPC properties, e.g. confidentiality and integrity, from the 5689 * host's first EPC section, i.e. assume there is one EPC section or 5690 * that all EPC sections have the same security properties. 5691 */ 5692 if (count > 1) { 5693 uint64_t epc_addr, epc_size; 5694 5695 if (sgx_epc_get_section(count - 2, &epc_addr, &epc_size)) { 5696 *eax = *ebx = *ecx = *edx = 0; 5697 break; 5698 } 5699 host_cpuid(index, 2, eax, ebx, ecx, edx); 5700 *eax = (uint32_t)(epc_addr & 0xfffff000) | 0x1; 5701 *ebx = (uint32_t)(epc_addr >> 32); 5702 *ecx = (uint32_t)(epc_size & 0xfffff000) | (*ecx & 0xf); 5703 *edx = (uint32_t)(epc_size >> 32); 5704 break; 5705 } 5706 5707 /* 5708 * SGX sub-leafs CPUID.0x12.{0x0,0x1} are heavily dependent on hardware 5709 * and KVM, i.e. QEMU cannot emulate features to override what KVM 5710 * supports. Features can be further restricted by userspace, but not 5711 * made more permissive. 5712 */ 5713 x86_cpu_get_supported_cpuid(0x12, count, eax, ebx, ecx, edx); 5714 5715 if (count == 0) { 5716 *eax &= env->features[FEAT_SGX_12_0_EAX]; 5717 *ebx &= env->features[FEAT_SGX_12_0_EBX]; 5718 } else { 5719 *eax &= env->features[FEAT_SGX_12_1_EAX]; 5720 *ebx &= 0; /* ebx reserve */ 5721 *ecx &= env->features[FEAT_XSAVE_XSS_LO]; 5722 *edx &= env->features[FEAT_XSAVE_XSS_HI]; 5723 5724 /* FP and SSE are always allowed regardless of XSAVE/XCR0. */ 5725 *ecx |= XSTATE_FP_MASK | XSTATE_SSE_MASK; 5726 5727 /* Access to PROVISIONKEY requires additional credentials. */ 5728 if ((*eax & (1U << 4)) && 5729 !kvm_enable_sgx_provisioning(cs->kvm_state)) { 5730 *eax &= ~(1U << 4); 5731 } 5732 } 5733 #endif 5734 break; 5735 case 0x14: { 5736 /* Intel Processor Trace Enumeration */ 5737 *eax = 0; 5738 *ebx = 0; 5739 *ecx = 0; 5740 *edx = 0; 5741 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) || 5742 !kvm_enabled()) { 5743 break; 5744 } 5745 5746 if (count == 0) { 5747 *eax = INTEL_PT_MAX_SUBLEAF; 5748 *ebx = INTEL_PT_MINIMAL_EBX; 5749 *ecx = INTEL_PT_MINIMAL_ECX; 5750 if (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP) { 5751 *ecx |= CPUID_14_0_ECX_LIP; 5752 } 5753 } else if (count == 1) { 5754 *eax = INTEL_PT_MTC_BITMAP | INTEL_PT_ADDR_RANGES_NUM; 5755 *ebx = INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP; 5756 } 5757 break; 5758 } 5759 case 0x1D: { 5760 /* AMX TILE, for now hardcoded for Sapphire Rapids*/ 5761 *eax = 0; 5762 *ebx = 0; 5763 *ecx = 0; 5764 *edx = 0; 5765 if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) { 5766 break; 5767 } 5768 5769 if (count == 0) { 5770 /* Highest numbered palette subleaf */ 5771 *eax = INTEL_AMX_TILE_MAX_SUBLEAF; 5772 } else if (count == 1) { 5773 *eax = INTEL_AMX_TOTAL_TILE_BYTES | 5774 (INTEL_AMX_BYTES_PER_TILE << 16); 5775 *ebx = INTEL_AMX_BYTES_PER_ROW | (INTEL_AMX_TILE_MAX_NAMES << 16); 5776 *ecx = INTEL_AMX_TILE_MAX_ROWS; 5777 } 5778 break; 5779 } 5780 case 0x1E: { 5781 /* AMX TMUL, for now hardcoded for Sapphire Rapids */ 5782 *eax = 0; 5783 *ebx = 0; 5784 *ecx = 0; 5785 *edx = 0; 5786 if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) { 5787 break; 5788 } 5789 5790 if (count == 0) { 5791 /* Highest numbered palette subleaf */ 5792 *ebx = INTEL_AMX_TMUL_MAX_K | (INTEL_AMX_TMUL_MAX_N << 8); 5793 } 5794 break; 5795 } 5796 case 0x40000000: 5797 /* 5798 * CPUID code in kvm_arch_init_vcpu() ignores stuff 5799 * set here, but we restrict to TCG none the less. 5800 */ 5801 if (tcg_enabled() && cpu->expose_tcg) { 5802 memcpy(signature, "TCGTCGTCGTCG", 12); 5803 *eax = 0x40000001; 5804 *ebx = signature[0]; 5805 *ecx = signature[1]; 5806 *edx = signature[2]; 5807 } else { 5808 *eax = 0; 5809 *ebx = 0; 5810 *ecx = 0; 5811 *edx = 0; 5812 } 5813 break; 5814 case 0x40000001: 5815 *eax = 0; 5816 *ebx = 0; 5817 *ecx = 0; 5818 *edx = 0; 5819 break; 5820 case 0x80000000: 5821 *eax = env->cpuid_xlevel; 5822 *ebx = env->cpuid_vendor1; 5823 *edx = env->cpuid_vendor2; 5824 *ecx = env->cpuid_vendor3; 5825 break; 5826 case 0x80000001: 5827 *eax = env->cpuid_version; 5828 *ebx = 0; 5829 *ecx = env->features[FEAT_8000_0001_ECX]; 5830 *edx = env->features[FEAT_8000_0001_EDX]; 5831 5832 /* The Linux kernel checks for the CMPLegacy bit and 5833 * discards multiple thread information if it is set. 5834 * So don't set it here for Intel to make Linux guests happy. 5835 */ 5836 if (cs->nr_cores * cs->nr_threads > 1) { 5837 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 || 5838 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 || 5839 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) { 5840 *ecx |= 1 << 1; /* CmpLegacy bit */ 5841 } 5842 } 5843 break; 5844 case 0x80000002: 5845 case 0x80000003: 5846 case 0x80000004: 5847 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0]; 5848 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1]; 5849 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2]; 5850 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3]; 5851 break; 5852 case 0x80000005: 5853 /* cache info (L1 cache) */ 5854 if (cpu->cache_info_passthrough) { 5855 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 5856 break; 5857 } 5858 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | 5859 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES); 5860 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | 5861 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES); 5862 *ecx = encode_cache_cpuid80000005(env->cache_info_amd.l1d_cache); 5863 *edx = encode_cache_cpuid80000005(env->cache_info_amd.l1i_cache); 5864 break; 5865 case 0x80000006: 5866 /* cache info (L2 cache) */ 5867 if (cpu->cache_info_passthrough) { 5868 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 5869 break; 5870 } 5871 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | 5872 (L2_DTLB_2M_ENTRIES << 16) | 5873 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | 5874 (L2_ITLB_2M_ENTRIES); 5875 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | 5876 (L2_DTLB_4K_ENTRIES << 16) | 5877 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | 5878 (L2_ITLB_4K_ENTRIES); 5879 encode_cache_cpuid80000006(env->cache_info_amd.l2_cache, 5880 cpu->enable_l3_cache ? 5881 env->cache_info_amd.l3_cache : NULL, 5882 ecx, edx); 5883 break; 5884 case 0x80000007: 5885 *eax = 0; 5886 *ebx = 0; 5887 *ecx = 0; 5888 *edx = env->features[FEAT_8000_0007_EDX]; 5889 break; 5890 case 0x80000008: 5891 /* virtual & phys address size in low 2 bytes. */ 5892 *eax = cpu->phys_bits; 5893 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 5894 /* 64 bit processor */ 5895 *eax |= (cpu_x86_virtual_addr_width(env) << 8); 5896 } 5897 *ebx = env->features[FEAT_8000_0008_EBX]; 5898 if (cs->nr_cores * cs->nr_threads > 1) { 5899 /* 5900 * Bits 15:12 is "The number of bits in the initial 5901 * Core::X86::Apic::ApicId[ApicId] value that indicate 5902 * thread ID within a package". 5903 * Bits 7:0 is "The number of threads in the package is NC+1" 5904 */ 5905 *ecx = (apicid_pkg_offset(&topo_info) << 12) | 5906 ((cs->nr_cores * cs->nr_threads) - 1); 5907 } else { 5908 *ecx = 0; 5909 } 5910 *edx = 0; 5911 break; 5912 case 0x8000000A: 5913 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { 5914 *eax = 0x00000001; /* SVM Revision */ 5915 *ebx = 0x00000010; /* nr of ASIDs */ 5916 *ecx = 0; 5917 *edx = env->features[FEAT_SVM]; /* optional features */ 5918 } else { 5919 *eax = 0; 5920 *ebx = 0; 5921 *ecx = 0; 5922 *edx = 0; 5923 } 5924 break; 5925 case 0x8000001D: 5926 *eax = 0; 5927 if (cpu->cache_info_passthrough) { 5928 x86_cpu_get_cache_cpuid(index, count, eax, ebx, ecx, edx); 5929 break; 5930 } 5931 switch (count) { 5932 case 0: /* L1 dcache info */ 5933 encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache, 5934 &topo_info, eax, ebx, ecx, edx); 5935 break; 5936 case 1: /* L1 icache info */ 5937 encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache, 5938 &topo_info, eax, ebx, ecx, edx); 5939 break; 5940 case 2: /* L2 cache info */ 5941 encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache, 5942 &topo_info, eax, ebx, ecx, edx); 5943 break; 5944 case 3: /* L3 cache info */ 5945 encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache, 5946 &topo_info, eax, ebx, ecx, edx); 5947 break; 5948 default: /* end of info */ 5949 *eax = *ebx = *ecx = *edx = 0; 5950 break; 5951 } 5952 break; 5953 case 0x8000001E: 5954 if (cpu->core_id <= 255) { 5955 encode_topo_cpuid8000001e(cpu, &topo_info, eax, ebx, ecx, edx); 5956 } else { 5957 *eax = 0; 5958 *ebx = 0; 5959 *ecx = 0; 5960 *edx = 0; 5961 } 5962 break; 5963 case 0xC0000000: 5964 *eax = env->cpuid_xlevel2; 5965 *ebx = 0; 5966 *ecx = 0; 5967 *edx = 0; 5968 break; 5969 case 0xC0000001: 5970 /* Support for VIA CPU's CPUID instruction */ 5971 *eax = env->cpuid_version; 5972 *ebx = 0; 5973 *ecx = 0; 5974 *edx = env->features[FEAT_C000_0001_EDX]; 5975 break; 5976 case 0xC0000002: 5977 case 0xC0000003: 5978 case 0xC0000004: 5979 /* Reserved for the future, and now filled with zero */ 5980 *eax = 0; 5981 *ebx = 0; 5982 *ecx = 0; 5983 *edx = 0; 5984 break; 5985 case 0x8000001F: 5986 *eax = *ebx = *ecx = *edx = 0; 5987 if (sev_enabled()) { 5988 *eax = 0x2; 5989 *eax |= sev_es_enabled() ? 0x8 : 0; 5990 *ebx = sev_get_cbit_position(); 5991 *ebx |= sev_get_reduced_phys_bits() << 6; 5992 } 5993 break; 5994 default: 5995 /* reserved values: zero */ 5996 *eax = 0; 5997 *ebx = 0; 5998 *ecx = 0; 5999 *edx = 0; 6000 break; 6001 } 6002 } 6003 6004 static void x86_cpu_set_sgxlepubkeyhash(CPUX86State *env) 6005 { 6006 #ifndef CONFIG_USER_ONLY 6007 /* Those default values are defined in Skylake HW */ 6008 env->msr_ia32_sgxlepubkeyhash[0] = 0xa6053e051270b7acULL; 6009 env->msr_ia32_sgxlepubkeyhash[1] = 0x6cfbe8ba8b3b413dULL; 6010 env->msr_ia32_sgxlepubkeyhash[2] = 0xc4916d99f2b3735dULL; 6011 env->msr_ia32_sgxlepubkeyhash[3] = 0xd4f8c05909f9bb3bULL; 6012 #endif 6013 } 6014 6015 static void x86_cpu_reset_hold(Object *obj) 6016 { 6017 CPUState *s = CPU(obj); 6018 X86CPU *cpu = X86_CPU(s); 6019 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu); 6020 CPUX86State *env = &cpu->env; 6021 target_ulong cr4; 6022 uint64_t xcr0; 6023 int i; 6024 6025 if (xcc->parent_phases.hold) { 6026 xcc->parent_phases.hold(obj); 6027 } 6028 6029 memset(env, 0, offsetof(CPUX86State, end_reset_fields)); 6030 6031 env->old_exception = -1; 6032 6033 /* init to reset state */ 6034 env->int_ctl = 0; 6035 env->hflags2 |= HF2_GIF_MASK; 6036 env->hflags2 |= HF2_VGIF_MASK; 6037 env->hflags &= ~HF_GUEST_MASK; 6038 6039 cpu_x86_update_cr0(env, 0x60000010); 6040 env->a20_mask = ~0x0; 6041 env->smbase = 0x30000; 6042 env->msr_smi_count = 0; 6043 6044 env->idt.limit = 0xffff; 6045 env->gdt.limit = 0xffff; 6046 env->ldt.limit = 0xffff; 6047 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT); 6048 env->tr.limit = 0xffff; 6049 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT); 6050 6051 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff, 6052 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK | 6053 DESC_R_MASK | DESC_A_MASK); 6054 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff, 6055 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 6056 DESC_A_MASK); 6057 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff, 6058 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 6059 DESC_A_MASK); 6060 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff, 6061 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 6062 DESC_A_MASK); 6063 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff, 6064 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 6065 DESC_A_MASK); 6066 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff, 6067 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 6068 DESC_A_MASK); 6069 6070 env->eip = 0xfff0; 6071 env->regs[R_EDX] = env->cpuid_version; 6072 6073 env->eflags = 0x2; 6074 6075 /* FPU init */ 6076 for (i = 0; i < 8; i++) { 6077 env->fptags[i] = 1; 6078 } 6079 cpu_set_fpuc(env, 0x37f); 6080 6081 env->mxcsr = 0x1f80; 6082 /* All units are in INIT state. */ 6083 env->xstate_bv = 0; 6084 6085 env->pat = 0x0007040600070406ULL; 6086 6087 if (kvm_enabled()) { 6088 /* 6089 * KVM handles TSC = 0 specially and thinks we are hot-plugging 6090 * a new CPU, use 1 instead to force a reset. 6091 */ 6092 if (env->tsc != 0) { 6093 env->tsc = 1; 6094 } 6095 } else { 6096 env->tsc = 0; 6097 } 6098 6099 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT; 6100 if (env->features[FEAT_1_ECX] & CPUID_EXT_MONITOR) { 6101 env->msr_ia32_misc_enable |= MSR_IA32_MISC_ENABLE_MWAIT; 6102 } 6103 6104 memset(env->dr, 0, sizeof(env->dr)); 6105 env->dr[6] = DR6_FIXED_1; 6106 env->dr[7] = DR7_FIXED_1; 6107 cpu_breakpoint_remove_all(s, BP_CPU); 6108 cpu_watchpoint_remove_all(s, BP_CPU); 6109 6110 cr4 = 0; 6111 xcr0 = XSTATE_FP_MASK; 6112 6113 #ifdef CONFIG_USER_ONLY 6114 /* Enable all the features for user-mode. */ 6115 if (env->features[FEAT_1_EDX] & CPUID_SSE) { 6116 xcr0 |= XSTATE_SSE_MASK; 6117 } 6118 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 6119 const ExtSaveArea *esa = &x86_ext_save_areas[i]; 6120 if (!((1 << i) & CPUID_XSTATE_XCR0_MASK)) { 6121 continue; 6122 } 6123 if (env->features[esa->feature] & esa->bits) { 6124 xcr0 |= 1ull << i; 6125 } 6126 } 6127 6128 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) { 6129 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK; 6130 } 6131 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) { 6132 cr4 |= CR4_FSGSBASE_MASK; 6133 } 6134 #endif 6135 6136 env->xcr0 = xcr0; 6137 cpu_x86_update_cr4(env, cr4); 6138 6139 /* 6140 * SDM 11.11.5 requires: 6141 * - IA32_MTRR_DEF_TYPE MSR.E = 0 6142 * - IA32_MTRR_PHYSMASKn.V = 0 6143 * All other bits are undefined. For simplification, zero it all. 6144 */ 6145 env->mtrr_deftype = 0; 6146 memset(env->mtrr_var, 0, sizeof(env->mtrr_var)); 6147 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed)); 6148 6149 env->interrupt_injected = -1; 6150 env->exception_nr = -1; 6151 env->exception_pending = 0; 6152 env->exception_injected = 0; 6153 env->exception_has_payload = false; 6154 env->exception_payload = 0; 6155 env->nmi_injected = false; 6156 env->triple_fault_pending = false; 6157 #if !defined(CONFIG_USER_ONLY) 6158 /* We hard-wire the BSP to the first CPU. */ 6159 apic_designate_bsp(cpu->apic_state, s->cpu_index == 0); 6160 6161 s->halted = !cpu_is_bsp(cpu); 6162 6163 if (kvm_enabled()) { 6164 kvm_arch_reset_vcpu(cpu); 6165 } 6166 6167 x86_cpu_set_sgxlepubkeyhash(env); 6168 6169 env->amd_tsc_scale_msr = MSR_AMD64_TSC_RATIO_DEFAULT; 6170 6171 #endif 6172 } 6173 6174 void x86_cpu_after_reset(X86CPU *cpu) 6175 { 6176 #ifndef CONFIG_USER_ONLY 6177 if (kvm_enabled()) { 6178 kvm_arch_after_reset_vcpu(cpu); 6179 } 6180 6181 if (cpu->apic_state) { 6182 device_cold_reset(cpu->apic_state); 6183 } 6184 #endif 6185 } 6186 6187 static void mce_init(X86CPU *cpu) 6188 { 6189 CPUX86State *cenv = &cpu->env; 6190 unsigned int bank; 6191 6192 if (((cenv->cpuid_version >> 8) & 0xf) >= 6 6193 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) == 6194 (CPUID_MCE | CPUID_MCA)) { 6195 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF | 6196 (cpu->enable_lmce ? MCG_LMCE_P : 0); 6197 cenv->mcg_ctl = ~(uint64_t)0; 6198 for (bank = 0; bank < MCE_BANKS_DEF; bank++) { 6199 cenv->mce_banks[bank * 4] = ~(uint64_t)0; 6200 } 6201 } 6202 } 6203 6204 static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value) 6205 { 6206 if (*min < value) { 6207 *min = value; 6208 } 6209 } 6210 6211 /* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */ 6212 static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w) 6213 { 6214 CPUX86State *env = &cpu->env; 6215 FeatureWordInfo *fi = &feature_word_info[w]; 6216 uint32_t eax = fi->cpuid.eax; 6217 uint32_t region = eax & 0xF0000000; 6218 6219 assert(feature_word_info[w].type == CPUID_FEATURE_WORD); 6220 if (!env->features[w]) { 6221 return; 6222 } 6223 6224 switch (region) { 6225 case 0x00000000: 6226 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax); 6227 break; 6228 case 0x80000000: 6229 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax); 6230 break; 6231 case 0xC0000000: 6232 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax); 6233 break; 6234 } 6235 6236 if (eax == 7) { 6237 x86_cpu_adjust_level(cpu, &env->cpuid_min_level_func7, 6238 fi->cpuid.ecx); 6239 } 6240 } 6241 6242 /* Calculate XSAVE components based on the configured CPU feature flags */ 6243 static void x86_cpu_enable_xsave_components(X86CPU *cpu) 6244 { 6245 CPUX86State *env = &cpu->env; 6246 int i; 6247 uint64_t mask; 6248 static bool request_perm; 6249 6250 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { 6251 env->features[FEAT_XSAVE_XCR0_LO] = 0; 6252 env->features[FEAT_XSAVE_XCR0_HI] = 0; 6253 return; 6254 } 6255 6256 mask = 0; 6257 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 6258 const ExtSaveArea *esa = &x86_ext_save_areas[i]; 6259 if (env->features[esa->feature] & esa->bits) { 6260 mask |= (1ULL << i); 6261 } 6262 } 6263 6264 /* Only request permission for first vcpu */ 6265 if (kvm_enabled() && !request_perm) { 6266 kvm_request_xsave_components(cpu, mask); 6267 request_perm = true; 6268 } 6269 6270 env->features[FEAT_XSAVE_XCR0_LO] = mask & CPUID_XSTATE_XCR0_MASK; 6271 env->features[FEAT_XSAVE_XCR0_HI] = mask >> 32; 6272 env->features[FEAT_XSAVE_XSS_LO] = mask & CPUID_XSTATE_XSS_MASK; 6273 env->features[FEAT_XSAVE_XSS_HI] = mask >> 32; 6274 } 6275 6276 /***** Steps involved on loading and filtering CPUID data 6277 * 6278 * When initializing and realizing a CPU object, the steps 6279 * involved in setting up CPUID data are: 6280 * 6281 * 1) Loading CPU model definition (X86CPUDefinition). This is 6282 * implemented by x86_cpu_load_model() and should be completely 6283 * transparent, as it is done automatically by instance_init. 6284 * No code should need to look at X86CPUDefinition structs 6285 * outside instance_init. 6286 * 6287 * 2) CPU expansion. This is done by realize before CPUID 6288 * filtering, and will make sure host/accelerator data is 6289 * loaded for CPU models that depend on host capabilities 6290 * (e.g. "host"). Done by x86_cpu_expand_features(). 6291 * 6292 * 3) CPUID filtering. This initializes extra data related to 6293 * CPUID, and checks if the host supports all capabilities 6294 * required by the CPU. Runnability of a CPU model is 6295 * determined at this step. Done by x86_cpu_filter_features(). 6296 * 6297 * Some operations don't require all steps to be performed. 6298 * More precisely: 6299 * 6300 * - CPU instance creation (instance_init) will run only CPU 6301 * model loading. CPU expansion can't run at instance_init-time 6302 * because host/accelerator data may be not available yet. 6303 * - CPU realization will perform both CPU model expansion and CPUID 6304 * filtering, and return an error in case one of them fails. 6305 * - query-cpu-definitions needs to run all 3 steps. It needs 6306 * to run CPUID filtering, as the 'unavailable-features' 6307 * field is set based on the filtering results. 6308 * - The query-cpu-model-expansion QMP command only needs to run 6309 * CPU model loading and CPU expansion. It should not filter 6310 * any CPUID data based on host capabilities. 6311 */ 6312 6313 /* Expand CPU configuration data, based on configured features 6314 * and host/accelerator capabilities when appropriate. 6315 */ 6316 void x86_cpu_expand_features(X86CPU *cpu, Error **errp) 6317 { 6318 CPUX86State *env = &cpu->env; 6319 FeatureWord w; 6320 int i; 6321 GList *l; 6322 6323 for (l = plus_features; l; l = l->next) { 6324 const char *prop = l->data; 6325 if (!object_property_set_bool(OBJECT(cpu), prop, true, errp)) { 6326 return; 6327 } 6328 } 6329 6330 for (l = minus_features; l; l = l->next) { 6331 const char *prop = l->data; 6332 if (!object_property_set_bool(OBJECT(cpu), prop, false, errp)) { 6333 return; 6334 } 6335 } 6336 6337 /*TODO: Now cpu->max_features doesn't overwrite features 6338 * set using QOM properties, and we can convert 6339 * plus_features & minus_features to global properties 6340 * inside x86_cpu_parse_featurestr() too. 6341 */ 6342 if (cpu->max_features) { 6343 for (w = 0; w < FEATURE_WORDS; w++) { 6344 /* Override only features that weren't set explicitly 6345 * by the user. 6346 */ 6347 env->features[w] |= 6348 x86_cpu_get_supported_feature_word(w, cpu->migratable) & 6349 ~env->user_features[w] & 6350 ~feature_word_info[w].no_autoenable_flags; 6351 } 6352 } 6353 6354 for (i = 0; i < ARRAY_SIZE(feature_dependencies); i++) { 6355 FeatureDep *d = &feature_dependencies[i]; 6356 if (!(env->features[d->from.index] & d->from.mask)) { 6357 uint64_t unavailable_features = env->features[d->to.index] & d->to.mask; 6358 6359 /* Not an error unless the dependent feature was added explicitly. */ 6360 mark_unavailable_features(cpu, d->to.index, 6361 unavailable_features & env->user_features[d->to.index], 6362 "This feature depends on other features that were not requested"); 6363 6364 env->features[d->to.index] &= ~unavailable_features; 6365 } 6366 } 6367 6368 if (!kvm_enabled() || !cpu->expose_kvm) { 6369 env->features[FEAT_KVM] = 0; 6370 } 6371 6372 x86_cpu_enable_xsave_components(cpu); 6373 6374 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */ 6375 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX); 6376 if (cpu->full_cpuid_auto_level) { 6377 x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX); 6378 x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX); 6379 x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX); 6380 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX); 6381 x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EAX); 6382 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX); 6383 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX); 6384 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX); 6385 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0008_EBX); 6386 x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX); 6387 x86_cpu_adjust_feat_level(cpu, FEAT_SVM); 6388 x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE); 6389 6390 /* Intel Processor Trace requires CPUID[0x14] */ 6391 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT)) { 6392 if (cpu->intel_pt_auto_level) { 6393 x86_cpu_adjust_level(cpu, &cpu->env.cpuid_min_level, 0x14); 6394 } else if (cpu->env.cpuid_min_level < 0x14) { 6395 mark_unavailable_features(cpu, FEAT_7_0_EBX, 6396 CPUID_7_0_EBX_INTEL_PT, 6397 "Intel PT need CPUID leaf 0x14, please set by \"-cpu ...,intel-pt=on,min-level=0x14\""); 6398 } 6399 } 6400 6401 /* 6402 * Intel CPU topology with multi-dies support requires CPUID[0x1F]. 6403 * For AMD Rome/Milan, cpuid level is 0x10, and guest OS should detect 6404 * extended toplogy by leaf 0xB. Only adjust it for Intel CPU, unless 6405 * cpu->vendor_cpuid_only has been unset for compatibility with older 6406 * machine types. 6407 */ 6408 if ((env->nr_dies > 1) && 6409 (IS_INTEL_CPU(env) || !cpu->vendor_cpuid_only)) { 6410 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x1F); 6411 } 6412 6413 /* SVM requires CPUID[0x8000000A] */ 6414 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { 6415 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A); 6416 } 6417 6418 /* SEV requires CPUID[0x8000001F] */ 6419 if (sev_enabled()) { 6420 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F); 6421 } 6422 6423 /* SGX requires CPUID[0x12] for EPC enumeration */ 6424 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX) { 6425 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x12); 6426 } 6427 } 6428 6429 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */ 6430 if (env->cpuid_level_func7 == UINT32_MAX) { 6431 env->cpuid_level_func7 = env->cpuid_min_level_func7; 6432 } 6433 if (env->cpuid_level == UINT32_MAX) { 6434 env->cpuid_level = env->cpuid_min_level; 6435 } 6436 if (env->cpuid_xlevel == UINT32_MAX) { 6437 env->cpuid_xlevel = env->cpuid_min_xlevel; 6438 } 6439 if (env->cpuid_xlevel2 == UINT32_MAX) { 6440 env->cpuid_xlevel2 = env->cpuid_min_xlevel2; 6441 } 6442 6443 if (kvm_enabled()) { 6444 kvm_hyperv_expand_features(cpu, errp); 6445 } 6446 } 6447 6448 /* 6449 * Finishes initialization of CPUID data, filters CPU feature 6450 * words based on host availability of each feature. 6451 * 6452 * Returns: 0 if all flags are supported by the host, non-zero otherwise. 6453 */ 6454 static void x86_cpu_filter_features(X86CPU *cpu, bool verbose) 6455 { 6456 CPUX86State *env = &cpu->env; 6457 FeatureWord w; 6458 const char *prefix = NULL; 6459 6460 if (verbose) { 6461 prefix = accel_uses_host_cpuid() 6462 ? "host doesn't support requested feature" 6463 : "TCG doesn't support requested feature"; 6464 } 6465 6466 for (w = 0; w < FEATURE_WORDS; w++) { 6467 uint64_t host_feat = 6468 x86_cpu_get_supported_feature_word(w, false); 6469 uint64_t requested_features = env->features[w]; 6470 uint64_t unavailable_features = requested_features & ~host_feat; 6471 mark_unavailable_features(cpu, w, unavailable_features, prefix); 6472 } 6473 6474 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) && 6475 kvm_enabled()) { 6476 KVMState *s = CPU(cpu)->kvm_state; 6477 uint32_t eax_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EAX); 6478 uint32_t ebx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EBX); 6479 uint32_t ecx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_ECX); 6480 uint32_t eax_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EAX); 6481 uint32_t ebx_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EBX); 6482 6483 if (!eax_0 || 6484 ((ebx_0 & INTEL_PT_MINIMAL_EBX) != INTEL_PT_MINIMAL_EBX) || 6485 ((ecx_0 & INTEL_PT_MINIMAL_ECX) != INTEL_PT_MINIMAL_ECX) || 6486 ((eax_1 & INTEL_PT_MTC_BITMAP) != INTEL_PT_MTC_BITMAP) || 6487 ((eax_1 & INTEL_PT_ADDR_RANGES_NUM_MASK) < 6488 INTEL_PT_ADDR_RANGES_NUM) || 6489 ((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) != 6490 (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) || 6491 ((ecx_0 & CPUID_14_0_ECX_LIP) != 6492 (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP))) { 6493 /* 6494 * Processor Trace capabilities aren't configurable, so if the 6495 * host can't emulate the capabilities we report on 6496 * cpu_x86_cpuid(), intel-pt can't be enabled on the current host. 6497 */ 6498 mark_unavailable_features(cpu, FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT, prefix); 6499 } 6500 } 6501 } 6502 6503 static void x86_cpu_hyperv_realize(X86CPU *cpu) 6504 { 6505 size_t len; 6506 6507 /* Hyper-V vendor id */ 6508 if (!cpu->hyperv_vendor) { 6509 object_property_set_str(OBJECT(cpu), "hv-vendor-id", "Microsoft Hv", 6510 &error_abort); 6511 } 6512 len = strlen(cpu->hyperv_vendor); 6513 if (len > 12) { 6514 warn_report("hv-vendor-id truncated to 12 characters"); 6515 len = 12; 6516 } 6517 memset(cpu->hyperv_vendor_id, 0, 12); 6518 memcpy(cpu->hyperv_vendor_id, cpu->hyperv_vendor, len); 6519 6520 /* 'Hv#1' interface identification*/ 6521 cpu->hyperv_interface_id[0] = 0x31237648; 6522 cpu->hyperv_interface_id[1] = 0; 6523 cpu->hyperv_interface_id[2] = 0; 6524 cpu->hyperv_interface_id[3] = 0; 6525 6526 /* Hypervisor implementation limits */ 6527 cpu->hyperv_limits[0] = 64; 6528 cpu->hyperv_limits[1] = 0; 6529 cpu->hyperv_limits[2] = 0; 6530 } 6531 6532 static void x86_cpu_realizefn(DeviceState *dev, Error **errp) 6533 { 6534 CPUState *cs = CPU(dev); 6535 X86CPU *cpu = X86_CPU(dev); 6536 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev); 6537 CPUX86State *env = &cpu->env; 6538 Error *local_err = NULL; 6539 static bool ht_warned; 6540 unsigned requested_lbr_fmt; 6541 6542 /* Use pc-relative instructions in system-mode */ 6543 #ifndef CONFIG_USER_ONLY 6544 cs->tcg_cflags |= CF_PCREL; 6545 #endif 6546 6547 if (cpu->apic_id == UNASSIGNED_APIC_ID) { 6548 error_setg(errp, "apic-id property was not initialized properly"); 6549 return; 6550 } 6551 6552 /* 6553 * Process Hyper-V enlightenments. 6554 * Note: this currently has to happen before the expansion of CPU features. 6555 */ 6556 x86_cpu_hyperv_realize(cpu); 6557 6558 x86_cpu_expand_features(cpu, &local_err); 6559 if (local_err) { 6560 goto out; 6561 } 6562 6563 /* 6564 * Override env->features[FEAT_PERF_CAPABILITIES].LBR_FMT 6565 * with user-provided setting. 6566 */ 6567 if (cpu->lbr_fmt != ~PERF_CAP_LBR_FMT) { 6568 if ((cpu->lbr_fmt & PERF_CAP_LBR_FMT) != cpu->lbr_fmt) { 6569 error_setg(errp, "invalid lbr-fmt"); 6570 return; 6571 } 6572 env->features[FEAT_PERF_CAPABILITIES] &= ~PERF_CAP_LBR_FMT; 6573 env->features[FEAT_PERF_CAPABILITIES] |= cpu->lbr_fmt; 6574 } 6575 6576 /* 6577 * vPMU LBR is supported when 1) KVM is enabled 2) Option pmu=on and 6578 * 3)vPMU LBR format matches that of host setting. 6579 */ 6580 requested_lbr_fmt = 6581 env->features[FEAT_PERF_CAPABILITIES] & PERF_CAP_LBR_FMT; 6582 if (requested_lbr_fmt && kvm_enabled()) { 6583 uint64_t host_perf_cap = 6584 x86_cpu_get_supported_feature_word(FEAT_PERF_CAPABILITIES, false); 6585 unsigned host_lbr_fmt = host_perf_cap & PERF_CAP_LBR_FMT; 6586 6587 if (!cpu->enable_pmu) { 6588 error_setg(errp, "vPMU: LBR is unsupported without pmu=on"); 6589 return; 6590 } 6591 if (requested_lbr_fmt != host_lbr_fmt) { 6592 error_setg(errp, "vPMU: the lbr-fmt value (0x%x) does not match " 6593 "the host value (0x%x).", 6594 requested_lbr_fmt, host_lbr_fmt); 6595 return; 6596 } 6597 } 6598 6599 x86_cpu_filter_features(cpu, cpu->check_cpuid || cpu->enforce_cpuid); 6600 6601 if (cpu->enforce_cpuid && x86_cpu_have_filtered_features(cpu)) { 6602 error_setg(&local_err, 6603 accel_uses_host_cpuid() ? 6604 "Host doesn't support requested features" : 6605 "TCG doesn't support requested features"); 6606 goto out; 6607 } 6608 6609 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on 6610 * CPUID[1].EDX. 6611 */ 6612 if (IS_AMD_CPU(env)) { 6613 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES; 6614 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX] 6615 & CPUID_EXT2_AMD_ALIASES); 6616 } 6617 6618 x86_cpu_set_sgxlepubkeyhash(env); 6619 6620 /* 6621 * note: the call to the framework needs to happen after feature expansion, 6622 * but before the checks/modifications to ucode_rev, mwait, phys_bits. 6623 * These may be set by the accel-specific code, 6624 * and the results are subsequently checked / assumed in this function. 6625 */ 6626 cpu_exec_realizefn(cs, &local_err); 6627 if (local_err != NULL) { 6628 error_propagate(errp, local_err); 6629 return; 6630 } 6631 6632 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) { 6633 g_autofree char *name = x86_cpu_class_get_model_name(xcc); 6634 error_setg(&local_err, "CPU model '%s' requires KVM or HVF", name); 6635 goto out; 6636 } 6637 6638 if (cpu->ucode_rev == 0) { 6639 /* 6640 * The default is the same as KVM's. Note that this check 6641 * needs to happen after the evenual setting of ucode_rev in 6642 * accel-specific code in cpu_exec_realizefn. 6643 */ 6644 if (IS_AMD_CPU(env)) { 6645 cpu->ucode_rev = 0x01000065; 6646 } else { 6647 cpu->ucode_rev = 0x100000000ULL; 6648 } 6649 } 6650 6651 /* 6652 * mwait extended info: needed for Core compatibility 6653 * We always wake on interrupt even if host does not have the capability. 6654 * 6655 * requires the accel-specific code in cpu_exec_realizefn to 6656 * have already acquired the CPUID data into cpu->mwait. 6657 */ 6658 cpu->mwait.ecx |= CPUID_MWAIT_EMX | CPUID_MWAIT_IBE; 6659 6660 /* For 64bit systems think about the number of physical bits to present. 6661 * ideally this should be the same as the host; anything other than matching 6662 * the host can cause incorrect guest behaviour. 6663 * QEMU used to pick the magic value of 40 bits that corresponds to 6664 * consumer AMD devices but nothing else. 6665 * 6666 * Note that this code assumes features expansion has already been done 6667 * (as it checks for CPUID_EXT2_LM), and also assumes that potential 6668 * phys_bits adjustments to match the host have been already done in 6669 * accel-specific code in cpu_exec_realizefn. 6670 */ 6671 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 6672 if (cpu->phys_bits && 6673 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS || 6674 cpu->phys_bits < 32)) { 6675 error_setg(errp, "phys-bits should be between 32 and %u " 6676 " (but is %u)", 6677 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits); 6678 return; 6679 } 6680 /* 6681 * 0 means it was not explicitly set by the user (or by machine 6682 * compat_props or by the host code in host-cpu.c). 6683 * In this case, the default is the value used by TCG (40). 6684 */ 6685 if (cpu->phys_bits == 0) { 6686 cpu->phys_bits = TCG_PHYS_ADDR_BITS; 6687 } 6688 } else { 6689 /* For 32 bit systems don't use the user set value, but keep 6690 * phys_bits consistent with what we tell the guest. 6691 */ 6692 if (cpu->phys_bits != 0) { 6693 error_setg(errp, "phys-bits is not user-configurable in 32 bit"); 6694 return; 6695 } 6696 6697 if (env->features[FEAT_1_EDX] & CPUID_PSE36) { 6698 cpu->phys_bits = 36; 6699 } else { 6700 cpu->phys_bits = 32; 6701 } 6702 } 6703 6704 /* Cache information initialization */ 6705 if (!cpu->legacy_cache) { 6706 if (!xcc->model || !xcc->model->cpudef->cache_info) { 6707 g_autofree char *name = x86_cpu_class_get_model_name(xcc); 6708 error_setg(errp, 6709 "CPU model '%s' doesn't support legacy-cache=off", name); 6710 return; 6711 } 6712 env->cache_info_cpuid2 = env->cache_info_cpuid4 = env->cache_info_amd = 6713 *xcc->model->cpudef->cache_info; 6714 } else { 6715 /* Build legacy cache information */ 6716 env->cache_info_cpuid2.l1d_cache = &legacy_l1d_cache; 6717 env->cache_info_cpuid2.l1i_cache = &legacy_l1i_cache; 6718 env->cache_info_cpuid2.l2_cache = &legacy_l2_cache_cpuid2; 6719 env->cache_info_cpuid2.l3_cache = &legacy_l3_cache; 6720 6721 env->cache_info_cpuid4.l1d_cache = &legacy_l1d_cache; 6722 env->cache_info_cpuid4.l1i_cache = &legacy_l1i_cache; 6723 env->cache_info_cpuid4.l2_cache = &legacy_l2_cache; 6724 env->cache_info_cpuid4.l3_cache = &legacy_l3_cache; 6725 6726 env->cache_info_amd.l1d_cache = &legacy_l1d_cache_amd; 6727 env->cache_info_amd.l1i_cache = &legacy_l1i_cache_amd; 6728 env->cache_info_amd.l2_cache = &legacy_l2_cache_amd; 6729 env->cache_info_amd.l3_cache = &legacy_l3_cache; 6730 } 6731 6732 #ifndef CONFIG_USER_ONLY 6733 MachineState *ms = MACHINE(qdev_get_machine()); 6734 qemu_register_reset(x86_cpu_machine_reset_cb, cpu); 6735 6736 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || ms->smp.cpus > 1) { 6737 x86_cpu_apic_create(cpu, &local_err); 6738 if (local_err != NULL) { 6739 goto out; 6740 } 6741 } 6742 #endif 6743 6744 mce_init(cpu); 6745 6746 qemu_init_vcpu(cs); 6747 6748 /* 6749 * Most Intel and certain AMD CPUs support hyperthreading. Even though QEMU 6750 * fixes this issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX 6751 * based on inputs (sockets,cores,threads), it is still better to give 6752 * users a warning. 6753 * 6754 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise 6755 * cs->nr_threads hasn't be populated yet and the checking is incorrect. 6756 */ 6757 if (IS_AMD_CPU(env) && 6758 !(env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) && 6759 cs->nr_threads > 1 && !ht_warned) { 6760 warn_report("This family of AMD CPU doesn't support " 6761 "hyperthreading(%d)", 6762 cs->nr_threads); 6763 error_printf("Please configure -smp options properly" 6764 " or try enabling topoext feature.\n"); 6765 ht_warned = true; 6766 } 6767 6768 #ifndef CONFIG_USER_ONLY 6769 x86_cpu_apic_realize(cpu, &local_err); 6770 if (local_err != NULL) { 6771 goto out; 6772 } 6773 #endif /* !CONFIG_USER_ONLY */ 6774 cpu_reset(cs); 6775 6776 xcc->parent_realize(dev, &local_err); 6777 6778 out: 6779 if (local_err != NULL) { 6780 error_propagate(errp, local_err); 6781 return; 6782 } 6783 } 6784 6785 static void x86_cpu_unrealizefn(DeviceState *dev) 6786 { 6787 X86CPU *cpu = X86_CPU(dev); 6788 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev); 6789 6790 #ifndef CONFIG_USER_ONLY 6791 cpu_remove_sync(CPU(dev)); 6792 qemu_unregister_reset(x86_cpu_machine_reset_cb, dev); 6793 #endif 6794 6795 if (cpu->apic_state) { 6796 object_unparent(OBJECT(cpu->apic_state)); 6797 cpu->apic_state = NULL; 6798 } 6799 6800 xcc->parent_unrealize(dev); 6801 } 6802 6803 typedef struct BitProperty { 6804 FeatureWord w; 6805 uint64_t mask; 6806 } BitProperty; 6807 6808 static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name, 6809 void *opaque, Error **errp) 6810 { 6811 X86CPU *cpu = X86_CPU(obj); 6812 BitProperty *fp = opaque; 6813 uint64_t f = cpu->env.features[fp->w]; 6814 bool value = (f & fp->mask) == fp->mask; 6815 visit_type_bool(v, name, &value, errp); 6816 } 6817 6818 static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name, 6819 void *opaque, Error **errp) 6820 { 6821 DeviceState *dev = DEVICE(obj); 6822 X86CPU *cpu = X86_CPU(obj); 6823 BitProperty *fp = opaque; 6824 bool value; 6825 6826 if (dev->realized) { 6827 qdev_prop_set_after_realize(dev, name, errp); 6828 return; 6829 } 6830 6831 if (!visit_type_bool(v, name, &value, errp)) { 6832 return; 6833 } 6834 6835 if (value) { 6836 cpu->env.features[fp->w] |= fp->mask; 6837 } else { 6838 cpu->env.features[fp->w] &= ~fp->mask; 6839 } 6840 cpu->env.user_features[fp->w] |= fp->mask; 6841 } 6842 6843 /* Register a boolean property to get/set a single bit in a uint32_t field. 6844 * 6845 * The same property name can be registered multiple times to make it affect 6846 * multiple bits in the same FeatureWord. In that case, the getter will return 6847 * true only if all bits are set. 6848 */ 6849 static void x86_cpu_register_bit_prop(X86CPUClass *xcc, 6850 const char *prop_name, 6851 FeatureWord w, 6852 int bitnr) 6853 { 6854 ObjectClass *oc = OBJECT_CLASS(xcc); 6855 BitProperty *fp; 6856 ObjectProperty *op; 6857 uint64_t mask = (1ULL << bitnr); 6858 6859 op = object_class_property_find(oc, prop_name); 6860 if (op) { 6861 fp = op->opaque; 6862 assert(fp->w == w); 6863 fp->mask |= mask; 6864 } else { 6865 fp = g_new0(BitProperty, 1); 6866 fp->w = w; 6867 fp->mask = mask; 6868 object_class_property_add(oc, prop_name, "bool", 6869 x86_cpu_get_bit_prop, 6870 x86_cpu_set_bit_prop, 6871 NULL, fp); 6872 } 6873 } 6874 6875 static void x86_cpu_register_feature_bit_props(X86CPUClass *xcc, 6876 FeatureWord w, 6877 int bitnr) 6878 { 6879 FeatureWordInfo *fi = &feature_word_info[w]; 6880 const char *name = fi->feat_names[bitnr]; 6881 6882 if (!name) { 6883 return; 6884 } 6885 6886 /* Property names should use "-" instead of "_". 6887 * Old names containing underscores are registered as aliases 6888 * using object_property_add_alias() 6889 */ 6890 assert(!strchr(name, '_')); 6891 /* aliases don't use "|" delimiters anymore, they are registered 6892 * manually using object_property_add_alias() */ 6893 assert(!strchr(name, '|')); 6894 x86_cpu_register_bit_prop(xcc, name, w, bitnr); 6895 } 6896 6897 static void x86_cpu_post_initfn(Object *obj) 6898 { 6899 accel_cpu_instance_init(CPU(obj)); 6900 } 6901 6902 static void x86_cpu_initfn(Object *obj) 6903 { 6904 X86CPU *cpu = X86_CPU(obj); 6905 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj); 6906 CPUX86State *env = &cpu->env; 6907 6908 env->nr_dies = 1; 6909 cpu_set_cpustate_pointers(cpu); 6910 6911 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo", 6912 x86_cpu_get_feature_words, 6913 NULL, NULL, (void *)env->features); 6914 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo", 6915 x86_cpu_get_feature_words, 6916 NULL, NULL, (void *)cpu->filtered_features); 6917 6918 object_property_add_alias(obj, "sse3", obj, "pni"); 6919 object_property_add_alias(obj, "pclmuldq", obj, "pclmulqdq"); 6920 object_property_add_alias(obj, "sse4-1", obj, "sse4.1"); 6921 object_property_add_alias(obj, "sse4-2", obj, "sse4.2"); 6922 object_property_add_alias(obj, "xd", obj, "nx"); 6923 object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt"); 6924 object_property_add_alias(obj, "i64", obj, "lm"); 6925 6926 object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl"); 6927 object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust"); 6928 object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt"); 6929 object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm"); 6930 object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy"); 6931 object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr"); 6932 object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core"); 6933 object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb"); 6934 object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay"); 6935 object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu"); 6936 object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf"); 6937 object_property_add_alias(obj, "kvm_asyncpf_int", obj, "kvm-asyncpf-int"); 6938 object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time"); 6939 object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi"); 6940 object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt"); 6941 object_property_add_alias(obj, "kvm_poll_control", obj, "kvm-poll-control"); 6942 object_property_add_alias(obj, "svm_lock", obj, "svm-lock"); 6943 object_property_add_alias(obj, "nrip_save", obj, "nrip-save"); 6944 object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale"); 6945 object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean"); 6946 object_property_add_alias(obj, "pause_filter", obj, "pause-filter"); 6947 object_property_add_alias(obj, "sse4_1", obj, "sse4.1"); 6948 object_property_add_alias(obj, "sse4_2", obj, "sse4.2"); 6949 6950 object_property_add_alias(obj, "hv-apicv", obj, "hv-avic"); 6951 cpu->lbr_fmt = ~PERF_CAP_LBR_FMT; 6952 object_property_add_alias(obj, "lbr_fmt", obj, "lbr-fmt"); 6953 6954 if (xcc->model) { 6955 x86_cpu_load_model(cpu, xcc->model); 6956 } 6957 } 6958 6959 static int64_t x86_cpu_get_arch_id(CPUState *cs) 6960 { 6961 X86CPU *cpu = X86_CPU(cs); 6962 6963 return cpu->apic_id; 6964 } 6965 6966 #if !defined(CONFIG_USER_ONLY) 6967 static bool x86_cpu_get_paging_enabled(const CPUState *cs) 6968 { 6969 X86CPU *cpu = X86_CPU(cs); 6970 6971 return cpu->env.cr[0] & CR0_PG_MASK; 6972 } 6973 #endif /* !CONFIG_USER_ONLY */ 6974 6975 static void x86_cpu_set_pc(CPUState *cs, vaddr value) 6976 { 6977 X86CPU *cpu = X86_CPU(cs); 6978 6979 cpu->env.eip = value; 6980 } 6981 6982 static vaddr x86_cpu_get_pc(CPUState *cs) 6983 { 6984 X86CPU *cpu = X86_CPU(cs); 6985 6986 /* Match cpu_get_tb_cpu_state. */ 6987 return cpu->env.eip + cpu->env.segs[R_CS].base; 6988 } 6989 6990 int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request) 6991 { 6992 X86CPU *cpu = X86_CPU(cs); 6993 CPUX86State *env = &cpu->env; 6994 6995 #if !defined(CONFIG_USER_ONLY) 6996 if (interrupt_request & CPU_INTERRUPT_POLL) { 6997 return CPU_INTERRUPT_POLL; 6998 } 6999 #endif 7000 if (interrupt_request & CPU_INTERRUPT_SIPI) { 7001 return CPU_INTERRUPT_SIPI; 7002 } 7003 7004 if (env->hflags2 & HF2_GIF_MASK) { 7005 if ((interrupt_request & CPU_INTERRUPT_SMI) && 7006 !(env->hflags & HF_SMM_MASK)) { 7007 return CPU_INTERRUPT_SMI; 7008 } else if ((interrupt_request & CPU_INTERRUPT_NMI) && 7009 !(env->hflags2 & HF2_NMI_MASK)) { 7010 return CPU_INTERRUPT_NMI; 7011 } else if (interrupt_request & CPU_INTERRUPT_MCE) { 7012 return CPU_INTERRUPT_MCE; 7013 } else if ((interrupt_request & CPU_INTERRUPT_HARD) && 7014 (((env->hflags2 & HF2_VINTR_MASK) && 7015 (env->hflags2 & HF2_HIF_MASK)) || 7016 (!(env->hflags2 & HF2_VINTR_MASK) && 7017 (env->eflags & IF_MASK && 7018 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) { 7019 return CPU_INTERRUPT_HARD; 7020 #if !defined(CONFIG_USER_ONLY) 7021 } else if (env->hflags2 & HF2_VGIF_MASK) { 7022 if((interrupt_request & CPU_INTERRUPT_VIRQ) && 7023 (env->eflags & IF_MASK) && 7024 !(env->hflags & HF_INHIBIT_IRQ_MASK)) { 7025 return CPU_INTERRUPT_VIRQ; 7026 } 7027 #endif 7028 } 7029 } 7030 7031 return 0; 7032 } 7033 7034 static bool x86_cpu_has_work(CPUState *cs) 7035 { 7036 return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0; 7037 } 7038 7039 static void x86_disas_set_info(CPUState *cs, disassemble_info *info) 7040 { 7041 X86CPU *cpu = X86_CPU(cs); 7042 CPUX86State *env = &cpu->env; 7043 7044 info->mach = (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64 7045 : env->hflags & HF_CS32_MASK ? bfd_mach_i386_i386 7046 : bfd_mach_i386_i8086); 7047 7048 info->cap_arch = CS_ARCH_X86; 7049 info->cap_mode = (env->hflags & HF_CS64_MASK ? CS_MODE_64 7050 : env->hflags & HF_CS32_MASK ? CS_MODE_32 7051 : CS_MODE_16); 7052 info->cap_insn_unit = 1; 7053 info->cap_insn_split = 8; 7054 } 7055 7056 void x86_update_hflags(CPUX86State *env) 7057 { 7058 uint32_t hflags; 7059 #define HFLAG_COPY_MASK \ 7060 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \ 7061 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \ 7062 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \ 7063 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK) 7064 7065 hflags = env->hflags & HFLAG_COPY_MASK; 7066 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK; 7067 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT); 7068 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) & 7069 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK); 7070 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK)); 7071 7072 if (env->cr[4] & CR4_OSFXSR_MASK) { 7073 hflags |= HF_OSFXSR_MASK; 7074 } 7075 7076 if (env->efer & MSR_EFER_LMA) { 7077 hflags |= HF_LMA_MASK; 7078 } 7079 7080 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) { 7081 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; 7082 } else { 7083 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >> 7084 (DESC_B_SHIFT - HF_CS32_SHIFT); 7085 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >> 7086 (DESC_B_SHIFT - HF_SS32_SHIFT); 7087 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) || 7088 !(hflags & HF_CS32_MASK)) { 7089 hflags |= HF_ADDSEG_MASK; 7090 } else { 7091 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base | 7092 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT; 7093 } 7094 } 7095 env->hflags = hflags; 7096 } 7097 7098 static Property x86_cpu_properties[] = { 7099 #ifdef CONFIG_USER_ONLY 7100 /* apic_id = 0 by default for *-user, see commit 9886e834 */ 7101 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0), 7102 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0), 7103 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0), 7104 DEFINE_PROP_INT32("die-id", X86CPU, die_id, 0), 7105 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0), 7106 #else 7107 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID), 7108 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1), 7109 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1), 7110 DEFINE_PROP_INT32("die-id", X86CPU, die_id, -1), 7111 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1), 7112 #endif 7113 DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID), 7114 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false), 7115 DEFINE_PROP_UINT64_CHECKMASK("lbr-fmt", X86CPU, lbr_fmt, PERF_CAP_LBR_FMT), 7116 7117 DEFINE_PROP_UINT32("hv-spinlocks", X86CPU, hyperv_spinlock_attempts, 7118 HYPERV_SPINLOCK_NEVER_NOTIFY), 7119 DEFINE_PROP_BIT64("hv-relaxed", X86CPU, hyperv_features, 7120 HYPERV_FEAT_RELAXED, 0), 7121 DEFINE_PROP_BIT64("hv-vapic", X86CPU, hyperv_features, 7122 HYPERV_FEAT_VAPIC, 0), 7123 DEFINE_PROP_BIT64("hv-time", X86CPU, hyperv_features, 7124 HYPERV_FEAT_TIME, 0), 7125 DEFINE_PROP_BIT64("hv-crash", X86CPU, hyperv_features, 7126 HYPERV_FEAT_CRASH, 0), 7127 DEFINE_PROP_BIT64("hv-reset", X86CPU, hyperv_features, 7128 HYPERV_FEAT_RESET, 0), 7129 DEFINE_PROP_BIT64("hv-vpindex", X86CPU, hyperv_features, 7130 HYPERV_FEAT_VPINDEX, 0), 7131 DEFINE_PROP_BIT64("hv-runtime", X86CPU, hyperv_features, 7132 HYPERV_FEAT_RUNTIME, 0), 7133 DEFINE_PROP_BIT64("hv-synic", X86CPU, hyperv_features, 7134 HYPERV_FEAT_SYNIC, 0), 7135 DEFINE_PROP_BIT64("hv-stimer", X86CPU, hyperv_features, 7136 HYPERV_FEAT_STIMER, 0), 7137 DEFINE_PROP_BIT64("hv-frequencies", X86CPU, hyperv_features, 7138 HYPERV_FEAT_FREQUENCIES, 0), 7139 DEFINE_PROP_BIT64("hv-reenlightenment", X86CPU, hyperv_features, 7140 HYPERV_FEAT_REENLIGHTENMENT, 0), 7141 DEFINE_PROP_BIT64("hv-tlbflush", X86CPU, hyperv_features, 7142 HYPERV_FEAT_TLBFLUSH, 0), 7143 DEFINE_PROP_BIT64("hv-evmcs", X86CPU, hyperv_features, 7144 HYPERV_FEAT_EVMCS, 0), 7145 DEFINE_PROP_BIT64("hv-ipi", X86CPU, hyperv_features, 7146 HYPERV_FEAT_IPI, 0), 7147 DEFINE_PROP_BIT64("hv-stimer-direct", X86CPU, hyperv_features, 7148 HYPERV_FEAT_STIMER_DIRECT, 0), 7149 DEFINE_PROP_BIT64("hv-avic", X86CPU, hyperv_features, 7150 HYPERV_FEAT_AVIC, 0), 7151 DEFINE_PROP_BIT64("hv-emsr-bitmap", X86CPU, hyperv_features, 7152 HYPERV_FEAT_MSR_BITMAP, 0), 7153 DEFINE_PROP_BIT64("hv-xmm-input", X86CPU, hyperv_features, 7154 HYPERV_FEAT_XMM_INPUT, 0), 7155 DEFINE_PROP_BIT64("hv-tlbflush-ext", X86CPU, hyperv_features, 7156 HYPERV_FEAT_TLBFLUSH_EXT, 0), 7157 DEFINE_PROP_BIT64("hv-tlbflush-direct", X86CPU, hyperv_features, 7158 HYPERV_FEAT_TLBFLUSH_DIRECT, 0), 7159 DEFINE_PROP_ON_OFF_AUTO("hv-no-nonarch-coresharing", X86CPU, 7160 hyperv_no_nonarch_cs, ON_OFF_AUTO_OFF), 7161 DEFINE_PROP_BIT64("hv-syndbg", X86CPU, hyperv_features, 7162 HYPERV_FEAT_SYNDBG, 0), 7163 DEFINE_PROP_BOOL("hv-passthrough", X86CPU, hyperv_passthrough, false), 7164 DEFINE_PROP_BOOL("hv-enforce-cpuid", X86CPU, hyperv_enforce_cpuid, false), 7165 7166 /* WS2008R2 identify by default */ 7167 DEFINE_PROP_UINT32("hv-version-id-build", X86CPU, hyperv_ver_id_build, 7168 0x3839), 7169 DEFINE_PROP_UINT16("hv-version-id-major", X86CPU, hyperv_ver_id_major, 7170 0x000A), 7171 DEFINE_PROP_UINT16("hv-version-id-minor", X86CPU, hyperv_ver_id_minor, 7172 0x0000), 7173 DEFINE_PROP_UINT32("hv-version-id-spack", X86CPU, hyperv_ver_id_sp, 0), 7174 DEFINE_PROP_UINT8("hv-version-id-sbranch", X86CPU, hyperv_ver_id_sb, 0), 7175 DEFINE_PROP_UINT32("hv-version-id-snumber", X86CPU, hyperv_ver_id_sn, 0), 7176 7177 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true), 7178 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false), 7179 DEFINE_PROP_BOOL("x-force-features", X86CPU, force_features, false), 7180 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true), 7181 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0), 7182 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false), 7183 DEFINE_PROP_UINT8("host-phys-bits-limit", X86CPU, host_phys_bits_limit, 0), 7184 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true), 7185 DEFINE_PROP_UINT32("level-func7", X86CPU, env.cpuid_level_func7, 7186 UINT32_MAX), 7187 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX), 7188 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX), 7189 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX), 7190 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0), 7191 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0), 7192 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0), 7193 DEFINE_PROP_UINT64("ucode-rev", X86CPU, ucode_rev, 0), 7194 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true), 7195 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor), 7196 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true), 7197 DEFINE_PROP_BOOL("x-vendor-cpuid-only", X86CPU, vendor_cpuid_only, true), 7198 DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false), 7199 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true), 7200 DEFINE_PROP_BOOL("kvm-no-smi-migration", X86CPU, kvm_no_smi_migration, 7201 false), 7202 DEFINE_PROP_BOOL("kvm-pv-enforce-cpuid", X86CPU, kvm_pv_enforce_cpuid, 7203 false), 7204 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true), 7205 DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true), 7206 DEFINE_PROP_BOOL("x-migrate-smi-count", X86CPU, migrate_smi_count, 7207 true), 7208 /* 7209 * lecacy_cache defaults to true unless the CPU model provides its 7210 * own cache information (see x86_cpu_load_def()). 7211 */ 7212 DEFINE_PROP_BOOL("legacy-cache", X86CPU, legacy_cache, true), 7213 DEFINE_PROP_BOOL("xen-vapic", X86CPU, xen_vapic, false), 7214 7215 /* 7216 * From "Requirements for Implementing the Microsoft 7217 * Hypervisor Interface": 7218 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs 7219 * 7220 * "Starting with Windows Server 2012 and Windows 8, if 7221 * CPUID.40000005.EAX contains a value of -1, Windows assumes that 7222 * the hypervisor imposes no specific limit to the number of VPs. 7223 * In this case, Windows Server 2012 guest VMs may use more than 7224 * 64 VPs, up to the maximum supported number of processors applicable 7225 * to the specific Windows version being used." 7226 */ 7227 DEFINE_PROP_INT32("x-hv-max-vps", X86CPU, hv_max_vps, -1), 7228 DEFINE_PROP_BOOL("x-hv-synic-kvm-only", X86CPU, hyperv_synic_kvm_only, 7229 false), 7230 DEFINE_PROP_BOOL("x-intel-pt-auto-level", X86CPU, intel_pt_auto_level, 7231 true), 7232 DEFINE_PROP_END_OF_LIST() 7233 }; 7234 7235 #ifndef CONFIG_USER_ONLY 7236 #include "hw/core/sysemu-cpu-ops.h" 7237 7238 static const struct SysemuCPUOps i386_sysemu_ops = { 7239 .get_memory_mapping = x86_cpu_get_memory_mapping, 7240 .get_paging_enabled = x86_cpu_get_paging_enabled, 7241 .get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug, 7242 .asidx_from_attrs = x86_asidx_from_attrs, 7243 .get_crash_info = x86_cpu_get_crash_info, 7244 .write_elf32_note = x86_cpu_write_elf32_note, 7245 .write_elf64_note = x86_cpu_write_elf64_note, 7246 .write_elf32_qemunote = x86_cpu_write_elf32_qemunote, 7247 .write_elf64_qemunote = x86_cpu_write_elf64_qemunote, 7248 .legacy_vmsd = &vmstate_x86_cpu, 7249 }; 7250 #endif 7251 7252 static void x86_cpu_common_class_init(ObjectClass *oc, void *data) 7253 { 7254 X86CPUClass *xcc = X86_CPU_CLASS(oc); 7255 CPUClass *cc = CPU_CLASS(oc); 7256 DeviceClass *dc = DEVICE_CLASS(oc); 7257 ResettableClass *rc = RESETTABLE_CLASS(oc); 7258 FeatureWord w; 7259 7260 device_class_set_parent_realize(dc, x86_cpu_realizefn, 7261 &xcc->parent_realize); 7262 device_class_set_parent_unrealize(dc, x86_cpu_unrealizefn, 7263 &xcc->parent_unrealize); 7264 device_class_set_props(dc, x86_cpu_properties); 7265 7266 resettable_class_set_parent_phases(rc, NULL, x86_cpu_reset_hold, NULL, 7267 &xcc->parent_phases); 7268 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP; 7269 7270 cc->class_by_name = x86_cpu_class_by_name; 7271 cc->parse_features = x86_cpu_parse_featurestr; 7272 cc->has_work = x86_cpu_has_work; 7273 cc->dump_state = x86_cpu_dump_state; 7274 cc->set_pc = x86_cpu_set_pc; 7275 cc->get_pc = x86_cpu_get_pc; 7276 cc->gdb_read_register = x86_cpu_gdb_read_register; 7277 cc->gdb_write_register = x86_cpu_gdb_write_register; 7278 cc->get_arch_id = x86_cpu_get_arch_id; 7279 7280 #ifndef CONFIG_USER_ONLY 7281 cc->sysemu_ops = &i386_sysemu_ops; 7282 #endif /* !CONFIG_USER_ONLY */ 7283 7284 cc->gdb_arch_name = x86_gdb_arch_name; 7285 #ifdef TARGET_X86_64 7286 cc->gdb_core_xml_file = "i386-64bit.xml"; 7287 cc->gdb_num_core_regs = 66; 7288 #else 7289 cc->gdb_core_xml_file = "i386-32bit.xml"; 7290 cc->gdb_num_core_regs = 50; 7291 #endif 7292 cc->disas_set_info = x86_disas_set_info; 7293 7294 dc->user_creatable = true; 7295 7296 object_class_property_add(oc, "family", "int", 7297 x86_cpuid_version_get_family, 7298 x86_cpuid_version_set_family, NULL, NULL); 7299 object_class_property_add(oc, "model", "int", 7300 x86_cpuid_version_get_model, 7301 x86_cpuid_version_set_model, NULL, NULL); 7302 object_class_property_add(oc, "stepping", "int", 7303 x86_cpuid_version_get_stepping, 7304 x86_cpuid_version_set_stepping, NULL, NULL); 7305 object_class_property_add_str(oc, "vendor", 7306 x86_cpuid_get_vendor, 7307 x86_cpuid_set_vendor); 7308 object_class_property_add_str(oc, "model-id", 7309 x86_cpuid_get_model_id, 7310 x86_cpuid_set_model_id); 7311 object_class_property_add(oc, "tsc-frequency", "int", 7312 x86_cpuid_get_tsc_freq, 7313 x86_cpuid_set_tsc_freq, NULL, NULL); 7314 /* 7315 * The "unavailable-features" property has the same semantics as 7316 * CpuDefinitionInfo.unavailable-features on the "query-cpu-definitions" 7317 * QMP command: they list the features that would have prevented the 7318 * CPU from running if the "enforce" flag was set. 7319 */ 7320 object_class_property_add(oc, "unavailable-features", "strList", 7321 x86_cpu_get_unavailable_features, 7322 NULL, NULL, NULL); 7323 7324 #if !defined(CONFIG_USER_ONLY) 7325 object_class_property_add(oc, "crash-information", "GuestPanicInformation", 7326 x86_cpu_get_crash_info_qom, NULL, NULL, NULL); 7327 #endif 7328 7329 for (w = 0; w < FEATURE_WORDS; w++) { 7330 int bitnr; 7331 for (bitnr = 0; bitnr < 64; bitnr++) { 7332 x86_cpu_register_feature_bit_props(xcc, w, bitnr); 7333 } 7334 } 7335 } 7336 7337 static const TypeInfo x86_cpu_type_info = { 7338 .name = TYPE_X86_CPU, 7339 .parent = TYPE_CPU, 7340 .instance_size = sizeof(X86CPU), 7341 .instance_init = x86_cpu_initfn, 7342 .instance_post_init = x86_cpu_post_initfn, 7343 7344 .abstract = true, 7345 .class_size = sizeof(X86CPUClass), 7346 .class_init = x86_cpu_common_class_init, 7347 }; 7348 7349 /* "base" CPU model, used by query-cpu-model-expansion */ 7350 static void x86_cpu_base_class_init(ObjectClass *oc, void *data) 7351 { 7352 X86CPUClass *xcc = X86_CPU_CLASS(oc); 7353 7354 xcc->static_model = true; 7355 xcc->migration_safe = true; 7356 xcc->model_description = "base CPU model type with no features enabled"; 7357 xcc->ordering = 8; 7358 } 7359 7360 static const TypeInfo x86_base_cpu_type_info = { 7361 .name = X86_CPU_TYPE_NAME("base"), 7362 .parent = TYPE_X86_CPU, 7363 .class_init = x86_cpu_base_class_init, 7364 }; 7365 7366 static void x86_cpu_register_types(void) 7367 { 7368 int i; 7369 7370 type_register_static(&x86_cpu_type_info); 7371 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) { 7372 x86_register_cpudef_types(&builtin_x86_defs[i]); 7373 } 7374 type_register_static(&max_x86_cpu_type_info); 7375 type_register_static(&x86_base_cpu_type_info); 7376 } 7377 7378 type_init(x86_cpu_register_types) 7379