1 /* 2 * i386 CPUID, CPU class, definitions, models 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/units.h" 22 #include "qemu/cutils.h" 23 #include "qemu/qemu-print.h" 24 #include "qemu/hw-version.h" 25 #include "cpu.h" 26 #include "tcg/helper-tcg.h" 27 #include "exec/translation-block.h" 28 #include "system/hvf.h" 29 #include "hvf/hvf-i386.h" 30 #include "kvm/kvm_i386.h" 31 #include "sev.h" 32 #include "qapi/error.h" 33 #include "qemu/error-report.h" 34 #include "qapi/qapi-visit-machine.h" 35 #include "standard-headers/asm-x86/kvm_para.h" 36 #include "hw/qdev-properties.h" 37 #include "hw/i386/topology.h" 38 #ifndef CONFIG_USER_ONLY 39 #include "system/reset.h" 40 #include "qapi/qapi-commands-machine-target.h" 41 #include "exec/address-spaces.h" 42 #include "hw/boards.h" 43 #include "hw/i386/sgx-epc.h" 44 #endif 45 46 #include "disas/capstone.h" 47 #include "cpu-internal.h" 48 49 static void x86_cpu_realizefn(DeviceState *dev, Error **errp); 50 static void x86_cpu_get_supported_cpuid(uint32_t func, uint32_t index, 51 uint32_t *eax, uint32_t *ebx, 52 uint32_t *ecx, uint32_t *edx); 53 54 /* Helpers for building CPUID[2] descriptors: */ 55 56 struct CPUID2CacheDescriptorInfo { 57 enum CacheType type; 58 int level; 59 int size; 60 int line_size; 61 int associativity; 62 }; 63 64 /* 65 * Known CPUID 2 cache descriptors. 66 * From Intel SDM Volume 2A, CPUID instruction 67 */ 68 struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = { 69 [0x06] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 8 * KiB, 70 .associativity = 4, .line_size = 32, }, 71 [0x08] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 16 * KiB, 72 .associativity = 4, .line_size = 32, }, 73 [0x09] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB, 74 .associativity = 4, .line_size = 64, }, 75 [0x0A] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB, 76 .associativity = 2, .line_size = 32, }, 77 [0x0C] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 78 .associativity = 4, .line_size = 32, }, 79 [0x0D] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 80 .associativity = 4, .line_size = 64, }, 81 [0x0E] = { .level = 1, .type = DATA_CACHE, .size = 24 * KiB, 82 .associativity = 6, .line_size = 64, }, 83 [0x1D] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB, 84 .associativity = 2, .line_size = 64, }, 85 [0x21] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 86 .associativity = 8, .line_size = 64, }, 87 /* lines per sector is not supported cpuid2_cache_descriptor(), 88 * so descriptors 0x22, 0x23 are not included 89 */ 90 [0x24] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 91 .associativity = 16, .line_size = 64, }, 92 /* lines per sector is not supported cpuid2_cache_descriptor(), 93 * so descriptors 0x25, 0x20 are not included 94 */ 95 [0x2C] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB, 96 .associativity = 8, .line_size = 64, }, 97 [0x30] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB, 98 .associativity = 8, .line_size = 64, }, 99 [0x41] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB, 100 .associativity = 4, .line_size = 32, }, 101 [0x42] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 102 .associativity = 4, .line_size = 32, }, 103 [0x43] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 104 .associativity = 4, .line_size = 32, }, 105 [0x44] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 106 .associativity = 4, .line_size = 32, }, 107 [0x45] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 108 .associativity = 4, .line_size = 32, }, 109 [0x46] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 110 .associativity = 4, .line_size = 64, }, 111 [0x47] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 112 .associativity = 8, .line_size = 64, }, 113 [0x48] = { .level = 2, .type = UNIFIED_CACHE, .size = 3 * MiB, 114 .associativity = 12, .line_size = 64, }, 115 /* Descriptor 0x49 depends on CPU family/model, so it is not included */ 116 [0x4A] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB, 117 .associativity = 12, .line_size = 64, }, 118 [0x4B] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 119 .associativity = 16, .line_size = 64, }, 120 [0x4C] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB, 121 .associativity = 12, .line_size = 64, }, 122 [0x4D] = { .level = 3, .type = UNIFIED_CACHE, .size = 16 * MiB, 123 .associativity = 16, .line_size = 64, }, 124 [0x4E] = { .level = 2, .type = UNIFIED_CACHE, .size = 6 * MiB, 125 .associativity = 24, .line_size = 64, }, 126 [0x60] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 127 .associativity = 8, .line_size = 64, }, 128 [0x66] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB, 129 .associativity = 4, .line_size = 64, }, 130 [0x67] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 131 .associativity = 4, .line_size = 64, }, 132 [0x68] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB, 133 .associativity = 4, .line_size = 64, }, 134 [0x78] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 135 .associativity = 4, .line_size = 64, }, 136 /* lines per sector is not supported cpuid2_cache_descriptor(), 137 * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included. 138 */ 139 [0x7D] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 140 .associativity = 8, .line_size = 64, }, 141 [0x7F] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 142 .associativity = 2, .line_size = 64, }, 143 [0x80] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 144 .associativity = 8, .line_size = 64, }, 145 [0x82] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 146 .associativity = 8, .line_size = 32, }, 147 [0x83] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 148 .associativity = 8, .line_size = 32, }, 149 [0x84] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 150 .associativity = 8, .line_size = 32, }, 151 [0x85] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 152 .associativity = 8, .line_size = 32, }, 153 [0x86] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 154 .associativity = 4, .line_size = 64, }, 155 [0x87] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 156 .associativity = 8, .line_size = 64, }, 157 [0xD0] = { .level = 3, .type = UNIFIED_CACHE, .size = 512 * KiB, 158 .associativity = 4, .line_size = 64, }, 159 [0xD1] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB, 160 .associativity = 4, .line_size = 64, }, 161 [0xD2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 162 .associativity = 4, .line_size = 64, }, 163 [0xD6] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB, 164 .associativity = 8, .line_size = 64, }, 165 [0xD7] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 166 .associativity = 8, .line_size = 64, }, 167 [0xD8] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 168 .associativity = 8, .line_size = 64, }, 169 [0xDC] = { .level = 3, .type = UNIFIED_CACHE, .size = 1.5 * MiB, 170 .associativity = 12, .line_size = 64, }, 171 [0xDD] = { .level = 3, .type = UNIFIED_CACHE, .size = 3 * MiB, 172 .associativity = 12, .line_size = 64, }, 173 [0xDE] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB, 174 .associativity = 12, .line_size = 64, }, 175 [0xE2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 176 .associativity = 16, .line_size = 64, }, 177 [0xE3] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 178 .associativity = 16, .line_size = 64, }, 179 [0xE4] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 180 .associativity = 16, .line_size = 64, }, 181 [0xEA] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB, 182 .associativity = 24, .line_size = 64, }, 183 [0xEB] = { .level = 3, .type = UNIFIED_CACHE, .size = 18 * MiB, 184 .associativity = 24, .line_size = 64, }, 185 [0xEC] = { .level = 3, .type = UNIFIED_CACHE, .size = 24 * MiB, 186 .associativity = 24, .line_size = 64, }, 187 }; 188 189 /* 190 * "CPUID leaf 2 does not report cache descriptor information, 191 * use CPUID leaf 4 to query cache parameters" 192 */ 193 #define CACHE_DESCRIPTOR_UNAVAILABLE 0xFF 194 195 /* 196 * Return a CPUID 2 cache descriptor for a given cache. 197 * If no known descriptor is found, return CACHE_DESCRIPTOR_UNAVAILABLE 198 */ 199 static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache) 200 { 201 int i; 202 203 assert(cache->size > 0); 204 assert(cache->level > 0); 205 assert(cache->line_size > 0); 206 assert(cache->associativity > 0); 207 for (i = 0; i < ARRAY_SIZE(cpuid2_cache_descriptors); i++) { 208 struct CPUID2CacheDescriptorInfo *d = &cpuid2_cache_descriptors[i]; 209 if (d->level == cache->level && d->type == cache->type && 210 d->size == cache->size && d->line_size == cache->line_size && 211 d->associativity == cache->associativity) { 212 return i; 213 } 214 } 215 216 return CACHE_DESCRIPTOR_UNAVAILABLE; 217 } 218 219 /* CPUID Leaf 4 constants: */ 220 221 /* EAX: */ 222 #define CACHE_TYPE_D 1 223 #define CACHE_TYPE_I 2 224 #define CACHE_TYPE_UNIFIED 3 225 226 #define CACHE_LEVEL(l) (l << 5) 227 228 #define CACHE_SELF_INIT_LEVEL (1 << 8) 229 230 /* EDX: */ 231 #define CACHE_NO_INVD_SHARING (1 << 0) 232 #define CACHE_INCLUSIVE (1 << 1) 233 #define CACHE_COMPLEX_IDX (1 << 2) 234 235 /* Encode CacheType for CPUID[4].EAX */ 236 #define CACHE_TYPE(t) (((t) == DATA_CACHE) ? CACHE_TYPE_D : \ 237 ((t) == INSTRUCTION_CACHE) ? CACHE_TYPE_I : \ 238 ((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \ 239 0 /* Invalid value */) 240 241 static uint32_t max_thread_ids_for_cache(X86CPUTopoInfo *topo_info, 242 enum CpuTopologyLevel share_level) 243 { 244 uint32_t num_ids = 0; 245 246 switch (share_level) { 247 case CPU_TOPOLOGY_LEVEL_CORE: 248 num_ids = 1 << apicid_core_offset(topo_info); 249 break; 250 case CPU_TOPOLOGY_LEVEL_DIE: 251 num_ids = 1 << apicid_die_offset(topo_info); 252 break; 253 case CPU_TOPOLOGY_LEVEL_SOCKET: 254 num_ids = 1 << apicid_pkg_offset(topo_info); 255 break; 256 default: 257 /* 258 * Currently there is no use case for THREAD and MODULE, so use 259 * assert directly to facilitate debugging. 260 */ 261 g_assert_not_reached(); 262 } 263 264 return num_ids - 1; 265 } 266 267 static uint32_t max_core_ids_in_package(X86CPUTopoInfo *topo_info) 268 { 269 uint32_t num_cores = 1 << (apicid_pkg_offset(topo_info) - 270 apicid_core_offset(topo_info)); 271 return num_cores - 1; 272 } 273 274 /* Encode cache info for CPUID[4] */ 275 static void encode_cache_cpuid4(CPUCacheInfo *cache, 276 X86CPUTopoInfo *topo_info, 277 uint32_t *eax, uint32_t *ebx, 278 uint32_t *ecx, uint32_t *edx) 279 { 280 assert(cache->size == cache->line_size * cache->associativity * 281 cache->partitions * cache->sets); 282 283 *eax = CACHE_TYPE(cache->type) | 284 CACHE_LEVEL(cache->level) | 285 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) | 286 (max_core_ids_in_package(topo_info) << 26) | 287 (max_thread_ids_for_cache(topo_info, cache->share_level) << 14); 288 289 assert(cache->line_size > 0); 290 assert(cache->partitions > 0); 291 assert(cache->associativity > 0); 292 /* We don't implement fully-associative caches */ 293 assert(cache->associativity < cache->sets); 294 *ebx = (cache->line_size - 1) | 295 ((cache->partitions - 1) << 12) | 296 ((cache->associativity - 1) << 22); 297 298 assert(cache->sets > 0); 299 *ecx = cache->sets - 1; 300 301 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) | 302 (cache->inclusive ? CACHE_INCLUSIVE : 0) | 303 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); 304 } 305 306 static uint32_t num_threads_by_topo_level(X86CPUTopoInfo *topo_info, 307 enum CpuTopologyLevel topo_level) 308 { 309 switch (topo_level) { 310 case CPU_TOPOLOGY_LEVEL_THREAD: 311 return 1; 312 case CPU_TOPOLOGY_LEVEL_CORE: 313 return topo_info->threads_per_core; 314 case CPU_TOPOLOGY_LEVEL_MODULE: 315 return x86_threads_per_module(topo_info); 316 case CPU_TOPOLOGY_LEVEL_DIE: 317 return x86_threads_per_die(topo_info); 318 case CPU_TOPOLOGY_LEVEL_SOCKET: 319 return x86_threads_per_pkg(topo_info); 320 default: 321 g_assert_not_reached(); 322 } 323 return 0; 324 } 325 326 static uint32_t apicid_offset_by_topo_level(X86CPUTopoInfo *topo_info, 327 enum CpuTopologyLevel topo_level) 328 { 329 switch (topo_level) { 330 case CPU_TOPOLOGY_LEVEL_THREAD: 331 return 0; 332 case CPU_TOPOLOGY_LEVEL_CORE: 333 return apicid_core_offset(topo_info); 334 case CPU_TOPOLOGY_LEVEL_MODULE: 335 return apicid_module_offset(topo_info); 336 case CPU_TOPOLOGY_LEVEL_DIE: 337 return apicid_die_offset(topo_info); 338 case CPU_TOPOLOGY_LEVEL_SOCKET: 339 return apicid_pkg_offset(topo_info); 340 default: 341 g_assert_not_reached(); 342 } 343 return 0; 344 } 345 346 static uint32_t cpuid1f_topo_type(enum CpuTopologyLevel topo_level) 347 { 348 switch (topo_level) { 349 case CPU_TOPOLOGY_LEVEL_INVALID: 350 return CPUID_1F_ECX_TOPO_LEVEL_INVALID; 351 case CPU_TOPOLOGY_LEVEL_THREAD: 352 return CPUID_1F_ECX_TOPO_LEVEL_SMT; 353 case CPU_TOPOLOGY_LEVEL_CORE: 354 return CPUID_1F_ECX_TOPO_LEVEL_CORE; 355 case CPU_TOPOLOGY_LEVEL_MODULE: 356 return CPUID_1F_ECX_TOPO_LEVEL_MODULE; 357 case CPU_TOPOLOGY_LEVEL_DIE: 358 return CPUID_1F_ECX_TOPO_LEVEL_DIE; 359 default: 360 /* Other types are not supported in QEMU. */ 361 g_assert_not_reached(); 362 } 363 return 0; 364 } 365 366 static void encode_topo_cpuid1f(CPUX86State *env, uint32_t count, 367 X86CPUTopoInfo *topo_info, 368 uint32_t *eax, uint32_t *ebx, 369 uint32_t *ecx, uint32_t *edx) 370 { 371 X86CPU *cpu = env_archcpu(env); 372 unsigned long level, base_level, next_level; 373 uint32_t num_threads_next_level, offset_next_level; 374 375 assert(count <= CPU_TOPOLOGY_LEVEL_SOCKET); 376 377 /* 378 * Find the No.(count + 1) topology level in avail_cpu_topo bitmap. 379 * The search starts from bit 0 (CPU_TOPOLOGY_LEVEL_THREAD). 380 */ 381 level = CPU_TOPOLOGY_LEVEL_THREAD; 382 base_level = level; 383 for (int i = 0; i <= count; i++) { 384 level = find_next_bit(env->avail_cpu_topo, 385 CPU_TOPOLOGY_LEVEL_SOCKET, 386 base_level); 387 388 /* 389 * CPUID[0x1f] doesn't explicitly encode the package level, 390 * and it just encodes the invalid level (all fields are 0) 391 * into the last subleaf of 0x1f. 392 */ 393 if (level == CPU_TOPOLOGY_LEVEL_SOCKET) { 394 level = CPU_TOPOLOGY_LEVEL_INVALID; 395 break; 396 } 397 /* Search the next level. */ 398 base_level = level + 1; 399 } 400 401 if (level == CPU_TOPOLOGY_LEVEL_INVALID) { 402 num_threads_next_level = 0; 403 offset_next_level = 0; 404 } else { 405 next_level = find_next_bit(env->avail_cpu_topo, 406 CPU_TOPOLOGY_LEVEL_SOCKET, 407 level + 1); 408 num_threads_next_level = num_threads_by_topo_level(topo_info, 409 next_level); 410 offset_next_level = apicid_offset_by_topo_level(topo_info, 411 next_level); 412 } 413 414 *eax = offset_next_level; 415 /* The count (bits 15-00) doesn't need to be reliable. */ 416 *ebx = num_threads_next_level & 0xffff; 417 *ecx = (count & 0xff) | (cpuid1f_topo_type(level) << 8); 418 *edx = cpu->apic_id; 419 420 assert(!(*eax & ~0x1f)); 421 } 422 423 /* Encode cache info for CPUID[0x80000005].ECX or CPUID[0x80000005].EDX */ 424 static uint32_t encode_cache_cpuid80000005(CPUCacheInfo *cache) 425 { 426 assert(cache->size % 1024 == 0); 427 assert(cache->lines_per_tag > 0); 428 assert(cache->associativity > 0); 429 assert(cache->line_size > 0); 430 return ((cache->size / 1024) << 24) | (cache->associativity << 16) | 431 (cache->lines_per_tag << 8) | (cache->line_size); 432 } 433 434 #define ASSOC_FULL 0xFF 435 436 /* AMD associativity encoding used on CPUID Leaf 0x80000006: */ 437 #define AMD_ENC_ASSOC(a) (a <= 1 ? a : \ 438 a == 2 ? 0x2 : \ 439 a == 4 ? 0x4 : \ 440 a == 8 ? 0x6 : \ 441 a == 16 ? 0x8 : \ 442 a == 32 ? 0xA : \ 443 a == 48 ? 0xB : \ 444 a == 64 ? 0xC : \ 445 a == 96 ? 0xD : \ 446 a == 128 ? 0xE : \ 447 a == ASSOC_FULL ? 0xF : \ 448 0 /* invalid value */) 449 450 /* 451 * Encode cache info for CPUID[0x80000006].ECX and CPUID[0x80000006].EDX 452 * @l3 can be NULL. 453 */ 454 static void encode_cache_cpuid80000006(CPUCacheInfo *l2, 455 CPUCacheInfo *l3, 456 uint32_t *ecx, uint32_t *edx) 457 { 458 assert(l2->size % 1024 == 0); 459 assert(l2->associativity > 0); 460 assert(l2->lines_per_tag > 0); 461 assert(l2->line_size > 0); 462 *ecx = ((l2->size / 1024) << 16) | 463 (AMD_ENC_ASSOC(l2->associativity) << 12) | 464 (l2->lines_per_tag << 8) | (l2->line_size); 465 466 if (l3) { 467 assert(l3->size % (512 * 1024) == 0); 468 assert(l3->associativity > 0); 469 assert(l3->lines_per_tag > 0); 470 assert(l3->line_size > 0); 471 *edx = ((l3->size / (512 * 1024)) << 18) | 472 (AMD_ENC_ASSOC(l3->associativity) << 12) | 473 (l3->lines_per_tag << 8) | (l3->line_size); 474 } else { 475 *edx = 0; 476 } 477 } 478 479 /* Encode cache info for CPUID[8000001D] */ 480 static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, 481 X86CPUTopoInfo *topo_info, 482 uint32_t *eax, uint32_t *ebx, 483 uint32_t *ecx, uint32_t *edx) 484 { 485 assert(cache->size == cache->line_size * cache->associativity * 486 cache->partitions * cache->sets); 487 488 *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) | 489 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0); 490 *eax |= max_thread_ids_for_cache(topo_info, cache->share_level) << 14; 491 492 assert(cache->line_size > 0); 493 assert(cache->partitions > 0); 494 assert(cache->associativity > 0); 495 /* We don't implement fully-associative caches */ 496 assert(cache->associativity < cache->sets); 497 *ebx = (cache->line_size - 1) | 498 ((cache->partitions - 1) << 12) | 499 ((cache->associativity - 1) << 22); 500 501 assert(cache->sets > 0); 502 *ecx = cache->sets - 1; 503 504 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) | 505 (cache->inclusive ? CACHE_INCLUSIVE : 0) | 506 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); 507 } 508 509 /* Encode cache info for CPUID[8000001E] */ 510 static void encode_topo_cpuid8000001e(X86CPU *cpu, X86CPUTopoInfo *topo_info, 511 uint32_t *eax, uint32_t *ebx, 512 uint32_t *ecx, uint32_t *edx) 513 { 514 X86CPUTopoIDs topo_ids; 515 516 x86_topo_ids_from_apicid(cpu->apic_id, topo_info, &topo_ids); 517 518 *eax = cpu->apic_id; 519 520 /* 521 * CPUID_Fn8000001E_EBX [Core Identifiers] (CoreId) 522 * Read-only. Reset: 0000_XXXXh. 523 * See Core::X86::Cpuid::ExtApicId. 524 * Core::X86::Cpuid::CoreId_lthree[1:0]_core[3:0]_thread[1:0]; 525 * Bits Description 526 * 31:16 Reserved. 527 * 15:8 ThreadsPerCore: threads per core. Read-only. Reset: XXh. 528 * The number of threads per core is ThreadsPerCore+1. 529 * 7:0 CoreId: core ID. Read-only. Reset: XXh. 530 * 531 * NOTE: CoreId is already part of apic_id. Just use it. We can 532 * use all the 8 bits to represent the core_id here. 533 */ 534 *ebx = ((topo_info->threads_per_core - 1) << 8) | (topo_ids.core_id & 0xFF); 535 536 /* 537 * CPUID_Fn8000001E_ECX [Node Identifiers] (NodeId) 538 * Read-only. Reset: 0000_0XXXh. 539 * Core::X86::Cpuid::NodeId_lthree[1:0]_core[3:0]_thread[1:0]; 540 * Bits Description 541 * 31:11 Reserved. 542 * 10:8 NodesPerProcessor: Node per processor. Read-only. Reset: XXXb. 543 * ValidValues: 544 * Value Description 545 * 0h 1 node per processor. 546 * 7h-1h Reserved. 547 * 7:0 NodeId: Node ID. Read-only. Reset: XXh. 548 * 549 * NOTE: Hardware reserves 3 bits for number of nodes per processor. 550 * But users can create more nodes than the actual hardware can 551 * support. To genaralize we can use all the upper 8 bits for nodes. 552 * NodeId is combination of node and socket_id which is already decoded 553 * in apic_id. Just use it by shifting. 554 */ 555 if (cpu->legacy_multi_node) { 556 *ecx = ((topo_info->dies_per_pkg - 1) << 8) | 557 ((cpu->apic_id >> apicid_die_offset(topo_info)) & 0xFF); 558 } else { 559 *ecx = (cpu->apic_id >> apicid_pkg_offset(topo_info)) & 0xFF; 560 } 561 562 *edx = 0; 563 } 564 565 /* 566 * Definitions of the hardcoded cache entries we expose: 567 * These are legacy cache values. If there is a need to change any 568 * of these values please use builtin_x86_defs 569 */ 570 571 /* L1 data cache: */ 572 static CPUCacheInfo legacy_l1d_cache = { 573 .type = DATA_CACHE, 574 .level = 1, 575 .size = 32 * KiB, 576 .self_init = 1, 577 .line_size = 64, 578 .associativity = 8, 579 .sets = 64, 580 .partitions = 1, 581 .no_invd_sharing = true, 582 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 583 }; 584 585 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ 586 static CPUCacheInfo legacy_l1d_cache_amd = { 587 .type = DATA_CACHE, 588 .level = 1, 589 .size = 64 * KiB, 590 .self_init = 1, 591 .line_size = 64, 592 .associativity = 2, 593 .sets = 512, 594 .partitions = 1, 595 .lines_per_tag = 1, 596 .no_invd_sharing = true, 597 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 598 }; 599 600 /* L1 instruction cache: */ 601 static CPUCacheInfo legacy_l1i_cache = { 602 .type = INSTRUCTION_CACHE, 603 .level = 1, 604 .size = 32 * KiB, 605 .self_init = 1, 606 .line_size = 64, 607 .associativity = 8, 608 .sets = 64, 609 .partitions = 1, 610 .no_invd_sharing = true, 611 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 612 }; 613 614 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ 615 static CPUCacheInfo legacy_l1i_cache_amd = { 616 .type = INSTRUCTION_CACHE, 617 .level = 1, 618 .size = 64 * KiB, 619 .self_init = 1, 620 .line_size = 64, 621 .associativity = 2, 622 .sets = 512, 623 .partitions = 1, 624 .lines_per_tag = 1, 625 .no_invd_sharing = true, 626 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 627 }; 628 629 /* Level 2 unified cache: */ 630 static CPUCacheInfo legacy_l2_cache = { 631 .type = UNIFIED_CACHE, 632 .level = 2, 633 .size = 4 * MiB, 634 .self_init = 1, 635 .line_size = 64, 636 .associativity = 16, 637 .sets = 4096, 638 .partitions = 1, 639 .no_invd_sharing = true, 640 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 641 }; 642 643 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */ 644 static CPUCacheInfo legacy_l2_cache_cpuid2 = { 645 .type = UNIFIED_CACHE, 646 .level = 2, 647 .size = 2 * MiB, 648 .line_size = 64, 649 .associativity = 8, 650 .share_level = CPU_TOPOLOGY_LEVEL_INVALID, 651 }; 652 653 654 /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */ 655 static CPUCacheInfo legacy_l2_cache_amd = { 656 .type = UNIFIED_CACHE, 657 .level = 2, 658 .size = 512 * KiB, 659 .line_size = 64, 660 .lines_per_tag = 1, 661 .associativity = 16, 662 .sets = 512, 663 .partitions = 1, 664 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 665 }; 666 667 /* Level 3 unified cache: */ 668 static CPUCacheInfo legacy_l3_cache = { 669 .type = UNIFIED_CACHE, 670 .level = 3, 671 .size = 16 * MiB, 672 .line_size = 64, 673 .associativity = 16, 674 .sets = 16384, 675 .partitions = 1, 676 .lines_per_tag = 1, 677 .self_init = true, 678 .inclusive = true, 679 .complex_indexing = true, 680 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 681 }; 682 683 /* TLB definitions: */ 684 685 #define L1_DTLB_2M_ASSOC 1 686 #define L1_DTLB_2M_ENTRIES 255 687 #define L1_DTLB_4K_ASSOC 1 688 #define L1_DTLB_4K_ENTRIES 255 689 690 #define L1_ITLB_2M_ASSOC 1 691 #define L1_ITLB_2M_ENTRIES 255 692 #define L1_ITLB_4K_ASSOC 1 693 #define L1_ITLB_4K_ENTRIES 255 694 695 #define L2_DTLB_2M_ASSOC 0 /* disabled */ 696 #define L2_DTLB_2M_ENTRIES 0 /* disabled */ 697 #define L2_DTLB_4K_ASSOC 4 698 #define L2_DTLB_4K_ENTRIES 512 699 700 #define L2_ITLB_2M_ASSOC 0 /* disabled */ 701 #define L2_ITLB_2M_ENTRIES 0 /* disabled */ 702 #define L2_ITLB_4K_ASSOC 4 703 #define L2_ITLB_4K_ENTRIES 512 704 705 /* CPUID Leaf 0x14 constants: */ 706 #define INTEL_PT_MAX_SUBLEAF 0x1 707 /* 708 * bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MATCH 709 * MSR can be accessed; 710 * bit[01]: Support Configurable PSB and Cycle-Accurate Mode; 711 * bit[02]: Support IP Filtering, TraceStop filtering, and preservation 712 * of Intel PT MSRs across warm reset; 713 * bit[03]: Support MTC timing packet and suppression of COFI-based packets; 714 */ 715 #define INTEL_PT_MINIMAL_EBX 0xf 716 /* 717 * bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 and 718 * IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be 719 * accessed; 720 * bit[01]: ToPA tables can hold any number of output entries, up to the 721 * maximum allowed by the MaskOrTableOffset field of 722 * IA32_RTIT_OUTPUT_MASK_PTRS; 723 * bit[02]: Support Single-Range Output scheme; 724 */ 725 #define INTEL_PT_MINIMAL_ECX 0x7 726 /* generated packets which contain IP payloads have LIP values */ 727 #define INTEL_PT_IP_LIP (1 << 31) 728 #define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */ 729 #define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3 730 #define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */ 731 #define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */ 732 #define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */ 733 734 /* CPUID Leaf 0x1D constants: */ 735 #define INTEL_AMX_TILE_MAX_SUBLEAF 0x1 736 #define INTEL_AMX_TOTAL_TILE_BYTES 0x2000 737 #define INTEL_AMX_BYTES_PER_TILE 0x400 738 #define INTEL_AMX_BYTES_PER_ROW 0x40 739 #define INTEL_AMX_TILE_MAX_NAMES 0x8 740 #define INTEL_AMX_TILE_MAX_ROWS 0x10 741 742 /* CPUID Leaf 0x1E constants: */ 743 #define INTEL_AMX_TMUL_MAX_K 0x10 744 #define INTEL_AMX_TMUL_MAX_N 0x40 745 746 void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1, 747 uint32_t vendor2, uint32_t vendor3) 748 { 749 int i; 750 for (i = 0; i < 4; i++) { 751 dst[i] = vendor1 >> (8 * i); 752 dst[i + 4] = vendor2 >> (8 * i); 753 dst[i + 8] = vendor3 >> (8 * i); 754 } 755 dst[CPUID_VENDOR_SZ] = '\0'; 756 } 757 758 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE) 759 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \ 760 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC) 761 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \ 762 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ 763 CPUID_PSE36 | CPUID_FXSR) 764 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE) 765 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \ 766 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \ 767 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \ 768 CPUID_PAE | CPUID_SEP | CPUID_APIC) 769 770 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \ 771 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \ 772 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ 773 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \ 774 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE) 775 /* partly implemented: 776 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */ 777 /* missing: 778 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */ 779 780 /* 781 * Kernel-only features that can be shown to usermode programs even if 782 * they aren't actually supported by TCG, because qemu-user only runs 783 * in CPL=3; remove them if they are ever implemented for system emulation. 784 */ 785 #if defined CONFIG_USER_ONLY 786 #define CPUID_EXT_KERNEL_FEATURES \ 787 (CPUID_EXT_PCID | CPUID_EXT_TSC_DEADLINE_TIMER) 788 #else 789 #define CPUID_EXT_KERNEL_FEATURES 0 790 #endif 791 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \ 792 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \ 793 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \ 794 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \ 795 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR | \ 796 CPUID_EXT_RDRAND | CPUID_EXT_AVX | CPUID_EXT_F16C | \ 797 CPUID_EXT_FMA | CPUID_EXT_X2APIC | CPUID_EXT_KERNEL_FEATURES) 798 /* missing: 799 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX, 800 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, 801 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA, 802 CPUID_EXT_TSC_DEADLINE_TIMER 803 */ 804 805 #ifdef TARGET_X86_64 806 #define TCG_EXT2_X86_64_FEATURES CPUID_EXT2_LM 807 #else 808 #define TCG_EXT2_X86_64_FEATURES 0 809 #endif 810 811 /* 812 * CPUID_*_KERNEL_FEATURES denotes bits and features that are not usable 813 * in usermode or by 32-bit programs. Those are added to supported 814 * TCG features unconditionally in user-mode emulation mode. This may 815 * indeed seem strange or incorrect, but it works because code running 816 * under usermode emulation cannot access them. 817 * 818 * Even for long mode, qemu-i386 is not running "a userspace program on a 819 * 32-bit CPU"; it's running "a userspace program with a 32-bit code segment" 820 * and therefore using the 32-bit ABI; the CPU itself might be 64-bit 821 * but again the difference is only visible in kernel mode. 822 */ 823 #if defined CONFIG_LINUX_USER 824 #define CPUID_EXT2_KERNEL_FEATURES (CPUID_EXT2_LM | CPUID_EXT2_FFXSR) 825 #elif defined CONFIG_USER_ONLY 826 /* FIXME: Long mode not yet supported for i386 bsd-user */ 827 #define CPUID_EXT2_KERNEL_FEATURES CPUID_EXT2_FFXSR 828 #else 829 #define CPUID_EXT2_KERNEL_FEATURES 0 830 #endif 831 832 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \ 833 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \ 834 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \ 835 CPUID_EXT2_SYSCALL | TCG_EXT2_X86_64_FEATURES | \ 836 CPUID_EXT2_KERNEL_FEATURES) 837 838 #if defined CONFIG_USER_ONLY 839 #define CPUID_EXT3_KERNEL_FEATURES CPUID_EXT3_OSVW 840 #else 841 #define CPUID_EXT3_KERNEL_FEATURES 0 842 #endif 843 844 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \ 845 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A | \ 846 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_KERNEL_FEATURES) 847 848 #define TCG_EXT4_FEATURES 0 849 850 #if defined CONFIG_USER_ONLY 851 #define CPUID_SVM_KERNEL_FEATURES (CPUID_SVM_NRIPSAVE | CPUID_SVM_VNMI) 852 #else 853 #define CPUID_SVM_KERNEL_FEATURES 0 854 #endif 855 #define TCG_SVM_FEATURES (CPUID_SVM_NPT | CPUID_SVM_VGIF | \ 856 CPUID_SVM_SVME_ADDR_CHK | CPUID_SVM_KERNEL_FEATURES) 857 858 #define TCG_KVM_FEATURES 0 859 860 #if defined CONFIG_USER_ONLY 861 #define CPUID_7_0_EBX_KERNEL_FEATURES CPUID_7_0_EBX_INVPCID 862 #else 863 #define CPUID_7_0_EBX_KERNEL_FEATURES 0 864 #endif 865 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \ 866 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \ 867 CPUID_7_0_EBX_CLFLUSHOPT | \ 868 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \ 869 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_RDSEED | \ 870 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_KERNEL_FEATURES) 871 /* missing: 872 CPUID_7_0_EBX_HLE 873 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM */ 874 875 #if !defined CONFIG_USER_ONLY || defined CONFIG_LINUX 876 #define TCG_7_0_ECX_RDPID CPUID_7_0_ECX_RDPID 877 #else 878 #define TCG_7_0_ECX_RDPID 0 879 #endif 880 #define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | \ 881 /* CPUID_7_0_ECX_OSPKE is dynamic */ \ 882 CPUID_7_0_ECX_LA57 | CPUID_7_0_ECX_PKS | CPUID_7_0_ECX_VAES | \ 883 TCG_7_0_ECX_RDPID) 884 885 #if defined CONFIG_USER_ONLY 886 #define CPUID_7_0_EDX_KERNEL_FEATURES (CPUID_7_0_EDX_SPEC_CTRL | \ 887 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD) 888 #else 889 #define CPUID_7_0_EDX_KERNEL_FEATURES 0 890 #endif 891 #define TCG_7_0_EDX_FEATURES (CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_KERNEL_FEATURES) 892 893 #define TCG_7_1_EAX_FEATURES (CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | \ 894 CPUID_7_1_EAX_FSRC | CPUID_7_1_EAX_CMPCCXADD) 895 #define TCG_7_1_EDX_FEATURES 0 896 #define TCG_7_2_EDX_FEATURES 0 897 #define TCG_APM_FEATURES 0 898 #define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT 899 #define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1) 900 /* missing: 901 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */ 902 #define TCG_14_0_ECX_FEATURES 0 903 #define TCG_SGX_12_0_EAX_FEATURES 0 904 #define TCG_SGX_12_0_EBX_FEATURES 0 905 #define TCG_SGX_12_1_EAX_FEATURES 0 906 #define TCG_24_0_EBX_FEATURES 0 907 908 #if defined CONFIG_USER_ONLY 909 #define CPUID_8000_0008_EBX_KERNEL_FEATURES (CPUID_8000_0008_EBX_IBPB | \ 910 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | \ 911 CPUID_8000_0008_EBX_STIBP_ALWAYS_ON | CPUID_8000_0008_EBX_AMD_SSBD | \ 912 CPUID_8000_0008_EBX_AMD_PSFD) 913 #else 914 #define CPUID_8000_0008_EBX_KERNEL_FEATURES 0 915 #endif 916 917 #define TCG_8000_0008_EBX (CPUID_8000_0008_EBX_XSAVEERPTR | \ 918 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_KERNEL_FEATURES) 919 920 FeatureWordInfo feature_word_info[FEATURE_WORDS] = { 921 [FEAT_1_EDX] = { 922 .type = CPUID_FEATURE_WORD, 923 .feat_names = { 924 "fpu", "vme", "de", "pse", 925 "tsc", "msr", "pae", "mce", 926 "cx8", "apic", NULL, "sep", 927 "mtrr", "pge", "mca", "cmov", 928 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */, 929 NULL, "ds" /* Intel dts */, "acpi", "mmx", 930 "fxsr", "sse", "sse2", "ss", 931 "ht" /* Intel htt */, "tm", "ia64", "pbe", 932 }, 933 .cpuid = {.eax = 1, .reg = R_EDX, }, 934 .tcg_features = TCG_FEATURES, 935 .no_autoenable_flags = CPUID_HT, 936 }, 937 [FEAT_1_ECX] = { 938 .type = CPUID_FEATURE_WORD, 939 .feat_names = { 940 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor", 941 "ds-cpl", "vmx", "smx", "est", 942 "tm2", "ssse3", "cid", NULL, 943 "fma", "cx16", "xtpr", "pdcm", 944 NULL, "pcid", "dca", "sse4.1", 945 "sse4.2", "x2apic", "movbe", "popcnt", 946 "tsc-deadline", "aes", "xsave", NULL /* osxsave */, 947 "avx", "f16c", "rdrand", "hypervisor", 948 }, 949 .cpuid = { .eax = 1, .reg = R_ECX, }, 950 .tcg_features = TCG_EXT_FEATURES, 951 }, 952 /* Feature names that are already defined on feature_name[] but 953 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their 954 * names on feat_names below. They are copied automatically 955 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD. 956 */ 957 [FEAT_8000_0001_EDX] = { 958 .type = CPUID_FEATURE_WORD, 959 .feat_names = { 960 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */, 961 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */, 962 NULL /* cx8 */, NULL /* apic */, NULL, "syscall", 963 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */, 964 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */, 965 "nx", NULL, "mmxext", NULL /* mmx */, 966 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp", 967 NULL, "lm", "3dnowext", "3dnow", 968 }, 969 .cpuid = { .eax = 0x80000001, .reg = R_EDX, }, 970 .tcg_features = TCG_EXT2_FEATURES, 971 }, 972 [FEAT_8000_0001_ECX] = { 973 .type = CPUID_FEATURE_WORD, 974 .feat_names = { 975 "lahf-lm", "cmp-legacy", "svm", "extapic", 976 "cr8legacy", "abm", "sse4a", "misalignsse", 977 "3dnowprefetch", "osvw", "ibs", "xop", 978 "skinit", "wdt", NULL, "lwp", 979 "fma4", "tce", NULL, "nodeid-msr", 980 NULL, "tbm", "topoext", "perfctr-core", 981 "perfctr-nb", NULL, NULL, NULL, 982 NULL, NULL, NULL, NULL, 983 }, 984 .cpuid = { .eax = 0x80000001, .reg = R_ECX, }, 985 .tcg_features = TCG_EXT3_FEATURES, 986 /* 987 * TOPOEXT is always allowed but can't be enabled blindly by 988 * "-cpu host", as it requires consistent cache topology info 989 * to be provided so it doesn't confuse guests. 990 */ 991 .no_autoenable_flags = CPUID_EXT3_TOPOEXT, 992 }, 993 [FEAT_C000_0001_EDX] = { 994 .type = CPUID_FEATURE_WORD, 995 .feat_names = { 996 NULL, NULL, "xstore", "xstore-en", 997 NULL, NULL, "xcrypt", "xcrypt-en", 998 "ace2", "ace2-en", "phe", "phe-en", 999 "pmm", "pmm-en", NULL, NULL, 1000 NULL, NULL, NULL, NULL, 1001 NULL, NULL, NULL, NULL, 1002 NULL, NULL, NULL, NULL, 1003 NULL, NULL, NULL, NULL, 1004 }, 1005 .cpuid = { .eax = 0xC0000001, .reg = R_EDX, }, 1006 .tcg_features = TCG_EXT4_FEATURES, 1007 }, 1008 [FEAT_KVM] = { 1009 .type = CPUID_FEATURE_WORD, 1010 .feat_names = { 1011 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock", 1012 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt", 1013 NULL, "kvm-pv-tlb-flush", "kvm-asyncpf-vmexit", "kvm-pv-ipi", 1014 "kvm-poll-control", "kvm-pv-sched-yield", "kvm-asyncpf-int", "kvm-msi-ext-dest-id", 1015 NULL, NULL, NULL, NULL, 1016 NULL, NULL, NULL, NULL, 1017 "kvmclock-stable-bit", NULL, NULL, NULL, 1018 NULL, NULL, NULL, NULL, 1019 }, 1020 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EAX, }, 1021 .tcg_features = TCG_KVM_FEATURES, 1022 }, 1023 [FEAT_KVM_HINTS] = { 1024 .type = CPUID_FEATURE_WORD, 1025 .feat_names = { 1026 "kvm-hint-dedicated", NULL, NULL, NULL, 1027 NULL, NULL, NULL, NULL, 1028 NULL, NULL, NULL, NULL, 1029 NULL, NULL, NULL, NULL, 1030 NULL, NULL, NULL, NULL, 1031 NULL, NULL, NULL, NULL, 1032 NULL, NULL, NULL, NULL, 1033 NULL, NULL, NULL, NULL, 1034 }, 1035 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EDX, }, 1036 .tcg_features = TCG_KVM_FEATURES, 1037 /* 1038 * KVM hints aren't auto-enabled by -cpu host, they need to be 1039 * explicitly enabled in the command-line. 1040 */ 1041 .no_autoenable_flags = ~0U, 1042 }, 1043 [FEAT_SVM] = { 1044 .type = CPUID_FEATURE_WORD, 1045 .feat_names = { 1046 "npt", "lbrv", "svm-lock", "nrip-save", 1047 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists", 1048 NULL, NULL, "pause-filter", NULL, 1049 "pfthreshold", "avic", NULL, "v-vmsave-vmload", 1050 "vgif", NULL, NULL, NULL, 1051 NULL, NULL, NULL, NULL, 1052 NULL, "vnmi", NULL, NULL, 1053 "svme-addr-chk", NULL, NULL, NULL, 1054 }, 1055 .cpuid = { .eax = 0x8000000A, .reg = R_EDX, }, 1056 .tcg_features = TCG_SVM_FEATURES, 1057 }, 1058 [FEAT_7_0_EBX] = { 1059 .type = CPUID_FEATURE_WORD, 1060 .feat_names = { 1061 "fsgsbase", "tsc-adjust", "sgx", "bmi1", 1062 "hle", "avx2", "fdp-excptn-only", "smep", 1063 "bmi2", "erms", "invpcid", "rtm", 1064 NULL, "zero-fcs-fds", "mpx", NULL, 1065 "avx512f", "avx512dq", "rdseed", "adx", 1066 "smap", "avx512ifma", "pcommit", "clflushopt", 1067 "clwb", "intel-pt", "avx512pf", "avx512er", 1068 "avx512cd", "sha-ni", "avx512bw", "avx512vl", 1069 }, 1070 .cpuid = { 1071 .eax = 7, 1072 .needs_ecx = true, .ecx = 0, 1073 .reg = R_EBX, 1074 }, 1075 .tcg_features = TCG_7_0_EBX_FEATURES, 1076 }, 1077 [FEAT_7_0_ECX] = { 1078 .type = CPUID_FEATURE_WORD, 1079 .feat_names = { 1080 NULL, "avx512vbmi", "umip", "pku", 1081 NULL /* ospke */, "waitpkg", "avx512vbmi2", NULL, 1082 "gfni", "vaes", "vpclmulqdq", "avx512vnni", 1083 "avx512bitalg", NULL, "avx512-vpopcntdq", NULL, 1084 "la57", NULL, NULL, NULL, 1085 NULL, NULL, "rdpid", NULL, 1086 "bus-lock-detect", "cldemote", NULL, "movdiri", 1087 "movdir64b", NULL, "sgxlc", "pks", 1088 }, 1089 .cpuid = { 1090 .eax = 7, 1091 .needs_ecx = true, .ecx = 0, 1092 .reg = R_ECX, 1093 }, 1094 .tcg_features = TCG_7_0_ECX_FEATURES, 1095 }, 1096 [FEAT_7_0_EDX] = { 1097 .type = CPUID_FEATURE_WORD, 1098 .feat_names = { 1099 NULL, NULL, "avx512-4vnniw", "avx512-4fmaps", 1100 "fsrm", NULL, NULL, NULL, 1101 "avx512-vp2intersect", NULL, "md-clear", NULL, 1102 NULL, NULL, "serialize", NULL, 1103 "tsx-ldtrk", NULL, NULL /* pconfig */, "arch-lbr", 1104 NULL, NULL, "amx-bf16", "avx512-fp16", 1105 "amx-tile", "amx-int8", "spec-ctrl", "stibp", 1106 "flush-l1d", "arch-capabilities", "core-capability", "ssbd", 1107 }, 1108 .cpuid = { 1109 .eax = 7, 1110 .needs_ecx = true, .ecx = 0, 1111 .reg = R_EDX, 1112 }, 1113 .tcg_features = TCG_7_0_EDX_FEATURES, 1114 }, 1115 [FEAT_7_1_EAX] = { 1116 .type = CPUID_FEATURE_WORD, 1117 .feat_names = { 1118 "sha512", "sm3", "sm4", NULL, 1119 "avx-vnni", "avx512-bf16", NULL, "cmpccxadd", 1120 NULL, NULL, "fzrm", "fsrs", 1121 "fsrc", NULL, NULL, NULL, 1122 NULL, "fred", "lkgs", "wrmsrns", 1123 NULL, "amx-fp16", NULL, "avx-ifma", 1124 NULL, NULL, "lam", NULL, 1125 NULL, NULL, NULL, NULL, 1126 }, 1127 .cpuid = { 1128 .eax = 7, 1129 .needs_ecx = true, .ecx = 1, 1130 .reg = R_EAX, 1131 }, 1132 .tcg_features = TCG_7_1_EAX_FEATURES, 1133 }, 1134 [FEAT_7_1_EDX] = { 1135 .type = CPUID_FEATURE_WORD, 1136 .feat_names = { 1137 NULL, NULL, NULL, NULL, 1138 "avx-vnni-int8", "avx-ne-convert", NULL, NULL, 1139 "amx-complex", NULL, "avx-vnni-int16", NULL, 1140 NULL, NULL, "prefetchiti", NULL, 1141 NULL, NULL, NULL, "avx10", 1142 NULL, NULL, NULL, NULL, 1143 NULL, NULL, NULL, NULL, 1144 NULL, NULL, NULL, NULL, 1145 }, 1146 .cpuid = { 1147 .eax = 7, 1148 .needs_ecx = true, .ecx = 1, 1149 .reg = R_EDX, 1150 }, 1151 .tcg_features = TCG_7_1_EDX_FEATURES, 1152 }, 1153 [FEAT_7_2_EDX] = { 1154 .type = CPUID_FEATURE_WORD, 1155 .feat_names = { 1156 "intel-psfd", "ipred-ctrl", "rrsba-ctrl", "ddpd-u", 1157 "bhi-ctrl", "mcdt-no", NULL, NULL, 1158 NULL, NULL, NULL, NULL, 1159 NULL, NULL, NULL, NULL, 1160 NULL, NULL, NULL, NULL, 1161 NULL, NULL, NULL, NULL, 1162 NULL, NULL, NULL, NULL, 1163 NULL, NULL, NULL, NULL, 1164 }, 1165 .cpuid = { 1166 .eax = 7, 1167 .needs_ecx = true, .ecx = 2, 1168 .reg = R_EDX, 1169 }, 1170 .tcg_features = TCG_7_2_EDX_FEATURES, 1171 }, 1172 [FEAT_24_0_EBX] = { 1173 .type = CPUID_FEATURE_WORD, 1174 .feat_names = { 1175 [16] = "avx10-128", 1176 [17] = "avx10-256", 1177 [18] = "avx10-512", 1178 }, 1179 .cpuid = { 1180 .eax = 0x24, 1181 .needs_ecx = true, .ecx = 0, 1182 .reg = R_EBX, 1183 }, 1184 .tcg_features = TCG_24_0_EBX_FEATURES, 1185 }, 1186 [FEAT_8000_0007_EDX] = { 1187 .type = CPUID_FEATURE_WORD, 1188 .feat_names = { 1189 NULL, NULL, NULL, NULL, 1190 NULL, NULL, NULL, NULL, 1191 "invtsc", NULL, NULL, NULL, 1192 NULL, NULL, NULL, NULL, 1193 NULL, NULL, NULL, NULL, 1194 NULL, NULL, NULL, NULL, 1195 NULL, NULL, NULL, NULL, 1196 NULL, NULL, NULL, NULL, 1197 }, 1198 .cpuid = { .eax = 0x80000007, .reg = R_EDX, }, 1199 .tcg_features = TCG_APM_FEATURES, 1200 .unmigratable_flags = CPUID_APM_INVTSC, 1201 }, 1202 [FEAT_8000_0007_EBX] = { 1203 .type = CPUID_FEATURE_WORD, 1204 .feat_names = { 1205 "overflow-recov", "succor", NULL, NULL, 1206 NULL, NULL, NULL, NULL, 1207 NULL, NULL, NULL, NULL, 1208 NULL, NULL, NULL, NULL, 1209 NULL, NULL, NULL, NULL, 1210 NULL, NULL, NULL, NULL, 1211 NULL, NULL, NULL, NULL, 1212 NULL, NULL, NULL, NULL, 1213 }, 1214 .cpuid = { .eax = 0x80000007, .reg = R_EBX, }, 1215 .tcg_features = 0, 1216 .unmigratable_flags = 0, 1217 }, 1218 [FEAT_8000_0008_EBX] = { 1219 .type = CPUID_FEATURE_WORD, 1220 .feat_names = { 1221 "clzero", NULL, "xsaveerptr", NULL, 1222 NULL, NULL, NULL, NULL, 1223 NULL, "wbnoinvd", NULL, NULL, 1224 "ibpb", NULL, "ibrs", "amd-stibp", 1225 NULL, "stibp-always-on", NULL, NULL, 1226 NULL, NULL, NULL, NULL, 1227 "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL, 1228 "amd-psfd", NULL, NULL, NULL, 1229 }, 1230 .cpuid = { .eax = 0x80000008, .reg = R_EBX, }, 1231 .tcg_features = TCG_8000_0008_EBX, 1232 .unmigratable_flags = 0, 1233 }, 1234 [FEAT_8000_0021_EAX] = { 1235 .type = CPUID_FEATURE_WORD, 1236 .feat_names = { 1237 "no-nested-data-bp", NULL, "lfence-always-serializing", NULL, 1238 NULL, NULL, "null-sel-clr-base", NULL, 1239 "auto-ibrs", NULL, NULL, NULL, 1240 NULL, NULL, NULL, NULL, 1241 NULL, NULL, NULL, NULL, 1242 NULL, NULL, NULL, NULL, 1243 "eraps", NULL, NULL, "sbpb", 1244 "ibpb-brtype", "srso-no", "srso-user-kernel-no", NULL, 1245 }, 1246 .cpuid = { .eax = 0x80000021, .reg = R_EAX, }, 1247 .tcg_features = 0, 1248 .unmigratable_flags = 0, 1249 }, 1250 [FEAT_8000_0021_EBX] = { 1251 .type = CPUID_FEATURE_WORD, 1252 .cpuid = { .eax = 0x80000021, .reg = R_EBX, }, 1253 .tcg_features = 0, 1254 .unmigratable_flags = 0, 1255 }, 1256 [FEAT_8000_0022_EAX] = { 1257 .type = CPUID_FEATURE_WORD, 1258 .feat_names = { 1259 "perfmon-v2", NULL, NULL, NULL, 1260 NULL, NULL, NULL, NULL, 1261 NULL, NULL, NULL, NULL, 1262 NULL, NULL, NULL, NULL, 1263 NULL, NULL, NULL, NULL, 1264 NULL, NULL, NULL, NULL, 1265 NULL, NULL, NULL, NULL, 1266 NULL, NULL, NULL, NULL, 1267 }, 1268 .cpuid = { .eax = 0x80000022, .reg = R_EAX, }, 1269 .tcg_features = 0, 1270 .unmigratable_flags = 0, 1271 }, 1272 [FEAT_XSAVE] = { 1273 .type = CPUID_FEATURE_WORD, 1274 .feat_names = { 1275 "xsaveopt", "xsavec", "xgetbv1", "xsaves", 1276 "xfd", NULL, NULL, NULL, 1277 NULL, NULL, NULL, NULL, 1278 NULL, NULL, NULL, NULL, 1279 NULL, NULL, NULL, NULL, 1280 NULL, NULL, NULL, NULL, 1281 NULL, NULL, NULL, NULL, 1282 NULL, NULL, NULL, NULL, 1283 }, 1284 .cpuid = { 1285 .eax = 0xd, 1286 .needs_ecx = true, .ecx = 1, 1287 .reg = R_EAX, 1288 }, 1289 .tcg_features = TCG_XSAVE_FEATURES, 1290 }, 1291 [FEAT_XSAVE_XSS_LO] = { 1292 .type = CPUID_FEATURE_WORD, 1293 .feat_names = { 1294 NULL, NULL, NULL, NULL, 1295 NULL, NULL, NULL, NULL, 1296 NULL, NULL, NULL, NULL, 1297 NULL, NULL, NULL, NULL, 1298 NULL, NULL, NULL, NULL, 1299 NULL, NULL, NULL, NULL, 1300 NULL, NULL, NULL, NULL, 1301 NULL, NULL, NULL, NULL, 1302 }, 1303 .cpuid = { 1304 .eax = 0xD, 1305 .needs_ecx = true, 1306 .ecx = 1, 1307 .reg = R_ECX, 1308 }, 1309 }, 1310 [FEAT_XSAVE_XSS_HI] = { 1311 .type = CPUID_FEATURE_WORD, 1312 .cpuid = { 1313 .eax = 0xD, 1314 .needs_ecx = true, 1315 .ecx = 1, 1316 .reg = R_EDX 1317 }, 1318 }, 1319 [FEAT_6_EAX] = { 1320 .type = CPUID_FEATURE_WORD, 1321 .feat_names = { 1322 NULL, NULL, "arat", NULL, 1323 NULL, NULL, NULL, NULL, 1324 NULL, NULL, NULL, NULL, 1325 NULL, NULL, NULL, NULL, 1326 NULL, NULL, NULL, NULL, 1327 NULL, NULL, NULL, NULL, 1328 NULL, NULL, NULL, NULL, 1329 NULL, NULL, NULL, NULL, 1330 }, 1331 .cpuid = { .eax = 6, .reg = R_EAX, }, 1332 .tcg_features = TCG_6_EAX_FEATURES, 1333 }, 1334 [FEAT_XSAVE_XCR0_LO] = { 1335 .type = CPUID_FEATURE_WORD, 1336 .cpuid = { 1337 .eax = 0xD, 1338 .needs_ecx = true, .ecx = 0, 1339 .reg = R_EAX, 1340 }, 1341 .tcg_features = XSTATE_FP_MASK | XSTATE_SSE_MASK | 1342 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK | 1343 XSTATE_PKRU_MASK, 1344 .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK | 1345 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK | 1346 XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK | 1347 XSTATE_PKRU_MASK, 1348 }, 1349 [FEAT_XSAVE_XCR0_HI] = { 1350 .type = CPUID_FEATURE_WORD, 1351 .cpuid = { 1352 .eax = 0xD, 1353 .needs_ecx = true, .ecx = 0, 1354 .reg = R_EDX, 1355 }, 1356 .tcg_features = 0U, 1357 }, 1358 /*Below are MSR exposed features*/ 1359 [FEAT_ARCH_CAPABILITIES] = { 1360 .type = MSR_FEATURE_WORD, 1361 .feat_names = { 1362 "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry", 1363 "ssb-no", "mds-no", "pschange-mc-no", "tsx-ctrl", 1364 "taa-no", NULL, NULL, NULL, 1365 NULL, "sbdr-ssdp-no", "fbsdp-no", "psdp-no", 1366 NULL, "fb-clear", NULL, NULL, 1367 NULL, NULL, NULL, NULL, 1368 "pbrsb-no", NULL, "gds-no", "rfds-no", 1369 "rfds-clear", NULL, NULL, NULL, 1370 }, 1371 .msr = { 1372 .index = MSR_IA32_ARCH_CAPABILITIES, 1373 }, 1374 /* 1375 * FEAT_ARCH_CAPABILITIES only affects a read-only MSR, which 1376 * cannot be read from user mode. Therefore, it has no impact 1377 > on any user-mode operation, and warnings about unsupported 1378 * features do not matter. 1379 */ 1380 .tcg_features = ~0U, 1381 }, 1382 [FEAT_CORE_CAPABILITY] = { 1383 .type = MSR_FEATURE_WORD, 1384 .feat_names = { 1385 NULL, NULL, NULL, NULL, 1386 NULL, "split-lock-detect", NULL, NULL, 1387 NULL, NULL, NULL, NULL, 1388 NULL, NULL, NULL, NULL, 1389 NULL, NULL, NULL, NULL, 1390 NULL, NULL, NULL, NULL, 1391 NULL, NULL, NULL, NULL, 1392 NULL, NULL, NULL, NULL, 1393 }, 1394 .msr = { 1395 .index = MSR_IA32_CORE_CAPABILITY, 1396 }, 1397 }, 1398 [FEAT_PERF_CAPABILITIES] = { 1399 .type = MSR_FEATURE_WORD, 1400 .feat_names = { 1401 NULL, NULL, NULL, NULL, 1402 NULL, NULL, NULL, NULL, 1403 NULL, NULL, NULL, NULL, 1404 NULL, "full-width-write", NULL, NULL, 1405 NULL, NULL, NULL, NULL, 1406 NULL, NULL, NULL, NULL, 1407 NULL, NULL, NULL, NULL, 1408 NULL, NULL, NULL, NULL, 1409 }, 1410 .msr = { 1411 .index = MSR_IA32_PERF_CAPABILITIES, 1412 }, 1413 }, 1414 1415 [FEAT_VMX_PROCBASED_CTLS] = { 1416 .type = MSR_FEATURE_WORD, 1417 .feat_names = { 1418 NULL, NULL, "vmx-vintr-pending", "vmx-tsc-offset", 1419 NULL, NULL, NULL, "vmx-hlt-exit", 1420 NULL, "vmx-invlpg-exit", "vmx-mwait-exit", "vmx-rdpmc-exit", 1421 "vmx-rdtsc-exit", NULL, NULL, "vmx-cr3-load-noexit", 1422 "vmx-cr3-store-noexit", NULL, NULL, "vmx-cr8-load-exit", 1423 "vmx-cr8-store-exit", "vmx-flexpriority", "vmx-vnmi-pending", "vmx-movdr-exit", 1424 "vmx-io-exit", "vmx-io-bitmap", NULL, "vmx-mtf", 1425 "vmx-msr-bitmap", "vmx-monitor-exit", "vmx-pause-exit", "vmx-secondary-ctls", 1426 }, 1427 .msr = { 1428 .index = MSR_IA32_VMX_TRUE_PROCBASED_CTLS, 1429 } 1430 }, 1431 1432 [FEAT_VMX_SECONDARY_CTLS] = { 1433 .type = MSR_FEATURE_WORD, 1434 .feat_names = { 1435 "vmx-apicv-xapic", "vmx-ept", "vmx-desc-exit", "vmx-rdtscp-exit", 1436 "vmx-apicv-x2apic", "vmx-vpid", "vmx-wbinvd-exit", "vmx-unrestricted-guest", 1437 "vmx-apicv-register", "vmx-apicv-vid", "vmx-ple", "vmx-rdrand-exit", 1438 "vmx-invpcid-exit", "vmx-vmfunc", "vmx-shadow-vmcs", "vmx-encls-exit", 1439 "vmx-rdseed-exit", "vmx-pml", NULL, NULL, 1440 "vmx-xsaves", NULL, NULL, NULL, 1441 NULL, "vmx-tsc-scaling", "vmx-enable-user-wait-pause", NULL, 1442 NULL, NULL, NULL, NULL, 1443 }, 1444 .msr = { 1445 .index = MSR_IA32_VMX_PROCBASED_CTLS2, 1446 } 1447 }, 1448 1449 [FEAT_VMX_PINBASED_CTLS] = { 1450 .type = MSR_FEATURE_WORD, 1451 .feat_names = { 1452 "vmx-intr-exit", NULL, NULL, "vmx-nmi-exit", 1453 NULL, "vmx-vnmi", "vmx-preemption-timer", "vmx-posted-intr", 1454 NULL, NULL, NULL, NULL, 1455 NULL, NULL, NULL, NULL, 1456 NULL, NULL, NULL, NULL, 1457 NULL, NULL, NULL, NULL, 1458 NULL, NULL, NULL, NULL, 1459 NULL, NULL, NULL, NULL, 1460 }, 1461 .msr = { 1462 .index = MSR_IA32_VMX_TRUE_PINBASED_CTLS, 1463 } 1464 }, 1465 1466 [FEAT_VMX_EXIT_CTLS] = { 1467 .type = MSR_FEATURE_WORD, 1468 /* 1469 * VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE is copied from 1470 * the LM CPUID bit. 1471 */ 1472 .feat_names = { 1473 NULL, NULL, "vmx-exit-nosave-debugctl", NULL, 1474 NULL, NULL, NULL, NULL, 1475 NULL, NULL /* vmx-exit-host-addr-space-size */, NULL, NULL, 1476 "vmx-exit-load-perf-global-ctrl", NULL, NULL, "vmx-exit-ack-intr", 1477 NULL, NULL, "vmx-exit-save-pat", "vmx-exit-load-pat", 1478 "vmx-exit-save-efer", "vmx-exit-load-efer", 1479 "vmx-exit-save-preemption-timer", "vmx-exit-clear-bndcfgs", 1480 NULL, "vmx-exit-clear-rtit-ctl", NULL, NULL, 1481 NULL, "vmx-exit-load-pkrs", NULL, "vmx-exit-secondary-ctls", 1482 }, 1483 .msr = { 1484 .index = MSR_IA32_VMX_TRUE_EXIT_CTLS, 1485 } 1486 }, 1487 1488 [FEAT_VMX_ENTRY_CTLS] = { 1489 .type = MSR_FEATURE_WORD, 1490 .feat_names = { 1491 NULL, NULL, "vmx-entry-noload-debugctl", NULL, 1492 NULL, NULL, NULL, NULL, 1493 NULL, "vmx-entry-ia32e-mode", NULL, NULL, 1494 NULL, "vmx-entry-load-perf-global-ctrl", "vmx-entry-load-pat", "vmx-entry-load-efer", 1495 "vmx-entry-load-bndcfgs", NULL, "vmx-entry-load-rtit-ctl", NULL, 1496 NULL, NULL, "vmx-entry-load-pkrs", "vmx-entry-load-fred", 1497 NULL, NULL, NULL, NULL, 1498 NULL, NULL, NULL, NULL, 1499 }, 1500 .msr = { 1501 .index = MSR_IA32_VMX_TRUE_ENTRY_CTLS, 1502 } 1503 }, 1504 1505 [FEAT_VMX_MISC] = { 1506 .type = MSR_FEATURE_WORD, 1507 .feat_names = { 1508 NULL, NULL, NULL, NULL, 1509 NULL, "vmx-store-lma", "vmx-activity-hlt", "vmx-activity-shutdown", 1510 "vmx-activity-wait-sipi", NULL, NULL, NULL, 1511 NULL, NULL, NULL, NULL, 1512 NULL, NULL, NULL, NULL, 1513 NULL, NULL, NULL, NULL, 1514 NULL, NULL, NULL, NULL, 1515 NULL, "vmx-vmwrite-vmexit-fields", "vmx-zero-len-inject", NULL, 1516 }, 1517 .msr = { 1518 .index = MSR_IA32_VMX_MISC, 1519 } 1520 }, 1521 1522 [FEAT_VMX_EPT_VPID_CAPS] = { 1523 .type = MSR_FEATURE_WORD, 1524 .feat_names = { 1525 "vmx-ept-execonly", NULL, NULL, NULL, 1526 NULL, NULL, "vmx-page-walk-4", "vmx-page-walk-5", 1527 NULL, NULL, NULL, NULL, 1528 NULL, NULL, NULL, NULL, 1529 "vmx-ept-2mb", "vmx-ept-1gb", NULL, NULL, 1530 "vmx-invept", "vmx-eptad", "vmx-ept-advanced-exitinfo", NULL, 1531 NULL, "vmx-invept-single-context", "vmx-invept-all-context", NULL, 1532 NULL, NULL, NULL, NULL, 1533 "vmx-invvpid", NULL, NULL, NULL, 1534 NULL, NULL, NULL, NULL, 1535 "vmx-invvpid-single-addr", "vmx-invept-single-context", 1536 "vmx-invvpid-all-context", "vmx-invept-single-context-noglobals", 1537 NULL, NULL, NULL, NULL, 1538 NULL, NULL, NULL, NULL, 1539 NULL, NULL, NULL, NULL, 1540 NULL, NULL, NULL, NULL, 1541 NULL, NULL, NULL, NULL, 1542 }, 1543 .msr = { 1544 .index = MSR_IA32_VMX_EPT_VPID_CAP, 1545 } 1546 }, 1547 1548 [FEAT_VMX_BASIC] = { 1549 .type = MSR_FEATURE_WORD, 1550 .feat_names = { 1551 [54] = "vmx-ins-outs", 1552 [55] = "vmx-true-ctls", 1553 [56] = "vmx-any-errcode", 1554 [58] = "vmx-nested-exception", 1555 }, 1556 .msr = { 1557 .index = MSR_IA32_VMX_BASIC, 1558 }, 1559 /* Just to be safe - we don't support setting the MSEG version field. */ 1560 .no_autoenable_flags = MSR_VMX_BASIC_DUAL_MONITOR, 1561 }, 1562 1563 [FEAT_VMX_VMFUNC] = { 1564 .type = MSR_FEATURE_WORD, 1565 .feat_names = { 1566 [0] = "vmx-eptp-switching", 1567 }, 1568 .msr = { 1569 .index = MSR_IA32_VMX_VMFUNC, 1570 } 1571 }, 1572 1573 [FEAT_14_0_ECX] = { 1574 .type = CPUID_FEATURE_WORD, 1575 .feat_names = { 1576 NULL, NULL, NULL, NULL, 1577 NULL, NULL, NULL, NULL, 1578 NULL, NULL, NULL, NULL, 1579 NULL, NULL, NULL, NULL, 1580 NULL, NULL, NULL, NULL, 1581 NULL, NULL, NULL, NULL, 1582 NULL, NULL, NULL, NULL, 1583 NULL, NULL, NULL, "intel-pt-lip", 1584 }, 1585 .cpuid = { 1586 .eax = 0x14, 1587 .needs_ecx = true, .ecx = 0, 1588 .reg = R_ECX, 1589 }, 1590 .tcg_features = TCG_14_0_ECX_FEATURES, 1591 }, 1592 1593 [FEAT_SGX_12_0_EAX] = { 1594 .type = CPUID_FEATURE_WORD, 1595 .feat_names = { 1596 "sgx1", "sgx2", NULL, NULL, 1597 NULL, NULL, NULL, NULL, 1598 NULL, NULL, NULL, "sgx-edeccssa", 1599 NULL, NULL, NULL, NULL, 1600 NULL, NULL, NULL, NULL, 1601 NULL, NULL, NULL, NULL, 1602 NULL, NULL, NULL, NULL, 1603 NULL, NULL, NULL, NULL, 1604 }, 1605 .cpuid = { 1606 .eax = 0x12, 1607 .needs_ecx = true, .ecx = 0, 1608 .reg = R_EAX, 1609 }, 1610 .tcg_features = TCG_SGX_12_0_EAX_FEATURES, 1611 }, 1612 1613 [FEAT_SGX_12_0_EBX] = { 1614 .type = CPUID_FEATURE_WORD, 1615 .feat_names = { 1616 "sgx-exinfo" , NULL, NULL, NULL, 1617 NULL, NULL, NULL, NULL, 1618 NULL, NULL, NULL, NULL, 1619 NULL, NULL, NULL, NULL, 1620 NULL, NULL, NULL, NULL, 1621 NULL, NULL, NULL, NULL, 1622 NULL, NULL, NULL, NULL, 1623 NULL, NULL, NULL, NULL, 1624 }, 1625 .cpuid = { 1626 .eax = 0x12, 1627 .needs_ecx = true, .ecx = 0, 1628 .reg = R_EBX, 1629 }, 1630 .tcg_features = TCG_SGX_12_0_EBX_FEATURES, 1631 }, 1632 1633 [FEAT_SGX_12_1_EAX] = { 1634 .type = CPUID_FEATURE_WORD, 1635 .feat_names = { 1636 NULL, "sgx-debug", "sgx-mode64", NULL, 1637 "sgx-provisionkey", "sgx-tokenkey", NULL, "sgx-kss", 1638 NULL, NULL, "sgx-aex-notify", NULL, 1639 NULL, NULL, NULL, NULL, 1640 NULL, NULL, NULL, NULL, 1641 NULL, NULL, NULL, NULL, 1642 NULL, NULL, NULL, NULL, 1643 NULL, NULL, NULL, NULL, 1644 }, 1645 .cpuid = { 1646 .eax = 0x12, 1647 .needs_ecx = true, .ecx = 1, 1648 .reg = R_EAX, 1649 }, 1650 .tcg_features = TCG_SGX_12_1_EAX_FEATURES, 1651 }, 1652 }; 1653 1654 typedef struct FeatureMask { 1655 FeatureWord index; 1656 uint64_t mask; 1657 } FeatureMask; 1658 1659 typedef struct FeatureDep { 1660 FeatureMask from, to; 1661 } FeatureDep; 1662 1663 static FeatureDep feature_dependencies[] = { 1664 { 1665 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_ARCH_CAPABILITIES }, 1666 .to = { FEAT_ARCH_CAPABILITIES, ~0ull }, 1667 }, 1668 { 1669 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_CORE_CAPABILITY }, 1670 .to = { FEAT_CORE_CAPABILITY, ~0ull }, 1671 }, 1672 { 1673 .from = { FEAT_1_ECX, CPUID_EXT_PDCM }, 1674 .to = { FEAT_PERF_CAPABILITIES, ~0ull }, 1675 }, 1676 { 1677 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1678 .to = { FEAT_VMX_PROCBASED_CTLS, ~0ull }, 1679 }, 1680 { 1681 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1682 .to = { FEAT_VMX_PINBASED_CTLS, ~0ull }, 1683 }, 1684 { 1685 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1686 .to = { FEAT_VMX_EXIT_CTLS, ~0ull }, 1687 }, 1688 { 1689 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1690 .to = { FEAT_VMX_ENTRY_CTLS, ~0ull }, 1691 }, 1692 { 1693 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1694 .to = { FEAT_VMX_MISC, ~0ull }, 1695 }, 1696 { 1697 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1698 .to = { FEAT_VMX_BASIC, ~0ull }, 1699 }, 1700 { 1701 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_LM }, 1702 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_IA32E_MODE }, 1703 }, 1704 { 1705 .from = { FEAT_VMX_PROCBASED_CTLS, VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS }, 1706 .to = { FEAT_VMX_SECONDARY_CTLS, ~0ull }, 1707 }, 1708 { 1709 .from = { FEAT_XSAVE, CPUID_XSAVE_XSAVES }, 1710 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_XSAVES }, 1711 }, 1712 { 1713 .from = { FEAT_1_ECX, CPUID_EXT_RDRAND }, 1714 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDRAND_EXITING }, 1715 }, 1716 { 1717 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INVPCID }, 1718 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_INVPCID }, 1719 }, 1720 { 1721 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_MPX }, 1722 .to = { FEAT_VMX_EXIT_CTLS, VMX_VM_EXIT_CLEAR_BNDCFGS }, 1723 }, 1724 { 1725 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_MPX }, 1726 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_LOAD_BNDCFGS }, 1727 }, 1728 { 1729 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_RDSEED }, 1730 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDSEED_EXITING }, 1731 }, 1732 { 1733 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT }, 1734 .to = { FEAT_14_0_ECX, ~0ull }, 1735 }, 1736 { 1737 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_RDTSCP }, 1738 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDTSCP }, 1739 }, 1740 { 1741 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT }, 1742 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull }, 1743 }, 1744 { 1745 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT }, 1746 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST }, 1747 }, 1748 { 1749 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VPID }, 1750 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull << 32 }, 1751 }, 1752 { 1753 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VMFUNC }, 1754 .to = { FEAT_VMX_VMFUNC, ~0ull }, 1755 }, 1756 { 1757 .from = { FEAT_8000_0001_ECX, CPUID_EXT3_SVM }, 1758 .to = { FEAT_SVM, ~0ull }, 1759 }, 1760 { 1761 .from = { FEAT_7_0_ECX, CPUID_7_0_ECX_WAITPKG }, 1762 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_USER_WAIT_PAUSE }, 1763 }, 1764 { 1765 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_LM }, 1766 .to = { FEAT_7_1_EAX, CPUID_7_1_EAX_FRED }, 1767 }, 1768 { 1769 .from = { FEAT_7_1_EAX, CPUID_7_1_EAX_LKGS }, 1770 .to = { FEAT_7_1_EAX, CPUID_7_1_EAX_FRED }, 1771 }, 1772 { 1773 .from = { FEAT_7_1_EAX, CPUID_7_1_EAX_WRMSRNS }, 1774 .to = { FEAT_7_1_EAX, CPUID_7_1_EAX_FRED }, 1775 }, 1776 { 1777 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_SGX }, 1778 .to = { FEAT_7_0_ECX, CPUID_7_0_ECX_SGX_LC }, 1779 }, 1780 { 1781 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_SGX }, 1782 .to = { FEAT_SGX_12_0_EAX, ~0ull }, 1783 }, 1784 { 1785 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_SGX }, 1786 .to = { FEAT_SGX_12_0_EBX, ~0ull }, 1787 }, 1788 { 1789 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_SGX }, 1790 .to = { FEAT_SGX_12_1_EAX, ~0ull }, 1791 }, 1792 { 1793 .from = { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_128 }, 1794 .to = { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_256 }, 1795 }, 1796 { 1797 .from = { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_256 }, 1798 .to = { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_512 }, 1799 }, 1800 { 1801 .from = { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_VL_MASK }, 1802 .to = { FEAT_7_1_EDX, CPUID_7_1_EDX_AVX10 }, 1803 }, 1804 { 1805 .from = { FEAT_7_1_EDX, CPUID_7_1_EDX_AVX10 }, 1806 .to = { FEAT_24_0_EBX, ~0ull }, 1807 }, 1808 }; 1809 1810 typedef struct X86RegisterInfo32 { 1811 /* Name of register */ 1812 const char *name; 1813 /* QAPI enum value register */ 1814 X86CPURegister32 qapi_enum; 1815 } X86RegisterInfo32; 1816 1817 #define REGISTER(reg) \ 1818 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg } 1819 static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = { 1820 REGISTER(EAX), 1821 REGISTER(ECX), 1822 REGISTER(EDX), 1823 REGISTER(EBX), 1824 REGISTER(ESP), 1825 REGISTER(EBP), 1826 REGISTER(ESI), 1827 REGISTER(EDI), 1828 }; 1829 #undef REGISTER 1830 1831 /* CPUID feature bits available in XSS */ 1832 #define CPUID_XSTATE_XSS_MASK (XSTATE_ARCH_LBR_MASK) 1833 1834 ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUNT] = { 1835 [XSTATE_FP_BIT] = { 1836 /* x87 FP state component is always enabled if XSAVE is supported */ 1837 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE, 1838 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader), 1839 }, 1840 [XSTATE_SSE_BIT] = { 1841 /* SSE state component is always enabled if XSAVE is supported */ 1842 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE, 1843 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader), 1844 }, 1845 [XSTATE_YMM_BIT] = 1846 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX, 1847 .size = sizeof(XSaveAVX) }, 1848 [XSTATE_BNDREGS_BIT] = 1849 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX, 1850 .size = sizeof(XSaveBNDREG) }, 1851 [XSTATE_BNDCSR_BIT] = 1852 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX, 1853 .size = sizeof(XSaveBNDCSR) }, 1854 [XSTATE_OPMASK_BIT] = 1855 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1856 .size = sizeof(XSaveOpmask) }, 1857 [XSTATE_ZMM_Hi256_BIT] = 1858 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1859 .size = sizeof(XSaveZMM_Hi256) }, 1860 [XSTATE_Hi16_ZMM_BIT] = 1861 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1862 .size = sizeof(XSaveHi16_ZMM) }, 1863 [XSTATE_PKRU_BIT] = 1864 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU, 1865 .size = sizeof(XSavePKRU) }, 1866 [XSTATE_ARCH_LBR_BIT] = { 1867 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_ARCH_LBR, 1868 .offset = 0 /*supervisor mode component, offset = 0 */, 1869 .size = sizeof(XSavesArchLBR) }, 1870 [XSTATE_XTILE_CFG_BIT] = { 1871 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_AMX_TILE, 1872 .size = sizeof(XSaveXTILECFG), 1873 }, 1874 [XSTATE_XTILE_DATA_BIT] = { 1875 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_AMX_TILE, 1876 .size = sizeof(XSaveXTILEDATA) 1877 }, 1878 }; 1879 1880 uint32_t xsave_area_size(uint64_t mask, bool compacted) 1881 { 1882 uint64_t ret = x86_ext_save_areas[0].size; 1883 const ExtSaveArea *esa; 1884 uint32_t offset = 0; 1885 int i; 1886 1887 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 1888 esa = &x86_ext_save_areas[i]; 1889 if ((mask >> i) & 1) { 1890 offset = compacted ? ret : esa->offset; 1891 ret = MAX(ret, offset + esa->size); 1892 } 1893 } 1894 return ret; 1895 } 1896 1897 static inline bool accel_uses_host_cpuid(void) 1898 { 1899 return kvm_enabled() || hvf_enabled(); 1900 } 1901 1902 static inline uint64_t x86_cpu_xsave_xcr0_components(X86CPU *cpu) 1903 { 1904 return ((uint64_t)cpu->env.features[FEAT_XSAVE_XCR0_HI]) << 32 | 1905 cpu->env.features[FEAT_XSAVE_XCR0_LO]; 1906 } 1907 1908 /* Return name of 32-bit register, from a R_* constant */ 1909 static const char *get_register_name_32(unsigned int reg) 1910 { 1911 if (reg >= CPU_NB_REGS32) { 1912 return NULL; 1913 } 1914 return x86_reg_info_32[reg].name; 1915 } 1916 1917 static inline uint64_t x86_cpu_xsave_xss_components(X86CPU *cpu) 1918 { 1919 return ((uint64_t)cpu->env.features[FEAT_XSAVE_XSS_HI]) << 32 | 1920 cpu->env.features[FEAT_XSAVE_XSS_LO]; 1921 } 1922 1923 /* 1924 * Returns the set of feature flags that are supported and migratable by 1925 * QEMU, for a given FeatureWord. 1926 */ 1927 static uint64_t x86_cpu_get_migratable_flags(X86CPU *cpu, FeatureWord w) 1928 { 1929 FeatureWordInfo *wi = &feature_word_info[w]; 1930 CPUX86State *env = &cpu->env; 1931 uint64_t r = 0; 1932 int i; 1933 1934 for (i = 0; i < 64; i++) { 1935 uint64_t f = 1ULL << i; 1936 1937 /* If the feature name is known, it is implicitly considered migratable, 1938 * unless it is explicitly set in unmigratable_flags */ 1939 if ((wi->migratable_flags & f) || 1940 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) { 1941 r |= f; 1942 } 1943 } 1944 1945 /* when tsc-khz is set explicitly, invtsc is migratable */ 1946 if ((w == FEAT_8000_0007_EDX) && env->user_tsc_khz) { 1947 r |= CPUID_APM_INVTSC; 1948 } 1949 1950 return r; 1951 } 1952 1953 void host_cpuid(uint32_t function, uint32_t count, 1954 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) 1955 { 1956 uint32_t vec[4]; 1957 1958 #ifdef __x86_64__ 1959 asm volatile("cpuid" 1960 : "=a"(vec[0]), "=b"(vec[1]), 1961 "=c"(vec[2]), "=d"(vec[3]) 1962 : "0"(function), "c"(count) : "cc"); 1963 #elif defined(__i386__) 1964 asm volatile("pusha \n\t" 1965 "cpuid \n\t" 1966 "mov %%eax, 0(%2) \n\t" 1967 "mov %%ebx, 4(%2) \n\t" 1968 "mov %%ecx, 8(%2) \n\t" 1969 "mov %%edx, 12(%2) \n\t" 1970 "popa" 1971 : : "a"(function), "c"(count), "S"(vec) 1972 : "memory", "cc"); 1973 #else 1974 abort(); 1975 #endif 1976 1977 if (eax) 1978 *eax = vec[0]; 1979 if (ebx) 1980 *ebx = vec[1]; 1981 if (ecx) 1982 *ecx = vec[2]; 1983 if (edx) 1984 *edx = vec[3]; 1985 } 1986 1987 /* CPU class name definitions: */ 1988 1989 /* Return type name for a given CPU model name 1990 * Caller is responsible for freeing the returned string. 1991 */ 1992 static char *x86_cpu_type_name(const char *model_name) 1993 { 1994 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name); 1995 } 1996 1997 static ObjectClass *x86_cpu_class_by_name(const char *cpu_model) 1998 { 1999 g_autofree char *typename = x86_cpu_type_name(cpu_model); 2000 return object_class_by_name(typename); 2001 } 2002 2003 static char *x86_cpu_class_get_model_name(X86CPUClass *cc) 2004 { 2005 const char *class_name = object_class_get_name(OBJECT_CLASS(cc)); 2006 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX)); 2007 return cpu_model_from_type(class_name); 2008 } 2009 2010 typedef struct X86CPUVersionDefinition { 2011 X86CPUVersion version; 2012 const char *alias; 2013 const char *note; 2014 PropValue *props; 2015 const CPUCaches *const cache_info; 2016 } X86CPUVersionDefinition; 2017 2018 /* Base definition for a CPU model */ 2019 typedef struct X86CPUDefinition { 2020 const char *name; 2021 uint32_t level; 2022 uint32_t xlevel; 2023 /* vendor is zero-terminated, 12 character ASCII string */ 2024 char vendor[CPUID_VENDOR_SZ + 1]; 2025 int family; 2026 int model; 2027 int stepping; 2028 uint8_t avx10_version; 2029 FeatureWordArray features; 2030 const char *model_id; 2031 const CPUCaches *const cache_info; 2032 /* 2033 * Definitions for alternative versions of CPU model. 2034 * List is terminated by item with version == 0. 2035 * If NULL, version 1 will be registered automatically. 2036 */ 2037 const X86CPUVersionDefinition *versions; 2038 const char *deprecation_note; 2039 } X86CPUDefinition; 2040 2041 /* Reference to a specific CPU model version */ 2042 struct X86CPUModel { 2043 /* Base CPU definition */ 2044 const X86CPUDefinition *cpudef; 2045 /* CPU model version */ 2046 X86CPUVersion version; 2047 const char *note; 2048 /* 2049 * If true, this is an alias CPU model. 2050 * This matters only for "-cpu help" and query-cpu-definitions 2051 */ 2052 bool is_alias; 2053 }; 2054 2055 /* Get full model name for CPU version */ 2056 static char *x86_cpu_versioned_model_name(const X86CPUDefinition *cpudef, 2057 X86CPUVersion version) 2058 { 2059 assert(version > 0); 2060 return g_strdup_printf("%s-v%d", cpudef->name, (int)version); 2061 } 2062 2063 static const X86CPUVersionDefinition * 2064 x86_cpu_def_get_versions(const X86CPUDefinition *def) 2065 { 2066 /* When X86CPUDefinition::versions is NULL, we register only v1 */ 2067 static const X86CPUVersionDefinition default_version_list[] = { 2068 { 1 }, 2069 { /* end of list */ } 2070 }; 2071 2072 return def->versions ?: default_version_list; 2073 } 2074 2075 static const CPUCaches epyc_cache_info = { 2076 .l1d_cache = &(CPUCacheInfo) { 2077 .type = DATA_CACHE, 2078 .level = 1, 2079 .size = 32 * KiB, 2080 .line_size = 64, 2081 .associativity = 8, 2082 .partitions = 1, 2083 .sets = 64, 2084 .lines_per_tag = 1, 2085 .self_init = 1, 2086 .no_invd_sharing = true, 2087 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2088 }, 2089 .l1i_cache = &(CPUCacheInfo) { 2090 .type = INSTRUCTION_CACHE, 2091 .level = 1, 2092 .size = 64 * KiB, 2093 .line_size = 64, 2094 .associativity = 4, 2095 .partitions = 1, 2096 .sets = 256, 2097 .lines_per_tag = 1, 2098 .self_init = 1, 2099 .no_invd_sharing = true, 2100 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2101 }, 2102 .l2_cache = &(CPUCacheInfo) { 2103 .type = UNIFIED_CACHE, 2104 .level = 2, 2105 .size = 512 * KiB, 2106 .line_size = 64, 2107 .associativity = 8, 2108 .partitions = 1, 2109 .sets = 1024, 2110 .lines_per_tag = 1, 2111 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2112 }, 2113 .l3_cache = &(CPUCacheInfo) { 2114 .type = UNIFIED_CACHE, 2115 .level = 3, 2116 .size = 8 * MiB, 2117 .line_size = 64, 2118 .associativity = 16, 2119 .partitions = 1, 2120 .sets = 8192, 2121 .lines_per_tag = 1, 2122 .self_init = true, 2123 .inclusive = true, 2124 .complex_indexing = true, 2125 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2126 }, 2127 }; 2128 2129 static CPUCaches epyc_v4_cache_info = { 2130 .l1d_cache = &(CPUCacheInfo) { 2131 .type = DATA_CACHE, 2132 .level = 1, 2133 .size = 32 * KiB, 2134 .line_size = 64, 2135 .associativity = 8, 2136 .partitions = 1, 2137 .sets = 64, 2138 .lines_per_tag = 1, 2139 .self_init = 1, 2140 .no_invd_sharing = true, 2141 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2142 }, 2143 .l1i_cache = &(CPUCacheInfo) { 2144 .type = INSTRUCTION_CACHE, 2145 .level = 1, 2146 .size = 64 * KiB, 2147 .line_size = 64, 2148 .associativity = 4, 2149 .partitions = 1, 2150 .sets = 256, 2151 .lines_per_tag = 1, 2152 .self_init = 1, 2153 .no_invd_sharing = true, 2154 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2155 }, 2156 .l2_cache = &(CPUCacheInfo) { 2157 .type = UNIFIED_CACHE, 2158 .level = 2, 2159 .size = 512 * KiB, 2160 .line_size = 64, 2161 .associativity = 8, 2162 .partitions = 1, 2163 .sets = 1024, 2164 .lines_per_tag = 1, 2165 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2166 }, 2167 .l3_cache = &(CPUCacheInfo) { 2168 .type = UNIFIED_CACHE, 2169 .level = 3, 2170 .size = 8 * MiB, 2171 .line_size = 64, 2172 .associativity = 16, 2173 .partitions = 1, 2174 .sets = 8192, 2175 .lines_per_tag = 1, 2176 .self_init = true, 2177 .inclusive = true, 2178 .complex_indexing = false, 2179 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2180 }, 2181 }; 2182 2183 static const CPUCaches epyc_rome_cache_info = { 2184 .l1d_cache = &(CPUCacheInfo) { 2185 .type = DATA_CACHE, 2186 .level = 1, 2187 .size = 32 * KiB, 2188 .line_size = 64, 2189 .associativity = 8, 2190 .partitions = 1, 2191 .sets = 64, 2192 .lines_per_tag = 1, 2193 .self_init = 1, 2194 .no_invd_sharing = true, 2195 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2196 }, 2197 .l1i_cache = &(CPUCacheInfo) { 2198 .type = INSTRUCTION_CACHE, 2199 .level = 1, 2200 .size = 32 * KiB, 2201 .line_size = 64, 2202 .associativity = 8, 2203 .partitions = 1, 2204 .sets = 64, 2205 .lines_per_tag = 1, 2206 .self_init = 1, 2207 .no_invd_sharing = true, 2208 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2209 }, 2210 .l2_cache = &(CPUCacheInfo) { 2211 .type = UNIFIED_CACHE, 2212 .level = 2, 2213 .size = 512 * KiB, 2214 .line_size = 64, 2215 .associativity = 8, 2216 .partitions = 1, 2217 .sets = 1024, 2218 .lines_per_tag = 1, 2219 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2220 }, 2221 .l3_cache = &(CPUCacheInfo) { 2222 .type = UNIFIED_CACHE, 2223 .level = 3, 2224 .size = 16 * MiB, 2225 .line_size = 64, 2226 .associativity = 16, 2227 .partitions = 1, 2228 .sets = 16384, 2229 .lines_per_tag = 1, 2230 .self_init = true, 2231 .inclusive = true, 2232 .complex_indexing = true, 2233 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2234 }, 2235 }; 2236 2237 static const CPUCaches epyc_rome_v3_cache_info = { 2238 .l1d_cache = &(CPUCacheInfo) { 2239 .type = DATA_CACHE, 2240 .level = 1, 2241 .size = 32 * KiB, 2242 .line_size = 64, 2243 .associativity = 8, 2244 .partitions = 1, 2245 .sets = 64, 2246 .lines_per_tag = 1, 2247 .self_init = 1, 2248 .no_invd_sharing = true, 2249 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2250 }, 2251 .l1i_cache = &(CPUCacheInfo) { 2252 .type = INSTRUCTION_CACHE, 2253 .level = 1, 2254 .size = 32 * KiB, 2255 .line_size = 64, 2256 .associativity = 8, 2257 .partitions = 1, 2258 .sets = 64, 2259 .lines_per_tag = 1, 2260 .self_init = 1, 2261 .no_invd_sharing = true, 2262 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2263 }, 2264 .l2_cache = &(CPUCacheInfo) { 2265 .type = UNIFIED_CACHE, 2266 .level = 2, 2267 .size = 512 * KiB, 2268 .line_size = 64, 2269 .associativity = 8, 2270 .partitions = 1, 2271 .sets = 1024, 2272 .lines_per_tag = 1, 2273 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2274 }, 2275 .l3_cache = &(CPUCacheInfo) { 2276 .type = UNIFIED_CACHE, 2277 .level = 3, 2278 .size = 16 * MiB, 2279 .line_size = 64, 2280 .associativity = 16, 2281 .partitions = 1, 2282 .sets = 16384, 2283 .lines_per_tag = 1, 2284 .self_init = true, 2285 .inclusive = true, 2286 .complex_indexing = false, 2287 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2288 }, 2289 }; 2290 2291 static const CPUCaches epyc_milan_cache_info = { 2292 .l1d_cache = &(CPUCacheInfo) { 2293 .type = DATA_CACHE, 2294 .level = 1, 2295 .size = 32 * KiB, 2296 .line_size = 64, 2297 .associativity = 8, 2298 .partitions = 1, 2299 .sets = 64, 2300 .lines_per_tag = 1, 2301 .self_init = 1, 2302 .no_invd_sharing = true, 2303 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2304 }, 2305 .l1i_cache = &(CPUCacheInfo) { 2306 .type = INSTRUCTION_CACHE, 2307 .level = 1, 2308 .size = 32 * KiB, 2309 .line_size = 64, 2310 .associativity = 8, 2311 .partitions = 1, 2312 .sets = 64, 2313 .lines_per_tag = 1, 2314 .self_init = 1, 2315 .no_invd_sharing = true, 2316 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2317 }, 2318 .l2_cache = &(CPUCacheInfo) { 2319 .type = UNIFIED_CACHE, 2320 .level = 2, 2321 .size = 512 * KiB, 2322 .line_size = 64, 2323 .associativity = 8, 2324 .partitions = 1, 2325 .sets = 1024, 2326 .lines_per_tag = 1, 2327 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2328 }, 2329 .l3_cache = &(CPUCacheInfo) { 2330 .type = UNIFIED_CACHE, 2331 .level = 3, 2332 .size = 32 * MiB, 2333 .line_size = 64, 2334 .associativity = 16, 2335 .partitions = 1, 2336 .sets = 32768, 2337 .lines_per_tag = 1, 2338 .self_init = true, 2339 .inclusive = true, 2340 .complex_indexing = true, 2341 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2342 }, 2343 }; 2344 2345 static const CPUCaches epyc_milan_v2_cache_info = { 2346 .l1d_cache = &(CPUCacheInfo) { 2347 .type = DATA_CACHE, 2348 .level = 1, 2349 .size = 32 * KiB, 2350 .line_size = 64, 2351 .associativity = 8, 2352 .partitions = 1, 2353 .sets = 64, 2354 .lines_per_tag = 1, 2355 .self_init = 1, 2356 .no_invd_sharing = true, 2357 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2358 }, 2359 .l1i_cache = &(CPUCacheInfo) { 2360 .type = INSTRUCTION_CACHE, 2361 .level = 1, 2362 .size = 32 * KiB, 2363 .line_size = 64, 2364 .associativity = 8, 2365 .partitions = 1, 2366 .sets = 64, 2367 .lines_per_tag = 1, 2368 .self_init = 1, 2369 .no_invd_sharing = true, 2370 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2371 }, 2372 .l2_cache = &(CPUCacheInfo) { 2373 .type = UNIFIED_CACHE, 2374 .level = 2, 2375 .size = 512 * KiB, 2376 .line_size = 64, 2377 .associativity = 8, 2378 .partitions = 1, 2379 .sets = 1024, 2380 .lines_per_tag = 1, 2381 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2382 }, 2383 .l3_cache = &(CPUCacheInfo) { 2384 .type = UNIFIED_CACHE, 2385 .level = 3, 2386 .size = 32 * MiB, 2387 .line_size = 64, 2388 .associativity = 16, 2389 .partitions = 1, 2390 .sets = 32768, 2391 .lines_per_tag = 1, 2392 .self_init = true, 2393 .inclusive = true, 2394 .complex_indexing = false, 2395 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2396 }, 2397 }; 2398 2399 static const CPUCaches epyc_genoa_cache_info = { 2400 .l1d_cache = &(CPUCacheInfo) { 2401 .type = DATA_CACHE, 2402 .level = 1, 2403 .size = 32 * KiB, 2404 .line_size = 64, 2405 .associativity = 8, 2406 .partitions = 1, 2407 .sets = 64, 2408 .lines_per_tag = 1, 2409 .self_init = 1, 2410 .no_invd_sharing = true, 2411 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2412 }, 2413 .l1i_cache = &(CPUCacheInfo) { 2414 .type = INSTRUCTION_CACHE, 2415 .level = 1, 2416 .size = 32 * KiB, 2417 .line_size = 64, 2418 .associativity = 8, 2419 .partitions = 1, 2420 .sets = 64, 2421 .lines_per_tag = 1, 2422 .self_init = 1, 2423 .no_invd_sharing = true, 2424 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2425 }, 2426 .l2_cache = &(CPUCacheInfo) { 2427 .type = UNIFIED_CACHE, 2428 .level = 2, 2429 .size = 1 * MiB, 2430 .line_size = 64, 2431 .associativity = 8, 2432 .partitions = 1, 2433 .sets = 2048, 2434 .lines_per_tag = 1, 2435 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2436 }, 2437 .l3_cache = &(CPUCacheInfo) { 2438 .type = UNIFIED_CACHE, 2439 .level = 3, 2440 .size = 32 * MiB, 2441 .line_size = 64, 2442 .associativity = 16, 2443 .partitions = 1, 2444 .sets = 32768, 2445 .lines_per_tag = 1, 2446 .self_init = true, 2447 .inclusive = true, 2448 .complex_indexing = false, 2449 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2450 }, 2451 }; 2452 2453 /* The following VMX features are not supported by KVM and are left out in the 2454 * CPU definitions: 2455 * 2456 * Dual-monitor support (all processors) 2457 * Entry to SMM 2458 * Deactivate dual-monitor treatment 2459 * Number of CR3-target values 2460 * Shutdown activity state 2461 * Wait-for-SIPI activity state 2462 * PAUSE-loop exiting (Westmere and newer) 2463 * EPT-violation #VE (Broadwell and newer) 2464 * Inject event with insn length=0 (Skylake and newer) 2465 * Conceal non-root operation from PT 2466 * Conceal VM exits from PT 2467 * Conceal VM entries from PT 2468 * Enable ENCLS exiting 2469 * Mode-based execute control (XS/XU) 2470 * TSC scaling (Skylake Server and newer) 2471 * GPA translation for PT (IceLake and newer) 2472 * User wait and pause 2473 * ENCLV exiting 2474 * Load IA32_RTIT_CTL 2475 * Clear IA32_RTIT_CTL 2476 * Advanced VM-exit information for EPT violations 2477 * Sub-page write permissions 2478 * PT in VMX operation 2479 */ 2480 2481 static const X86CPUDefinition builtin_x86_defs[] = { 2482 { 2483 .name = "qemu64", 2484 .level = 0xd, 2485 .vendor = CPUID_VENDOR_AMD, 2486 .family = 15, 2487 .model = 107, 2488 .stepping = 1, 2489 .features[FEAT_1_EDX] = 2490 PPRO_FEATURES | 2491 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2492 CPUID_PSE36, 2493 .features[FEAT_1_ECX] = 2494 CPUID_EXT_SSE3 | CPUID_EXT_CX16, 2495 .features[FEAT_8000_0001_EDX] = 2496 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2497 .features[FEAT_8000_0001_ECX] = 2498 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM, 2499 .xlevel = 0x8000000A, 2500 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 2501 }, 2502 { 2503 .name = "phenom", 2504 .level = 5, 2505 .vendor = CPUID_VENDOR_AMD, 2506 .family = 16, 2507 .model = 2, 2508 .stepping = 3, 2509 /* Missing: CPUID_HT */ 2510 .features[FEAT_1_EDX] = 2511 PPRO_FEATURES | 2512 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2513 CPUID_PSE36 | CPUID_VME, 2514 .features[FEAT_1_ECX] = 2515 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 | 2516 CPUID_EXT_POPCNT, 2517 .features[FEAT_8000_0001_EDX] = 2518 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | 2519 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT | 2520 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP, 2521 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, 2522 CPUID_EXT3_CR8LEG, 2523 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, 2524 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */ 2525 .features[FEAT_8000_0001_ECX] = 2526 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | 2527 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A, 2528 /* Missing: CPUID_SVM_LBRV */ 2529 .features[FEAT_SVM] = 2530 CPUID_SVM_NPT, 2531 .xlevel = 0x8000001A, 2532 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor" 2533 }, 2534 { 2535 .name = "core2duo", 2536 .level = 10, 2537 .vendor = CPUID_VENDOR_INTEL, 2538 .family = 6, 2539 .model = 15, 2540 .stepping = 11, 2541 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2542 .features[FEAT_1_EDX] = 2543 PPRO_FEATURES | 2544 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2545 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS, 2546 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST, 2547 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */ 2548 .features[FEAT_1_ECX] = 2549 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | 2550 CPUID_EXT_CX16, 2551 .features[FEAT_8000_0001_EDX] = 2552 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2553 .features[FEAT_8000_0001_ECX] = 2554 CPUID_EXT3_LAHF_LM, 2555 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2556 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2557 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2558 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2559 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2560 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2561 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2562 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2563 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2564 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2565 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2566 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2567 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2568 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2569 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2570 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2571 .features[FEAT_VMX_SECONDARY_CTLS] = 2572 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES, 2573 .xlevel = 0x80000008, 2574 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz", 2575 }, 2576 { 2577 .name = "kvm64", 2578 .level = 0xd, 2579 .vendor = CPUID_VENDOR_INTEL, 2580 .family = 15, 2581 .model = 6, 2582 .stepping = 1, 2583 /* Missing: CPUID_HT */ 2584 .features[FEAT_1_EDX] = 2585 PPRO_FEATURES | CPUID_VME | 2586 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2587 CPUID_PSE36, 2588 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */ 2589 .features[FEAT_1_ECX] = 2590 CPUID_EXT_SSE3 | CPUID_EXT_CX16, 2591 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */ 2592 .features[FEAT_8000_0001_EDX] = 2593 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2594 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, 2595 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A, 2596 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, 2597 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */ 2598 .features[FEAT_8000_0001_ECX] = 2599 0, 2600 /* VMX features from Cedar Mill/Prescott */ 2601 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2602 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2603 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2604 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2605 VMX_PIN_BASED_NMI_EXITING, 2606 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2607 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2608 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2609 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2610 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2611 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2612 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2613 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING, 2614 .xlevel = 0x80000008, 2615 .model_id = "Common KVM processor" 2616 }, 2617 { 2618 .name = "qemu32", 2619 .level = 4, 2620 .vendor = CPUID_VENDOR_INTEL, 2621 .family = 6, 2622 .model = 6, 2623 .stepping = 3, 2624 .features[FEAT_1_EDX] = 2625 PPRO_FEATURES, 2626 .features[FEAT_1_ECX] = 2627 CPUID_EXT_SSE3, 2628 .xlevel = 0x80000004, 2629 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 2630 }, 2631 { 2632 .name = "kvm32", 2633 .level = 5, 2634 .vendor = CPUID_VENDOR_INTEL, 2635 .family = 15, 2636 .model = 6, 2637 .stepping = 1, 2638 .features[FEAT_1_EDX] = 2639 PPRO_FEATURES | CPUID_VME | 2640 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36, 2641 .features[FEAT_1_ECX] = 2642 CPUID_EXT_SSE3, 2643 .features[FEAT_8000_0001_ECX] = 2644 0, 2645 /* VMX features from Yonah */ 2646 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2647 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2648 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2649 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2650 VMX_PIN_BASED_NMI_EXITING, 2651 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2652 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2653 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2654 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2655 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 2656 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 2657 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS, 2658 .xlevel = 0x80000008, 2659 .model_id = "Common 32-bit KVM processor" 2660 }, 2661 { 2662 .name = "coreduo", 2663 .level = 10, 2664 .vendor = CPUID_VENDOR_INTEL, 2665 .family = 6, 2666 .model = 14, 2667 .stepping = 8, 2668 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2669 .features[FEAT_1_EDX] = 2670 PPRO_FEATURES | CPUID_VME | 2671 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI | 2672 CPUID_SS, 2673 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR, 2674 * CPUID_EXT_PDCM, CPUID_EXT_VMX */ 2675 .features[FEAT_1_ECX] = 2676 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR, 2677 .features[FEAT_8000_0001_EDX] = 2678 CPUID_EXT2_NX, 2679 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2680 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2681 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2682 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2683 VMX_PIN_BASED_NMI_EXITING, 2684 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2685 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2686 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2687 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2688 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 2689 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 2690 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS, 2691 .xlevel = 0x80000008, 2692 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz", 2693 }, 2694 { 2695 .name = "486", 2696 .level = 1, 2697 .vendor = CPUID_VENDOR_INTEL, 2698 .family = 4, 2699 .model = 8, 2700 .stepping = 0, 2701 .features[FEAT_1_EDX] = 2702 I486_FEATURES, 2703 .xlevel = 0, 2704 .model_id = "", 2705 }, 2706 { 2707 .name = "pentium", 2708 .level = 1, 2709 .vendor = CPUID_VENDOR_INTEL, 2710 .family = 5, 2711 .model = 4, 2712 .stepping = 3, 2713 .features[FEAT_1_EDX] = 2714 PENTIUM_FEATURES, 2715 .xlevel = 0, 2716 .model_id = "", 2717 }, 2718 { 2719 .name = "pentium2", 2720 .level = 2, 2721 .vendor = CPUID_VENDOR_INTEL, 2722 .family = 6, 2723 .model = 5, 2724 .stepping = 2, 2725 .features[FEAT_1_EDX] = 2726 PENTIUM2_FEATURES, 2727 .xlevel = 0, 2728 .model_id = "", 2729 }, 2730 { 2731 .name = "pentium3", 2732 .level = 3, 2733 .vendor = CPUID_VENDOR_INTEL, 2734 .family = 6, 2735 .model = 7, 2736 .stepping = 3, 2737 .features[FEAT_1_EDX] = 2738 PENTIUM3_FEATURES, 2739 .xlevel = 0, 2740 .model_id = "", 2741 }, 2742 { 2743 .name = "athlon", 2744 .level = 2, 2745 .vendor = CPUID_VENDOR_AMD, 2746 .family = 6, 2747 .model = 2, 2748 .stepping = 3, 2749 .features[FEAT_1_EDX] = 2750 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR | 2751 CPUID_MCA, 2752 .features[FEAT_8000_0001_EDX] = 2753 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT, 2754 .xlevel = 0x80000008, 2755 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 2756 }, 2757 { 2758 .name = "n270", 2759 .level = 10, 2760 .vendor = CPUID_VENDOR_INTEL, 2761 .family = 6, 2762 .model = 28, 2763 .stepping = 2, 2764 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2765 .features[FEAT_1_EDX] = 2766 PPRO_FEATURES | 2767 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | 2768 CPUID_ACPI | CPUID_SS, 2769 /* Some CPUs got no CPUID_SEP */ 2770 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2, 2771 * CPUID_EXT_XTPR */ 2772 .features[FEAT_1_ECX] = 2773 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | 2774 CPUID_EXT_MOVBE, 2775 .features[FEAT_8000_0001_EDX] = 2776 CPUID_EXT2_NX, 2777 .features[FEAT_8000_0001_ECX] = 2778 CPUID_EXT3_LAHF_LM, 2779 .xlevel = 0x80000008, 2780 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz", 2781 }, 2782 { 2783 .name = "Conroe", 2784 .level = 10, 2785 .vendor = CPUID_VENDOR_INTEL, 2786 .family = 6, 2787 .model = 15, 2788 .stepping = 3, 2789 .features[FEAT_1_EDX] = 2790 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2791 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2792 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2793 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2794 CPUID_DE | CPUID_FP87, 2795 .features[FEAT_1_ECX] = 2796 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, 2797 .features[FEAT_8000_0001_EDX] = 2798 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 2799 .features[FEAT_8000_0001_ECX] = 2800 CPUID_EXT3_LAHF_LM, 2801 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2802 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2803 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2804 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2805 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2806 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2807 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2808 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2809 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2810 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2811 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2812 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2813 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2814 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2815 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2816 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2817 .features[FEAT_VMX_SECONDARY_CTLS] = 2818 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES, 2819 .xlevel = 0x80000008, 2820 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)", 2821 }, 2822 { 2823 .name = "Penryn", 2824 .level = 10, 2825 .vendor = CPUID_VENDOR_INTEL, 2826 .family = 6, 2827 .model = 23, 2828 .stepping = 3, 2829 .features[FEAT_1_EDX] = 2830 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2831 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2832 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2833 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2834 CPUID_DE | CPUID_FP87, 2835 .features[FEAT_1_ECX] = 2836 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2837 CPUID_EXT_SSE3, 2838 .features[FEAT_8000_0001_EDX] = 2839 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 2840 .features[FEAT_8000_0001_ECX] = 2841 CPUID_EXT3_LAHF_LM, 2842 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2843 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2844 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, 2845 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT | 2846 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL, 2847 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2848 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2849 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2850 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2851 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2852 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2853 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2854 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2855 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2856 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2857 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2858 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2859 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2860 .features[FEAT_VMX_SECONDARY_CTLS] = 2861 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2862 VMX_SECONDARY_EXEC_WBINVD_EXITING, 2863 .xlevel = 0x80000008, 2864 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)", 2865 }, 2866 { 2867 .name = "Nehalem", 2868 .level = 11, 2869 .vendor = CPUID_VENDOR_INTEL, 2870 .family = 6, 2871 .model = 26, 2872 .stepping = 3, 2873 .features[FEAT_1_EDX] = 2874 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2875 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2876 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2877 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2878 CPUID_DE | CPUID_FP87, 2879 .features[FEAT_1_ECX] = 2880 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 2881 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, 2882 .features[FEAT_8000_0001_EDX] = 2883 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2884 .features[FEAT_8000_0001_ECX] = 2885 CPUID_EXT3_LAHF_LM, 2886 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2887 MSR_VMX_BASIC_TRUE_CTLS, 2888 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2889 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2890 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2891 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2892 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2893 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2894 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2895 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2896 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2897 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2898 .features[FEAT_VMX_EXIT_CTLS] = 2899 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2900 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2901 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2902 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2903 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2904 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2905 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2906 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2907 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2908 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2909 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2910 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2911 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2912 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2913 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2914 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2915 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2916 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2917 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2918 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2919 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2920 .features[FEAT_VMX_SECONDARY_CTLS] = 2921 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2922 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2923 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2924 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2925 VMX_SECONDARY_EXEC_ENABLE_VPID, 2926 .xlevel = 0x80000008, 2927 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)", 2928 .versions = (X86CPUVersionDefinition[]) { 2929 { .version = 1 }, 2930 { 2931 .version = 2, 2932 .alias = "Nehalem-IBRS", 2933 .props = (PropValue[]) { 2934 { "spec-ctrl", "on" }, 2935 { "model-id", 2936 "Intel Core i7 9xx (Nehalem Core i7, IBRS update)" }, 2937 { /* end of list */ } 2938 } 2939 }, 2940 { /* end of list */ } 2941 } 2942 }, 2943 { 2944 .name = "Westmere", 2945 .level = 11, 2946 .vendor = CPUID_VENDOR_INTEL, 2947 .family = 6, 2948 .model = 44, 2949 .stepping = 1, 2950 .features[FEAT_1_EDX] = 2951 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2952 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2953 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2954 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2955 CPUID_DE | CPUID_FP87, 2956 .features[FEAT_1_ECX] = 2957 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | 2958 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2959 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 2960 .features[FEAT_8000_0001_EDX] = 2961 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2962 .features[FEAT_8000_0001_ECX] = 2963 CPUID_EXT3_LAHF_LM, 2964 .features[FEAT_6_EAX] = 2965 CPUID_6_EAX_ARAT, 2966 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2967 MSR_VMX_BASIC_TRUE_CTLS, 2968 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2969 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2970 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2971 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2972 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2973 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2974 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2975 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2976 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2977 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2978 .features[FEAT_VMX_EXIT_CTLS] = 2979 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2980 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2981 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2982 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2983 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2984 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2985 MSR_VMX_MISC_STORE_LMA, 2986 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2987 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2988 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2989 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2990 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2991 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2992 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2993 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2994 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2995 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2996 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2997 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2998 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2999 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3000 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3001 .features[FEAT_VMX_SECONDARY_CTLS] = 3002 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3003 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3004 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3005 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3006 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST, 3007 .xlevel = 0x80000008, 3008 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)", 3009 .versions = (X86CPUVersionDefinition[]) { 3010 { .version = 1 }, 3011 { 3012 .version = 2, 3013 .alias = "Westmere-IBRS", 3014 .props = (PropValue[]) { 3015 { "spec-ctrl", "on" }, 3016 { "model-id", 3017 "Westmere E56xx/L56xx/X56xx (IBRS update)" }, 3018 { /* end of list */ } 3019 } 3020 }, 3021 { /* end of list */ } 3022 } 3023 }, 3024 { 3025 .name = "SandyBridge", 3026 .level = 0xd, 3027 .vendor = CPUID_VENDOR_INTEL, 3028 .family = 6, 3029 .model = 42, 3030 .stepping = 1, 3031 .features[FEAT_1_EDX] = 3032 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3033 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3034 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3035 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3036 CPUID_DE | CPUID_FP87, 3037 .features[FEAT_1_ECX] = 3038 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3039 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | 3040 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 3041 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 3042 CPUID_EXT_SSE3, 3043 .features[FEAT_8000_0001_EDX] = 3044 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3045 CPUID_EXT2_SYSCALL, 3046 .features[FEAT_8000_0001_ECX] = 3047 CPUID_EXT3_LAHF_LM, 3048 .features[FEAT_XSAVE] = 3049 CPUID_XSAVE_XSAVEOPT, 3050 .features[FEAT_6_EAX] = 3051 CPUID_6_EAX_ARAT, 3052 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3053 MSR_VMX_BASIC_TRUE_CTLS, 3054 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3055 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3056 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3057 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3058 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3059 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3060 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3061 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3062 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3063 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 3064 .features[FEAT_VMX_EXIT_CTLS] = 3065 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3066 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3067 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3068 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3069 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3070 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3071 MSR_VMX_MISC_STORE_LMA, 3072 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3073 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3074 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 3075 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3076 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3077 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3078 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3079 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3080 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3081 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3082 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3083 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3084 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3085 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3086 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3087 .features[FEAT_VMX_SECONDARY_CTLS] = 3088 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3089 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3090 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3091 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3092 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST, 3093 .xlevel = 0x80000008, 3094 .model_id = "Intel Xeon E312xx (Sandy Bridge)", 3095 .versions = (X86CPUVersionDefinition[]) { 3096 { .version = 1 }, 3097 { 3098 .version = 2, 3099 .alias = "SandyBridge-IBRS", 3100 .props = (PropValue[]) { 3101 { "spec-ctrl", "on" }, 3102 { "model-id", 3103 "Intel Xeon E312xx (Sandy Bridge, IBRS update)" }, 3104 { /* end of list */ } 3105 } 3106 }, 3107 { /* end of list */ } 3108 } 3109 }, 3110 { 3111 .name = "IvyBridge", 3112 .level = 0xd, 3113 .vendor = CPUID_VENDOR_INTEL, 3114 .family = 6, 3115 .model = 58, 3116 .stepping = 9, 3117 .features[FEAT_1_EDX] = 3118 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3119 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3120 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3121 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3122 CPUID_DE | CPUID_FP87, 3123 .features[FEAT_1_ECX] = 3124 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3125 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | 3126 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 3127 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 3128 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3129 .features[FEAT_7_0_EBX] = 3130 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | 3131 CPUID_7_0_EBX_ERMS, 3132 .features[FEAT_8000_0001_EDX] = 3133 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3134 CPUID_EXT2_SYSCALL, 3135 .features[FEAT_8000_0001_ECX] = 3136 CPUID_EXT3_LAHF_LM, 3137 .features[FEAT_XSAVE] = 3138 CPUID_XSAVE_XSAVEOPT, 3139 .features[FEAT_6_EAX] = 3140 CPUID_6_EAX_ARAT, 3141 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3142 MSR_VMX_BASIC_TRUE_CTLS, 3143 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3144 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3145 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3146 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3147 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3148 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3149 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3150 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3151 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3152 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 3153 .features[FEAT_VMX_EXIT_CTLS] = 3154 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3155 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3156 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3157 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3158 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3159 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3160 MSR_VMX_MISC_STORE_LMA, 3161 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3162 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3163 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3164 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3165 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3166 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3167 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3168 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3169 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3170 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3171 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3172 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3173 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3174 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3175 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3176 .features[FEAT_VMX_SECONDARY_CTLS] = 3177 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3178 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3179 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3180 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3181 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3182 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3183 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3184 VMX_SECONDARY_EXEC_RDRAND_EXITING, 3185 .xlevel = 0x80000008, 3186 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)", 3187 .versions = (X86CPUVersionDefinition[]) { 3188 { .version = 1 }, 3189 { 3190 .version = 2, 3191 .alias = "IvyBridge-IBRS", 3192 .props = (PropValue[]) { 3193 { "spec-ctrl", "on" }, 3194 { "model-id", 3195 "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)" }, 3196 { /* end of list */ } 3197 } 3198 }, 3199 { /* end of list */ } 3200 } 3201 }, 3202 { 3203 .name = "Haswell", 3204 .level = 0xd, 3205 .vendor = CPUID_VENDOR_INTEL, 3206 .family = 6, 3207 .model = 60, 3208 .stepping = 4, 3209 .features[FEAT_1_EDX] = 3210 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3211 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3212 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3213 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3214 CPUID_DE | CPUID_FP87, 3215 .features[FEAT_1_ECX] = 3216 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3217 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3218 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3219 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3220 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3221 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3222 .features[FEAT_8000_0001_EDX] = 3223 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3224 CPUID_EXT2_SYSCALL, 3225 .features[FEAT_8000_0001_ECX] = 3226 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM, 3227 .features[FEAT_7_0_EBX] = 3228 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3229 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3230 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3231 CPUID_7_0_EBX_RTM, 3232 .features[FEAT_XSAVE] = 3233 CPUID_XSAVE_XSAVEOPT, 3234 .features[FEAT_6_EAX] = 3235 CPUID_6_EAX_ARAT, 3236 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3237 MSR_VMX_BASIC_TRUE_CTLS, 3238 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3239 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3240 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3241 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3242 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3243 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3244 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3245 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3246 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3247 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3248 .features[FEAT_VMX_EXIT_CTLS] = 3249 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3250 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3251 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3252 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3253 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3254 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3255 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3256 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3257 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3258 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3259 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3260 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3261 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3262 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3263 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3264 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3265 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3266 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3267 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3268 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3269 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3270 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3271 .features[FEAT_VMX_SECONDARY_CTLS] = 3272 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3273 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3274 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3275 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3276 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3277 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3278 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3279 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3280 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS, 3281 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3282 .xlevel = 0x80000008, 3283 .model_id = "Intel Core Processor (Haswell)", 3284 .versions = (X86CPUVersionDefinition[]) { 3285 { .version = 1 }, 3286 { 3287 .version = 2, 3288 .alias = "Haswell-noTSX", 3289 .props = (PropValue[]) { 3290 { "hle", "off" }, 3291 { "rtm", "off" }, 3292 { "stepping", "1" }, 3293 { "model-id", "Intel Core Processor (Haswell, no TSX)", }, 3294 { /* end of list */ } 3295 }, 3296 }, 3297 { 3298 .version = 3, 3299 .alias = "Haswell-IBRS", 3300 .props = (PropValue[]) { 3301 /* Restore TSX features removed by -v2 above */ 3302 { "hle", "on" }, 3303 { "rtm", "on" }, 3304 /* 3305 * Haswell and Haswell-IBRS had stepping=4 in 3306 * QEMU 4.0 and older 3307 */ 3308 { "stepping", "4" }, 3309 { "spec-ctrl", "on" }, 3310 { "model-id", 3311 "Intel Core Processor (Haswell, IBRS)" }, 3312 { /* end of list */ } 3313 } 3314 }, 3315 { 3316 .version = 4, 3317 .alias = "Haswell-noTSX-IBRS", 3318 .props = (PropValue[]) { 3319 { "hle", "off" }, 3320 { "rtm", "off" }, 3321 /* spec-ctrl was already enabled by -v3 above */ 3322 { "stepping", "1" }, 3323 { "model-id", 3324 "Intel Core Processor (Haswell, no TSX, IBRS)" }, 3325 { /* end of list */ } 3326 } 3327 }, 3328 { /* end of list */ } 3329 } 3330 }, 3331 { 3332 .name = "Broadwell", 3333 .level = 0xd, 3334 .vendor = CPUID_VENDOR_INTEL, 3335 .family = 6, 3336 .model = 61, 3337 .stepping = 2, 3338 .features[FEAT_1_EDX] = 3339 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3340 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3341 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3342 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3343 CPUID_DE | CPUID_FP87, 3344 .features[FEAT_1_ECX] = 3345 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3346 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3347 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3348 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3349 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3350 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3351 .features[FEAT_8000_0001_EDX] = 3352 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3353 CPUID_EXT2_SYSCALL, 3354 .features[FEAT_8000_0001_ECX] = 3355 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3356 .features[FEAT_7_0_EBX] = 3357 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3358 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3359 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3360 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3361 CPUID_7_0_EBX_SMAP, 3362 .features[FEAT_XSAVE] = 3363 CPUID_XSAVE_XSAVEOPT, 3364 .features[FEAT_6_EAX] = 3365 CPUID_6_EAX_ARAT, 3366 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3367 MSR_VMX_BASIC_TRUE_CTLS, 3368 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3369 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3370 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3371 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3372 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3373 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3374 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3375 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3376 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3377 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3378 .features[FEAT_VMX_EXIT_CTLS] = 3379 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3380 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3381 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3382 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3383 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3384 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3385 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3386 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3387 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3388 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3389 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3390 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3391 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3392 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3393 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3394 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3395 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3396 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3397 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3398 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3399 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3400 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3401 .features[FEAT_VMX_SECONDARY_CTLS] = 3402 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3403 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3404 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3405 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3406 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3407 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3408 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3409 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3410 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3411 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3412 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3413 .xlevel = 0x80000008, 3414 .model_id = "Intel Core Processor (Broadwell)", 3415 .versions = (X86CPUVersionDefinition[]) { 3416 { .version = 1 }, 3417 { 3418 .version = 2, 3419 .alias = "Broadwell-noTSX", 3420 .props = (PropValue[]) { 3421 { "hle", "off" }, 3422 { "rtm", "off" }, 3423 { "model-id", "Intel Core Processor (Broadwell, no TSX)", }, 3424 { /* end of list */ } 3425 }, 3426 }, 3427 { 3428 .version = 3, 3429 .alias = "Broadwell-IBRS", 3430 .props = (PropValue[]) { 3431 /* Restore TSX features removed by -v2 above */ 3432 { "hle", "on" }, 3433 { "rtm", "on" }, 3434 { "spec-ctrl", "on" }, 3435 { "model-id", 3436 "Intel Core Processor (Broadwell, IBRS)" }, 3437 { /* end of list */ } 3438 } 3439 }, 3440 { 3441 .version = 4, 3442 .alias = "Broadwell-noTSX-IBRS", 3443 .props = (PropValue[]) { 3444 { "hle", "off" }, 3445 { "rtm", "off" }, 3446 /* spec-ctrl was already enabled by -v3 above */ 3447 { "model-id", 3448 "Intel Core Processor (Broadwell, no TSX, IBRS)" }, 3449 { /* end of list */ } 3450 } 3451 }, 3452 { /* end of list */ } 3453 } 3454 }, 3455 { 3456 .name = "Skylake-Client", 3457 .level = 0xd, 3458 .vendor = CPUID_VENDOR_INTEL, 3459 .family = 6, 3460 .model = 94, 3461 .stepping = 3, 3462 .features[FEAT_1_EDX] = 3463 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3464 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3465 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3466 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3467 CPUID_DE | CPUID_FP87, 3468 .features[FEAT_1_ECX] = 3469 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3470 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3471 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3472 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3473 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3474 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3475 .features[FEAT_8000_0001_EDX] = 3476 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3477 CPUID_EXT2_SYSCALL, 3478 .features[FEAT_8000_0001_ECX] = 3479 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3480 .features[FEAT_7_0_EBX] = 3481 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3482 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3483 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3484 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3485 CPUID_7_0_EBX_SMAP, 3486 /* XSAVES is added in version 4 */ 3487 .features[FEAT_XSAVE] = 3488 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3489 CPUID_XSAVE_XGETBV1, 3490 .features[FEAT_6_EAX] = 3491 CPUID_6_EAX_ARAT, 3492 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3493 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3494 MSR_VMX_BASIC_TRUE_CTLS, 3495 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3496 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3497 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3498 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3499 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3500 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3501 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3502 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3503 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3504 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3505 .features[FEAT_VMX_EXIT_CTLS] = 3506 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3507 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3508 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3509 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3510 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3511 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3512 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3513 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3514 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3515 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 3516 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3517 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3518 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3519 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3520 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3521 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3522 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3523 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3524 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3525 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3526 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3527 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3528 .features[FEAT_VMX_SECONDARY_CTLS] = 3529 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3530 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3531 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3532 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3533 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3534 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3535 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3536 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3537 .xlevel = 0x80000008, 3538 .model_id = "Intel Core Processor (Skylake)", 3539 .versions = (X86CPUVersionDefinition[]) { 3540 { .version = 1 }, 3541 { 3542 .version = 2, 3543 .alias = "Skylake-Client-IBRS", 3544 .props = (PropValue[]) { 3545 { "spec-ctrl", "on" }, 3546 { "model-id", 3547 "Intel Core Processor (Skylake, IBRS)" }, 3548 { /* end of list */ } 3549 } 3550 }, 3551 { 3552 .version = 3, 3553 .alias = "Skylake-Client-noTSX-IBRS", 3554 .props = (PropValue[]) { 3555 { "hle", "off" }, 3556 { "rtm", "off" }, 3557 { "model-id", 3558 "Intel Core Processor (Skylake, IBRS, no TSX)" }, 3559 { /* end of list */ } 3560 } 3561 }, 3562 { 3563 .version = 4, 3564 .note = "IBRS, XSAVES, no TSX", 3565 .props = (PropValue[]) { 3566 { "xsaves", "on" }, 3567 { "vmx-xsaves", "on" }, 3568 { /* end of list */ } 3569 } 3570 }, 3571 { /* end of list */ } 3572 } 3573 }, 3574 { 3575 .name = "Skylake-Server", 3576 .level = 0xd, 3577 .vendor = CPUID_VENDOR_INTEL, 3578 .family = 6, 3579 .model = 85, 3580 .stepping = 4, 3581 .features[FEAT_1_EDX] = 3582 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3583 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3584 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3585 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3586 CPUID_DE | CPUID_FP87, 3587 .features[FEAT_1_ECX] = 3588 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3589 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3590 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3591 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3592 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3593 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3594 .features[FEAT_8000_0001_EDX] = 3595 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3596 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3597 .features[FEAT_8000_0001_ECX] = 3598 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3599 .features[FEAT_7_0_EBX] = 3600 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3601 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3602 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3603 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3604 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3605 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3606 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3607 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3608 .features[FEAT_7_0_ECX] = 3609 CPUID_7_0_ECX_PKU, 3610 /* XSAVES is added in version 5 */ 3611 .features[FEAT_XSAVE] = 3612 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3613 CPUID_XSAVE_XGETBV1, 3614 .features[FEAT_6_EAX] = 3615 CPUID_6_EAX_ARAT, 3616 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3617 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3618 MSR_VMX_BASIC_TRUE_CTLS, 3619 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3620 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3621 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3622 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3623 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3624 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3625 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3626 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3627 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3628 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3629 .features[FEAT_VMX_EXIT_CTLS] = 3630 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3631 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3632 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3633 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3634 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3635 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3636 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3637 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3638 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3639 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3640 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3641 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3642 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3643 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3644 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3645 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3646 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3647 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3648 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3649 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3650 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3651 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3652 .features[FEAT_VMX_SECONDARY_CTLS] = 3653 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3654 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3655 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3656 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3657 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3658 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3659 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3660 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3661 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3662 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3663 .xlevel = 0x80000008, 3664 .model_id = "Intel Xeon Processor (Skylake)", 3665 .versions = (X86CPUVersionDefinition[]) { 3666 { .version = 1 }, 3667 { 3668 .version = 2, 3669 .alias = "Skylake-Server-IBRS", 3670 .props = (PropValue[]) { 3671 /* clflushopt was not added to Skylake-Server-IBRS */ 3672 /* TODO: add -v3 including clflushopt */ 3673 { "clflushopt", "off" }, 3674 { "spec-ctrl", "on" }, 3675 { "model-id", 3676 "Intel Xeon Processor (Skylake, IBRS)" }, 3677 { /* end of list */ } 3678 } 3679 }, 3680 { 3681 .version = 3, 3682 .alias = "Skylake-Server-noTSX-IBRS", 3683 .props = (PropValue[]) { 3684 { "hle", "off" }, 3685 { "rtm", "off" }, 3686 { "model-id", 3687 "Intel Xeon Processor (Skylake, IBRS, no TSX)" }, 3688 { /* end of list */ } 3689 } 3690 }, 3691 { 3692 .version = 4, 3693 .note = "IBRS, EPT switching, no TSX", 3694 .props = (PropValue[]) { 3695 { "vmx-eptp-switching", "on" }, 3696 { /* end of list */ } 3697 } 3698 }, 3699 { 3700 .version = 5, 3701 .note = "IBRS, XSAVES, EPT switching, no TSX", 3702 .props = (PropValue[]) { 3703 { "xsaves", "on" }, 3704 { "vmx-xsaves", "on" }, 3705 { /* end of list */ } 3706 } 3707 }, 3708 { /* end of list */ } 3709 } 3710 }, 3711 { 3712 .name = "Cascadelake-Server", 3713 .level = 0xd, 3714 .vendor = CPUID_VENDOR_INTEL, 3715 .family = 6, 3716 .model = 85, 3717 .stepping = 6, 3718 .features[FEAT_1_EDX] = 3719 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3720 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3721 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3722 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3723 CPUID_DE | CPUID_FP87, 3724 .features[FEAT_1_ECX] = 3725 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3726 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3727 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3728 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3729 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3730 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3731 .features[FEAT_8000_0001_EDX] = 3732 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3733 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3734 .features[FEAT_8000_0001_ECX] = 3735 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3736 .features[FEAT_7_0_EBX] = 3737 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3738 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3739 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3740 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3741 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3742 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3743 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3744 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3745 .features[FEAT_7_0_ECX] = 3746 CPUID_7_0_ECX_PKU | 3747 CPUID_7_0_ECX_AVX512VNNI, 3748 .features[FEAT_7_0_EDX] = 3749 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 3750 /* XSAVES is added in version 5 */ 3751 .features[FEAT_XSAVE] = 3752 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3753 CPUID_XSAVE_XGETBV1, 3754 .features[FEAT_6_EAX] = 3755 CPUID_6_EAX_ARAT, 3756 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3757 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3758 MSR_VMX_BASIC_TRUE_CTLS, 3759 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3760 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3761 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3762 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3763 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3764 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3765 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3766 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3767 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3768 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3769 .features[FEAT_VMX_EXIT_CTLS] = 3770 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3771 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3772 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3773 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3774 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3775 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3776 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3777 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3778 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3779 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3780 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3781 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3782 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3783 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3784 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3785 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3786 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3787 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3788 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3789 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3790 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3791 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3792 .features[FEAT_VMX_SECONDARY_CTLS] = 3793 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3794 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3795 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3796 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3797 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3798 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3799 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3800 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3801 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3802 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3803 .xlevel = 0x80000008, 3804 .model_id = "Intel Xeon Processor (Cascadelake)", 3805 .versions = (X86CPUVersionDefinition[]) { 3806 { .version = 1 }, 3807 { .version = 2, 3808 .note = "ARCH_CAPABILITIES", 3809 .props = (PropValue[]) { 3810 { "arch-capabilities", "on" }, 3811 { "rdctl-no", "on" }, 3812 { "ibrs-all", "on" }, 3813 { "skip-l1dfl-vmentry", "on" }, 3814 { "mds-no", "on" }, 3815 { /* end of list */ } 3816 }, 3817 }, 3818 { .version = 3, 3819 .alias = "Cascadelake-Server-noTSX", 3820 .note = "ARCH_CAPABILITIES, no TSX", 3821 .props = (PropValue[]) { 3822 { "hle", "off" }, 3823 { "rtm", "off" }, 3824 { /* end of list */ } 3825 }, 3826 }, 3827 { .version = 4, 3828 .note = "ARCH_CAPABILITIES, EPT switching, no TSX", 3829 .props = (PropValue[]) { 3830 { "vmx-eptp-switching", "on" }, 3831 { /* end of list */ } 3832 }, 3833 }, 3834 { .version = 5, 3835 .note = "ARCH_CAPABILITIES, EPT switching, XSAVES, no TSX", 3836 .props = (PropValue[]) { 3837 { "xsaves", "on" }, 3838 { "vmx-xsaves", "on" }, 3839 { /* end of list */ } 3840 }, 3841 }, 3842 { /* end of list */ } 3843 } 3844 }, 3845 { 3846 .name = "Cooperlake", 3847 .level = 0xd, 3848 .vendor = CPUID_VENDOR_INTEL, 3849 .family = 6, 3850 .model = 85, 3851 .stepping = 10, 3852 .features[FEAT_1_EDX] = 3853 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3854 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3855 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3856 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3857 CPUID_DE | CPUID_FP87, 3858 .features[FEAT_1_ECX] = 3859 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3860 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3861 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3862 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3863 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3864 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3865 .features[FEAT_8000_0001_EDX] = 3866 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3867 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3868 .features[FEAT_8000_0001_ECX] = 3869 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3870 .features[FEAT_7_0_EBX] = 3871 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3872 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3873 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3874 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3875 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3876 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3877 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3878 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3879 .features[FEAT_7_0_ECX] = 3880 CPUID_7_0_ECX_PKU | 3881 CPUID_7_0_ECX_AVX512VNNI, 3882 .features[FEAT_7_0_EDX] = 3883 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_STIBP | 3884 CPUID_7_0_EDX_SPEC_CTRL_SSBD | CPUID_7_0_EDX_ARCH_CAPABILITIES, 3885 .features[FEAT_ARCH_CAPABILITIES] = 3886 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 3887 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 3888 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO, 3889 .features[FEAT_7_1_EAX] = 3890 CPUID_7_1_EAX_AVX512_BF16, 3891 /* XSAVES is added in version 2 */ 3892 .features[FEAT_XSAVE] = 3893 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3894 CPUID_XSAVE_XGETBV1, 3895 .features[FEAT_6_EAX] = 3896 CPUID_6_EAX_ARAT, 3897 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3898 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3899 MSR_VMX_BASIC_TRUE_CTLS, 3900 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3901 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3902 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3903 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3904 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3905 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3906 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3907 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3908 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3909 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3910 .features[FEAT_VMX_EXIT_CTLS] = 3911 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3912 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3913 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3914 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3915 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3916 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3917 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3918 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3919 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3920 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3921 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3922 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3923 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3924 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3925 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3926 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3927 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3928 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3929 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3930 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3931 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3932 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3933 .features[FEAT_VMX_SECONDARY_CTLS] = 3934 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3935 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3936 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3937 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3938 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3939 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3940 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3941 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3942 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3943 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3944 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3945 .xlevel = 0x80000008, 3946 .model_id = "Intel Xeon Processor (Cooperlake)", 3947 .versions = (X86CPUVersionDefinition[]) { 3948 { .version = 1 }, 3949 { .version = 2, 3950 .note = "XSAVES", 3951 .props = (PropValue[]) { 3952 { "xsaves", "on" }, 3953 { "vmx-xsaves", "on" }, 3954 { /* end of list */ } 3955 }, 3956 }, 3957 { /* end of list */ } 3958 } 3959 }, 3960 { 3961 .name = "Icelake-Server", 3962 .level = 0xd, 3963 .vendor = CPUID_VENDOR_INTEL, 3964 .family = 6, 3965 .model = 134, 3966 .stepping = 0, 3967 .features[FEAT_1_EDX] = 3968 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3969 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3970 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3971 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3972 CPUID_DE | CPUID_FP87, 3973 .features[FEAT_1_ECX] = 3974 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3975 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3976 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3977 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3978 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3979 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3980 .features[FEAT_8000_0001_EDX] = 3981 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3982 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3983 .features[FEAT_8000_0001_ECX] = 3984 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3985 .features[FEAT_8000_0008_EBX] = 3986 CPUID_8000_0008_EBX_WBNOINVD, 3987 .features[FEAT_7_0_EBX] = 3988 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3989 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3990 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3991 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3992 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3993 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3994 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3995 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3996 .features[FEAT_7_0_ECX] = 3997 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 3998 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 3999 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4000 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 4001 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57, 4002 .features[FEAT_7_0_EDX] = 4003 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4004 /* XSAVES is added in version 5 */ 4005 .features[FEAT_XSAVE] = 4006 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4007 CPUID_XSAVE_XGETBV1, 4008 .features[FEAT_6_EAX] = 4009 CPUID_6_EAX_ARAT, 4010 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 4011 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 4012 MSR_VMX_BASIC_TRUE_CTLS, 4013 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 4014 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 4015 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 4016 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 4017 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 4018 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 4019 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4020 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4021 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4022 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 4023 .features[FEAT_VMX_EXIT_CTLS] = 4024 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4025 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4026 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 4027 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4028 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4029 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 4030 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 4031 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 4032 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 4033 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 4034 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4035 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4036 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4037 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4038 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4039 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 4040 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 4041 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 4042 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 4043 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4044 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4045 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4046 .features[FEAT_VMX_SECONDARY_CTLS] = 4047 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4048 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 4049 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 4050 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4051 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4052 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4053 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4054 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4055 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS, 4056 .xlevel = 0x80000008, 4057 .model_id = "Intel Xeon Processor (Icelake)", 4058 .versions = (X86CPUVersionDefinition[]) { 4059 { .version = 1 }, 4060 { 4061 .version = 2, 4062 .note = "no TSX", 4063 .alias = "Icelake-Server-noTSX", 4064 .props = (PropValue[]) { 4065 { "hle", "off" }, 4066 { "rtm", "off" }, 4067 { /* end of list */ } 4068 }, 4069 }, 4070 { 4071 .version = 3, 4072 .props = (PropValue[]) { 4073 { "arch-capabilities", "on" }, 4074 { "rdctl-no", "on" }, 4075 { "ibrs-all", "on" }, 4076 { "skip-l1dfl-vmentry", "on" }, 4077 { "mds-no", "on" }, 4078 { "pschange-mc-no", "on" }, 4079 { "taa-no", "on" }, 4080 { /* end of list */ } 4081 }, 4082 }, 4083 { 4084 .version = 4, 4085 .props = (PropValue[]) { 4086 { "sha-ni", "on" }, 4087 { "avx512ifma", "on" }, 4088 { "rdpid", "on" }, 4089 { "fsrm", "on" }, 4090 { "vmx-rdseed-exit", "on" }, 4091 { "vmx-pml", "on" }, 4092 { "vmx-eptp-switching", "on" }, 4093 { "model", "106" }, 4094 { /* end of list */ } 4095 }, 4096 }, 4097 { 4098 .version = 5, 4099 .note = "XSAVES", 4100 .props = (PropValue[]) { 4101 { "xsaves", "on" }, 4102 { "vmx-xsaves", "on" }, 4103 { /* end of list */ } 4104 }, 4105 }, 4106 { 4107 .version = 6, 4108 .note = "5-level EPT", 4109 .props = (PropValue[]) { 4110 { "vmx-page-walk-5", "on" }, 4111 { /* end of list */ } 4112 }, 4113 }, 4114 { 4115 .version = 7, 4116 .note = "TSX, taa-no", 4117 .props = (PropValue[]) { 4118 /* Restore TSX features removed by -v2 above */ 4119 { "hle", "on" }, 4120 { "rtm", "on" }, 4121 { /* end of list */ } 4122 }, 4123 }, 4124 { /* end of list */ } 4125 } 4126 }, 4127 { 4128 .name = "SapphireRapids", 4129 .level = 0x20, 4130 .vendor = CPUID_VENDOR_INTEL, 4131 .family = 6, 4132 .model = 143, 4133 .stepping = 4, 4134 /* 4135 * please keep the ascending order so that we can have a clear view of 4136 * bit position of each feature. 4137 */ 4138 .features[FEAT_1_EDX] = 4139 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4140 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4141 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4142 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4143 CPUID_SSE | CPUID_SSE2, 4144 .features[FEAT_1_ECX] = 4145 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 4146 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 4147 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4148 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 4149 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4150 .features[FEAT_8000_0001_EDX] = 4151 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4152 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4153 .features[FEAT_8000_0001_ECX] = 4154 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 4155 .features[FEAT_8000_0008_EBX] = 4156 CPUID_8000_0008_EBX_WBNOINVD, 4157 .features[FEAT_7_0_EBX] = 4158 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_HLE | 4159 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | 4160 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RTM | 4161 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 4162 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | 4163 CPUID_7_0_EBX_AVX512IFMA | CPUID_7_0_EBX_CLFLUSHOPT | 4164 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | 4165 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, 4166 .features[FEAT_7_0_ECX] = 4167 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 4168 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 4169 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4170 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 4171 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | 4172 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT, 4173 .features[FEAT_7_0_EDX] = 4174 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 4175 CPUID_7_0_EDX_TSX_LDTRK | CPUID_7_0_EDX_AMX_BF16 | 4176 CPUID_7_0_EDX_AVX512_FP16 | CPUID_7_0_EDX_AMX_TILE | 4177 CPUID_7_0_EDX_AMX_INT8 | CPUID_7_0_EDX_SPEC_CTRL | 4178 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4179 .features[FEAT_ARCH_CAPABILITIES] = 4180 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 4181 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 4182 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO, 4183 .features[FEAT_XSAVE] = 4184 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4185 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES | CPUID_D_1_EAX_XFD, 4186 .features[FEAT_6_EAX] = 4187 CPUID_6_EAX_ARAT, 4188 .features[FEAT_7_1_EAX] = 4189 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_AVX512_BF16 | 4190 CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC, 4191 .features[FEAT_VMX_BASIC] = 4192 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 4193 .features[FEAT_VMX_ENTRY_CTLS] = 4194 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 4195 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 4196 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 4197 .features[FEAT_VMX_EPT_VPID_CAPS] = 4198 MSR_VMX_EPT_EXECONLY | 4199 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_PAGE_WALK_LENGTH_5 | 4200 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 4201 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 4202 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4203 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4204 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 4205 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4206 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 4207 .features[FEAT_VMX_EXIT_CTLS] = 4208 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4209 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4210 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 4211 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4212 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4213 .features[FEAT_VMX_MISC] = 4214 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 4215 MSR_VMX_MISC_VMWRITE_VMEXIT, 4216 .features[FEAT_VMX_PINBASED_CTLS] = 4217 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 4218 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 4219 VMX_PIN_BASED_POSTED_INTR, 4220 .features[FEAT_VMX_PROCBASED_CTLS] = 4221 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4222 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4223 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4224 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4225 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4226 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4227 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 4228 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 4229 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4230 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 4231 VMX_CPU_BASED_PAUSE_EXITING | 4232 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4233 .features[FEAT_VMX_SECONDARY_CTLS] = 4234 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4235 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 4236 VMX_SECONDARY_EXEC_RDTSCP | 4237 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4238 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 4239 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4240 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4241 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4242 VMX_SECONDARY_EXEC_RDRAND_EXITING | 4243 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4244 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4245 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 4246 VMX_SECONDARY_EXEC_XSAVES, 4247 .features[FEAT_VMX_VMFUNC] = 4248 MSR_VMX_VMFUNC_EPT_SWITCHING, 4249 .xlevel = 0x80000008, 4250 .model_id = "Intel Xeon Processor (SapphireRapids)", 4251 .versions = (X86CPUVersionDefinition[]) { 4252 { .version = 1 }, 4253 { 4254 .version = 2, 4255 .props = (PropValue[]) { 4256 { "sbdr-ssdp-no", "on" }, 4257 { "fbsdp-no", "on" }, 4258 { "psdp-no", "on" }, 4259 { /* end of list */ } 4260 } 4261 }, 4262 { 4263 .version = 3, 4264 .props = (PropValue[]) { 4265 { "ss", "on" }, 4266 { "tsc-adjust", "on" }, 4267 { "cldemote", "on" }, 4268 { "movdiri", "on" }, 4269 { "movdir64b", "on" }, 4270 { /* end of list */ } 4271 } 4272 }, 4273 { /* end of list */ } 4274 } 4275 }, 4276 { 4277 .name = "GraniteRapids", 4278 .level = 0x20, 4279 .vendor = CPUID_VENDOR_INTEL, 4280 .family = 6, 4281 .model = 173, 4282 .stepping = 0, 4283 /* 4284 * please keep the ascending order so that we can have a clear view of 4285 * bit position of each feature. 4286 */ 4287 .features[FEAT_1_EDX] = 4288 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4289 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4290 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4291 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4292 CPUID_SSE | CPUID_SSE2, 4293 .features[FEAT_1_ECX] = 4294 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 4295 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 4296 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4297 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 4298 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4299 .features[FEAT_8000_0001_EDX] = 4300 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4301 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4302 .features[FEAT_8000_0001_ECX] = 4303 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 4304 .features[FEAT_8000_0008_EBX] = 4305 CPUID_8000_0008_EBX_WBNOINVD, 4306 .features[FEAT_7_0_EBX] = 4307 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_HLE | 4308 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | 4309 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RTM | 4310 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 4311 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | 4312 CPUID_7_0_EBX_AVX512IFMA | CPUID_7_0_EBX_CLFLUSHOPT | 4313 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | 4314 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, 4315 .features[FEAT_7_0_ECX] = 4316 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 4317 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 4318 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4319 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 4320 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | 4321 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT, 4322 .features[FEAT_7_0_EDX] = 4323 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 4324 CPUID_7_0_EDX_TSX_LDTRK | CPUID_7_0_EDX_AMX_BF16 | 4325 CPUID_7_0_EDX_AVX512_FP16 | CPUID_7_0_EDX_AMX_TILE | 4326 CPUID_7_0_EDX_AMX_INT8 | CPUID_7_0_EDX_SPEC_CTRL | 4327 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4328 .features[FEAT_ARCH_CAPABILITIES] = 4329 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 4330 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 4331 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO | 4332 MSR_ARCH_CAP_SBDR_SSDP_NO | MSR_ARCH_CAP_FBSDP_NO | 4333 MSR_ARCH_CAP_PSDP_NO | MSR_ARCH_CAP_PBRSB_NO, 4334 .features[FEAT_XSAVE] = 4335 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4336 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES | CPUID_D_1_EAX_XFD, 4337 .features[FEAT_6_EAX] = 4338 CPUID_6_EAX_ARAT, 4339 .features[FEAT_7_1_EAX] = 4340 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_AVX512_BF16 | 4341 CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC | 4342 CPUID_7_1_EAX_AMX_FP16, 4343 .features[FEAT_7_1_EDX] = 4344 CPUID_7_1_EDX_PREFETCHITI, 4345 .features[FEAT_7_2_EDX] = 4346 CPUID_7_2_EDX_MCDT_NO, 4347 .features[FEAT_VMX_BASIC] = 4348 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 4349 .features[FEAT_VMX_ENTRY_CTLS] = 4350 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 4351 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 4352 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 4353 .features[FEAT_VMX_EPT_VPID_CAPS] = 4354 MSR_VMX_EPT_EXECONLY | 4355 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_PAGE_WALK_LENGTH_5 | 4356 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 4357 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 4358 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4359 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4360 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 4361 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4362 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 4363 .features[FEAT_VMX_EXIT_CTLS] = 4364 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4365 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4366 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 4367 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4368 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4369 .features[FEAT_VMX_MISC] = 4370 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 4371 MSR_VMX_MISC_VMWRITE_VMEXIT, 4372 .features[FEAT_VMX_PINBASED_CTLS] = 4373 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 4374 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 4375 VMX_PIN_BASED_POSTED_INTR, 4376 .features[FEAT_VMX_PROCBASED_CTLS] = 4377 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4378 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4379 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4380 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4381 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4382 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4383 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 4384 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 4385 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4386 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 4387 VMX_CPU_BASED_PAUSE_EXITING | 4388 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4389 .features[FEAT_VMX_SECONDARY_CTLS] = 4390 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4391 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 4392 VMX_SECONDARY_EXEC_RDTSCP | 4393 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4394 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 4395 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4396 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4397 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4398 VMX_SECONDARY_EXEC_RDRAND_EXITING | 4399 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4400 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4401 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 4402 VMX_SECONDARY_EXEC_XSAVES, 4403 .features[FEAT_VMX_VMFUNC] = 4404 MSR_VMX_VMFUNC_EPT_SWITCHING, 4405 .xlevel = 0x80000008, 4406 .model_id = "Intel Xeon Processor (GraniteRapids)", 4407 .versions = (X86CPUVersionDefinition[]) { 4408 { .version = 1 }, 4409 { 4410 .version = 2, 4411 .props = (PropValue[]) { 4412 { "ss", "on" }, 4413 { "tsc-adjust", "on" }, 4414 { "cldemote", "on" }, 4415 { "movdiri", "on" }, 4416 { "movdir64b", "on" }, 4417 { "avx10", "on" }, 4418 { "avx10-128", "on" }, 4419 { "avx10-256", "on" }, 4420 { "avx10-512", "on" }, 4421 { "avx10-version", "1" }, 4422 { "stepping", "1" }, 4423 { /* end of list */ } 4424 } 4425 }, 4426 { /* end of list */ }, 4427 }, 4428 }, 4429 { 4430 .name = "SierraForest", 4431 .level = 0x23, 4432 .vendor = CPUID_VENDOR_INTEL, 4433 .family = 6, 4434 .model = 175, 4435 .stepping = 0, 4436 /* 4437 * please keep the ascending order so that we can have a clear view of 4438 * bit position of each feature. 4439 */ 4440 .features[FEAT_1_EDX] = 4441 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4442 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4443 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4444 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4445 CPUID_SSE | CPUID_SSE2, 4446 .features[FEAT_1_ECX] = 4447 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 4448 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 4449 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4450 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 4451 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4452 .features[FEAT_8000_0001_EDX] = 4453 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4454 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4455 .features[FEAT_8000_0001_ECX] = 4456 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 4457 .features[FEAT_8000_0008_EBX] = 4458 CPUID_8000_0008_EBX_WBNOINVD, 4459 .features[FEAT_7_0_EBX] = 4460 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4461 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 4462 CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 4463 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB | 4464 CPUID_7_0_EBX_SHA_NI, 4465 .features[FEAT_7_0_ECX] = 4466 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_GFNI | 4467 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4468 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT, 4469 .features[FEAT_7_0_EDX] = 4470 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 4471 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES | 4472 CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4473 .features[FEAT_ARCH_CAPABILITIES] = 4474 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 4475 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 4476 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_SBDR_SSDP_NO | 4477 MSR_ARCH_CAP_FBSDP_NO | MSR_ARCH_CAP_PSDP_NO | 4478 MSR_ARCH_CAP_PBRSB_NO, 4479 .features[FEAT_XSAVE] = 4480 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4481 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 4482 .features[FEAT_6_EAX] = 4483 CPUID_6_EAX_ARAT, 4484 .features[FEAT_7_1_EAX] = 4485 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_CMPCCXADD | 4486 CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_AVX_IFMA, 4487 .features[FEAT_7_1_EDX] = 4488 CPUID_7_1_EDX_AVX_VNNI_INT8 | CPUID_7_1_EDX_AVX_NE_CONVERT, 4489 .features[FEAT_7_2_EDX] = 4490 CPUID_7_2_EDX_MCDT_NO, 4491 .features[FEAT_VMX_BASIC] = 4492 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 4493 .features[FEAT_VMX_ENTRY_CTLS] = 4494 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 4495 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 4496 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 4497 .features[FEAT_VMX_EPT_VPID_CAPS] = 4498 MSR_VMX_EPT_EXECONLY | MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | 4499 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 4500 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 4501 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4502 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4503 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 4504 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4505 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 4506 .features[FEAT_VMX_EXIT_CTLS] = 4507 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4508 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4509 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 4510 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4511 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4512 .features[FEAT_VMX_MISC] = 4513 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 4514 MSR_VMX_MISC_VMWRITE_VMEXIT, 4515 .features[FEAT_VMX_PINBASED_CTLS] = 4516 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 4517 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 4518 VMX_PIN_BASED_POSTED_INTR, 4519 .features[FEAT_VMX_PROCBASED_CTLS] = 4520 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4521 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4522 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4523 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4524 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4525 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4526 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 4527 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 4528 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4529 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 4530 VMX_CPU_BASED_PAUSE_EXITING | 4531 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4532 .features[FEAT_VMX_SECONDARY_CTLS] = 4533 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4534 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 4535 VMX_SECONDARY_EXEC_RDTSCP | 4536 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4537 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 4538 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4539 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4540 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4541 VMX_SECONDARY_EXEC_RDRAND_EXITING | 4542 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4543 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4544 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 4545 VMX_SECONDARY_EXEC_XSAVES, 4546 .features[FEAT_VMX_VMFUNC] = 4547 MSR_VMX_VMFUNC_EPT_SWITCHING, 4548 .xlevel = 0x80000008, 4549 .model_id = "Intel Xeon Processor (SierraForest)", 4550 .versions = (X86CPUVersionDefinition[]) { 4551 { .version = 1 }, 4552 { /* end of list */ }, 4553 }, 4554 }, 4555 { 4556 .name = "Denverton", 4557 .level = 21, 4558 .vendor = CPUID_VENDOR_INTEL, 4559 .family = 6, 4560 .model = 95, 4561 .stepping = 1, 4562 .features[FEAT_1_EDX] = 4563 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4564 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4565 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4566 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4567 CPUID_SSE | CPUID_SSE2, 4568 .features[FEAT_1_ECX] = 4569 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR | 4570 CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_SSE41 | 4571 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4572 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | 4573 CPUID_EXT_AES | CPUID_EXT_XSAVE | CPUID_EXT_RDRAND, 4574 .features[FEAT_8000_0001_EDX] = 4575 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4576 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4577 .features[FEAT_8000_0001_ECX] = 4578 CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 4579 .features[FEAT_7_0_EBX] = 4580 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_ERMS | 4581 CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_SMAP | 4582 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_SHA_NI, 4583 .features[FEAT_7_0_EDX] = 4584 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES | 4585 CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4586 /* XSAVES is added in version 3 */ 4587 .features[FEAT_XSAVE] = 4588 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | CPUID_XSAVE_XGETBV1, 4589 .features[FEAT_6_EAX] = 4590 CPUID_6_EAX_ARAT, 4591 .features[FEAT_ARCH_CAPABILITIES] = 4592 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY, 4593 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 4594 MSR_VMX_BASIC_TRUE_CTLS, 4595 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 4596 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 4597 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 4598 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 4599 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 4600 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 4601 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4602 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4603 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4604 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 4605 .features[FEAT_VMX_EXIT_CTLS] = 4606 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4607 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4608 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 4609 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4610 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4611 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 4612 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 4613 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 4614 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 4615 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 4616 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4617 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4618 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4619 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4620 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4621 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 4622 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 4623 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 4624 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 4625 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4626 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4627 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4628 .features[FEAT_VMX_SECONDARY_CTLS] = 4629 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4630 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 4631 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 4632 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4633 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4634 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4635 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4636 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4637 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4638 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 4639 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 4640 .xlevel = 0x80000008, 4641 .model_id = "Intel Atom Processor (Denverton)", 4642 .versions = (X86CPUVersionDefinition[]) { 4643 { .version = 1 }, 4644 { 4645 .version = 2, 4646 .note = "no MPX, no MONITOR", 4647 .props = (PropValue[]) { 4648 { "monitor", "off" }, 4649 { "mpx", "off" }, 4650 { /* end of list */ }, 4651 }, 4652 }, 4653 { 4654 .version = 3, 4655 .note = "XSAVES, no MPX, no MONITOR", 4656 .props = (PropValue[]) { 4657 { "xsaves", "on" }, 4658 { "vmx-xsaves", "on" }, 4659 { /* end of list */ }, 4660 }, 4661 }, 4662 { /* end of list */ }, 4663 }, 4664 }, 4665 { 4666 .name = "Snowridge", 4667 .level = 27, 4668 .vendor = CPUID_VENDOR_INTEL, 4669 .family = 6, 4670 .model = 134, 4671 .stepping = 1, 4672 .features[FEAT_1_EDX] = 4673 /* missing: CPUID_PN CPUID_IA64 */ 4674 /* missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 4675 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | 4676 CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_MCE | 4677 CPUID_CX8 | CPUID_APIC | CPUID_SEP | 4678 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4679 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | 4680 CPUID_MMX | 4681 CPUID_FXSR | CPUID_SSE | CPUID_SSE2, 4682 .features[FEAT_1_ECX] = 4683 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR | 4684 CPUID_EXT_SSSE3 | 4685 CPUID_EXT_CX16 | 4686 CPUID_EXT_SSE41 | 4687 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4688 CPUID_EXT_POPCNT | 4689 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | CPUID_EXT_XSAVE | 4690 CPUID_EXT_RDRAND, 4691 .features[FEAT_8000_0001_EDX] = 4692 CPUID_EXT2_SYSCALL | 4693 CPUID_EXT2_NX | 4694 CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 4695 CPUID_EXT2_LM, 4696 .features[FEAT_8000_0001_ECX] = 4697 CPUID_EXT3_LAHF_LM | 4698 CPUID_EXT3_3DNOWPREFETCH, 4699 .features[FEAT_7_0_EBX] = 4700 CPUID_7_0_EBX_FSGSBASE | 4701 CPUID_7_0_EBX_SMEP | 4702 CPUID_7_0_EBX_ERMS | 4703 CPUID_7_0_EBX_MPX | /* missing bits 13, 15 */ 4704 CPUID_7_0_EBX_RDSEED | 4705 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 4706 CPUID_7_0_EBX_CLWB | 4707 CPUID_7_0_EBX_SHA_NI, 4708 .features[FEAT_7_0_ECX] = 4709 CPUID_7_0_ECX_UMIP | 4710 /* missing bit 5 */ 4711 CPUID_7_0_ECX_GFNI | 4712 CPUID_7_0_ECX_MOVDIRI | CPUID_7_0_ECX_CLDEMOTE | 4713 CPUID_7_0_ECX_MOVDIR64B, 4714 .features[FEAT_7_0_EDX] = 4715 CPUID_7_0_EDX_SPEC_CTRL | 4716 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD | 4717 CPUID_7_0_EDX_CORE_CAPABILITY, 4718 .features[FEAT_CORE_CAPABILITY] = 4719 MSR_CORE_CAP_SPLIT_LOCK_DETECT, 4720 /* XSAVES is added in version 3 */ 4721 .features[FEAT_XSAVE] = 4722 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4723 CPUID_XSAVE_XGETBV1, 4724 .features[FEAT_6_EAX] = 4725 CPUID_6_EAX_ARAT, 4726 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 4727 MSR_VMX_BASIC_TRUE_CTLS, 4728 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 4729 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 4730 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 4731 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 4732 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 4733 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 4734 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4735 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4736 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4737 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 4738 .features[FEAT_VMX_EXIT_CTLS] = 4739 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4740 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4741 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 4742 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4743 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4744 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 4745 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 4746 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 4747 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 4748 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 4749 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4750 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4751 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4752 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4753 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4754 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 4755 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 4756 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 4757 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 4758 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4759 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4760 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4761 .features[FEAT_VMX_SECONDARY_CTLS] = 4762 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4763 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 4764 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 4765 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4766 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4767 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4768 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4769 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4770 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4771 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 4772 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 4773 .xlevel = 0x80000008, 4774 .model_id = "Intel Atom Processor (SnowRidge)", 4775 .versions = (X86CPUVersionDefinition[]) { 4776 { .version = 1 }, 4777 { 4778 .version = 2, 4779 .props = (PropValue[]) { 4780 { "mpx", "off" }, 4781 { "model-id", "Intel Atom Processor (Snowridge, no MPX)" }, 4782 { /* end of list */ }, 4783 }, 4784 }, 4785 { 4786 .version = 3, 4787 .note = "XSAVES, no MPX", 4788 .props = (PropValue[]) { 4789 { "xsaves", "on" }, 4790 { "vmx-xsaves", "on" }, 4791 { /* end of list */ }, 4792 }, 4793 }, 4794 { 4795 .version = 4, 4796 .note = "no split lock detect, no core-capability", 4797 .props = (PropValue[]) { 4798 { "split-lock-detect", "off" }, 4799 { "core-capability", "off" }, 4800 { /* end of list */ }, 4801 }, 4802 }, 4803 { /* end of list */ }, 4804 }, 4805 }, 4806 { 4807 .name = "KnightsMill", 4808 .level = 0xd, 4809 .vendor = CPUID_VENDOR_INTEL, 4810 .family = 6, 4811 .model = 133, 4812 .stepping = 0, 4813 .features[FEAT_1_EDX] = 4814 CPUID_VME | CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | 4815 CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | 4816 CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | 4817 CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | 4818 CPUID_PSE | CPUID_DE | CPUID_FP87, 4819 .features[FEAT_1_ECX] = 4820 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 4821 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 4822 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 4823 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 4824 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 4825 CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4826 .features[FEAT_8000_0001_EDX] = 4827 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 4828 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 4829 .features[FEAT_8000_0001_ECX] = 4830 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 4831 .features[FEAT_7_0_EBX] = 4832 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4833 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 4834 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_AVX512F | 4835 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_AVX512PF | 4836 CPUID_7_0_EBX_AVX512ER, 4837 .features[FEAT_7_0_ECX] = 4838 CPUID_7_0_ECX_AVX512_VPOPCNTDQ, 4839 .features[FEAT_7_0_EDX] = 4840 CPUID_7_0_EDX_AVX512_4VNNIW | CPUID_7_0_EDX_AVX512_4FMAPS, 4841 .features[FEAT_XSAVE] = 4842 CPUID_XSAVE_XSAVEOPT, 4843 .features[FEAT_6_EAX] = 4844 CPUID_6_EAX_ARAT, 4845 .xlevel = 0x80000008, 4846 .model_id = "Intel Xeon Phi Processor (Knights Mill)", 4847 }, 4848 { 4849 .name = "Opteron_G1", 4850 .level = 5, 4851 .vendor = CPUID_VENDOR_AMD, 4852 .family = 15, 4853 .model = 6, 4854 .stepping = 1, 4855 .features[FEAT_1_EDX] = 4856 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4857 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4858 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4859 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4860 CPUID_DE | CPUID_FP87, 4861 .features[FEAT_1_ECX] = 4862 CPUID_EXT_SSE3, 4863 .features[FEAT_8000_0001_EDX] = 4864 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 4865 .xlevel = 0x80000008, 4866 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)", 4867 }, 4868 { 4869 .name = "Opteron_G2", 4870 .level = 5, 4871 .vendor = CPUID_VENDOR_AMD, 4872 .family = 15, 4873 .model = 6, 4874 .stepping = 1, 4875 .features[FEAT_1_EDX] = 4876 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4877 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4878 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4879 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4880 CPUID_DE | CPUID_FP87, 4881 .features[FEAT_1_ECX] = 4882 CPUID_EXT_CX16 | CPUID_EXT_SSE3, 4883 .features[FEAT_8000_0001_EDX] = 4884 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 4885 .features[FEAT_8000_0001_ECX] = 4886 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, 4887 .xlevel = 0x80000008, 4888 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)", 4889 }, 4890 { 4891 .name = "Opteron_G3", 4892 .level = 5, 4893 .vendor = CPUID_VENDOR_AMD, 4894 .family = 16, 4895 .model = 2, 4896 .stepping = 3, 4897 .features[FEAT_1_EDX] = 4898 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4899 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4900 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4901 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4902 CPUID_DE | CPUID_FP87, 4903 .features[FEAT_1_ECX] = 4904 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR | 4905 CPUID_EXT_SSE3, 4906 .features[FEAT_8000_0001_EDX] = 4907 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL | 4908 CPUID_EXT2_RDTSCP, 4909 .features[FEAT_8000_0001_ECX] = 4910 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | 4911 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, 4912 .xlevel = 0x80000008, 4913 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)", 4914 }, 4915 { 4916 .name = "Opteron_G4", 4917 .level = 0xd, 4918 .vendor = CPUID_VENDOR_AMD, 4919 .family = 21, 4920 .model = 1, 4921 .stepping = 2, 4922 .features[FEAT_1_EDX] = 4923 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4924 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4925 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4926 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4927 CPUID_DE | CPUID_FP87, 4928 .features[FEAT_1_ECX] = 4929 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 4930 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 4931 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 4932 CPUID_EXT_SSE3, 4933 .features[FEAT_8000_0001_EDX] = 4934 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX | 4935 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP, 4936 .features[FEAT_8000_0001_ECX] = 4937 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP | 4938 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | 4939 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | 4940 CPUID_EXT3_LAHF_LM, 4941 .features[FEAT_SVM] = 4942 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 4943 /* no xsaveopt! */ 4944 .xlevel = 0x8000001A, 4945 .model_id = "AMD Opteron 62xx class CPU", 4946 }, 4947 { 4948 .name = "Opteron_G5", 4949 .level = 0xd, 4950 .vendor = CPUID_VENDOR_AMD, 4951 .family = 21, 4952 .model = 2, 4953 .stepping = 0, 4954 .features[FEAT_1_EDX] = 4955 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4956 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4957 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4958 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4959 CPUID_DE | CPUID_FP87, 4960 .features[FEAT_1_ECX] = 4961 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE | 4962 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | 4963 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA | 4964 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 4965 .features[FEAT_8000_0001_EDX] = 4966 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX | 4967 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP, 4968 .features[FEAT_8000_0001_ECX] = 4969 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP | 4970 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | 4971 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | 4972 CPUID_EXT3_LAHF_LM, 4973 .features[FEAT_SVM] = 4974 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 4975 /* no xsaveopt! */ 4976 .xlevel = 0x8000001A, 4977 .model_id = "AMD Opteron 63xx class CPU", 4978 }, 4979 { 4980 .name = "EPYC", 4981 .level = 0xd, 4982 .vendor = CPUID_VENDOR_AMD, 4983 .family = 23, 4984 .model = 1, 4985 .stepping = 2, 4986 .features[FEAT_1_EDX] = 4987 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 4988 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 4989 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 4990 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 4991 CPUID_VME | CPUID_FP87, 4992 .features[FEAT_1_ECX] = 4993 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 4994 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 4995 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 4996 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 4997 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 4998 .features[FEAT_8000_0001_EDX] = 4999 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5000 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5001 CPUID_EXT2_SYSCALL, 5002 .features[FEAT_8000_0001_ECX] = 5003 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5004 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5005 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5006 CPUID_EXT3_TOPOEXT, 5007 .features[FEAT_7_0_EBX] = 5008 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5009 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 5010 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 5011 CPUID_7_0_EBX_SHA_NI, 5012 .features[FEAT_XSAVE] = 5013 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5014 CPUID_XSAVE_XGETBV1, 5015 .features[FEAT_6_EAX] = 5016 CPUID_6_EAX_ARAT, 5017 .features[FEAT_SVM] = 5018 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 5019 .xlevel = 0x8000001E, 5020 .model_id = "AMD EPYC Processor", 5021 .cache_info = &epyc_cache_info, 5022 .versions = (X86CPUVersionDefinition[]) { 5023 { .version = 1 }, 5024 { 5025 .version = 2, 5026 .alias = "EPYC-IBPB", 5027 .props = (PropValue[]) { 5028 { "ibpb", "on" }, 5029 { "model-id", 5030 "AMD EPYC Processor (with IBPB)" }, 5031 { /* end of list */ } 5032 } 5033 }, 5034 { 5035 .version = 3, 5036 .props = (PropValue[]) { 5037 { "ibpb", "on" }, 5038 { "perfctr-core", "on" }, 5039 { "clzero", "on" }, 5040 { "xsaveerptr", "on" }, 5041 { "xsaves", "on" }, 5042 { "model-id", 5043 "AMD EPYC Processor" }, 5044 { /* end of list */ } 5045 } 5046 }, 5047 { 5048 .version = 4, 5049 .props = (PropValue[]) { 5050 { "model-id", 5051 "AMD EPYC-v4 Processor" }, 5052 { /* end of list */ } 5053 }, 5054 .cache_info = &epyc_v4_cache_info 5055 }, 5056 { /* end of list */ } 5057 } 5058 }, 5059 { 5060 .name = "Dhyana", 5061 .level = 0xd, 5062 .vendor = CPUID_VENDOR_HYGON, 5063 .family = 24, 5064 .model = 0, 5065 .stepping = 1, 5066 .features[FEAT_1_EDX] = 5067 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 5068 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 5069 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 5070 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 5071 CPUID_VME | CPUID_FP87, 5072 .features[FEAT_1_ECX] = 5073 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5074 CPUID_EXT_XSAVE | CPUID_EXT_POPCNT | 5075 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5076 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 5077 CPUID_EXT_MONITOR | CPUID_EXT_SSE3, 5078 .features[FEAT_8000_0001_EDX] = 5079 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5080 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5081 CPUID_EXT2_SYSCALL, 5082 .features[FEAT_8000_0001_ECX] = 5083 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5084 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5085 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5086 CPUID_EXT3_TOPOEXT, 5087 .features[FEAT_8000_0008_EBX] = 5088 CPUID_8000_0008_EBX_IBPB, 5089 .features[FEAT_7_0_EBX] = 5090 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5091 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 5092 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT, 5093 /* XSAVES is added in version 2 */ 5094 .features[FEAT_XSAVE] = 5095 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5096 CPUID_XSAVE_XGETBV1, 5097 .features[FEAT_6_EAX] = 5098 CPUID_6_EAX_ARAT, 5099 .features[FEAT_SVM] = 5100 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 5101 .xlevel = 0x8000001E, 5102 .model_id = "Hygon Dhyana Processor", 5103 .cache_info = &epyc_cache_info, 5104 .versions = (X86CPUVersionDefinition[]) { 5105 { .version = 1 }, 5106 { .version = 2, 5107 .note = "XSAVES", 5108 .props = (PropValue[]) { 5109 { "xsaves", "on" }, 5110 { /* end of list */ } 5111 }, 5112 }, 5113 { /* end of list */ } 5114 } 5115 }, 5116 { 5117 .name = "EPYC-Rome", 5118 .level = 0xd, 5119 .vendor = CPUID_VENDOR_AMD, 5120 .family = 23, 5121 .model = 49, 5122 .stepping = 0, 5123 .features[FEAT_1_EDX] = 5124 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 5125 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 5126 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 5127 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 5128 CPUID_VME | CPUID_FP87, 5129 .features[FEAT_1_ECX] = 5130 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5131 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 5132 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5133 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 5134 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 5135 .features[FEAT_8000_0001_EDX] = 5136 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5137 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5138 CPUID_EXT2_SYSCALL, 5139 .features[FEAT_8000_0001_ECX] = 5140 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5141 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5142 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5143 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 5144 .features[FEAT_8000_0008_EBX] = 5145 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 5146 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 5147 CPUID_8000_0008_EBX_STIBP, 5148 .features[FEAT_7_0_EBX] = 5149 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5150 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 5151 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 5152 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB, 5153 .features[FEAT_7_0_ECX] = 5154 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID, 5155 .features[FEAT_XSAVE] = 5156 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5157 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 5158 .features[FEAT_6_EAX] = 5159 CPUID_6_EAX_ARAT, 5160 .features[FEAT_SVM] = 5161 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 5162 .xlevel = 0x8000001E, 5163 .model_id = "AMD EPYC-Rome Processor", 5164 .cache_info = &epyc_rome_cache_info, 5165 .versions = (X86CPUVersionDefinition[]) { 5166 { .version = 1 }, 5167 { 5168 .version = 2, 5169 .props = (PropValue[]) { 5170 { "ibrs", "on" }, 5171 { "amd-ssbd", "on" }, 5172 { /* end of list */ } 5173 } 5174 }, 5175 { 5176 .version = 3, 5177 .props = (PropValue[]) { 5178 { "model-id", 5179 "AMD EPYC-Rome-v3 Processor" }, 5180 { /* end of list */ } 5181 }, 5182 .cache_info = &epyc_rome_v3_cache_info 5183 }, 5184 { 5185 .version = 4, 5186 .props = (PropValue[]) { 5187 /* Erratum 1386 */ 5188 { "model-id", 5189 "AMD EPYC-Rome-v4 Processor (no XSAVES)" }, 5190 { "xsaves", "off" }, 5191 { /* end of list */ } 5192 }, 5193 }, 5194 { /* end of list */ } 5195 } 5196 }, 5197 { 5198 .name = "EPYC-Milan", 5199 .level = 0xd, 5200 .vendor = CPUID_VENDOR_AMD, 5201 .family = 25, 5202 .model = 1, 5203 .stepping = 1, 5204 .features[FEAT_1_EDX] = 5205 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 5206 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 5207 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 5208 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 5209 CPUID_VME | CPUID_FP87, 5210 .features[FEAT_1_ECX] = 5211 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5212 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 5213 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5214 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 5215 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 5216 CPUID_EXT_PCID, 5217 .features[FEAT_8000_0001_EDX] = 5218 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5219 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5220 CPUID_EXT2_SYSCALL, 5221 .features[FEAT_8000_0001_ECX] = 5222 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5223 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5224 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5225 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 5226 .features[FEAT_8000_0008_EBX] = 5227 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 5228 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 5229 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | 5230 CPUID_8000_0008_EBX_AMD_SSBD, 5231 .features[FEAT_7_0_EBX] = 5232 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5233 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 5234 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 5235 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_ERMS | 5236 CPUID_7_0_EBX_INVPCID, 5237 .features[FEAT_7_0_ECX] = 5238 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_PKU, 5239 .features[FEAT_7_0_EDX] = 5240 CPUID_7_0_EDX_FSRM, 5241 .features[FEAT_XSAVE] = 5242 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5243 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 5244 .features[FEAT_6_EAX] = 5245 CPUID_6_EAX_ARAT, 5246 .features[FEAT_SVM] = 5247 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE | CPUID_SVM_SVME_ADDR_CHK, 5248 .xlevel = 0x8000001E, 5249 .model_id = "AMD EPYC-Milan Processor", 5250 .cache_info = &epyc_milan_cache_info, 5251 .versions = (X86CPUVersionDefinition[]) { 5252 { .version = 1 }, 5253 { 5254 .version = 2, 5255 .props = (PropValue[]) { 5256 { "model-id", 5257 "AMD EPYC-Milan-v2 Processor" }, 5258 { "vaes", "on" }, 5259 { "vpclmulqdq", "on" }, 5260 { "stibp-always-on", "on" }, 5261 { "amd-psfd", "on" }, 5262 { "no-nested-data-bp", "on" }, 5263 { "lfence-always-serializing", "on" }, 5264 { "null-sel-clr-base", "on" }, 5265 { /* end of list */ } 5266 }, 5267 .cache_info = &epyc_milan_v2_cache_info 5268 }, 5269 { /* end of list */ } 5270 } 5271 }, 5272 { 5273 .name = "EPYC-Genoa", 5274 .level = 0xd, 5275 .vendor = CPUID_VENDOR_AMD, 5276 .family = 25, 5277 .model = 17, 5278 .stepping = 0, 5279 .features[FEAT_1_EDX] = 5280 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 5281 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 5282 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 5283 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 5284 CPUID_VME | CPUID_FP87, 5285 .features[FEAT_1_ECX] = 5286 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5287 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 5288 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5289 CPUID_EXT_PCID | CPUID_EXT_CX16 | CPUID_EXT_FMA | 5290 CPUID_EXT_SSSE3 | CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | 5291 CPUID_EXT_SSE3, 5292 .features[FEAT_8000_0001_EDX] = 5293 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5294 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5295 CPUID_EXT2_SYSCALL, 5296 .features[FEAT_8000_0001_ECX] = 5297 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5298 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5299 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5300 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 5301 .features[FEAT_8000_0008_EBX] = 5302 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 5303 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 5304 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | 5305 CPUID_8000_0008_EBX_STIBP_ALWAYS_ON | 5306 CPUID_8000_0008_EBX_AMD_SSBD | CPUID_8000_0008_EBX_AMD_PSFD, 5307 .features[FEAT_8000_0021_EAX] = 5308 CPUID_8000_0021_EAX_NO_NESTED_DATA_BP | 5309 CPUID_8000_0021_EAX_LFENCE_ALWAYS_SERIALIZING | 5310 CPUID_8000_0021_EAX_NULL_SEL_CLR_BASE | 5311 CPUID_8000_0021_EAX_AUTO_IBRS, 5312 .features[FEAT_7_0_EBX] = 5313 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5314 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 5315 CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_AVX512F | 5316 CPUID_7_0_EBX_AVX512DQ | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 5317 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_AVX512IFMA | 5318 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB | 5319 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | 5320 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, 5321 .features[FEAT_7_0_ECX] = 5322 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 5323 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 5324 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 5325 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 5326 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | 5327 CPUID_7_0_ECX_RDPID, 5328 .features[FEAT_7_0_EDX] = 5329 CPUID_7_0_EDX_FSRM, 5330 .features[FEAT_7_1_EAX] = 5331 CPUID_7_1_EAX_AVX512_BF16, 5332 .features[FEAT_XSAVE] = 5333 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5334 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 5335 .features[FEAT_6_EAX] = 5336 CPUID_6_EAX_ARAT, 5337 .features[FEAT_SVM] = 5338 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE | CPUID_SVM_VNMI | 5339 CPUID_SVM_SVME_ADDR_CHK, 5340 .xlevel = 0x80000022, 5341 .model_id = "AMD EPYC-Genoa Processor", 5342 .cache_info = &epyc_genoa_cache_info, 5343 }, 5344 }; 5345 5346 /* 5347 * We resolve CPU model aliases using -v1 when using "-machine 5348 * none", but this is just for compatibility while libvirt isn't 5349 * adapted to resolve CPU model versions before creating VMs. 5350 * See "Runnability guarantee of CPU models" at 5351 * docs/about/deprecated.rst. 5352 */ 5353 X86CPUVersion default_cpu_version = 1; 5354 5355 void x86_cpu_set_default_version(X86CPUVersion version) 5356 { 5357 /* Translating CPU_VERSION_AUTO to CPU_VERSION_AUTO doesn't make sense */ 5358 assert(version != CPU_VERSION_AUTO); 5359 default_cpu_version = version; 5360 } 5361 5362 static X86CPUVersion x86_cpu_model_last_version(const X86CPUModel *model) 5363 { 5364 int v = 0; 5365 const X86CPUVersionDefinition *vdef = 5366 x86_cpu_def_get_versions(model->cpudef); 5367 while (vdef->version) { 5368 v = vdef->version; 5369 vdef++; 5370 } 5371 return v; 5372 } 5373 5374 /* Return the actual version being used for a specific CPU model */ 5375 static X86CPUVersion x86_cpu_model_resolve_version(const X86CPUModel *model) 5376 { 5377 X86CPUVersion v = model->version; 5378 if (v == CPU_VERSION_AUTO) { 5379 v = default_cpu_version; 5380 } 5381 if (v == CPU_VERSION_LATEST) { 5382 return x86_cpu_model_last_version(model); 5383 } 5384 return v; 5385 } 5386 5387 static const Property max_x86_cpu_properties[] = { 5388 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true), 5389 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false), 5390 }; 5391 5392 static void max_x86_cpu_realize(DeviceState *dev, Error **errp) 5393 { 5394 Object *obj = OBJECT(dev); 5395 5396 if (!object_property_get_int(obj, "family", &error_abort)) { 5397 if (X86_CPU(obj)->env.features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 5398 object_property_set_int(obj, "family", 15, &error_abort); 5399 object_property_set_int(obj, "model", 107, &error_abort); 5400 object_property_set_int(obj, "stepping", 1, &error_abort); 5401 } else { 5402 object_property_set_int(obj, "family", 6, &error_abort); 5403 object_property_set_int(obj, "model", 6, &error_abort); 5404 object_property_set_int(obj, "stepping", 3, &error_abort); 5405 } 5406 } 5407 5408 x86_cpu_realizefn(dev, errp); 5409 } 5410 5411 static void max_x86_cpu_class_init(ObjectClass *oc, void *data) 5412 { 5413 DeviceClass *dc = DEVICE_CLASS(oc); 5414 X86CPUClass *xcc = X86_CPU_CLASS(oc); 5415 5416 xcc->ordering = 9; 5417 5418 xcc->model_description = 5419 "Enables all features supported by the accelerator in the current host"; 5420 5421 device_class_set_props(dc, max_x86_cpu_properties); 5422 dc->realize = max_x86_cpu_realize; 5423 } 5424 5425 static void max_x86_cpu_initfn(Object *obj) 5426 { 5427 X86CPU *cpu = X86_CPU(obj); 5428 5429 /* We can't fill the features array here because we don't know yet if 5430 * "migratable" is true or false. 5431 */ 5432 cpu->max_features = true; 5433 object_property_set_bool(OBJECT(cpu), "pmu", true, &error_abort); 5434 5435 /* 5436 * these defaults are used for TCG and all other accelerators 5437 * besides KVM and HVF, which overwrite these values 5438 */ 5439 object_property_set_str(OBJECT(cpu), "vendor", CPUID_VENDOR_AMD, 5440 &error_abort); 5441 object_property_set_str(OBJECT(cpu), "model-id", 5442 "QEMU TCG CPU version " QEMU_HW_VERSION, 5443 &error_abort); 5444 } 5445 5446 static const TypeInfo max_x86_cpu_type_info = { 5447 .name = X86_CPU_TYPE_NAME("max"), 5448 .parent = TYPE_X86_CPU, 5449 .instance_init = max_x86_cpu_initfn, 5450 .class_init = max_x86_cpu_class_init, 5451 }; 5452 5453 static char *feature_word_description(FeatureWordInfo *f, uint32_t bit) 5454 { 5455 assert(f->type == CPUID_FEATURE_WORD || f->type == MSR_FEATURE_WORD); 5456 5457 switch (f->type) { 5458 case CPUID_FEATURE_WORD: 5459 { 5460 const char *reg = get_register_name_32(f->cpuid.reg); 5461 assert(reg); 5462 return g_strdup_printf("CPUID.%02XH:%s", 5463 f->cpuid.eax, reg); 5464 } 5465 case MSR_FEATURE_WORD: 5466 return g_strdup_printf("MSR(%02XH)", 5467 f->msr.index); 5468 } 5469 5470 return NULL; 5471 } 5472 5473 static bool x86_cpu_have_filtered_features(X86CPU *cpu) 5474 { 5475 FeatureWord w; 5476 5477 for (w = 0; w < FEATURE_WORDS; w++) { 5478 if (cpu->filtered_features[w]) { 5479 return true; 5480 } 5481 } 5482 5483 return false; 5484 } 5485 5486 static void mark_unavailable_features(X86CPU *cpu, FeatureWord w, uint64_t mask, 5487 const char *verbose_prefix) 5488 { 5489 CPUX86State *env = &cpu->env; 5490 FeatureWordInfo *f = &feature_word_info[w]; 5491 int i; 5492 5493 if (!cpu->force_features) { 5494 env->features[w] &= ~mask; 5495 } 5496 cpu->filtered_features[w] |= mask; 5497 5498 if (!verbose_prefix) { 5499 return; 5500 } 5501 5502 for (i = 0; i < 64; ++i) { 5503 if ((1ULL << i) & mask) { 5504 g_autofree char *feat_word_str = feature_word_description(f, i); 5505 warn_report("%s: %s%s%s [bit %d]", 5506 verbose_prefix, 5507 feat_word_str, 5508 f->feat_names[i] ? "." : "", 5509 f->feat_names[i] ? f->feat_names[i] : "", i); 5510 } 5511 } 5512 } 5513 5514 static void x86_cpuid_version_get_family(Object *obj, Visitor *v, 5515 const char *name, void *opaque, 5516 Error **errp) 5517 { 5518 X86CPU *cpu = X86_CPU(obj); 5519 CPUX86State *env = &cpu->env; 5520 uint64_t value; 5521 5522 value = (env->cpuid_version >> 8) & 0xf; 5523 if (value == 0xf) { 5524 value += (env->cpuid_version >> 20) & 0xff; 5525 } 5526 visit_type_uint64(v, name, &value, errp); 5527 } 5528 5529 static void x86_cpuid_version_set_family(Object *obj, Visitor *v, 5530 const char *name, void *opaque, 5531 Error **errp) 5532 { 5533 X86CPU *cpu = X86_CPU(obj); 5534 CPUX86State *env = &cpu->env; 5535 const uint64_t max = 0xff + 0xf; 5536 uint64_t value; 5537 5538 if (!visit_type_uint64(v, name, &value, errp)) { 5539 return; 5540 } 5541 if (value > max) { 5542 error_setg(errp, "parameter '%s' can be at most %" PRIu64, 5543 name ? name : "null", max); 5544 return; 5545 } 5546 5547 env->cpuid_version &= ~0xff00f00; 5548 if (value > 0x0f) { 5549 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20); 5550 } else { 5551 env->cpuid_version |= value << 8; 5552 } 5553 } 5554 5555 static void x86_cpuid_version_get_model(Object *obj, Visitor *v, 5556 const char *name, void *opaque, 5557 Error **errp) 5558 { 5559 X86CPU *cpu = X86_CPU(obj); 5560 CPUX86State *env = &cpu->env; 5561 uint64_t value; 5562 5563 value = (env->cpuid_version >> 4) & 0xf; 5564 value |= ((env->cpuid_version >> 16) & 0xf) << 4; 5565 visit_type_uint64(v, name, &value, errp); 5566 } 5567 5568 static void x86_cpuid_version_set_model(Object *obj, Visitor *v, 5569 const char *name, void *opaque, 5570 Error **errp) 5571 { 5572 X86CPU *cpu = X86_CPU(obj); 5573 CPUX86State *env = &cpu->env; 5574 const uint64_t max = 0xff; 5575 uint64_t value; 5576 5577 if (!visit_type_uint64(v, name, &value, errp)) { 5578 return; 5579 } 5580 if (value > max) { 5581 error_setg(errp, "parameter '%s' can be at most %" PRIu64, 5582 name ? name : "null", max); 5583 return; 5584 } 5585 5586 env->cpuid_version &= ~0xf00f0; 5587 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16); 5588 } 5589 5590 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v, 5591 const char *name, void *opaque, 5592 Error **errp) 5593 { 5594 X86CPU *cpu = X86_CPU(obj); 5595 CPUX86State *env = &cpu->env; 5596 uint64_t value; 5597 5598 value = env->cpuid_version & 0xf; 5599 visit_type_uint64(v, name, &value, errp); 5600 } 5601 5602 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v, 5603 const char *name, void *opaque, 5604 Error **errp) 5605 { 5606 X86CPU *cpu = X86_CPU(obj); 5607 CPUX86State *env = &cpu->env; 5608 const uint64_t max = 0xf; 5609 uint64_t value; 5610 5611 if (!visit_type_uint64(v, name, &value, errp)) { 5612 return; 5613 } 5614 if (value > max) { 5615 error_setg(errp, "parameter '%s' can be at most %" PRIu64, 5616 name ? name : "null", max); 5617 return; 5618 } 5619 5620 env->cpuid_version &= ~0xf; 5621 env->cpuid_version |= value & 0xf; 5622 } 5623 5624 static char *x86_cpuid_get_vendor(Object *obj, Error **errp) 5625 { 5626 X86CPU *cpu = X86_CPU(obj); 5627 CPUX86State *env = &cpu->env; 5628 char *value; 5629 5630 value = g_malloc(CPUID_VENDOR_SZ + 1); 5631 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2, 5632 env->cpuid_vendor3); 5633 return value; 5634 } 5635 5636 static void x86_cpuid_set_vendor(Object *obj, const char *value, 5637 Error **errp) 5638 { 5639 X86CPU *cpu = X86_CPU(obj); 5640 CPUX86State *env = &cpu->env; 5641 int i; 5642 5643 if (strlen(value) != CPUID_VENDOR_SZ) { 5644 error_setg(errp, "value of property 'vendor' must consist of" 5645 " exactly " stringify(CPUID_VENDOR_SZ) " characters"); 5646 return; 5647 } 5648 5649 env->cpuid_vendor1 = 0; 5650 env->cpuid_vendor2 = 0; 5651 env->cpuid_vendor3 = 0; 5652 for (i = 0; i < 4; i++) { 5653 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i); 5654 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i); 5655 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i); 5656 } 5657 } 5658 5659 static char *x86_cpuid_get_model_id(Object *obj, Error **errp) 5660 { 5661 X86CPU *cpu = X86_CPU(obj); 5662 CPUX86State *env = &cpu->env; 5663 char *value; 5664 int i; 5665 5666 value = g_malloc(48 + 1); 5667 for (i = 0; i < 48; i++) { 5668 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3)); 5669 } 5670 value[48] = '\0'; 5671 return value; 5672 } 5673 5674 static void x86_cpuid_set_model_id(Object *obj, const char *model_id, 5675 Error **errp) 5676 { 5677 X86CPU *cpu = X86_CPU(obj); 5678 CPUX86State *env = &cpu->env; 5679 int c, len, i; 5680 5681 if (model_id == NULL) { 5682 model_id = ""; 5683 } 5684 len = strlen(model_id); 5685 memset(env->cpuid_model, 0, 48); 5686 for (i = 0; i < 48; i++) { 5687 if (i >= len) { 5688 c = '\0'; 5689 } else { 5690 c = (uint8_t)model_id[i]; 5691 } 5692 env->cpuid_model[i >> 2] |= c << (8 * (i & 3)); 5693 } 5694 } 5695 5696 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name, 5697 void *opaque, Error **errp) 5698 { 5699 X86CPU *cpu = X86_CPU(obj); 5700 int64_t value; 5701 5702 value = cpu->env.tsc_khz * 1000; 5703 visit_type_int(v, name, &value, errp); 5704 } 5705 5706 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name, 5707 void *opaque, Error **errp) 5708 { 5709 X86CPU *cpu = X86_CPU(obj); 5710 const int64_t max = INT64_MAX; 5711 int64_t value; 5712 5713 if (!visit_type_int(v, name, &value, errp)) { 5714 return; 5715 } 5716 if (value < 0 || value > max) { 5717 error_setg(errp, "parameter '%s' can be at most %" PRId64, 5718 name ? name : "null", max); 5719 return; 5720 } 5721 5722 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000; 5723 } 5724 5725 /* Generic getter for "feature-words" and "filtered-features" properties */ 5726 static void x86_cpu_get_feature_words(Object *obj, Visitor *v, 5727 const char *name, void *opaque, 5728 Error **errp) 5729 { 5730 uint64_t *array = (uint64_t *)opaque; 5731 FeatureWord w; 5732 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { }; 5733 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { }; 5734 X86CPUFeatureWordInfoList *list = NULL; 5735 5736 for (w = 0; w < FEATURE_WORDS; w++) { 5737 FeatureWordInfo *wi = &feature_word_info[w]; 5738 /* 5739 * We didn't have MSR features when "feature-words" was 5740 * introduced. Therefore skipped other type entries. 5741 */ 5742 if (wi->type != CPUID_FEATURE_WORD) { 5743 continue; 5744 } 5745 X86CPUFeatureWordInfo *qwi = &word_infos[w]; 5746 qwi->cpuid_input_eax = wi->cpuid.eax; 5747 qwi->has_cpuid_input_ecx = wi->cpuid.needs_ecx; 5748 qwi->cpuid_input_ecx = wi->cpuid.ecx; 5749 qwi->cpuid_register = x86_reg_info_32[wi->cpuid.reg].qapi_enum; 5750 qwi->features = array[w]; 5751 5752 /* List will be in reverse order, but order shouldn't matter */ 5753 list_entries[w].next = list; 5754 list_entries[w].value = &word_infos[w]; 5755 list = &list_entries[w]; 5756 } 5757 5758 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp); 5759 } 5760 5761 /* Convert all '_' in a feature string option name to '-', to make feature 5762 * name conform to QOM property naming rule, which uses '-' instead of '_'. 5763 */ 5764 static inline void feat2prop(char *s) 5765 { 5766 while ((s = strchr(s, '_'))) { 5767 *s = '-'; 5768 } 5769 } 5770 5771 /* Return the feature property name for a feature flag bit */ 5772 static const char *x86_cpu_feature_name(FeatureWord w, int bitnr) 5773 { 5774 const char *name; 5775 /* XSAVE components are automatically enabled by other features, 5776 * so return the original feature name instead 5777 */ 5778 if (w == FEAT_XSAVE_XCR0_LO || w == FEAT_XSAVE_XCR0_HI) { 5779 int comp = (w == FEAT_XSAVE_XCR0_HI) ? bitnr + 32 : bitnr; 5780 5781 if (comp < ARRAY_SIZE(x86_ext_save_areas) && 5782 x86_ext_save_areas[comp].bits) { 5783 w = x86_ext_save_areas[comp].feature; 5784 bitnr = ctz32(x86_ext_save_areas[comp].bits); 5785 } 5786 } 5787 5788 assert(bitnr < 64); 5789 assert(w < FEATURE_WORDS); 5790 name = feature_word_info[w].feat_names[bitnr]; 5791 assert(bitnr < 32 || !(name && feature_word_info[w].type == CPUID_FEATURE_WORD)); 5792 return name; 5793 } 5794 5795 /* Compatibility hack to maintain legacy +-feat semantic, 5796 * where +-feat overwrites any feature set by 5797 * feat=on|feat even if the later is parsed after +-feat 5798 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled) 5799 */ 5800 static GList *plus_features, *minus_features; 5801 5802 static gint compare_string(gconstpointer a, gconstpointer b) 5803 { 5804 return g_strcmp0(a, b); 5805 } 5806 5807 /* Parse "+feature,-feature,feature=foo" CPU feature string 5808 */ 5809 static void x86_cpu_parse_featurestr(const char *typename, char *features, 5810 Error **errp) 5811 { 5812 char *featurestr; /* Single 'key=value" string being parsed */ 5813 static bool cpu_globals_initialized; 5814 bool ambiguous = false; 5815 5816 if (cpu_globals_initialized) { 5817 return; 5818 } 5819 cpu_globals_initialized = true; 5820 5821 if (!features) { 5822 return; 5823 } 5824 5825 for (featurestr = strtok(features, ","); 5826 featurestr; 5827 featurestr = strtok(NULL, ",")) { 5828 const char *name; 5829 const char *val = NULL; 5830 char *eq = NULL; 5831 char num[32]; 5832 GlobalProperty *prop; 5833 5834 /* Compatibility syntax: */ 5835 if (featurestr[0] == '+') { 5836 plus_features = g_list_append(plus_features, 5837 g_strdup(featurestr + 1)); 5838 continue; 5839 } else if (featurestr[0] == '-') { 5840 minus_features = g_list_append(minus_features, 5841 g_strdup(featurestr + 1)); 5842 continue; 5843 } 5844 5845 eq = strchr(featurestr, '='); 5846 if (eq) { 5847 *eq++ = 0; 5848 val = eq; 5849 } else { 5850 val = "on"; 5851 } 5852 5853 feat2prop(featurestr); 5854 name = featurestr; 5855 5856 if (g_list_find_custom(plus_features, name, compare_string)) { 5857 warn_report("Ambiguous CPU model string. " 5858 "Don't mix both \"+%s\" and \"%s=%s\"", 5859 name, name, val); 5860 ambiguous = true; 5861 } 5862 if (g_list_find_custom(minus_features, name, compare_string)) { 5863 warn_report("Ambiguous CPU model string. " 5864 "Don't mix both \"-%s\" and \"%s=%s\"", 5865 name, name, val); 5866 ambiguous = true; 5867 } 5868 5869 /* Special case: */ 5870 if (!strcmp(name, "tsc-freq")) { 5871 int ret; 5872 uint64_t tsc_freq; 5873 5874 ret = qemu_strtosz_metric(val, NULL, &tsc_freq); 5875 if (ret < 0 || tsc_freq > INT64_MAX) { 5876 error_setg(errp, "bad numerical value %s", val); 5877 return; 5878 } 5879 snprintf(num, sizeof(num), "%" PRId64, tsc_freq); 5880 val = num; 5881 name = "tsc-frequency"; 5882 } 5883 5884 prop = g_new0(typeof(*prop), 1); 5885 prop->driver = typename; 5886 prop->property = g_strdup(name); 5887 prop->value = g_strdup(val); 5888 qdev_prop_register_global(prop); 5889 } 5890 5891 if (ambiguous) { 5892 warn_report("Compatibility of ambiguous CPU model " 5893 "strings won't be kept on future QEMU versions"); 5894 } 5895 } 5896 5897 static bool x86_cpu_filter_features(X86CPU *cpu, bool verbose); 5898 5899 /* Build a list with the name of all features on a feature word array */ 5900 static void x86_cpu_list_feature_names(FeatureWordArray features, 5901 strList **list) 5902 { 5903 strList **tail = list; 5904 FeatureWord w; 5905 5906 for (w = 0; w < FEATURE_WORDS; w++) { 5907 uint64_t filtered = features[w]; 5908 int i; 5909 for (i = 0; i < 64; i++) { 5910 if (filtered & (1ULL << i)) { 5911 QAPI_LIST_APPEND(tail, g_strdup(x86_cpu_feature_name(w, i))); 5912 } 5913 } 5914 } 5915 } 5916 5917 static void x86_cpu_get_unavailable_features(Object *obj, Visitor *v, 5918 const char *name, void *opaque, 5919 Error **errp) 5920 { 5921 X86CPU *xc = X86_CPU(obj); 5922 strList *result = NULL; 5923 5924 x86_cpu_list_feature_names(xc->filtered_features, &result); 5925 visit_type_strList(v, "unavailable-features", &result, errp); 5926 } 5927 5928 /* Print all cpuid feature names in featureset 5929 */ 5930 static void listflags(GList *features) 5931 { 5932 size_t len = 0; 5933 GList *tmp; 5934 5935 for (tmp = features; tmp; tmp = tmp->next) { 5936 const char *name = tmp->data; 5937 if ((len + strlen(name) + 1) >= 75) { 5938 qemu_printf("\n"); 5939 len = 0; 5940 } 5941 qemu_printf("%s%s", len == 0 ? " " : " ", name); 5942 len += strlen(name) + 1; 5943 } 5944 qemu_printf("\n"); 5945 } 5946 5947 /* Sort alphabetically by type name, respecting X86CPUClass::ordering. */ 5948 static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b) 5949 { 5950 ObjectClass *class_a = (ObjectClass *)a; 5951 ObjectClass *class_b = (ObjectClass *)b; 5952 X86CPUClass *cc_a = X86_CPU_CLASS(class_a); 5953 X86CPUClass *cc_b = X86_CPU_CLASS(class_b); 5954 int ret; 5955 5956 if (cc_a->ordering != cc_b->ordering) { 5957 ret = cc_a->ordering - cc_b->ordering; 5958 } else { 5959 g_autofree char *name_a = x86_cpu_class_get_model_name(cc_a); 5960 g_autofree char *name_b = x86_cpu_class_get_model_name(cc_b); 5961 ret = strcmp(name_a, name_b); 5962 } 5963 return ret; 5964 } 5965 5966 static GSList *get_sorted_cpu_model_list(void) 5967 { 5968 GSList *list = object_class_get_list(TYPE_X86_CPU, false); 5969 list = g_slist_sort(list, x86_cpu_list_compare); 5970 return list; 5971 } 5972 5973 static char *x86_cpu_class_get_model_id(X86CPUClass *xc) 5974 { 5975 Object *obj = object_new_with_class(OBJECT_CLASS(xc)); 5976 char *r = object_property_get_str(obj, "model-id", &error_abort); 5977 object_unref(obj); 5978 return r; 5979 } 5980 5981 static char *x86_cpu_class_get_alias_of(X86CPUClass *cc) 5982 { 5983 X86CPUVersion version; 5984 5985 if (!cc->model || !cc->model->is_alias) { 5986 return NULL; 5987 } 5988 version = x86_cpu_model_resolve_version(cc->model); 5989 if (version <= 0) { 5990 return NULL; 5991 } 5992 return x86_cpu_versioned_model_name(cc->model->cpudef, version); 5993 } 5994 5995 static void x86_cpu_list_entry(gpointer data, gpointer user_data) 5996 { 5997 ObjectClass *oc = data; 5998 X86CPUClass *cc = X86_CPU_CLASS(oc); 5999 g_autofree char *name = x86_cpu_class_get_model_name(cc); 6000 g_autofree char *desc = g_strdup(cc->model_description); 6001 g_autofree char *alias_of = x86_cpu_class_get_alias_of(cc); 6002 g_autofree char *model_id = x86_cpu_class_get_model_id(cc); 6003 6004 if (!desc && alias_of) { 6005 if (cc->model && cc->model->version == CPU_VERSION_AUTO) { 6006 desc = g_strdup("(alias configured by machine type)"); 6007 } else { 6008 desc = g_strdup_printf("(alias of %s)", alias_of); 6009 } 6010 } 6011 if (!desc && cc->model && cc->model->note) { 6012 desc = g_strdup_printf("%s [%s]", model_id, cc->model->note); 6013 } 6014 if (!desc) { 6015 desc = g_strdup_printf("%s", model_id); 6016 } 6017 6018 if (cc->model && cc->model->cpudef->deprecation_note) { 6019 g_autofree char *olddesc = desc; 6020 desc = g_strdup_printf("%s (deprecated)", olddesc); 6021 } 6022 6023 qemu_printf(" %-20s %s\n", name, desc); 6024 } 6025 6026 /* list available CPU models and flags */ 6027 void x86_cpu_list(void) 6028 { 6029 int i, j; 6030 GSList *list; 6031 GList *names = NULL; 6032 6033 qemu_printf("Available CPUs:\n"); 6034 list = get_sorted_cpu_model_list(); 6035 g_slist_foreach(list, x86_cpu_list_entry, NULL); 6036 g_slist_free(list); 6037 6038 names = NULL; 6039 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) { 6040 FeatureWordInfo *fw = &feature_word_info[i]; 6041 for (j = 0; j < 64; j++) { 6042 if (fw->feat_names[j]) { 6043 names = g_list_append(names, (gpointer)fw->feat_names[j]); 6044 } 6045 } 6046 } 6047 6048 names = g_list_sort(names, (GCompareFunc)strcmp); 6049 6050 qemu_printf("\nRecognized CPUID flags:\n"); 6051 listflags(names); 6052 qemu_printf("\n"); 6053 g_list_free(names); 6054 } 6055 6056 #ifndef CONFIG_USER_ONLY 6057 6058 /* Check for missing features that may prevent the CPU class from 6059 * running using the current machine and accelerator. 6060 */ 6061 static void x86_cpu_class_check_missing_features(X86CPUClass *xcc, 6062 strList **list) 6063 { 6064 strList **tail = list; 6065 X86CPU *xc; 6066 Error *err = NULL; 6067 6068 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) { 6069 QAPI_LIST_APPEND(tail, g_strdup("kvm")); 6070 return; 6071 } 6072 6073 xc = X86_CPU(object_new_with_class(OBJECT_CLASS(xcc))); 6074 6075 x86_cpu_expand_features(xc, &err); 6076 if (err) { 6077 /* Errors at x86_cpu_expand_features should never happen, 6078 * but in case it does, just report the model as not 6079 * runnable at all using the "type" property. 6080 */ 6081 QAPI_LIST_APPEND(tail, g_strdup("type")); 6082 error_free(err); 6083 } 6084 6085 x86_cpu_filter_features(xc, false); 6086 6087 x86_cpu_list_feature_names(xc->filtered_features, tail); 6088 6089 object_unref(OBJECT(xc)); 6090 } 6091 6092 static void x86_cpu_definition_entry(gpointer data, gpointer user_data) 6093 { 6094 ObjectClass *oc = data; 6095 X86CPUClass *cc = X86_CPU_CLASS(oc); 6096 CpuDefinitionInfoList **cpu_list = user_data; 6097 CpuDefinitionInfo *info; 6098 6099 info = g_malloc0(sizeof(*info)); 6100 info->name = x86_cpu_class_get_model_name(cc); 6101 x86_cpu_class_check_missing_features(cc, &info->unavailable_features); 6102 info->has_unavailable_features = true; 6103 info->q_typename = g_strdup(object_class_get_name(oc)); 6104 info->migration_safe = cc->migration_safe; 6105 info->has_migration_safe = true; 6106 info->q_static = cc->static_model; 6107 if (cc->model && cc->model->cpudef->deprecation_note) { 6108 info->deprecated = true; 6109 } else { 6110 info->deprecated = false; 6111 } 6112 /* 6113 * Old machine types won't report aliases, so that alias translation 6114 * doesn't break compatibility with previous QEMU versions. 6115 */ 6116 if (default_cpu_version != CPU_VERSION_LEGACY) { 6117 info->alias_of = x86_cpu_class_get_alias_of(cc); 6118 } 6119 6120 QAPI_LIST_PREPEND(*cpu_list, info); 6121 } 6122 6123 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) 6124 { 6125 CpuDefinitionInfoList *cpu_list = NULL; 6126 GSList *list = get_sorted_cpu_model_list(); 6127 g_slist_foreach(list, x86_cpu_definition_entry, &cpu_list); 6128 g_slist_free(list); 6129 return cpu_list; 6130 } 6131 6132 #endif /* !CONFIG_USER_ONLY */ 6133 6134 uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w) 6135 { 6136 FeatureWordInfo *wi = &feature_word_info[w]; 6137 uint64_t r = 0; 6138 uint64_t unavail = 0; 6139 6140 if (kvm_enabled()) { 6141 switch (wi->type) { 6142 case CPUID_FEATURE_WORD: 6143 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid.eax, 6144 wi->cpuid.ecx, 6145 wi->cpuid.reg); 6146 break; 6147 case MSR_FEATURE_WORD: 6148 r = kvm_arch_get_supported_msr_feature(kvm_state, 6149 wi->msr.index); 6150 break; 6151 } 6152 } else if (hvf_enabled()) { 6153 if (wi->type != CPUID_FEATURE_WORD) { 6154 return 0; 6155 } 6156 r = hvf_get_supported_cpuid(wi->cpuid.eax, 6157 wi->cpuid.ecx, 6158 wi->cpuid.reg); 6159 } else if (tcg_enabled()) { 6160 r = wi->tcg_features; 6161 } else { 6162 return ~0; 6163 } 6164 6165 switch (w) { 6166 #ifndef TARGET_X86_64 6167 case FEAT_8000_0001_EDX: 6168 /* 6169 * 32-bit TCG can emulate 64-bit compatibility mode. If there is no 6170 * way for userspace to get out of its 32-bit jail, we can leave 6171 * the LM bit set. 6172 */ 6173 unavail = tcg_enabled() 6174 ? CPUID_EXT2_LM & ~CPUID_EXT2_KERNEL_FEATURES 6175 : CPUID_EXT2_LM; 6176 break; 6177 #endif 6178 6179 case FEAT_8000_0007_EBX: 6180 if (cpu && !IS_AMD_CPU(&cpu->env)) { 6181 /* Disable AMD machine check architecture for Intel CPU. */ 6182 unavail = ~0; 6183 } 6184 break; 6185 6186 case FEAT_7_0_EBX: 6187 #ifndef CONFIG_USER_ONLY 6188 if (!check_sgx_support()) { 6189 unavail = CPUID_7_0_EBX_SGX; 6190 } 6191 #endif 6192 break; 6193 case FEAT_7_0_ECX: 6194 #ifndef CONFIG_USER_ONLY 6195 if (!check_sgx_support()) { 6196 unavail = CPUID_7_0_ECX_SGX_LC; 6197 } 6198 #endif 6199 break; 6200 6201 default: 6202 break; 6203 } 6204 6205 r &= ~unavail; 6206 if (cpu && cpu->migratable) { 6207 r &= x86_cpu_get_migratable_flags(cpu, w); 6208 } 6209 return r; 6210 } 6211 6212 static void x86_cpu_get_supported_cpuid(uint32_t func, uint32_t index, 6213 uint32_t *eax, uint32_t *ebx, 6214 uint32_t *ecx, uint32_t *edx) 6215 { 6216 if (kvm_enabled()) { 6217 *eax = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EAX); 6218 *ebx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EBX); 6219 *ecx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_ECX); 6220 *edx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EDX); 6221 } else if (hvf_enabled()) { 6222 *eax = hvf_get_supported_cpuid(func, index, R_EAX); 6223 *ebx = hvf_get_supported_cpuid(func, index, R_EBX); 6224 *ecx = hvf_get_supported_cpuid(func, index, R_ECX); 6225 *edx = hvf_get_supported_cpuid(func, index, R_EDX); 6226 } else { 6227 *eax = 0; 6228 *ebx = 0; 6229 *ecx = 0; 6230 *edx = 0; 6231 } 6232 } 6233 6234 static void x86_cpu_get_cache_cpuid(uint32_t func, uint32_t index, 6235 uint32_t *eax, uint32_t *ebx, 6236 uint32_t *ecx, uint32_t *edx) 6237 { 6238 uint32_t level, unused; 6239 6240 /* Only return valid host leaves. */ 6241 switch (func) { 6242 case 2: 6243 case 4: 6244 host_cpuid(0, 0, &level, &unused, &unused, &unused); 6245 break; 6246 case 0x80000005: 6247 case 0x80000006: 6248 case 0x8000001d: 6249 host_cpuid(0x80000000, 0, &level, &unused, &unused, &unused); 6250 break; 6251 default: 6252 return; 6253 } 6254 6255 if (func > level) { 6256 *eax = 0; 6257 *ebx = 0; 6258 *ecx = 0; 6259 *edx = 0; 6260 } else { 6261 host_cpuid(func, index, eax, ebx, ecx, edx); 6262 } 6263 } 6264 6265 /* 6266 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 6267 */ 6268 void x86_cpu_apply_props(X86CPU *cpu, PropValue *props) 6269 { 6270 PropValue *pv; 6271 for (pv = props; pv->prop; pv++) { 6272 if (!pv->value) { 6273 continue; 6274 } 6275 object_property_parse(OBJECT(cpu), pv->prop, pv->value, 6276 &error_abort); 6277 } 6278 } 6279 6280 /* 6281 * Apply properties for the CPU model version specified in model. 6282 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 6283 */ 6284 6285 static void x86_cpu_apply_version_props(X86CPU *cpu, X86CPUModel *model) 6286 { 6287 const X86CPUVersionDefinition *vdef; 6288 X86CPUVersion version = x86_cpu_model_resolve_version(model); 6289 6290 if (version == CPU_VERSION_LEGACY) { 6291 return; 6292 } 6293 6294 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) { 6295 PropValue *p; 6296 6297 for (p = vdef->props; p && p->prop; p++) { 6298 object_property_parse(OBJECT(cpu), p->prop, p->value, 6299 &error_abort); 6300 } 6301 6302 if (vdef->version == version) { 6303 break; 6304 } 6305 } 6306 6307 /* 6308 * If we reached the end of the list, version number was invalid 6309 */ 6310 assert(vdef->version == version); 6311 } 6312 6313 static const CPUCaches *x86_cpu_get_versioned_cache_info(X86CPU *cpu, 6314 X86CPUModel *model) 6315 { 6316 const X86CPUVersionDefinition *vdef; 6317 X86CPUVersion version = x86_cpu_model_resolve_version(model); 6318 const CPUCaches *cache_info = model->cpudef->cache_info; 6319 6320 if (version == CPU_VERSION_LEGACY) { 6321 return cache_info; 6322 } 6323 6324 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) { 6325 if (vdef->cache_info) { 6326 cache_info = vdef->cache_info; 6327 } 6328 6329 if (vdef->version == version) { 6330 break; 6331 } 6332 } 6333 6334 assert(vdef->version == version); 6335 return cache_info; 6336 } 6337 6338 /* 6339 * Load data from X86CPUDefinition into a X86CPU object. 6340 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 6341 */ 6342 static void x86_cpu_load_model(X86CPU *cpu, X86CPUModel *model) 6343 { 6344 const X86CPUDefinition *def = model->cpudef; 6345 CPUX86State *env = &cpu->env; 6346 FeatureWord w; 6347 6348 /*NOTE: any property set by this function should be returned by 6349 * x86_cpu_static_props(), so static expansion of 6350 * query-cpu-model-expansion is always complete. 6351 */ 6352 6353 /* CPU models only set _minimum_ values for level/xlevel: */ 6354 object_property_set_uint(OBJECT(cpu), "min-level", def->level, 6355 &error_abort); 6356 object_property_set_uint(OBJECT(cpu), "min-xlevel", def->xlevel, 6357 &error_abort); 6358 6359 object_property_set_int(OBJECT(cpu), "family", def->family, &error_abort); 6360 object_property_set_int(OBJECT(cpu), "model", def->model, &error_abort); 6361 object_property_set_int(OBJECT(cpu), "stepping", def->stepping, 6362 &error_abort); 6363 object_property_set_str(OBJECT(cpu), "model-id", def->model_id, 6364 &error_abort); 6365 for (w = 0; w < FEATURE_WORDS; w++) { 6366 env->features[w] = def->features[w]; 6367 } 6368 6369 /* legacy-cache defaults to 'off' if CPU model provides cache info */ 6370 cpu->legacy_cache = !x86_cpu_get_versioned_cache_info(cpu, model); 6371 6372 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR; 6373 6374 /* sysenter isn't supported in compatibility mode on AMD, 6375 * syscall isn't supported in compatibility mode on Intel. 6376 * Normally we advertise the actual CPU vendor, but you can 6377 * override this using the 'vendor' property if you want to use 6378 * KVM's sysenter/syscall emulation in compatibility mode and 6379 * when doing cross vendor migration 6380 */ 6381 6382 /* 6383 * vendor property is set here but then overloaded with the 6384 * host cpu vendor for KVM and HVF. 6385 */ 6386 object_property_set_str(OBJECT(cpu), "vendor", def->vendor, &error_abort); 6387 6388 object_property_set_uint(OBJECT(cpu), "avx10-version", def->avx10_version, 6389 &error_abort); 6390 6391 x86_cpu_apply_version_props(cpu, model); 6392 6393 /* 6394 * Properties in versioned CPU model are not user specified features. 6395 * We can simply clear env->user_features here since it will be filled later 6396 * in x86_cpu_expand_features() based on plus_features and minus_features. 6397 */ 6398 memset(&env->user_features, 0, sizeof(env->user_features)); 6399 } 6400 6401 static const gchar *x86_gdb_arch_name(CPUState *cs) 6402 { 6403 #ifdef TARGET_X86_64 6404 return "i386:x86-64"; 6405 #else 6406 return "i386"; 6407 #endif 6408 } 6409 6410 static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data) 6411 { 6412 X86CPUModel *model = data; 6413 X86CPUClass *xcc = X86_CPU_CLASS(oc); 6414 CPUClass *cc = CPU_CLASS(oc); 6415 6416 xcc->model = model; 6417 xcc->migration_safe = true; 6418 cc->deprecation_note = model->cpudef->deprecation_note; 6419 } 6420 6421 static void x86_register_cpu_model_type(const char *name, X86CPUModel *model) 6422 { 6423 g_autofree char *typename = x86_cpu_type_name(name); 6424 TypeInfo ti = { 6425 .name = typename, 6426 .parent = TYPE_X86_CPU, 6427 .class_init = x86_cpu_cpudef_class_init, 6428 .class_data = model, 6429 }; 6430 6431 type_register_static(&ti); 6432 } 6433 6434 6435 /* 6436 * register builtin_x86_defs; 6437 * "max", "base" and subclasses ("host") are not registered here. 6438 * See x86_cpu_register_types for all model registrations. 6439 */ 6440 static void x86_register_cpudef_types(const X86CPUDefinition *def) 6441 { 6442 X86CPUModel *m; 6443 const X86CPUVersionDefinition *vdef; 6444 6445 /* AMD aliases are handled at runtime based on CPUID vendor, so 6446 * they shouldn't be set on the CPU model table. 6447 */ 6448 assert(!(def->features[FEAT_8000_0001_EDX] & CPUID_EXT2_AMD_ALIASES)); 6449 /* catch mistakes instead of silently truncating model_id when too long */ 6450 assert(def->model_id && strlen(def->model_id) <= 48); 6451 6452 /* Unversioned model: */ 6453 m = g_new0(X86CPUModel, 1); 6454 m->cpudef = def; 6455 m->version = CPU_VERSION_AUTO; 6456 m->is_alias = true; 6457 x86_register_cpu_model_type(def->name, m); 6458 6459 /* Versioned models: */ 6460 6461 for (vdef = x86_cpu_def_get_versions(def); vdef->version; vdef++) { 6462 g_autofree char *name = 6463 x86_cpu_versioned_model_name(def, vdef->version); 6464 6465 m = g_new0(X86CPUModel, 1); 6466 m->cpudef = def; 6467 m->version = vdef->version; 6468 m->note = vdef->note; 6469 x86_register_cpu_model_type(name, m); 6470 6471 if (vdef->alias) { 6472 X86CPUModel *am = g_new0(X86CPUModel, 1); 6473 am->cpudef = def; 6474 am->version = vdef->version; 6475 am->is_alias = true; 6476 x86_register_cpu_model_type(vdef->alias, am); 6477 } 6478 } 6479 6480 } 6481 6482 uint32_t cpu_x86_virtual_addr_width(CPUX86State *env) 6483 { 6484 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57) { 6485 return 57; /* 57 bits virtual */ 6486 } else { 6487 return 48; /* 48 bits virtual */ 6488 } 6489 } 6490 6491 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, 6492 uint32_t *eax, uint32_t *ebx, 6493 uint32_t *ecx, uint32_t *edx) 6494 { 6495 X86CPU *cpu = env_archcpu(env); 6496 CPUState *cs = env_cpu(env); 6497 uint32_t limit; 6498 uint32_t signature[3]; 6499 X86CPUTopoInfo *topo_info = &env->topo_info; 6500 uint32_t threads_per_pkg; 6501 6502 threads_per_pkg = x86_threads_per_pkg(topo_info); 6503 6504 /* Calculate & apply limits for different index ranges */ 6505 if (index >= 0xC0000000) { 6506 limit = env->cpuid_xlevel2; 6507 } else if (index >= 0x80000000) { 6508 limit = env->cpuid_xlevel; 6509 } else if (index >= 0x40000000) { 6510 limit = 0x40000001; 6511 } else { 6512 limit = env->cpuid_level; 6513 } 6514 6515 if (index > limit) { 6516 /* Intel documentation states that invalid EAX input will 6517 * return the same information as EAX=cpuid_level 6518 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID) 6519 */ 6520 index = env->cpuid_level; 6521 } 6522 6523 switch(index) { 6524 case 0: 6525 *eax = env->cpuid_level; 6526 *ebx = env->cpuid_vendor1; 6527 *edx = env->cpuid_vendor2; 6528 *ecx = env->cpuid_vendor3; 6529 break; 6530 case 1: 6531 *eax = env->cpuid_version; 6532 *ebx = (cpu->apic_id << 24) | 6533 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */ 6534 *ecx = env->features[FEAT_1_ECX]; 6535 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) { 6536 *ecx |= CPUID_EXT_OSXSAVE; 6537 } 6538 *edx = env->features[FEAT_1_EDX]; 6539 if (threads_per_pkg > 1) { 6540 *ebx |= threads_per_pkg << 16; 6541 *edx |= CPUID_HT; 6542 } 6543 if (!cpu->enable_pmu) { 6544 *ecx &= ~CPUID_EXT_PDCM; 6545 } 6546 break; 6547 case 2: 6548 /* cache info: needed for Pentium Pro compatibility */ 6549 if (cpu->cache_info_passthrough) { 6550 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 6551 break; 6552 } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { 6553 *eax = *ebx = *ecx = *edx = 0; 6554 break; 6555 } 6556 *eax = 1; /* Number of CPUID[EAX=2] calls required */ 6557 *ebx = 0; 6558 if (!cpu->enable_l3_cache) { 6559 *ecx = 0; 6560 } else { 6561 *ecx = cpuid2_cache_descriptor(env->cache_info_cpuid2.l3_cache); 6562 } 6563 *edx = (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1d_cache) << 16) | 6564 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1i_cache) << 8) | 6565 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l2_cache)); 6566 break; 6567 case 4: 6568 /* cache info: needed for Core compatibility */ 6569 if (cpu->cache_info_passthrough) { 6570 x86_cpu_get_cache_cpuid(index, count, eax, ebx, ecx, edx); 6571 /* 6572 * QEMU has its own number of cores/logical cpus, 6573 * set 24..14, 31..26 bit to configured values 6574 */ 6575 if (*eax & 31) { 6576 int host_vcpus_per_cache = 1 + ((*eax & 0x3FFC000) >> 14); 6577 6578 *eax &= ~0xFC000000; 6579 *eax |= max_core_ids_in_package(topo_info) << 26; 6580 if (host_vcpus_per_cache > threads_per_pkg) { 6581 *eax &= ~0x3FFC000; 6582 6583 /* Share the cache at package level. */ 6584 *eax |= max_thread_ids_for_cache(topo_info, 6585 CPU_TOPOLOGY_LEVEL_SOCKET) << 14; 6586 } 6587 } 6588 } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { 6589 *eax = *ebx = *ecx = *edx = 0; 6590 } else { 6591 *eax = 0; 6592 6593 switch (count) { 6594 case 0: /* L1 dcache info */ 6595 encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache, 6596 topo_info, 6597 eax, ebx, ecx, edx); 6598 if (!cpu->l1_cache_per_core) { 6599 *eax &= ~MAKE_64BIT_MASK(14, 12); 6600 } 6601 break; 6602 case 1: /* L1 icache info */ 6603 encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache, 6604 topo_info, 6605 eax, ebx, ecx, edx); 6606 if (!cpu->l1_cache_per_core) { 6607 *eax &= ~MAKE_64BIT_MASK(14, 12); 6608 } 6609 break; 6610 case 2: /* L2 cache info */ 6611 encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache, 6612 topo_info, 6613 eax, ebx, ecx, edx); 6614 break; 6615 case 3: /* L3 cache info */ 6616 if (cpu->enable_l3_cache) { 6617 encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache, 6618 topo_info, 6619 eax, ebx, ecx, edx); 6620 break; 6621 } 6622 /* fall through */ 6623 default: /* end of info */ 6624 *eax = *ebx = *ecx = *edx = 0; 6625 break; 6626 } 6627 } 6628 break; 6629 case 5: 6630 /* MONITOR/MWAIT Leaf */ 6631 *eax = cpu->mwait.eax; /* Smallest monitor-line size in bytes */ 6632 *ebx = cpu->mwait.ebx; /* Largest monitor-line size in bytes */ 6633 *ecx = cpu->mwait.ecx; /* flags */ 6634 *edx = cpu->mwait.edx; /* mwait substates */ 6635 break; 6636 case 6: 6637 /* Thermal and Power Leaf */ 6638 *eax = env->features[FEAT_6_EAX]; 6639 *ebx = 0; 6640 *ecx = 0; 6641 *edx = 0; 6642 break; 6643 case 7: 6644 /* Structured Extended Feature Flags Enumeration Leaf */ 6645 if (count == 0) { 6646 /* Maximum ECX value for sub-leaves */ 6647 *eax = env->cpuid_level_func7; 6648 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */ 6649 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */ 6650 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) { 6651 *ecx |= CPUID_7_0_ECX_OSPKE; 6652 } 6653 *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */ 6654 } else if (count == 1) { 6655 *eax = env->features[FEAT_7_1_EAX]; 6656 *edx = env->features[FEAT_7_1_EDX]; 6657 *ebx = 0; 6658 *ecx = 0; 6659 } else if (count == 2) { 6660 *edx = env->features[FEAT_7_2_EDX]; 6661 *eax = 0; 6662 *ebx = 0; 6663 *ecx = 0; 6664 } else { 6665 *eax = 0; 6666 *ebx = 0; 6667 *ecx = 0; 6668 *edx = 0; 6669 } 6670 break; 6671 case 9: 6672 /* Direct Cache Access Information Leaf */ 6673 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */ 6674 *ebx = 0; 6675 *ecx = 0; 6676 *edx = 0; 6677 break; 6678 case 0xA: 6679 /* Architectural Performance Monitoring Leaf */ 6680 if (cpu->enable_pmu) { 6681 x86_cpu_get_supported_cpuid(0xA, count, eax, ebx, ecx, edx); 6682 } else { 6683 *eax = 0; 6684 *ebx = 0; 6685 *ecx = 0; 6686 *edx = 0; 6687 } 6688 break; 6689 case 0xB: 6690 /* Extended Topology Enumeration Leaf */ 6691 if (!cpu->enable_cpuid_0xb) { 6692 *eax = *ebx = *ecx = *edx = 0; 6693 break; 6694 } 6695 6696 *ecx = count & 0xff; 6697 *edx = cpu->apic_id; 6698 6699 switch (count) { 6700 case 0: 6701 *eax = apicid_core_offset(topo_info); 6702 *ebx = topo_info->threads_per_core; 6703 *ecx |= CPUID_B_ECX_TOPO_LEVEL_SMT << 8; 6704 break; 6705 case 1: 6706 *eax = apicid_pkg_offset(topo_info); 6707 *ebx = threads_per_pkg; 6708 *ecx |= CPUID_B_ECX_TOPO_LEVEL_CORE << 8; 6709 break; 6710 default: 6711 *eax = 0; 6712 *ebx = 0; 6713 *ecx |= CPUID_B_ECX_TOPO_LEVEL_INVALID << 8; 6714 } 6715 6716 assert(!(*eax & ~0x1f)); 6717 *ebx &= 0xffff; /* The count doesn't need to be reliable. */ 6718 break; 6719 case 0x1C: 6720 if (cpu->enable_pmu && (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) { 6721 x86_cpu_get_supported_cpuid(0x1C, 0, eax, ebx, ecx, edx); 6722 *edx = 0; 6723 } 6724 break; 6725 case 0x1F: 6726 /* V2 Extended Topology Enumeration Leaf */ 6727 if (!x86_has_extended_topo(env->avail_cpu_topo)) { 6728 *eax = *ebx = *ecx = *edx = 0; 6729 break; 6730 } 6731 6732 encode_topo_cpuid1f(env, count, topo_info, eax, ebx, ecx, edx); 6733 break; 6734 case 0xD: { 6735 /* Processor Extended State */ 6736 *eax = 0; 6737 *ebx = 0; 6738 *ecx = 0; 6739 *edx = 0; 6740 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { 6741 break; 6742 } 6743 6744 if (count == 0) { 6745 *ecx = xsave_area_size(x86_cpu_xsave_xcr0_components(cpu), false); 6746 *eax = env->features[FEAT_XSAVE_XCR0_LO]; 6747 *edx = env->features[FEAT_XSAVE_XCR0_HI]; 6748 /* 6749 * The initial value of xcr0 and ebx == 0, On host without kvm 6750 * commit 412a3c41(e.g., CentOS 6), the ebx's value always == 0 6751 * even through guest update xcr0, this will crash some legacy guest 6752 * (e.g., CentOS 6), So set ebx == ecx to workaround it. 6753 */ 6754 *ebx = kvm_enabled() ? *ecx : xsave_area_size(env->xcr0, false); 6755 } else if (count == 1) { 6756 uint64_t xstate = x86_cpu_xsave_xcr0_components(cpu) | 6757 x86_cpu_xsave_xss_components(cpu); 6758 6759 *eax = env->features[FEAT_XSAVE]; 6760 *ebx = xsave_area_size(xstate, true); 6761 *ecx = env->features[FEAT_XSAVE_XSS_LO]; 6762 *edx = env->features[FEAT_XSAVE_XSS_HI]; 6763 if (kvm_enabled() && cpu->enable_pmu && 6764 (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR) && 6765 (*eax & CPUID_XSAVE_XSAVES)) { 6766 *ecx |= XSTATE_ARCH_LBR_MASK; 6767 } else { 6768 *ecx &= ~XSTATE_ARCH_LBR_MASK; 6769 } 6770 } else if (count == 0xf && cpu->enable_pmu 6771 && (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) { 6772 x86_cpu_get_supported_cpuid(0xD, count, eax, ebx, ecx, edx); 6773 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) { 6774 const ExtSaveArea *esa = &x86_ext_save_areas[count]; 6775 6776 if (x86_cpu_xsave_xcr0_components(cpu) & (1ULL << count)) { 6777 *eax = esa->size; 6778 *ebx = esa->offset; 6779 *ecx = esa->ecx & 6780 (ESA_FEATURE_ALIGN64_MASK | ESA_FEATURE_XFD_MASK); 6781 } else if (x86_cpu_xsave_xss_components(cpu) & (1ULL << count)) { 6782 *eax = esa->size; 6783 *ebx = 0; 6784 *ecx = 1; 6785 } 6786 } 6787 break; 6788 } 6789 case 0x12: 6790 #ifndef CONFIG_USER_ONLY 6791 if (!kvm_enabled() || 6792 !(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX)) { 6793 *eax = *ebx = *ecx = *edx = 0; 6794 break; 6795 } 6796 6797 /* 6798 * SGX sub-leafs CPUID.0x12.{0x2..N} enumerate EPC sections. Retrieve 6799 * the EPC properties, e.g. confidentiality and integrity, from the 6800 * host's first EPC section, i.e. assume there is one EPC section or 6801 * that all EPC sections have the same security properties. 6802 */ 6803 if (count > 1) { 6804 uint64_t epc_addr, epc_size; 6805 6806 if (sgx_epc_get_section(count - 2, &epc_addr, &epc_size)) { 6807 *eax = *ebx = *ecx = *edx = 0; 6808 break; 6809 } 6810 host_cpuid(index, 2, eax, ebx, ecx, edx); 6811 *eax = (uint32_t)(epc_addr & 0xfffff000) | 0x1; 6812 *ebx = (uint32_t)(epc_addr >> 32); 6813 *ecx = (uint32_t)(epc_size & 0xfffff000) | (*ecx & 0xf); 6814 *edx = (uint32_t)(epc_size >> 32); 6815 break; 6816 } 6817 6818 /* 6819 * SGX sub-leafs CPUID.0x12.{0x0,0x1} are heavily dependent on hardware 6820 * and KVM, i.e. QEMU cannot emulate features to override what KVM 6821 * supports. Features can be further restricted by userspace, but not 6822 * made more permissive. 6823 */ 6824 x86_cpu_get_supported_cpuid(0x12, count, eax, ebx, ecx, edx); 6825 6826 if (count == 0) { 6827 *eax &= env->features[FEAT_SGX_12_0_EAX]; 6828 *ebx &= env->features[FEAT_SGX_12_0_EBX]; 6829 } else { 6830 *eax &= env->features[FEAT_SGX_12_1_EAX]; 6831 *ebx &= 0; /* ebx reserve */ 6832 *ecx &= env->features[FEAT_XSAVE_XCR0_LO]; 6833 *edx &= env->features[FEAT_XSAVE_XCR0_HI]; 6834 6835 /* FP and SSE are always allowed regardless of XSAVE/XCR0. */ 6836 *ecx |= XSTATE_FP_MASK | XSTATE_SSE_MASK; 6837 6838 /* Access to PROVISIONKEY requires additional credentials. */ 6839 if ((*eax & (1U << 4)) && 6840 !kvm_enable_sgx_provisioning(cs->kvm_state)) { 6841 *eax &= ~(1U << 4); 6842 } 6843 } 6844 #endif 6845 break; 6846 case 0x14: { 6847 /* Intel Processor Trace Enumeration */ 6848 *eax = 0; 6849 *ebx = 0; 6850 *ecx = 0; 6851 *edx = 0; 6852 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) || 6853 !kvm_enabled()) { 6854 break; 6855 } 6856 6857 /* 6858 * If these are changed, they should stay in sync with 6859 * x86_cpu_filter_features(). 6860 */ 6861 if (count == 0) { 6862 *eax = INTEL_PT_MAX_SUBLEAF; 6863 *ebx = INTEL_PT_MINIMAL_EBX; 6864 *ecx = INTEL_PT_MINIMAL_ECX; 6865 if (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP) { 6866 *ecx |= CPUID_14_0_ECX_LIP; 6867 } 6868 } else if (count == 1) { 6869 *eax = INTEL_PT_MTC_BITMAP | INTEL_PT_ADDR_RANGES_NUM; 6870 *ebx = INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP; 6871 } 6872 break; 6873 } 6874 case 0x1D: { 6875 /* AMX TILE, for now hardcoded for Sapphire Rapids*/ 6876 *eax = 0; 6877 *ebx = 0; 6878 *ecx = 0; 6879 *edx = 0; 6880 if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) { 6881 break; 6882 } 6883 6884 if (count == 0) { 6885 /* Highest numbered palette subleaf */ 6886 *eax = INTEL_AMX_TILE_MAX_SUBLEAF; 6887 } else if (count == 1) { 6888 *eax = INTEL_AMX_TOTAL_TILE_BYTES | 6889 (INTEL_AMX_BYTES_PER_TILE << 16); 6890 *ebx = INTEL_AMX_BYTES_PER_ROW | (INTEL_AMX_TILE_MAX_NAMES << 16); 6891 *ecx = INTEL_AMX_TILE_MAX_ROWS; 6892 } 6893 break; 6894 } 6895 case 0x1E: { 6896 /* AMX TMUL, for now hardcoded for Sapphire Rapids */ 6897 *eax = 0; 6898 *ebx = 0; 6899 *ecx = 0; 6900 *edx = 0; 6901 if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) { 6902 break; 6903 } 6904 6905 if (count == 0) { 6906 /* Highest numbered palette subleaf */ 6907 *ebx = INTEL_AMX_TMUL_MAX_K | (INTEL_AMX_TMUL_MAX_N << 8); 6908 } 6909 break; 6910 } 6911 case 0x24: { 6912 *eax = 0; 6913 *ebx = 0; 6914 *ecx = 0; 6915 *edx = 0; 6916 if ((env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) && count == 0) { 6917 *ebx = env->features[FEAT_24_0_EBX] | env->avx10_version; 6918 } 6919 break; 6920 } 6921 case 0x40000000: 6922 /* 6923 * CPUID code in kvm_arch_init_vcpu() ignores stuff 6924 * set here, but we restrict to TCG none the less. 6925 */ 6926 if (tcg_enabled() && cpu->expose_tcg) { 6927 memcpy(signature, "TCGTCGTCGTCG", 12); 6928 *eax = 0x40000001; 6929 *ebx = signature[0]; 6930 *ecx = signature[1]; 6931 *edx = signature[2]; 6932 } else { 6933 *eax = 0; 6934 *ebx = 0; 6935 *ecx = 0; 6936 *edx = 0; 6937 } 6938 break; 6939 case 0x40000001: 6940 *eax = 0; 6941 *ebx = 0; 6942 *ecx = 0; 6943 *edx = 0; 6944 break; 6945 case 0x80000000: 6946 *eax = env->cpuid_xlevel; 6947 *ebx = env->cpuid_vendor1; 6948 *edx = env->cpuid_vendor2; 6949 *ecx = env->cpuid_vendor3; 6950 break; 6951 case 0x80000001: 6952 *eax = env->cpuid_version; 6953 *ebx = 0; 6954 *ecx = env->features[FEAT_8000_0001_ECX]; 6955 *edx = env->features[FEAT_8000_0001_EDX]; 6956 6957 /* The Linux kernel checks for the CMPLegacy bit and 6958 * discards multiple thread information if it is set. 6959 * So don't set it here for Intel to make Linux guests happy. 6960 */ 6961 if (threads_per_pkg > 1) { 6962 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 || 6963 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 || 6964 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) { 6965 *ecx |= 1 << 1; /* CmpLegacy bit */ 6966 } 6967 } 6968 if (tcg_enabled() && env->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && 6969 !(env->hflags & HF_LMA_MASK)) { 6970 *edx &= ~CPUID_EXT2_SYSCALL; 6971 } 6972 break; 6973 case 0x80000002: 6974 case 0x80000003: 6975 case 0x80000004: 6976 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0]; 6977 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1]; 6978 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2]; 6979 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3]; 6980 break; 6981 case 0x80000005: 6982 /* cache info (L1 cache) */ 6983 if (cpu->cache_info_passthrough) { 6984 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 6985 break; 6986 } 6987 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | 6988 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES); 6989 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | 6990 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES); 6991 *ecx = encode_cache_cpuid80000005(env->cache_info_amd.l1d_cache); 6992 *edx = encode_cache_cpuid80000005(env->cache_info_amd.l1i_cache); 6993 break; 6994 case 0x80000006: 6995 /* cache info (L2 cache) */ 6996 if (cpu->cache_info_passthrough) { 6997 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 6998 break; 6999 } 7000 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | 7001 (L2_DTLB_2M_ENTRIES << 16) | 7002 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | 7003 (L2_ITLB_2M_ENTRIES); 7004 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | 7005 (L2_DTLB_4K_ENTRIES << 16) | 7006 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | 7007 (L2_ITLB_4K_ENTRIES); 7008 encode_cache_cpuid80000006(env->cache_info_amd.l2_cache, 7009 cpu->enable_l3_cache ? 7010 env->cache_info_amd.l3_cache : NULL, 7011 ecx, edx); 7012 break; 7013 case 0x80000007: 7014 *eax = 0; 7015 *ebx = env->features[FEAT_8000_0007_EBX]; 7016 *ecx = 0; 7017 *edx = env->features[FEAT_8000_0007_EDX]; 7018 break; 7019 case 0x80000008: 7020 /* virtual & phys address size in low 2 bytes. */ 7021 *eax = cpu->phys_bits; 7022 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 7023 /* 64 bit processor */ 7024 *eax |= (cpu_x86_virtual_addr_width(env) << 8); 7025 *eax |= (cpu->guest_phys_bits << 16); 7026 } 7027 *ebx = env->features[FEAT_8000_0008_EBX]; 7028 if (threads_per_pkg > 1) { 7029 /* 7030 * Bits 15:12 is "The number of bits in the initial 7031 * Core::X86::Apic::ApicId[ApicId] value that indicate 7032 * thread ID within a package". 7033 * Bits 7:0 is "The number of threads in the package is NC+1" 7034 */ 7035 *ecx = (apicid_pkg_offset(topo_info) << 12) | 7036 (threads_per_pkg - 1); 7037 } else { 7038 *ecx = 0; 7039 } 7040 *edx = 0; 7041 break; 7042 case 0x8000000A: 7043 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { 7044 *eax = 0x00000001; /* SVM Revision */ 7045 *ebx = 0x00000010; /* nr of ASIDs */ 7046 *ecx = 0; 7047 *edx = env->features[FEAT_SVM]; /* optional features */ 7048 } else { 7049 *eax = 0; 7050 *ebx = 0; 7051 *ecx = 0; 7052 *edx = 0; 7053 } 7054 break; 7055 case 0x8000001D: 7056 *eax = 0; 7057 if (cpu->cache_info_passthrough) { 7058 x86_cpu_get_cache_cpuid(index, count, eax, ebx, ecx, edx); 7059 break; 7060 } 7061 switch (count) { 7062 case 0: /* L1 dcache info */ 7063 encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache, 7064 topo_info, eax, ebx, ecx, edx); 7065 break; 7066 case 1: /* L1 icache info */ 7067 encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache, 7068 topo_info, eax, ebx, ecx, edx); 7069 break; 7070 case 2: /* L2 cache info */ 7071 encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache, 7072 topo_info, eax, ebx, ecx, edx); 7073 break; 7074 case 3: /* L3 cache info */ 7075 encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache, 7076 topo_info, eax, ebx, ecx, edx); 7077 break; 7078 default: /* end of info */ 7079 *eax = *ebx = *ecx = *edx = 0; 7080 break; 7081 } 7082 if (cpu->amd_topoext_features_only) { 7083 *edx &= CACHE_NO_INVD_SHARING | CACHE_INCLUSIVE; 7084 } 7085 break; 7086 case 0x8000001E: 7087 if (cpu->core_id <= 255) { 7088 encode_topo_cpuid8000001e(cpu, topo_info, eax, ebx, ecx, edx); 7089 } else { 7090 *eax = 0; 7091 *ebx = 0; 7092 *ecx = 0; 7093 *edx = 0; 7094 } 7095 break; 7096 case 0x80000022: 7097 *eax = *ebx = *ecx = *edx = 0; 7098 /* AMD Extended Performance Monitoring and Debug */ 7099 if (kvm_enabled() && cpu->enable_pmu && 7100 (env->features[FEAT_8000_0022_EAX] & CPUID_8000_0022_EAX_PERFMON_V2)) { 7101 *eax |= CPUID_8000_0022_EAX_PERFMON_V2; 7102 *ebx |= kvm_arch_get_supported_cpuid(cs->kvm_state, index, count, 7103 R_EBX) & 0xf; 7104 } 7105 break; 7106 case 0xC0000000: 7107 *eax = env->cpuid_xlevel2; 7108 *ebx = 0; 7109 *ecx = 0; 7110 *edx = 0; 7111 break; 7112 case 0xC0000001: 7113 /* Support for VIA CPU's CPUID instruction */ 7114 *eax = env->cpuid_version; 7115 *ebx = 0; 7116 *ecx = 0; 7117 *edx = env->features[FEAT_C000_0001_EDX]; 7118 break; 7119 case 0xC0000002: 7120 case 0xC0000003: 7121 case 0xC0000004: 7122 /* Reserved for the future, and now filled with zero */ 7123 *eax = 0; 7124 *ebx = 0; 7125 *ecx = 0; 7126 *edx = 0; 7127 break; 7128 case 0x8000001F: 7129 *eax = *ebx = *ecx = *edx = 0; 7130 if (sev_enabled()) { 7131 *eax = 0x2; 7132 *eax |= sev_es_enabled() ? 0x8 : 0; 7133 *eax |= sev_snp_enabled() ? 0x10 : 0; 7134 *ebx = sev_get_cbit_position() & 0x3f; /* EBX[5:0] */ 7135 *ebx |= (sev_get_reduced_phys_bits() & 0x3f) << 6; /* EBX[11:6] */ 7136 } 7137 break; 7138 case 0x80000021: 7139 *eax = *ebx = *ecx = *edx = 0; 7140 *eax = env->features[FEAT_8000_0021_EAX]; 7141 *ebx = env->features[FEAT_8000_0021_EBX]; 7142 break; 7143 default: 7144 /* reserved values: zero */ 7145 *eax = 0; 7146 *ebx = 0; 7147 *ecx = 0; 7148 *edx = 0; 7149 break; 7150 } 7151 } 7152 7153 static void x86_cpu_set_sgxlepubkeyhash(CPUX86State *env) 7154 { 7155 #ifndef CONFIG_USER_ONLY 7156 /* Those default values are defined in Skylake HW */ 7157 env->msr_ia32_sgxlepubkeyhash[0] = 0xa6053e051270b7acULL; 7158 env->msr_ia32_sgxlepubkeyhash[1] = 0x6cfbe8ba8b3b413dULL; 7159 env->msr_ia32_sgxlepubkeyhash[2] = 0xc4916d99f2b3735dULL; 7160 env->msr_ia32_sgxlepubkeyhash[3] = 0xd4f8c05909f9bb3bULL; 7161 #endif 7162 } 7163 7164 static bool cpuid_has_xsave_feature(CPUX86State *env, const ExtSaveArea *esa) 7165 { 7166 if (!esa->size) { 7167 return false; 7168 } 7169 7170 if (env->features[esa->feature] & esa->bits) { 7171 return true; 7172 } 7173 if (esa->feature == FEAT_7_0_EBX && esa->bits == CPUID_7_0_EBX_AVX512F 7174 && (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10)) { 7175 return true; 7176 } 7177 7178 return false; 7179 } 7180 7181 static void x86_cpu_reset_hold(Object *obj, ResetType type) 7182 { 7183 CPUState *cs = CPU(obj); 7184 X86CPU *cpu = X86_CPU(cs); 7185 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj); 7186 CPUX86State *env = &cpu->env; 7187 target_ulong cr4; 7188 uint64_t xcr0; 7189 int i; 7190 7191 if (xcc->parent_phases.hold) { 7192 xcc->parent_phases.hold(obj, type); 7193 } 7194 7195 memset(env, 0, offsetof(CPUX86State, end_reset_fields)); 7196 7197 if (tcg_enabled()) { 7198 cpu_init_fp_statuses(env); 7199 } 7200 7201 env->old_exception = -1; 7202 7203 /* init to reset state */ 7204 env->int_ctl = 0; 7205 env->hflags2 |= HF2_GIF_MASK; 7206 env->hflags2 |= HF2_VGIF_MASK; 7207 env->hflags &= ~HF_GUEST_MASK; 7208 7209 cpu_x86_update_cr0(env, 0x60000010); 7210 env->a20_mask = ~0x0; 7211 env->smbase = 0x30000; 7212 env->msr_smi_count = 0; 7213 7214 env->idt.limit = 0xffff; 7215 env->gdt.limit = 0xffff; 7216 env->ldt.limit = 0xffff; 7217 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT); 7218 env->tr.limit = 0xffff; 7219 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT); 7220 7221 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff, 7222 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK | 7223 DESC_R_MASK | DESC_A_MASK); 7224 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff, 7225 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7226 DESC_A_MASK); 7227 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff, 7228 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7229 DESC_A_MASK); 7230 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff, 7231 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7232 DESC_A_MASK); 7233 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff, 7234 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7235 DESC_A_MASK); 7236 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff, 7237 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7238 DESC_A_MASK); 7239 7240 env->eip = 0xfff0; 7241 env->regs[R_EDX] = env->cpuid_version; 7242 7243 env->eflags = 0x2; 7244 7245 /* FPU init */ 7246 for (i = 0; i < 8; i++) { 7247 env->fptags[i] = 1; 7248 } 7249 cpu_set_fpuc(env, 0x37f); 7250 7251 env->mxcsr = 0x1f80; 7252 /* All units are in INIT state. */ 7253 env->xstate_bv = 0; 7254 7255 env->pat = 0x0007040600070406ULL; 7256 7257 if (kvm_enabled()) { 7258 /* 7259 * KVM handles TSC = 0 specially and thinks we are hot-plugging 7260 * a new CPU, use 1 instead to force a reset. 7261 */ 7262 if (env->tsc != 0) { 7263 env->tsc = 1; 7264 } 7265 } else { 7266 env->tsc = 0; 7267 } 7268 7269 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT; 7270 if (env->features[FEAT_1_ECX] & CPUID_EXT_MONITOR) { 7271 env->msr_ia32_misc_enable |= MSR_IA32_MISC_ENABLE_MWAIT; 7272 } 7273 7274 memset(env->dr, 0, sizeof(env->dr)); 7275 env->dr[6] = DR6_FIXED_1; 7276 env->dr[7] = DR7_FIXED_1; 7277 cpu_breakpoint_remove_all(cs, BP_CPU); 7278 cpu_watchpoint_remove_all(cs, BP_CPU); 7279 7280 cr4 = 0; 7281 xcr0 = XSTATE_FP_MASK; 7282 7283 #ifdef CONFIG_USER_ONLY 7284 /* Enable all the features for user-mode. */ 7285 if (env->features[FEAT_1_EDX] & CPUID_SSE) { 7286 xcr0 |= XSTATE_SSE_MASK; 7287 } 7288 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 7289 const ExtSaveArea *esa = &x86_ext_save_areas[i]; 7290 if (!((1 << i) & CPUID_XSTATE_XCR0_MASK)) { 7291 continue; 7292 } 7293 if (cpuid_has_xsave_feature(env, esa)) { 7294 xcr0 |= 1ull << i; 7295 } 7296 } 7297 7298 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) { 7299 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK; 7300 } 7301 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) { 7302 cr4 |= CR4_FSGSBASE_MASK; 7303 } 7304 #endif 7305 7306 env->xcr0 = xcr0; 7307 cpu_x86_update_cr4(env, cr4); 7308 7309 /* 7310 * SDM 11.11.5 requires: 7311 * - IA32_MTRR_DEF_TYPE MSR.E = 0 7312 * - IA32_MTRR_PHYSMASKn.V = 0 7313 * All other bits are undefined. For simplification, zero it all. 7314 */ 7315 env->mtrr_deftype = 0; 7316 memset(env->mtrr_var, 0, sizeof(env->mtrr_var)); 7317 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed)); 7318 7319 env->interrupt_injected = -1; 7320 env->exception_nr = -1; 7321 env->exception_pending = 0; 7322 env->exception_injected = 0; 7323 env->exception_has_payload = false; 7324 env->exception_payload = 0; 7325 env->nmi_injected = false; 7326 env->triple_fault_pending = false; 7327 #if !defined(CONFIG_USER_ONLY) 7328 /* We hard-wire the BSP to the first CPU. */ 7329 apic_designate_bsp(cpu->apic_state, cs->cpu_index == 0); 7330 7331 cs->halted = !cpu_is_bsp(cpu); 7332 7333 if (kvm_enabled()) { 7334 kvm_arch_reset_vcpu(cpu); 7335 } 7336 7337 x86_cpu_set_sgxlepubkeyhash(env); 7338 7339 env->amd_tsc_scale_msr = MSR_AMD64_TSC_RATIO_DEFAULT; 7340 7341 #endif 7342 } 7343 7344 void x86_cpu_after_reset(X86CPU *cpu) 7345 { 7346 #ifndef CONFIG_USER_ONLY 7347 if (kvm_enabled()) { 7348 kvm_arch_after_reset_vcpu(cpu); 7349 } 7350 7351 if (cpu->apic_state) { 7352 device_cold_reset(cpu->apic_state); 7353 } 7354 #endif 7355 } 7356 7357 static void mce_init(X86CPU *cpu) 7358 { 7359 CPUX86State *cenv = &cpu->env; 7360 unsigned int bank; 7361 7362 if (((cenv->cpuid_version >> 8) & 0xf) >= 6 7363 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) == 7364 (CPUID_MCE | CPUID_MCA)) { 7365 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF | 7366 (cpu->enable_lmce ? MCG_LMCE_P : 0); 7367 cenv->mcg_ctl = ~(uint64_t)0; 7368 for (bank = 0; bank < MCE_BANKS_DEF; bank++) { 7369 cenv->mce_banks[bank * 4] = ~(uint64_t)0; 7370 } 7371 } 7372 } 7373 7374 static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value) 7375 { 7376 if (*min < value) { 7377 *min = value; 7378 } 7379 } 7380 7381 /* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */ 7382 static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w) 7383 { 7384 CPUX86State *env = &cpu->env; 7385 FeatureWordInfo *fi = &feature_word_info[w]; 7386 uint32_t eax = fi->cpuid.eax; 7387 uint32_t region = eax & 0xF0000000; 7388 7389 assert(feature_word_info[w].type == CPUID_FEATURE_WORD); 7390 if (!env->features[w]) { 7391 return; 7392 } 7393 7394 switch (region) { 7395 case 0x00000000: 7396 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax); 7397 break; 7398 case 0x80000000: 7399 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax); 7400 break; 7401 case 0xC0000000: 7402 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax); 7403 break; 7404 } 7405 7406 if (eax == 7) { 7407 x86_cpu_adjust_level(cpu, &env->cpuid_min_level_func7, 7408 fi->cpuid.ecx); 7409 } 7410 } 7411 7412 /* Calculate XSAVE components based on the configured CPU feature flags */ 7413 static void x86_cpu_enable_xsave_components(X86CPU *cpu) 7414 { 7415 CPUX86State *env = &cpu->env; 7416 int i; 7417 uint64_t mask; 7418 static bool request_perm; 7419 7420 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { 7421 env->features[FEAT_XSAVE_XCR0_LO] = 0; 7422 env->features[FEAT_XSAVE_XCR0_HI] = 0; 7423 env->features[FEAT_XSAVE_XSS_LO] = 0; 7424 env->features[FEAT_XSAVE_XSS_HI] = 0; 7425 return; 7426 } 7427 7428 mask = 0; 7429 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 7430 const ExtSaveArea *esa = &x86_ext_save_areas[i]; 7431 if (cpuid_has_xsave_feature(env, esa)) { 7432 mask |= (1ULL << i); 7433 } 7434 } 7435 7436 /* Only request permission for first vcpu */ 7437 if (kvm_enabled() && !request_perm) { 7438 kvm_request_xsave_components(cpu, mask); 7439 request_perm = true; 7440 } 7441 7442 env->features[FEAT_XSAVE_XCR0_LO] = mask & CPUID_XSTATE_XCR0_MASK; 7443 env->features[FEAT_XSAVE_XCR0_HI] = (mask & CPUID_XSTATE_XCR0_MASK) >> 32; 7444 env->features[FEAT_XSAVE_XSS_LO] = mask & CPUID_XSTATE_XSS_MASK; 7445 env->features[FEAT_XSAVE_XSS_HI] = (mask & CPUID_XSTATE_XSS_MASK) >> 32; 7446 } 7447 7448 /***** Steps involved on loading and filtering CPUID data 7449 * 7450 * When initializing and realizing a CPU object, the steps 7451 * involved in setting up CPUID data are: 7452 * 7453 * 1) Loading CPU model definition (X86CPUDefinition). This is 7454 * implemented by x86_cpu_load_model() and should be completely 7455 * transparent, as it is done automatically by instance_init. 7456 * No code should need to look at X86CPUDefinition structs 7457 * outside instance_init. 7458 * 7459 * 2) CPU expansion. This is done by realize before CPUID 7460 * filtering, and will make sure host/accelerator data is 7461 * loaded for CPU models that depend on host capabilities 7462 * (e.g. "host"). Done by x86_cpu_expand_features(). 7463 * 7464 * 3) CPUID filtering. This initializes extra data related to 7465 * CPUID, and checks if the host supports all capabilities 7466 * required by the CPU. Runnability of a CPU model is 7467 * determined at this step. Done by x86_cpu_filter_features(). 7468 * 7469 * Some operations don't require all steps to be performed. 7470 * More precisely: 7471 * 7472 * - CPU instance creation (instance_init) will run only CPU 7473 * model loading. CPU expansion can't run at instance_init-time 7474 * because host/accelerator data may be not available yet. 7475 * - CPU realization will perform both CPU model expansion and CPUID 7476 * filtering, and return an error in case one of them fails. 7477 * - query-cpu-definitions needs to run all 3 steps. It needs 7478 * to run CPUID filtering, as the 'unavailable-features' 7479 * field is set based on the filtering results. 7480 * - The query-cpu-model-expansion QMP command only needs to run 7481 * CPU model loading and CPU expansion. It should not filter 7482 * any CPUID data based on host capabilities. 7483 */ 7484 7485 /* Expand CPU configuration data, based on configured features 7486 * and host/accelerator capabilities when appropriate. 7487 */ 7488 void x86_cpu_expand_features(X86CPU *cpu, Error **errp) 7489 { 7490 CPUX86State *env = &cpu->env; 7491 FeatureWord w; 7492 int i; 7493 GList *l; 7494 7495 for (l = plus_features; l; l = l->next) { 7496 const char *prop = l->data; 7497 if (!object_property_set_bool(OBJECT(cpu), prop, true, errp)) { 7498 return; 7499 } 7500 } 7501 7502 for (l = minus_features; l; l = l->next) { 7503 const char *prop = l->data; 7504 if (!object_property_set_bool(OBJECT(cpu), prop, false, errp)) { 7505 return; 7506 } 7507 } 7508 7509 /*TODO: Now cpu->max_features doesn't overwrite features 7510 * set using QOM properties, and we can convert 7511 * plus_features & minus_features to global properties 7512 * inside x86_cpu_parse_featurestr() too. 7513 */ 7514 if (cpu->max_features) { 7515 for (w = 0; w < FEATURE_WORDS; w++) { 7516 /* Override only features that weren't set explicitly 7517 * by the user. 7518 */ 7519 env->features[w] |= 7520 x86_cpu_get_supported_feature_word(cpu, w) & 7521 ~env->user_features[w] & 7522 ~feature_word_info[w].no_autoenable_flags; 7523 } 7524 7525 if ((env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) && !env->avx10_version) { 7526 uint32_t eax, ebx, ecx, edx; 7527 x86_cpu_get_supported_cpuid(0x24, 0, &eax, &ebx, &ecx, &edx); 7528 env->avx10_version = ebx & 0xff; 7529 } 7530 } 7531 7532 for (i = 0; i < ARRAY_SIZE(feature_dependencies); i++) { 7533 FeatureDep *d = &feature_dependencies[i]; 7534 if (!(env->features[d->from.index] & d->from.mask)) { 7535 uint64_t unavailable_features = env->features[d->to.index] & d->to.mask; 7536 7537 /* Not an error unless the dependent feature was added explicitly. */ 7538 mark_unavailable_features(cpu, d->to.index, 7539 unavailable_features & env->user_features[d->to.index], 7540 "This feature depends on other features that were not requested"); 7541 7542 env->features[d->to.index] &= ~unavailable_features; 7543 } 7544 } 7545 7546 if (!kvm_enabled() || !cpu->expose_kvm) { 7547 env->features[FEAT_KVM] = 0; 7548 } 7549 7550 x86_cpu_enable_xsave_components(cpu); 7551 7552 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */ 7553 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX); 7554 if (cpu->full_cpuid_auto_level) { 7555 x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX); 7556 x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX); 7557 x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX); 7558 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX); 7559 x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EAX); 7560 x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EDX); 7561 x86_cpu_adjust_feat_level(cpu, FEAT_7_2_EDX); 7562 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX); 7563 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX); 7564 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX); 7565 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0008_EBX); 7566 x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX); 7567 x86_cpu_adjust_feat_level(cpu, FEAT_SVM); 7568 x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE); 7569 7570 /* Intel Processor Trace requires CPUID[0x14] */ 7571 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT)) { 7572 if (cpu->intel_pt_auto_level) { 7573 x86_cpu_adjust_level(cpu, &cpu->env.cpuid_min_level, 0x14); 7574 } else if (cpu->env.cpuid_min_level < 0x14) { 7575 mark_unavailable_features(cpu, FEAT_7_0_EBX, 7576 CPUID_7_0_EBX_INTEL_PT, 7577 "Intel PT need CPUID leaf 0x14, please set by \"-cpu ...,intel-pt=on,min-level=0x14\""); 7578 } 7579 } 7580 7581 /* 7582 * Intel CPU topology with multi-dies support requires CPUID[0x1F]. 7583 * For AMD Rome/Milan, cpuid level is 0x10, and guest OS should detect 7584 * extended toplogy by leaf 0xB. Only adjust it for Intel CPU, unless 7585 * cpu->vendor_cpuid_only has been unset for compatibility with older 7586 * machine types. 7587 */ 7588 if (x86_has_extended_topo(env->avail_cpu_topo) && 7589 (IS_INTEL_CPU(env) || !cpu->vendor_cpuid_only)) { 7590 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x1F); 7591 } 7592 7593 /* Advanced Vector Extensions 10 (AVX10) requires CPUID[0x24] */ 7594 if (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) { 7595 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x24); 7596 } 7597 7598 /* SVM requires CPUID[0x8000000A] */ 7599 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { 7600 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A); 7601 } 7602 7603 /* SEV requires CPUID[0x8000001F] */ 7604 if (sev_enabled()) { 7605 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F); 7606 } 7607 7608 if (env->features[FEAT_8000_0021_EAX]) { 7609 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x80000021); 7610 } 7611 7612 /* SGX requires CPUID[0x12] for EPC enumeration */ 7613 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX) { 7614 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x12); 7615 } 7616 } 7617 7618 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */ 7619 if (env->cpuid_level_func7 == UINT32_MAX) { 7620 env->cpuid_level_func7 = env->cpuid_min_level_func7; 7621 } 7622 if (env->cpuid_level == UINT32_MAX) { 7623 env->cpuid_level = env->cpuid_min_level; 7624 } 7625 if (env->cpuid_xlevel == UINT32_MAX) { 7626 env->cpuid_xlevel = env->cpuid_min_xlevel; 7627 } 7628 if (env->cpuid_xlevel2 == UINT32_MAX) { 7629 env->cpuid_xlevel2 = env->cpuid_min_xlevel2; 7630 } 7631 7632 if (kvm_enabled() && !kvm_hyperv_expand_features(cpu, errp)) { 7633 return; 7634 } 7635 } 7636 7637 /* 7638 * Finishes initialization of CPUID data, filters CPU feature 7639 * words based on host availability of each feature. 7640 * 7641 * Returns: true if any flag is not supported by the host, false otherwise. 7642 */ 7643 static bool x86_cpu_filter_features(X86CPU *cpu, bool verbose) 7644 { 7645 CPUX86State *env = &cpu->env; 7646 FeatureWord w; 7647 const char *prefix = NULL; 7648 bool have_filtered_features; 7649 7650 uint32_t eax_0, ebx_0, ecx_0, edx_0; 7651 uint32_t eax_1, ebx_1, ecx_1, edx_1; 7652 7653 if (verbose) { 7654 prefix = accel_uses_host_cpuid() 7655 ? "host doesn't support requested feature" 7656 : "TCG doesn't support requested feature"; 7657 } 7658 7659 for (w = 0; w < FEATURE_WORDS; w++) { 7660 uint64_t host_feat = 7661 x86_cpu_get_supported_feature_word(NULL, w); 7662 uint64_t requested_features = env->features[w]; 7663 uint64_t unavailable_features = requested_features & ~host_feat; 7664 mark_unavailable_features(cpu, w, unavailable_features, prefix); 7665 } 7666 7667 /* 7668 * Check that KVM actually allows the processor tracing features that 7669 * are advertised by cpu_x86_cpuid(). Keep these two in sync. 7670 */ 7671 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) && 7672 kvm_enabled()) { 7673 x86_cpu_get_supported_cpuid(0x14, 0, 7674 &eax_0, &ebx_0, &ecx_0, &edx_0); 7675 x86_cpu_get_supported_cpuid(0x14, 1, 7676 &eax_1, &ebx_1, &ecx_1, &edx_1); 7677 7678 if (!eax_0 || 7679 ((ebx_0 & INTEL_PT_MINIMAL_EBX) != INTEL_PT_MINIMAL_EBX) || 7680 ((ecx_0 & INTEL_PT_MINIMAL_ECX) != INTEL_PT_MINIMAL_ECX) || 7681 ((eax_1 & INTEL_PT_MTC_BITMAP) != INTEL_PT_MTC_BITMAP) || 7682 ((eax_1 & INTEL_PT_ADDR_RANGES_NUM_MASK) < 7683 INTEL_PT_ADDR_RANGES_NUM) || 7684 ((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) != 7685 (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) || 7686 ((ecx_0 & CPUID_14_0_ECX_LIP) != 7687 (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP))) { 7688 /* 7689 * Processor Trace capabilities aren't configurable, so if the 7690 * host can't emulate the capabilities we report on 7691 * cpu_x86_cpuid(), intel-pt can't be enabled on the current host. 7692 */ 7693 mark_unavailable_features(cpu, FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT, prefix); 7694 } 7695 } 7696 7697 have_filtered_features = x86_cpu_have_filtered_features(cpu); 7698 7699 if (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) { 7700 x86_cpu_get_supported_cpuid(0x24, 0, 7701 &eax_0, &ebx_0, &ecx_0, &edx_0); 7702 uint8_t version = ebx_0 & 0xff; 7703 7704 if (version < env->avx10_version) { 7705 if (prefix) { 7706 warn_report("%s: avx10.%d. Adjust to avx10.%d", 7707 prefix, env->avx10_version, version); 7708 } 7709 env->avx10_version = version; 7710 have_filtered_features = true; 7711 } 7712 } else if (env->avx10_version) { 7713 if (prefix) { 7714 warn_report("%s: avx10.%d.", prefix, env->avx10_version); 7715 } 7716 have_filtered_features = true; 7717 } 7718 7719 return have_filtered_features; 7720 } 7721 7722 static void x86_cpu_hyperv_realize(X86CPU *cpu) 7723 { 7724 size_t len; 7725 7726 /* Hyper-V vendor id */ 7727 if (!cpu->hyperv_vendor) { 7728 object_property_set_str(OBJECT(cpu), "hv-vendor-id", "Microsoft Hv", 7729 &error_abort); 7730 } 7731 len = strlen(cpu->hyperv_vendor); 7732 if (len > 12) { 7733 warn_report("hv-vendor-id truncated to 12 characters"); 7734 len = 12; 7735 } 7736 memset(cpu->hyperv_vendor_id, 0, 12); 7737 memcpy(cpu->hyperv_vendor_id, cpu->hyperv_vendor, len); 7738 7739 /* 'Hv#1' interface identification*/ 7740 cpu->hyperv_interface_id[0] = 0x31237648; 7741 cpu->hyperv_interface_id[1] = 0; 7742 cpu->hyperv_interface_id[2] = 0; 7743 cpu->hyperv_interface_id[3] = 0; 7744 7745 /* Hypervisor implementation limits */ 7746 cpu->hyperv_limits[0] = 64; 7747 cpu->hyperv_limits[1] = 0; 7748 cpu->hyperv_limits[2] = 0; 7749 } 7750 7751 static void x86_cpu_realizefn(DeviceState *dev, Error **errp) 7752 { 7753 CPUState *cs = CPU(dev); 7754 X86CPU *cpu = X86_CPU(dev); 7755 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev); 7756 CPUX86State *env = &cpu->env; 7757 Error *local_err = NULL; 7758 unsigned requested_lbr_fmt; 7759 7760 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) 7761 /* Use pc-relative instructions in system-mode */ 7762 tcg_cflags_set(cs, CF_PCREL); 7763 #endif 7764 7765 if (cpu->apic_id == UNASSIGNED_APIC_ID) { 7766 error_setg(errp, "apic-id property was not initialized properly"); 7767 return; 7768 } 7769 7770 /* 7771 * Process Hyper-V enlightenments. 7772 * Note: this currently has to happen before the expansion of CPU features. 7773 */ 7774 x86_cpu_hyperv_realize(cpu); 7775 7776 x86_cpu_expand_features(cpu, &local_err); 7777 if (local_err) { 7778 goto out; 7779 } 7780 7781 /* 7782 * Override env->features[FEAT_PERF_CAPABILITIES].LBR_FMT 7783 * with user-provided setting. 7784 */ 7785 if (cpu->lbr_fmt != ~PERF_CAP_LBR_FMT) { 7786 if ((cpu->lbr_fmt & PERF_CAP_LBR_FMT) != cpu->lbr_fmt) { 7787 error_setg(errp, "invalid lbr-fmt"); 7788 return; 7789 } 7790 env->features[FEAT_PERF_CAPABILITIES] &= ~PERF_CAP_LBR_FMT; 7791 env->features[FEAT_PERF_CAPABILITIES] |= cpu->lbr_fmt; 7792 } 7793 7794 /* 7795 * vPMU LBR is supported when 1) KVM is enabled 2) Option pmu=on and 7796 * 3)vPMU LBR format matches that of host setting. 7797 */ 7798 requested_lbr_fmt = 7799 env->features[FEAT_PERF_CAPABILITIES] & PERF_CAP_LBR_FMT; 7800 if (requested_lbr_fmt && kvm_enabled()) { 7801 uint64_t host_perf_cap = 7802 x86_cpu_get_supported_feature_word(NULL, FEAT_PERF_CAPABILITIES); 7803 unsigned host_lbr_fmt = host_perf_cap & PERF_CAP_LBR_FMT; 7804 7805 if (!cpu->enable_pmu) { 7806 error_setg(errp, "vPMU: LBR is unsupported without pmu=on"); 7807 return; 7808 } 7809 if (requested_lbr_fmt != host_lbr_fmt) { 7810 error_setg(errp, "vPMU: the lbr-fmt value (0x%x) does not match " 7811 "the host value (0x%x).", 7812 requested_lbr_fmt, host_lbr_fmt); 7813 return; 7814 } 7815 } 7816 7817 if (x86_cpu_filter_features(cpu, cpu->check_cpuid || cpu->enforce_cpuid)) { 7818 if (cpu->enforce_cpuid) { 7819 error_setg(&local_err, 7820 accel_uses_host_cpuid() ? 7821 "Host doesn't support requested features" : 7822 "TCG doesn't support requested features"); 7823 goto out; 7824 } 7825 } 7826 7827 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on 7828 * CPUID[1].EDX. 7829 */ 7830 if (IS_AMD_CPU(env)) { 7831 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES; 7832 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX] 7833 & CPUID_EXT2_AMD_ALIASES); 7834 } 7835 7836 x86_cpu_set_sgxlepubkeyhash(env); 7837 7838 /* 7839 * note: the call to the framework needs to happen after feature expansion, 7840 * but before the checks/modifications to ucode_rev, mwait, phys_bits. 7841 * These may be set by the accel-specific code, 7842 * and the results are subsequently checked / assumed in this function. 7843 */ 7844 cpu_exec_realizefn(cs, &local_err); 7845 if (local_err != NULL) { 7846 error_propagate(errp, local_err); 7847 return; 7848 } 7849 7850 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) { 7851 g_autofree char *name = x86_cpu_class_get_model_name(xcc); 7852 error_setg(&local_err, "CPU model '%s' requires KVM or HVF", name); 7853 goto out; 7854 } 7855 7856 if (cpu->guest_phys_bits == -1) { 7857 /* 7858 * If it was not set by the user, or by the accelerator via 7859 * cpu_exec_realizefn, clear. 7860 */ 7861 cpu->guest_phys_bits = 0; 7862 } 7863 7864 if (cpu->ucode_rev == 0) { 7865 /* 7866 * The default is the same as KVM's. Note that this check 7867 * needs to happen after the evenual setting of ucode_rev in 7868 * accel-specific code in cpu_exec_realizefn. 7869 */ 7870 if (IS_AMD_CPU(env)) { 7871 cpu->ucode_rev = 0x01000065; 7872 } else { 7873 cpu->ucode_rev = 0x100000000ULL; 7874 } 7875 } 7876 7877 /* 7878 * mwait extended info: needed for Core compatibility 7879 * We always wake on interrupt even if host does not have the capability. 7880 * 7881 * requires the accel-specific code in cpu_exec_realizefn to 7882 * have already acquired the CPUID data into cpu->mwait. 7883 */ 7884 cpu->mwait.ecx |= CPUID_MWAIT_EMX | CPUID_MWAIT_IBE; 7885 7886 /* 7887 * Most Intel and certain AMD CPUs support hyperthreading. Even though QEMU 7888 * fixes this issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX 7889 * based on inputs (sockets,cores,threads), it is still better to give 7890 * users a warning. 7891 */ 7892 if (IS_AMD_CPU(env) && 7893 !(env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) && 7894 env->topo_info.threads_per_core > 1) { 7895 warn_report_once("This family of AMD CPU doesn't support " 7896 "hyperthreading(%d). Please configure -smp " 7897 "options properly or try enabling topoext " 7898 "feature.", env->topo_info.threads_per_core); 7899 } 7900 7901 /* For 64bit systems think about the number of physical bits to present. 7902 * ideally this should be the same as the host; anything other than matching 7903 * the host can cause incorrect guest behaviour. 7904 * QEMU used to pick the magic value of 40 bits that corresponds to 7905 * consumer AMD devices but nothing else. 7906 * 7907 * Note that this code assumes features expansion has already been done 7908 * (as it checks for CPUID_EXT2_LM), and also assumes that potential 7909 * phys_bits adjustments to match the host have been already done in 7910 * accel-specific code in cpu_exec_realizefn. 7911 */ 7912 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 7913 if (cpu->phys_bits && 7914 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS || 7915 cpu->phys_bits < 32)) { 7916 error_setg(errp, "phys-bits should be between 32 and %u " 7917 " (but is %u)", 7918 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits); 7919 return; 7920 } 7921 /* 7922 * 0 means it was not explicitly set by the user (or by machine 7923 * compat_props or by the host code in host-cpu.c). 7924 * In this case, the default is the value used by TCG (40). 7925 */ 7926 if (cpu->phys_bits == 0) { 7927 cpu->phys_bits = TCG_PHYS_ADDR_BITS; 7928 } 7929 if (cpu->guest_phys_bits && 7930 (cpu->guest_phys_bits > cpu->phys_bits || 7931 cpu->guest_phys_bits < 32)) { 7932 error_setg(errp, "guest-phys-bits should be between 32 and %u " 7933 " (but is %u)", 7934 cpu->phys_bits, cpu->guest_phys_bits); 7935 return; 7936 } 7937 } else { 7938 /* For 32 bit systems don't use the user set value, but keep 7939 * phys_bits consistent with what we tell the guest. 7940 */ 7941 if (cpu->phys_bits != 0) { 7942 error_setg(errp, "phys-bits is not user-configurable in 32 bit"); 7943 return; 7944 } 7945 if (cpu->guest_phys_bits != 0) { 7946 error_setg(errp, "guest-phys-bits is not user-configurable in 32 bit"); 7947 return; 7948 } 7949 7950 if (env->features[FEAT_1_EDX] & (CPUID_PSE36 | CPUID_PAE)) { 7951 cpu->phys_bits = 36; 7952 } else { 7953 cpu->phys_bits = 32; 7954 } 7955 } 7956 7957 /* Cache information initialization */ 7958 if (!cpu->legacy_cache) { 7959 const CPUCaches *cache_info = 7960 x86_cpu_get_versioned_cache_info(cpu, xcc->model); 7961 7962 if (!xcc->model || !cache_info) { 7963 g_autofree char *name = x86_cpu_class_get_model_name(xcc); 7964 error_setg(errp, 7965 "CPU model '%s' doesn't support legacy-cache=off", name); 7966 return; 7967 } 7968 env->cache_info_cpuid2 = env->cache_info_cpuid4 = env->cache_info_amd = 7969 *cache_info; 7970 } else { 7971 /* Build legacy cache information */ 7972 env->cache_info_cpuid2.l1d_cache = &legacy_l1d_cache; 7973 env->cache_info_cpuid2.l1i_cache = &legacy_l1i_cache; 7974 env->cache_info_cpuid2.l2_cache = &legacy_l2_cache_cpuid2; 7975 env->cache_info_cpuid2.l3_cache = &legacy_l3_cache; 7976 7977 env->cache_info_cpuid4.l1d_cache = &legacy_l1d_cache; 7978 env->cache_info_cpuid4.l1i_cache = &legacy_l1i_cache; 7979 env->cache_info_cpuid4.l2_cache = &legacy_l2_cache; 7980 env->cache_info_cpuid4.l3_cache = &legacy_l3_cache; 7981 7982 env->cache_info_amd.l1d_cache = &legacy_l1d_cache_amd; 7983 env->cache_info_amd.l1i_cache = &legacy_l1i_cache_amd; 7984 env->cache_info_amd.l2_cache = &legacy_l2_cache_amd; 7985 env->cache_info_amd.l3_cache = &legacy_l3_cache; 7986 } 7987 7988 #ifndef CONFIG_USER_ONLY 7989 MachineState *ms = MACHINE(qdev_get_machine()); 7990 qemu_register_reset(x86_cpu_machine_reset_cb, cpu); 7991 7992 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || ms->smp.cpus > 1) { 7993 x86_cpu_apic_create(cpu, &local_err); 7994 if (local_err != NULL) { 7995 goto out; 7996 } 7997 } 7998 #endif 7999 8000 mce_init(cpu); 8001 8002 x86_cpu_gdb_init(cs); 8003 qemu_init_vcpu(cs); 8004 8005 #ifndef CONFIG_USER_ONLY 8006 x86_cpu_apic_realize(cpu, &local_err); 8007 if (local_err != NULL) { 8008 goto out; 8009 } 8010 #endif /* !CONFIG_USER_ONLY */ 8011 cpu_reset(cs); 8012 8013 xcc->parent_realize(dev, &local_err); 8014 8015 out: 8016 if (local_err != NULL) { 8017 error_propagate(errp, local_err); 8018 return; 8019 } 8020 } 8021 8022 static void x86_cpu_unrealizefn(DeviceState *dev) 8023 { 8024 X86CPU *cpu = X86_CPU(dev); 8025 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev); 8026 8027 #ifndef CONFIG_USER_ONLY 8028 cpu_remove_sync(CPU(dev)); 8029 qemu_unregister_reset(x86_cpu_machine_reset_cb, dev); 8030 #endif 8031 8032 if (cpu->apic_state) { 8033 object_unparent(OBJECT(cpu->apic_state)); 8034 cpu->apic_state = NULL; 8035 } 8036 8037 xcc->parent_unrealize(dev); 8038 } 8039 8040 typedef struct BitProperty { 8041 FeatureWord w; 8042 uint64_t mask; 8043 } BitProperty; 8044 8045 static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name, 8046 void *opaque, Error **errp) 8047 { 8048 X86CPU *cpu = X86_CPU(obj); 8049 BitProperty *fp = opaque; 8050 uint64_t f = cpu->env.features[fp->w]; 8051 bool value = (f & fp->mask) == fp->mask; 8052 visit_type_bool(v, name, &value, errp); 8053 } 8054 8055 static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name, 8056 void *opaque, Error **errp) 8057 { 8058 DeviceState *dev = DEVICE(obj); 8059 X86CPU *cpu = X86_CPU(obj); 8060 BitProperty *fp = opaque; 8061 bool value; 8062 8063 if (dev->realized) { 8064 qdev_prop_set_after_realize(dev, name, errp); 8065 return; 8066 } 8067 8068 if (!visit_type_bool(v, name, &value, errp)) { 8069 return; 8070 } 8071 8072 if (value) { 8073 cpu->env.features[fp->w] |= fp->mask; 8074 } else { 8075 cpu->env.features[fp->w] &= ~fp->mask; 8076 } 8077 cpu->env.user_features[fp->w] |= fp->mask; 8078 } 8079 8080 /* Register a boolean property to get/set a single bit in a uint32_t field. 8081 * 8082 * The same property name can be registered multiple times to make it affect 8083 * multiple bits in the same FeatureWord. In that case, the getter will return 8084 * true only if all bits are set. 8085 */ 8086 static void x86_cpu_register_bit_prop(X86CPUClass *xcc, 8087 const char *prop_name, 8088 FeatureWord w, 8089 int bitnr) 8090 { 8091 ObjectClass *oc = OBJECT_CLASS(xcc); 8092 BitProperty *fp; 8093 ObjectProperty *op; 8094 uint64_t mask = (1ULL << bitnr); 8095 8096 op = object_class_property_find(oc, prop_name); 8097 if (op) { 8098 fp = op->opaque; 8099 assert(fp->w == w); 8100 fp->mask |= mask; 8101 } else { 8102 fp = g_new0(BitProperty, 1); 8103 fp->w = w; 8104 fp->mask = mask; 8105 object_class_property_add(oc, prop_name, "bool", 8106 x86_cpu_get_bit_prop, 8107 x86_cpu_set_bit_prop, 8108 NULL, fp); 8109 } 8110 } 8111 8112 static void x86_cpu_register_feature_bit_props(X86CPUClass *xcc, 8113 FeatureWord w, 8114 int bitnr) 8115 { 8116 FeatureWordInfo *fi = &feature_word_info[w]; 8117 const char *name = fi->feat_names[bitnr]; 8118 8119 if (!name) { 8120 return; 8121 } 8122 8123 /* Property names should use "-" instead of "_". 8124 * Old names containing underscores are registered as aliases 8125 * using object_property_add_alias() 8126 */ 8127 assert(!strchr(name, '_')); 8128 /* aliases don't use "|" delimiters anymore, they are registered 8129 * manually using object_property_add_alias() */ 8130 assert(!strchr(name, '|')); 8131 x86_cpu_register_bit_prop(xcc, name, w, bitnr); 8132 } 8133 8134 static void x86_cpu_post_initfn(Object *obj) 8135 { 8136 static bool first = true; 8137 uint64_t supported_xcr0; 8138 int i; 8139 8140 if (first) { 8141 first = false; 8142 8143 supported_xcr0 = 8144 ((uint64_t) x86_cpu_get_supported_feature_word(NULL, FEAT_XSAVE_XCR0_HI) << 32) | 8145 x86_cpu_get_supported_feature_word(NULL, FEAT_XSAVE_XCR0_LO); 8146 8147 for (i = XSTATE_SSE_BIT + 1; i < XSAVE_STATE_AREA_COUNT; i++) { 8148 ExtSaveArea *esa = &x86_ext_save_areas[i]; 8149 8150 if (!(supported_xcr0 & (1 << i))) { 8151 esa->size = 0; 8152 } 8153 } 8154 } 8155 8156 accel_cpu_instance_init(CPU(obj)); 8157 } 8158 8159 static void x86_cpu_init_default_topo(X86CPU *cpu) 8160 { 8161 CPUX86State *env = &cpu->env; 8162 8163 env->topo_info = (X86CPUTopoInfo) {1, 1, 1, 1}; 8164 8165 /* thread, core and socket levels are set by default. */ 8166 set_bit(CPU_TOPOLOGY_LEVEL_THREAD, env->avail_cpu_topo); 8167 set_bit(CPU_TOPOLOGY_LEVEL_CORE, env->avail_cpu_topo); 8168 set_bit(CPU_TOPOLOGY_LEVEL_SOCKET, env->avail_cpu_topo); 8169 } 8170 8171 static void x86_cpu_initfn(Object *obj) 8172 { 8173 X86CPU *cpu = X86_CPU(obj); 8174 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj); 8175 CPUX86State *env = &cpu->env; 8176 8177 x86_cpu_init_default_topo(cpu); 8178 8179 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo", 8180 x86_cpu_get_feature_words, 8181 NULL, NULL, (void *)env->features); 8182 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo", 8183 x86_cpu_get_feature_words, 8184 NULL, NULL, (void *)cpu->filtered_features); 8185 8186 object_property_add_alias(obj, "sse3", obj, "pni"); 8187 object_property_add_alias(obj, "pclmuldq", obj, "pclmulqdq"); 8188 object_property_add_alias(obj, "sse4-1", obj, "sse4.1"); 8189 object_property_add_alias(obj, "sse4-2", obj, "sse4.2"); 8190 object_property_add_alias(obj, "xd", obj, "nx"); 8191 object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt"); 8192 object_property_add_alias(obj, "i64", obj, "lm"); 8193 8194 object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl"); 8195 object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust"); 8196 object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt"); 8197 object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm"); 8198 object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy"); 8199 object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr"); 8200 object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core"); 8201 object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb"); 8202 object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay"); 8203 object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu"); 8204 object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf"); 8205 object_property_add_alias(obj, "kvm_asyncpf_int", obj, "kvm-asyncpf-int"); 8206 object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time"); 8207 object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi"); 8208 object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt"); 8209 object_property_add_alias(obj, "kvm_poll_control", obj, "kvm-poll-control"); 8210 object_property_add_alias(obj, "svm_lock", obj, "svm-lock"); 8211 object_property_add_alias(obj, "nrip_save", obj, "nrip-save"); 8212 object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale"); 8213 object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean"); 8214 object_property_add_alias(obj, "pause_filter", obj, "pause-filter"); 8215 object_property_add_alias(obj, "sse4_1", obj, "sse4.1"); 8216 object_property_add_alias(obj, "sse4_2", obj, "sse4.2"); 8217 8218 object_property_add_alias(obj, "hv-apicv", obj, "hv-avic"); 8219 cpu->lbr_fmt = ~PERF_CAP_LBR_FMT; 8220 object_property_add_alias(obj, "lbr_fmt", obj, "lbr-fmt"); 8221 8222 if (xcc->model) { 8223 x86_cpu_load_model(cpu, xcc->model); 8224 } 8225 } 8226 8227 static int64_t x86_cpu_get_arch_id(CPUState *cs) 8228 { 8229 X86CPU *cpu = X86_CPU(cs); 8230 8231 return cpu->apic_id; 8232 } 8233 8234 #if !defined(CONFIG_USER_ONLY) 8235 static bool x86_cpu_get_paging_enabled(const CPUState *cs) 8236 { 8237 X86CPU *cpu = X86_CPU(cs); 8238 8239 return cpu->env.cr[0] & CR0_PG_MASK; 8240 } 8241 #endif /* !CONFIG_USER_ONLY */ 8242 8243 static void x86_cpu_set_pc(CPUState *cs, vaddr value) 8244 { 8245 X86CPU *cpu = X86_CPU(cs); 8246 8247 cpu->env.eip = value; 8248 } 8249 8250 static vaddr x86_cpu_get_pc(CPUState *cs) 8251 { 8252 X86CPU *cpu = X86_CPU(cs); 8253 8254 /* Match cpu_get_tb_cpu_state. */ 8255 return cpu->env.eip + cpu->env.segs[R_CS].base; 8256 } 8257 8258 int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request) 8259 { 8260 X86CPU *cpu = X86_CPU(cs); 8261 CPUX86State *env = &cpu->env; 8262 8263 #if !defined(CONFIG_USER_ONLY) 8264 if (interrupt_request & CPU_INTERRUPT_POLL) { 8265 return CPU_INTERRUPT_POLL; 8266 } 8267 #endif 8268 if (interrupt_request & CPU_INTERRUPT_SIPI) { 8269 return CPU_INTERRUPT_SIPI; 8270 } 8271 8272 if (env->hflags2 & HF2_GIF_MASK) { 8273 if ((interrupt_request & CPU_INTERRUPT_SMI) && 8274 !(env->hflags & HF_SMM_MASK)) { 8275 return CPU_INTERRUPT_SMI; 8276 } else if ((interrupt_request & CPU_INTERRUPT_NMI) && 8277 !(env->hflags2 & HF2_NMI_MASK)) { 8278 return CPU_INTERRUPT_NMI; 8279 } else if (interrupt_request & CPU_INTERRUPT_MCE) { 8280 return CPU_INTERRUPT_MCE; 8281 } else if ((interrupt_request & CPU_INTERRUPT_HARD) && 8282 (((env->hflags2 & HF2_VINTR_MASK) && 8283 (env->hflags2 & HF2_HIF_MASK)) || 8284 (!(env->hflags2 & HF2_VINTR_MASK) && 8285 (env->eflags & IF_MASK && 8286 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) { 8287 return CPU_INTERRUPT_HARD; 8288 #if !defined(CONFIG_USER_ONLY) 8289 } else if (env->hflags2 & HF2_VGIF_MASK) { 8290 if((interrupt_request & CPU_INTERRUPT_VIRQ) && 8291 (env->eflags & IF_MASK) && 8292 !(env->hflags & HF_INHIBIT_IRQ_MASK)) { 8293 return CPU_INTERRUPT_VIRQ; 8294 } 8295 #endif 8296 } 8297 } 8298 8299 return 0; 8300 } 8301 8302 static bool x86_cpu_has_work(CPUState *cs) 8303 { 8304 return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0; 8305 } 8306 8307 int x86_mmu_index_pl(CPUX86State *env, unsigned pl) 8308 { 8309 int mmu_index_32 = (env->hflags & HF_CS64_MASK) ? 0 : 1; 8310 int mmu_index_base = 8311 pl == 3 ? MMU_USER64_IDX : 8312 !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP64_IDX : 8313 (env->eflags & AC_MASK) ? MMU_KNOSMAP64_IDX : MMU_KSMAP64_IDX; 8314 8315 return mmu_index_base + mmu_index_32; 8316 } 8317 8318 static int x86_cpu_mmu_index(CPUState *cs, bool ifetch) 8319 { 8320 CPUX86State *env = cpu_env(cs); 8321 return x86_mmu_index_pl(env, env->hflags & HF_CPL_MASK); 8322 } 8323 8324 static int x86_mmu_index_kernel_pl(CPUX86State *env, unsigned pl) 8325 { 8326 int mmu_index_32 = (env->hflags & HF_LMA_MASK) ? 0 : 1; 8327 int mmu_index_base = 8328 !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP64_IDX : 8329 (pl < 3 && (env->eflags & AC_MASK) 8330 ? MMU_KNOSMAP64_IDX : MMU_KSMAP64_IDX); 8331 8332 return mmu_index_base + mmu_index_32; 8333 } 8334 8335 int cpu_mmu_index_kernel(CPUX86State *env) 8336 { 8337 return x86_mmu_index_kernel_pl(env, env->hflags & HF_CPL_MASK); 8338 } 8339 8340 static void x86_disas_set_info(CPUState *cs, disassemble_info *info) 8341 { 8342 X86CPU *cpu = X86_CPU(cs); 8343 CPUX86State *env = &cpu->env; 8344 8345 info->mach = (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64 8346 : env->hflags & HF_CS32_MASK ? bfd_mach_i386_i386 8347 : bfd_mach_i386_i8086); 8348 8349 info->cap_arch = CS_ARCH_X86; 8350 info->cap_mode = (env->hflags & HF_CS64_MASK ? CS_MODE_64 8351 : env->hflags & HF_CS32_MASK ? CS_MODE_32 8352 : CS_MODE_16); 8353 info->cap_insn_unit = 1; 8354 info->cap_insn_split = 8; 8355 } 8356 8357 void x86_update_hflags(CPUX86State *env) 8358 { 8359 uint32_t hflags; 8360 #define HFLAG_COPY_MASK \ 8361 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \ 8362 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \ 8363 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \ 8364 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK) 8365 8366 hflags = env->hflags & HFLAG_COPY_MASK; 8367 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK; 8368 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT); 8369 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) & 8370 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK); 8371 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK)); 8372 8373 if (env->cr[4] & CR4_OSFXSR_MASK) { 8374 hflags |= HF_OSFXSR_MASK; 8375 } 8376 8377 if (env->efer & MSR_EFER_LMA) { 8378 hflags |= HF_LMA_MASK; 8379 } 8380 8381 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) { 8382 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; 8383 } else { 8384 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >> 8385 (DESC_B_SHIFT - HF_CS32_SHIFT); 8386 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >> 8387 (DESC_B_SHIFT - HF_SS32_SHIFT); 8388 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) || 8389 !(hflags & HF_CS32_MASK)) { 8390 hflags |= HF_ADDSEG_MASK; 8391 } else { 8392 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base | 8393 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT; 8394 } 8395 } 8396 env->hflags = hflags; 8397 } 8398 8399 static const Property x86_cpu_properties[] = { 8400 #ifdef CONFIG_USER_ONLY 8401 /* apic_id = 0 by default for *-user, see commit 9886e834 */ 8402 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0), 8403 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0), 8404 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0), 8405 DEFINE_PROP_INT32("module-id", X86CPU, module_id, 0), 8406 DEFINE_PROP_INT32("die-id", X86CPU, die_id, 0), 8407 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0), 8408 #else 8409 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID), 8410 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1), 8411 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1), 8412 DEFINE_PROP_INT32("module-id", X86CPU, module_id, -1), 8413 DEFINE_PROP_INT32("die-id", X86CPU, die_id, -1), 8414 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1), 8415 #endif 8416 DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID), 8417 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false), 8418 DEFINE_PROP_UINT64_CHECKMASK("lbr-fmt", X86CPU, lbr_fmt, PERF_CAP_LBR_FMT), 8419 8420 DEFINE_PROP_UINT32("hv-spinlocks", X86CPU, hyperv_spinlock_attempts, 8421 HYPERV_SPINLOCK_NEVER_NOTIFY), 8422 DEFINE_PROP_BIT64("hv-relaxed", X86CPU, hyperv_features, 8423 HYPERV_FEAT_RELAXED, 0), 8424 DEFINE_PROP_BIT64("hv-vapic", X86CPU, hyperv_features, 8425 HYPERV_FEAT_VAPIC, 0), 8426 DEFINE_PROP_BIT64("hv-time", X86CPU, hyperv_features, 8427 HYPERV_FEAT_TIME, 0), 8428 DEFINE_PROP_BIT64("hv-crash", X86CPU, hyperv_features, 8429 HYPERV_FEAT_CRASH, 0), 8430 DEFINE_PROP_BIT64("hv-reset", X86CPU, hyperv_features, 8431 HYPERV_FEAT_RESET, 0), 8432 DEFINE_PROP_BIT64("hv-vpindex", X86CPU, hyperv_features, 8433 HYPERV_FEAT_VPINDEX, 0), 8434 DEFINE_PROP_BIT64("hv-runtime", X86CPU, hyperv_features, 8435 HYPERV_FEAT_RUNTIME, 0), 8436 DEFINE_PROP_BIT64("hv-synic", X86CPU, hyperv_features, 8437 HYPERV_FEAT_SYNIC, 0), 8438 DEFINE_PROP_BIT64("hv-stimer", X86CPU, hyperv_features, 8439 HYPERV_FEAT_STIMER, 0), 8440 DEFINE_PROP_BIT64("hv-frequencies", X86CPU, hyperv_features, 8441 HYPERV_FEAT_FREQUENCIES, 0), 8442 DEFINE_PROP_BIT64("hv-reenlightenment", X86CPU, hyperv_features, 8443 HYPERV_FEAT_REENLIGHTENMENT, 0), 8444 DEFINE_PROP_BIT64("hv-tlbflush", X86CPU, hyperv_features, 8445 HYPERV_FEAT_TLBFLUSH, 0), 8446 DEFINE_PROP_BIT64("hv-evmcs", X86CPU, hyperv_features, 8447 HYPERV_FEAT_EVMCS, 0), 8448 DEFINE_PROP_BIT64("hv-ipi", X86CPU, hyperv_features, 8449 HYPERV_FEAT_IPI, 0), 8450 DEFINE_PROP_BIT64("hv-stimer-direct", X86CPU, hyperv_features, 8451 HYPERV_FEAT_STIMER_DIRECT, 0), 8452 DEFINE_PROP_BIT64("hv-avic", X86CPU, hyperv_features, 8453 HYPERV_FEAT_AVIC, 0), 8454 DEFINE_PROP_BIT64("hv-emsr-bitmap", X86CPU, hyperv_features, 8455 HYPERV_FEAT_MSR_BITMAP, 0), 8456 DEFINE_PROP_BIT64("hv-xmm-input", X86CPU, hyperv_features, 8457 HYPERV_FEAT_XMM_INPUT, 0), 8458 DEFINE_PROP_BIT64("hv-tlbflush-ext", X86CPU, hyperv_features, 8459 HYPERV_FEAT_TLBFLUSH_EXT, 0), 8460 DEFINE_PROP_BIT64("hv-tlbflush-direct", X86CPU, hyperv_features, 8461 HYPERV_FEAT_TLBFLUSH_DIRECT, 0), 8462 DEFINE_PROP_ON_OFF_AUTO("hv-no-nonarch-coresharing", X86CPU, 8463 hyperv_no_nonarch_cs, ON_OFF_AUTO_OFF), 8464 #ifdef CONFIG_SYNDBG 8465 DEFINE_PROP_BIT64("hv-syndbg", X86CPU, hyperv_features, 8466 HYPERV_FEAT_SYNDBG, 0), 8467 #endif 8468 DEFINE_PROP_BOOL("hv-passthrough", X86CPU, hyperv_passthrough, false), 8469 DEFINE_PROP_BOOL("hv-enforce-cpuid", X86CPU, hyperv_enforce_cpuid, false), 8470 8471 /* WS2008R2 identify by default */ 8472 DEFINE_PROP_UINT32("hv-version-id-build", X86CPU, hyperv_ver_id_build, 8473 0x3839), 8474 DEFINE_PROP_UINT16("hv-version-id-major", X86CPU, hyperv_ver_id_major, 8475 0x000A), 8476 DEFINE_PROP_UINT16("hv-version-id-minor", X86CPU, hyperv_ver_id_minor, 8477 0x0000), 8478 DEFINE_PROP_UINT32("hv-version-id-spack", X86CPU, hyperv_ver_id_sp, 0), 8479 DEFINE_PROP_UINT8("hv-version-id-sbranch", X86CPU, hyperv_ver_id_sb, 0), 8480 DEFINE_PROP_UINT32("hv-version-id-snumber", X86CPU, hyperv_ver_id_sn, 0), 8481 8482 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true), 8483 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false), 8484 DEFINE_PROP_BOOL("x-force-features", X86CPU, force_features, false), 8485 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true), 8486 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0), 8487 DEFINE_PROP_UINT32("guest-phys-bits", X86CPU, guest_phys_bits, -1), 8488 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false), 8489 DEFINE_PROP_UINT8("host-phys-bits-limit", X86CPU, host_phys_bits_limit, 0), 8490 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true), 8491 DEFINE_PROP_UINT32("level-func7", X86CPU, env.cpuid_level_func7, 8492 UINT32_MAX), 8493 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX), 8494 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX), 8495 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX), 8496 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0), 8497 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0), 8498 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0), 8499 DEFINE_PROP_UINT8("avx10-version", X86CPU, env.avx10_version, 0), 8500 DEFINE_PROP_UINT64("ucode-rev", X86CPU, ucode_rev, 0), 8501 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true), 8502 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor), 8503 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true), 8504 DEFINE_PROP_BOOL("x-vendor-cpuid-only", X86CPU, vendor_cpuid_only, true), 8505 DEFINE_PROP_BOOL("x-amd-topoext-features-only", X86CPU, amd_topoext_features_only, true), 8506 DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false), 8507 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true), 8508 DEFINE_PROP_BOOL("kvm-pv-enforce-cpuid", X86CPU, kvm_pv_enforce_cpuid, 8509 false), 8510 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true), 8511 DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true), 8512 DEFINE_PROP_BOOL("x-migrate-smi-count", X86CPU, migrate_smi_count, 8513 true), 8514 /* 8515 * lecacy_cache defaults to true unless the CPU model provides its 8516 * own cache information (see x86_cpu_load_def()). 8517 */ 8518 DEFINE_PROP_BOOL("legacy-cache", X86CPU, legacy_cache, true), 8519 DEFINE_PROP_BOOL("legacy-multi-node", X86CPU, legacy_multi_node, false), 8520 DEFINE_PROP_BOOL("xen-vapic", X86CPU, xen_vapic, false), 8521 8522 /* 8523 * From "Requirements for Implementing the Microsoft 8524 * Hypervisor Interface": 8525 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs 8526 * 8527 * "Starting with Windows Server 2012 and Windows 8, if 8528 * CPUID.40000005.EAX contains a value of -1, Windows assumes that 8529 * the hypervisor imposes no specific limit to the number of VPs. 8530 * In this case, Windows Server 2012 guest VMs may use more than 8531 * 64 VPs, up to the maximum supported number of processors applicable 8532 * to the specific Windows version being used." 8533 */ 8534 DEFINE_PROP_INT32("x-hv-max-vps", X86CPU, hv_max_vps, -1), 8535 DEFINE_PROP_BOOL("x-hv-synic-kvm-only", X86CPU, hyperv_synic_kvm_only, 8536 false), 8537 DEFINE_PROP_BOOL("x-intel-pt-auto-level", X86CPU, intel_pt_auto_level, 8538 true), 8539 DEFINE_PROP_BOOL("x-l1-cache-per-thread", X86CPU, l1_cache_per_core, true), 8540 }; 8541 8542 #ifndef CONFIG_USER_ONLY 8543 #include "hw/core/sysemu-cpu-ops.h" 8544 8545 static const struct SysemuCPUOps i386_sysemu_ops = { 8546 .get_memory_mapping = x86_cpu_get_memory_mapping, 8547 .get_paging_enabled = x86_cpu_get_paging_enabled, 8548 .get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug, 8549 .asidx_from_attrs = x86_asidx_from_attrs, 8550 .get_crash_info = x86_cpu_get_crash_info, 8551 .write_elf32_note = x86_cpu_write_elf32_note, 8552 .write_elf64_note = x86_cpu_write_elf64_note, 8553 .write_elf32_qemunote = x86_cpu_write_elf32_qemunote, 8554 .write_elf64_qemunote = x86_cpu_write_elf64_qemunote, 8555 .legacy_vmsd = &vmstate_x86_cpu, 8556 }; 8557 #endif 8558 8559 static void x86_cpu_common_class_init(ObjectClass *oc, void *data) 8560 { 8561 X86CPUClass *xcc = X86_CPU_CLASS(oc); 8562 CPUClass *cc = CPU_CLASS(oc); 8563 DeviceClass *dc = DEVICE_CLASS(oc); 8564 ResettableClass *rc = RESETTABLE_CLASS(oc); 8565 FeatureWord w; 8566 8567 device_class_set_parent_realize(dc, x86_cpu_realizefn, 8568 &xcc->parent_realize); 8569 device_class_set_parent_unrealize(dc, x86_cpu_unrealizefn, 8570 &xcc->parent_unrealize); 8571 device_class_set_props(dc, x86_cpu_properties); 8572 8573 resettable_class_set_parent_phases(rc, NULL, x86_cpu_reset_hold, NULL, 8574 &xcc->parent_phases); 8575 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP; 8576 8577 cc->class_by_name = x86_cpu_class_by_name; 8578 cc->parse_features = x86_cpu_parse_featurestr; 8579 cc->has_work = x86_cpu_has_work; 8580 cc->mmu_index = x86_cpu_mmu_index; 8581 cc->dump_state = x86_cpu_dump_state; 8582 cc->set_pc = x86_cpu_set_pc; 8583 cc->get_pc = x86_cpu_get_pc; 8584 cc->gdb_read_register = x86_cpu_gdb_read_register; 8585 cc->gdb_write_register = x86_cpu_gdb_write_register; 8586 cc->get_arch_id = x86_cpu_get_arch_id; 8587 8588 #ifndef CONFIG_USER_ONLY 8589 cc->sysemu_ops = &i386_sysemu_ops; 8590 #endif /* !CONFIG_USER_ONLY */ 8591 8592 cc->gdb_arch_name = x86_gdb_arch_name; 8593 #ifdef TARGET_X86_64 8594 cc->gdb_core_xml_file = "i386-64bit.xml"; 8595 #else 8596 cc->gdb_core_xml_file = "i386-32bit.xml"; 8597 #endif 8598 cc->disas_set_info = x86_disas_set_info; 8599 8600 dc->user_creatable = true; 8601 8602 object_class_property_add(oc, "family", "int", 8603 x86_cpuid_version_get_family, 8604 x86_cpuid_version_set_family, NULL, NULL); 8605 object_class_property_add(oc, "model", "int", 8606 x86_cpuid_version_get_model, 8607 x86_cpuid_version_set_model, NULL, NULL); 8608 object_class_property_add(oc, "stepping", "int", 8609 x86_cpuid_version_get_stepping, 8610 x86_cpuid_version_set_stepping, NULL, NULL); 8611 object_class_property_add_str(oc, "vendor", 8612 x86_cpuid_get_vendor, 8613 x86_cpuid_set_vendor); 8614 object_class_property_add_str(oc, "model-id", 8615 x86_cpuid_get_model_id, 8616 x86_cpuid_set_model_id); 8617 object_class_property_add(oc, "tsc-frequency", "int", 8618 x86_cpuid_get_tsc_freq, 8619 x86_cpuid_set_tsc_freq, NULL, NULL); 8620 /* 8621 * The "unavailable-features" property has the same semantics as 8622 * CpuDefinitionInfo.unavailable-features on the "query-cpu-definitions" 8623 * QMP command: they list the features that would have prevented the 8624 * CPU from running if the "enforce" flag was set. 8625 */ 8626 object_class_property_add(oc, "unavailable-features", "strList", 8627 x86_cpu_get_unavailable_features, 8628 NULL, NULL, NULL); 8629 8630 #if !defined(CONFIG_USER_ONLY) 8631 object_class_property_add(oc, "crash-information", "GuestPanicInformation", 8632 x86_cpu_get_crash_info_qom, NULL, NULL, NULL); 8633 #endif 8634 8635 for (w = 0; w < FEATURE_WORDS; w++) { 8636 int bitnr; 8637 for (bitnr = 0; bitnr < 64; bitnr++) { 8638 x86_cpu_register_feature_bit_props(xcc, w, bitnr); 8639 } 8640 } 8641 } 8642 8643 static const TypeInfo x86_cpu_type_info = { 8644 .name = TYPE_X86_CPU, 8645 .parent = TYPE_CPU, 8646 .instance_size = sizeof(X86CPU), 8647 .instance_align = __alignof(X86CPU), 8648 .instance_init = x86_cpu_initfn, 8649 .instance_post_init = x86_cpu_post_initfn, 8650 8651 .abstract = true, 8652 .class_size = sizeof(X86CPUClass), 8653 .class_init = x86_cpu_common_class_init, 8654 }; 8655 8656 /* "base" CPU model, used by query-cpu-model-expansion */ 8657 static void x86_cpu_base_class_init(ObjectClass *oc, void *data) 8658 { 8659 X86CPUClass *xcc = X86_CPU_CLASS(oc); 8660 8661 xcc->static_model = true; 8662 xcc->migration_safe = true; 8663 xcc->model_description = "base CPU model type with no features enabled"; 8664 xcc->ordering = 8; 8665 } 8666 8667 static const TypeInfo x86_base_cpu_type_info = { 8668 .name = X86_CPU_TYPE_NAME("base"), 8669 .parent = TYPE_X86_CPU, 8670 .class_init = x86_cpu_base_class_init, 8671 }; 8672 8673 static void x86_cpu_register_types(void) 8674 { 8675 int i; 8676 8677 type_register_static(&x86_cpu_type_info); 8678 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) { 8679 x86_register_cpudef_types(&builtin_x86_defs[i]); 8680 } 8681 type_register_static(&max_x86_cpu_type_info); 8682 type_register_static(&x86_base_cpu_type_info); 8683 } 8684 8685 type_init(x86_cpu_register_types) 8686