1 /* 2 * i386 CPUID, CPU class, definitions, models 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/units.h" 22 #include "qemu/cutils.h" 23 #include "qemu/qemu-print.h" 24 #include "qemu/hw-version.h" 25 #include "cpu.h" 26 #include "tcg/helper-tcg.h" 27 #include "sysemu/reset.h" 28 #include "sysemu/hvf.h" 29 #include "hvf/hvf-i386.h" 30 #include "kvm/kvm_i386.h" 31 #include "sev.h" 32 #include "qapi/error.h" 33 #include "qemu/error-report.h" 34 #include "qapi/qapi-visit-machine.h" 35 #include "qapi/qmp/qerror.h" 36 #include "standard-headers/asm-x86/kvm_para.h" 37 #include "hw/qdev-properties.h" 38 #include "hw/i386/topology.h" 39 #ifndef CONFIG_USER_ONLY 40 #include "qapi/qapi-commands-machine-target.h" 41 #include "exec/address-spaces.h" 42 #include "hw/boards.h" 43 #include "hw/i386/sgx-epc.h" 44 #endif 45 46 #include "disas/capstone.h" 47 #include "cpu-internal.h" 48 49 static void x86_cpu_realizefn(DeviceState *dev, Error **errp); 50 51 /* Helpers for building CPUID[2] descriptors: */ 52 53 struct CPUID2CacheDescriptorInfo { 54 enum CacheType type; 55 int level; 56 int size; 57 int line_size; 58 int associativity; 59 }; 60 61 /* 62 * Known CPUID 2 cache descriptors. 63 * From Intel SDM Volume 2A, CPUID instruction 64 */ 65 struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = { 66 [0x06] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 8 * KiB, 67 .associativity = 4, .line_size = 32, }, 68 [0x08] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 16 * KiB, 69 .associativity = 4, .line_size = 32, }, 70 [0x09] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB, 71 .associativity = 4, .line_size = 64, }, 72 [0x0A] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB, 73 .associativity = 2, .line_size = 32, }, 74 [0x0C] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 75 .associativity = 4, .line_size = 32, }, 76 [0x0D] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 77 .associativity = 4, .line_size = 64, }, 78 [0x0E] = { .level = 1, .type = DATA_CACHE, .size = 24 * KiB, 79 .associativity = 6, .line_size = 64, }, 80 [0x1D] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB, 81 .associativity = 2, .line_size = 64, }, 82 [0x21] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 83 .associativity = 8, .line_size = 64, }, 84 /* lines per sector is not supported cpuid2_cache_descriptor(), 85 * so descriptors 0x22, 0x23 are not included 86 */ 87 [0x24] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 88 .associativity = 16, .line_size = 64, }, 89 /* lines per sector is not supported cpuid2_cache_descriptor(), 90 * so descriptors 0x25, 0x20 are not included 91 */ 92 [0x2C] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB, 93 .associativity = 8, .line_size = 64, }, 94 [0x30] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB, 95 .associativity = 8, .line_size = 64, }, 96 [0x41] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB, 97 .associativity = 4, .line_size = 32, }, 98 [0x42] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 99 .associativity = 4, .line_size = 32, }, 100 [0x43] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 101 .associativity = 4, .line_size = 32, }, 102 [0x44] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 103 .associativity = 4, .line_size = 32, }, 104 [0x45] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 105 .associativity = 4, .line_size = 32, }, 106 [0x46] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 107 .associativity = 4, .line_size = 64, }, 108 [0x47] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 109 .associativity = 8, .line_size = 64, }, 110 [0x48] = { .level = 2, .type = UNIFIED_CACHE, .size = 3 * MiB, 111 .associativity = 12, .line_size = 64, }, 112 /* Descriptor 0x49 depends on CPU family/model, so it is not included */ 113 [0x4A] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB, 114 .associativity = 12, .line_size = 64, }, 115 [0x4B] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 116 .associativity = 16, .line_size = 64, }, 117 [0x4C] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB, 118 .associativity = 12, .line_size = 64, }, 119 [0x4D] = { .level = 3, .type = UNIFIED_CACHE, .size = 16 * MiB, 120 .associativity = 16, .line_size = 64, }, 121 [0x4E] = { .level = 2, .type = UNIFIED_CACHE, .size = 6 * MiB, 122 .associativity = 24, .line_size = 64, }, 123 [0x60] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 124 .associativity = 8, .line_size = 64, }, 125 [0x66] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB, 126 .associativity = 4, .line_size = 64, }, 127 [0x67] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 128 .associativity = 4, .line_size = 64, }, 129 [0x68] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB, 130 .associativity = 4, .line_size = 64, }, 131 [0x78] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 132 .associativity = 4, .line_size = 64, }, 133 /* lines per sector is not supported cpuid2_cache_descriptor(), 134 * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included. 135 */ 136 [0x7D] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 137 .associativity = 8, .line_size = 64, }, 138 [0x7F] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 139 .associativity = 2, .line_size = 64, }, 140 [0x80] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 141 .associativity = 8, .line_size = 64, }, 142 [0x82] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 143 .associativity = 8, .line_size = 32, }, 144 [0x83] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 145 .associativity = 8, .line_size = 32, }, 146 [0x84] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 147 .associativity = 8, .line_size = 32, }, 148 [0x85] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 149 .associativity = 8, .line_size = 32, }, 150 [0x86] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 151 .associativity = 4, .line_size = 64, }, 152 [0x87] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 153 .associativity = 8, .line_size = 64, }, 154 [0xD0] = { .level = 3, .type = UNIFIED_CACHE, .size = 512 * KiB, 155 .associativity = 4, .line_size = 64, }, 156 [0xD1] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB, 157 .associativity = 4, .line_size = 64, }, 158 [0xD2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 159 .associativity = 4, .line_size = 64, }, 160 [0xD6] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB, 161 .associativity = 8, .line_size = 64, }, 162 [0xD7] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 163 .associativity = 8, .line_size = 64, }, 164 [0xD8] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 165 .associativity = 8, .line_size = 64, }, 166 [0xDC] = { .level = 3, .type = UNIFIED_CACHE, .size = 1.5 * MiB, 167 .associativity = 12, .line_size = 64, }, 168 [0xDD] = { .level = 3, .type = UNIFIED_CACHE, .size = 3 * MiB, 169 .associativity = 12, .line_size = 64, }, 170 [0xDE] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB, 171 .associativity = 12, .line_size = 64, }, 172 [0xE2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 173 .associativity = 16, .line_size = 64, }, 174 [0xE3] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 175 .associativity = 16, .line_size = 64, }, 176 [0xE4] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 177 .associativity = 16, .line_size = 64, }, 178 [0xEA] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB, 179 .associativity = 24, .line_size = 64, }, 180 [0xEB] = { .level = 3, .type = UNIFIED_CACHE, .size = 18 * MiB, 181 .associativity = 24, .line_size = 64, }, 182 [0xEC] = { .level = 3, .type = UNIFIED_CACHE, .size = 24 * MiB, 183 .associativity = 24, .line_size = 64, }, 184 }; 185 186 /* 187 * "CPUID leaf 2 does not report cache descriptor information, 188 * use CPUID leaf 4 to query cache parameters" 189 */ 190 #define CACHE_DESCRIPTOR_UNAVAILABLE 0xFF 191 192 /* 193 * Return a CPUID 2 cache descriptor for a given cache. 194 * If no known descriptor is found, return CACHE_DESCRIPTOR_UNAVAILABLE 195 */ 196 static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache) 197 { 198 int i; 199 200 assert(cache->size > 0); 201 assert(cache->level > 0); 202 assert(cache->line_size > 0); 203 assert(cache->associativity > 0); 204 for (i = 0; i < ARRAY_SIZE(cpuid2_cache_descriptors); i++) { 205 struct CPUID2CacheDescriptorInfo *d = &cpuid2_cache_descriptors[i]; 206 if (d->level == cache->level && d->type == cache->type && 207 d->size == cache->size && d->line_size == cache->line_size && 208 d->associativity == cache->associativity) { 209 return i; 210 } 211 } 212 213 return CACHE_DESCRIPTOR_UNAVAILABLE; 214 } 215 216 /* CPUID Leaf 4 constants: */ 217 218 /* EAX: */ 219 #define CACHE_TYPE_D 1 220 #define CACHE_TYPE_I 2 221 #define CACHE_TYPE_UNIFIED 3 222 223 #define CACHE_LEVEL(l) (l << 5) 224 225 #define CACHE_SELF_INIT_LEVEL (1 << 8) 226 227 /* EDX: */ 228 #define CACHE_NO_INVD_SHARING (1 << 0) 229 #define CACHE_INCLUSIVE (1 << 1) 230 #define CACHE_COMPLEX_IDX (1 << 2) 231 232 /* Encode CacheType for CPUID[4].EAX */ 233 #define CACHE_TYPE(t) (((t) == DATA_CACHE) ? CACHE_TYPE_D : \ 234 ((t) == INSTRUCTION_CACHE) ? CACHE_TYPE_I : \ 235 ((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \ 236 0 /* Invalid value */) 237 238 239 /* Encode cache info for CPUID[4] */ 240 static void encode_cache_cpuid4(CPUCacheInfo *cache, 241 int num_apic_ids, int num_cores, 242 uint32_t *eax, uint32_t *ebx, 243 uint32_t *ecx, uint32_t *edx) 244 { 245 assert(cache->size == cache->line_size * cache->associativity * 246 cache->partitions * cache->sets); 247 248 assert(num_apic_ids > 0); 249 *eax = CACHE_TYPE(cache->type) | 250 CACHE_LEVEL(cache->level) | 251 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) | 252 ((num_cores - 1) << 26) | 253 ((num_apic_ids - 1) << 14); 254 255 assert(cache->line_size > 0); 256 assert(cache->partitions > 0); 257 assert(cache->associativity > 0); 258 /* We don't implement fully-associative caches */ 259 assert(cache->associativity < cache->sets); 260 *ebx = (cache->line_size - 1) | 261 ((cache->partitions - 1) << 12) | 262 ((cache->associativity - 1) << 22); 263 264 assert(cache->sets > 0); 265 *ecx = cache->sets - 1; 266 267 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) | 268 (cache->inclusive ? CACHE_INCLUSIVE : 0) | 269 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); 270 } 271 272 /* Encode cache info for CPUID[0x80000005].ECX or CPUID[0x80000005].EDX */ 273 static uint32_t encode_cache_cpuid80000005(CPUCacheInfo *cache) 274 { 275 assert(cache->size % 1024 == 0); 276 assert(cache->lines_per_tag > 0); 277 assert(cache->associativity > 0); 278 assert(cache->line_size > 0); 279 return ((cache->size / 1024) << 24) | (cache->associativity << 16) | 280 (cache->lines_per_tag << 8) | (cache->line_size); 281 } 282 283 #define ASSOC_FULL 0xFF 284 285 /* AMD associativity encoding used on CPUID Leaf 0x80000006: */ 286 #define AMD_ENC_ASSOC(a) (a <= 1 ? a : \ 287 a == 2 ? 0x2 : \ 288 a == 4 ? 0x4 : \ 289 a == 8 ? 0x6 : \ 290 a == 16 ? 0x8 : \ 291 a == 32 ? 0xA : \ 292 a == 48 ? 0xB : \ 293 a == 64 ? 0xC : \ 294 a == 96 ? 0xD : \ 295 a == 128 ? 0xE : \ 296 a == ASSOC_FULL ? 0xF : \ 297 0 /* invalid value */) 298 299 /* 300 * Encode cache info for CPUID[0x80000006].ECX and CPUID[0x80000006].EDX 301 * @l3 can be NULL. 302 */ 303 static void encode_cache_cpuid80000006(CPUCacheInfo *l2, 304 CPUCacheInfo *l3, 305 uint32_t *ecx, uint32_t *edx) 306 { 307 assert(l2->size % 1024 == 0); 308 assert(l2->associativity > 0); 309 assert(l2->lines_per_tag > 0); 310 assert(l2->line_size > 0); 311 *ecx = ((l2->size / 1024) << 16) | 312 (AMD_ENC_ASSOC(l2->associativity) << 12) | 313 (l2->lines_per_tag << 8) | (l2->line_size); 314 315 if (l3) { 316 assert(l3->size % (512 * 1024) == 0); 317 assert(l3->associativity > 0); 318 assert(l3->lines_per_tag > 0); 319 assert(l3->line_size > 0); 320 *edx = ((l3->size / (512 * 1024)) << 18) | 321 (AMD_ENC_ASSOC(l3->associativity) << 12) | 322 (l3->lines_per_tag << 8) | (l3->line_size); 323 } else { 324 *edx = 0; 325 } 326 } 327 328 /* Encode cache info for CPUID[8000001D] */ 329 static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, 330 X86CPUTopoInfo *topo_info, 331 uint32_t *eax, uint32_t *ebx, 332 uint32_t *ecx, uint32_t *edx) 333 { 334 uint32_t l3_threads; 335 assert(cache->size == cache->line_size * cache->associativity * 336 cache->partitions * cache->sets); 337 338 *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) | 339 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0); 340 341 /* L3 is shared among multiple cores */ 342 if (cache->level == 3) { 343 l3_threads = topo_info->cores_per_die * topo_info->threads_per_core; 344 *eax |= (l3_threads - 1) << 14; 345 } else { 346 *eax |= ((topo_info->threads_per_core - 1) << 14); 347 } 348 349 assert(cache->line_size > 0); 350 assert(cache->partitions > 0); 351 assert(cache->associativity > 0); 352 /* We don't implement fully-associative caches */ 353 assert(cache->associativity < cache->sets); 354 *ebx = (cache->line_size - 1) | 355 ((cache->partitions - 1) << 12) | 356 ((cache->associativity - 1) << 22); 357 358 assert(cache->sets > 0); 359 *ecx = cache->sets - 1; 360 361 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) | 362 (cache->inclusive ? CACHE_INCLUSIVE : 0) | 363 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); 364 } 365 366 /* Encode cache info for CPUID[8000001E] */ 367 static void encode_topo_cpuid8000001e(X86CPU *cpu, X86CPUTopoInfo *topo_info, 368 uint32_t *eax, uint32_t *ebx, 369 uint32_t *ecx, uint32_t *edx) 370 { 371 X86CPUTopoIDs topo_ids; 372 373 x86_topo_ids_from_apicid(cpu->apic_id, topo_info, &topo_ids); 374 375 *eax = cpu->apic_id; 376 377 /* 378 * CPUID_Fn8000001E_EBX [Core Identifiers] (CoreId) 379 * Read-only. Reset: 0000_XXXXh. 380 * See Core::X86::Cpuid::ExtApicId. 381 * Core::X86::Cpuid::CoreId_lthree[1:0]_core[3:0]_thread[1:0]; 382 * Bits Description 383 * 31:16 Reserved. 384 * 15:8 ThreadsPerCore: threads per core. Read-only. Reset: XXh. 385 * The number of threads per core is ThreadsPerCore+1. 386 * 7:0 CoreId: core ID. Read-only. Reset: XXh. 387 * 388 * NOTE: CoreId is already part of apic_id. Just use it. We can 389 * use all the 8 bits to represent the core_id here. 390 */ 391 *ebx = ((topo_info->threads_per_core - 1) << 8) | (topo_ids.core_id & 0xFF); 392 393 /* 394 * CPUID_Fn8000001E_ECX [Node Identifiers] (NodeId) 395 * Read-only. Reset: 0000_0XXXh. 396 * Core::X86::Cpuid::NodeId_lthree[1:0]_core[3:0]_thread[1:0]; 397 * Bits Description 398 * 31:11 Reserved. 399 * 10:8 NodesPerProcessor: Node per processor. Read-only. Reset: XXXb. 400 * ValidValues: 401 * Value Description 402 * 000b 1 node per processor. 403 * 001b 2 nodes per processor. 404 * 010b Reserved. 405 * 011b 4 nodes per processor. 406 * 111b-100b Reserved. 407 * 7:0 NodeId: Node ID. Read-only. Reset: XXh. 408 * 409 * NOTE: Hardware reserves 3 bits for number of nodes per processor. 410 * But users can create more nodes than the actual hardware can 411 * support. To genaralize we can use all the upper 8 bits for nodes. 412 * NodeId is combination of node and socket_id which is already decoded 413 * in apic_id. Just use it by shifting. 414 */ 415 *ecx = ((topo_info->dies_per_pkg - 1) << 8) | 416 ((cpu->apic_id >> apicid_die_offset(topo_info)) & 0xFF); 417 418 *edx = 0; 419 } 420 421 /* 422 * Definitions of the hardcoded cache entries we expose: 423 * These are legacy cache values. If there is a need to change any 424 * of these values please use builtin_x86_defs 425 */ 426 427 /* L1 data cache: */ 428 static CPUCacheInfo legacy_l1d_cache = { 429 .type = DATA_CACHE, 430 .level = 1, 431 .size = 32 * KiB, 432 .self_init = 1, 433 .line_size = 64, 434 .associativity = 8, 435 .sets = 64, 436 .partitions = 1, 437 .no_invd_sharing = true, 438 }; 439 440 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ 441 static CPUCacheInfo legacy_l1d_cache_amd = { 442 .type = DATA_CACHE, 443 .level = 1, 444 .size = 64 * KiB, 445 .self_init = 1, 446 .line_size = 64, 447 .associativity = 2, 448 .sets = 512, 449 .partitions = 1, 450 .lines_per_tag = 1, 451 .no_invd_sharing = true, 452 }; 453 454 /* L1 instruction cache: */ 455 static CPUCacheInfo legacy_l1i_cache = { 456 .type = INSTRUCTION_CACHE, 457 .level = 1, 458 .size = 32 * KiB, 459 .self_init = 1, 460 .line_size = 64, 461 .associativity = 8, 462 .sets = 64, 463 .partitions = 1, 464 .no_invd_sharing = true, 465 }; 466 467 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ 468 static CPUCacheInfo legacy_l1i_cache_amd = { 469 .type = INSTRUCTION_CACHE, 470 .level = 1, 471 .size = 64 * KiB, 472 .self_init = 1, 473 .line_size = 64, 474 .associativity = 2, 475 .sets = 512, 476 .partitions = 1, 477 .lines_per_tag = 1, 478 .no_invd_sharing = true, 479 }; 480 481 /* Level 2 unified cache: */ 482 static CPUCacheInfo legacy_l2_cache = { 483 .type = UNIFIED_CACHE, 484 .level = 2, 485 .size = 4 * MiB, 486 .self_init = 1, 487 .line_size = 64, 488 .associativity = 16, 489 .sets = 4096, 490 .partitions = 1, 491 .no_invd_sharing = true, 492 }; 493 494 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */ 495 static CPUCacheInfo legacy_l2_cache_cpuid2 = { 496 .type = UNIFIED_CACHE, 497 .level = 2, 498 .size = 2 * MiB, 499 .line_size = 64, 500 .associativity = 8, 501 }; 502 503 504 /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */ 505 static CPUCacheInfo legacy_l2_cache_amd = { 506 .type = UNIFIED_CACHE, 507 .level = 2, 508 .size = 512 * KiB, 509 .line_size = 64, 510 .lines_per_tag = 1, 511 .associativity = 16, 512 .sets = 512, 513 .partitions = 1, 514 }; 515 516 /* Level 3 unified cache: */ 517 static CPUCacheInfo legacy_l3_cache = { 518 .type = UNIFIED_CACHE, 519 .level = 3, 520 .size = 16 * MiB, 521 .line_size = 64, 522 .associativity = 16, 523 .sets = 16384, 524 .partitions = 1, 525 .lines_per_tag = 1, 526 .self_init = true, 527 .inclusive = true, 528 .complex_indexing = true, 529 }; 530 531 /* TLB definitions: */ 532 533 #define L1_DTLB_2M_ASSOC 1 534 #define L1_DTLB_2M_ENTRIES 255 535 #define L1_DTLB_4K_ASSOC 1 536 #define L1_DTLB_4K_ENTRIES 255 537 538 #define L1_ITLB_2M_ASSOC 1 539 #define L1_ITLB_2M_ENTRIES 255 540 #define L1_ITLB_4K_ASSOC 1 541 #define L1_ITLB_4K_ENTRIES 255 542 543 #define L2_DTLB_2M_ASSOC 0 /* disabled */ 544 #define L2_DTLB_2M_ENTRIES 0 /* disabled */ 545 #define L2_DTLB_4K_ASSOC 4 546 #define L2_DTLB_4K_ENTRIES 512 547 548 #define L2_ITLB_2M_ASSOC 0 /* disabled */ 549 #define L2_ITLB_2M_ENTRIES 0 /* disabled */ 550 #define L2_ITLB_4K_ASSOC 4 551 #define L2_ITLB_4K_ENTRIES 512 552 553 /* CPUID Leaf 0x14 constants: */ 554 #define INTEL_PT_MAX_SUBLEAF 0x1 555 /* 556 * bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MATCH 557 * MSR can be accessed; 558 * bit[01]: Support Configurable PSB and Cycle-Accurate Mode; 559 * bit[02]: Support IP Filtering, TraceStop filtering, and preservation 560 * of Intel PT MSRs across warm reset; 561 * bit[03]: Support MTC timing packet and suppression of COFI-based packets; 562 */ 563 #define INTEL_PT_MINIMAL_EBX 0xf 564 /* 565 * bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 and 566 * IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be 567 * accessed; 568 * bit[01]: ToPA tables can hold any number of output entries, up to the 569 * maximum allowed by the MaskOrTableOffset field of 570 * IA32_RTIT_OUTPUT_MASK_PTRS; 571 * bit[02]: Support Single-Range Output scheme; 572 */ 573 #define INTEL_PT_MINIMAL_ECX 0x7 574 /* generated packets which contain IP payloads have LIP values */ 575 #define INTEL_PT_IP_LIP (1 << 31) 576 #define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */ 577 #define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3 578 #define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */ 579 #define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */ 580 #define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */ 581 582 /* CPUID Leaf 0x1D constants: */ 583 #define INTEL_AMX_TILE_MAX_SUBLEAF 0x1 584 #define INTEL_AMX_TOTAL_TILE_BYTES 0x2000 585 #define INTEL_AMX_BYTES_PER_TILE 0x400 586 #define INTEL_AMX_BYTES_PER_ROW 0x40 587 #define INTEL_AMX_TILE_MAX_NAMES 0x8 588 #define INTEL_AMX_TILE_MAX_ROWS 0x10 589 590 /* CPUID Leaf 0x1E constants: */ 591 #define INTEL_AMX_TMUL_MAX_K 0x10 592 #define INTEL_AMX_TMUL_MAX_N 0x40 593 594 void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1, 595 uint32_t vendor2, uint32_t vendor3) 596 { 597 int i; 598 for (i = 0; i < 4; i++) { 599 dst[i] = vendor1 >> (8 * i); 600 dst[i + 4] = vendor2 >> (8 * i); 601 dst[i + 8] = vendor3 >> (8 * i); 602 } 603 dst[CPUID_VENDOR_SZ] = '\0'; 604 } 605 606 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE) 607 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \ 608 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC) 609 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \ 610 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ 611 CPUID_PSE36 | CPUID_FXSR) 612 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE) 613 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \ 614 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \ 615 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \ 616 CPUID_PAE | CPUID_SEP | CPUID_APIC) 617 618 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \ 619 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \ 620 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ 621 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \ 622 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE) 623 /* partly implemented: 624 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */ 625 /* missing: 626 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */ 627 628 /* 629 * Kernel-only features that can be shown to usermode programs even if 630 * they aren't actually supported by TCG, because qemu-user only runs 631 * in CPL=3; remove them if they are ever implemented for system emulation. 632 */ 633 #if defined CONFIG_USER_ONLY 634 #define CPUID_EXT_KERNEL_FEATURES (CPUID_EXT_PCID | CPUID_EXT_TSC_DEADLINE_TIMER | \ 635 CPUID_EXT_X2APIC) 636 #else 637 #define CPUID_EXT_KERNEL_FEATURES 0 638 #endif 639 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \ 640 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \ 641 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \ 642 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \ 643 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR | \ 644 CPUID_EXT_RDRAND | CPUID_EXT_AVX | CPUID_EXT_F16C | \ 645 CPUID_EXT_FMA | CPUID_EXT_KERNEL_FEATURES) 646 /* missing: 647 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX, 648 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, 649 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA, 650 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER */ 651 652 #ifdef TARGET_X86_64 653 #define TCG_EXT2_X86_64_FEATURES CPUID_EXT2_LM 654 #else 655 #define TCG_EXT2_X86_64_FEATURES 0 656 #endif 657 658 /* 659 * CPUID_*_KERNEL_FEATURES denotes bits and features that are not usable 660 * in usermode or by 32-bit programs. Those are added to supported 661 * TCG features unconditionally in user-mode emulation mode. This may 662 * indeed seem strange or incorrect, but it works because code running 663 * under usermode emulation cannot access them. 664 * 665 * Even for long mode, qemu-i386 is not running "a userspace program on a 666 * 32-bit CPU"; it's running "a userspace program with a 32-bit code segment" 667 * and therefore using the 32-bit ABI; the CPU itself might be 64-bit 668 * but again the difference is only visible in kernel mode. 669 */ 670 #if defined CONFIG_LINUX_USER 671 #define CPUID_EXT2_KERNEL_FEATURES (CPUID_EXT2_LM | CPUID_EXT2_FFXSR) 672 #elif defined CONFIG_USER_ONLY 673 /* FIXME: Long mode not yet supported for i386 bsd-user */ 674 #define CPUID_EXT2_KERNEL_FEATURES CPUID_EXT2_FFXSR 675 #else 676 #define CPUID_EXT2_KERNEL_FEATURES 0 677 #endif 678 679 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \ 680 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \ 681 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \ 682 CPUID_EXT2_SYSCALL | TCG_EXT2_X86_64_FEATURES | \ 683 CPUID_EXT2_KERNEL_FEATURES) 684 685 #if defined CONFIG_USER_ONLY 686 #define CPUID_EXT3_KERNEL_FEATURES CPUID_EXT3_OSVW 687 #else 688 #define CPUID_EXT3_KERNEL_FEATURES 0 689 #endif 690 691 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \ 692 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A | \ 693 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_KERNEL_FEATURES) 694 695 #define TCG_EXT4_FEATURES 0 696 697 #if defined CONFIG_USER_ONLY 698 #define CPUID_SVM_KERNEL_FEATURES (CPUID_SVM_NRIPSAVE | CPUID_SVM_VNMI) 699 #else 700 #define CPUID_SVM_KERNEL_FEATURES 0 701 #endif 702 #define TCG_SVM_FEATURES (CPUID_SVM_NPT | CPUID_SVM_VGIF | \ 703 CPUID_SVM_SVME_ADDR_CHK | CPUID_SVM_KERNEL_FEATURES) 704 705 #define TCG_KVM_FEATURES 0 706 707 #if defined CONFIG_USER_ONLY 708 #define CPUID_7_0_EBX_KERNEL_FEATURES CPUID_7_0_EBX_INVPCID 709 #else 710 #define CPUID_7_0_EBX_KERNEL_FEATURES 0 711 #endif 712 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \ 713 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \ 714 CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \ 715 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \ 716 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_RDSEED | \ 717 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_KERNEL_FEATURES) 718 /* missing: 719 CPUID_7_0_EBX_HLE 720 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM */ 721 722 #if !defined CONFIG_USER_ONLY || defined CONFIG_LINUX 723 #define TCG_7_0_ECX_RDPID CPUID_7_0_ECX_RDPID 724 #else 725 #define TCG_7_0_ECX_RDPID 0 726 #endif 727 #define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | \ 728 /* CPUID_7_0_ECX_OSPKE is dynamic */ \ 729 CPUID_7_0_ECX_LA57 | CPUID_7_0_ECX_PKS | CPUID_7_0_ECX_VAES | \ 730 TCG_7_0_ECX_RDPID) 731 732 #if defined CONFIG_USER_ONLY 733 #define CPUID_7_0_EDX_KERNEL_FEATURES (CPUID_7_0_EDX_SPEC_CTRL | \ 734 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD) 735 #else 736 #define CPUID_7_0_EDX_KERNEL_FEATURES 0 737 #endif 738 #define TCG_7_0_EDX_FEATURES (CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_KERNEL_FEATURES) 739 740 #define TCG_7_1_EAX_FEATURES (CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | \ 741 CPUID_7_1_EAX_FSRC) 742 #define TCG_7_1_EDX_FEATURES 0 743 #define TCG_7_2_EDX_FEATURES 0 744 #define TCG_APM_FEATURES 0 745 #define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT 746 #define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1) 747 /* missing: 748 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */ 749 #define TCG_14_0_ECX_FEATURES 0 750 #define TCG_SGX_12_0_EAX_FEATURES 0 751 #define TCG_SGX_12_0_EBX_FEATURES 0 752 #define TCG_SGX_12_1_EAX_FEATURES 0 753 754 #if defined CONFIG_USER_ONLY 755 #define CPUID_8000_0008_EBX_KERNEL_FEATURES (CPUID_8000_0008_EBX_IBPB | \ 756 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | \ 757 CPUID_8000_0008_EBX_STIBP_ALWAYS_ON | CPUID_8000_0008_EBX_AMD_SSBD | \ 758 CPUID_8000_0008_EBX_AMD_PSFD) 759 #else 760 #define CPUID_8000_0008_EBX_KERNEL_FEATURES 0 761 #endif 762 763 #define TCG_8000_0008_EBX (CPUID_8000_0008_EBX_XSAVEERPTR | \ 764 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_KERNEL_FEATURES) 765 766 FeatureWordInfo feature_word_info[FEATURE_WORDS] = { 767 [FEAT_1_EDX] = { 768 .type = CPUID_FEATURE_WORD, 769 .feat_names = { 770 "fpu", "vme", "de", "pse", 771 "tsc", "msr", "pae", "mce", 772 "cx8", "apic", NULL, "sep", 773 "mtrr", "pge", "mca", "cmov", 774 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */, 775 NULL, "ds" /* Intel dts */, "acpi", "mmx", 776 "fxsr", "sse", "sse2", "ss", 777 "ht" /* Intel htt */, "tm", "ia64", "pbe", 778 }, 779 .cpuid = {.eax = 1, .reg = R_EDX, }, 780 .tcg_features = TCG_FEATURES, 781 .no_autoenable_flags = CPUID_HT, 782 }, 783 [FEAT_1_ECX] = { 784 .type = CPUID_FEATURE_WORD, 785 .feat_names = { 786 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor", 787 "ds-cpl", "vmx", "smx", "est", 788 "tm2", "ssse3", "cid", NULL, 789 "fma", "cx16", "xtpr", "pdcm", 790 NULL, "pcid", "dca", "sse4.1", 791 "sse4.2", "x2apic", "movbe", "popcnt", 792 "tsc-deadline", "aes", "xsave", NULL /* osxsave */, 793 "avx", "f16c", "rdrand", "hypervisor", 794 }, 795 .cpuid = { .eax = 1, .reg = R_ECX, }, 796 .tcg_features = TCG_EXT_FEATURES, 797 }, 798 /* Feature names that are already defined on feature_name[] but 799 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their 800 * names on feat_names below. They are copied automatically 801 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD. 802 */ 803 [FEAT_8000_0001_EDX] = { 804 .type = CPUID_FEATURE_WORD, 805 .feat_names = { 806 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */, 807 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */, 808 NULL /* cx8 */, NULL /* apic */, NULL, "syscall", 809 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */, 810 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */, 811 "nx", NULL, "mmxext", NULL /* mmx */, 812 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp", 813 NULL, "lm", "3dnowext", "3dnow", 814 }, 815 .cpuid = { .eax = 0x80000001, .reg = R_EDX, }, 816 .tcg_features = TCG_EXT2_FEATURES, 817 }, 818 [FEAT_8000_0001_ECX] = { 819 .type = CPUID_FEATURE_WORD, 820 .feat_names = { 821 "lahf-lm", "cmp-legacy", "svm", "extapic", 822 "cr8legacy", "abm", "sse4a", "misalignsse", 823 "3dnowprefetch", "osvw", "ibs", "xop", 824 "skinit", "wdt", NULL, "lwp", 825 "fma4", "tce", NULL, "nodeid-msr", 826 NULL, "tbm", "topoext", "perfctr-core", 827 "perfctr-nb", NULL, NULL, NULL, 828 NULL, NULL, NULL, NULL, 829 }, 830 .cpuid = { .eax = 0x80000001, .reg = R_ECX, }, 831 .tcg_features = TCG_EXT3_FEATURES, 832 /* 833 * TOPOEXT is always allowed but can't be enabled blindly by 834 * "-cpu host", as it requires consistent cache topology info 835 * to be provided so it doesn't confuse guests. 836 */ 837 .no_autoenable_flags = CPUID_EXT3_TOPOEXT, 838 }, 839 [FEAT_C000_0001_EDX] = { 840 .type = CPUID_FEATURE_WORD, 841 .feat_names = { 842 NULL, NULL, "xstore", "xstore-en", 843 NULL, NULL, "xcrypt", "xcrypt-en", 844 "ace2", "ace2-en", "phe", "phe-en", 845 "pmm", "pmm-en", NULL, NULL, 846 NULL, NULL, NULL, NULL, 847 NULL, NULL, NULL, NULL, 848 NULL, NULL, NULL, NULL, 849 NULL, NULL, NULL, NULL, 850 }, 851 .cpuid = { .eax = 0xC0000001, .reg = R_EDX, }, 852 .tcg_features = TCG_EXT4_FEATURES, 853 }, 854 [FEAT_KVM] = { 855 .type = CPUID_FEATURE_WORD, 856 .feat_names = { 857 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock", 858 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt", 859 NULL, "kvm-pv-tlb-flush", NULL, "kvm-pv-ipi", 860 "kvm-poll-control", "kvm-pv-sched-yield", "kvm-asyncpf-int", "kvm-msi-ext-dest-id", 861 NULL, NULL, NULL, NULL, 862 NULL, NULL, NULL, NULL, 863 "kvmclock-stable-bit", NULL, NULL, NULL, 864 NULL, NULL, NULL, NULL, 865 }, 866 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EAX, }, 867 .tcg_features = TCG_KVM_FEATURES, 868 }, 869 [FEAT_KVM_HINTS] = { 870 .type = CPUID_FEATURE_WORD, 871 .feat_names = { 872 "kvm-hint-dedicated", NULL, NULL, NULL, 873 NULL, NULL, NULL, NULL, 874 NULL, NULL, NULL, NULL, 875 NULL, NULL, NULL, NULL, 876 NULL, NULL, NULL, NULL, 877 NULL, NULL, NULL, NULL, 878 NULL, NULL, NULL, NULL, 879 NULL, NULL, NULL, NULL, 880 }, 881 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EDX, }, 882 .tcg_features = TCG_KVM_FEATURES, 883 /* 884 * KVM hints aren't auto-enabled by -cpu host, they need to be 885 * explicitly enabled in the command-line. 886 */ 887 .no_autoenable_flags = ~0U, 888 }, 889 [FEAT_SVM] = { 890 .type = CPUID_FEATURE_WORD, 891 .feat_names = { 892 "npt", "lbrv", "svm-lock", "nrip-save", 893 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists", 894 NULL, NULL, "pause-filter", NULL, 895 "pfthreshold", "avic", NULL, "v-vmsave-vmload", 896 "vgif", NULL, NULL, NULL, 897 NULL, NULL, NULL, NULL, 898 NULL, "vnmi", NULL, NULL, 899 "svme-addr-chk", NULL, NULL, NULL, 900 }, 901 .cpuid = { .eax = 0x8000000A, .reg = R_EDX, }, 902 .tcg_features = TCG_SVM_FEATURES, 903 }, 904 [FEAT_7_0_EBX] = { 905 .type = CPUID_FEATURE_WORD, 906 .feat_names = { 907 "fsgsbase", "tsc-adjust", "sgx", "bmi1", 908 "hle", "avx2", NULL, "smep", 909 "bmi2", "erms", "invpcid", "rtm", 910 NULL, NULL, "mpx", NULL, 911 "avx512f", "avx512dq", "rdseed", "adx", 912 "smap", "avx512ifma", "pcommit", "clflushopt", 913 "clwb", "intel-pt", "avx512pf", "avx512er", 914 "avx512cd", "sha-ni", "avx512bw", "avx512vl", 915 }, 916 .cpuid = { 917 .eax = 7, 918 .needs_ecx = true, .ecx = 0, 919 .reg = R_EBX, 920 }, 921 .tcg_features = TCG_7_0_EBX_FEATURES, 922 }, 923 [FEAT_7_0_ECX] = { 924 .type = CPUID_FEATURE_WORD, 925 .feat_names = { 926 NULL, "avx512vbmi", "umip", "pku", 927 NULL /* ospke */, "waitpkg", "avx512vbmi2", NULL, 928 "gfni", "vaes", "vpclmulqdq", "avx512vnni", 929 "avx512bitalg", NULL, "avx512-vpopcntdq", NULL, 930 "la57", NULL, NULL, NULL, 931 NULL, NULL, "rdpid", NULL, 932 "bus-lock-detect", "cldemote", NULL, "movdiri", 933 "movdir64b", NULL, "sgxlc", "pks", 934 }, 935 .cpuid = { 936 .eax = 7, 937 .needs_ecx = true, .ecx = 0, 938 .reg = R_ECX, 939 }, 940 .tcg_features = TCG_7_0_ECX_FEATURES, 941 }, 942 [FEAT_7_0_EDX] = { 943 .type = CPUID_FEATURE_WORD, 944 .feat_names = { 945 NULL, NULL, "avx512-4vnniw", "avx512-4fmaps", 946 "fsrm", NULL, NULL, NULL, 947 "avx512-vp2intersect", NULL, "md-clear", NULL, 948 NULL, NULL, "serialize", NULL, 949 "tsx-ldtrk", NULL, NULL /* pconfig */, "arch-lbr", 950 NULL, NULL, "amx-bf16", "avx512-fp16", 951 "amx-tile", "amx-int8", "spec-ctrl", "stibp", 952 "flush-l1d", "arch-capabilities", "core-capability", "ssbd", 953 }, 954 .cpuid = { 955 .eax = 7, 956 .needs_ecx = true, .ecx = 0, 957 .reg = R_EDX, 958 }, 959 .tcg_features = TCG_7_0_EDX_FEATURES, 960 }, 961 [FEAT_7_1_EAX] = { 962 .type = CPUID_FEATURE_WORD, 963 .feat_names = { 964 NULL, NULL, NULL, NULL, 965 "avx-vnni", "avx512-bf16", NULL, "cmpccxadd", 966 NULL, NULL, "fzrm", "fsrs", 967 "fsrc", NULL, NULL, NULL, 968 NULL, NULL, NULL, NULL, 969 NULL, "amx-fp16", NULL, "avx-ifma", 970 NULL, NULL, NULL, NULL, 971 NULL, NULL, NULL, NULL, 972 }, 973 .cpuid = { 974 .eax = 7, 975 .needs_ecx = true, .ecx = 1, 976 .reg = R_EAX, 977 }, 978 .tcg_features = TCG_7_1_EAX_FEATURES, 979 }, 980 [FEAT_7_1_EDX] = { 981 .type = CPUID_FEATURE_WORD, 982 .feat_names = { 983 NULL, NULL, NULL, NULL, 984 "avx-vnni-int8", "avx-ne-convert", NULL, NULL, 985 "amx-complex", NULL, NULL, NULL, 986 NULL, NULL, "prefetchiti", NULL, 987 NULL, NULL, NULL, NULL, 988 NULL, NULL, NULL, NULL, 989 NULL, NULL, NULL, NULL, 990 NULL, NULL, NULL, NULL, 991 }, 992 .cpuid = { 993 .eax = 7, 994 .needs_ecx = true, .ecx = 1, 995 .reg = R_EDX, 996 }, 997 .tcg_features = TCG_7_1_EDX_FEATURES, 998 }, 999 [FEAT_7_2_EDX] = { 1000 .type = CPUID_FEATURE_WORD, 1001 .feat_names = { 1002 NULL, NULL, NULL, NULL, 1003 NULL, "mcdt-no", NULL, NULL, 1004 NULL, NULL, NULL, NULL, 1005 NULL, NULL, NULL, NULL, 1006 NULL, NULL, NULL, NULL, 1007 NULL, NULL, NULL, NULL, 1008 NULL, NULL, NULL, NULL, 1009 NULL, NULL, NULL, NULL, 1010 }, 1011 .cpuid = { 1012 .eax = 7, 1013 .needs_ecx = true, .ecx = 2, 1014 .reg = R_EDX, 1015 }, 1016 .tcg_features = TCG_7_2_EDX_FEATURES, 1017 }, 1018 [FEAT_8000_0007_EDX] = { 1019 .type = CPUID_FEATURE_WORD, 1020 .feat_names = { 1021 NULL, NULL, NULL, NULL, 1022 NULL, NULL, NULL, NULL, 1023 "invtsc", NULL, NULL, NULL, 1024 NULL, NULL, NULL, NULL, 1025 NULL, NULL, NULL, NULL, 1026 NULL, NULL, NULL, NULL, 1027 NULL, NULL, NULL, NULL, 1028 NULL, NULL, NULL, NULL, 1029 }, 1030 .cpuid = { .eax = 0x80000007, .reg = R_EDX, }, 1031 .tcg_features = TCG_APM_FEATURES, 1032 .unmigratable_flags = CPUID_APM_INVTSC, 1033 }, 1034 [FEAT_8000_0008_EBX] = { 1035 .type = CPUID_FEATURE_WORD, 1036 .feat_names = { 1037 "clzero", NULL, "xsaveerptr", NULL, 1038 NULL, NULL, NULL, NULL, 1039 NULL, "wbnoinvd", NULL, NULL, 1040 "ibpb", NULL, "ibrs", "amd-stibp", 1041 NULL, "stibp-always-on", NULL, NULL, 1042 NULL, NULL, NULL, NULL, 1043 "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL, 1044 "amd-psfd", NULL, NULL, NULL, 1045 }, 1046 .cpuid = { .eax = 0x80000008, .reg = R_EBX, }, 1047 .tcg_features = TCG_8000_0008_EBX, 1048 .unmigratable_flags = 0, 1049 }, 1050 [FEAT_8000_0021_EAX] = { 1051 .type = CPUID_FEATURE_WORD, 1052 .feat_names = { 1053 "no-nested-data-bp", NULL, "lfence-always-serializing", NULL, 1054 NULL, NULL, "null-sel-clr-base", NULL, 1055 "auto-ibrs", NULL, NULL, NULL, 1056 NULL, NULL, NULL, NULL, 1057 NULL, NULL, NULL, NULL, 1058 NULL, NULL, NULL, NULL, 1059 NULL, NULL, NULL, NULL, 1060 NULL, NULL, NULL, NULL, 1061 }, 1062 .cpuid = { .eax = 0x80000021, .reg = R_EAX, }, 1063 .tcg_features = 0, 1064 .unmigratable_flags = 0, 1065 }, 1066 [FEAT_XSAVE] = { 1067 .type = CPUID_FEATURE_WORD, 1068 .feat_names = { 1069 "xsaveopt", "xsavec", "xgetbv1", "xsaves", 1070 "xfd", NULL, NULL, NULL, 1071 NULL, NULL, NULL, NULL, 1072 NULL, NULL, NULL, NULL, 1073 NULL, NULL, NULL, NULL, 1074 NULL, NULL, NULL, NULL, 1075 NULL, NULL, NULL, NULL, 1076 NULL, NULL, NULL, NULL, 1077 }, 1078 .cpuid = { 1079 .eax = 0xd, 1080 .needs_ecx = true, .ecx = 1, 1081 .reg = R_EAX, 1082 }, 1083 .tcg_features = TCG_XSAVE_FEATURES, 1084 }, 1085 [FEAT_XSAVE_XSS_LO] = { 1086 .type = CPUID_FEATURE_WORD, 1087 .feat_names = { 1088 NULL, NULL, NULL, NULL, 1089 NULL, NULL, NULL, NULL, 1090 NULL, NULL, NULL, NULL, 1091 NULL, NULL, NULL, NULL, 1092 NULL, NULL, NULL, NULL, 1093 NULL, NULL, NULL, NULL, 1094 NULL, NULL, NULL, NULL, 1095 NULL, NULL, NULL, NULL, 1096 }, 1097 .cpuid = { 1098 .eax = 0xD, 1099 .needs_ecx = true, 1100 .ecx = 1, 1101 .reg = R_ECX, 1102 }, 1103 }, 1104 [FEAT_XSAVE_XSS_HI] = { 1105 .type = CPUID_FEATURE_WORD, 1106 .cpuid = { 1107 .eax = 0xD, 1108 .needs_ecx = true, 1109 .ecx = 1, 1110 .reg = R_EDX 1111 }, 1112 }, 1113 [FEAT_6_EAX] = { 1114 .type = CPUID_FEATURE_WORD, 1115 .feat_names = { 1116 NULL, NULL, "arat", NULL, 1117 NULL, NULL, NULL, NULL, 1118 NULL, NULL, NULL, NULL, 1119 NULL, NULL, NULL, NULL, 1120 NULL, NULL, NULL, NULL, 1121 NULL, NULL, NULL, NULL, 1122 NULL, NULL, NULL, NULL, 1123 NULL, NULL, NULL, NULL, 1124 }, 1125 .cpuid = { .eax = 6, .reg = R_EAX, }, 1126 .tcg_features = TCG_6_EAX_FEATURES, 1127 }, 1128 [FEAT_XSAVE_XCR0_LO] = { 1129 .type = CPUID_FEATURE_WORD, 1130 .cpuid = { 1131 .eax = 0xD, 1132 .needs_ecx = true, .ecx = 0, 1133 .reg = R_EAX, 1134 }, 1135 .tcg_features = ~0U, 1136 .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK | 1137 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK | 1138 XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK | 1139 XSTATE_PKRU_MASK, 1140 }, 1141 [FEAT_XSAVE_XCR0_HI] = { 1142 .type = CPUID_FEATURE_WORD, 1143 .cpuid = { 1144 .eax = 0xD, 1145 .needs_ecx = true, .ecx = 0, 1146 .reg = R_EDX, 1147 }, 1148 .tcg_features = ~0U, 1149 }, 1150 /*Below are MSR exposed features*/ 1151 [FEAT_ARCH_CAPABILITIES] = { 1152 .type = MSR_FEATURE_WORD, 1153 .feat_names = { 1154 "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry", 1155 "ssb-no", "mds-no", "pschange-mc-no", "tsx-ctrl", 1156 "taa-no", NULL, NULL, NULL, 1157 NULL, "sbdr-ssdp-no", "fbsdp-no", "psdp-no", 1158 NULL, "fb-clear", NULL, NULL, 1159 NULL, NULL, NULL, NULL, 1160 "pbrsb-no", NULL, "gds-no", NULL, 1161 NULL, NULL, NULL, NULL, 1162 }, 1163 .msr = { 1164 .index = MSR_IA32_ARCH_CAPABILITIES, 1165 }, 1166 /* 1167 * FEAT_ARCH_CAPABILITIES only affects a read-only MSR, which 1168 * cannot be read from user mode. Therefore, it has no impact 1169 > on any user-mode operation, and warnings about unsupported 1170 * features do not matter. 1171 */ 1172 .tcg_features = ~0U, 1173 }, 1174 [FEAT_CORE_CAPABILITY] = { 1175 .type = MSR_FEATURE_WORD, 1176 .feat_names = { 1177 NULL, NULL, NULL, NULL, 1178 NULL, "split-lock-detect", NULL, NULL, 1179 NULL, NULL, NULL, NULL, 1180 NULL, NULL, NULL, NULL, 1181 NULL, NULL, NULL, NULL, 1182 NULL, NULL, NULL, NULL, 1183 NULL, NULL, NULL, NULL, 1184 NULL, NULL, NULL, NULL, 1185 }, 1186 .msr = { 1187 .index = MSR_IA32_CORE_CAPABILITY, 1188 }, 1189 }, 1190 [FEAT_PERF_CAPABILITIES] = { 1191 .type = MSR_FEATURE_WORD, 1192 .feat_names = { 1193 NULL, NULL, NULL, NULL, 1194 NULL, NULL, NULL, NULL, 1195 NULL, NULL, NULL, NULL, 1196 NULL, "full-width-write", NULL, NULL, 1197 NULL, NULL, NULL, NULL, 1198 NULL, NULL, NULL, NULL, 1199 NULL, NULL, NULL, NULL, 1200 NULL, NULL, NULL, NULL, 1201 }, 1202 .msr = { 1203 .index = MSR_IA32_PERF_CAPABILITIES, 1204 }, 1205 }, 1206 1207 [FEAT_VMX_PROCBASED_CTLS] = { 1208 .type = MSR_FEATURE_WORD, 1209 .feat_names = { 1210 NULL, NULL, "vmx-vintr-pending", "vmx-tsc-offset", 1211 NULL, NULL, NULL, "vmx-hlt-exit", 1212 NULL, "vmx-invlpg-exit", "vmx-mwait-exit", "vmx-rdpmc-exit", 1213 "vmx-rdtsc-exit", NULL, NULL, "vmx-cr3-load-noexit", 1214 "vmx-cr3-store-noexit", NULL, NULL, "vmx-cr8-load-exit", 1215 "vmx-cr8-store-exit", "vmx-flexpriority", "vmx-vnmi-pending", "vmx-movdr-exit", 1216 "vmx-io-exit", "vmx-io-bitmap", NULL, "vmx-mtf", 1217 "vmx-msr-bitmap", "vmx-monitor-exit", "vmx-pause-exit", "vmx-secondary-ctls", 1218 }, 1219 .msr = { 1220 .index = MSR_IA32_VMX_TRUE_PROCBASED_CTLS, 1221 } 1222 }, 1223 1224 [FEAT_VMX_SECONDARY_CTLS] = { 1225 .type = MSR_FEATURE_WORD, 1226 .feat_names = { 1227 "vmx-apicv-xapic", "vmx-ept", "vmx-desc-exit", "vmx-rdtscp-exit", 1228 "vmx-apicv-x2apic", "vmx-vpid", "vmx-wbinvd-exit", "vmx-unrestricted-guest", 1229 "vmx-apicv-register", "vmx-apicv-vid", "vmx-ple", "vmx-rdrand-exit", 1230 "vmx-invpcid-exit", "vmx-vmfunc", "vmx-shadow-vmcs", "vmx-encls-exit", 1231 "vmx-rdseed-exit", "vmx-pml", NULL, NULL, 1232 "vmx-xsaves", NULL, NULL, NULL, 1233 NULL, "vmx-tsc-scaling", "vmx-enable-user-wait-pause", NULL, 1234 NULL, NULL, NULL, NULL, 1235 }, 1236 .msr = { 1237 .index = MSR_IA32_VMX_PROCBASED_CTLS2, 1238 } 1239 }, 1240 1241 [FEAT_VMX_PINBASED_CTLS] = { 1242 .type = MSR_FEATURE_WORD, 1243 .feat_names = { 1244 "vmx-intr-exit", NULL, NULL, "vmx-nmi-exit", 1245 NULL, "vmx-vnmi", "vmx-preemption-timer", "vmx-posted-intr", 1246 NULL, NULL, NULL, NULL, 1247 NULL, NULL, NULL, NULL, 1248 NULL, NULL, NULL, NULL, 1249 NULL, NULL, NULL, NULL, 1250 NULL, NULL, NULL, NULL, 1251 NULL, NULL, NULL, NULL, 1252 }, 1253 .msr = { 1254 .index = MSR_IA32_VMX_TRUE_PINBASED_CTLS, 1255 } 1256 }, 1257 1258 [FEAT_VMX_EXIT_CTLS] = { 1259 .type = MSR_FEATURE_WORD, 1260 /* 1261 * VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE is copied from 1262 * the LM CPUID bit. 1263 */ 1264 .feat_names = { 1265 NULL, NULL, "vmx-exit-nosave-debugctl", NULL, 1266 NULL, NULL, NULL, NULL, 1267 NULL, NULL /* vmx-exit-host-addr-space-size */, NULL, NULL, 1268 "vmx-exit-load-perf-global-ctrl", NULL, NULL, "vmx-exit-ack-intr", 1269 NULL, NULL, "vmx-exit-save-pat", "vmx-exit-load-pat", 1270 "vmx-exit-save-efer", "vmx-exit-load-efer", 1271 "vmx-exit-save-preemption-timer", "vmx-exit-clear-bndcfgs", 1272 NULL, "vmx-exit-clear-rtit-ctl", NULL, NULL, 1273 NULL, "vmx-exit-load-pkrs", NULL, NULL, 1274 }, 1275 .msr = { 1276 .index = MSR_IA32_VMX_TRUE_EXIT_CTLS, 1277 } 1278 }, 1279 1280 [FEAT_VMX_ENTRY_CTLS] = { 1281 .type = MSR_FEATURE_WORD, 1282 .feat_names = { 1283 NULL, NULL, "vmx-entry-noload-debugctl", NULL, 1284 NULL, NULL, NULL, NULL, 1285 NULL, "vmx-entry-ia32e-mode", NULL, NULL, 1286 NULL, "vmx-entry-load-perf-global-ctrl", "vmx-entry-load-pat", "vmx-entry-load-efer", 1287 "vmx-entry-load-bndcfgs", NULL, "vmx-entry-load-rtit-ctl", NULL, 1288 NULL, NULL, "vmx-entry-load-pkrs", NULL, 1289 NULL, NULL, NULL, NULL, 1290 NULL, NULL, NULL, NULL, 1291 }, 1292 .msr = { 1293 .index = MSR_IA32_VMX_TRUE_ENTRY_CTLS, 1294 } 1295 }, 1296 1297 [FEAT_VMX_MISC] = { 1298 .type = MSR_FEATURE_WORD, 1299 .feat_names = { 1300 NULL, NULL, NULL, NULL, 1301 NULL, "vmx-store-lma", "vmx-activity-hlt", "vmx-activity-shutdown", 1302 "vmx-activity-wait-sipi", NULL, NULL, NULL, 1303 NULL, NULL, NULL, NULL, 1304 NULL, NULL, NULL, NULL, 1305 NULL, NULL, NULL, NULL, 1306 NULL, NULL, NULL, NULL, 1307 NULL, "vmx-vmwrite-vmexit-fields", "vmx-zero-len-inject", NULL, 1308 }, 1309 .msr = { 1310 .index = MSR_IA32_VMX_MISC, 1311 } 1312 }, 1313 1314 [FEAT_VMX_EPT_VPID_CAPS] = { 1315 .type = MSR_FEATURE_WORD, 1316 .feat_names = { 1317 "vmx-ept-execonly", NULL, NULL, NULL, 1318 NULL, NULL, "vmx-page-walk-4", "vmx-page-walk-5", 1319 NULL, NULL, NULL, NULL, 1320 NULL, NULL, NULL, NULL, 1321 "vmx-ept-2mb", "vmx-ept-1gb", NULL, NULL, 1322 "vmx-invept", "vmx-eptad", "vmx-ept-advanced-exitinfo", NULL, 1323 NULL, "vmx-invept-single-context", "vmx-invept-all-context", NULL, 1324 NULL, NULL, NULL, NULL, 1325 "vmx-invvpid", NULL, NULL, NULL, 1326 NULL, NULL, NULL, NULL, 1327 "vmx-invvpid-single-addr", "vmx-invept-single-context", 1328 "vmx-invvpid-all-context", "vmx-invept-single-context-noglobals", 1329 NULL, NULL, NULL, NULL, 1330 NULL, NULL, NULL, NULL, 1331 NULL, NULL, NULL, NULL, 1332 NULL, NULL, NULL, NULL, 1333 NULL, NULL, NULL, NULL, 1334 }, 1335 .msr = { 1336 .index = MSR_IA32_VMX_EPT_VPID_CAP, 1337 } 1338 }, 1339 1340 [FEAT_VMX_BASIC] = { 1341 .type = MSR_FEATURE_WORD, 1342 .feat_names = { 1343 [54] = "vmx-ins-outs", 1344 [55] = "vmx-true-ctls", 1345 [56] = "vmx-any-errcode", 1346 }, 1347 .msr = { 1348 .index = MSR_IA32_VMX_BASIC, 1349 }, 1350 /* Just to be safe - we don't support setting the MSEG version field. */ 1351 .no_autoenable_flags = MSR_VMX_BASIC_DUAL_MONITOR, 1352 }, 1353 1354 [FEAT_VMX_VMFUNC] = { 1355 .type = MSR_FEATURE_WORD, 1356 .feat_names = { 1357 [0] = "vmx-eptp-switching", 1358 }, 1359 .msr = { 1360 .index = MSR_IA32_VMX_VMFUNC, 1361 } 1362 }, 1363 1364 [FEAT_14_0_ECX] = { 1365 .type = CPUID_FEATURE_WORD, 1366 .feat_names = { 1367 NULL, NULL, NULL, NULL, 1368 NULL, NULL, NULL, NULL, 1369 NULL, NULL, NULL, NULL, 1370 NULL, NULL, NULL, NULL, 1371 NULL, NULL, NULL, NULL, 1372 NULL, NULL, NULL, NULL, 1373 NULL, NULL, NULL, NULL, 1374 NULL, NULL, NULL, "intel-pt-lip", 1375 }, 1376 .cpuid = { 1377 .eax = 0x14, 1378 .needs_ecx = true, .ecx = 0, 1379 .reg = R_ECX, 1380 }, 1381 .tcg_features = TCG_14_0_ECX_FEATURES, 1382 }, 1383 1384 [FEAT_SGX_12_0_EAX] = { 1385 .type = CPUID_FEATURE_WORD, 1386 .feat_names = { 1387 "sgx1", "sgx2", NULL, NULL, 1388 NULL, NULL, NULL, NULL, 1389 NULL, NULL, NULL, "sgx-edeccssa", 1390 NULL, NULL, NULL, NULL, 1391 NULL, NULL, NULL, NULL, 1392 NULL, NULL, NULL, NULL, 1393 NULL, NULL, NULL, NULL, 1394 NULL, NULL, NULL, NULL, 1395 }, 1396 .cpuid = { 1397 .eax = 0x12, 1398 .needs_ecx = true, .ecx = 0, 1399 .reg = R_EAX, 1400 }, 1401 .tcg_features = TCG_SGX_12_0_EAX_FEATURES, 1402 }, 1403 1404 [FEAT_SGX_12_0_EBX] = { 1405 .type = CPUID_FEATURE_WORD, 1406 .feat_names = { 1407 "sgx-exinfo" , NULL, NULL, NULL, 1408 NULL, NULL, NULL, NULL, 1409 NULL, NULL, NULL, NULL, 1410 NULL, NULL, NULL, NULL, 1411 NULL, NULL, NULL, NULL, 1412 NULL, NULL, NULL, NULL, 1413 NULL, NULL, NULL, NULL, 1414 NULL, NULL, NULL, NULL, 1415 }, 1416 .cpuid = { 1417 .eax = 0x12, 1418 .needs_ecx = true, .ecx = 0, 1419 .reg = R_EBX, 1420 }, 1421 .tcg_features = TCG_SGX_12_0_EBX_FEATURES, 1422 }, 1423 1424 [FEAT_SGX_12_1_EAX] = { 1425 .type = CPUID_FEATURE_WORD, 1426 .feat_names = { 1427 NULL, "sgx-debug", "sgx-mode64", NULL, 1428 "sgx-provisionkey", "sgx-tokenkey", NULL, "sgx-kss", 1429 NULL, NULL, "sgx-aex-notify", NULL, 1430 NULL, NULL, NULL, NULL, 1431 NULL, NULL, NULL, NULL, 1432 NULL, NULL, NULL, NULL, 1433 NULL, NULL, NULL, NULL, 1434 NULL, NULL, NULL, NULL, 1435 }, 1436 .cpuid = { 1437 .eax = 0x12, 1438 .needs_ecx = true, .ecx = 1, 1439 .reg = R_EAX, 1440 }, 1441 .tcg_features = TCG_SGX_12_1_EAX_FEATURES, 1442 }, 1443 }; 1444 1445 typedef struct FeatureMask { 1446 FeatureWord index; 1447 uint64_t mask; 1448 } FeatureMask; 1449 1450 typedef struct FeatureDep { 1451 FeatureMask from, to; 1452 } FeatureDep; 1453 1454 static FeatureDep feature_dependencies[] = { 1455 { 1456 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_ARCH_CAPABILITIES }, 1457 .to = { FEAT_ARCH_CAPABILITIES, ~0ull }, 1458 }, 1459 { 1460 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_CORE_CAPABILITY }, 1461 .to = { FEAT_CORE_CAPABILITY, ~0ull }, 1462 }, 1463 { 1464 .from = { FEAT_1_ECX, CPUID_EXT_PDCM }, 1465 .to = { FEAT_PERF_CAPABILITIES, ~0ull }, 1466 }, 1467 { 1468 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1469 .to = { FEAT_VMX_PROCBASED_CTLS, ~0ull }, 1470 }, 1471 { 1472 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1473 .to = { FEAT_VMX_PINBASED_CTLS, ~0ull }, 1474 }, 1475 { 1476 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1477 .to = { FEAT_VMX_EXIT_CTLS, ~0ull }, 1478 }, 1479 { 1480 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1481 .to = { FEAT_VMX_ENTRY_CTLS, ~0ull }, 1482 }, 1483 { 1484 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1485 .to = { FEAT_VMX_MISC, ~0ull }, 1486 }, 1487 { 1488 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1489 .to = { FEAT_VMX_BASIC, ~0ull }, 1490 }, 1491 { 1492 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_LM }, 1493 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_IA32E_MODE }, 1494 }, 1495 { 1496 .from = { FEAT_VMX_PROCBASED_CTLS, VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS }, 1497 .to = { FEAT_VMX_SECONDARY_CTLS, ~0ull }, 1498 }, 1499 { 1500 .from = { FEAT_XSAVE, CPUID_XSAVE_XSAVES }, 1501 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_XSAVES }, 1502 }, 1503 { 1504 .from = { FEAT_1_ECX, CPUID_EXT_RDRAND }, 1505 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDRAND_EXITING }, 1506 }, 1507 { 1508 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INVPCID }, 1509 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_INVPCID }, 1510 }, 1511 { 1512 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_MPX }, 1513 .to = { FEAT_VMX_EXIT_CTLS, VMX_VM_EXIT_CLEAR_BNDCFGS }, 1514 }, 1515 { 1516 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_MPX }, 1517 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_LOAD_BNDCFGS }, 1518 }, 1519 { 1520 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_RDSEED }, 1521 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDSEED_EXITING }, 1522 }, 1523 { 1524 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT }, 1525 .to = { FEAT_14_0_ECX, ~0ull }, 1526 }, 1527 { 1528 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_RDTSCP }, 1529 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDTSCP }, 1530 }, 1531 { 1532 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT }, 1533 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull }, 1534 }, 1535 { 1536 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT }, 1537 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST }, 1538 }, 1539 { 1540 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VPID }, 1541 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull << 32 }, 1542 }, 1543 { 1544 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VMFUNC }, 1545 .to = { FEAT_VMX_VMFUNC, ~0ull }, 1546 }, 1547 { 1548 .from = { FEAT_8000_0001_ECX, CPUID_EXT3_SVM }, 1549 .to = { FEAT_SVM, ~0ull }, 1550 }, 1551 { 1552 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_USER_WAIT_PAUSE }, 1553 .to = { FEAT_7_0_ECX, CPUID_7_0_ECX_WAITPKG }, 1554 }, 1555 }; 1556 1557 typedef struct X86RegisterInfo32 { 1558 /* Name of register */ 1559 const char *name; 1560 /* QAPI enum value register */ 1561 X86CPURegister32 qapi_enum; 1562 } X86RegisterInfo32; 1563 1564 #define REGISTER(reg) \ 1565 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg } 1566 static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = { 1567 REGISTER(EAX), 1568 REGISTER(ECX), 1569 REGISTER(EDX), 1570 REGISTER(EBX), 1571 REGISTER(ESP), 1572 REGISTER(EBP), 1573 REGISTER(ESI), 1574 REGISTER(EDI), 1575 }; 1576 #undef REGISTER 1577 1578 /* CPUID feature bits available in XSS */ 1579 #define CPUID_XSTATE_XSS_MASK (XSTATE_ARCH_LBR_MASK) 1580 1581 ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUNT] = { 1582 [XSTATE_FP_BIT] = { 1583 /* x87 FP state component is always enabled if XSAVE is supported */ 1584 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE, 1585 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader), 1586 }, 1587 [XSTATE_SSE_BIT] = { 1588 /* SSE state component is always enabled if XSAVE is supported */ 1589 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE, 1590 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader), 1591 }, 1592 [XSTATE_YMM_BIT] = 1593 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX, 1594 .size = sizeof(XSaveAVX) }, 1595 [XSTATE_BNDREGS_BIT] = 1596 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX, 1597 .size = sizeof(XSaveBNDREG) }, 1598 [XSTATE_BNDCSR_BIT] = 1599 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX, 1600 .size = sizeof(XSaveBNDCSR) }, 1601 [XSTATE_OPMASK_BIT] = 1602 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1603 .size = sizeof(XSaveOpmask) }, 1604 [XSTATE_ZMM_Hi256_BIT] = 1605 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1606 .size = sizeof(XSaveZMM_Hi256) }, 1607 [XSTATE_Hi16_ZMM_BIT] = 1608 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1609 .size = sizeof(XSaveHi16_ZMM) }, 1610 [XSTATE_PKRU_BIT] = 1611 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU, 1612 .size = sizeof(XSavePKRU) }, 1613 [XSTATE_ARCH_LBR_BIT] = { 1614 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_ARCH_LBR, 1615 .offset = 0 /*supervisor mode component, offset = 0 */, 1616 .size = sizeof(XSavesArchLBR) }, 1617 [XSTATE_XTILE_CFG_BIT] = { 1618 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_AMX_TILE, 1619 .size = sizeof(XSaveXTILECFG), 1620 }, 1621 [XSTATE_XTILE_DATA_BIT] = { 1622 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_AMX_TILE, 1623 .size = sizeof(XSaveXTILEDATA) 1624 }, 1625 }; 1626 1627 uint32_t xsave_area_size(uint64_t mask, bool compacted) 1628 { 1629 uint64_t ret = x86_ext_save_areas[0].size; 1630 const ExtSaveArea *esa; 1631 uint32_t offset = 0; 1632 int i; 1633 1634 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 1635 esa = &x86_ext_save_areas[i]; 1636 if ((mask >> i) & 1) { 1637 offset = compacted ? ret : esa->offset; 1638 ret = MAX(ret, offset + esa->size); 1639 } 1640 } 1641 return ret; 1642 } 1643 1644 static inline bool accel_uses_host_cpuid(void) 1645 { 1646 return kvm_enabled() || hvf_enabled(); 1647 } 1648 1649 static inline uint64_t x86_cpu_xsave_xcr0_components(X86CPU *cpu) 1650 { 1651 return ((uint64_t)cpu->env.features[FEAT_XSAVE_XCR0_HI]) << 32 | 1652 cpu->env.features[FEAT_XSAVE_XCR0_LO]; 1653 } 1654 1655 /* Return name of 32-bit register, from a R_* constant */ 1656 static const char *get_register_name_32(unsigned int reg) 1657 { 1658 if (reg >= CPU_NB_REGS32) { 1659 return NULL; 1660 } 1661 return x86_reg_info_32[reg].name; 1662 } 1663 1664 static inline uint64_t x86_cpu_xsave_xss_components(X86CPU *cpu) 1665 { 1666 return ((uint64_t)cpu->env.features[FEAT_XSAVE_XSS_HI]) << 32 | 1667 cpu->env.features[FEAT_XSAVE_XSS_LO]; 1668 } 1669 1670 /* 1671 * Returns the set of feature flags that are supported and migratable by 1672 * QEMU, for a given FeatureWord. 1673 */ 1674 static uint64_t x86_cpu_get_migratable_flags(FeatureWord w) 1675 { 1676 FeatureWordInfo *wi = &feature_word_info[w]; 1677 uint64_t r = 0; 1678 int i; 1679 1680 for (i = 0; i < 64; i++) { 1681 uint64_t f = 1ULL << i; 1682 1683 /* If the feature name is known, it is implicitly considered migratable, 1684 * unless it is explicitly set in unmigratable_flags */ 1685 if ((wi->migratable_flags & f) || 1686 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) { 1687 r |= f; 1688 } 1689 } 1690 return r; 1691 } 1692 1693 void host_cpuid(uint32_t function, uint32_t count, 1694 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) 1695 { 1696 uint32_t vec[4]; 1697 1698 #ifdef __x86_64__ 1699 asm volatile("cpuid" 1700 : "=a"(vec[0]), "=b"(vec[1]), 1701 "=c"(vec[2]), "=d"(vec[3]) 1702 : "0"(function), "c"(count) : "cc"); 1703 #elif defined(__i386__) 1704 asm volatile("pusha \n\t" 1705 "cpuid \n\t" 1706 "mov %%eax, 0(%2) \n\t" 1707 "mov %%ebx, 4(%2) \n\t" 1708 "mov %%ecx, 8(%2) \n\t" 1709 "mov %%edx, 12(%2) \n\t" 1710 "popa" 1711 : : "a"(function), "c"(count), "S"(vec) 1712 : "memory", "cc"); 1713 #else 1714 abort(); 1715 #endif 1716 1717 if (eax) 1718 *eax = vec[0]; 1719 if (ebx) 1720 *ebx = vec[1]; 1721 if (ecx) 1722 *ecx = vec[2]; 1723 if (edx) 1724 *edx = vec[3]; 1725 } 1726 1727 /* CPU class name definitions: */ 1728 1729 /* Return type name for a given CPU model name 1730 * Caller is responsible for freeing the returned string. 1731 */ 1732 static char *x86_cpu_type_name(const char *model_name) 1733 { 1734 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name); 1735 } 1736 1737 static ObjectClass *x86_cpu_class_by_name(const char *cpu_model) 1738 { 1739 g_autofree char *typename = x86_cpu_type_name(cpu_model); 1740 return object_class_by_name(typename); 1741 } 1742 1743 static char *x86_cpu_class_get_model_name(X86CPUClass *cc) 1744 { 1745 const char *class_name = object_class_get_name(OBJECT_CLASS(cc)); 1746 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX)); 1747 return g_strndup(class_name, 1748 strlen(class_name) - strlen(X86_CPU_TYPE_SUFFIX)); 1749 } 1750 1751 typedef struct X86CPUVersionDefinition { 1752 X86CPUVersion version; 1753 const char *alias; 1754 const char *note; 1755 PropValue *props; 1756 const CPUCaches *const cache_info; 1757 } X86CPUVersionDefinition; 1758 1759 /* Base definition for a CPU model */ 1760 typedef struct X86CPUDefinition { 1761 const char *name; 1762 uint32_t level; 1763 uint32_t xlevel; 1764 /* vendor is zero-terminated, 12 character ASCII string */ 1765 char vendor[CPUID_VENDOR_SZ + 1]; 1766 int family; 1767 int model; 1768 int stepping; 1769 FeatureWordArray features; 1770 const char *model_id; 1771 const CPUCaches *const cache_info; 1772 /* 1773 * Definitions for alternative versions of CPU model. 1774 * List is terminated by item with version == 0. 1775 * If NULL, version 1 will be registered automatically. 1776 */ 1777 const X86CPUVersionDefinition *versions; 1778 const char *deprecation_note; 1779 } X86CPUDefinition; 1780 1781 /* Reference to a specific CPU model version */ 1782 struct X86CPUModel { 1783 /* Base CPU definition */ 1784 const X86CPUDefinition *cpudef; 1785 /* CPU model version */ 1786 X86CPUVersion version; 1787 const char *note; 1788 /* 1789 * If true, this is an alias CPU model. 1790 * This matters only for "-cpu help" and query-cpu-definitions 1791 */ 1792 bool is_alias; 1793 }; 1794 1795 /* Get full model name for CPU version */ 1796 static char *x86_cpu_versioned_model_name(const X86CPUDefinition *cpudef, 1797 X86CPUVersion version) 1798 { 1799 assert(version > 0); 1800 return g_strdup_printf("%s-v%d", cpudef->name, (int)version); 1801 } 1802 1803 static const X86CPUVersionDefinition * 1804 x86_cpu_def_get_versions(const X86CPUDefinition *def) 1805 { 1806 /* When X86CPUDefinition::versions is NULL, we register only v1 */ 1807 static const X86CPUVersionDefinition default_version_list[] = { 1808 { 1 }, 1809 { /* end of list */ } 1810 }; 1811 1812 return def->versions ?: default_version_list; 1813 } 1814 1815 static const CPUCaches epyc_cache_info = { 1816 .l1d_cache = &(CPUCacheInfo) { 1817 .type = DATA_CACHE, 1818 .level = 1, 1819 .size = 32 * KiB, 1820 .line_size = 64, 1821 .associativity = 8, 1822 .partitions = 1, 1823 .sets = 64, 1824 .lines_per_tag = 1, 1825 .self_init = 1, 1826 .no_invd_sharing = true, 1827 }, 1828 .l1i_cache = &(CPUCacheInfo) { 1829 .type = INSTRUCTION_CACHE, 1830 .level = 1, 1831 .size = 64 * KiB, 1832 .line_size = 64, 1833 .associativity = 4, 1834 .partitions = 1, 1835 .sets = 256, 1836 .lines_per_tag = 1, 1837 .self_init = 1, 1838 .no_invd_sharing = true, 1839 }, 1840 .l2_cache = &(CPUCacheInfo) { 1841 .type = UNIFIED_CACHE, 1842 .level = 2, 1843 .size = 512 * KiB, 1844 .line_size = 64, 1845 .associativity = 8, 1846 .partitions = 1, 1847 .sets = 1024, 1848 .lines_per_tag = 1, 1849 }, 1850 .l3_cache = &(CPUCacheInfo) { 1851 .type = UNIFIED_CACHE, 1852 .level = 3, 1853 .size = 8 * MiB, 1854 .line_size = 64, 1855 .associativity = 16, 1856 .partitions = 1, 1857 .sets = 8192, 1858 .lines_per_tag = 1, 1859 .self_init = true, 1860 .inclusive = true, 1861 .complex_indexing = true, 1862 }, 1863 }; 1864 1865 static CPUCaches epyc_v4_cache_info = { 1866 .l1d_cache = &(CPUCacheInfo) { 1867 .type = DATA_CACHE, 1868 .level = 1, 1869 .size = 32 * KiB, 1870 .line_size = 64, 1871 .associativity = 8, 1872 .partitions = 1, 1873 .sets = 64, 1874 .lines_per_tag = 1, 1875 .self_init = 1, 1876 .no_invd_sharing = true, 1877 }, 1878 .l1i_cache = &(CPUCacheInfo) { 1879 .type = INSTRUCTION_CACHE, 1880 .level = 1, 1881 .size = 64 * KiB, 1882 .line_size = 64, 1883 .associativity = 4, 1884 .partitions = 1, 1885 .sets = 256, 1886 .lines_per_tag = 1, 1887 .self_init = 1, 1888 .no_invd_sharing = true, 1889 }, 1890 .l2_cache = &(CPUCacheInfo) { 1891 .type = UNIFIED_CACHE, 1892 .level = 2, 1893 .size = 512 * KiB, 1894 .line_size = 64, 1895 .associativity = 8, 1896 .partitions = 1, 1897 .sets = 1024, 1898 .lines_per_tag = 1, 1899 }, 1900 .l3_cache = &(CPUCacheInfo) { 1901 .type = UNIFIED_CACHE, 1902 .level = 3, 1903 .size = 8 * MiB, 1904 .line_size = 64, 1905 .associativity = 16, 1906 .partitions = 1, 1907 .sets = 8192, 1908 .lines_per_tag = 1, 1909 .self_init = true, 1910 .inclusive = true, 1911 .complex_indexing = false, 1912 }, 1913 }; 1914 1915 static const CPUCaches epyc_rome_cache_info = { 1916 .l1d_cache = &(CPUCacheInfo) { 1917 .type = DATA_CACHE, 1918 .level = 1, 1919 .size = 32 * KiB, 1920 .line_size = 64, 1921 .associativity = 8, 1922 .partitions = 1, 1923 .sets = 64, 1924 .lines_per_tag = 1, 1925 .self_init = 1, 1926 .no_invd_sharing = true, 1927 }, 1928 .l1i_cache = &(CPUCacheInfo) { 1929 .type = INSTRUCTION_CACHE, 1930 .level = 1, 1931 .size = 32 * KiB, 1932 .line_size = 64, 1933 .associativity = 8, 1934 .partitions = 1, 1935 .sets = 64, 1936 .lines_per_tag = 1, 1937 .self_init = 1, 1938 .no_invd_sharing = true, 1939 }, 1940 .l2_cache = &(CPUCacheInfo) { 1941 .type = UNIFIED_CACHE, 1942 .level = 2, 1943 .size = 512 * KiB, 1944 .line_size = 64, 1945 .associativity = 8, 1946 .partitions = 1, 1947 .sets = 1024, 1948 .lines_per_tag = 1, 1949 }, 1950 .l3_cache = &(CPUCacheInfo) { 1951 .type = UNIFIED_CACHE, 1952 .level = 3, 1953 .size = 16 * MiB, 1954 .line_size = 64, 1955 .associativity = 16, 1956 .partitions = 1, 1957 .sets = 16384, 1958 .lines_per_tag = 1, 1959 .self_init = true, 1960 .inclusive = true, 1961 .complex_indexing = true, 1962 }, 1963 }; 1964 1965 static const CPUCaches epyc_rome_v3_cache_info = { 1966 .l1d_cache = &(CPUCacheInfo) { 1967 .type = DATA_CACHE, 1968 .level = 1, 1969 .size = 32 * KiB, 1970 .line_size = 64, 1971 .associativity = 8, 1972 .partitions = 1, 1973 .sets = 64, 1974 .lines_per_tag = 1, 1975 .self_init = 1, 1976 .no_invd_sharing = true, 1977 }, 1978 .l1i_cache = &(CPUCacheInfo) { 1979 .type = INSTRUCTION_CACHE, 1980 .level = 1, 1981 .size = 32 * KiB, 1982 .line_size = 64, 1983 .associativity = 8, 1984 .partitions = 1, 1985 .sets = 64, 1986 .lines_per_tag = 1, 1987 .self_init = 1, 1988 .no_invd_sharing = true, 1989 }, 1990 .l2_cache = &(CPUCacheInfo) { 1991 .type = UNIFIED_CACHE, 1992 .level = 2, 1993 .size = 512 * KiB, 1994 .line_size = 64, 1995 .associativity = 8, 1996 .partitions = 1, 1997 .sets = 1024, 1998 .lines_per_tag = 1, 1999 }, 2000 .l3_cache = &(CPUCacheInfo) { 2001 .type = UNIFIED_CACHE, 2002 .level = 3, 2003 .size = 16 * MiB, 2004 .line_size = 64, 2005 .associativity = 16, 2006 .partitions = 1, 2007 .sets = 16384, 2008 .lines_per_tag = 1, 2009 .self_init = true, 2010 .inclusive = true, 2011 .complex_indexing = false, 2012 }, 2013 }; 2014 2015 static const CPUCaches epyc_milan_cache_info = { 2016 .l1d_cache = &(CPUCacheInfo) { 2017 .type = DATA_CACHE, 2018 .level = 1, 2019 .size = 32 * KiB, 2020 .line_size = 64, 2021 .associativity = 8, 2022 .partitions = 1, 2023 .sets = 64, 2024 .lines_per_tag = 1, 2025 .self_init = 1, 2026 .no_invd_sharing = true, 2027 }, 2028 .l1i_cache = &(CPUCacheInfo) { 2029 .type = INSTRUCTION_CACHE, 2030 .level = 1, 2031 .size = 32 * KiB, 2032 .line_size = 64, 2033 .associativity = 8, 2034 .partitions = 1, 2035 .sets = 64, 2036 .lines_per_tag = 1, 2037 .self_init = 1, 2038 .no_invd_sharing = true, 2039 }, 2040 .l2_cache = &(CPUCacheInfo) { 2041 .type = UNIFIED_CACHE, 2042 .level = 2, 2043 .size = 512 * KiB, 2044 .line_size = 64, 2045 .associativity = 8, 2046 .partitions = 1, 2047 .sets = 1024, 2048 .lines_per_tag = 1, 2049 }, 2050 .l3_cache = &(CPUCacheInfo) { 2051 .type = UNIFIED_CACHE, 2052 .level = 3, 2053 .size = 32 * MiB, 2054 .line_size = 64, 2055 .associativity = 16, 2056 .partitions = 1, 2057 .sets = 32768, 2058 .lines_per_tag = 1, 2059 .self_init = true, 2060 .inclusive = true, 2061 .complex_indexing = true, 2062 }, 2063 }; 2064 2065 static const CPUCaches epyc_milan_v2_cache_info = { 2066 .l1d_cache = &(CPUCacheInfo) { 2067 .type = DATA_CACHE, 2068 .level = 1, 2069 .size = 32 * KiB, 2070 .line_size = 64, 2071 .associativity = 8, 2072 .partitions = 1, 2073 .sets = 64, 2074 .lines_per_tag = 1, 2075 .self_init = 1, 2076 .no_invd_sharing = true, 2077 }, 2078 .l1i_cache = &(CPUCacheInfo) { 2079 .type = INSTRUCTION_CACHE, 2080 .level = 1, 2081 .size = 32 * KiB, 2082 .line_size = 64, 2083 .associativity = 8, 2084 .partitions = 1, 2085 .sets = 64, 2086 .lines_per_tag = 1, 2087 .self_init = 1, 2088 .no_invd_sharing = true, 2089 }, 2090 .l2_cache = &(CPUCacheInfo) { 2091 .type = UNIFIED_CACHE, 2092 .level = 2, 2093 .size = 512 * KiB, 2094 .line_size = 64, 2095 .associativity = 8, 2096 .partitions = 1, 2097 .sets = 1024, 2098 .lines_per_tag = 1, 2099 }, 2100 .l3_cache = &(CPUCacheInfo) { 2101 .type = UNIFIED_CACHE, 2102 .level = 3, 2103 .size = 32 * MiB, 2104 .line_size = 64, 2105 .associativity = 16, 2106 .partitions = 1, 2107 .sets = 32768, 2108 .lines_per_tag = 1, 2109 .self_init = true, 2110 .inclusive = true, 2111 .complex_indexing = false, 2112 }, 2113 }; 2114 2115 static const CPUCaches epyc_genoa_cache_info = { 2116 .l1d_cache = &(CPUCacheInfo) { 2117 .type = DATA_CACHE, 2118 .level = 1, 2119 .size = 32 * KiB, 2120 .line_size = 64, 2121 .associativity = 8, 2122 .partitions = 1, 2123 .sets = 64, 2124 .lines_per_tag = 1, 2125 .self_init = 1, 2126 .no_invd_sharing = true, 2127 }, 2128 .l1i_cache = &(CPUCacheInfo) { 2129 .type = INSTRUCTION_CACHE, 2130 .level = 1, 2131 .size = 32 * KiB, 2132 .line_size = 64, 2133 .associativity = 8, 2134 .partitions = 1, 2135 .sets = 64, 2136 .lines_per_tag = 1, 2137 .self_init = 1, 2138 .no_invd_sharing = true, 2139 }, 2140 .l2_cache = &(CPUCacheInfo) { 2141 .type = UNIFIED_CACHE, 2142 .level = 2, 2143 .size = 1 * MiB, 2144 .line_size = 64, 2145 .associativity = 8, 2146 .partitions = 1, 2147 .sets = 2048, 2148 .lines_per_tag = 1, 2149 }, 2150 .l3_cache = &(CPUCacheInfo) { 2151 .type = UNIFIED_CACHE, 2152 .level = 3, 2153 .size = 32 * MiB, 2154 .line_size = 64, 2155 .associativity = 16, 2156 .partitions = 1, 2157 .sets = 32768, 2158 .lines_per_tag = 1, 2159 .self_init = true, 2160 .inclusive = true, 2161 .complex_indexing = false, 2162 }, 2163 }; 2164 2165 /* The following VMX features are not supported by KVM and are left out in the 2166 * CPU definitions: 2167 * 2168 * Dual-monitor support (all processors) 2169 * Entry to SMM 2170 * Deactivate dual-monitor treatment 2171 * Number of CR3-target values 2172 * Shutdown activity state 2173 * Wait-for-SIPI activity state 2174 * PAUSE-loop exiting (Westmere and newer) 2175 * EPT-violation #VE (Broadwell and newer) 2176 * Inject event with insn length=0 (Skylake and newer) 2177 * Conceal non-root operation from PT 2178 * Conceal VM exits from PT 2179 * Conceal VM entries from PT 2180 * Enable ENCLS exiting 2181 * Mode-based execute control (XS/XU) 2182 s TSC scaling (Skylake Server and newer) 2183 * GPA translation for PT (IceLake and newer) 2184 * User wait and pause 2185 * ENCLV exiting 2186 * Load IA32_RTIT_CTL 2187 * Clear IA32_RTIT_CTL 2188 * Advanced VM-exit information for EPT violations 2189 * Sub-page write permissions 2190 * PT in VMX operation 2191 */ 2192 2193 static const X86CPUDefinition builtin_x86_defs[] = { 2194 { 2195 .name = "qemu64", 2196 .level = 0xd, 2197 .vendor = CPUID_VENDOR_AMD, 2198 .family = 15, 2199 .model = 107, 2200 .stepping = 1, 2201 .features[FEAT_1_EDX] = 2202 PPRO_FEATURES | 2203 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2204 CPUID_PSE36, 2205 .features[FEAT_1_ECX] = 2206 CPUID_EXT_SSE3 | CPUID_EXT_CX16, 2207 .features[FEAT_8000_0001_EDX] = 2208 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2209 .features[FEAT_8000_0001_ECX] = 2210 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM, 2211 .xlevel = 0x8000000A, 2212 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 2213 }, 2214 { 2215 .name = "phenom", 2216 .level = 5, 2217 .vendor = CPUID_VENDOR_AMD, 2218 .family = 16, 2219 .model = 2, 2220 .stepping = 3, 2221 /* Missing: CPUID_HT */ 2222 .features[FEAT_1_EDX] = 2223 PPRO_FEATURES | 2224 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2225 CPUID_PSE36 | CPUID_VME, 2226 .features[FEAT_1_ECX] = 2227 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 | 2228 CPUID_EXT_POPCNT, 2229 .features[FEAT_8000_0001_EDX] = 2230 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | 2231 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT | 2232 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP, 2233 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, 2234 CPUID_EXT3_CR8LEG, 2235 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, 2236 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */ 2237 .features[FEAT_8000_0001_ECX] = 2238 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | 2239 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A, 2240 /* Missing: CPUID_SVM_LBRV */ 2241 .features[FEAT_SVM] = 2242 CPUID_SVM_NPT, 2243 .xlevel = 0x8000001A, 2244 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor" 2245 }, 2246 { 2247 .name = "core2duo", 2248 .level = 10, 2249 .vendor = CPUID_VENDOR_INTEL, 2250 .family = 6, 2251 .model = 15, 2252 .stepping = 11, 2253 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2254 .features[FEAT_1_EDX] = 2255 PPRO_FEATURES | 2256 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2257 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS, 2258 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST, 2259 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */ 2260 .features[FEAT_1_ECX] = 2261 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | 2262 CPUID_EXT_CX16, 2263 .features[FEAT_8000_0001_EDX] = 2264 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2265 .features[FEAT_8000_0001_ECX] = 2266 CPUID_EXT3_LAHF_LM, 2267 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2268 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2269 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2270 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2271 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2272 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2273 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2274 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2275 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2276 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2277 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2278 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2279 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2280 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2281 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2282 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2283 .features[FEAT_VMX_SECONDARY_CTLS] = 2284 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES, 2285 .xlevel = 0x80000008, 2286 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz", 2287 }, 2288 { 2289 .name = "kvm64", 2290 .level = 0xd, 2291 .vendor = CPUID_VENDOR_INTEL, 2292 .family = 15, 2293 .model = 6, 2294 .stepping = 1, 2295 /* Missing: CPUID_HT */ 2296 .features[FEAT_1_EDX] = 2297 PPRO_FEATURES | CPUID_VME | 2298 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2299 CPUID_PSE36, 2300 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */ 2301 .features[FEAT_1_ECX] = 2302 CPUID_EXT_SSE3 | CPUID_EXT_CX16, 2303 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */ 2304 .features[FEAT_8000_0001_EDX] = 2305 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2306 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, 2307 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A, 2308 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, 2309 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */ 2310 .features[FEAT_8000_0001_ECX] = 2311 0, 2312 /* VMX features from Cedar Mill/Prescott */ 2313 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2314 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2315 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2316 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2317 VMX_PIN_BASED_NMI_EXITING, 2318 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2319 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2320 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2321 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2322 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2323 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2324 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2325 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING, 2326 .xlevel = 0x80000008, 2327 .model_id = "Common KVM processor" 2328 }, 2329 { 2330 .name = "qemu32", 2331 .level = 4, 2332 .vendor = CPUID_VENDOR_INTEL, 2333 .family = 6, 2334 .model = 6, 2335 .stepping = 3, 2336 .features[FEAT_1_EDX] = 2337 PPRO_FEATURES, 2338 .features[FEAT_1_ECX] = 2339 CPUID_EXT_SSE3, 2340 .xlevel = 0x80000004, 2341 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 2342 }, 2343 { 2344 .name = "kvm32", 2345 .level = 5, 2346 .vendor = CPUID_VENDOR_INTEL, 2347 .family = 15, 2348 .model = 6, 2349 .stepping = 1, 2350 .features[FEAT_1_EDX] = 2351 PPRO_FEATURES | CPUID_VME | 2352 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36, 2353 .features[FEAT_1_ECX] = 2354 CPUID_EXT_SSE3, 2355 .features[FEAT_8000_0001_ECX] = 2356 0, 2357 /* VMX features from Yonah */ 2358 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2359 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2360 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2361 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2362 VMX_PIN_BASED_NMI_EXITING, 2363 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2364 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2365 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2366 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2367 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 2368 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 2369 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS, 2370 .xlevel = 0x80000008, 2371 .model_id = "Common 32-bit KVM processor" 2372 }, 2373 { 2374 .name = "coreduo", 2375 .level = 10, 2376 .vendor = CPUID_VENDOR_INTEL, 2377 .family = 6, 2378 .model = 14, 2379 .stepping = 8, 2380 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2381 .features[FEAT_1_EDX] = 2382 PPRO_FEATURES | CPUID_VME | 2383 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI | 2384 CPUID_SS, 2385 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR, 2386 * CPUID_EXT_PDCM, CPUID_EXT_VMX */ 2387 .features[FEAT_1_ECX] = 2388 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR, 2389 .features[FEAT_8000_0001_EDX] = 2390 CPUID_EXT2_NX, 2391 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2392 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2393 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2394 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2395 VMX_PIN_BASED_NMI_EXITING, 2396 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2397 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2398 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2399 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2400 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 2401 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 2402 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS, 2403 .xlevel = 0x80000008, 2404 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz", 2405 }, 2406 { 2407 .name = "486", 2408 .level = 1, 2409 .vendor = CPUID_VENDOR_INTEL, 2410 .family = 4, 2411 .model = 8, 2412 .stepping = 0, 2413 .features[FEAT_1_EDX] = 2414 I486_FEATURES, 2415 .xlevel = 0, 2416 .model_id = "", 2417 }, 2418 { 2419 .name = "pentium", 2420 .level = 1, 2421 .vendor = CPUID_VENDOR_INTEL, 2422 .family = 5, 2423 .model = 4, 2424 .stepping = 3, 2425 .features[FEAT_1_EDX] = 2426 PENTIUM_FEATURES, 2427 .xlevel = 0, 2428 .model_id = "", 2429 }, 2430 { 2431 .name = "pentium2", 2432 .level = 2, 2433 .vendor = CPUID_VENDOR_INTEL, 2434 .family = 6, 2435 .model = 5, 2436 .stepping = 2, 2437 .features[FEAT_1_EDX] = 2438 PENTIUM2_FEATURES, 2439 .xlevel = 0, 2440 .model_id = "", 2441 }, 2442 { 2443 .name = "pentium3", 2444 .level = 3, 2445 .vendor = CPUID_VENDOR_INTEL, 2446 .family = 6, 2447 .model = 7, 2448 .stepping = 3, 2449 .features[FEAT_1_EDX] = 2450 PENTIUM3_FEATURES, 2451 .xlevel = 0, 2452 .model_id = "", 2453 }, 2454 { 2455 .name = "athlon", 2456 .level = 2, 2457 .vendor = CPUID_VENDOR_AMD, 2458 .family = 6, 2459 .model = 2, 2460 .stepping = 3, 2461 .features[FEAT_1_EDX] = 2462 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR | 2463 CPUID_MCA, 2464 .features[FEAT_8000_0001_EDX] = 2465 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT, 2466 .xlevel = 0x80000008, 2467 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 2468 }, 2469 { 2470 .name = "n270", 2471 .level = 10, 2472 .vendor = CPUID_VENDOR_INTEL, 2473 .family = 6, 2474 .model = 28, 2475 .stepping = 2, 2476 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2477 .features[FEAT_1_EDX] = 2478 PPRO_FEATURES | 2479 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | 2480 CPUID_ACPI | CPUID_SS, 2481 /* Some CPUs got no CPUID_SEP */ 2482 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2, 2483 * CPUID_EXT_XTPR */ 2484 .features[FEAT_1_ECX] = 2485 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | 2486 CPUID_EXT_MOVBE, 2487 .features[FEAT_8000_0001_EDX] = 2488 CPUID_EXT2_NX, 2489 .features[FEAT_8000_0001_ECX] = 2490 CPUID_EXT3_LAHF_LM, 2491 .xlevel = 0x80000008, 2492 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz", 2493 }, 2494 { 2495 .name = "Conroe", 2496 .level = 10, 2497 .vendor = CPUID_VENDOR_INTEL, 2498 .family = 6, 2499 .model = 15, 2500 .stepping = 3, 2501 .features[FEAT_1_EDX] = 2502 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2503 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2504 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2505 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2506 CPUID_DE | CPUID_FP87, 2507 .features[FEAT_1_ECX] = 2508 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, 2509 .features[FEAT_8000_0001_EDX] = 2510 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 2511 .features[FEAT_8000_0001_ECX] = 2512 CPUID_EXT3_LAHF_LM, 2513 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2514 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2515 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2516 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2517 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2518 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2519 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2520 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2521 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2522 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2523 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2524 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2525 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2526 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2527 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2528 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2529 .features[FEAT_VMX_SECONDARY_CTLS] = 2530 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES, 2531 .xlevel = 0x80000008, 2532 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)", 2533 }, 2534 { 2535 .name = "Penryn", 2536 .level = 10, 2537 .vendor = CPUID_VENDOR_INTEL, 2538 .family = 6, 2539 .model = 23, 2540 .stepping = 3, 2541 .features[FEAT_1_EDX] = 2542 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2543 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2544 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2545 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2546 CPUID_DE | CPUID_FP87, 2547 .features[FEAT_1_ECX] = 2548 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2549 CPUID_EXT_SSE3, 2550 .features[FEAT_8000_0001_EDX] = 2551 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 2552 .features[FEAT_8000_0001_ECX] = 2553 CPUID_EXT3_LAHF_LM, 2554 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2555 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2556 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, 2557 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT | 2558 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL, 2559 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2560 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2561 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2562 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2563 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2564 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2565 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2566 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2567 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2568 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2569 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2570 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2571 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2572 .features[FEAT_VMX_SECONDARY_CTLS] = 2573 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2574 VMX_SECONDARY_EXEC_WBINVD_EXITING, 2575 .xlevel = 0x80000008, 2576 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)", 2577 }, 2578 { 2579 .name = "Nehalem", 2580 .level = 11, 2581 .vendor = CPUID_VENDOR_INTEL, 2582 .family = 6, 2583 .model = 26, 2584 .stepping = 3, 2585 .features[FEAT_1_EDX] = 2586 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2587 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2588 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2589 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2590 CPUID_DE | CPUID_FP87, 2591 .features[FEAT_1_ECX] = 2592 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 2593 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, 2594 .features[FEAT_8000_0001_EDX] = 2595 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2596 .features[FEAT_8000_0001_ECX] = 2597 CPUID_EXT3_LAHF_LM, 2598 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2599 MSR_VMX_BASIC_TRUE_CTLS, 2600 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2601 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2602 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2603 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2604 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2605 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2606 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2607 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2608 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2609 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2610 .features[FEAT_VMX_EXIT_CTLS] = 2611 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2612 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2613 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2614 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2615 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2616 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2617 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2618 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2619 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2620 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2621 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2622 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2623 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2624 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2625 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2626 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2627 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2628 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2629 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2630 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2631 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2632 .features[FEAT_VMX_SECONDARY_CTLS] = 2633 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2634 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2635 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2636 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2637 VMX_SECONDARY_EXEC_ENABLE_VPID, 2638 .xlevel = 0x80000008, 2639 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)", 2640 .versions = (X86CPUVersionDefinition[]) { 2641 { .version = 1 }, 2642 { 2643 .version = 2, 2644 .alias = "Nehalem-IBRS", 2645 .props = (PropValue[]) { 2646 { "spec-ctrl", "on" }, 2647 { "model-id", 2648 "Intel Core i7 9xx (Nehalem Core i7, IBRS update)" }, 2649 { /* end of list */ } 2650 } 2651 }, 2652 { /* end of list */ } 2653 } 2654 }, 2655 { 2656 .name = "Westmere", 2657 .level = 11, 2658 .vendor = CPUID_VENDOR_INTEL, 2659 .family = 6, 2660 .model = 44, 2661 .stepping = 1, 2662 .features[FEAT_1_EDX] = 2663 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2664 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2665 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2666 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2667 CPUID_DE | CPUID_FP87, 2668 .features[FEAT_1_ECX] = 2669 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | 2670 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2671 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 2672 .features[FEAT_8000_0001_EDX] = 2673 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2674 .features[FEAT_8000_0001_ECX] = 2675 CPUID_EXT3_LAHF_LM, 2676 .features[FEAT_6_EAX] = 2677 CPUID_6_EAX_ARAT, 2678 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2679 MSR_VMX_BASIC_TRUE_CTLS, 2680 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2681 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2682 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2683 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2684 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2685 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2686 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2687 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2688 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2689 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2690 .features[FEAT_VMX_EXIT_CTLS] = 2691 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2692 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2693 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2694 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2695 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2696 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2697 MSR_VMX_MISC_STORE_LMA, 2698 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2699 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2700 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2701 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2702 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2703 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2704 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2705 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2706 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2707 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2708 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2709 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2710 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2711 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2712 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2713 .features[FEAT_VMX_SECONDARY_CTLS] = 2714 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2715 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2716 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2717 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2718 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST, 2719 .xlevel = 0x80000008, 2720 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)", 2721 .versions = (X86CPUVersionDefinition[]) { 2722 { .version = 1 }, 2723 { 2724 .version = 2, 2725 .alias = "Westmere-IBRS", 2726 .props = (PropValue[]) { 2727 { "spec-ctrl", "on" }, 2728 { "model-id", 2729 "Westmere E56xx/L56xx/X56xx (IBRS update)" }, 2730 { /* end of list */ } 2731 } 2732 }, 2733 { /* end of list */ } 2734 } 2735 }, 2736 { 2737 .name = "SandyBridge", 2738 .level = 0xd, 2739 .vendor = CPUID_VENDOR_INTEL, 2740 .family = 6, 2741 .model = 42, 2742 .stepping = 1, 2743 .features[FEAT_1_EDX] = 2744 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2745 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2746 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2747 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2748 CPUID_DE | CPUID_FP87, 2749 .features[FEAT_1_ECX] = 2750 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2751 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | 2752 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 2753 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 2754 CPUID_EXT_SSE3, 2755 .features[FEAT_8000_0001_EDX] = 2756 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 2757 CPUID_EXT2_SYSCALL, 2758 .features[FEAT_8000_0001_ECX] = 2759 CPUID_EXT3_LAHF_LM, 2760 .features[FEAT_XSAVE] = 2761 CPUID_XSAVE_XSAVEOPT, 2762 .features[FEAT_6_EAX] = 2763 CPUID_6_EAX_ARAT, 2764 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2765 MSR_VMX_BASIC_TRUE_CTLS, 2766 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2767 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2768 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2769 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2770 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2771 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2772 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2773 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2774 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2775 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2776 .features[FEAT_VMX_EXIT_CTLS] = 2777 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2778 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2779 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2780 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2781 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2782 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2783 MSR_VMX_MISC_STORE_LMA, 2784 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2785 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2786 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2787 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2788 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2789 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2790 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2791 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2792 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2793 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2794 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2795 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2796 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2797 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2798 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2799 .features[FEAT_VMX_SECONDARY_CTLS] = 2800 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2801 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2802 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2803 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2804 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST, 2805 .xlevel = 0x80000008, 2806 .model_id = "Intel Xeon E312xx (Sandy Bridge)", 2807 .versions = (X86CPUVersionDefinition[]) { 2808 { .version = 1 }, 2809 { 2810 .version = 2, 2811 .alias = "SandyBridge-IBRS", 2812 .props = (PropValue[]) { 2813 { "spec-ctrl", "on" }, 2814 { "model-id", 2815 "Intel Xeon E312xx (Sandy Bridge, IBRS update)" }, 2816 { /* end of list */ } 2817 } 2818 }, 2819 { /* end of list */ } 2820 } 2821 }, 2822 { 2823 .name = "IvyBridge", 2824 .level = 0xd, 2825 .vendor = CPUID_VENDOR_INTEL, 2826 .family = 6, 2827 .model = 58, 2828 .stepping = 9, 2829 .features[FEAT_1_EDX] = 2830 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2831 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2832 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2833 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2834 CPUID_DE | CPUID_FP87, 2835 .features[FEAT_1_ECX] = 2836 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2837 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | 2838 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 2839 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 2840 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 2841 .features[FEAT_7_0_EBX] = 2842 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | 2843 CPUID_7_0_EBX_ERMS, 2844 .features[FEAT_8000_0001_EDX] = 2845 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 2846 CPUID_EXT2_SYSCALL, 2847 .features[FEAT_8000_0001_ECX] = 2848 CPUID_EXT3_LAHF_LM, 2849 .features[FEAT_XSAVE] = 2850 CPUID_XSAVE_XSAVEOPT, 2851 .features[FEAT_6_EAX] = 2852 CPUID_6_EAX_ARAT, 2853 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2854 MSR_VMX_BASIC_TRUE_CTLS, 2855 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2856 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2857 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2858 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2859 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2860 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2861 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2862 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2863 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2864 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2865 .features[FEAT_VMX_EXIT_CTLS] = 2866 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2867 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2868 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2869 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2870 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2871 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2872 MSR_VMX_MISC_STORE_LMA, 2873 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2874 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2875 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 2876 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2877 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2878 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2879 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2880 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2881 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2882 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2883 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2884 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2885 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2886 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2887 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2888 .features[FEAT_VMX_SECONDARY_CTLS] = 2889 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2890 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2891 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2892 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2893 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 2894 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 2895 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 2896 VMX_SECONDARY_EXEC_RDRAND_EXITING, 2897 .xlevel = 0x80000008, 2898 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)", 2899 .versions = (X86CPUVersionDefinition[]) { 2900 { .version = 1 }, 2901 { 2902 .version = 2, 2903 .alias = "IvyBridge-IBRS", 2904 .props = (PropValue[]) { 2905 { "spec-ctrl", "on" }, 2906 { "model-id", 2907 "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)" }, 2908 { /* end of list */ } 2909 } 2910 }, 2911 { /* end of list */ } 2912 } 2913 }, 2914 { 2915 .name = "Haswell", 2916 .level = 0xd, 2917 .vendor = CPUID_VENDOR_INTEL, 2918 .family = 6, 2919 .model = 60, 2920 .stepping = 4, 2921 .features[FEAT_1_EDX] = 2922 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2923 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2924 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2925 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2926 CPUID_DE | CPUID_FP87, 2927 .features[FEAT_1_ECX] = 2928 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2929 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 2930 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2931 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 2932 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 2933 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 2934 .features[FEAT_8000_0001_EDX] = 2935 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 2936 CPUID_EXT2_SYSCALL, 2937 .features[FEAT_8000_0001_ECX] = 2938 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM, 2939 .features[FEAT_7_0_EBX] = 2940 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 2941 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 2942 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 2943 CPUID_7_0_EBX_RTM, 2944 .features[FEAT_XSAVE] = 2945 CPUID_XSAVE_XSAVEOPT, 2946 .features[FEAT_6_EAX] = 2947 CPUID_6_EAX_ARAT, 2948 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2949 MSR_VMX_BASIC_TRUE_CTLS, 2950 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2951 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2952 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2953 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2954 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2955 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2956 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2957 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2958 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2959 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 2960 .features[FEAT_VMX_EXIT_CTLS] = 2961 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2962 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2963 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2964 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2965 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2966 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2967 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 2968 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2969 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2970 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 2971 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2972 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2973 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2974 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2975 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2976 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2977 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2978 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2979 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2980 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2981 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2982 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2983 .features[FEAT_VMX_SECONDARY_CTLS] = 2984 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2985 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2986 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2987 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2988 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 2989 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 2990 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 2991 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 2992 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS, 2993 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 2994 .xlevel = 0x80000008, 2995 .model_id = "Intel Core Processor (Haswell)", 2996 .versions = (X86CPUVersionDefinition[]) { 2997 { .version = 1 }, 2998 { 2999 .version = 2, 3000 .alias = "Haswell-noTSX", 3001 .props = (PropValue[]) { 3002 { "hle", "off" }, 3003 { "rtm", "off" }, 3004 { "stepping", "1" }, 3005 { "model-id", "Intel Core Processor (Haswell, no TSX)", }, 3006 { /* end of list */ } 3007 }, 3008 }, 3009 { 3010 .version = 3, 3011 .alias = "Haswell-IBRS", 3012 .props = (PropValue[]) { 3013 /* Restore TSX features removed by -v2 above */ 3014 { "hle", "on" }, 3015 { "rtm", "on" }, 3016 /* 3017 * Haswell and Haswell-IBRS had stepping=4 in 3018 * QEMU 4.0 and older 3019 */ 3020 { "stepping", "4" }, 3021 { "spec-ctrl", "on" }, 3022 { "model-id", 3023 "Intel Core Processor (Haswell, IBRS)" }, 3024 { /* end of list */ } 3025 } 3026 }, 3027 { 3028 .version = 4, 3029 .alias = "Haswell-noTSX-IBRS", 3030 .props = (PropValue[]) { 3031 { "hle", "off" }, 3032 { "rtm", "off" }, 3033 /* spec-ctrl was already enabled by -v3 above */ 3034 { "stepping", "1" }, 3035 { "model-id", 3036 "Intel Core Processor (Haswell, no TSX, IBRS)" }, 3037 { /* end of list */ } 3038 } 3039 }, 3040 { /* end of list */ } 3041 } 3042 }, 3043 { 3044 .name = "Broadwell", 3045 .level = 0xd, 3046 .vendor = CPUID_VENDOR_INTEL, 3047 .family = 6, 3048 .model = 61, 3049 .stepping = 2, 3050 .features[FEAT_1_EDX] = 3051 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3052 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3053 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3054 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3055 CPUID_DE | CPUID_FP87, 3056 .features[FEAT_1_ECX] = 3057 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3058 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3059 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3060 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3061 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3062 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3063 .features[FEAT_8000_0001_EDX] = 3064 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3065 CPUID_EXT2_SYSCALL, 3066 .features[FEAT_8000_0001_ECX] = 3067 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3068 .features[FEAT_7_0_EBX] = 3069 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3070 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3071 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3072 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3073 CPUID_7_0_EBX_SMAP, 3074 .features[FEAT_XSAVE] = 3075 CPUID_XSAVE_XSAVEOPT, 3076 .features[FEAT_6_EAX] = 3077 CPUID_6_EAX_ARAT, 3078 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3079 MSR_VMX_BASIC_TRUE_CTLS, 3080 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3081 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3082 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3083 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3084 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3085 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3086 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3087 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3088 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3089 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3090 .features[FEAT_VMX_EXIT_CTLS] = 3091 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3092 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3093 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3094 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3095 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3096 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3097 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3098 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3099 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3100 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3101 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3102 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3103 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3104 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3105 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3106 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3107 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3108 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3109 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3110 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3111 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3112 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3113 .features[FEAT_VMX_SECONDARY_CTLS] = 3114 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3115 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3116 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3117 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3118 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3119 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3120 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3121 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3122 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3123 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3124 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3125 .xlevel = 0x80000008, 3126 .model_id = "Intel Core Processor (Broadwell)", 3127 .versions = (X86CPUVersionDefinition[]) { 3128 { .version = 1 }, 3129 { 3130 .version = 2, 3131 .alias = "Broadwell-noTSX", 3132 .props = (PropValue[]) { 3133 { "hle", "off" }, 3134 { "rtm", "off" }, 3135 { "model-id", "Intel Core Processor (Broadwell, no TSX)", }, 3136 { /* end of list */ } 3137 }, 3138 }, 3139 { 3140 .version = 3, 3141 .alias = "Broadwell-IBRS", 3142 .props = (PropValue[]) { 3143 /* Restore TSX features removed by -v2 above */ 3144 { "hle", "on" }, 3145 { "rtm", "on" }, 3146 { "spec-ctrl", "on" }, 3147 { "model-id", 3148 "Intel Core Processor (Broadwell, IBRS)" }, 3149 { /* end of list */ } 3150 } 3151 }, 3152 { 3153 .version = 4, 3154 .alias = "Broadwell-noTSX-IBRS", 3155 .props = (PropValue[]) { 3156 { "hle", "off" }, 3157 { "rtm", "off" }, 3158 /* spec-ctrl was already enabled by -v3 above */ 3159 { "model-id", 3160 "Intel Core Processor (Broadwell, no TSX, IBRS)" }, 3161 { /* end of list */ } 3162 } 3163 }, 3164 { /* end of list */ } 3165 } 3166 }, 3167 { 3168 .name = "Skylake-Client", 3169 .level = 0xd, 3170 .vendor = CPUID_VENDOR_INTEL, 3171 .family = 6, 3172 .model = 94, 3173 .stepping = 3, 3174 .features[FEAT_1_EDX] = 3175 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3176 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3177 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3178 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3179 CPUID_DE | CPUID_FP87, 3180 .features[FEAT_1_ECX] = 3181 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3182 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3183 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3184 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3185 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3186 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3187 .features[FEAT_8000_0001_EDX] = 3188 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3189 CPUID_EXT2_SYSCALL, 3190 .features[FEAT_8000_0001_ECX] = 3191 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3192 .features[FEAT_7_0_EBX] = 3193 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3194 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3195 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3196 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3197 CPUID_7_0_EBX_SMAP, 3198 /* XSAVES is added in version 4 */ 3199 .features[FEAT_XSAVE] = 3200 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3201 CPUID_XSAVE_XGETBV1, 3202 .features[FEAT_6_EAX] = 3203 CPUID_6_EAX_ARAT, 3204 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3205 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3206 MSR_VMX_BASIC_TRUE_CTLS, 3207 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3208 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3209 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3210 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3211 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3212 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3213 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3214 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3215 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3216 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3217 .features[FEAT_VMX_EXIT_CTLS] = 3218 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3219 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3220 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3221 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3222 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3223 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3224 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3225 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3226 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3227 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 3228 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3229 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3230 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3231 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3232 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3233 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3234 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3235 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3236 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3237 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3238 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3239 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3240 .features[FEAT_VMX_SECONDARY_CTLS] = 3241 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3242 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3243 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3244 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3245 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3246 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3247 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3248 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3249 .xlevel = 0x80000008, 3250 .model_id = "Intel Core Processor (Skylake)", 3251 .versions = (X86CPUVersionDefinition[]) { 3252 { .version = 1 }, 3253 { 3254 .version = 2, 3255 .alias = "Skylake-Client-IBRS", 3256 .props = (PropValue[]) { 3257 { "spec-ctrl", "on" }, 3258 { "model-id", 3259 "Intel Core Processor (Skylake, IBRS)" }, 3260 { /* end of list */ } 3261 } 3262 }, 3263 { 3264 .version = 3, 3265 .alias = "Skylake-Client-noTSX-IBRS", 3266 .props = (PropValue[]) { 3267 { "hle", "off" }, 3268 { "rtm", "off" }, 3269 { "model-id", 3270 "Intel Core Processor (Skylake, IBRS, no TSX)" }, 3271 { /* end of list */ } 3272 } 3273 }, 3274 { 3275 .version = 4, 3276 .note = "IBRS, XSAVES, no TSX", 3277 .props = (PropValue[]) { 3278 { "xsaves", "on" }, 3279 { "vmx-xsaves", "on" }, 3280 { /* end of list */ } 3281 } 3282 }, 3283 { /* end of list */ } 3284 } 3285 }, 3286 { 3287 .name = "Skylake-Server", 3288 .level = 0xd, 3289 .vendor = CPUID_VENDOR_INTEL, 3290 .family = 6, 3291 .model = 85, 3292 .stepping = 4, 3293 .features[FEAT_1_EDX] = 3294 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3295 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3296 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3297 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3298 CPUID_DE | CPUID_FP87, 3299 .features[FEAT_1_ECX] = 3300 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3301 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3302 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3303 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3304 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3305 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3306 .features[FEAT_8000_0001_EDX] = 3307 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3308 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3309 .features[FEAT_8000_0001_ECX] = 3310 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3311 .features[FEAT_7_0_EBX] = 3312 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3313 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3314 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3315 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3316 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3317 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3318 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3319 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3320 .features[FEAT_7_0_ECX] = 3321 CPUID_7_0_ECX_PKU, 3322 /* XSAVES is added in version 5 */ 3323 .features[FEAT_XSAVE] = 3324 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3325 CPUID_XSAVE_XGETBV1, 3326 .features[FEAT_6_EAX] = 3327 CPUID_6_EAX_ARAT, 3328 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3329 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3330 MSR_VMX_BASIC_TRUE_CTLS, 3331 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3332 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3333 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3334 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3335 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3336 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3337 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3338 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3339 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3340 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3341 .features[FEAT_VMX_EXIT_CTLS] = 3342 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3343 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3344 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3345 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3346 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3347 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3348 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3349 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3350 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3351 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3352 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3353 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3354 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3355 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3356 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3357 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3358 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3359 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3360 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3361 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3362 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3363 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3364 .features[FEAT_VMX_SECONDARY_CTLS] = 3365 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3366 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3367 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3368 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3369 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3370 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3371 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3372 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3373 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3374 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3375 .xlevel = 0x80000008, 3376 .model_id = "Intel Xeon Processor (Skylake)", 3377 .versions = (X86CPUVersionDefinition[]) { 3378 { .version = 1 }, 3379 { 3380 .version = 2, 3381 .alias = "Skylake-Server-IBRS", 3382 .props = (PropValue[]) { 3383 /* clflushopt was not added to Skylake-Server-IBRS */ 3384 /* TODO: add -v3 including clflushopt */ 3385 { "clflushopt", "off" }, 3386 { "spec-ctrl", "on" }, 3387 { "model-id", 3388 "Intel Xeon Processor (Skylake, IBRS)" }, 3389 { /* end of list */ } 3390 } 3391 }, 3392 { 3393 .version = 3, 3394 .alias = "Skylake-Server-noTSX-IBRS", 3395 .props = (PropValue[]) { 3396 { "hle", "off" }, 3397 { "rtm", "off" }, 3398 { "model-id", 3399 "Intel Xeon Processor (Skylake, IBRS, no TSX)" }, 3400 { /* end of list */ } 3401 } 3402 }, 3403 { 3404 .version = 4, 3405 .props = (PropValue[]) { 3406 { "vmx-eptp-switching", "on" }, 3407 { /* end of list */ } 3408 } 3409 }, 3410 { 3411 .version = 5, 3412 .note = "IBRS, XSAVES, EPT switching, no TSX", 3413 .props = (PropValue[]) { 3414 { "xsaves", "on" }, 3415 { "vmx-xsaves", "on" }, 3416 { /* end of list */ } 3417 } 3418 }, 3419 { /* end of list */ } 3420 } 3421 }, 3422 { 3423 .name = "Cascadelake-Server", 3424 .level = 0xd, 3425 .vendor = CPUID_VENDOR_INTEL, 3426 .family = 6, 3427 .model = 85, 3428 .stepping = 6, 3429 .features[FEAT_1_EDX] = 3430 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3431 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3432 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3433 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3434 CPUID_DE | CPUID_FP87, 3435 .features[FEAT_1_ECX] = 3436 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3437 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3438 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3439 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3440 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3441 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3442 .features[FEAT_8000_0001_EDX] = 3443 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3444 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3445 .features[FEAT_8000_0001_ECX] = 3446 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3447 .features[FEAT_7_0_EBX] = 3448 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3449 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3450 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3451 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3452 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3453 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3454 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3455 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3456 .features[FEAT_7_0_ECX] = 3457 CPUID_7_0_ECX_PKU | 3458 CPUID_7_0_ECX_AVX512VNNI, 3459 .features[FEAT_7_0_EDX] = 3460 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 3461 /* XSAVES is added in version 5 */ 3462 .features[FEAT_XSAVE] = 3463 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3464 CPUID_XSAVE_XGETBV1, 3465 .features[FEAT_6_EAX] = 3466 CPUID_6_EAX_ARAT, 3467 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3468 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3469 MSR_VMX_BASIC_TRUE_CTLS, 3470 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3471 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3472 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3473 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3474 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3475 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3476 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3477 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3478 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3479 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3480 .features[FEAT_VMX_EXIT_CTLS] = 3481 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3482 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3483 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3484 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3485 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3486 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3487 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3488 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3489 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3490 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3491 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3492 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3493 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3494 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3495 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3496 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3497 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3498 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3499 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3500 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3501 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3502 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3503 .features[FEAT_VMX_SECONDARY_CTLS] = 3504 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3505 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3506 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3507 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3508 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3509 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3510 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3511 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3512 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3513 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3514 .xlevel = 0x80000008, 3515 .model_id = "Intel Xeon Processor (Cascadelake)", 3516 .versions = (X86CPUVersionDefinition[]) { 3517 { .version = 1 }, 3518 { .version = 2, 3519 .note = "ARCH_CAPABILITIES", 3520 .props = (PropValue[]) { 3521 { "arch-capabilities", "on" }, 3522 { "rdctl-no", "on" }, 3523 { "ibrs-all", "on" }, 3524 { "skip-l1dfl-vmentry", "on" }, 3525 { "mds-no", "on" }, 3526 { /* end of list */ } 3527 }, 3528 }, 3529 { .version = 3, 3530 .alias = "Cascadelake-Server-noTSX", 3531 .note = "ARCH_CAPABILITIES, no TSX", 3532 .props = (PropValue[]) { 3533 { "hle", "off" }, 3534 { "rtm", "off" }, 3535 { /* end of list */ } 3536 }, 3537 }, 3538 { .version = 4, 3539 .note = "ARCH_CAPABILITIES, no TSX", 3540 .props = (PropValue[]) { 3541 { "vmx-eptp-switching", "on" }, 3542 { /* end of list */ } 3543 }, 3544 }, 3545 { .version = 5, 3546 .note = "ARCH_CAPABILITIES, EPT switching, XSAVES, no TSX", 3547 .props = (PropValue[]) { 3548 { "xsaves", "on" }, 3549 { "vmx-xsaves", "on" }, 3550 { /* end of list */ } 3551 }, 3552 }, 3553 { /* end of list */ } 3554 } 3555 }, 3556 { 3557 .name = "Cooperlake", 3558 .level = 0xd, 3559 .vendor = CPUID_VENDOR_INTEL, 3560 .family = 6, 3561 .model = 85, 3562 .stepping = 10, 3563 .features[FEAT_1_EDX] = 3564 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3565 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3566 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3567 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3568 CPUID_DE | CPUID_FP87, 3569 .features[FEAT_1_ECX] = 3570 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3571 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3572 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3573 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3574 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3575 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3576 .features[FEAT_8000_0001_EDX] = 3577 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3578 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3579 .features[FEAT_8000_0001_ECX] = 3580 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3581 .features[FEAT_7_0_EBX] = 3582 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3583 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3584 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3585 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3586 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3587 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3588 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3589 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3590 .features[FEAT_7_0_ECX] = 3591 CPUID_7_0_ECX_PKU | 3592 CPUID_7_0_ECX_AVX512VNNI, 3593 .features[FEAT_7_0_EDX] = 3594 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_STIBP | 3595 CPUID_7_0_EDX_SPEC_CTRL_SSBD | CPUID_7_0_EDX_ARCH_CAPABILITIES, 3596 .features[FEAT_ARCH_CAPABILITIES] = 3597 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 3598 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 3599 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO, 3600 .features[FEAT_7_1_EAX] = 3601 CPUID_7_1_EAX_AVX512_BF16, 3602 /* XSAVES is added in version 2 */ 3603 .features[FEAT_XSAVE] = 3604 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3605 CPUID_XSAVE_XGETBV1, 3606 .features[FEAT_6_EAX] = 3607 CPUID_6_EAX_ARAT, 3608 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3609 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3610 MSR_VMX_BASIC_TRUE_CTLS, 3611 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3612 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3613 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3614 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3615 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3616 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3617 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3618 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3619 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3620 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3621 .features[FEAT_VMX_EXIT_CTLS] = 3622 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3623 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3624 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3625 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3626 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3627 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3628 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3629 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3630 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3631 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3632 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3633 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3634 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3635 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3636 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3637 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3638 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3639 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3640 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3641 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3642 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3643 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3644 .features[FEAT_VMX_SECONDARY_CTLS] = 3645 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3646 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3647 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3648 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3649 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3650 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3651 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3652 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3653 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3654 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3655 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3656 .xlevel = 0x80000008, 3657 .model_id = "Intel Xeon Processor (Cooperlake)", 3658 .versions = (X86CPUVersionDefinition[]) { 3659 { .version = 1 }, 3660 { .version = 2, 3661 .note = "XSAVES", 3662 .props = (PropValue[]) { 3663 { "xsaves", "on" }, 3664 { "vmx-xsaves", "on" }, 3665 { /* end of list */ } 3666 }, 3667 }, 3668 { /* end of list */ } 3669 } 3670 }, 3671 { 3672 .name = "Icelake-Server", 3673 .level = 0xd, 3674 .vendor = CPUID_VENDOR_INTEL, 3675 .family = 6, 3676 .model = 134, 3677 .stepping = 0, 3678 .features[FEAT_1_EDX] = 3679 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3680 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3681 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3682 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3683 CPUID_DE | CPUID_FP87, 3684 .features[FEAT_1_ECX] = 3685 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3686 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3687 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3688 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3689 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3690 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3691 .features[FEAT_8000_0001_EDX] = 3692 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3693 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3694 .features[FEAT_8000_0001_ECX] = 3695 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3696 .features[FEAT_8000_0008_EBX] = 3697 CPUID_8000_0008_EBX_WBNOINVD, 3698 .features[FEAT_7_0_EBX] = 3699 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3700 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3701 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3702 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3703 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3704 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3705 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3706 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3707 .features[FEAT_7_0_ECX] = 3708 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 3709 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 3710 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 3711 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 3712 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57, 3713 .features[FEAT_7_0_EDX] = 3714 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 3715 /* XSAVES is added in version 5 */ 3716 .features[FEAT_XSAVE] = 3717 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3718 CPUID_XSAVE_XGETBV1, 3719 .features[FEAT_6_EAX] = 3720 CPUID_6_EAX_ARAT, 3721 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3722 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3723 MSR_VMX_BASIC_TRUE_CTLS, 3724 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3725 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3726 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3727 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3728 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3729 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3730 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3731 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3732 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3733 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3734 .features[FEAT_VMX_EXIT_CTLS] = 3735 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3736 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3737 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3738 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3739 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3740 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3741 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3742 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3743 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3744 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3745 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3746 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3747 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3748 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3749 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3750 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3751 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3752 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3753 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3754 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3755 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3756 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3757 .features[FEAT_VMX_SECONDARY_CTLS] = 3758 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3759 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3760 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3761 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3762 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3763 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3764 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3765 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3766 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS, 3767 .xlevel = 0x80000008, 3768 .model_id = "Intel Xeon Processor (Icelake)", 3769 .versions = (X86CPUVersionDefinition[]) { 3770 { .version = 1 }, 3771 { 3772 .version = 2, 3773 .note = "no TSX", 3774 .alias = "Icelake-Server-noTSX", 3775 .props = (PropValue[]) { 3776 { "hle", "off" }, 3777 { "rtm", "off" }, 3778 { /* end of list */ } 3779 }, 3780 }, 3781 { 3782 .version = 3, 3783 .props = (PropValue[]) { 3784 { "arch-capabilities", "on" }, 3785 { "rdctl-no", "on" }, 3786 { "ibrs-all", "on" }, 3787 { "skip-l1dfl-vmentry", "on" }, 3788 { "mds-no", "on" }, 3789 { "pschange-mc-no", "on" }, 3790 { "taa-no", "on" }, 3791 { /* end of list */ } 3792 }, 3793 }, 3794 { 3795 .version = 4, 3796 .props = (PropValue[]) { 3797 { "sha-ni", "on" }, 3798 { "avx512ifma", "on" }, 3799 { "rdpid", "on" }, 3800 { "fsrm", "on" }, 3801 { "vmx-rdseed-exit", "on" }, 3802 { "vmx-pml", "on" }, 3803 { "vmx-eptp-switching", "on" }, 3804 { "model", "106" }, 3805 { /* end of list */ } 3806 }, 3807 }, 3808 { 3809 .version = 5, 3810 .note = "XSAVES", 3811 .props = (PropValue[]) { 3812 { "xsaves", "on" }, 3813 { "vmx-xsaves", "on" }, 3814 { /* end of list */ } 3815 }, 3816 }, 3817 { 3818 .version = 6, 3819 .note = "5-level EPT", 3820 .props = (PropValue[]) { 3821 { "vmx-page-walk-5", "on" }, 3822 { /* end of list */ } 3823 }, 3824 }, 3825 { /* end of list */ } 3826 } 3827 }, 3828 { 3829 .name = "SapphireRapids", 3830 .level = 0x20, 3831 .vendor = CPUID_VENDOR_INTEL, 3832 .family = 6, 3833 .model = 143, 3834 .stepping = 4, 3835 /* 3836 * please keep the ascending order so that we can have a clear view of 3837 * bit position of each feature. 3838 */ 3839 .features[FEAT_1_EDX] = 3840 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 3841 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 3842 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 3843 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 3844 CPUID_SSE | CPUID_SSE2, 3845 .features[FEAT_1_ECX] = 3846 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 3847 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 3848 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 3849 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 3850 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3851 .features[FEAT_8000_0001_EDX] = 3852 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 3853 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 3854 .features[FEAT_8000_0001_ECX] = 3855 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 3856 .features[FEAT_8000_0008_EBX] = 3857 CPUID_8000_0008_EBX_WBNOINVD, 3858 .features[FEAT_7_0_EBX] = 3859 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_HLE | 3860 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | 3861 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RTM | 3862 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3863 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | 3864 CPUID_7_0_EBX_AVX512IFMA | CPUID_7_0_EBX_CLFLUSHOPT | 3865 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | 3866 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, 3867 .features[FEAT_7_0_ECX] = 3868 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 3869 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 3870 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 3871 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 3872 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | 3873 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT, 3874 .features[FEAT_7_0_EDX] = 3875 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 3876 CPUID_7_0_EDX_TSX_LDTRK | CPUID_7_0_EDX_AMX_BF16 | 3877 CPUID_7_0_EDX_AVX512_FP16 | CPUID_7_0_EDX_AMX_TILE | 3878 CPUID_7_0_EDX_AMX_INT8 | CPUID_7_0_EDX_SPEC_CTRL | 3879 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 3880 .features[FEAT_ARCH_CAPABILITIES] = 3881 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 3882 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 3883 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO, 3884 .features[FEAT_XSAVE] = 3885 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3886 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES | CPUID_D_1_EAX_XFD, 3887 .features[FEAT_6_EAX] = 3888 CPUID_6_EAX_ARAT, 3889 .features[FEAT_7_1_EAX] = 3890 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_AVX512_BF16 | 3891 CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC, 3892 .features[FEAT_VMX_BASIC] = 3893 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 3894 .features[FEAT_VMX_ENTRY_CTLS] = 3895 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 3896 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 3897 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 3898 .features[FEAT_VMX_EPT_VPID_CAPS] = 3899 MSR_VMX_EPT_EXECONLY | 3900 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_PAGE_WALK_LENGTH_5 | 3901 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 3902 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 3903 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3904 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3905 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 3906 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3907 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 3908 .features[FEAT_VMX_EXIT_CTLS] = 3909 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3910 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3911 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 3912 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3913 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3914 .features[FEAT_VMX_MISC] = 3915 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 3916 MSR_VMX_MISC_VMWRITE_VMEXIT, 3917 .features[FEAT_VMX_PINBASED_CTLS] = 3918 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 3919 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 3920 VMX_PIN_BASED_POSTED_INTR, 3921 .features[FEAT_VMX_PROCBASED_CTLS] = 3922 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3923 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3924 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3925 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3926 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3927 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3928 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 3929 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 3930 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3931 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 3932 VMX_CPU_BASED_PAUSE_EXITING | 3933 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3934 .features[FEAT_VMX_SECONDARY_CTLS] = 3935 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3936 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 3937 VMX_SECONDARY_EXEC_RDTSCP | 3938 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3939 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 3940 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3941 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3942 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3943 VMX_SECONDARY_EXEC_RDRAND_EXITING | 3944 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3945 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3946 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 3947 VMX_SECONDARY_EXEC_XSAVES, 3948 .features[FEAT_VMX_VMFUNC] = 3949 MSR_VMX_VMFUNC_EPT_SWITCHING, 3950 .xlevel = 0x80000008, 3951 .model_id = "Intel Xeon Processor (SapphireRapids)", 3952 .versions = (X86CPUVersionDefinition[]) { 3953 { .version = 1 }, 3954 { 3955 .version = 2, 3956 .props = (PropValue[]) { 3957 { "sbdr-ssdp-no", "on" }, 3958 { "fbsdp-no", "on" }, 3959 { "psdp-no", "on" }, 3960 { /* end of list */ } 3961 } 3962 }, 3963 { /* end of list */ } 3964 } 3965 }, 3966 { 3967 .name = "GraniteRapids", 3968 .level = 0x20, 3969 .vendor = CPUID_VENDOR_INTEL, 3970 .family = 6, 3971 .model = 173, 3972 .stepping = 0, 3973 /* 3974 * please keep the ascending order so that we can have a clear view of 3975 * bit position of each feature. 3976 */ 3977 .features[FEAT_1_EDX] = 3978 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 3979 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 3980 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 3981 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 3982 CPUID_SSE | CPUID_SSE2, 3983 .features[FEAT_1_ECX] = 3984 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 3985 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 3986 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 3987 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 3988 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3989 .features[FEAT_8000_0001_EDX] = 3990 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 3991 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 3992 .features[FEAT_8000_0001_ECX] = 3993 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 3994 .features[FEAT_8000_0008_EBX] = 3995 CPUID_8000_0008_EBX_WBNOINVD, 3996 .features[FEAT_7_0_EBX] = 3997 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_HLE | 3998 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | 3999 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RTM | 4000 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 4001 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | 4002 CPUID_7_0_EBX_AVX512IFMA | CPUID_7_0_EBX_CLFLUSHOPT | 4003 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | 4004 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, 4005 .features[FEAT_7_0_ECX] = 4006 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 4007 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 4008 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4009 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 4010 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | 4011 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT, 4012 .features[FEAT_7_0_EDX] = 4013 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 4014 CPUID_7_0_EDX_TSX_LDTRK | CPUID_7_0_EDX_AMX_BF16 | 4015 CPUID_7_0_EDX_AVX512_FP16 | CPUID_7_0_EDX_AMX_TILE | 4016 CPUID_7_0_EDX_AMX_INT8 | CPUID_7_0_EDX_SPEC_CTRL | 4017 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4018 .features[FEAT_ARCH_CAPABILITIES] = 4019 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 4020 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 4021 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO | 4022 MSR_ARCH_CAP_SBDR_SSDP_NO | MSR_ARCH_CAP_FBSDP_NO | 4023 MSR_ARCH_CAP_PSDP_NO | MSR_ARCH_CAP_PBRSB_NO, 4024 .features[FEAT_XSAVE] = 4025 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4026 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES | CPUID_D_1_EAX_XFD, 4027 .features[FEAT_6_EAX] = 4028 CPUID_6_EAX_ARAT, 4029 .features[FEAT_7_1_EAX] = 4030 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_AVX512_BF16 | 4031 CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC | 4032 CPUID_7_1_EAX_AMX_FP16, 4033 .features[FEAT_7_1_EDX] = 4034 CPUID_7_1_EDX_PREFETCHITI, 4035 .features[FEAT_7_2_EDX] = 4036 CPUID_7_2_EDX_MCDT_NO, 4037 .features[FEAT_VMX_BASIC] = 4038 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 4039 .features[FEAT_VMX_ENTRY_CTLS] = 4040 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 4041 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 4042 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 4043 .features[FEAT_VMX_EPT_VPID_CAPS] = 4044 MSR_VMX_EPT_EXECONLY | 4045 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_PAGE_WALK_LENGTH_5 | 4046 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 4047 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 4048 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4049 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4050 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 4051 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4052 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 4053 .features[FEAT_VMX_EXIT_CTLS] = 4054 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4055 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4056 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 4057 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4058 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4059 .features[FEAT_VMX_MISC] = 4060 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 4061 MSR_VMX_MISC_VMWRITE_VMEXIT, 4062 .features[FEAT_VMX_PINBASED_CTLS] = 4063 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 4064 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 4065 VMX_PIN_BASED_POSTED_INTR, 4066 .features[FEAT_VMX_PROCBASED_CTLS] = 4067 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4068 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4069 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4070 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4071 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4072 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4073 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 4074 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 4075 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4076 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 4077 VMX_CPU_BASED_PAUSE_EXITING | 4078 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4079 .features[FEAT_VMX_SECONDARY_CTLS] = 4080 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4081 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 4082 VMX_SECONDARY_EXEC_RDTSCP | 4083 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4084 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 4085 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4086 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4087 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4088 VMX_SECONDARY_EXEC_RDRAND_EXITING | 4089 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4090 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4091 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 4092 VMX_SECONDARY_EXEC_XSAVES, 4093 .features[FEAT_VMX_VMFUNC] = 4094 MSR_VMX_VMFUNC_EPT_SWITCHING, 4095 .xlevel = 0x80000008, 4096 .model_id = "Intel Xeon Processor (GraniteRapids)", 4097 .versions = (X86CPUVersionDefinition[]) { 4098 { .version = 1 }, 4099 { /* end of list */ }, 4100 }, 4101 }, 4102 { 4103 .name = "Denverton", 4104 .level = 21, 4105 .vendor = CPUID_VENDOR_INTEL, 4106 .family = 6, 4107 .model = 95, 4108 .stepping = 1, 4109 .features[FEAT_1_EDX] = 4110 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4111 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4112 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4113 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4114 CPUID_SSE | CPUID_SSE2, 4115 .features[FEAT_1_ECX] = 4116 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR | 4117 CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_SSE41 | 4118 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4119 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | 4120 CPUID_EXT_AES | CPUID_EXT_XSAVE | CPUID_EXT_RDRAND, 4121 .features[FEAT_8000_0001_EDX] = 4122 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4123 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4124 .features[FEAT_8000_0001_ECX] = 4125 CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 4126 .features[FEAT_7_0_EBX] = 4127 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_ERMS | 4128 CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_SMAP | 4129 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_SHA_NI, 4130 .features[FEAT_7_0_EDX] = 4131 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES | 4132 CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4133 /* XSAVES is added in version 3 */ 4134 .features[FEAT_XSAVE] = 4135 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | CPUID_XSAVE_XGETBV1, 4136 .features[FEAT_6_EAX] = 4137 CPUID_6_EAX_ARAT, 4138 .features[FEAT_ARCH_CAPABILITIES] = 4139 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY, 4140 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 4141 MSR_VMX_BASIC_TRUE_CTLS, 4142 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 4143 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 4144 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 4145 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 4146 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 4147 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 4148 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4149 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4150 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4151 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 4152 .features[FEAT_VMX_EXIT_CTLS] = 4153 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4154 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4155 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 4156 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4157 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4158 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 4159 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 4160 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 4161 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 4162 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 4163 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4164 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4165 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4166 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4167 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4168 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 4169 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 4170 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 4171 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 4172 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4173 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4174 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4175 .features[FEAT_VMX_SECONDARY_CTLS] = 4176 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4177 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 4178 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 4179 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4180 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4181 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4182 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4183 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4184 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4185 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 4186 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 4187 .xlevel = 0x80000008, 4188 .model_id = "Intel Atom Processor (Denverton)", 4189 .versions = (X86CPUVersionDefinition[]) { 4190 { .version = 1 }, 4191 { 4192 .version = 2, 4193 .note = "no MPX, no MONITOR", 4194 .props = (PropValue[]) { 4195 { "monitor", "off" }, 4196 { "mpx", "off" }, 4197 { /* end of list */ }, 4198 }, 4199 }, 4200 { 4201 .version = 3, 4202 .note = "XSAVES, no MPX, no MONITOR", 4203 .props = (PropValue[]) { 4204 { "xsaves", "on" }, 4205 { "vmx-xsaves", "on" }, 4206 { /* end of list */ }, 4207 }, 4208 }, 4209 { /* end of list */ }, 4210 }, 4211 }, 4212 { 4213 .name = "Snowridge", 4214 .level = 27, 4215 .vendor = CPUID_VENDOR_INTEL, 4216 .family = 6, 4217 .model = 134, 4218 .stepping = 1, 4219 .features[FEAT_1_EDX] = 4220 /* missing: CPUID_PN CPUID_IA64 */ 4221 /* missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 4222 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | 4223 CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_MCE | 4224 CPUID_CX8 | CPUID_APIC | CPUID_SEP | 4225 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4226 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | 4227 CPUID_MMX | 4228 CPUID_FXSR | CPUID_SSE | CPUID_SSE2, 4229 .features[FEAT_1_ECX] = 4230 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR | 4231 CPUID_EXT_SSSE3 | 4232 CPUID_EXT_CX16 | 4233 CPUID_EXT_SSE41 | 4234 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4235 CPUID_EXT_POPCNT | 4236 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | CPUID_EXT_XSAVE | 4237 CPUID_EXT_RDRAND, 4238 .features[FEAT_8000_0001_EDX] = 4239 CPUID_EXT2_SYSCALL | 4240 CPUID_EXT2_NX | 4241 CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 4242 CPUID_EXT2_LM, 4243 .features[FEAT_8000_0001_ECX] = 4244 CPUID_EXT3_LAHF_LM | 4245 CPUID_EXT3_3DNOWPREFETCH, 4246 .features[FEAT_7_0_EBX] = 4247 CPUID_7_0_EBX_FSGSBASE | 4248 CPUID_7_0_EBX_SMEP | 4249 CPUID_7_0_EBX_ERMS | 4250 CPUID_7_0_EBX_MPX | /* missing bits 13, 15 */ 4251 CPUID_7_0_EBX_RDSEED | 4252 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 4253 CPUID_7_0_EBX_CLWB | 4254 CPUID_7_0_EBX_SHA_NI, 4255 .features[FEAT_7_0_ECX] = 4256 CPUID_7_0_ECX_UMIP | 4257 /* missing bit 5 */ 4258 CPUID_7_0_ECX_GFNI | 4259 CPUID_7_0_ECX_MOVDIRI | CPUID_7_0_ECX_CLDEMOTE | 4260 CPUID_7_0_ECX_MOVDIR64B, 4261 .features[FEAT_7_0_EDX] = 4262 CPUID_7_0_EDX_SPEC_CTRL | 4263 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD | 4264 CPUID_7_0_EDX_CORE_CAPABILITY, 4265 .features[FEAT_CORE_CAPABILITY] = 4266 MSR_CORE_CAP_SPLIT_LOCK_DETECT, 4267 /* XSAVES is added in version 3 */ 4268 .features[FEAT_XSAVE] = 4269 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4270 CPUID_XSAVE_XGETBV1, 4271 .features[FEAT_6_EAX] = 4272 CPUID_6_EAX_ARAT, 4273 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 4274 MSR_VMX_BASIC_TRUE_CTLS, 4275 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 4276 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 4277 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 4278 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 4279 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 4280 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 4281 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4282 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4283 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4284 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 4285 .features[FEAT_VMX_EXIT_CTLS] = 4286 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4287 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4288 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 4289 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4290 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4291 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 4292 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 4293 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 4294 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 4295 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 4296 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4297 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4298 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4299 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4300 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4301 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 4302 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 4303 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 4304 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 4305 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4306 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4307 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4308 .features[FEAT_VMX_SECONDARY_CTLS] = 4309 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4310 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 4311 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 4312 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4313 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4314 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4315 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4316 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4317 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4318 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 4319 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 4320 .xlevel = 0x80000008, 4321 .model_id = "Intel Atom Processor (SnowRidge)", 4322 .versions = (X86CPUVersionDefinition[]) { 4323 { .version = 1 }, 4324 { 4325 .version = 2, 4326 .props = (PropValue[]) { 4327 { "mpx", "off" }, 4328 { "model-id", "Intel Atom Processor (Snowridge, no MPX)" }, 4329 { /* end of list */ }, 4330 }, 4331 }, 4332 { 4333 .version = 3, 4334 .note = "XSAVES, no MPX", 4335 .props = (PropValue[]) { 4336 { "xsaves", "on" }, 4337 { "vmx-xsaves", "on" }, 4338 { /* end of list */ }, 4339 }, 4340 }, 4341 { 4342 .version = 4, 4343 .note = "no split lock detect, no core-capability", 4344 .props = (PropValue[]) { 4345 { "split-lock-detect", "off" }, 4346 { "core-capability", "off" }, 4347 { /* end of list */ }, 4348 }, 4349 }, 4350 { /* end of list */ }, 4351 }, 4352 }, 4353 { 4354 .name = "KnightsMill", 4355 .level = 0xd, 4356 .vendor = CPUID_VENDOR_INTEL, 4357 .family = 6, 4358 .model = 133, 4359 .stepping = 0, 4360 .features[FEAT_1_EDX] = 4361 CPUID_VME | CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | 4362 CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | 4363 CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | 4364 CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | 4365 CPUID_PSE | CPUID_DE | CPUID_FP87, 4366 .features[FEAT_1_ECX] = 4367 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 4368 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 4369 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 4370 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 4371 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 4372 CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4373 .features[FEAT_8000_0001_EDX] = 4374 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 4375 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 4376 .features[FEAT_8000_0001_ECX] = 4377 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 4378 .features[FEAT_7_0_EBX] = 4379 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4380 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 4381 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_AVX512F | 4382 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_AVX512PF | 4383 CPUID_7_0_EBX_AVX512ER, 4384 .features[FEAT_7_0_ECX] = 4385 CPUID_7_0_ECX_AVX512_VPOPCNTDQ, 4386 .features[FEAT_7_0_EDX] = 4387 CPUID_7_0_EDX_AVX512_4VNNIW | CPUID_7_0_EDX_AVX512_4FMAPS, 4388 .features[FEAT_XSAVE] = 4389 CPUID_XSAVE_XSAVEOPT, 4390 .features[FEAT_6_EAX] = 4391 CPUID_6_EAX_ARAT, 4392 .xlevel = 0x80000008, 4393 .model_id = "Intel Xeon Phi Processor (Knights Mill)", 4394 }, 4395 { 4396 .name = "Opteron_G1", 4397 .level = 5, 4398 .vendor = CPUID_VENDOR_AMD, 4399 .family = 15, 4400 .model = 6, 4401 .stepping = 1, 4402 .features[FEAT_1_EDX] = 4403 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4404 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4405 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4406 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4407 CPUID_DE | CPUID_FP87, 4408 .features[FEAT_1_ECX] = 4409 CPUID_EXT_SSE3, 4410 .features[FEAT_8000_0001_EDX] = 4411 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 4412 .xlevel = 0x80000008, 4413 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)", 4414 }, 4415 { 4416 .name = "Opteron_G2", 4417 .level = 5, 4418 .vendor = CPUID_VENDOR_AMD, 4419 .family = 15, 4420 .model = 6, 4421 .stepping = 1, 4422 .features[FEAT_1_EDX] = 4423 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4424 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4425 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4426 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4427 CPUID_DE | CPUID_FP87, 4428 .features[FEAT_1_ECX] = 4429 CPUID_EXT_CX16 | CPUID_EXT_SSE3, 4430 .features[FEAT_8000_0001_EDX] = 4431 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 4432 .features[FEAT_8000_0001_ECX] = 4433 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, 4434 .xlevel = 0x80000008, 4435 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)", 4436 }, 4437 { 4438 .name = "Opteron_G3", 4439 .level = 5, 4440 .vendor = CPUID_VENDOR_AMD, 4441 .family = 16, 4442 .model = 2, 4443 .stepping = 3, 4444 .features[FEAT_1_EDX] = 4445 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4446 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4447 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4448 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4449 CPUID_DE | CPUID_FP87, 4450 .features[FEAT_1_ECX] = 4451 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR | 4452 CPUID_EXT_SSE3, 4453 .features[FEAT_8000_0001_EDX] = 4454 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL | 4455 CPUID_EXT2_RDTSCP, 4456 .features[FEAT_8000_0001_ECX] = 4457 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | 4458 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, 4459 .xlevel = 0x80000008, 4460 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)", 4461 }, 4462 { 4463 .name = "Opteron_G4", 4464 .level = 0xd, 4465 .vendor = CPUID_VENDOR_AMD, 4466 .family = 21, 4467 .model = 1, 4468 .stepping = 2, 4469 .features[FEAT_1_EDX] = 4470 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4471 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4472 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4473 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4474 CPUID_DE | CPUID_FP87, 4475 .features[FEAT_1_ECX] = 4476 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 4477 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 4478 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 4479 CPUID_EXT_SSE3, 4480 .features[FEAT_8000_0001_EDX] = 4481 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX | 4482 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP, 4483 .features[FEAT_8000_0001_ECX] = 4484 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP | 4485 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | 4486 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | 4487 CPUID_EXT3_LAHF_LM, 4488 .features[FEAT_SVM] = 4489 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 4490 /* no xsaveopt! */ 4491 .xlevel = 0x8000001A, 4492 .model_id = "AMD Opteron 62xx class CPU", 4493 }, 4494 { 4495 .name = "Opteron_G5", 4496 .level = 0xd, 4497 .vendor = CPUID_VENDOR_AMD, 4498 .family = 21, 4499 .model = 2, 4500 .stepping = 0, 4501 .features[FEAT_1_EDX] = 4502 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4503 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4504 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4505 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4506 CPUID_DE | CPUID_FP87, 4507 .features[FEAT_1_ECX] = 4508 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE | 4509 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | 4510 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA | 4511 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 4512 .features[FEAT_8000_0001_EDX] = 4513 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX | 4514 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP, 4515 .features[FEAT_8000_0001_ECX] = 4516 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP | 4517 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | 4518 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | 4519 CPUID_EXT3_LAHF_LM, 4520 .features[FEAT_SVM] = 4521 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 4522 /* no xsaveopt! */ 4523 .xlevel = 0x8000001A, 4524 .model_id = "AMD Opteron 63xx class CPU", 4525 }, 4526 { 4527 .name = "EPYC", 4528 .level = 0xd, 4529 .vendor = CPUID_VENDOR_AMD, 4530 .family = 23, 4531 .model = 1, 4532 .stepping = 2, 4533 .features[FEAT_1_EDX] = 4534 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 4535 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 4536 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 4537 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 4538 CPUID_VME | CPUID_FP87, 4539 .features[FEAT_1_ECX] = 4540 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 4541 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 4542 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 4543 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 4544 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 4545 .features[FEAT_8000_0001_EDX] = 4546 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 4547 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 4548 CPUID_EXT2_SYSCALL, 4549 .features[FEAT_8000_0001_ECX] = 4550 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 4551 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 4552 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 4553 CPUID_EXT3_TOPOEXT, 4554 .features[FEAT_7_0_EBX] = 4555 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4556 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 4557 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 4558 CPUID_7_0_EBX_SHA_NI, 4559 .features[FEAT_XSAVE] = 4560 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4561 CPUID_XSAVE_XGETBV1, 4562 .features[FEAT_6_EAX] = 4563 CPUID_6_EAX_ARAT, 4564 .features[FEAT_SVM] = 4565 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 4566 .xlevel = 0x8000001E, 4567 .model_id = "AMD EPYC Processor", 4568 .cache_info = &epyc_cache_info, 4569 .versions = (X86CPUVersionDefinition[]) { 4570 { .version = 1 }, 4571 { 4572 .version = 2, 4573 .alias = "EPYC-IBPB", 4574 .props = (PropValue[]) { 4575 { "ibpb", "on" }, 4576 { "model-id", 4577 "AMD EPYC Processor (with IBPB)" }, 4578 { /* end of list */ } 4579 } 4580 }, 4581 { 4582 .version = 3, 4583 .props = (PropValue[]) { 4584 { "ibpb", "on" }, 4585 { "perfctr-core", "on" }, 4586 { "clzero", "on" }, 4587 { "xsaveerptr", "on" }, 4588 { "xsaves", "on" }, 4589 { "model-id", 4590 "AMD EPYC Processor" }, 4591 { /* end of list */ } 4592 } 4593 }, 4594 { 4595 .version = 4, 4596 .props = (PropValue[]) { 4597 { "model-id", 4598 "AMD EPYC-v4 Processor" }, 4599 { /* end of list */ } 4600 }, 4601 .cache_info = &epyc_v4_cache_info 4602 }, 4603 { /* end of list */ } 4604 } 4605 }, 4606 { 4607 .name = "Dhyana", 4608 .level = 0xd, 4609 .vendor = CPUID_VENDOR_HYGON, 4610 .family = 24, 4611 .model = 0, 4612 .stepping = 1, 4613 .features[FEAT_1_EDX] = 4614 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 4615 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 4616 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 4617 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 4618 CPUID_VME | CPUID_FP87, 4619 .features[FEAT_1_ECX] = 4620 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 4621 CPUID_EXT_XSAVE | CPUID_EXT_POPCNT | 4622 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 4623 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 4624 CPUID_EXT_MONITOR | CPUID_EXT_SSE3, 4625 .features[FEAT_8000_0001_EDX] = 4626 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 4627 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 4628 CPUID_EXT2_SYSCALL, 4629 .features[FEAT_8000_0001_ECX] = 4630 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 4631 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 4632 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 4633 CPUID_EXT3_TOPOEXT, 4634 .features[FEAT_8000_0008_EBX] = 4635 CPUID_8000_0008_EBX_IBPB, 4636 .features[FEAT_7_0_EBX] = 4637 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4638 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 4639 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT, 4640 /* XSAVES is added in version 2 */ 4641 .features[FEAT_XSAVE] = 4642 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4643 CPUID_XSAVE_XGETBV1, 4644 .features[FEAT_6_EAX] = 4645 CPUID_6_EAX_ARAT, 4646 .features[FEAT_SVM] = 4647 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 4648 .xlevel = 0x8000001E, 4649 .model_id = "Hygon Dhyana Processor", 4650 .cache_info = &epyc_cache_info, 4651 .versions = (X86CPUVersionDefinition[]) { 4652 { .version = 1 }, 4653 { .version = 2, 4654 .note = "XSAVES", 4655 .props = (PropValue[]) { 4656 { "xsaves", "on" }, 4657 { /* end of list */ } 4658 }, 4659 }, 4660 { /* end of list */ } 4661 } 4662 }, 4663 { 4664 .name = "EPYC-Rome", 4665 .level = 0xd, 4666 .vendor = CPUID_VENDOR_AMD, 4667 .family = 23, 4668 .model = 49, 4669 .stepping = 0, 4670 .features[FEAT_1_EDX] = 4671 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 4672 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 4673 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 4674 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 4675 CPUID_VME | CPUID_FP87, 4676 .features[FEAT_1_ECX] = 4677 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 4678 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 4679 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 4680 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 4681 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 4682 .features[FEAT_8000_0001_EDX] = 4683 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 4684 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 4685 CPUID_EXT2_SYSCALL, 4686 .features[FEAT_8000_0001_ECX] = 4687 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 4688 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 4689 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 4690 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 4691 .features[FEAT_8000_0008_EBX] = 4692 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 4693 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 4694 CPUID_8000_0008_EBX_STIBP, 4695 .features[FEAT_7_0_EBX] = 4696 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4697 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 4698 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 4699 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB, 4700 .features[FEAT_7_0_ECX] = 4701 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID, 4702 .features[FEAT_XSAVE] = 4703 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4704 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 4705 .features[FEAT_6_EAX] = 4706 CPUID_6_EAX_ARAT, 4707 .features[FEAT_SVM] = 4708 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 4709 .xlevel = 0x8000001E, 4710 .model_id = "AMD EPYC-Rome Processor", 4711 .cache_info = &epyc_rome_cache_info, 4712 .versions = (X86CPUVersionDefinition[]) { 4713 { .version = 1 }, 4714 { 4715 .version = 2, 4716 .props = (PropValue[]) { 4717 { "ibrs", "on" }, 4718 { "amd-ssbd", "on" }, 4719 { /* end of list */ } 4720 } 4721 }, 4722 { 4723 .version = 3, 4724 .props = (PropValue[]) { 4725 { "model-id", 4726 "AMD EPYC-Rome-v3 Processor" }, 4727 { /* end of list */ } 4728 }, 4729 .cache_info = &epyc_rome_v3_cache_info 4730 }, 4731 { 4732 .version = 4, 4733 .props = (PropValue[]) { 4734 /* Erratum 1386 */ 4735 { "model-id", 4736 "AMD EPYC-Rome-v4 Processor (no XSAVES)" }, 4737 { "xsaves", "off" }, 4738 { /* end of list */ } 4739 }, 4740 }, 4741 { /* end of list */ } 4742 } 4743 }, 4744 { 4745 .name = "EPYC-Milan", 4746 .level = 0xd, 4747 .vendor = CPUID_VENDOR_AMD, 4748 .family = 25, 4749 .model = 1, 4750 .stepping = 1, 4751 .features[FEAT_1_EDX] = 4752 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 4753 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 4754 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 4755 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 4756 CPUID_VME | CPUID_FP87, 4757 .features[FEAT_1_ECX] = 4758 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 4759 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 4760 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 4761 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 4762 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 4763 CPUID_EXT_PCID, 4764 .features[FEAT_8000_0001_EDX] = 4765 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 4766 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 4767 CPUID_EXT2_SYSCALL, 4768 .features[FEAT_8000_0001_ECX] = 4769 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 4770 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 4771 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 4772 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 4773 .features[FEAT_8000_0008_EBX] = 4774 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 4775 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 4776 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | 4777 CPUID_8000_0008_EBX_AMD_SSBD, 4778 .features[FEAT_7_0_EBX] = 4779 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4780 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 4781 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 4782 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_ERMS | 4783 CPUID_7_0_EBX_INVPCID, 4784 .features[FEAT_7_0_ECX] = 4785 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_PKU, 4786 .features[FEAT_7_0_EDX] = 4787 CPUID_7_0_EDX_FSRM, 4788 .features[FEAT_XSAVE] = 4789 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4790 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 4791 .features[FEAT_6_EAX] = 4792 CPUID_6_EAX_ARAT, 4793 .features[FEAT_SVM] = 4794 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE | CPUID_SVM_SVME_ADDR_CHK, 4795 .xlevel = 0x8000001E, 4796 .model_id = "AMD EPYC-Milan Processor", 4797 .cache_info = &epyc_milan_cache_info, 4798 .versions = (X86CPUVersionDefinition[]) { 4799 { .version = 1 }, 4800 { 4801 .version = 2, 4802 .props = (PropValue[]) { 4803 { "model-id", 4804 "AMD EPYC-Milan-v2 Processor" }, 4805 { "vaes", "on" }, 4806 { "vpclmulqdq", "on" }, 4807 { "stibp-always-on", "on" }, 4808 { "amd-psfd", "on" }, 4809 { "no-nested-data-bp", "on" }, 4810 { "lfence-always-serializing", "on" }, 4811 { "null-sel-clr-base", "on" }, 4812 { /* end of list */ } 4813 }, 4814 .cache_info = &epyc_milan_v2_cache_info 4815 }, 4816 { /* end of list */ } 4817 } 4818 }, 4819 { 4820 .name = "EPYC-Genoa", 4821 .level = 0xd, 4822 .vendor = CPUID_VENDOR_AMD, 4823 .family = 25, 4824 .model = 17, 4825 .stepping = 0, 4826 .features[FEAT_1_EDX] = 4827 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 4828 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 4829 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 4830 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 4831 CPUID_VME | CPUID_FP87, 4832 .features[FEAT_1_ECX] = 4833 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 4834 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 4835 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 4836 CPUID_EXT_PCID | CPUID_EXT_CX16 | CPUID_EXT_FMA | 4837 CPUID_EXT_SSSE3 | CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | 4838 CPUID_EXT_SSE3, 4839 .features[FEAT_8000_0001_EDX] = 4840 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 4841 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 4842 CPUID_EXT2_SYSCALL, 4843 .features[FEAT_8000_0001_ECX] = 4844 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 4845 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 4846 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 4847 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 4848 .features[FEAT_8000_0008_EBX] = 4849 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 4850 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 4851 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | 4852 CPUID_8000_0008_EBX_STIBP_ALWAYS_ON | 4853 CPUID_8000_0008_EBX_AMD_SSBD | CPUID_8000_0008_EBX_AMD_PSFD, 4854 .features[FEAT_8000_0021_EAX] = 4855 CPUID_8000_0021_EAX_No_NESTED_DATA_BP | 4856 CPUID_8000_0021_EAX_LFENCE_ALWAYS_SERIALIZING | 4857 CPUID_8000_0021_EAX_NULL_SEL_CLR_BASE | 4858 CPUID_8000_0021_EAX_AUTO_IBRS, 4859 .features[FEAT_7_0_EBX] = 4860 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4861 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 4862 CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_AVX512F | 4863 CPUID_7_0_EBX_AVX512DQ | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 4864 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_AVX512IFMA | 4865 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB | 4866 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | 4867 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, 4868 .features[FEAT_7_0_ECX] = 4869 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 4870 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 4871 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4872 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 4873 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | 4874 CPUID_7_0_ECX_RDPID, 4875 .features[FEAT_7_0_EDX] = 4876 CPUID_7_0_EDX_FSRM, 4877 .features[FEAT_7_1_EAX] = 4878 CPUID_7_1_EAX_AVX512_BF16, 4879 .features[FEAT_XSAVE] = 4880 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4881 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 4882 .features[FEAT_6_EAX] = 4883 CPUID_6_EAX_ARAT, 4884 .features[FEAT_SVM] = 4885 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE | CPUID_SVM_VNMI | 4886 CPUID_SVM_SVME_ADDR_CHK, 4887 .xlevel = 0x80000022, 4888 .model_id = "AMD EPYC-Genoa Processor", 4889 .cache_info = &epyc_genoa_cache_info, 4890 }, 4891 }; 4892 4893 /* 4894 * We resolve CPU model aliases using -v1 when using "-machine 4895 * none", but this is just for compatibility while libvirt isn't 4896 * adapted to resolve CPU model versions before creating VMs. 4897 * See "Runnability guarantee of CPU models" at 4898 * docs/about/deprecated.rst. 4899 */ 4900 X86CPUVersion default_cpu_version = 1; 4901 4902 void x86_cpu_set_default_version(X86CPUVersion version) 4903 { 4904 /* Translating CPU_VERSION_AUTO to CPU_VERSION_AUTO doesn't make sense */ 4905 assert(version != CPU_VERSION_AUTO); 4906 default_cpu_version = version; 4907 } 4908 4909 static X86CPUVersion x86_cpu_model_last_version(const X86CPUModel *model) 4910 { 4911 int v = 0; 4912 const X86CPUVersionDefinition *vdef = 4913 x86_cpu_def_get_versions(model->cpudef); 4914 while (vdef->version) { 4915 v = vdef->version; 4916 vdef++; 4917 } 4918 return v; 4919 } 4920 4921 /* Return the actual version being used for a specific CPU model */ 4922 static X86CPUVersion x86_cpu_model_resolve_version(const X86CPUModel *model) 4923 { 4924 X86CPUVersion v = model->version; 4925 if (v == CPU_VERSION_AUTO) { 4926 v = default_cpu_version; 4927 } 4928 if (v == CPU_VERSION_LATEST) { 4929 return x86_cpu_model_last_version(model); 4930 } 4931 return v; 4932 } 4933 4934 static Property max_x86_cpu_properties[] = { 4935 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true), 4936 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false), 4937 DEFINE_PROP_END_OF_LIST() 4938 }; 4939 4940 static void max_x86_cpu_realize(DeviceState *dev, Error **errp) 4941 { 4942 Object *obj = OBJECT(dev); 4943 4944 if (!object_property_get_int(obj, "family", &error_abort)) { 4945 if (X86_CPU(obj)->env.features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 4946 object_property_set_int(obj, "family", 15, &error_abort); 4947 object_property_set_int(obj, "model", 107, &error_abort); 4948 object_property_set_int(obj, "stepping", 1, &error_abort); 4949 } else { 4950 object_property_set_int(obj, "family", 6, &error_abort); 4951 object_property_set_int(obj, "model", 6, &error_abort); 4952 object_property_set_int(obj, "stepping", 3, &error_abort); 4953 } 4954 } 4955 4956 x86_cpu_realizefn(dev, errp); 4957 } 4958 4959 static void max_x86_cpu_class_init(ObjectClass *oc, void *data) 4960 { 4961 DeviceClass *dc = DEVICE_CLASS(oc); 4962 X86CPUClass *xcc = X86_CPU_CLASS(oc); 4963 4964 xcc->ordering = 9; 4965 4966 xcc->model_description = 4967 "Enables all features supported by the accelerator in the current host"; 4968 4969 device_class_set_props(dc, max_x86_cpu_properties); 4970 dc->realize = max_x86_cpu_realize; 4971 } 4972 4973 static void max_x86_cpu_initfn(Object *obj) 4974 { 4975 X86CPU *cpu = X86_CPU(obj); 4976 4977 /* We can't fill the features array here because we don't know yet if 4978 * "migratable" is true or false. 4979 */ 4980 cpu->max_features = true; 4981 object_property_set_bool(OBJECT(cpu), "pmu", true, &error_abort); 4982 4983 /* 4984 * these defaults are used for TCG and all other accelerators 4985 * besides KVM and HVF, which overwrite these values 4986 */ 4987 object_property_set_str(OBJECT(cpu), "vendor", CPUID_VENDOR_AMD, 4988 &error_abort); 4989 object_property_set_str(OBJECT(cpu), "model-id", 4990 "QEMU TCG CPU version " QEMU_HW_VERSION, 4991 &error_abort); 4992 } 4993 4994 static const TypeInfo max_x86_cpu_type_info = { 4995 .name = X86_CPU_TYPE_NAME("max"), 4996 .parent = TYPE_X86_CPU, 4997 .instance_init = max_x86_cpu_initfn, 4998 .class_init = max_x86_cpu_class_init, 4999 }; 5000 5001 static char *feature_word_description(FeatureWordInfo *f, uint32_t bit) 5002 { 5003 assert(f->type == CPUID_FEATURE_WORD || f->type == MSR_FEATURE_WORD); 5004 5005 switch (f->type) { 5006 case CPUID_FEATURE_WORD: 5007 { 5008 const char *reg = get_register_name_32(f->cpuid.reg); 5009 assert(reg); 5010 return g_strdup_printf("CPUID.%02XH:%s", 5011 f->cpuid.eax, reg); 5012 } 5013 case MSR_FEATURE_WORD: 5014 return g_strdup_printf("MSR(%02XH)", 5015 f->msr.index); 5016 } 5017 5018 return NULL; 5019 } 5020 5021 static bool x86_cpu_have_filtered_features(X86CPU *cpu) 5022 { 5023 FeatureWord w; 5024 5025 for (w = 0; w < FEATURE_WORDS; w++) { 5026 if (cpu->filtered_features[w]) { 5027 return true; 5028 } 5029 } 5030 5031 return false; 5032 } 5033 5034 static void mark_unavailable_features(X86CPU *cpu, FeatureWord w, uint64_t mask, 5035 const char *verbose_prefix) 5036 { 5037 CPUX86State *env = &cpu->env; 5038 FeatureWordInfo *f = &feature_word_info[w]; 5039 int i; 5040 5041 if (!cpu->force_features) { 5042 env->features[w] &= ~mask; 5043 } 5044 cpu->filtered_features[w] |= mask; 5045 5046 if (!verbose_prefix) { 5047 return; 5048 } 5049 5050 for (i = 0; i < 64; ++i) { 5051 if ((1ULL << i) & mask) { 5052 g_autofree char *feat_word_str = feature_word_description(f, i); 5053 warn_report("%s: %s%s%s [bit %d]", 5054 verbose_prefix, 5055 feat_word_str, 5056 f->feat_names[i] ? "." : "", 5057 f->feat_names[i] ? f->feat_names[i] : "", i); 5058 } 5059 } 5060 } 5061 5062 static void x86_cpuid_version_get_family(Object *obj, Visitor *v, 5063 const char *name, void *opaque, 5064 Error **errp) 5065 { 5066 X86CPU *cpu = X86_CPU(obj); 5067 CPUX86State *env = &cpu->env; 5068 int64_t value; 5069 5070 value = (env->cpuid_version >> 8) & 0xf; 5071 if (value == 0xf) { 5072 value += (env->cpuid_version >> 20) & 0xff; 5073 } 5074 visit_type_int(v, name, &value, errp); 5075 } 5076 5077 static void x86_cpuid_version_set_family(Object *obj, Visitor *v, 5078 const char *name, void *opaque, 5079 Error **errp) 5080 { 5081 X86CPU *cpu = X86_CPU(obj); 5082 CPUX86State *env = &cpu->env; 5083 const int64_t min = 0; 5084 const int64_t max = 0xff + 0xf; 5085 int64_t value; 5086 5087 if (!visit_type_int(v, name, &value, errp)) { 5088 return; 5089 } 5090 if (value < min || value > max) { 5091 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", 5092 name ? name : "null", value, min, max); 5093 return; 5094 } 5095 5096 env->cpuid_version &= ~0xff00f00; 5097 if (value > 0x0f) { 5098 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20); 5099 } else { 5100 env->cpuid_version |= value << 8; 5101 } 5102 } 5103 5104 static void x86_cpuid_version_get_model(Object *obj, Visitor *v, 5105 const char *name, void *opaque, 5106 Error **errp) 5107 { 5108 X86CPU *cpu = X86_CPU(obj); 5109 CPUX86State *env = &cpu->env; 5110 int64_t value; 5111 5112 value = (env->cpuid_version >> 4) & 0xf; 5113 value |= ((env->cpuid_version >> 16) & 0xf) << 4; 5114 visit_type_int(v, name, &value, errp); 5115 } 5116 5117 static void x86_cpuid_version_set_model(Object *obj, Visitor *v, 5118 const char *name, void *opaque, 5119 Error **errp) 5120 { 5121 X86CPU *cpu = X86_CPU(obj); 5122 CPUX86State *env = &cpu->env; 5123 const int64_t min = 0; 5124 const int64_t max = 0xff; 5125 int64_t value; 5126 5127 if (!visit_type_int(v, name, &value, errp)) { 5128 return; 5129 } 5130 if (value < min || value > max) { 5131 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", 5132 name ? name : "null", value, min, max); 5133 return; 5134 } 5135 5136 env->cpuid_version &= ~0xf00f0; 5137 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16); 5138 } 5139 5140 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v, 5141 const char *name, void *opaque, 5142 Error **errp) 5143 { 5144 X86CPU *cpu = X86_CPU(obj); 5145 CPUX86State *env = &cpu->env; 5146 int64_t value; 5147 5148 value = env->cpuid_version & 0xf; 5149 visit_type_int(v, name, &value, errp); 5150 } 5151 5152 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v, 5153 const char *name, void *opaque, 5154 Error **errp) 5155 { 5156 X86CPU *cpu = X86_CPU(obj); 5157 CPUX86State *env = &cpu->env; 5158 const int64_t min = 0; 5159 const int64_t max = 0xf; 5160 int64_t value; 5161 5162 if (!visit_type_int(v, name, &value, errp)) { 5163 return; 5164 } 5165 if (value < min || value > max) { 5166 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", 5167 name ? name : "null", value, min, max); 5168 return; 5169 } 5170 5171 env->cpuid_version &= ~0xf; 5172 env->cpuid_version |= value & 0xf; 5173 } 5174 5175 static char *x86_cpuid_get_vendor(Object *obj, Error **errp) 5176 { 5177 X86CPU *cpu = X86_CPU(obj); 5178 CPUX86State *env = &cpu->env; 5179 char *value; 5180 5181 value = g_malloc(CPUID_VENDOR_SZ + 1); 5182 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2, 5183 env->cpuid_vendor3); 5184 return value; 5185 } 5186 5187 static void x86_cpuid_set_vendor(Object *obj, const char *value, 5188 Error **errp) 5189 { 5190 X86CPU *cpu = X86_CPU(obj); 5191 CPUX86State *env = &cpu->env; 5192 int i; 5193 5194 if (strlen(value) != CPUID_VENDOR_SZ) { 5195 error_setg(errp, QERR_PROPERTY_VALUE_BAD, "", "vendor", value); 5196 return; 5197 } 5198 5199 env->cpuid_vendor1 = 0; 5200 env->cpuid_vendor2 = 0; 5201 env->cpuid_vendor3 = 0; 5202 for (i = 0; i < 4; i++) { 5203 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i); 5204 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i); 5205 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i); 5206 } 5207 } 5208 5209 static char *x86_cpuid_get_model_id(Object *obj, Error **errp) 5210 { 5211 X86CPU *cpu = X86_CPU(obj); 5212 CPUX86State *env = &cpu->env; 5213 char *value; 5214 int i; 5215 5216 value = g_malloc(48 + 1); 5217 for (i = 0; i < 48; i++) { 5218 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3)); 5219 } 5220 value[48] = '\0'; 5221 return value; 5222 } 5223 5224 static void x86_cpuid_set_model_id(Object *obj, const char *model_id, 5225 Error **errp) 5226 { 5227 X86CPU *cpu = X86_CPU(obj); 5228 CPUX86State *env = &cpu->env; 5229 int c, len, i; 5230 5231 if (model_id == NULL) { 5232 model_id = ""; 5233 } 5234 len = strlen(model_id); 5235 memset(env->cpuid_model, 0, 48); 5236 for (i = 0; i < 48; i++) { 5237 if (i >= len) { 5238 c = '\0'; 5239 } else { 5240 c = (uint8_t)model_id[i]; 5241 } 5242 env->cpuid_model[i >> 2] |= c << (8 * (i & 3)); 5243 } 5244 } 5245 5246 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name, 5247 void *opaque, Error **errp) 5248 { 5249 X86CPU *cpu = X86_CPU(obj); 5250 int64_t value; 5251 5252 value = cpu->env.tsc_khz * 1000; 5253 visit_type_int(v, name, &value, errp); 5254 } 5255 5256 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name, 5257 void *opaque, Error **errp) 5258 { 5259 X86CPU *cpu = X86_CPU(obj); 5260 const int64_t min = 0; 5261 const int64_t max = INT64_MAX; 5262 int64_t value; 5263 5264 if (!visit_type_int(v, name, &value, errp)) { 5265 return; 5266 } 5267 if (value < min || value > max) { 5268 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", 5269 name ? name : "null", value, min, max); 5270 return; 5271 } 5272 5273 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000; 5274 } 5275 5276 /* Generic getter for "feature-words" and "filtered-features" properties */ 5277 static void x86_cpu_get_feature_words(Object *obj, Visitor *v, 5278 const char *name, void *opaque, 5279 Error **errp) 5280 { 5281 uint64_t *array = (uint64_t *)opaque; 5282 FeatureWord w; 5283 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { }; 5284 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { }; 5285 X86CPUFeatureWordInfoList *list = NULL; 5286 5287 for (w = 0; w < FEATURE_WORDS; w++) { 5288 FeatureWordInfo *wi = &feature_word_info[w]; 5289 /* 5290 * We didn't have MSR features when "feature-words" was 5291 * introduced. Therefore skipped other type entries. 5292 */ 5293 if (wi->type != CPUID_FEATURE_WORD) { 5294 continue; 5295 } 5296 X86CPUFeatureWordInfo *qwi = &word_infos[w]; 5297 qwi->cpuid_input_eax = wi->cpuid.eax; 5298 qwi->has_cpuid_input_ecx = wi->cpuid.needs_ecx; 5299 qwi->cpuid_input_ecx = wi->cpuid.ecx; 5300 qwi->cpuid_register = x86_reg_info_32[wi->cpuid.reg].qapi_enum; 5301 qwi->features = array[w]; 5302 5303 /* List will be in reverse order, but order shouldn't matter */ 5304 list_entries[w].next = list; 5305 list_entries[w].value = &word_infos[w]; 5306 list = &list_entries[w]; 5307 } 5308 5309 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp); 5310 } 5311 5312 /* Convert all '_' in a feature string option name to '-', to make feature 5313 * name conform to QOM property naming rule, which uses '-' instead of '_'. 5314 */ 5315 static inline void feat2prop(char *s) 5316 { 5317 while ((s = strchr(s, '_'))) { 5318 *s = '-'; 5319 } 5320 } 5321 5322 /* Return the feature property name for a feature flag bit */ 5323 static const char *x86_cpu_feature_name(FeatureWord w, int bitnr) 5324 { 5325 const char *name; 5326 /* XSAVE components are automatically enabled by other features, 5327 * so return the original feature name instead 5328 */ 5329 if (w == FEAT_XSAVE_XCR0_LO || w == FEAT_XSAVE_XCR0_HI) { 5330 int comp = (w == FEAT_XSAVE_XCR0_HI) ? bitnr + 32 : bitnr; 5331 5332 if (comp < ARRAY_SIZE(x86_ext_save_areas) && 5333 x86_ext_save_areas[comp].bits) { 5334 w = x86_ext_save_areas[comp].feature; 5335 bitnr = ctz32(x86_ext_save_areas[comp].bits); 5336 } 5337 } 5338 5339 assert(bitnr < 64); 5340 assert(w < FEATURE_WORDS); 5341 name = feature_word_info[w].feat_names[bitnr]; 5342 assert(bitnr < 32 || !(name && feature_word_info[w].type == CPUID_FEATURE_WORD)); 5343 return name; 5344 } 5345 5346 /* Compatibility hack to maintain legacy +-feat semantic, 5347 * where +-feat overwrites any feature set by 5348 * feat=on|feat even if the later is parsed after +-feat 5349 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled) 5350 */ 5351 static GList *plus_features, *minus_features; 5352 5353 static gint compare_string(gconstpointer a, gconstpointer b) 5354 { 5355 return g_strcmp0(a, b); 5356 } 5357 5358 /* Parse "+feature,-feature,feature=foo" CPU feature string 5359 */ 5360 static void x86_cpu_parse_featurestr(const char *typename, char *features, 5361 Error **errp) 5362 { 5363 char *featurestr; /* Single 'key=value" string being parsed */ 5364 static bool cpu_globals_initialized; 5365 bool ambiguous = false; 5366 5367 if (cpu_globals_initialized) { 5368 return; 5369 } 5370 cpu_globals_initialized = true; 5371 5372 if (!features) { 5373 return; 5374 } 5375 5376 for (featurestr = strtok(features, ","); 5377 featurestr; 5378 featurestr = strtok(NULL, ",")) { 5379 const char *name; 5380 const char *val = NULL; 5381 char *eq = NULL; 5382 char num[32]; 5383 GlobalProperty *prop; 5384 5385 /* Compatibility syntax: */ 5386 if (featurestr[0] == '+') { 5387 plus_features = g_list_append(plus_features, 5388 g_strdup(featurestr + 1)); 5389 continue; 5390 } else if (featurestr[0] == '-') { 5391 minus_features = g_list_append(minus_features, 5392 g_strdup(featurestr + 1)); 5393 continue; 5394 } 5395 5396 eq = strchr(featurestr, '='); 5397 if (eq) { 5398 *eq++ = 0; 5399 val = eq; 5400 } else { 5401 val = "on"; 5402 } 5403 5404 feat2prop(featurestr); 5405 name = featurestr; 5406 5407 if (g_list_find_custom(plus_features, name, compare_string)) { 5408 warn_report("Ambiguous CPU model string. " 5409 "Don't mix both \"+%s\" and \"%s=%s\"", 5410 name, name, val); 5411 ambiguous = true; 5412 } 5413 if (g_list_find_custom(minus_features, name, compare_string)) { 5414 warn_report("Ambiguous CPU model string. " 5415 "Don't mix both \"-%s\" and \"%s=%s\"", 5416 name, name, val); 5417 ambiguous = true; 5418 } 5419 5420 /* Special case: */ 5421 if (!strcmp(name, "tsc-freq")) { 5422 int ret; 5423 uint64_t tsc_freq; 5424 5425 ret = qemu_strtosz_metric(val, NULL, &tsc_freq); 5426 if (ret < 0 || tsc_freq > INT64_MAX) { 5427 error_setg(errp, "bad numerical value %s", val); 5428 return; 5429 } 5430 snprintf(num, sizeof(num), "%" PRId64, tsc_freq); 5431 val = num; 5432 name = "tsc-frequency"; 5433 } 5434 5435 prop = g_new0(typeof(*prop), 1); 5436 prop->driver = typename; 5437 prop->property = g_strdup(name); 5438 prop->value = g_strdup(val); 5439 qdev_prop_register_global(prop); 5440 } 5441 5442 if (ambiguous) { 5443 warn_report("Compatibility of ambiguous CPU model " 5444 "strings won't be kept on future QEMU versions"); 5445 } 5446 } 5447 5448 static void x86_cpu_filter_features(X86CPU *cpu, bool verbose); 5449 5450 /* Build a list with the name of all features on a feature word array */ 5451 static void x86_cpu_list_feature_names(FeatureWordArray features, 5452 strList **list) 5453 { 5454 strList **tail = list; 5455 FeatureWord w; 5456 5457 for (w = 0; w < FEATURE_WORDS; w++) { 5458 uint64_t filtered = features[w]; 5459 int i; 5460 for (i = 0; i < 64; i++) { 5461 if (filtered & (1ULL << i)) { 5462 QAPI_LIST_APPEND(tail, g_strdup(x86_cpu_feature_name(w, i))); 5463 } 5464 } 5465 } 5466 } 5467 5468 static void x86_cpu_get_unavailable_features(Object *obj, Visitor *v, 5469 const char *name, void *opaque, 5470 Error **errp) 5471 { 5472 X86CPU *xc = X86_CPU(obj); 5473 strList *result = NULL; 5474 5475 x86_cpu_list_feature_names(xc->filtered_features, &result); 5476 visit_type_strList(v, "unavailable-features", &result, errp); 5477 } 5478 5479 /* Print all cpuid feature names in featureset 5480 */ 5481 static void listflags(GList *features) 5482 { 5483 size_t len = 0; 5484 GList *tmp; 5485 5486 for (tmp = features; tmp; tmp = tmp->next) { 5487 const char *name = tmp->data; 5488 if ((len + strlen(name) + 1) >= 75) { 5489 qemu_printf("\n"); 5490 len = 0; 5491 } 5492 qemu_printf("%s%s", len == 0 ? " " : " ", name); 5493 len += strlen(name) + 1; 5494 } 5495 qemu_printf("\n"); 5496 } 5497 5498 /* Sort alphabetically by type name, respecting X86CPUClass::ordering. */ 5499 static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b) 5500 { 5501 ObjectClass *class_a = (ObjectClass *)a; 5502 ObjectClass *class_b = (ObjectClass *)b; 5503 X86CPUClass *cc_a = X86_CPU_CLASS(class_a); 5504 X86CPUClass *cc_b = X86_CPU_CLASS(class_b); 5505 int ret; 5506 5507 if (cc_a->ordering != cc_b->ordering) { 5508 ret = cc_a->ordering - cc_b->ordering; 5509 } else { 5510 g_autofree char *name_a = x86_cpu_class_get_model_name(cc_a); 5511 g_autofree char *name_b = x86_cpu_class_get_model_name(cc_b); 5512 ret = strcmp(name_a, name_b); 5513 } 5514 return ret; 5515 } 5516 5517 static GSList *get_sorted_cpu_model_list(void) 5518 { 5519 GSList *list = object_class_get_list(TYPE_X86_CPU, false); 5520 list = g_slist_sort(list, x86_cpu_list_compare); 5521 return list; 5522 } 5523 5524 static char *x86_cpu_class_get_model_id(X86CPUClass *xc) 5525 { 5526 Object *obj = object_new_with_class(OBJECT_CLASS(xc)); 5527 char *r = object_property_get_str(obj, "model-id", &error_abort); 5528 object_unref(obj); 5529 return r; 5530 } 5531 5532 static char *x86_cpu_class_get_alias_of(X86CPUClass *cc) 5533 { 5534 X86CPUVersion version; 5535 5536 if (!cc->model || !cc->model->is_alias) { 5537 return NULL; 5538 } 5539 version = x86_cpu_model_resolve_version(cc->model); 5540 if (version <= 0) { 5541 return NULL; 5542 } 5543 return x86_cpu_versioned_model_name(cc->model->cpudef, version); 5544 } 5545 5546 static void x86_cpu_list_entry(gpointer data, gpointer user_data) 5547 { 5548 ObjectClass *oc = data; 5549 X86CPUClass *cc = X86_CPU_CLASS(oc); 5550 g_autofree char *name = x86_cpu_class_get_model_name(cc); 5551 g_autofree char *desc = g_strdup(cc->model_description); 5552 g_autofree char *alias_of = x86_cpu_class_get_alias_of(cc); 5553 g_autofree char *model_id = x86_cpu_class_get_model_id(cc); 5554 5555 if (!desc && alias_of) { 5556 if (cc->model && cc->model->version == CPU_VERSION_AUTO) { 5557 desc = g_strdup("(alias configured by machine type)"); 5558 } else { 5559 desc = g_strdup_printf("(alias of %s)", alias_of); 5560 } 5561 } 5562 if (!desc && cc->model && cc->model->note) { 5563 desc = g_strdup_printf("%s [%s]", model_id, cc->model->note); 5564 } 5565 if (!desc) { 5566 desc = g_strdup_printf("%s", model_id); 5567 } 5568 5569 if (cc->model && cc->model->cpudef->deprecation_note) { 5570 g_autofree char *olddesc = desc; 5571 desc = g_strdup_printf("%s (deprecated)", olddesc); 5572 } 5573 5574 qemu_printf("x86 %-20s %s\n", name, desc); 5575 } 5576 5577 /* list available CPU models and flags */ 5578 void x86_cpu_list(void) 5579 { 5580 int i, j; 5581 GSList *list; 5582 GList *names = NULL; 5583 5584 qemu_printf("Available CPUs:\n"); 5585 list = get_sorted_cpu_model_list(); 5586 g_slist_foreach(list, x86_cpu_list_entry, NULL); 5587 g_slist_free(list); 5588 5589 names = NULL; 5590 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) { 5591 FeatureWordInfo *fw = &feature_word_info[i]; 5592 for (j = 0; j < 64; j++) { 5593 if (fw->feat_names[j]) { 5594 names = g_list_append(names, (gpointer)fw->feat_names[j]); 5595 } 5596 } 5597 } 5598 5599 names = g_list_sort(names, (GCompareFunc)strcmp); 5600 5601 qemu_printf("\nRecognized CPUID flags:\n"); 5602 listflags(names); 5603 qemu_printf("\n"); 5604 g_list_free(names); 5605 } 5606 5607 #ifndef CONFIG_USER_ONLY 5608 5609 /* Check for missing features that may prevent the CPU class from 5610 * running using the current machine and accelerator. 5611 */ 5612 static void x86_cpu_class_check_missing_features(X86CPUClass *xcc, 5613 strList **list) 5614 { 5615 strList **tail = list; 5616 X86CPU *xc; 5617 Error *err = NULL; 5618 5619 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) { 5620 QAPI_LIST_APPEND(tail, g_strdup("kvm")); 5621 return; 5622 } 5623 5624 xc = X86_CPU(object_new_with_class(OBJECT_CLASS(xcc))); 5625 5626 x86_cpu_expand_features(xc, &err); 5627 if (err) { 5628 /* Errors at x86_cpu_expand_features should never happen, 5629 * but in case it does, just report the model as not 5630 * runnable at all using the "type" property. 5631 */ 5632 QAPI_LIST_APPEND(tail, g_strdup("type")); 5633 error_free(err); 5634 } 5635 5636 x86_cpu_filter_features(xc, false); 5637 5638 x86_cpu_list_feature_names(xc->filtered_features, tail); 5639 5640 object_unref(OBJECT(xc)); 5641 } 5642 5643 static void x86_cpu_definition_entry(gpointer data, gpointer user_data) 5644 { 5645 ObjectClass *oc = data; 5646 X86CPUClass *cc = X86_CPU_CLASS(oc); 5647 CpuDefinitionInfoList **cpu_list = user_data; 5648 CpuDefinitionInfo *info; 5649 5650 info = g_malloc0(sizeof(*info)); 5651 info->name = x86_cpu_class_get_model_name(cc); 5652 x86_cpu_class_check_missing_features(cc, &info->unavailable_features); 5653 info->has_unavailable_features = true; 5654 info->q_typename = g_strdup(object_class_get_name(oc)); 5655 info->migration_safe = cc->migration_safe; 5656 info->has_migration_safe = true; 5657 info->q_static = cc->static_model; 5658 if (cc->model && cc->model->cpudef->deprecation_note) { 5659 info->deprecated = true; 5660 } else { 5661 info->deprecated = false; 5662 } 5663 /* 5664 * Old machine types won't report aliases, so that alias translation 5665 * doesn't break compatibility with previous QEMU versions. 5666 */ 5667 if (default_cpu_version != CPU_VERSION_LEGACY) { 5668 info->alias_of = x86_cpu_class_get_alias_of(cc); 5669 } 5670 5671 QAPI_LIST_PREPEND(*cpu_list, info); 5672 } 5673 5674 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) 5675 { 5676 CpuDefinitionInfoList *cpu_list = NULL; 5677 GSList *list = get_sorted_cpu_model_list(); 5678 g_slist_foreach(list, x86_cpu_definition_entry, &cpu_list); 5679 g_slist_free(list); 5680 return cpu_list; 5681 } 5682 5683 #endif /* !CONFIG_USER_ONLY */ 5684 5685 uint64_t x86_cpu_get_supported_feature_word(FeatureWord w, 5686 bool migratable_only) 5687 { 5688 FeatureWordInfo *wi = &feature_word_info[w]; 5689 uint64_t r = 0; 5690 5691 if (kvm_enabled()) { 5692 switch (wi->type) { 5693 case CPUID_FEATURE_WORD: 5694 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid.eax, 5695 wi->cpuid.ecx, 5696 wi->cpuid.reg); 5697 break; 5698 case MSR_FEATURE_WORD: 5699 r = kvm_arch_get_supported_msr_feature(kvm_state, 5700 wi->msr.index); 5701 break; 5702 } 5703 } else if (hvf_enabled()) { 5704 if (wi->type != CPUID_FEATURE_WORD) { 5705 return 0; 5706 } 5707 r = hvf_get_supported_cpuid(wi->cpuid.eax, 5708 wi->cpuid.ecx, 5709 wi->cpuid.reg); 5710 } else if (tcg_enabled()) { 5711 r = wi->tcg_features; 5712 } else { 5713 return ~0; 5714 } 5715 #ifndef TARGET_X86_64 5716 if (w == FEAT_8000_0001_EDX) { 5717 /* 5718 * 32-bit TCG can emulate 64-bit compatibility mode. If there is no 5719 * way for userspace to get out of its 32-bit jail, we can leave 5720 * the LM bit set. 5721 */ 5722 uint32_t unavail = tcg_enabled() 5723 ? CPUID_EXT2_LM & ~CPUID_EXT2_KERNEL_FEATURES 5724 : CPUID_EXT2_LM; 5725 r &= ~unavail; 5726 } 5727 #endif 5728 if (migratable_only) { 5729 r &= x86_cpu_get_migratable_flags(w); 5730 } 5731 return r; 5732 } 5733 5734 static void x86_cpu_get_supported_cpuid(uint32_t func, uint32_t index, 5735 uint32_t *eax, uint32_t *ebx, 5736 uint32_t *ecx, uint32_t *edx) 5737 { 5738 if (kvm_enabled()) { 5739 *eax = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EAX); 5740 *ebx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EBX); 5741 *ecx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_ECX); 5742 *edx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EDX); 5743 } else if (hvf_enabled()) { 5744 *eax = hvf_get_supported_cpuid(func, index, R_EAX); 5745 *ebx = hvf_get_supported_cpuid(func, index, R_EBX); 5746 *ecx = hvf_get_supported_cpuid(func, index, R_ECX); 5747 *edx = hvf_get_supported_cpuid(func, index, R_EDX); 5748 } else { 5749 *eax = 0; 5750 *ebx = 0; 5751 *ecx = 0; 5752 *edx = 0; 5753 } 5754 } 5755 5756 static void x86_cpu_get_cache_cpuid(uint32_t func, uint32_t index, 5757 uint32_t *eax, uint32_t *ebx, 5758 uint32_t *ecx, uint32_t *edx) 5759 { 5760 uint32_t level, unused; 5761 5762 /* Only return valid host leaves. */ 5763 switch (func) { 5764 case 2: 5765 case 4: 5766 host_cpuid(0, 0, &level, &unused, &unused, &unused); 5767 break; 5768 case 0x80000005: 5769 case 0x80000006: 5770 case 0x8000001d: 5771 host_cpuid(0x80000000, 0, &level, &unused, &unused, &unused); 5772 break; 5773 default: 5774 return; 5775 } 5776 5777 if (func > level) { 5778 *eax = 0; 5779 *ebx = 0; 5780 *ecx = 0; 5781 *edx = 0; 5782 } else { 5783 host_cpuid(func, index, eax, ebx, ecx, edx); 5784 } 5785 } 5786 5787 /* 5788 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 5789 */ 5790 void x86_cpu_apply_props(X86CPU *cpu, PropValue *props) 5791 { 5792 PropValue *pv; 5793 for (pv = props; pv->prop; pv++) { 5794 if (!pv->value) { 5795 continue; 5796 } 5797 object_property_parse(OBJECT(cpu), pv->prop, pv->value, 5798 &error_abort); 5799 } 5800 } 5801 5802 /* 5803 * Apply properties for the CPU model version specified in model. 5804 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 5805 */ 5806 5807 static void x86_cpu_apply_version_props(X86CPU *cpu, X86CPUModel *model) 5808 { 5809 const X86CPUVersionDefinition *vdef; 5810 X86CPUVersion version = x86_cpu_model_resolve_version(model); 5811 5812 if (version == CPU_VERSION_LEGACY) { 5813 return; 5814 } 5815 5816 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) { 5817 PropValue *p; 5818 5819 for (p = vdef->props; p && p->prop; p++) { 5820 object_property_parse(OBJECT(cpu), p->prop, p->value, 5821 &error_abort); 5822 } 5823 5824 if (vdef->version == version) { 5825 break; 5826 } 5827 } 5828 5829 /* 5830 * If we reached the end of the list, version number was invalid 5831 */ 5832 assert(vdef->version == version); 5833 } 5834 5835 static const CPUCaches *x86_cpu_get_versioned_cache_info(X86CPU *cpu, 5836 X86CPUModel *model) 5837 { 5838 const X86CPUVersionDefinition *vdef; 5839 X86CPUVersion version = x86_cpu_model_resolve_version(model); 5840 const CPUCaches *cache_info = model->cpudef->cache_info; 5841 5842 if (version == CPU_VERSION_LEGACY) { 5843 return cache_info; 5844 } 5845 5846 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) { 5847 if (vdef->cache_info) { 5848 cache_info = vdef->cache_info; 5849 } 5850 5851 if (vdef->version == version) { 5852 break; 5853 } 5854 } 5855 5856 assert(vdef->version == version); 5857 return cache_info; 5858 } 5859 5860 /* 5861 * Load data from X86CPUDefinition into a X86CPU object. 5862 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 5863 */ 5864 static void x86_cpu_load_model(X86CPU *cpu, X86CPUModel *model) 5865 { 5866 const X86CPUDefinition *def = model->cpudef; 5867 CPUX86State *env = &cpu->env; 5868 FeatureWord w; 5869 5870 /*NOTE: any property set by this function should be returned by 5871 * x86_cpu_static_props(), so static expansion of 5872 * query-cpu-model-expansion is always complete. 5873 */ 5874 5875 /* CPU models only set _minimum_ values for level/xlevel: */ 5876 object_property_set_uint(OBJECT(cpu), "min-level", def->level, 5877 &error_abort); 5878 object_property_set_uint(OBJECT(cpu), "min-xlevel", def->xlevel, 5879 &error_abort); 5880 5881 object_property_set_int(OBJECT(cpu), "family", def->family, &error_abort); 5882 object_property_set_int(OBJECT(cpu), "model", def->model, &error_abort); 5883 object_property_set_int(OBJECT(cpu), "stepping", def->stepping, 5884 &error_abort); 5885 object_property_set_str(OBJECT(cpu), "model-id", def->model_id, 5886 &error_abort); 5887 for (w = 0; w < FEATURE_WORDS; w++) { 5888 env->features[w] = def->features[w]; 5889 } 5890 5891 /* legacy-cache defaults to 'off' if CPU model provides cache info */ 5892 cpu->legacy_cache = !x86_cpu_get_versioned_cache_info(cpu, model); 5893 5894 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR; 5895 5896 /* sysenter isn't supported in compatibility mode on AMD, 5897 * syscall isn't supported in compatibility mode on Intel. 5898 * Normally we advertise the actual CPU vendor, but you can 5899 * override this using the 'vendor' property if you want to use 5900 * KVM's sysenter/syscall emulation in compatibility mode and 5901 * when doing cross vendor migration 5902 */ 5903 5904 /* 5905 * vendor property is set here but then overloaded with the 5906 * host cpu vendor for KVM and HVF. 5907 */ 5908 object_property_set_str(OBJECT(cpu), "vendor", def->vendor, &error_abort); 5909 5910 x86_cpu_apply_version_props(cpu, model); 5911 5912 /* 5913 * Properties in versioned CPU model are not user specified features. 5914 * We can simply clear env->user_features here since it will be filled later 5915 * in x86_cpu_expand_features() based on plus_features and minus_features. 5916 */ 5917 memset(&env->user_features, 0, sizeof(env->user_features)); 5918 } 5919 5920 static const gchar *x86_gdb_arch_name(CPUState *cs) 5921 { 5922 #ifdef TARGET_X86_64 5923 return "i386:x86-64"; 5924 #else 5925 return "i386"; 5926 #endif 5927 } 5928 5929 static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data) 5930 { 5931 X86CPUModel *model = data; 5932 X86CPUClass *xcc = X86_CPU_CLASS(oc); 5933 CPUClass *cc = CPU_CLASS(oc); 5934 5935 xcc->model = model; 5936 xcc->migration_safe = true; 5937 cc->deprecation_note = model->cpudef->deprecation_note; 5938 } 5939 5940 static void x86_register_cpu_model_type(const char *name, X86CPUModel *model) 5941 { 5942 g_autofree char *typename = x86_cpu_type_name(name); 5943 TypeInfo ti = { 5944 .name = typename, 5945 .parent = TYPE_X86_CPU, 5946 .class_init = x86_cpu_cpudef_class_init, 5947 .class_data = model, 5948 }; 5949 5950 type_register(&ti); 5951 } 5952 5953 5954 /* 5955 * register builtin_x86_defs; 5956 * "max", "base" and subclasses ("host") are not registered here. 5957 * See x86_cpu_register_types for all model registrations. 5958 */ 5959 static void x86_register_cpudef_types(const X86CPUDefinition *def) 5960 { 5961 X86CPUModel *m; 5962 const X86CPUVersionDefinition *vdef; 5963 5964 /* AMD aliases are handled at runtime based on CPUID vendor, so 5965 * they shouldn't be set on the CPU model table. 5966 */ 5967 assert(!(def->features[FEAT_8000_0001_EDX] & CPUID_EXT2_AMD_ALIASES)); 5968 /* catch mistakes instead of silently truncating model_id when too long */ 5969 assert(def->model_id && strlen(def->model_id) <= 48); 5970 5971 /* Unversioned model: */ 5972 m = g_new0(X86CPUModel, 1); 5973 m->cpudef = def; 5974 m->version = CPU_VERSION_AUTO; 5975 m->is_alias = true; 5976 x86_register_cpu_model_type(def->name, m); 5977 5978 /* Versioned models: */ 5979 5980 for (vdef = x86_cpu_def_get_versions(def); vdef->version; vdef++) { 5981 g_autofree char *name = 5982 x86_cpu_versioned_model_name(def, vdef->version); 5983 5984 m = g_new0(X86CPUModel, 1); 5985 m->cpudef = def; 5986 m->version = vdef->version; 5987 m->note = vdef->note; 5988 x86_register_cpu_model_type(name, m); 5989 5990 if (vdef->alias) { 5991 X86CPUModel *am = g_new0(X86CPUModel, 1); 5992 am->cpudef = def; 5993 am->version = vdef->version; 5994 am->is_alias = true; 5995 x86_register_cpu_model_type(vdef->alias, am); 5996 } 5997 } 5998 5999 } 6000 6001 uint32_t cpu_x86_virtual_addr_width(CPUX86State *env) 6002 { 6003 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57) { 6004 return 57; /* 57 bits virtual */ 6005 } else { 6006 return 48; /* 48 bits virtual */ 6007 } 6008 } 6009 6010 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, 6011 uint32_t *eax, uint32_t *ebx, 6012 uint32_t *ecx, uint32_t *edx) 6013 { 6014 X86CPU *cpu = env_archcpu(env); 6015 CPUState *cs = env_cpu(env); 6016 uint32_t die_offset; 6017 uint32_t limit; 6018 uint32_t signature[3]; 6019 X86CPUTopoInfo topo_info; 6020 6021 topo_info.dies_per_pkg = env->nr_dies; 6022 topo_info.cores_per_die = cs->nr_cores; 6023 topo_info.threads_per_core = cs->nr_threads; 6024 6025 /* Calculate & apply limits for different index ranges */ 6026 if (index >= 0xC0000000) { 6027 limit = env->cpuid_xlevel2; 6028 } else if (index >= 0x80000000) { 6029 limit = env->cpuid_xlevel; 6030 } else if (index >= 0x40000000) { 6031 limit = 0x40000001; 6032 } else { 6033 limit = env->cpuid_level; 6034 } 6035 6036 if (index > limit) { 6037 /* Intel documentation states that invalid EAX input will 6038 * return the same information as EAX=cpuid_level 6039 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID) 6040 */ 6041 index = env->cpuid_level; 6042 } 6043 6044 switch(index) { 6045 case 0: 6046 *eax = env->cpuid_level; 6047 *ebx = env->cpuid_vendor1; 6048 *edx = env->cpuid_vendor2; 6049 *ecx = env->cpuid_vendor3; 6050 break; 6051 case 1: 6052 *eax = env->cpuid_version; 6053 *ebx = (cpu->apic_id << 24) | 6054 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */ 6055 *ecx = env->features[FEAT_1_ECX]; 6056 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) { 6057 *ecx |= CPUID_EXT_OSXSAVE; 6058 } 6059 *edx = env->features[FEAT_1_EDX]; 6060 if (cs->nr_cores * cs->nr_threads > 1) { 6061 *ebx |= (cs->nr_cores * cs->nr_threads) << 16; 6062 *edx |= CPUID_HT; 6063 } 6064 if (!cpu->enable_pmu) { 6065 *ecx &= ~CPUID_EXT_PDCM; 6066 } 6067 break; 6068 case 2: 6069 /* cache info: needed for Pentium Pro compatibility */ 6070 if (cpu->cache_info_passthrough) { 6071 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 6072 break; 6073 } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { 6074 *eax = *ebx = *ecx = *edx = 0; 6075 break; 6076 } 6077 *eax = 1; /* Number of CPUID[EAX=2] calls required */ 6078 *ebx = 0; 6079 if (!cpu->enable_l3_cache) { 6080 *ecx = 0; 6081 } else { 6082 *ecx = cpuid2_cache_descriptor(env->cache_info_cpuid2.l3_cache); 6083 } 6084 *edx = (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1d_cache) << 16) | 6085 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1i_cache) << 8) | 6086 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l2_cache)); 6087 break; 6088 case 4: 6089 /* cache info: needed for Core compatibility */ 6090 if (cpu->cache_info_passthrough) { 6091 x86_cpu_get_cache_cpuid(index, count, eax, ebx, ecx, edx); 6092 /* 6093 * QEMU has its own number of cores/logical cpus, 6094 * set 24..14, 31..26 bit to configured values 6095 */ 6096 if (*eax & 31) { 6097 int host_vcpus_per_cache = 1 + ((*eax & 0x3FFC000) >> 14); 6098 int vcpus_per_socket = env->nr_dies * cs->nr_cores * 6099 cs->nr_threads; 6100 if (cs->nr_cores > 1) { 6101 *eax &= ~0xFC000000; 6102 *eax |= (pow2ceil(cs->nr_cores) - 1) << 26; 6103 } 6104 if (host_vcpus_per_cache > vcpus_per_socket) { 6105 *eax &= ~0x3FFC000; 6106 *eax |= (pow2ceil(vcpus_per_socket) - 1) << 14; 6107 } 6108 } 6109 } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { 6110 *eax = *ebx = *ecx = *edx = 0; 6111 } else { 6112 *eax = 0; 6113 switch (count) { 6114 case 0: /* L1 dcache info */ 6115 encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache, 6116 1, cs->nr_cores, 6117 eax, ebx, ecx, edx); 6118 break; 6119 case 1: /* L1 icache info */ 6120 encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache, 6121 1, cs->nr_cores, 6122 eax, ebx, ecx, edx); 6123 break; 6124 case 2: /* L2 cache info */ 6125 encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache, 6126 cs->nr_threads, cs->nr_cores, 6127 eax, ebx, ecx, edx); 6128 break; 6129 case 3: /* L3 cache info */ 6130 die_offset = apicid_die_offset(&topo_info); 6131 if (cpu->enable_l3_cache) { 6132 encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache, 6133 (1 << die_offset), cs->nr_cores, 6134 eax, ebx, ecx, edx); 6135 break; 6136 } 6137 /* fall through */ 6138 default: /* end of info */ 6139 *eax = *ebx = *ecx = *edx = 0; 6140 break; 6141 } 6142 } 6143 break; 6144 case 5: 6145 /* MONITOR/MWAIT Leaf */ 6146 *eax = cpu->mwait.eax; /* Smallest monitor-line size in bytes */ 6147 *ebx = cpu->mwait.ebx; /* Largest monitor-line size in bytes */ 6148 *ecx = cpu->mwait.ecx; /* flags */ 6149 *edx = cpu->mwait.edx; /* mwait substates */ 6150 break; 6151 case 6: 6152 /* Thermal and Power Leaf */ 6153 *eax = env->features[FEAT_6_EAX]; 6154 *ebx = 0; 6155 *ecx = 0; 6156 *edx = 0; 6157 break; 6158 case 7: 6159 /* Structured Extended Feature Flags Enumeration Leaf */ 6160 if (count == 0) { 6161 uint32_t eax_0_unused, ebx_0, ecx_0, edx_0_unused; 6162 6163 /* Maximum ECX value for sub-leaves */ 6164 *eax = env->cpuid_level_func7; 6165 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */ 6166 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */ 6167 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) { 6168 *ecx |= CPUID_7_0_ECX_OSPKE; 6169 } 6170 *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */ 6171 6172 /* 6173 * SGX cannot be emulated in software. If hardware does not 6174 * support enabling SGX and/or SGX flexible launch control, 6175 * then we need to update the VM's CPUID values accordingly. 6176 */ 6177 x86_cpu_get_supported_cpuid(0x7, 0, 6178 &eax_0_unused, &ebx_0, 6179 &ecx_0, &edx_0_unused); 6180 if ((*ebx & CPUID_7_0_EBX_SGX) && !(ebx_0 & CPUID_7_0_EBX_SGX)) { 6181 *ebx &= ~CPUID_7_0_EBX_SGX; 6182 } 6183 6184 if ((*ecx & CPUID_7_0_ECX_SGX_LC) 6185 && (!(*ebx & CPUID_7_0_EBX_SGX) || !(ecx_0 & CPUID_7_0_ECX_SGX_LC))) { 6186 *ecx &= ~CPUID_7_0_ECX_SGX_LC; 6187 } 6188 } else if (count == 1) { 6189 *eax = env->features[FEAT_7_1_EAX]; 6190 *edx = env->features[FEAT_7_1_EDX]; 6191 *ebx = 0; 6192 *ecx = 0; 6193 } else if (count == 2) { 6194 *edx = env->features[FEAT_7_2_EDX]; 6195 *eax = 0; 6196 *ebx = 0; 6197 *ecx = 0; 6198 } else { 6199 *eax = 0; 6200 *ebx = 0; 6201 *ecx = 0; 6202 *edx = 0; 6203 } 6204 break; 6205 case 9: 6206 /* Direct Cache Access Information Leaf */ 6207 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */ 6208 *ebx = 0; 6209 *ecx = 0; 6210 *edx = 0; 6211 break; 6212 case 0xA: 6213 /* Architectural Performance Monitoring Leaf */ 6214 if (cpu->enable_pmu) { 6215 x86_cpu_get_supported_cpuid(0xA, count, eax, ebx, ecx, edx); 6216 } else { 6217 *eax = 0; 6218 *ebx = 0; 6219 *ecx = 0; 6220 *edx = 0; 6221 } 6222 break; 6223 case 0xB: 6224 /* Extended Topology Enumeration Leaf */ 6225 if (!cpu->enable_cpuid_0xb) { 6226 *eax = *ebx = *ecx = *edx = 0; 6227 break; 6228 } 6229 6230 *ecx = count & 0xff; 6231 *edx = cpu->apic_id; 6232 6233 switch (count) { 6234 case 0: 6235 *eax = apicid_core_offset(&topo_info); 6236 *ebx = cs->nr_threads; 6237 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT; 6238 break; 6239 case 1: 6240 *eax = apicid_pkg_offset(&topo_info); 6241 *ebx = cs->nr_cores * cs->nr_threads; 6242 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE; 6243 break; 6244 default: 6245 *eax = 0; 6246 *ebx = 0; 6247 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID; 6248 } 6249 6250 assert(!(*eax & ~0x1f)); 6251 *ebx &= 0xffff; /* The count doesn't need to be reliable. */ 6252 break; 6253 case 0x1C: 6254 if (cpu->enable_pmu && (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) { 6255 x86_cpu_get_supported_cpuid(0x1C, 0, eax, ebx, ecx, edx); 6256 *edx = 0; 6257 } 6258 break; 6259 case 0x1F: 6260 /* V2 Extended Topology Enumeration Leaf */ 6261 if (env->nr_dies < 2) { 6262 *eax = *ebx = *ecx = *edx = 0; 6263 break; 6264 } 6265 6266 *ecx = count & 0xff; 6267 *edx = cpu->apic_id; 6268 switch (count) { 6269 case 0: 6270 *eax = apicid_core_offset(&topo_info); 6271 *ebx = cs->nr_threads; 6272 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT; 6273 break; 6274 case 1: 6275 *eax = apicid_die_offset(&topo_info); 6276 *ebx = cs->nr_cores * cs->nr_threads; 6277 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE; 6278 break; 6279 case 2: 6280 *eax = apicid_pkg_offset(&topo_info); 6281 *ebx = env->nr_dies * cs->nr_cores * cs->nr_threads; 6282 *ecx |= CPUID_TOPOLOGY_LEVEL_DIE; 6283 break; 6284 default: 6285 *eax = 0; 6286 *ebx = 0; 6287 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID; 6288 } 6289 assert(!(*eax & ~0x1f)); 6290 *ebx &= 0xffff; /* The count doesn't need to be reliable. */ 6291 break; 6292 case 0xD: { 6293 /* Processor Extended State */ 6294 *eax = 0; 6295 *ebx = 0; 6296 *ecx = 0; 6297 *edx = 0; 6298 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { 6299 break; 6300 } 6301 6302 if (count == 0) { 6303 *ecx = xsave_area_size(x86_cpu_xsave_xcr0_components(cpu), false); 6304 *eax = env->features[FEAT_XSAVE_XCR0_LO]; 6305 *edx = env->features[FEAT_XSAVE_XCR0_HI]; 6306 /* 6307 * The initial value of xcr0 and ebx == 0, On host without kvm 6308 * commit 412a3c41(e.g., CentOS 6), the ebx's value always == 0 6309 * even through guest update xcr0, this will crash some legacy guest 6310 * (e.g., CentOS 6), So set ebx == ecx to workaround it. 6311 */ 6312 *ebx = kvm_enabled() ? *ecx : xsave_area_size(env->xcr0, false); 6313 } else if (count == 1) { 6314 uint64_t xstate = x86_cpu_xsave_xcr0_components(cpu) | 6315 x86_cpu_xsave_xss_components(cpu); 6316 6317 *eax = env->features[FEAT_XSAVE]; 6318 *ebx = xsave_area_size(xstate, true); 6319 *ecx = env->features[FEAT_XSAVE_XSS_LO]; 6320 *edx = env->features[FEAT_XSAVE_XSS_HI]; 6321 if (kvm_enabled() && cpu->enable_pmu && 6322 (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR) && 6323 (*eax & CPUID_XSAVE_XSAVES)) { 6324 *ecx |= XSTATE_ARCH_LBR_MASK; 6325 } else { 6326 *ecx &= ~XSTATE_ARCH_LBR_MASK; 6327 } 6328 } else if (count == 0xf && cpu->enable_pmu 6329 && (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) { 6330 x86_cpu_get_supported_cpuid(0xD, count, eax, ebx, ecx, edx); 6331 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) { 6332 const ExtSaveArea *esa = &x86_ext_save_areas[count]; 6333 6334 if (x86_cpu_xsave_xcr0_components(cpu) & (1ULL << count)) { 6335 *eax = esa->size; 6336 *ebx = esa->offset; 6337 *ecx = esa->ecx & 6338 (ESA_FEATURE_ALIGN64_MASK | ESA_FEATURE_XFD_MASK); 6339 } else if (x86_cpu_xsave_xss_components(cpu) & (1ULL << count)) { 6340 *eax = esa->size; 6341 *ebx = 0; 6342 *ecx = 1; 6343 } 6344 } 6345 break; 6346 } 6347 case 0x12: 6348 #ifndef CONFIG_USER_ONLY 6349 if (!kvm_enabled() || 6350 !(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX)) { 6351 *eax = *ebx = *ecx = *edx = 0; 6352 break; 6353 } 6354 6355 /* 6356 * SGX sub-leafs CPUID.0x12.{0x2..N} enumerate EPC sections. Retrieve 6357 * the EPC properties, e.g. confidentiality and integrity, from the 6358 * host's first EPC section, i.e. assume there is one EPC section or 6359 * that all EPC sections have the same security properties. 6360 */ 6361 if (count > 1) { 6362 uint64_t epc_addr, epc_size; 6363 6364 if (sgx_epc_get_section(count - 2, &epc_addr, &epc_size)) { 6365 *eax = *ebx = *ecx = *edx = 0; 6366 break; 6367 } 6368 host_cpuid(index, 2, eax, ebx, ecx, edx); 6369 *eax = (uint32_t)(epc_addr & 0xfffff000) | 0x1; 6370 *ebx = (uint32_t)(epc_addr >> 32); 6371 *ecx = (uint32_t)(epc_size & 0xfffff000) | (*ecx & 0xf); 6372 *edx = (uint32_t)(epc_size >> 32); 6373 break; 6374 } 6375 6376 /* 6377 * SGX sub-leafs CPUID.0x12.{0x0,0x1} are heavily dependent on hardware 6378 * and KVM, i.e. QEMU cannot emulate features to override what KVM 6379 * supports. Features can be further restricted by userspace, but not 6380 * made more permissive. 6381 */ 6382 x86_cpu_get_supported_cpuid(0x12, count, eax, ebx, ecx, edx); 6383 6384 if (count == 0) { 6385 *eax &= env->features[FEAT_SGX_12_0_EAX]; 6386 *ebx &= env->features[FEAT_SGX_12_0_EBX]; 6387 } else { 6388 *eax &= env->features[FEAT_SGX_12_1_EAX]; 6389 *ebx &= 0; /* ebx reserve */ 6390 *ecx &= env->features[FEAT_XSAVE_XCR0_LO]; 6391 *edx &= env->features[FEAT_XSAVE_XCR0_HI]; 6392 6393 /* FP and SSE are always allowed regardless of XSAVE/XCR0. */ 6394 *ecx |= XSTATE_FP_MASK | XSTATE_SSE_MASK; 6395 6396 /* Access to PROVISIONKEY requires additional credentials. */ 6397 if ((*eax & (1U << 4)) && 6398 !kvm_enable_sgx_provisioning(cs->kvm_state)) { 6399 *eax &= ~(1U << 4); 6400 } 6401 } 6402 #endif 6403 break; 6404 case 0x14: { 6405 /* Intel Processor Trace Enumeration */ 6406 *eax = 0; 6407 *ebx = 0; 6408 *ecx = 0; 6409 *edx = 0; 6410 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) || 6411 !kvm_enabled()) { 6412 break; 6413 } 6414 6415 if (count == 0) { 6416 *eax = INTEL_PT_MAX_SUBLEAF; 6417 *ebx = INTEL_PT_MINIMAL_EBX; 6418 *ecx = INTEL_PT_MINIMAL_ECX; 6419 if (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP) { 6420 *ecx |= CPUID_14_0_ECX_LIP; 6421 } 6422 } else if (count == 1) { 6423 *eax = INTEL_PT_MTC_BITMAP | INTEL_PT_ADDR_RANGES_NUM; 6424 *ebx = INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP; 6425 } 6426 break; 6427 } 6428 case 0x1D: { 6429 /* AMX TILE, for now hardcoded for Sapphire Rapids*/ 6430 *eax = 0; 6431 *ebx = 0; 6432 *ecx = 0; 6433 *edx = 0; 6434 if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) { 6435 break; 6436 } 6437 6438 if (count == 0) { 6439 /* Highest numbered palette subleaf */ 6440 *eax = INTEL_AMX_TILE_MAX_SUBLEAF; 6441 } else if (count == 1) { 6442 *eax = INTEL_AMX_TOTAL_TILE_BYTES | 6443 (INTEL_AMX_BYTES_PER_TILE << 16); 6444 *ebx = INTEL_AMX_BYTES_PER_ROW | (INTEL_AMX_TILE_MAX_NAMES << 16); 6445 *ecx = INTEL_AMX_TILE_MAX_ROWS; 6446 } 6447 break; 6448 } 6449 case 0x1E: { 6450 /* AMX TMUL, for now hardcoded for Sapphire Rapids */ 6451 *eax = 0; 6452 *ebx = 0; 6453 *ecx = 0; 6454 *edx = 0; 6455 if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) { 6456 break; 6457 } 6458 6459 if (count == 0) { 6460 /* Highest numbered palette subleaf */ 6461 *ebx = INTEL_AMX_TMUL_MAX_K | (INTEL_AMX_TMUL_MAX_N << 8); 6462 } 6463 break; 6464 } 6465 case 0x40000000: 6466 /* 6467 * CPUID code in kvm_arch_init_vcpu() ignores stuff 6468 * set here, but we restrict to TCG none the less. 6469 */ 6470 if (tcg_enabled() && cpu->expose_tcg) { 6471 memcpy(signature, "TCGTCGTCGTCG", 12); 6472 *eax = 0x40000001; 6473 *ebx = signature[0]; 6474 *ecx = signature[1]; 6475 *edx = signature[2]; 6476 } else { 6477 *eax = 0; 6478 *ebx = 0; 6479 *ecx = 0; 6480 *edx = 0; 6481 } 6482 break; 6483 case 0x40000001: 6484 *eax = 0; 6485 *ebx = 0; 6486 *ecx = 0; 6487 *edx = 0; 6488 break; 6489 case 0x80000000: 6490 *eax = env->cpuid_xlevel; 6491 *ebx = env->cpuid_vendor1; 6492 *edx = env->cpuid_vendor2; 6493 *ecx = env->cpuid_vendor3; 6494 break; 6495 case 0x80000001: 6496 *eax = env->cpuid_version; 6497 *ebx = 0; 6498 *ecx = env->features[FEAT_8000_0001_ECX]; 6499 *edx = env->features[FEAT_8000_0001_EDX]; 6500 6501 /* The Linux kernel checks for the CMPLegacy bit and 6502 * discards multiple thread information if it is set. 6503 * So don't set it here for Intel to make Linux guests happy. 6504 */ 6505 if (cs->nr_cores * cs->nr_threads > 1) { 6506 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 || 6507 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 || 6508 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) { 6509 *ecx |= 1 << 1; /* CmpLegacy bit */ 6510 } 6511 } 6512 if (tcg_enabled() && env->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && 6513 !(env->hflags & HF_LMA_MASK)) { 6514 *edx &= ~CPUID_EXT2_SYSCALL; 6515 } 6516 break; 6517 case 0x80000002: 6518 case 0x80000003: 6519 case 0x80000004: 6520 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0]; 6521 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1]; 6522 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2]; 6523 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3]; 6524 break; 6525 case 0x80000005: 6526 /* cache info (L1 cache) */ 6527 if (cpu->cache_info_passthrough) { 6528 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 6529 break; 6530 } 6531 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | 6532 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES); 6533 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | 6534 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES); 6535 *ecx = encode_cache_cpuid80000005(env->cache_info_amd.l1d_cache); 6536 *edx = encode_cache_cpuid80000005(env->cache_info_amd.l1i_cache); 6537 break; 6538 case 0x80000006: 6539 /* cache info (L2 cache) */ 6540 if (cpu->cache_info_passthrough) { 6541 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 6542 break; 6543 } 6544 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | 6545 (L2_DTLB_2M_ENTRIES << 16) | 6546 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | 6547 (L2_ITLB_2M_ENTRIES); 6548 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | 6549 (L2_DTLB_4K_ENTRIES << 16) | 6550 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | 6551 (L2_ITLB_4K_ENTRIES); 6552 encode_cache_cpuid80000006(env->cache_info_amd.l2_cache, 6553 cpu->enable_l3_cache ? 6554 env->cache_info_amd.l3_cache : NULL, 6555 ecx, edx); 6556 break; 6557 case 0x80000007: 6558 *eax = 0; 6559 *ebx = 0; 6560 *ecx = 0; 6561 *edx = env->features[FEAT_8000_0007_EDX]; 6562 break; 6563 case 0x80000008: 6564 /* virtual & phys address size in low 2 bytes. */ 6565 *eax = cpu->phys_bits; 6566 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 6567 /* 64 bit processor */ 6568 *eax |= (cpu_x86_virtual_addr_width(env) << 8); 6569 } 6570 *ebx = env->features[FEAT_8000_0008_EBX]; 6571 if (cs->nr_cores * cs->nr_threads > 1) { 6572 /* 6573 * Bits 15:12 is "The number of bits in the initial 6574 * Core::X86::Apic::ApicId[ApicId] value that indicate 6575 * thread ID within a package". 6576 * Bits 7:0 is "The number of threads in the package is NC+1" 6577 */ 6578 *ecx = (apicid_pkg_offset(&topo_info) << 12) | 6579 ((cs->nr_cores * cs->nr_threads) - 1); 6580 } else { 6581 *ecx = 0; 6582 } 6583 *edx = 0; 6584 break; 6585 case 0x8000000A: 6586 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { 6587 *eax = 0x00000001; /* SVM Revision */ 6588 *ebx = 0x00000010; /* nr of ASIDs */ 6589 *ecx = 0; 6590 *edx = env->features[FEAT_SVM]; /* optional features */ 6591 } else { 6592 *eax = 0; 6593 *ebx = 0; 6594 *ecx = 0; 6595 *edx = 0; 6596 } 6597 break; 6598 case 0x8000001D: 6599 *eax = 0; 6600 if (cpu->cache_info_passthrough) { 6601 x86_cpu_get_cache_cpuid(index, count, eax, ebx, ecx, edx); 6602 break; 6603 } 6604 switch (count) { 6605 case 0: /* L1 dcache info */ 6606 encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache, 6607 &topo_info, eax, ebx, ecx, edx); 6608 break; 6609 case 1: /* L1 icache info */ 6610 encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache, 6611 &topo_info, eax, ebx, ecx, edx); 6612 break; 6613 case 2: /* L2 cache info */ 6614 encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache, 6615 &topo_info, eax, ebx, ecx, edx); 6616 break; 6617 case 3: /* L3 cache info */ 6618 encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache, 6619 &topo_info, eax, ebx, ecx, edx); 6620 break; 6621 default: /* end of info */ 6622 *eax = *ebx = *ecx = *edx = 0; 6623 break; 6624 } 6625 break; 6626 case 0x8000001E: 6627 if (cpu->core_id <= 255) { 6628 encode_topo_cpuid8000001e(cpu, &topo_info, eax, ebx, ecx, edx); 6629 } else { 6630 *eax = 0; 6631 *ebx = 0; 6632 *ecx = 0; 6633 *edx = 0; 6634 } 6635 break; 6636 case 0xC0000000: 6637 *eax = env->cpuid_xlevel2; 6638 *ebx = 0; 6639 *ecx = 0; 6640 *edx = 0; 6641 break; 6642 case 0xC0000001: 6643 /* Support for VIA CPU's CPUID instruction */ 6644 *eax = env->cpuid_version; 6645 *ebx = 0; 6646 *ecx = 0; 6647 *edx = env->features[FEAT_C000_0001_EDX]; 6648 break; 6649 case 0xC0000002: 6650 case 0xC0000003: 6651 case 0xC0000004: 6652 /* Reserved for the future, and now filled with zero */ 6653 *eax = 0; 6654 *ebx = 0; 6655 *ecx = 0; 6656 *edx = 0; 6657 break; 6658 case 0x8000001F: 6659 *eax = *ebx = *ecx = *edx = 0; 6660 if (sev_enabled()) { 6661 *eax = 0x2; 6662 *eax |= sev_es_enabled() ? 0x8 : 0; 6663 *ebx = sev_get_cbit_position() & 0x3f; /* EBX[5:0] */ 6664 *ebx |= (sev_get_reduced_phys_bits() & 0x3f) << 6; /* EBX[11:6] */ 6665 } 6666 break; 6667 case 0x80000021: 6668 *eax = env->features[FEAT_8000_0021_EAX]; 6669 *ebx = *ecx = *edx = 0; 6670 break; 6671 default: 6672 /* reserved values: zero */ 6673 *eax = 0; 6674 *ebx = 0; 6675 *ecx = 0; 6676 *edx = 0; 6677 break; 6678 } 6679 } 6680 6681 static void x86_cpu_set_sgxlepubkeyhash(CPUX86State *env) 6682 { 6683 #ifndef CONFIG_USER_ONLY 6684 /* Those default values are defined in Skylake HW */ 6685 env->msr_ia32_sgxlepubkeyhash[0] = 0xa6053e051270b7acULL; 6686 env->msr_ia32_sgxlepubkeyhash[1] = 0x6cfbe8ba8b3b413dULL; 6687 env->msr_ia32_sgxlepubkeyhash[2] = 0xc4916d99f2b3735dULL; 6688 env->msr_ia32_sgxlepubkeyhash[3] = 0xd4f8c05909f9bb3bULL; 6689 #endif 6690 } 6691 6692 static void x86_cpu_reset_hold(Object *obj) 6693 { 6694 CPUState *s = CPU(obj); 6695 X86CPU *cpu = X86_CPU(s); 6696 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu); 6697 CPUX86State *env = &cpu->env; 6698 target_ulong cr4; 6699 uint64_t xcr0; 6700 int i; 6701 6702 if (xcc->parent_phases.hold) { 6703 xcc->parent_phases.hold(obj); 6704 } 6705 6706 memset(env, 0, offsetof(CPUX86State, end_reset_fields)); 6707 6708 env->old_exception = -1; 6709 6710 /* init to reset state */ 6711 env->int_ctl = 0; 6712 env->hflags2 |= HF2_GIF_MASK; 6713 env->hflags2 |= HF2_VGIF_MASK; 6714 env->hflags &= ~HF_GUEST_MASK; 6715 6716 cpu_x86_update_cr0(env, 0x60000010); 6717 env->a20_mask = ~0x0; 6718 env->smbase = 0x30000; 6719 env->msr_smi_count = 0; 6720 6721 env->idt.limit = 0xffff; 6722 env->gdt.limit = 0xffff; 6723 env->ldt.limit = 0xffff; 6724 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT); 6725 env->tr.limit = 0xffff; 6726 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT); 6727 6728 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff, 6729 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK | 6730 DESC_R_MASK | DESC_A_MASK); 6731 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff, 6732 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 6733 DESC_A_MASK); 6734 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff, 6735 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 6736 DESC_A_MASK); 6737 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff, 6738 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 6739 DESC_A_MASK); 6740 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff, 6741 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 6742 DESC_A_MASK); 6743 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff, 6744 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 6745 DESC_A_MASK); 6746 6747 env->eip = 0xfff0; 6748 env->regs[R_EDX] = env->cpuid_version; 6749 6750 env->eflags = 0x2; 6751 6752 /* FPU init */ 6753 for (i = 0; i < 8; i++) { 6754 env->fptags[i] = 1; 6755 } 6756 cpu_set_fpuc(env, 0x37f); 6757 6758 env->mxcsr = 0x1f80; 6759 /* All units are in INIT state. */ 6760 env->xstate_bv = 0; 6761 6762 env->pat = 0x0007040600070406ULL; 6763 6764 if (kvm_enabled()) { 6765 /* 6766 * KVM handles TSC = 0 specially and thinks we are hot-plugging 6767 * a new CPU, use 1 instead to force a reset. 6768 */ 6769 if (env->tsc != 0) { 6770 env->tsc = 1; 6771 } 6772 } else { 6773 env->tsc = 0; 6774 } 6775 6776 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT; 6777 if (env->features[FEAT_1_ECX] & CPUID_EXT_MONITOR) { 6778 env->msr_ia32_misc_enable |= MSR_IA32_MISC_ENABLE_MWAIT; 6779 } 6780 6781 memset(env->dr, 0, sizeof(env->dr)); 6782 env->dr[6] = DR6_FIXED_1; 6783 env->dr[7] = DR7_FIXED_1; 6784 cpu_breakpoint_remove_all(s, BP_CPU); 6785 cpu_watchpoint_remove_all(s, BP_CPU); 6786 6787 cr4 = 0; 6788 xcr0 = XSTATE_FP_MASK; 6789 6790 #ifdef CONFIG_USER_ONLY 6791 /* Enable all the features for user-mode. */ 6792 if (env->features[FEAT_1_EDX] & CPUID_SSE) { 6793 xcr0 |= XSTATE_SSE_MASK; 6794 } 6795 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 6796 const ExtSaveArea *esa = &x86_ext_save_areas[i]; 6797 if (!((1 << i) & CPUID_XSTATE_XCR0_MASK)) { 6798 continue; 6799 } 6800 if (env->features[esa->feature] & esa->bits) { 6801 xcr0 |= 1ull << i; 6802 } 6803 } 6804 6805 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) { 6806 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK; 6807 } 6808 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) { 6809 cr4 |= CR4_FSGSBASE_MASK; 6810 } 6811 #endif 6812 6813 env->xcr0 = xcr0; 6814 cpu_x86_update_cr4(env, cr4); 6815 6816 /* 6817 * SDM 11.11.5 requires: 6818 * - IA32_MTRR_DEF_TYPE MSR.E = 0 6819 * - IA32_MTRR_PHYSMASKn.V = 0 6820 * All other bits are undefined. For simplification, zero it all. 6821 */ 6822 env->mtrr_deftype = 0; 6823 memset(env->mtrr_var, 0, sizeof(env->mtrr_var)); 6824 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed)); 6825 6826 env->interrupt_injected = -1; 6827 env->exception_nr = -1; 6828 env->exception_pending = 0; 6829 env->exception_injected = 0; 6830 env->exception_has_payload = false; 6831 env->exception_payload = 0; 6832 env->nmi_injected = false; 6833 env->triple_fault_pending = false; 6834 #if !defined(CONFIG_USER_ONLY) 6835 /* We hard-wire the BSP to the first CPU. */ 6836 apic_designate_bsp(cpu->apic_state, s->cpu_index == 0); 6837 6838 s->halted = !cpu_is_bsp(cpu); 6839 6840 if (kvm_enabled()) { 6841 kvm_arch_reset_vcpu(cpu); 6842 } 6843 6844 x86_cpu_set_sgxlepubkeyhash(env); 6845 6846 env->amd_tsc_scale_msr = MSR_AMD64_TSC_RATIO_DEFAULT; 6847 6848 #endif 6849 } 6850 6851 void x86_cpu_after_reset(X86CPU *cpu) 6852 { 6853 #ifndef CONFIG_USER_ONLY 6854 if (kvm_enabled()) { 6855 kvm_arch_after_reset_vcpu(cpu); 6856 } 6857 6858 if (cpu->apic_state) { 6859 device_cold_reset(cpu->apic_state); 6860 } 6861 #endif 6862 } 6863 6864 static void mce_init(X86CPU *cpu) 6865 { 6866 CPUX86State *cenv = &cpu->env; 6867 unsigned int bank; 6868 6869 if (((cenv->cpuid_version >> 8) & 0xf) >= 6 6870 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) == 6871 (CPUID_MCE | CPUID_MCA)) { 6872 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF | 6873 (cpu->enable_lmce ? MCG_LMCE_P : 0); 6874 cenv->mcg_ctl = ~(uint64_t)0; 6875 for (bank = 0; bank < MCE_BANKS_DEF; bank++) { 6876 cenv->mce_banks[bank * 4] = ~(uint64_t)0; 6877 } 6878 } 6879 } 6880 6881 static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value) 6882 { 6883 if (*min < value) { 6884 *min = value; 6885 } 6886 } 6887 6888 /* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */ 6889 static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w) 6890 { 6891 CPUX86State *env = &cpu->env; 6892 FeatureWordInfo *fi = &feature_word_info[w]; 6893 uint32_t eax = fi->cpuid.eax; 6894 uint32_t region = eax & 0xF0000000; 6895 6896 assert(feature_word_info[w].type == CPUID_FEATURE_WORD); 6897 if (!env->features[w]) { 6898 return; 6899 } 6900 6901 switch (region) { 6902 case 0x00000000: 6903 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax); 6904 break; 6905 case 0x80000000: 6906 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax); 6907 break; 6908 case 0xC0000000: 6909 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax); 6910 break; 6911 } 6912 6913 if (eax == 7) { 6914 x86_cpu_adjust_level(cpu, &env->cpuid_min_level_func7, 6915 fi->cpuid.ecx); 6916 } 6917 } 6918 6919 /* Calculate XSAVE components based on the configured CPU feature flags */ 6920 static void x86_cpu_enable_xsave_components(X86CPU *cpu) 6921 { 6922 CPUX86State *env = &cpu->env; 6923 int i; 6924 uint64_t mask; 6925 static bool request_perm; 6926 6927 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { 6928 env->features[FEAT_XSAVE_XCR0_LO] = 0; 6929 env->features[FEAT_XSAVE_XCR0_HI] = 0; 6930 return; 6931 } 6932 6933 mask = 0; 6934 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 6935 const ExtSaveArea *esa = &x86_ext_save_areas[i]; 6936 if (env->features[esa->feature] & esa->bits) { 6937 mask |= (1ULL << i); 6938 } 6939 } 6940 6941 /* Only request permission for first vcpu */ 6942 if (kvm_enabled() && !request_perm) { 6943 kvm_request_xsave_components(cpu, mask); 6944 request_perm = true; 6945 } 6946 6947 env->features[FEAT_XSAVE_XCR0_LO] = mask & CPUID_XSTATE_XCR0_MASK; 6948 env->features[FEAT_XSAVE_XCR0_HI] = mask >> 32; 6949 env->features[FEAT_XSAVE_XSS_LO] = mask & CPUID_XSTATE_XSS_MASK; 6950 env->features[FEAT_XSAVE_XSS_HI] = mask >> 32; 6951 } 6952 6953 /***** Steps involved on loading and filtering CPUID data 6954 * 6955 * When initializing and realizing a CPU object, the steps 6956 * involved in setting up CPUID data are: 6957 * 6958 * 1) Loading CPU model definition (X86CPUDefinition). This is 6959 * implemented by x86_cpu_load_model() and should be completely 6960 * transparent, as it is done automatically by instance_init. 6961 * No code should need to look at X86CPUDefinition structs 6962 * outside instance_init. 6963 * 6964 * 2) CPU expansion. This is done by realize before CPUID 6965 * filtering, and will make sure host/accelerator data is 6966 * loaded for CPU models that depend on host capabilities 6967 * (e.g. "host"). Done by x86_cpu_expand_features(). 6968 * 6969 * 3) CPUID filtering. This initializes extra data related to 6970 * CPUID, and checks if the host supports all capabilities 6971 * required by the CPU. Runnability of a CPU model is 6972 * determined at this step. Done by x86_cpu_filter_features(). 6973 * 6974 * Some operations don't require all steps to be performed. 6975 * More precisely: 6976 * 6977 * - CPU instance creation (instance_init) will run only CPU 6978 * model loading. CPU expansion can't run at instance_init-time 6979 * because host/accelerator data may be not available yet. 6980 * - CPU realization will perform both CPU model expansion and CPUID 6981 * filtering, and return an error in case one of them fails. 6982 * - query-cpu-definitions needs to run all 3 steps. It needs 6983 * to run CPUID filtering, as the 'unavailable-features' 6984 * field is set based on the filtering results. 6985 * - The query-cpu-model-expansion QMP command only needs to run 6986 * CPU model loading and CPU expansion. It should not filter 6987 * any CPUID data based on host capabilities. 6988 */ 6989 6990 /* Expand CPU configuration data, based on configured features 6991 * and host/accelerator capabilities when appropriate. 6992 */ 6993 void x86_cpu_expand_features(X86CPU *cpu, Error **errp) 6994 { 6995 CPUX86State *env = &cpu->env; 6996 FeatureWord w; 6997 int i; 6998 GList *l; 6999 7000 for (l = plus_features; l; l = l->next) { 7001 const char *prop = l->data; 7002 if (!object_property_set_bool(OBJECT(cpu), prop, true, errp)) { 7003 return; 7004 } 7005 } 7006 7007 for (l = minus_features; l; l = l->next) { 7008 const char *prop = l->data; 7009 if (!object_property_set_bool(OBJECT(cpu), prop, false, errp)) { 7010 return; 7011 } 7012 } 7013 7014 /*TODO: Now cpu->max_features doesn't overwrite features 7015 * set using QOM properties, and we can convert 7016 * plus_features & minus_features to global properties 7017 * inside x86_cpu_parse_featurestr() too. 7018 */ 7019 if (cpu->max_features) { 7020 for (w = 0; w < FEATURE_WORDS; w++) { 7021 /* Override only features that weren't set explicitly 7022 * by the user. 7023 */ 7024 env->features[w] |= 7025 x86_cpu_get_supported_feature_word(w, cpu->migratable) & 7026 ~env->user_features[w] & 7027 ~feature_word_info[w].no_autoenable_flags; 7028 } 7029 } 7030 7031 for (i = 0; i < ARRAY_SIZE(feature_dependencies); i++) { 7032 FeatureDep *d = &feature_dependencies[i]; 7033 if (!(env->features[d->from.index] & d->from.mask)) { 7034 uint64_t unavailable_features = env->features[d->to.index] & d->to.mask; 7035 7036 /* Not an error unless the dependent feature was added explicitly. */ 7037 mark_unavailable_features(cpu, d->to.index, 7038 unavailable_features & env->user_features[d->to.index], 7039 "This feature depends on other features that were not requested"); 7040 7041 env->features[d->to.index] &= ~unavailable_features; 7042 } 7043 } 7044 7045 if (!kvm_enabled() || !cpu->expose_kvm) { 7046 env->features[FEAT_KVM] = 0; 7047 } 7048 7049 x86_cpu_enable_xsave_components(cpu); 7050 7051 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */ 7052 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX); 7053 if (cpu->full_cpuid_auto_level) { 7054 x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX); 7055 x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX); 7056 x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX); 7057 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX); 7058 x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EAX); 7059 x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EDX); 7060 x86_cpu_adjust_feat_level(cpu, FEAT_7_2_EDX); 7061 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX); 7062 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX); 7063 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX); 7064 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0008_EBX); 7065 x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX); 7066 x86_cpu_adjust_feat_level(cpu, FEAT_SVM); 7067 x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE); 7068 7069 /* Intel Processor Trace requires CPUID[0x14] */ 7070 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT)) { 7071 if (cpu->intel_pt_auto_level) { 7072 x86_cpu_adjust_level(cpu, &cpu->env.cpuid_min_level, 0x14); 7073 } else if (cpu->env.cpuid_min_level < 0x14) { 7074 mark_unavailable_features(cpu, FEAT_7_0_EBX, 7075 CPUID_7_0_EBX_INTEL_PT, 7076 "Intel PT need CPUID leaf 0x14, please set by \"-cpu ...,intel-pt=on,min-level=0x14\""); 7077 } 7078 } 7079 7080 /* 7081 * Intel CPU topology with multi-dies support requires CPUID[0x1F]. 7082 * For AMD Rome/Milan, cpuid level is 0x10, and guest OS should detect 7083 * extended toplogy by leaf 0xB. Only adjust it for Intel CPU, unless 7084 * cpu->vendor_cpuid_only has been unset for compatibility with older 7085 * machine types. 7086 */ 7087 if ((env->nr_dies > 1) && 7088 (IS_INTEL_CPU(env) || !cpu->vendor_cpuid_only)) { 7089 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x1F); 7090 } 7091 7092 /* SVM requires CPUID[0x8000000A] */ 7093 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { 7094 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A); 7095 } 7096 7097 /* SEV requires CPUID[0x8000001F] */ 7098 if (sev_enabled()) { 7099 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F); 7100 } 7101 7102 if (env->features[FEAT_8000_0021_EAX]) { 7103 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x80000021); 7104 } 7105 7106 /* SGX requires CPUID[0x12] for EPC enumeration */ 7107 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX) { 7108 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x12); 7109 } 7110 } 7111 7112 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */ 7113 if (env->cpuid_level_func7 == UINT32_MAX) { 7114 env->cpuid_level_func7 = env->cpuid_min_level_func7; 7115 } 7116 if (env->cpuid_level == UINT32_MAX) { 7117 env->cpuid_level = env->cpuid_min_level; 7118 } 7119 if (env->cpuid_xlevel == UINT32_MAX) { 7120 env->cpuid_xlevel = env->cpuid_min_xlevel; 7121 } 7122 if (env->cpuid_xlevel2 == UINT32_MAX) { 7123 env->cpuid_xlevel2 = env->cpuid_min_xlevel2; 7124 } 7125 7126 if (kvm_enabled() && !kvm_hyperv_expand_features(cpu, errp)) { 7127 return; 7128 } 7129 } 7130 7131 /* 7132 * Finishes initialization of CPUID data, filters CPU feature 7133 * words based on host availability of each feature. 7134 * 7135 * Returns: 0 if all flags are supported by the host, non-zero otherwise. 7136 */ 7137 static void x86_cpu_filter_features(X86CPU *cpu, bool verbose) 7138 { 7139 CPUX86State *env = &cpu->env; 7140 FeatureWord w; 7141 const char *prefix = NULL; 7142 7143 if (verbose) { 7144 prefix = accel_uses_host_cpuid() 7145 ? "host doesn't support requested feature" 7146 : "TCG doesn't support requested feature"; 7147 } 7148 7149 for (w = 0; w < FEATURE_WORDS; w++) { 7150 uint64_t host_feat = 7151 x86_cpu_get_supported_feature_word(w, false); 7152 uint64_t requested_features = env->features[w]; 7153 uint64_t unavailable_features = requested_features & ~host_feat; 7154 mark_unavailable_features(cpu, w, unavailable_features, prefix); 7155 } 7156 7157 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) { 7158 uint32_t eax_0, ebx_0, ecx_0, edx_0_unused; 7159 uint32_t eax_1, ebx_1, ecx_1_unused, edx_1_unused; 7160 7161 x86_cpu_get_supported_cpuid(0x14, 0, 7162 &eax_0, &ebx_0, &ecx_0, &edx_0_unused); 7163 x86_cpu_get_supported_cpuid(0x14, 1, 7164 &eax_1, &ebx_1, &ecx_1_unused, &edx_1_unused); 7165 7166 if (!eax_0 || 7167 ((ebx_0 & INTEL_PT_MINIMAL_EBX) != INTEL_PT_MINIMAL_EBX) || 7168 ((ecx_0 & INTEL_PT_MINIMAL_ECX) != INTEL_PT_MINIMAL_ECX) || 7169 ((eax_1 & INTEL_PT_MTC_BITMAP) != INTEL_PT_MTC_BITMAP) || 7170 ((eax_1 & INTEL_PT_ADDR_RANGES_NUM_MASK) < 7171 INTEL_PT_ADDR_RANGES_NUM) || 7172 ((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) != 7173 (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) || 7174 ((ecx_0 & CPUID_14_0_ECX_LIP) != 7175 (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP))) { 7176 /* 7177 * Processor Trace capabilities aren't configurable, so if the 7178 * host can't emulate the capabilities we report on 7179 * cpu_x86_cpuid(), intel-pt can't be enabled on the current host. 7180 */ 7181 mark_unavailable_features(cpu, FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT, prefix); 7182 } 7183 } 7184 } 7185 7186 static void x86_cpu_hyperv_realize(X86CPU *cpu) 7187 { 7188 size_t len; 7189 7190 /* Hyper-V vendor id */ 7191 if (!cpu->hyperv_vendor) { 7192 object_property_set_str(OBJECT(cpu), "hv-vendor-id", "Microsoft Hv", 7193 &error_abort); 7194 } 7195 len = strlen(cpu->hyperv_vendor); 7196 if (len > 12) { 7197 warn_report("hv-vendor-id truncated to 12 characters"); 7198 len = 12; 7199 } 7200 memset(cpu->hyperv_vendor_id, 0, 12); 7201 memcpy(cpu->hyperv_vendor_id, cpu->hyperv_vendor, len); 7202 7203 /* 'Hv#1' interface identification*/ 7204 cpu->hyperv_interface_id[0] = 0x31237648; 7205 cpu->hyperv_interface_id[1] = 0; 7206 cpu->hyperv_interface_id[2] = 0; 7207 cpu->hyperv_interface_id[3] = 0; 7208 7209 /* Hypervisor implementation limits */ 7210 cpu->hyperv_limits[0] = 64; 7211 cpu->hyperv_limits[1] = 0; 7212 cpu->hyperv_limits[2] = 0; 7213 } 7214 7215 static void x86_cpu_realizefn(DeviceState *dev, Error **errp) 7216 { 7217 CPUState *cs = CPU(dev); 7218 X86CPU *cpu = X86_CPU(dev); 7219 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev); 7220 CPUX86State *env = &cpu->env; 7221 Error *local_err = NULL; 7222 static bool ht_warned; 7223 unsigned requested_lbr_fmt; 7224 7225 /* Use pc-relative instructions in system-mode */ 7226 #ifndef CONFIG_USER_ONLY 7227 cs->tcg_cflags |= CF_PCREL; 7228 #endif 7229 7230 if (cpu->apic_id == UNASSIGNED_APIC_ID) { 7231 error_setg(errp, "apic-id property was not initialized properly"); 7232 return; 7233 } 7234 7235 /* 7236 * Process Hyper-V enlightenments. 7237 * Note: this currently has to happen before the expansion of CPU features. 7238 */ 7239 x86_cpu_hyperv_realize(cpu); 7240 7241 x86_cpu_expand_features(cpu, &local_err); 7242 if (local_err) { 7243 goto out; 7244 } 7245 7246 /* 7247 * Override env->features[FEAT_PERF_CAPABILITIES].LBR_FMT 7248 * with user-provided setting. 7249 */ 7250 if (cpu->lbr_fmt != ~PERF_CAP_LBR_FMT) { 7251 if ((cpu->lbr_fmt & PERF_CAP_LBR_FMT) != cpu->lbr_fmt) { 7252 error_setg(errp, "invalid lbr-fmt"); 7253 return; 7254 } 7255 env->features[FEAT_PERF_CAPABILITIES] &= ~PERF_CAP_LBR_FMT; 7256 env->features[FEAT_PERF_CAPABILITIES] |= cpu->lbr_fmt; 7257 } 7258 7259 /* 7260 * vPMU LBR is supported when 1) KVM is enabled 2) Option pmu=on and 7261 * 3)vPMU LBR format matches that of host setting. 7262 */ 7263 requested_lbr_fmt = 7264 env->features[FEAT_PERF_CAPABILITIES] & PERF_CAP_LBR_FMT; 7265 if (requested_lbr_fmt && kvm_enabled()) { 7266 uint64_t host_perf_cap = 7267 x86_cpu_get_supported_feature_word(FEAT_PERF_CAPABILITIES, false); 7268 unsigned host_lbr_fmt = host_perf_cap & PERF_CAP_LBR_FMT; 7269 7270 if (!cpu->enable_pmu) { 7271 error_setg(errp, "vPMU: LBR is unsupported without pmu=on"); 7272 return; 7273 } 7274 if (requested_lbr_fmt != host_lbr_fmt) { 7275 error_setg(errp, "vPMU: the lbr-fmt value (0x%x) does not match " 7276 "the host value (0x%x).", 7277 requested_lbr_fmt, host_lbr_fmt); 7278 return; 7279 } 7280 } 7281 7282 x86_cpu_filter_features(cpu, cpu->check_cpuid || cpu->enforce_cpuid); 7283 7284 if (cpu->enforce_cpuid && x86_cpu_have_filtered_features(cpu)) { 7285 error_setg(&local_err, 7286 accel_uses_host_cpuid() ? 7287 "Host doesn't support requested features" : 7288 "TCG doesn't support requested features"); 7289 goto out; 7290 } 7291 7292 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on 7293 * CPUID[1].EDX. 7294 */ 7295 if (IS_AMD_CPU(env)) { 7296 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES; 7297 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX] 7298 & CPUID_EXT2_AMD_ALIASES); 7299 } 7300 7301 x86_cpu_set_sgxlepubkeyhash(env); 7302 7303 /* 7304 * note: the call to the framework needs to happen after feature expansion, 7305 * but before the checks/modifications to ucode_rev, mwait, phys_bits. 7306 * These may be set by the accel-specific code, 7307 * and the results are subsequently checked / assumed in this function. 7308 */ 7309 cpu_exec_realizefn(cs, &local_err); 7310 if (local_err != NULL) { 7311 error_propagate(errp, local_err); 7312 return; 7313 } 7314 7315 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) { 7316 g_autofree char *name = x86_cpu_class_get_model_name(xcc); 7317 error_setg(&local_err, "CPU model '%s' requires KVM or HVF", name); 7318 goto out; 7319 } 7320 7321 if (cpu->ucode_rev == 0) { 7322 /* 7323 * The default is the same as KVM's. Note that this check 7324 * needs to happen after the evenual setting of ucode_rev in 7325 * accel-specific code in cpu_exec_realizefn. 7326 */ 7327 if (IS_AMD_CPU(env)) { 7328 cpu->ucode_rev = 0x01000065; 7329 } else { 7330 cpu->ucode_rev = 0x100000000ULL; 7331 } 7332 } 7333 7334 /* 7335 * mwait extended info: needed for Core compatibility 7336 * We always wake on interrupt even if host does not have the capability. 7337 * 7338 * requires the accel-specific code in cpu_exec_realizefn to 7339 * have already acquired the CPUID data into cpu->mwait. 7340 */ 7341 cpu->mwait.ecx |= CPUID_MWAIT_EMX | CPUID_MWAIT_IBE; 7342 7343 /* For 64bit systems think about the number of physical bits to present. 7344 * ideally this should be the same as the host; anything other than matching 7345 * the host can cause incorrect guest behaviour. 7346 * QEMU used to pick the magic value of 40 bits that corresponds to 7347 * consumer AMD devices but nothing else. 7348 * 7349 * Note that this code assumes features expansion has already been done 7350 * (as it checks for CPUID_EXT2_LM), and also assumes that potential 7351 * phys_bits adjustments to match the host have been already done in 7352 * accel-specific code in cpu_exec_realizefn. 7353 */ 7354 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 7355 if (cpu->phys_bits && 7356 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS || 7357 cpu->phys_bits < 32)) { 7358 error_setg(errp, "phys-bits should be between 32 and %u " 7359 " (but is %u)", 7360 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits); 7361 return; 7362 } 7363 /* 7364 * 0 means it was not explicitly set by the user (or by machine 7365 * compat_props or by the host code in host-cpu.c). 7366 * In this case, the default is the value used by TCG (40). 7367 */ 7368 if (cpu->phys_bits == 0) { 7369 cpu->phys_bits = TCG_PHYS_ADDR_BITS; 7370 } 7371 } else { 7372 /* For 32 bit systems don't use the user set value, but keep 7373 * phys_bits consistent with what we tell the guest. 7374 */ 7375 if (cpu->phys_bits != 0) { 7376 error_setg(errp, "phys-bits is not user-configurable in 32 bit"); 7377 return; 7378 } 7379 7380 if (env->features[FEAT_1_EDX] & (CPUID_PSE36 | CPUID_PAE)) { 7381 cpu->phys_bits = 36; 7382 } else { 7383 cpu->phys_bits = 32; 7384 } 7385 } 7386 7387 /* Cache information initialization */ 7388 if (!cpu->legacy_cache) { 7389 const CPUCaches *cache_info = 7390 x86_cpu_get_versioned_cache_info(cpu, xcc->model); 7391 7392 if (!xcc->model || !cache_info) { 7393 g_autofree char *name = x86_cpu_class_get_model_name(xcc); 7394 error_setg(errp, 7395 "CPU model '%s' doesn't support legacy-cache=off", name); 7396 return; 7397 } 7398 env->cache_info_cpuid2 = env->cache_info_cpuid4 = env->cache_info_amd = 7399 *cache_info; 7400 } else { 7401 /* Build legacy cache information */ 7402 env->cache_info_cpuid2.l1d_cache = &legacy_l1d_cache; 7403 env->cache_info_cpuid2.l1i_cache = &legacy_l1i_cache; 7404 env->cache_info_cpuid2.l2_cache = &legacy_l2_cache_cpuid2; 7405 env->cache_info_cpuid2.l3_cache = &legacy_l3_cache; 7406 7407 env->cache_info_cpuid4.l1d_cache = &legacy_l1d_cache; 7408 env->cache_info_cpuid4.l1i_cache = &legacy_l1i_cache; 7409 env->cache_info_cpuid4.l2_cache = &legacy_l2_cache; 7410 env->cache_info_cpuid4.l3_cache = &legacy_l3_cache; 7411 7412 env->cache_info_amd.l1d_cache = &legacy_l1d_cache_amd; 7413 env->cache_info_amd.l1i_cache = &legacy_l1i_cache_amd; 7414 env->cache_info_amd.l2_cache = &legacy_l2_cache_amd; 7415 env->cache_info_amd.l3_cache = &legacy_l3_cache; 7416 } 7417 7418 #ifndef CONFIG_USER_ONLY 7419 MachineState *ms = MACHINE(qdev_get_machine()); 7420 qemu_register_reset(x86_cpu_machine_reset_cb, cpu); 7421 7422 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || ms->smp.cpus > 1) { 7423 x86_cpu_apic_create(cpu, &local_err); 7424 if (local_err != NULL) { 7425 goto out; 7426 } 7427 } 7428 #endif 7429 7430 mce_init(cpu); 7431 7432 qemu_init_vcpu(cs); 7433 7434 /* 7435 * Most Intel and certain AMD CPUs support hyperthreading. Even though QEMU 7436 * fixes this issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX 7437 * based on inputs (sockets,cores,threads), it is still better to give 7438 * users a warning. 7439 * 7440 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise 7441 * cs->nr_threads hasn't be populated yet and the checking is incorrect. 7442 */ 7443 if (IS_AMD_CPU(env) && 7444 !(env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) && 7445 cs->nr_threads > 1 && !ht_warned) { 7446 warn_report("This family of AMD CPU doesn't support " 7447 "hyperthreading(%d)", 7448 cs->nr_threads); 7449 error_printf("Please configure -smp options properly" 7450 " or try enabling topoext feature.\n"); 7451 ht_warned = true; 7452 } 7453 7454 #ifndef CONFIG_USER_ONLY 7455 x86_cpu_apic_realize(cpu, &local_err); 7456 if (local_err != NULL) { 7457 goto out; 7458 } 7459 #endif /* !CONFIG_USER_ONLY */ 7460 cpu_reset(cs); 7461 7462 xcc->parent_realize(dev, &local_err); 7463 7464 out: 7465 if (local_err != NULL) { 7466 error_propagate(errp, local_err); 7467 return; 7468 } 7469 } 7470 7471 static void x86_cpu_unrealizefn(DeviceState *dev) 7472 { 7473 X86CPU *cpu = X86_CPU(dev); 7474 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev); 7475 7476 #ifndef CONFIG_USER_ONLY 7477 cpu_remove_sync(CPU(dev)); 7478 qemu_unregister_reset(x86_cpu_machine_reset_cb, dev); 7479 #endif 7480 7481 if (cpu->apic_state) { 7482 object_unparent(OBJECT(cpu->apic_state)); 7483 cpu->apic_state = NULL; 7484 } 7485 7486 xcc->parent_unrealize(dev); 7487 } 7488 7489 typedef struct BitProperty { 7490 FeatureWord w; 7491 uint64_t mask; 7492 } BitProperty; 7493 7494 static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name, 7495 void *opaque, Error **errp) 7496 { 7497 X86CPU *cpu = X86_CPU(obj); 7498 BitProperty *fp = opaque; 7499 uint64_t f = cpu->env.features[fp->w]; 7500 bool value = (f & fp->mask) == fp->mask; 7501 visit_type_bool(v, name, &value, errp); 7502 } 7503 7504 static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name, 7505 void *opaque, Error **errp) 7506 { 7507 DeviceState *dev = DEVICE(obj); 7508 X86CPU *cpu = X86_CPU(obj); 7509 BitProperty *fp = opaque; 7510 bool value; 7511 7512 if (dev->realized) { 7513 qdev_prop_set_after_realize(dev, name, errp); 7514 return; 7515 } 7516 7517 if (!visit_type_bool(v, name, &value, errp)) { 7518 return; 7519 } 7520 7521 if (value) { 7522 cpu->env.features[fp->w] |= fp->mask; 7523 } else { 7524 cpu->env.features[fp->w] &= ~fp->mask; 7525 } 7526 cpu->env.user_features[fp->w] |= fp->mask; 7527 } 7528 7529 /* Register a boolean property to get/set a single bit in a uint32_t field. 7530 * 7531 * The same property name can be registered multiple times to make it affect 7532 * multiple bits in the same FeatureWord. In that case, the getter will return 7533 * true only if all bits are set. 7534 */ 7535 static void x86_cpu_register_bit_prop(X86CPUClass *xcc, 7536 const char *prop_name, 7537 FeatureWord w, 7538 int bitnr) 7539 { 7540 ObjectClass *oc = OBJECT_CLASS(xcc); 7541 BitProperty *fp; 7542 ObjectProperty *op; 7543 uint64_t mask = (1ULL << bitnr); 7544 7545 op = object_class_property_find(oc, prop_name); 7546 if (op) { 7547 fp = op->opaque; 7548 assert(fp->w == w); 7549 fp->mask |= mask; 7550 } else { 7551 fp = g_new0(BitProperty, 1); 7552 fp->w = w; 7553 fp->mask = mask; 7554 object_class_property_add(oc, prop_name, "bool", 7555 x86_cpu_get_bit_prop, 7556 x86_cpu_set_bit_prop, 7557 NULL, fp); 7558 } 7559 } 7560 7561 static void x86_cpu_register_feature_bit_props(X86CPUClass *xcc, 7562 FeatureWord w, 7563 int bitnr) 7564 { 7565 FeatureWordInfo *fi = &feature_word_info[w]; 7566 const char *name = fi->feat_names[bitnr]; 7567 7568 if (!name) { 7569 return; 7570 } 7571 7572 /* Property names should use "-" instead of "_". 7573 * Old names containing underscores are registered as aliases 7574 * using object_property_add_alias() 7575 */ 7576 assert(!strchr(name, '_')); 7577 /* aliases don't use "|" delimiters anymore, they are registered 7578 * manually using object_property_add_alias() */ 7579 assert(!strchr(name, '|')); 7580 x86_cpu_register_bit_prop(xcc, name, w, bitnr); 7581 } 7582 7583 static void x86_cpu_post_initfn(Object *obj) 7584 { 7585 accel_cpu_instance_init(CPU(obj)); 7586 } 7587 7588 static void x86_cpu_initfn(Object *obj) 7589 { 7590 X86CPU *cpu = X86_CPU(obj); 7591 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj); 7592 CPUX86State *env = &cpu->env; 7593 7594 env->nr_dies = 1; 7595 7596 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo", 7597 x86_cpu_get_feature_words, 7598 NULL, NULL, (void *)env->features); 7599 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo", 7600 x86_cpu_get_feature_words, 7601 NULL, NULL, (void *)cpu->filtered_features); 7602 7603 object_property_add_alias(obj, "sse3", obj, "pni"); 7604 object_property_add_alias(obj, "pclmuldq", obj, "pclmulqdq"); 7605 object_property_add_alias(obj, "sse4-1", obj, "sse4.1"); 7606 object_property_add_alias(obj, "sse4-2", obj, "sse4.2"); 7607 object_property_add_alias(obj, "xd", obj, "nx"); 7608 object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt"); 7609 object_property_add_alias(obj, "i64", obj, "lm"); 7610 7611 object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl"); 7612 object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust"); 7613 object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt"); 7614 object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm"); 7615 object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy"); 7616 object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr"); 7617 object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core"); 7618 object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb"); 7619 object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay"); 7620 object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu"); 7621 object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf"); 7622 object_property_add_alias(obj, "kvm_asyncpf_int", obj, "kvm-asyncpf-int"); 7623 object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time"); 7624 object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi"); 7625 object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt"); 7626 object_property_add_alias(obj, "kvm_poll_control", obj, "kvm-poll-control"); 7627 object_property_add_alias(obj, "svm_lock", obj, "svm-lock"); 7628 object_property_add_alias(obj, "nrip_save", obj, "nrip-save"); 7629 object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale"); 7630 object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean"); 7631 object_property_add_alias(obj, "pause_filter", obj, "pause-filter"); 7632 object_property_add_alias(obj, "sse4_1", obj, "sse4.1"); 7633 object_property_add_alias(obj, "sse4_2", obj, "sse4.2"); 7634 7635 object_property_add_alias(obj, "hv-apicv", obj, "hv-avic"); 7636 cpu->lbr_fmt = ~PERF_CAP_LBR_FMT; 7637 object_property_add_alias(obj, "lbr_fmt", obj, "lbr-fmt"); 7638 7639 if (xcc->model) { 7640 x86_cpu_load_model(cpu, xcc->model); 7641 } 7642 } 7643 7644 static int64_t x86_cpu_get_arch_id(CPUState *cs) 7645 { 7646 X86CPU *cpu = X86_CPU(cs); 7647 7648 return cpu->apic_id; 7649 } 7650 7651 #if !defined(CONFIG_USER_ONLY) 7652 static bool x86_cpu_get_paging_enabled(const CPUState *cs) 7653 { 7654 X86CPU *cpu = X86_CPU(cs); 7655 7656 return cpu->env.cr[0] & CR0_PG_MASK; 7657 } 7658 #endif /* !CONFIG_USER_ONLY */ 7659 7660 static void x86_cpu_set_pc(CPUState *cs, vaddr value) 7661 { 7662 X86CPU *cpu = X86_CPU(cs); 7663 7664 cpu->env.eip = value; 7665 } 7666 7667 static vaddr x86_cpu_get_pc(CPUState *cs) 7668 { 7669 X86CPU *cpu = X86_CPU(cs); 7670 7671 /* Match cpu_get_tb_cpu_state. */ 7672 return cpu->env.eip + cpu->env.segs[R_CS].base; 7673 } 7674 7675 int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request) 7676 { 7677 X86CPU *cpu = X86_CPU(cs); 7678 CPUX86State *env = &cpu->env; 7679 7680 #if !defined(CONFIG_USER_ONLY) 7681 if (interrupt_request & CPU_INTERRUPT_POLL) { 7682 return CPU_INTERRUPT_POLL; 7683 } 7684 #endif 7685 if (interrupt_request & CPU_INTERRUPT_SIPI) { 7686 return CPU_INTERRUPT_SIPI; 7687 } 7688 7689 if (env->hflags2 & HF2_GIF_MASK) { 7690 if ((interrupt_request & CPU_INTERRUPT_SMI) && 7691 !(env->hflags & HF_SMM_MASK)) { 7692 return CPU_INTERRUPT_SMI; 7693 } else if ((interrupt_request & CPU_INTERRUPT_NMI) && 7694 !(env->hflags2 & HF2_NMI_MASK)) { 7695 return CPU_INTERRUPT_NMI; 7696 } else if (interrupt_request & CPU_INTERRUPT_MCE) { 7697 return CPU_INTERRUPT_MCE; 7698 } else if ((interrupt_request & CPU_INTERRUPT_HARD) && 7699 (((env->hflags2 & HF2_VINTR_MASK) && 7700 (env->hflags2 & HF2_HIF_MASK)) || 7701 (!(env->hflags2 & HF2_VINTR_MASK) && 7702 (env->eflags & IF_MASK && 7703 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) { 7704 return CPU_INTERRUPT_HARD; 7705 #if !defined(CONFIG_USER_ONLY) 7706 } else if (env->hflags2 & HF2_VGIF_MASK) { 7707 if((interrupt_request & CPU_INTERRUPT_VIRQ) && 7708 (env->eflags & IF_MASK) && 7709 !(env->hflags & HF_INHIBIT_IRQ_MASK)) { 7710 return CPU_INTERRUPT_VIRQ; 7711 } 7712 #endif 7713 } 7714 } 7715 7716 return 0; 7717 } 7718 7719 static bool x86_cpu_has_work(CPUState *cs) 7720 { 7721 return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0; 7722 } 7723 7724 static void x86_disas_set_info(CPUState *cs, disassemble_info *info) 7725 { 7726 X86CPU *cpu = X86_CPU(cs); 7727 CPUX86State *env = &cpu->env; 7728 7729 info->mach = (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64 7730 : env->hflags & HF_CS32_MASK ? bfd_mach_i386_i386 7731 : bfd_mach_i386_i8086); 7732 7733 info->cap_arch = CS_ARCH_X86; 7734 info->cap_mode = (env->hflags & HF_CS64_MASK ? CS_MODE_64 7735 : env->hflags & HF_CS32_MASK ? CS_MODE_32 7736 : CS_MODE_16); 7737 info->cap_insn_unit = 1; 7738 info->cap_insn_split = 8; 7739 } 7740 7741 void x86_update_hflags(CPUX86State *env) 7742 { 7743 uint32_t hflags; 7744 #define HFLAG_COPY_MASK \ 7745 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \ 7746 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \ 7747 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \ 7748 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK) 7749 7750 hflags = env->hflags & HFLAG_COPY_MASK; 7751 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK; 7752 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT); 7753 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) & 7754 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK); 7755 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK)); 7756 7757 if (env->cr[4] & CR4_OSFXSR_MASK) { 7758 hflags |= HF_OSFXSR_MASK; 7759 } 7760 7761 if (env->efer & MSR_EFER_LMA) { 7762 hflags |= HF_LMA_MASK; 7763 } 7764 7765 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) { 7766 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; 7767 } else { 7768 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >> 7769 (DESC_B_SHIFT - HF_CS32_SHIFT); 7770 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >> 7771 (DESC_B_SHIFT - HF_SS32_SHIFT); 7772 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) || 7773 !(hflags & HF_CS32_MASK)) { 7774 hflags |= HF_ADDSEG_MASK; 7775 } else { 7776 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base | 7777 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT; 7778 } 7779 } 7780 env->hflags = hflags; 7781 } 7782 7783 static Property x86_cpu_properties[] = { 7784 #ifdef CONFIG_USER_ONLY 7785 /* apic_id = 0 by default for *-user, see commit 9886e834 */ 7786 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0), 7787 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0), 7788 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0), 7789 DEFINE_PROP_INT32("die-id", X86CPU, die_id, 0), 7790 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0), 7791 #else 7792 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID), 7793 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1), 7794 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1), 7795 DEFINE_PROP_INT32("die-id", X86CPU, die_id, -1), 7796 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1), 7797 #endif 7798 DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID), 7799 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false), 7800 DEFINE_PROP_UINT64_CHECKMASK("lbr-fmt", X86CPU, lbr_fmt, PERF_CAP_LBR_FMT), 7801 7802 DEFINE_PROP_UINT32("hv-spinlocks", X86CPU, hyperv_spinlock_attempts, 7803 HYPERV_SPINLOCK_NEVER_NOTIFY), 7804 DEFINE_PROP_BIT64("hv-relaxed", X86CPU, hyperv_features, 7805 HYPERV_FEAT_RELAXED, 0), 7806 DEFINE_PROP_BIT64("hv-vapic", X86CPU, hyperv_features, 7807 HYPERV_FEAT_VAPIC, 0), 7808 DEFINE_PROP_BIT64("hv-time", X86CPU, hyperv_features, 7809 HYPERV_FEAT_TIME, 0), 7810 DEFINE_PROP_BIT64("hv-crash", X86CPU, hyperv_features, 7811 HYPERV_FEAT_CRASH, 0), 7812 DEFINE_PROP_BIT64("hv-reset", X86CPU, hyperv_features, 7813 HYPERV_FEAT_RESET, 0), 7814 DEFINE_PROP_BIT64("hv-vpindex", X86CPU, hyperv_features, 7815 HYPERV_FEAT_VPINDEX, 0), 7816 DEFINE_PROP_BIT64("hv-runtime", X86CPU, hyperv_features, 7817 HYPERV_FEAT_RUNTIME, 0), 7818 DEFINE_PROP_BIT64("hv-synic", X86CPU, hyperv_features, 7819 HYPERV_FEAT_SYNIC, 0), 7820 DEFINE_PROP_BIT64("hv-stimer", X86CPU, hyperv_features, 7821 HYPERV_FEAT_STIMER, 0), 7822 DEFINE_PROP_BIT64("hv-frequencies", X86CPU, hyperv_features, 7823 HYPERV_FEAT_FREQUENCIES, 0), 7824 DEFINE_PROP_BIT64("hv-reenlightenment", X86CPU, hyperv_features, 7825 HYPERV_FEAT_REENLIGHTENMENT, 0), 7826 DEFINE_PROP_BIT64("hv-tlbflush", X86CPU, hyperv_features, 7827 HYPERV_FEAT_TLBFLUSH, 0), 7828 DEFINE_PROP_BIT64("hv-evmcs", X86CPU, hyperv_features, 7829 HYPERV_FEAT_EVMCS, 0), 7830 DEFINE_PROP_BIT64("hv-ipi", X86CPU, hyperv_features, 7831 HYPERV_FEAT_IPI, 0), 7832 DEFINE_PROP_BIT64("hv-stimer-direct", X86CPU, hyperv_features, 7833 HYPERV_FEAT_STIMER_DIRECT, 0), 7834 DEFINE_PROP_BIT64("hv-avic", X86CPU, hyperv_features, 7835 HYPERV_FEAT_AVIC, 0), 7836 DEFINE_PROP_BIT64("hv-emsr-bitmap", X86CPU, hyperv_features, 7837 HYPERV_FEAT_MSR_BITMAP, 0), 7838 DEFINE_PROP_BIT64("hv-xmm-input", X86CPU, hyperv_features, 7839 HYPERV_FEAT_XMM_INPUT, 0), 7840 DEFINE_PROP_BIT64("hv-tlbflush-ext", X86CPU, hyperv_features, 7841 HYPERV_FEAT_TLBFLUSH_EXT, 0), 7842 DEFINE_PROP_BIT64("hv-tlbflush-direct", X86CPU, hyperv_features, 7843 HYPERV_FEAT_TLBFLUSH_DIRECT, 0), 7844 DEFINE_PROP_ON_OFF_AUTO("hv-no-nonarch-coresharing", X86CPU, 7845 hyperv_no_nonarch_cs, ON_OFF_AUTO_OFF), 7846 DEFINE_PROP_BIT64("hv-syndbg", X86CPU, hyperv_features, 7847 HYPERV_FEAT_SYNDBG, 0), 7848 DEFINE_PROP_BOOL("hv-passthrough", X86CPU, hyperv_passthrough, false), 7849 DEFINE_PROP_BOOL("hv-enforce-cpuid", X86CPU, hyperv_enforce_cpuid, false), 7850 7851 /* WS2008R2 identify by default */ 7852 DEFINE_PROP_UINT32("hv-version-id-build", X86CPU, hyperv_ver_id_build, 7853 0x3839), 7854 DEFINE_PROP_UINT16("hv-version-id-major", X86CPU, hyperv_ver_id_major, 7855 0x000A), 7856 DEFINE_PROP_UINT16("hv-version-id-minor", X86CPU, hyperv_ver_id_minor, 7857 0x0000), 7858 DEFINE_PROP_UINT32("hv-version-id-spack", X86CPU, hyperv_ver_id_sp, 0), 7859 DEFINE_PROP_UINT8("hv-version-id-sbranch", X86CPU, hyperv_ver_id_sb, 0), 7860 DEFINE_PROP_UINT32("hv-version-id-snumber", X86CPU, hyperv_ver_id_sn, 0), 7861 7862 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true), 7863 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false), 7864 DEFINE_PROP_BOOL("x-force-features", X86CPU, force_features, false), 7865 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true), 7866 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0), 7867 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false), 7868 DEFINE_PROP_UINT8("host-phys-bits-limit", X86CPU, host_phys_bits_limit, 0), 7869 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true), 7870 DEFINE_PROP_UINT32("level-func7", X86CPU, env.cpuid_level_func7, 7871 UINT32_MAX), 7872 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX), 7873 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX), 7874 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX), 7875 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0), 7876 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0), 7877 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0), 7878 DEFINE_PROP_UINT64("ucode-rev", X86CPU, ucode_rev, 0), 7879 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true), 7880 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor), 7881 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true), 7882 DEFINE_PROP_BOOL("x-vendor-cpuid-only", X86CPU, vendor_cpuid_only, true), 7883 DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false), 7884 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true), 7885 DEFINE_PROP_BOOL("kvm-no-smi-migration", X86CPU, kvm_no_smi_migration, 7886 false), 7887 DEFINE_PROP_BOOL("kvm-pv-enforce-cpuid", X86CPU, kvm_pv_enforce_cpuid, 7888 false), 7889 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true), 7890 DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true), 7891 DEFINE_PROP_BOOL("x-migrate-smi-count", X86CPU, migrate_smi_count, 7892 true), 7893 /* 7894 * lecacy_cache defaults to true unless the CPU model provides its 7895 * own cache information (see x86_cpu_load_def()). 7896 */ 7897 DEFINE_PROP_BOOL("legacy-cache", X86CPU, legacy_cache, true), 7898 DEFINE_PROP_BOOL("xen-vapic", X86CPU, xen_vapic, false), 7899 7900 /* 7901 * From "Requirements for Implementing the Microsoft 7902 * Hypervisor Interface": 7903 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs 7904 * 7905 * "Starting with Windows Server 2012 and Windows 8, if 7906 * CPUID.40000005.EAX contains a value of -1, Windows assumes that 7907 * the hypervisor imposes no specific limit to the number of VPs. 7908 * In this case, Windows Server 2012 guest VMs may use more than 7909 * 64 VPs, up to the maximum supported number of processors applicable 7910 * to the specific Windows version being used." 7911 */ 7912 DEFINE_PROP_INT32("x-hv-max-vps", X86CPU, hv_max_vps, -1), 7913 DEFINE_PROP_BOOL("x-hv-synic-kvm-only", X86CPU, hyperv_synic_kvm_only, 7914 false), 7915 DEFINE_PROP_BOOL("x-intel-pt-auto-level", X86CPU, intel_pt_auto_level, 7916 true), 7917 DEFINE_PROP_END_OF_LIST() 7918 }; 7919 7920 #ifndef CONFIG_USER_ONLY 7921 #include "hw/core/sysemu-cpu-ops.h" 7922 7923 static const struct SysemuCPUOps i386_sysemu_ops = { 7924 .get_memory_mapping = x86_cpu_get_memory_mapping, 7925 .get_paging_enabled = x86_cpu_get_paging_enabled, 7926 .get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug, 7927 .asidx_from_attrs = x86_asidx_from_attrs, 7928 .get_crash_info = x86_cpu_get_crash_info, 7929 .write_elf32_note = x86_cpu_write_elf32_note, 7930 .write_elf64_note = x86_cpu_write_elf64_note, 7931 .write_elf32_qemunote = x86_cpu_write_elf32_qemunote, 7932 .write_elf64_qemunote = x86_cpu_write_elf64_qemunote, 7933 .legacy_vmsd = &vmstate_x86_cpu, 7934 }; 7935 #endif 7936 7937 static void x86_cpu_common_class_init(ObjectClass *oc, void *data) 7938 { 7939 X86CPUClass *xcc = X86_CPU_CLASS(oc); 7940 CPUClass *cc = CPU_CLASS(oc); 7941 DeviceClass *dc = DEVICE_CLASS(oc); 7942 ResettableClass *rc = RESETTABLE_CLASS(oc); 7943 FeatureWord w; 7944 7945 device_class_set_parent_realize(dc, x86_cpu_realizefn, 7946 &xcc->parent_realize); 7947 device_class_set_parent_unrealize(dc, x86_cpu_unrealizefn, 7948 &xcc->parent_unrealize); 7949 device_class_set_props(dc, x86_cpu_properties); 7950 7951 resettable_class_set_parent_phases(rc, NULL, x86_cpu_reset_hold, NULL, 7952 &xcc->parent_phases); 7953 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP; 7954 7955 cc->class_by_name = x86_cpu_class_by_name; 7956 cc->parse_features = x86_cpu_parse_featurestr; 7957 cc->has_work = x86_cpu_has_work; 7958 cc->dump_state = x86_cpu_dump_state; 7959 cc->set_pc = x86_cpu_set_pc; 7960 cc->get_pc = x86_cpu_get_pc; 7961 cc->gdb_read_register = x86_cpu_gdb_read_register; 7962 cc->gdb_write_register = x86_cpu_gdb_write_register; 7963 cc->get_arch_id = x86_cpu_get_arch_id; 7964 7965 #ifndef CONFIG_USER_ONLY 7966 cc->sysemu_ops = &i386_sysemu_ops; 7967 #endif /* !CONFIG_USER_ONLY */ 7968 7969 cc->gdb_arch_name = x86_gdb_arch_name; 7970 #ifdef TARGET_X86_64 7971 cc->gdb_core_xml_file = "i386-64bit.xml"; 7972 cc->gdb_num_core_regs = 66; 7973 #else 7974 cc->gdb_core_xml_file = "i386-32bit.xml"; 7975 cc->gdb_num_core_regs = 50; 7976 #endif 7977 cc->disas_set_info = x86_disas_set_info; 7978 7979 dc->user_creatable = true; 7980 7981 object_class_property_add(oc, "family", "int", 7982 x86_cpuid_version_get_family, 7983 x86_cpuid_version_set_family, NULL, NULL); 7984 object_class_property_add(oc, "model", "int", 7985 x86_cpuid_version_get_model, 7986 x86_cpuid_version_set_model, NULL, NULL); 7987 object_class_property_add(oc, "stepping", "int", 7988 x86_cpuid_version_get_stepping, 7989 x86_cpuid_version_set_stepping, NULL, NULL); 7990 object_class_property_add_str(oc, "vendor", 7991 x86_cpuid_get_vendor, 7992 x86_cpuid_set_vendor); 7993 object_class_property_add_str(oc, "model-id", 7994 x86_cpuid_get_model_id, 7995 x86_cpuid_set_model_id); 7996 object_class_property_add(oc, "tsc-frequency", "int", 7997 x86_cpuid_get_tsc_freq, 7998 x86_cpuid_set_tsc_freq, NULL, NULL); 7999 /* 8000 * The "unavailable-features" property has the same semantics as 8001 * CpuDefinitionInfo.unavailable-features on the "query-cpu-definitions" 8002 * QMP command: they list the features that would have prevented the 8003 * CPU from running if the "enforce" flag was set. 8004 */ 8005 object_class_property_add(oc, "unavailable-features", "strList", 8006 x86_cpu_get_unavailable_features, 8007 NULL, NULL, NULL); 8008 8009 #if !defined(CONFIG_USER_ONLY) 8010 object_class_property_add(oc, "crash-information", "GuestPanicInformation", 8011 x86_cpu_get_crash_info_qom, NULL, NULL, NULL); 8012 #endif 8013 8014 for (w = 0; w < FEATURE_WORDS; w++) { 8015 int bitnr; 8016 for (bitnr = 0; bitnr < 64; bitnr++) { 8017 x86_cpu_register_feature_bit_props(xcc, w, bitnr); 8018 } 8019 } 8020 } 8021 8022 static const TypeInfo x86_cpu_type_info = { 8023 .name = TYPE_X86_CPU, 8024 .parent = TYPE_CPU, 8025 .instance_size = sizeof(X86CPU), 8026 .instance_align = __alignof(X86CPU), 8027 .instance_init = x86_cpu_initfn, 8028 .instance_post_init = x86_cpu_post_initfn, 8029 8030 .abstract = true, 8031 .class_size = sizeof(X86CPUClass), 8032 .class_init = x86_cpu_common_class_init, 8033 }; 8034 8035 /* "base" CPU model, used by query-cpu-model-expansion */ 8036 static void x86_cpu_base_class_init(ObjectClass *oc, void *data) 8037 { 8038 X86CPUClass *xcc = X86_CPU_CLASS(oc); 8039 8040 xcc->static_model = true; 8041 xcc->migration_safe = true; 8042 xcc->model_description = "base CPU model type with no features enabled"; 8043 xcc->ordering = 8; 8044 } 8045 8046 static const TypeInfo x86_base_cpu_type_info = { 8047 .name = X86_CPU_TYPE_NAME("base"), 8048 .parent = TYPE_X86_CPU, 8049 .class_init = x86_cpu_base_class_init, 8050 }; 8051 8052 static void x86_cpu_register_types(void) 8053 { 8054 int i; 8055 8056 type_register_static(&x86_cpu_type_info); 8057 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) { 8058 x86_register_cpudef_types(&builtin_x86_defs[i]); 8059 } 8060 type_register_static(&max_x86_cpu_type_info); 8061 type_register_static(&x86_base_cpu_type_info); 8062 } 8063 8064 type_init(x86_cpu_register_types) 8065