1 /* 2 * i386 CPUID, CPU class, definitions, models 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/units.h" 22 #include "qemu/cutils.h" 23 #include "qemu/qemu-print.h" 24 #include "qemu/hw-version.h" 25 #include "cpu.h" 26 #include "tcg/helper-tcg.h" 27 #include "exec/translation-block.h" 28 #include "system/hvf.h" 29 #include "hvf/hvf-i386.h" 30 #include "kvm/kvm_i386.h" 31 #include "kvm/tdx.h" 32 #include "sev.h" 33 #include "qapi/error.h" 34 #include "qemu/error-report.h" 35 #include "qapi/qapi-visit-machine.h" 36 #include "standard-headers/asm-x86/kvm_para.h" 37 #include "hw/qdev-properties.h" 38 #include "hw/i386/topology.h" 39 #include "exec/watchpoint.h" 40 #ifndef CONFIG_USER_ONLY 41 #include "confidential-guest.h" 42 #include "system/reset.h" 43 #include "qapi/qapi-commands-machine.h" 44 #include "system/address-spaces.h" 45 #include "hw/boards.h" 46 #include "hw/i386/sgx-epc.h" 47 #endif 48 #include "system/qtest.h" 49 #include "tcg/tcg-cpu.h" 50 51 #include "disas/capstone.h" 52 #include "cpu-internal.h" 53 54 static void x86_cpu_realizefn(DeviceState *dev, Error **errp); 55 static void x86_cpu_get_supported_cpuid(uint32_t func, uint32_t index, 56 uint32_t *eax, uint32_t *ebx, 57 uint32_t *ecx, uint32_t *edx); 58 59 /* Helpers for building CPUID[2] descriptors: */ 60 61 struct CPUID2CacheDescriptorInfo { 62 enum CacheType type; 63 int level; 64 int size; 65 int line_size; 66 int associativity; 67 }; 68 69 /* 70 * Known CPUID 2 cache descriptors. 71 * TLB, prefetch and sectored cache related descriptors are not included. 72 * From Intel SDM Volume 2A, CPUID instruction 73 */ 74 struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = { 75 [0x06] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 8 * KiB, 76 .associativity = 4, .line_size = 32, }, 77 [0x08] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 16 * KiB, 78 .associativity = 4, .line_size = 32, }, 79 [0x09] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB, 80 .associativity = 4, .line_size = 64, }, 81 [0x0A] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB, 82 .associativity = 2, .line_size = 32, }, 83 [0x0C] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 84 .associativity = 4, .line_size = 32, }, 85 [0x0D] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 86 .associativity = 4, .line_size = 64, }, 87 [0x0E] = { .level = 1, .type = DATA_CACHE, .size = 24 * KiB, 88 .associativity = 6, .line_size = 64, }, 89 [0x1D] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB, 90 .associativity = 2, .line_size = 64, }, 91 [0x21] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 92 .associativity = 8, .line_size = 64, }, 93 /* 94 * lines per sector is not supported cpuid2_cache_descriptor(), 95 * so descriptors 0x22, 0x23 are not included 96 */ 97 [0x24] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 98 .associativity = 16, .line_size = 64, }, 99 /* 100 * lines per sector is not supported cpuid2_cache_descriptor(), 101 * so descriptors 0x25, 0x29 are not included 102 */ 103 [0x2C] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB, 104 .associativity = 8, .line_size = 64, }, 105 [0x30] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB, 106 .associativity = 8, .line_size = 64, }, 107 /* 108 * Newer Intel CPUs (having the cores without L3, e.g., Intel MTL, ARL) 109 * use CPUID 0x4 leaf to describe cache topology, by encoding CPUID 0x2 110 * leaf with 0xFF. For older CPUs (without 0x4 leaf), it's also valid 111 * to just ignore L3's code if there's no L3. 112 * 113 * This already covers all the cases in QEMU, so code 0x40 is not 114 * included. 115 */ 116 [0x41] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB, 117 .associativity = 4, .line_size = 32, }, 118 [0x42] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 119 .associativity = 4, .line_size = 32, }, 120 [0x43] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 121 .associativity = 4, .line_size = 32, }, 122 [0x44] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 123 .associativity = 4, .line_size = 32, }, 124 [0x45] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 125 .associativity = 4, .line_size = 32, }, 126 [0x46] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 127 .associativity = 4, .line_size = 64, }, 128 [0x47] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 129 .associativity = 8, .line_size = 64, }, 130 [0x48] = { .level = 2, .type = UNIFIED_CACHE, .size = 3 * MiB, 131 .associativity = 12, .line_size = 64, }, 132 /* 133 * Descriptor 0x49 has 2 cases: 134 * - 2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size. 135 * - 3rd-level cache: 4MB, 16-way set associative, 64-byte line size 136 * (Intel Xeon processor MP, Family 0FH, Model 06H). 137 * 138 * When it represents L3, then it depends on CPU family/model. Fortunately, 139 * the legacy cache/CPU models don't have such special L3. So, just add it 140 * to represent the general L2 case. 141 */ 142 [0x49] = { .level = 2, .type = UNIFIED_CACHE, .size = 4 * MiB, 143 .associativity = 16, .line_size = 64, }, 144 [0x4A] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB, 145 .associativity = 12, .line_size = 64, }, 146 [0x4B] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 147 .associativity = 16, .line_size = 64, }, 148 [0x4C] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB, 149 .associativity = 12, .line_size = 64, }, 150 [0x4D] = { .level = 3, .type = UNIFIED_CACHE, .size = 16 * MiB, 151 .associativity = 16, .line_size = 64, }, 152 [0x4E] = { .level = 2, .type = UNIFIED_CACHE, .size = 6 * MiB, 153 .associativity = 24, .line_size = 64, }, 154 [0x60] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 155 .associativity = 8, .line_size = 64, }, 156 [0x66] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB, 157 .associativity = 4, .line_size = 64, }, 158 [0x67] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 159 .associativity = 4, .line_size = 64, }, 160 [0x68] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB, 161 .associativity = 4, .line_size = 64, }, 162 [0x78] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 163 .associativity = 4, .line_size = 64, }, 164 /* 165 * lines per sector is not supported cpuid2_cache_descriptor(), 166 * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included. 167 */ 168 [0x7D] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 169 .associativity = 8, .line_size = 64, }, 170 [0x7F] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 171 .associativity = 2, .line_size = 64, }, 172 [0x80] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 173 .associativity = 8, .line_size = 64, }, 174 [0x82] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 175 .associativity = 8, .line_size = 32, }, 176 [0x83] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 177 .associativity = 8, .line_size = 32, }, 178 [0x84] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 179 .associativity = 8, .line_size = 32, }, 180 [0x85] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 181 .associativity = 8, .line_size = 32, }, 182 [0x86] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 183 .associativity = 4, .line_size = 64, }, 184 [0x87] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 185 .associativity = 8, .line_size = 64, }, 186 [0xD0] = { .level = 3, .type = UNIFIED_CACHE, .size = 512 * KiB, 187 .associativity = 4, .line_size = 64, }, 188 [0xD1] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB, 189 .associativity = 4, .line_size = 64, }, 190 [0xD2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 191 .associativity = 4, .line_size = 64, }, 192 [0xD6] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB, 193 .associativity = 8, .line_size = 64, }, 194 [0xD7] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 195 .associativity = 8, .line_size = 64, }, 196 [0xD8] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 197 .associativity = 8, .line_size = 64, }, 198 [0xDC] = { .level = 3, .type = UNIFIED_CACHE, .size = 1.5 * MiB, 199 .associativity = 12, .line_size = 64, }, 200 [0xDD] = { .level = 3, .type = UNIFIED_CACHE, .size = 3 * MiB, 201 .associativity = 12, .line_size = 64, }, 202 [0xDE] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB, 203 .associativity = 12, .line_size = 64, }, 204 [0xE2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 205 .associativity = 16, .line_size = 64, }, 206 [0xE3] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 207 .associativity = 16, .line_size = 64, }, 208 [0xE4] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 209 .associativity = 16, .line_size = 64, }, 210 [0xEA] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB, 211 .associativity = 24, .line_size = 64, }, 212 [0xEB] = { .level = 3, .type = UNIFIED_CACHE, .size = 18 * MiB, 213 .associativity = 24, .line_size = 64, }, 214 [0xEC] = { .level = 3, .type = UNIFIED_CACHE, .size = 24 * MiB, 215 .associativity = 24, .line_size = 64, }, 216 }; 217 218 /* 219 * "CPUID leaf 2 does not report cache descriptor information, 220 * use CPUID leaf 4 to query cache parameters" 221 */ 222 #define CACHE_DESCRIPTOR_UNAVAILABLE 0xFF 223 224 /* 225 * Return a CPUID 2 cache descriptor for a given cache. 226 * If no known descriptor is found, return CACHE_DESCRIPTOR_UNAVAILABLE 227 */ 228 static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache, bool *unmacthed) 229 { 230 int i; 231 232 assert(cache->size > 0); 233 assert(cache->level > 0); 234 assert(cache->line_size > 0); 235 assert(cache->associativity > 0); 236 for (i = 0; i < ARRAY_SIZE(cpuid2_cache_descriptors); i++) { 237 struct CPUID2CacheDescriptorInfo *d = &cpuid2_cache_descriptors[i]; 238 if (d->level == cache->level && d->type == cache->type && 239 d->size == cache->size && d->line_size == cache->line_size && 240 d->associativity == cache->associativity) { 241 return i; 242 } 243 } 244 245 *unmacthed |= true; 246 return CACHE_DESCRIPTOR_UNAVAILABLE; 247 } 248 249 static const CPUCaches legacy_intel_cpuid2_cache_info; 250 251 /* Encode cache info for CPUID[2] */ 252 static void encode_cache_cpuid2(X86CPU *cpu, 253 const CPUCaches *caches, 254 uint32_t *eax, uint32_t *ebx, 255 uint32_t *ecx, uint32_t *edx) 256 { 257 CPUX86State *env = &cpu->env; 258 int l1d, l1i, l2, l3; 259 bool unmatched = false; 260 261 *eax = 1; /* Number of CPUID[EAX=2] calls required */ 262 *ebx = *ecx = *edx = 0; 263 264 l1d = cpuid2_cache_descriptor(caches->l1d_cache, &unmatched); 265 l1i = cpuid2_cache_descriptor(caches->l1i_cache, &unmatched); 266 l2 = cpuid2_cache_descriptor(caches->l2_cache, &unmatched); 267 l3 = cpuid2_cache_descriptor(caches->l3_cache, &unmatched); 268 269 if (!cpu->consistent_cache || 270 (env->cpuid_min_level < 0x4 && !unmatched)) { 271 /* 272 * Though SDM defines code 0x40 for cases with no L2 or L3. It's 273 * also valid to just ignore l3's code if there's no l2. 274 */ 275 if (cpu->enable_l3_cache) { 276 *ecx = l3; 277 } 278 *edx = (l1d << 16) | (l1i << 8) | l2; 279 } else { 280 *ecx = 0; 281 *edx = CACHE_DESCRIPTOR_UNAVAILABLE; 282 } 283 } 284 285 /* CPUID Leaf 4 constants: */ 286 287 /* EAX: */ 288 #define CACHE_TYPE_D 1 289 #define CACHE_TYPE_I 2 290 #define CACHE_TYPE_UNIFIED 3 291 292 #define CACHE_LEVEL(l) (l << 5) 293 294 #define CACHE_SELF_INIT_LEVEL (1 << 8) 295 296 /* EDX: */ 297 #define CACHE_NO_INVD_SHARING (1 << 0) 298 #define CACHE_INCLUSIVE (1 << 1) 299 #define CACHE_COMPLEX_IDX (1 << 2) 300 301 /* Encode CacheType for CPUID[4].EAX */ 302 #define CACHE_TYPE(t) (((t) == DATA_CACHE) ? CACHE_TYPE_D : \ 303 ((t) == INSTRUCTION_CACHE) ? CACHE_TYPE_I : \ 304 ((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \ 305 0 /* Invalid value */) 306 307 static uint32_t max_thread_ids_for_cache(X86CPUTopoInfo *topo_info, 308 enum CpuTopologyLevel share_level) 309 { 310 uint32_t num_ids = 0; 311 312 switch (share_level) { 313 case CPU_TOPOLOGY_LEVEL_CORE: 314 num_ids = 1 << apicid_core_offset(topo_info); 315 break; 316 case CPU_TOPOLOGY_LEVEL_MODULE: 317 num_ids = 1 << apicid_module_offset(topo_info); 318 break; 319 case CPU_TOPOLOGY_LEVEL_DIE: 320 num_ids = 1 << apicid_die_offset(topo_info); 321 break; 322 case CPU_TOPOLOGY_LEVEL_SOCKET: 323 num_ids = 1 << apicid_pkg_offset(topo_info); 324 break; 325 default: 326 /* 327 * Currently there is no use case for THREAD, so use 328 * assert directly to facilitate debugging. 329 */ 330 g_assert_not_reached(); 331 } 332 333 return num_ids - 1; 334 } 335 336 static uint32_t max_core_ids_in_package(X86CPUTopoInfo *topo_info) 337 { 338 uint32_t num_cores = 1 << (apicid_pkg_offset(topo_info) - 339 apicid_core_offset(topo_info)); 340 return num_cores - 1; 341 } 342 343 /* Encode cache info for CPUID[4] */ 344 static void encode_cache_cpuid4(CPUCacheInfo *cache, 345 X86CPUTopoInfo *topo_info, 346 uint32_t *eax, uint32_t *ebx, 347 uint32_t *ecx, uint32_t *edx) 348 { 349 assert(cache->size == cache->line_size * cache->associativity * 350 cache->partitions * cache->sets); 351 352 /* 353 * The following fields have bit-width limitations, so consider the 354 * maximum values to avoid overflow: 355 * Bits 25-14: maximum 4095. 356 * Bits 31-26: maximum 63. 357 */ 358 *eax = CACHE_TYPE(cache->type) | 359 CACHE_LEVEL(cache->level) | 360 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) | 361 (MIN(max_core_ids_in_package(topo_info), 63) << 26) | 362 (MIN(max_thread_ids_for_cache(topo_info, cache->share_level), 4095) << 14); 363 364 assert(cache->line_size > 0); 365 assert(cache->partitions > 0); 366 assert(cache->associativity > 0); 367 /* We don't implement fully-associative caches */ 368 assert(cache->associativity < cache->sets); 369 *ebx = (cache->line_size - 1) | 370 ((cache->partitions - 1) << 12) | 371 ((cache->associativity - 1) << 22); 372 373 assert(cache->sets > 0); 374 *ecx = cache->sets - 1; 375 376 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) | 377 (cache->inclusive ? CACHE_INCLUSIVE : 0) | 378 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); 379 } 380 381 static uint32_t num_threads_by_topo_level(X86CPUTopoInfo *topo_info, 382 enum CpuTopologyLevel topo_level) 383 { 384 switch (topo_level) { 385 case CPU_TOPOLOGY_LEVEL_THREAD: 386 return 1; 387 case CPU_TOPOLOGY_LEVEL_CORE: 388 return topo_info->threads_per_core; 389 case CPU_TOPOLOGY_LEVEL_MODULE: 390 return x86_threads_per_module(topo_info); 391 case CPU_TOPOLOGY_LEVEL_DIE: 392 return x86_threads_per_die(topo_info); 393 case CPU_TOPOLOGY_LEVEL_SOCKET: 394 return x86_threads_per_pkg(topo_info); 395 default: 396 g_assert_not_reached(); 397 } 398 return 0; 399 } 400 401 static uint32_t apicid_offset_by_topo_level(X86CPUTopoInfo *topo_info, 402 enum CpuTopologyLevel topo_level) 403 { 404 switch (topo_level) { 405 case CPU_TOPOLOGY_LEVEL_THREAD: 406 return 0; 407 case CPU_TOPOLOGY_LEVEL_CORE: 408 return apicid_core_offset(topo_info); 409 case CPU_TOPOLOGY_LEVEL_MODULE: 410 return apicid_module_offset(topo_info); 411 case CPU_TOPOLOGY_LEVEL_DIE: 412 return apicid_die_offset(topo_info); 413 case CPU_TOPOLOGY_LEVEL_SOCKET: 414 return apicid_pkg_offset(topo_info); 415 default: 416 g_assert_not_reached(); 417 } 418 return 0; 419 } 420 421 static uint32_t cpuid1f_topo_type(enum CpuTopologyLevel topo_level) 422 { 423 switch (topo_level) { 424 case CPU_TOPOLOGY_LEVEL_INVALID: 425 return CPUID_1F_ECX_TOPO_LEVEL_INVALID; 426 case CPU_TOPOLOGY_LEVEL_THREAD: 427 return CPUID_1F_ECX_TOPO_LEVEL_SMT; 428 case CPU_TOPOLOGY_LEVEL_CORE: 429 return CPUID_1F_ECX_TOPO_LEVEL_CORE; 430 case CPU_TOPOLOGY_LEVEL_MODULE: 431 return CPUID_1F_ECX_TOPO_LEVEL_MODULE; 432 case CPU_TOPOLOGY_LEVEL_DIE: 433 return CPUID_1F_ECX_TOPO_LEVEL_DIE; 434 default: 435 /* Other types are not supported in QEMU. */ 436 g_assert_not_reached(); 437 } 438 return 0; 439 } 440 441 static void encode_topo_cpuid1f(CPUX86State *env, uint32_t count, 442 X86CPUTopoInfo *topo_info, 443 uint32_t *eax, uint32_t *ebx, 444 uint32_t *ecx, uint32_t *edx) 445 { 446 X86CPU *cpu = env_archcpu(env); 447 unsigned long level, base_level, next_level; 448 uint32_t num_threads_next_level, offset_next_level; 449 450 assert(count <= CPU_TOPOLOGY_LEVEL_SOCKET); 451 452 /* 453 * Find the No.(count + 1) topology level in avail_cpu_topo bitmap. 454 * The search starts from bit 0 (CPU_TOPOLOGY_LEVEL_THREAD). 455 */ 456 level = CPU_TOPOLOGY_LEVEL_THREAD; 457 base_level = level; 458 for (int i = 0; i <= count; i++) { 459 level = find_next_bit(env->avail_cpu_topo, 460 CPU_TOPOLOGY_LEVEL_SOCKET, 461 base_level); 462 463 /* 464 * CPUID[0x1f] doesn't explicitly encode the package level, 465 * and it just encodes the invalid level (all fields are 0) 466 * into the last subleaf of 0x1f. 467 */ 468 if (level == CPU_TOPOLOGY_LEVEL_SOCKET) { 469 level = CPU_TOPOLOGY_LEVEL_INVALID; 470 break; 471 } 472 /* Search the next level. */ 473 base_level = level + 1; 474 } 475 476 if (level == CPU_TOPOLOGY_LEVEL_INVALID) { 477 num_threads_next_level = 0; 478 offset_next_level = 0; 479 } else { 480 next_level = find_next_bit(env->avail_cpu_topo, 481 CPU_TOPOLOGY_LEVEL_SOCKET, 482 level + 1); 483 num_threads_next_level = num_threads_by_topo_level(topo_info, 484 next_level); 485 offset_next_level = apicid_offset_by_topo_level(topo_info, 486 next_level); 487 } 488 489 *eax = offset_next_level; 490 /* The count (bits 15-00) doesn't need to be reliable. */ 491 *ebx = num_threads_next_level & 0xffff; 492 *ecx = (count & 0xff) | (cpuid1f_topo_type(level) << 8); 493 *edx = cpu->apic_id; 494 495 assert(!(*eax & ~0x1f)); 496 } 497 498 /* Encode cache info for CPUID[0x80000005].ECX or CPUID[0x80000005].EDX */ 499 static uint32_t encode_cache_cpuid80000005(CPUCacheInfo *cache) 500 { 501 assert(cache->size % 1024 == 0); 502 assert(cache->associativity > 0); 503 assert(cache->line_size > 0); 504 return ((cache->size / 1024) << 24) | (cache->associativity << 16) | 505 (cache->lines_per_tag << 8) | (cache->line_size); 506 } 507 508 #define ASSOC_FULL 0xFF 509 510 /* x86 associativity encoding used on CPUID Leaf 0x80000006: */ 511 #define X86_ENC_ASSOC(a) (a <= 1 ? a : \ 512 a == 2 ? 0x2 : \ 513 a == 4 ? 0x4 : \ 514 a == 8 ? 0x6 : \ 515 a == 16 ? 0x8 : \ 516 a == 32 ? 0xA : \ 517 a == 48 ? 0xB : \ 518 a == 64 ? 0xC : \ 519 a == 96 ? 0xD : \ 520 a == 128 ? 0xE : \ 521 a == ASSOC_FULL ? 0xF : \ 522 0 /* invalid value */) 523 524 /* 525 * Encode cache info for CPUID[0x80000006].ECX and CPUID[0x80000006].EDX 526 * @l3 can be NULL. 527 */ 528 static void encode_cache_cpuid80000006(CPUCacheInfo *l2, 529 CPUCacheInfo *l3, 530 uint32_t *ecx, uint32_t *edx) 531 { 532 assert(l2->size % 1024 == 0); 533 assert(l2->associativity > 0); 534 assert(l2->line_size > 0); 535 *ecx = ((l2->size / 1024) << 16) | 536 (X86_ENC_ASSOC(l2->associativity) << 12) | 537 (l2->lines_per_tag << 8) | (l2->line_size); 538 539 /* For Intel, EDX is reserved. */ 540 if (l3) { 541 assert(l3->size % (512 * 1024) == 0); 542 assert(l3->associativity > 0); 543 assert(l3->line_size > 0); 544 *edx = ((l3->size / (512 * 1024)) << 18) | 545 (X86_ENC_ASSOC(l3->associativity) << 12) | 546 (l3->lines_per_tag << 8) | (l3->line_size); 547 } else { 548 *edx = 0; 549 } 550 } 551 552 /* Encode cache info for CPUID[8000001D] */ 553 static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, 554 X86CPUTopoInfo *topo_info, 555 uint32_t *eax, uint32_t *ebx, 556 uint32_t *ecx, uint32_t *edx) 557 { 558 assert(cache->size == cache->line_size * cache->associativity * 559 cache->partitions * cache->sets); 560 561 *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) | 562 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0); 563 /* Bits 25:14 - NumSharingCache: maximum 4095. */ 564 *eax |= MIN(max_thread_ids_for_cache(topo_info, cache->share_level), 4095) << 14; 565 566 assert(cache->line_size > 0); 567 assert(cache->partitions > 0); 568 assert(cache->associativity > 0); 569 /* We don't implement fully-associative caches */ 570 assert(cache->associativity < cache->sets); 571 *ebx = (cache->line_size - 1) | 572 ((cache->partitions - 1) << 12) | 573 ((cache->associativity - 1) << 22); 574 575 assert(cache->sets > 0); 576 *ecx = cache->sets - 1; 577 578 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) | 579 (cache->inclusive ? CACHE_INCLUSIVE : 0) | 580 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); 581 } 582 583 /* Encode cache info for CPUID[8000001E] */ 584 static void encode_topo_cpuid8000001e(X86CPU *cpu, X86CPUTopoInfo *topo_info, 585 uint32_t *eax, uint32_t *ebx, 586 uint32_t *ecx, uint32_t *edx) 587 { 588 X86CPUTopoIDs topo_ids; 589 590 x86_topo_ids_from_apicid(cpu->apic_id, topo_info, &topo_ids); 591 592 *eax = cpu->apic_id; 593 594 /* 595 * CPUID_Fn8000001E_EBX [Core Identifiers] (CoreId) 596 * Read-only. Reset: 0000_XXXXh. 597 * See Core::X86::Cpuid::ExtApicId. 598 * Core::X86::Cpuid::CoreId_lthree[1:0]_core[3:0]_thread[1:0]; 599 * Bits Description 600 * 31:16 Reserved. 601 * 15:8 ThreadsPerCore: threads per core. Read-only. Reset: XXh. 602 * The number of threads per core is ThreadsPerCore+1. 603 * 7:0 CoreId: core ID. Read-only. Reset: XXh. 604 * 605 * NOTE: CoreId is already part of apic_id. Just use it. We can 606 * use all the 8 bits to represent the core_id here. 607 */ 608 *ebx = ((topo_info->threads_per_core - 1) << 8) | (topo_ids.core_id & 0xFF); 609 610 /* 611 * CPUID_Fn8000001E_ECX [Node Identifiers] (NodeId) 612 * Read-only. Reset: 0000_0XXXh. 613 * Core::X86::Cpuid::NodeId_lthree[1:0]_core[3:0]_thread[1:0]; 614 * Bits Description 615 * 31:11 Reserved. 616 * 10:8 NodesPerProcessor: Node per processor. Read-only. Reset: XXXb. 617 * ValidValues: 618 * Value Description 619 * 0h 1 node per processor. 620 * 7h-1h Reserved. 621 * 7:0 NodeId: Node ID. Read-only. Reset: XXh. 622 * 623 * NOTE: Hardware reserves 3 bits for number of nodes per processor. 624 * But users can create more nodes than the actual hardware can 625 * support. To genaralize we can use all the upper 8 bits for nodes. 626 * NodeId is combination of node and socket_id which is already decoded 627 * in apic_id. Just use it by shifting. 628 */ 629 if (cpu->legacy_multi_node) { 630 *ecx = ((topo_info->dies_per_pkg - 1) << 8) | 631 ((cpu->apic_id >> apicid_die_offset(topo_info)) & 0xFF); 632 } else { 633 *ecx = (cpu->apic_id >> apicid_pkg_offset(topo_info)) & 0xFF; 634 } 635 636 *edx = 0; 637 } 638 639 /* 640 * Definitions of the hardcoded cache entries we expose: 641 * These are legacy cache values. If there is a need to change any 642 * of these values please use builtin_x86_defs 643 */ 644 static const CPUCaches legacy_amd_cache_info = { 645 .l1d_cache = &(CPUCacheInfo) { 646 .type = DATA_CACHE, 647 .level = 1, 648 .size = 64 * KiB, 649 .self_init = 1, 650 .line_size = 64, 651 .associativity = 2, 652 .sets = 512, 653 .partitions = 1, 654 .lines_per_tag = 1, 655 .no_invd_sharing = true, 656 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 657 }, 658 .l1i_cache = &(CPUCacheInfo) { 659 .type = INSTRUCTION_CACHE, 660 .level = 1, 661 .size = 64 * KiB, 662 .self_init = 1, 663 .line_size = 64, 664 .associativity = 2, 665 .sets = 512, 666 .partitions = 1, 667 .lines_per_tag = 1, 668 .no_invd_sharing = true, 669 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 670 }, 671 .l2_cache = &(CPUCacheInfo) { 672 .type = UNIFIED_CACHE, 673 .level = 2, 674 .size = 512 * KiB, 675 .line_size = 64, 676 .lines_per_tag = 1, 677 .associativity = 16, 678 .sets = 512, 679 .partitions = 1, 680 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 681 }, 682 .l3_cache = &(CPUCacheInfo) { 683 .type = UNIFIED_CACHE, 684 .level = 3, 685 .size = 16 * MiB, 686 .line_size = 64, 687 .associativity = 16, 688 .sets = 16384, 689 .partitions = 1, 690 .lines_per_tag = 1, 691 .self_init = true, 692 .inclusive = true, 693 .complex_indexing = true, 694 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 695 }, 696 }; 697 698 /* 699 * Only used for the CPU models with CPUID level < 4. 700 * These CPUs (CPUID level < 4) only use CPUID leaf 2 to present 701 * cache information. 702 * 703 * Note: This cache model is just a default one, and is not 704 * guaranteed to match real hardwares. 705 */ 706 static const CPUCaches legacy_intel_cpuid2_cache_info = { 707 .l1d_cache = &(CPUCacheInfo) { 708 .type = DATA_CACHE, 709 .level = 1, 710 .size = 32 * KiB, 711 .self_init = 1, 712 .line_size = 64, 713 .associativity = 8, 714 .sets = 64, 715 .partitions = 1, 716 .no_invd_sharing = true, 717 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 718 }, 719 .l1i_cache = &(CPUCacheInfo) { 720 .type = INSTRUCTION_CACHE, 721 .level = 1, 722 .size = 32 * KiB, 723 .self_init = 1, 724 .line_size = 64, 725 .associativity = 8, 726 .sets = 64, 727 .partitions = 1, 728 .no_invd_sharing = true, 729 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 730 }, 731 .l2_cache = &(CPUCacheInfo) { 732 .type = UNIFIED_CACHE, 733 .level = 2, 734 .size = 2 * MiB, 735 .self_init = 1, 736 .line_size = 64, 737 .associativity = 8, 738 .sets = 4096, 739 .partitions = 1, 740 .no_invd_sharing = true, 741 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 742 }, 743 .l3_cache = &(CPUCacheInfo) { 744 .type = UNIFIED_CACHE, 745 .level = 3, 746 .size = 16 * MiB, 747 .line_size = 64, 748 .associativity = 16, 749 .sets = 16384, 750 .partitions = 1, 751 .lines_per_tag = 1, 752 .self_init = true, 753 .inclusive = true, 754 .complex_indexing = true, 755 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 756 }, 757 }; 758 759 static const CPUCaches legacy_intel_cache_info = { 760 .l1d_cache = &(CPUCacheInfo) { 761 .type = DATA_CACHE, 762 .level = 1, 763 .size = 32 * KiB, 764 .self_init = 1, 765 .line_size = 64, 766 .associativity = 8, 767 .sets = 64, 768 .partitions = 1, 769 .no_invd_sharing = true, 770 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 771 }, 772 .l1i_cache = &(CPUCacheInfo) { 773 .type = INSTRUCTION_CACHE, 774 .level = 1, 775 .size = 32 * KiB, 776 .self_init = 1, 777 .line_size = 64, 778 .associativity = 8, 779 .sets = 64, 780 .partitions = 1, 781 .no_invd_sharing = true, 782 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 783 }, 784 .l2_cache = &(CPUCacheInfo) { 785 .type = UNIFIED_CACHE, 786 .level = 2, 787 .size = 4 * MiB, 788 .self_init = 1, 789 .line_size = 64, 790 .associativity = 16, 791 .sets = 4096, 792 .partitions = 1, 793 .no_invd_sharing = true, 794 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 795 }, 796 .l3_cache = &(CPUCacheInfo) { 797 .type = UNIFIED_CACHE, 798 .level = 3, 799 .size = 16 * MiB, 800 .line_size = 64, 801 .associativity = 16, 802 .sets = 16384, 803 .partitions = 1, 804 .lines_per_tag = 1, 805 .self_init = true, 806 .inclusive = true, 807 .complex_indexing = true, 808 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 809 }, 810 }; 811 812 /* TLB definitions: */ 813 814 #define L1_DTLB_2M_ASSOC 1 815 #define L1_DTLB_2M_ENTRIES 255 816 #define L1_DTLB_4K_ASSOC 1 817 #define L1_DTLB_4K_ENTRIES 255 818 819 #define L1_ITLB_2M_ASSOC 1 820 #define L1_ITLB_2M_ENTRIES 255 821 #define L1_ITLB_4K_ASSOC 1 822 #define L1_ITLB_4K_ENTRIES 255 823 824 #define L2_DTLB_2M_ASSOC 0 /* disabled */ 825 #define L2_DTLB_2M_ENTRIES 0 /* disabled */ 826 #define L2_DTLB_4K_ASSOC 4 827 #define L2_DTLB_4K_ENTRIES 512 828 829 #define L2_ITLB_2M_ASSOC 0 /* disabled */ 830 #define L2_ITLB_2M_ENTRIES 0 /* disabled */ 831 #define L2_ITLB_4K_ASSOC 4 832 #define L2_ITLB_4K_ENTRIES 512 833 834 /* CPUID Leaf 0x14 constants: */ 835 #define INTEL_PT_MAX_SUBLEAF 0x1 836 /* 837 * bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MATCH 838 * MSR can be accessed; 839 * bit[01]: Support Configurable PSB and Cycle-Accurate Mode; 840 * bit[02]: Support IP Filtering, TraceStop filtering, and preservation 841 * of Intel PT MSRs across warm reset; 842 * bit[03]: Support MTC timing packet and suppression of COFI-based packets; 843 */ 844 #define INTEL_PT_MINIMAL_EBX 0xf 845 /* 846 * bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 and 847 * IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be 848 * accessed; 849 * bit[01]: ToPA tables can hold any number of output entries, up to the 850 * maximum allowed by the MaskOrTableOffset field of 851 * IA32_RTIT_OUTPUT_MASK_PTRS; 852 * bit[02]: Support Single-Range Output scheme; 853 */ 854 #define INTEL_PT_MINIMAL_ECX 0x7 855 /* generated packets which contain IP payloads have LIP values */ 856 #define INTEL_PT_IP_LIP (1 << 31) 857 #define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */ 858 #define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3 859 #define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */ 860 #define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */ 861 #define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */ 862 863 /* CPUID Leaf 0x1D constants: */ 864 #define INTEL_AMX_TILE_MAX_SUBLEAF 0x1 865 #define INTEL_AMX_TOTAL_TILE_BYTES 0x2000 866 #define INTEL_AMX_BYTES_PER_TILE 0x400 867 #define INTEL_AMX_BYTES_PER_ROW 0x40 868 #define INTEL_AMX_TILE_MAX_NAMES 0x8 869 #define INTEL_AMX_TILE_MAX_ROWS 0x10 870 871 /* CPUID Leaf 0x1E constants: */ 872 #define INTEL_AMX_TMUL_MAX_K 0x10 873 #define INTEL_AMX_TMUL_MAX_N 0x40 874 875 void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1, 876 uint32_t vendor2, uint32_t vendor3) 877 { 878 int i; 879 for (i = 0; i < 4; i++) { 880 dst[i] = vendor1 >> (8 * i); 881 dst[i + 4] = vendor2 >> (8 * i); 882 dst[i + 8] = vendor3 >> (8 * i); 883 } 884 dst[CPUID_VENDOR_SZ] = '\0'; 885 } 886 887 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE) 888 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \ 889 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC) 890 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \ 891 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ 892 CPUID_PSE36 | CPUID_FXSR) 893 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE) 894 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \ 895 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \ 896 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \ 897 CPUID_PAE | CPUID_SEP | CPUID_APIC) 898 899 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \ 900 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \ 901 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ 902 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \ 903 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE | \ 904 CPUID_HT) 905 /* partly implemented: 906 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */ 907 /* missing: 908 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_TM, CPUID_PBE */ 909 910 /* 911 * Kernel-only features that can be shown to usermode programs even if 912 * they aren't actually supported by TCG, because qemu-user only runs 913 * in CPL=3; remove them if they are ever implemented for system emulation. 914 */ 915 #if defined CONFIG_USER_ONLY 916 #define CPUID_EXT_KERNEL_FEATURES \ 917 (CPUID_EXT_PCID | CPUID_EXT_TSC_DEADLINE_TIMER) 918 #else 919 #define CPUID_EXT_KERNEL_FEATURES 0 920 #endif 921 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \ 922 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \ 923 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \ 924 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \ 925 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR | \ 926 CPUID_EXT_RDRAND | CPUID_EXT_AVX | CPUID_EXT_F16C | \ 927 CPUID_EXT_FMA | CPUID_EXT_X2APIC | CPUID_EXT_KERNEL_FEATURES) 928 /* missing: 929 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX, 930 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, 931 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA, 932 CPUID_EXT_TSC_DEADLINE_TIMER 933 */ 934 935 #ifdef TARGET_X86_64 936 #define TCG_EXT2_X86_64_FEATURES CPUID_EXT2_LM 937 #else 938 #define TCG_EXT2_X86_64_FEATURES 0 939 #endif 940 941 /* 942 * CPUID_*_KERNEL_FEATURES denotes bits and features that are not usable 943 * in usermode or by 32-bit programs. Those are added to supported 944 * TCG features unconditionally in user-mode emulation mode. This may 945 * indeed seem strange or incorrect, but it works because code running 946 * under usermode emulation cannot access them. 947 * 948 * Even for long mode, qemu-i386 is not running "a userspace program on a 949 * 32-bit CPU"; it's running "a userspace program with a 32-bit code segment" 950 * and therefore using the 32-bit ABI; the CPU itself might be 64-bit 951 * but again the difference is only visible in kernel mode. 952 */ 953 #if defined CONFIG_LINUX_USER 954 #define CPUID_EXT2_KERNEL_FEATURES (CPUID_EXT2_LM | CPUID_EXT2_FFXSR) 955 #elif defined CONFIG_USER_ONLY 956 /* FIXME: Long mode not yet supported for i386 bsd-user */ 957 #define CPUID_EXT2_KERNEL_FEATURES CPUID_EXT2_FFXSR 958 #else 959 #define CPUID_EXT2_KERNEL_FEATURES 0 960 #endif 961 962 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \ 963 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \ 964 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \ 965 CPUID_EXT2_SYSCALL | TCG_EXT2_X86_64_FEATURES | \ 966 CPUID_EXT2_KERNEL_FEATURES) 967 968 #if defined CONFIG_USER_ONLY 969 #define CPUID_EXT3_KERNEL_FEATURES CPUID_EXT3_OSVW 970 #else 971 #define CPUID_EXT3_KERNEL_FEATURES 0 972 #endif 973 974 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \ 975 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A | \ 976 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_KERNEL_FEATURES | \ 977 CPUID_EXT3_CMP_LEG) 978 979 #define TCG_EXT4_FEATURES 0 980 981 #if defined CONFIG_USER_ONLY 982 #define CPUID_SVM_KERNEL_FEATURES (CPUID_SVM_NRIPSAVE | CPUID_SVM_VNMI) 983 #else 984 #define CPUID_SVM_KERNEL_FEATURES 0 985 #endif 986 #define TCG_SVM_FEATURES (CPUID_SVM_NPT | CPUID_SVM_VGIF | \ 987 CPUID_SVM_SVME_ADDR_CHK | CPUID_SVM_KERNEL_FEATURES) 988 989 #define TCG_KVM_FEATURES 0 990 991 #if defined CONFIG_USER_ONLY 992 #define CPUID_7_0_EBX_KERNEL_FEATURES CPUID_7_0_EBX_INVPCID 993 #else 994 #define CPUID_7_0_EBX_KERNEL_FEATURES 0 995 #endif 996 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \ 997 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \ 998 CPUID_7_0_EBX_CLFLUSHOPT | \ 999 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \ 1000 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_RDSEED | \ 1001 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_KERNEL_FEATURES) 1002 /* missing: 1003 CPUID_7_0_EBX_HLE 1004 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM */ 1005 1006 #if !defined CONFIG_USER_ONLY || defined CONFIG_LINUX 1007 #define TCG_7_0_ECX_RDPID CPUID_7_0_ECX_RDPID 1008 #else 1009 #define TCG_7_0_ECX_RDPID 0 1010 #endif 1011 #define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | \ 1012 /* CPUID_7_0_ECX_OSPKE is dynamic */ \ 1013 CPUID_7_0_ECX_LA57 | CPUID_7_0_ECX_PKS | CPUID_7_0_ECX_VAES | \ 1014 TCG_7_0_ECX_RDPID) 1015 1016 #if defined CONFIG_USER_ONLY 1017 #define CPUID_7_0_EDX_KERNEL_FEATURES (CPUID_7_0_EDX_SPEC_CTRL | \ 1018 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD) 1019 #else 1020 #define CPUID_7_0_EDX_KERNEL_FEATURES 0 1021 #endif 1022 #define TCG_7_0_EDX_FEATURES (CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_KERNEL_FEATURES) 1023 1024 #define TCG_7_1_EAX_FEATURES (CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | \ 1025 CPUID_7_1_EAX_FSRC | CPUID_7_1_EAX_CMPCCXADD) 1026 #define TCG_7_1_ECX_FEATURES 0 1027 #define TCG_7_1_EDX_FEATURES 0 1028 #define TCG_7_2_EDX_FEATURES 0 1029 #define TCG_APM_FEATURES 0 1030 #define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT 1031 #define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1) 1032 /* missing: 1033 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */ 1034 #define TCG_14_0_ECX_FEATURES 0 1035 #define TCG_SGX_12_0_EAX_FEATURES 0 1036 #define TCG_SGX_12_0_EBX_FEATURES 0 1037 #define TCG_SGX_12_1_EAX_FEATURES 0 1038 #define TCG_24_0_EBX_FEATURES 0 1039 1040 #if defined CONFIG_USER_ONLY 1041 #define CPUID_8000_0008_EBX_KERNEL_FEATURES (CPUID_8000_0008_EBX_IBPB | \ 1042 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | \ 1043 CPUID_8000_0008_EBX_STIBP_ALWAYS_ON | CPUID_8000_0008_EBX_AMD_SSBD | \ 1044 CPUID_8000_0008_EBX_AMD_PSFD) 1045 #else 1046 #define CPUID_8000_0008_EBX_KERNEL_FEATURES 0 1047 #endif 1048 1049 #define TCG_8000_0008_EBX (CPUID_8000_0008_EBX_XSAVEERPTR | \ 1050 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_KERNEL_FEATURES) 1051 1052 #if defined CONFIG_USER_ONLY 1053 #define CPUID_8000_0021_EAX_KERNEL_FEATURES CPUID_8000_0021_EAX_AUTO_IBRS 1054 #else 1055 #define CPUID_8000_0021_EAX_KERNEL_FEATURES 0 1056 #endif 1057 1058 #define TCG_8000_0021_EAX_FEATURES ( \ 1059 CPUID_8000_0021_EAX_NO_NESTED_DATA_BP | \ 1060 CPUID_8000_0021_EAX_NULL_SEL_CLR_BASE | \ 1061 CPUID_8000_0021_EAX_KERNEL_FEATURES) 1062 1063 FeatureWordInfo feature_word_info[FEATURE_WORDS] = { 1064 [FEAT_1_EDX] = { 1065 .type = CPUID_FEATURE_WORD, 1066 .feat_names = { 1067 "fpu", "vme", "de", "pse", 1068 "tsc", "msr", "pae", "mce", 1069 "cx8", "apic", NULL, "sep", 1070 "mtrr", "pge", "mca", "cmov", 1071 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */, 1072 NULL, "ds" /* Intel dts */, "acpi", "mmx", 1073 "fxsr", "sse", "sse2", "ss", 1074 "ht" /* Intel htt */, "tm", "ia64", "pbe", 1075 }, 1076 .cpuid = {.eax = 1, .reg = R_EDX, }, 1077 .tcg_features = TCG_FEATURES, 1078 .no_autoenable_flags = CPUID_HT, 1079 }, 1080 [FEAT_1_ECX] = { 1081 .type = CPUID_FEATURE_WORD, 1082 .feat_names = { 1083 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor", 1084 "ds-cpl", "vmx", "smx", "est", 1085 "tm2", "ssse3", "cid", NULL, 1086 "fma", "cx16", "xtpr", "pdcm", 1087 NULL, "pcid", "dca", "sse4.1", 1088 "sse4.2", "x2apic", "movbe", "popcnt", 1089 "tsc-deadline", "aes", "xsave", NULL /* osxsave */, 1090 "avx", "f16c", "rdrand", "hypervisor", 1091 }, 1092 .cpuid = { .eax = 1, .reg = R_ECX, }, 1093 .tcg_features = TCG_EXT_FEATURES, 1094 }, 1095 /* Feature names that are already defined on feature_name[] but 1096 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their 1097 * names on feat_names below. They are copied automatically 1098 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD. 1099 */ 1100 [FEAT_8000_0001_EDX] = { 1101 .type = CPUID_FEATURE_WORD, 1102 .feat_names = { 1103 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */, 1104 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */, 1105 NULL /* cx8 */, NULL /* apic */, NULL, "syscall", 1106 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */, 1107 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */, 1108 "nx", NULL, "mmxext", NULL /* mmx */, 1109 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp", 1110 NULL, "lm", "3dnowext", "3dnow", 1111 }, 1112 .cpuid = { .eax = 0x80000001, .reg = R_EDX, }, 1113 .tcg_features = TCG_EXT2_FEATURES, 1114 }, 1115 [FEAT_8000_0001_ECX] = { 1116 .type = CPUID_FEATURE_WORD, 1117 .feat_names = { 1118 "lahf-lm", "cmp-legacy", "svm", "extapic", 1119 "cr8legacy", "abm", "sse4a", "misalignsse", 1120 "3dnowprefetch", "osvw", "ibs", "xop", 1121 "skinit", "wdt", NULL, "lwp", 1122 "fma4", "tce", NULL, "nodeid-msr", 1123 NULL, "tbm", "topoext", "perfctr-core", 1124 "perfctr-nb", NULL, NULL, NULL, 1125 NULL, NULL, NULL, NULL, 1126 }, 1127 .cpuid = { .eax = 0x80000001, .reg = R_ECX, }, 1128 .tcg_features = TCG_EXT3_FEATURES, 1129 /* 1130 * TOPOEXT is always allowed but can't be enabled blindly by 1131 * "-cpu host", as it requires consistent cache topology info 1132 * to be provided so it doesn't confuse guests. 1133 */ 1134 .no_autoenable_flags = CPUID_EXT3_TOPOEXT, 1135 }, 1136 [FEAT_C000_0001_EDX] = { 1137 .type = CPUID_FEATURE_WORD, 1138 .feat_names = { 1139 NULL, NULL, "xstore", "xstore-en", 1140 NULL, NULL, "xcrypt", "xcrypt-en", 1141 "ace2", "ace2-en", "phe", "phe-en", 1142 "pmm", "pmm-en", NULL, NULL, 1143 NULL, NULL, NULL, NULL, 1144 NULL, NULL, NULL, NULL, 1145 NULL, NULL, NULL, NULL, 1146 NULL, NULL, NULL, NULL, 1147 }, 1148 .cpuid = { .eax = 0xC0000001, .reg = R_EDX, }, 1149 .tcg_features = TCG_EXT4_FEATURES, 1150 }, 1151 [FEAT_KVM] = { 1152 .type = CPUID_FEATURE_WORD, 1153 .feat_names = { 1154 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock", 1155 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt", 1156 NULL, "kvm-pv-tlb-flush", "kvm-asyncpf-vmexit", "kvm-pv-ipi", 1157 "kvm-poll-control", "kvm-pv-sched-yield", "kvm-asyncpf-int", "kvm-msi-ext-dest-id", 1158 NULL, NULL, NULL, NULL, 1159 NULL, NULL, NULL, NULL, 1160 "kvmclock-stable-bit", NULL, NULL, NULL, 1161 NULL, NULL, NULL, NULL, 1162 }, 1163 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EAX, }, 1164 .tcg_features = TCG_KVM_FEATURES, 1165 }, 1166 [FEAT_KVM_HINTS] = { 1167 .type = CPUID_FEATURE_WORD, 1168 .feat_names = { 1169 "kvm-hint-dedicated", NULL, NULL, NULL, 1170 NULL, NULL, NULL, NULL, 1171 NULL, NULL, NULL, NULL, 1172 NULL, NULL, NULL, NULL, 1173 NULL, NULL, NULL, NULL, 1174 NULL, NULL, NULL, NULL, 1175 NULL, NULL, NULL, NULL, 1176 NULL, NULL, NULL, NULL, 1177 }, 1178 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EDX, }, 1179 .tcg_features = TCG_KVM_FEATURES, 1180 /* 1181 * KVM hints aren't auto-enabled by -cpu host, they need to be 1182 * explicitly enabled in the command-line. 1183 */ 1184 .no_autoenable_flags = ~0U, 1185 }, 1186 [FEAT_SVM] = { 1187 .type = CPUID_FEATURE_WORD, 1188 .feat_names = { 1189 "npt", "lbrv", "svm-lock", "nrip-save", 1190 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists", 1191 NULL, NULL, "pause-filter", NULL, 1192 "pfthreshold", "avic", NULL, "v-vmsave-vmload", 1193 "vgif", NULL, NULL, NULL, 1194 NULL, NULL, NULL, NULL, 1195 NULL, "vnmi", NULL, NULL, 1196 "svme-addr-chk", NULL, NULL, NULL, 1197 }, 1198 .cpuid = { .eax = 0x8000000A, .reg = R_EDX, }, 1199 .tcg_features = TCG_SVM_FEATURES, 1200 }, 1201 [FEAT_7_0_EBX] = { 1202 .type = CPUID_FEATURE_WORD, 1203 .feat_names = { 1204 "fsgsbase", "tsc-adjust", "sgx", "bmi1", 1205 "hle", "avx2", "fdp-excptn-only", "smep", 1206 "bmi2", "erms", "invpcid", "rtm", 1207 NULL, "zero-fcs-fds", "mpx", NULL, 1208 "avx512f", "avx512dq", "rdseed", "adx", 1209 "smap", "avx512ifma", "pcommit", "clflushopt", 1210 "clwb", "intel-pt", "avx512pf", "avx512er", 1211 "avx512cd", "sha-ni", "avx512bw", "avx512vl", 1212 }, 1213 .cpuid = { 1214 .eax = 7, 1215 .needs_ecx = true, .ecx = 0, 1216 .reg = R_EBX, 1217 }, 1218 .tcg_features = TCG_7_0_EBX_FEATURES, 1219 }, 1220 [FEAT_7_0_ECX] = { 1221 .type = CPUID_FEATURE_WORD, 1222 .feat_names = { 1223 NULL, "avx512vbmi", "umip", "pku", 1224 NULL /* ospke */, "waitpkg", "avx512vbmi2", NULL, 1225 "gfni", "vaes", "vpclmulqdq", "avx512vnni", 1226 "avx512bitalg", NULL, "avx512-vpopcntdq", NULL, 1227 "la57", NULL, NULL, NULL, 1228 NULL, NULL, "rdpid", NULL, 1229 "bus-lock-detect", "cldemote", NULL, "movdiri", 1230 "movdir64b", NULL, "sgxlc", "pks", 1231 }, 1232 .cpuid = { 1233 .eax = 7, 1234 .needs_ecx = true, .ecx = 0, 1235 .reg = R_ECX, 1236 }, 1237 .tcg_features = TCG_7_0_ECX_FEATURES, 1238 }, 1239 [FEAT_7_0_EDX] = { 1240 .type = CPUID_FEATURE_WORD, 1241 .feat_names = { 1242 NULL, NULL, "avx512-4vnniw", "avx512-4fmaps", 1243 "fsrm", NULL, NULL, NULL, 1244 "avx512-vp2intersect", NULL, "md-clear", NULL, 1245 NULL, NULL, "serialize", NULL, 1246 "tsx-ldtrk", NULL, NULL /* pconfig */, "arch-lbr", 1247 NULL, NULL, "amx-bf16", "avx512-fp16", 1248 "amx-tile", "amx-int8", "spec-ctrl", "stibp", 1249 "flush-l1d", "arch-capabilities", "core-capability", "ssbd", 1250 }, 1251 .cpuid = { 1252 .eax = 7, 1253 .needs_ecx = true, .ecx = 0, 1254 .reg = R_EDX, 1255 }, 1256 .tcg_features = TCG_7_0_EDX_FEATURES, 1257 }, 1258 [FEAT_7_1_EAX] = { 1259 .type = CPUID_FEATURE_WORD, 1260 .feat_names = { 1261 "sha512", "sm3", "sm4", NULL, 1262 "avx-vnni", "avx512-bf16", NULL, "cmpccxadd", 1263 NULL, NULL, "fzrm", "fsrs", 1264 "fsrc", NULL, NULL, NULL, 1265 NULL, "fred", "lkgs", "wrmsrns", 1266 NULL, "amx-fp16", NULL, "avx-ifma", 1267 NULL, NULL, "lam", NULL, 1268 NULL, NULL, NULL, NULL, 1269 }, 1270 .cpuid = { 1271 .eax = 7, 1272 .needs_ecx = true, .ecx = 1, 1273 .reg = R_EAX, 1274 }, 1275 .tcg_features = TCG_7_1_EAX_FEATURES, 1276 }, 1277 [FEAT_7_1_ECX] = { 1278 .type = CPUID_FEATURE_WORD, 1279 .feat_names = { 1280 NULL, NULL, NULL, NULL, 1281 NULL, "msr-imm", NULL, NULL, 1282 NULL, NULL, NULL, NULL, 1283 NULL, NULL, NULL, NULL, 1284 NULL, NULL, NULL, NULL, 1285 NULL, NULL, NULL, NULL, 1286 NULL, NULL, NULL, NULL, 1287 NULL, NULL, NULL, NULL, 1288 }, 1289 .cpuid = { 1290 .eax = 7, 1291 .needs_ecx = true, .ecx = 1, 1292 .reg = R_ECX, 1293 }, 1294 .tcg_features = TCG_7_1_ECX_FEATURES, 1295 }, 1296 [FEAT_7_1_EDX] = { 1297 .type = CPUID_FEATURE_WORD, 1298 .feat_names = { 1299 NULL, NULL, NULL, NULL, 1300 "avx-vnni-int8", "avx-ne-convert", NULL, NULL, 1301 "amx-complex", NULL, "avx-vnni-int16", NULL, 1302 NULL, NULL, "prefetchiti", NULL, 1303 NULL, NULL, NULL, "avx10", 1304 NULL, NULL, NULL, NULL, 1305 NULL, NULL, NULL, NULL, 1306 NULL, NULL, NULL, NULL, 1307 }, 1308 .cpuid = { 1309 .eax = 7, 1310 .needs_ecx = true, .ecx = 1, 1311 .reg = R_EDX, 1312 }, 1313 .tcg_features = TCG_7_1_EDX_FEATURES, 1314 }, 1315 [FEAT_7_2_EDX] = { 1316 .type = CPUID_FEATURE_WORD, 1317 .feat_names = { 1318 "intel-psfd", "ipred-ctrl", "rrsba-ctrl", "ddpd-u", 1319 "bhi-ctrl", "mcdt-no", NULL, NULL, 1320 NULL, NULL, NULL, NULL, 1321 NULL, NULL, NULL, NULL, 1322 NULL, NULL, NULL, NULL, 1323 NULL, NULL, NULL, NULL, 1324 NULL, NULL, NULL, NULL, 1325 NULL, NULL, NULL, NULL, 1326 }, 1327 .cpuid = { 1328 .eax = 7, 1329 .needs_ecx = true, .ecx = 2, 1330 .reg = R_EDX, 1331 }, 1332 .tcg_features = TCG_7_2_EDX_FEATURES, 1333 }, 1334 [FEAT_24_0_EBX] = { 1335 .type = CPUID_FEATURE_WORD, 1336 .feat_names = { 1337 [16] = "avx10-128", 1338 [17] = "avx10-256", 1339 [18] = "avx10-512", 1340 }, 1341 .cpuid = { 1342 .eax = 0x24, 1343 .needs_ecx = true, .ecx = 0, 1344 .reg = R_EBX, 1345 }, 1346 .tcg_features = TCG_24_0_EBX_FEATURES, 1347 }, 1348 [FEAT_8000_0007_EDX] = { 1349 .type = CPUID_FEATURE_WORD, 1350 .feat_names = { 1351 NULL, NULL, NULL, NULL, 1352 NULL, NULL, NULL, NULL, 1353 "invtsc", NULL, NULL, NULL, 1354 NULL, NULL, NULL, NULL, 1355 NULL, NULL, NULL, NULL, 1356 NULL, NULL, NULL, NULL, 1357 NULL, NULL, NULL, NULL, 1358 NULL, NULL, NULL, NULL, 1359 }, 1360 .cpuid = { .eax = 0x80000007, .reg = R_EDX, }, 1361 .tcg_features = TCG_APM_FEATURES, 1362 .unmigratable_flags = CPUID_APM_INVTSC, 1363 }, 1364 [FEAT_8000_0007_EBX] = { 1365 .type = CPUID_FEATURE_WORD, 1366 .feat_names = { 1367 "overflow-recov", "succor", NULL, NULL, 1368 NULL, NULL, NULL, NULL, 1369 NULL, NULL, NULL, NULL, 1370 NULL, NULL, NULL, NULL, 1371 NULL, NULL, NULL, NULL, 1372 NULL, NULL, NULL, NULL, 1373 NULL, NULL, NULL, NULL, 1374 NULL, NULL, NULL, NULL, 1375 }, 1376 .cpuid = { .eax = 0x80000007, .reg = R_EBX, }, 1377 .tcg_features = 0, 1378 .unmigratable_flags = 0, 1379 }, 1380 [FEAT_8000_0008_EBX] = { 1381 .type = CPUID_FEATURE_WORD, 1382 .feat_names = { 1383 "clzero", NULL, "xsaveerptr", NULL, 1384 NULL, NULL, NULL, NULL, 1385 NULL, "wbnoinvd", NULL, NULL, 1386 "ibpb", NULL, "ibrs", "amd-stibp", 1387 NULL, "stibp-always-on", NULL, NULL, 1388 NULL, NULL, NULL, NULL, 1389 "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL, 1390 "amd-psfd", NULL, NULL, NULL, 1391 }, 1392 .cpuid = { .eax = 0x80000008, .reg = R_EBX, }, 1393 .tcg_features = TCG_8000_0008_EBX, 1394 .unmigratable_flags = 0, 1395 }, 1396 [FEAT_8000_0021_EAX] = { 1397 .type = CPUID_FEATURE_WORD, 1398 .feat_names = { 1399 "no-nested-data-bp", "fs-gs-base-ns", "lfence-always-serializing", NULL, 1400 NULL, NULL, "null-sel-clr-base", NULL, 1401 "auto-ibrs", NULL, NULL, NULL, 1402 NULL, NULL, NULL, NULL, 1403 NULL, NULL, NULL, NULL, 1404 "prefetchi", NULL, NULL, NULL, 1405 "eraps", NULL, NULL, "sbpb", 1406 "ibpb-brtype", "srso-no", "srso-user-kernel-no", NULL, 1407 }, 1408 .cpuid = { .eax = 0x80000021, .reg = R_EAX, }, 1409 .tcg_features = TCG_8000_0021_EAX_FEATURES, 1410 .unmigratable_flags = 0, 1411 }, 1412 [FEAT_8000_0021_EBX] = { 1413 .type = CPUID_FEATURE_WORD, 1414 .cpuid = { .eax = 0x80000021, .reg = R_EBX, }, 1415 .tcg_features = 0, 1416 .unmigratable_flags = 0, 1417 }, 1418 [FEAT_8000_0022_EAX] = { 1419 .type = CPUID_FEATURE_WORD, 1420 .feat_names = { 1421 "perfmon-v2", NULL, NULL, NULL, 1422 NULL, NULL, NULL, NULL, 1423 NULL, NULL, NULL, NULL, 1424 NULL, NULL, NULL, NULL, 1425 NULL, NULL, NULL, NULL, 1426 NULL, NULL, NULL, NULL, 1427 NULL, NULL, NULL, NULL, 1428 NULL, NULL, NULL, NULL, 1429 }, 1430 .cpuid = { .eax = 0x80000022, .reg = R_EAX, }, 1431 .tcg_features = 0, 1432 .unmigratable_flags = 0, 1433 }, 1434 [FEAT_XSAVE] = { 1435 .type = CPUID_FEATURE_WORD, 1436 .feat_names = { 1437 "xsaveopt", "xsavec", "xgetbv1", "xsaves", 1438 "xfd", NULL, NULL, NULL, 1439 NULL, NULL, NULL, NULL, 1440 NULL, NULL, NULL, NULL, 1441 NULL, NULL, NULL, NULL, 1442 NULL, NULL, NULL, NULL, 1443 NULL, NULL, NULL, NULL, 1444 NULL, NULL, NULL, NULL, 1445 }, 1446 .cpuid = { 1447 .eax = 0xd, 1448 .needs_ecx = true, .ecx = 1, 1449 .reg = R_EAX, 1450 }, 1451 .tcg_features = TCG_XSAVE_FEATURES, 1452 }, 1453 [FEAT_XSAVE_XSS_LO] = { 1454 .type = CPUID_FEATURE_WORD, 1455 .feat_names = { 1456 NULL, NULL, NULL, NULL, 1457 NULL, NULL, NULL, NULL, 1458 NULL, NULL, NULL, NULL, 1459 NULL, NULL, NULL, NULL, 1460 NULL, NULL, NULL, NULL, 1461 NULL, NULL, NULL, NULL, 1462 NULL, NULL, NULL, NULL, 1463 NULL, NULL, NULL, NULL, 1464 }, 1465 .cpuid = { 1466 .eax = 0xD, 1467 .needs_ecx = true, 1468 .ecx = 1, 1469 .reg = R_ECX, 1470 }, 1471 }, 1472 [FEAT_XSAVE_XSS_HI] = { 1473 .type = CPUID_FEATURE_WORD, 1474 .cpuid = { 1475 .eax = 0xD, 1476 .needs_ecx = true, 1477 .ecx = 1, 1478 .reg = R_EDX 1479 }, 1480 }, 1481 [FEAT_6_EAX] = { 1482 .type = CPUID_FEATURE_WORD, 1483 .feat_names = { 1484 NULL, NULL, "arat", NULL, 1485 NULL, NULL, NULL, NULL, 1486 NULL, NULL, NULL, NULL, 1487 NULL, NULL, NULL, NULL, 1488 NULL, NULL, NULL, NULL, 1489 NULL, NULL, NULL, NULL, 1490 NULL, NULL, NULL, NULL, 1491 NULL, NULL, NULL, NULL, 1492 }, 1493 .cpuid = { .eax = 6, .reg = R_EAX, }, 1494 .tcg_features = TCG_6_EAX_FEATURES, 1495 }, 1496 [FEAT_XSAVE_XCR0_LO] = { 1497 .type = CPUID_FEATURE_WORD, 1498 .cpuid = { 1499 .eax = 0xD, 1500 .needs_ecx = true, .ecx = 0, 1501 .reg = R_EAX, 1502 }, 1503 .tcg_features = XSTATE_FP_MASK | XSTATE_SSE_MASK | 1504 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK | 1505 XSTATE_PKRU_MASK, 1506 .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK | 1507 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK | 1508 XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK | 1509 XSTATE_PKRU_MASK, 1510 }, 1511 [FEAT_XSAVE_XCR0_HI] = { 1512 .type = CPUID_FEATURE_WORD, 1513 .cpuid = { 1514 .eax = 0xD, 1515 .needs_ecx = true, .ecx = 0, 1516 .reg = R_EDX, 1517 }, 1518 .tcg_features = 0U, 1519 }, 1520 /*Below are MSR exposed features*/ 1521 [FEAT_ARCH_CAPABILITIES] = { 1522 .type = MSR_FEATURE_WORD, 1523 .feat_names = { 1524 "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry", 1525 "ssb-no", "mds-no", "pschange-mc-no", "tsx-ctrl", 1526 "taa-no", NULL, NULL, NULL, 1527 NULL, "sbdr-ssdp-no", "fbsdp-no", "psdp-no", 1528 NULL, "fb-clear", NULL, NULL, 1529 "bhi-no", NULL, NULL, NULL, 1530 "pbrsb-no", NULL, "gds-no", "rfds-no", 1531 "rfds-clear", NULL, NULL, NULL, 1532 NULL, NULL, NULL, NULL, 1533 NULL, NULL, NULL, NULL, 1534 NULL, NULL, NULL, NULL, 1535 NULL, NULL, NULL, NULL, 1536 NULL, NULL, NULL, NULL, 1537 NULL, NULL, NULL, NULL, 1538 NULL, NULL, NULL, NULL, 1539 NULL, NULL, "its-no", NULL, 1540 }, 1541 .msr = { 1542 .index = MSR_IA32_ARCH_CAPABILITIES, 1543 }, 1544 /* 1545 * FEAT_ARCH_CAPABILITIES only affects a read-only MSR, which 1546 * cannot be read from user mode. Therefore, it has no impact 1547 > on any user-mode operation, and warnings about unsupported 1548 * features do not matter. 1549 */ 1550 .tcg_features = ~0U, 1551 }, 1552 [FEAT_CORE_CAPABILITY] = { 1553 .type = MSR_FEATURE_WORD, 1554 .feat_names = { 1555 NULL, NULL, NULL, NULL, 1556 NULL, "split-lock-detect", NULL, NULL, 1557 NULL, NULL, NULL, NULL, 1558 NULL, NULL, NULL, NULL, 1559 NULL, NULL, NULL, NULL, 1560 NULL, NULL, NULL, NULL, 1561 NULL, NULL, NULL, NULL, 1562 NULL, NULL, NULL, NULL, 1563 }, 1564 .msr = { 1565 .index = MSR_IA32_CORE_CAPABILITY, 1566 }, 1567 }, 1568 [FEAT_PERF_CAPABILITIES] = { 1569 .type = MSR_FEATURE_WORD, 1570 .feat_names = { 1571 NULL, NULL, NULL, NULL, 1572 NULL, NULL, NULL, NULL, 1573 NULL, NULL, NULL, NULL, 1574 NULL, "full-width-write", NULL, NULL, 1575 NULL, NULL, NULL, NULL, 1576 NULL, NULL, NULL, NULL, 1577 NULL, NULL, NULL, NULL, 1578 NULL, NULL, NULL, NULL, 1579 }, 1580 .msr = { 1581 .index = MSR_IA32_PERF_CAPABILITIES, 1582 }, 1583 }, 1584 1585 [FEAT_VMX_PROCBASED_CTLS] = { 1586 .type = MSR_FEATURE_WORD, 1587 .feat_names = { 1588 NULL, NULL, "vmx-vintr-pending", "vmx-tsc-offset", 1589 NULL, NULL, NULL, "vmx-hlt-exit", 1590 NULL, "vmx-invlpg-exit", "vmx-mwait-exit", "vmx-rdpmc-exit", 1591 "vmx-rdtsc-exit", NULL, NULL, "vmx-cr3-load-noexit", 1592 "vmx-cr3-store-noexit", NULL, NULL, "vmx-cr8-load-exit", 1593 "vmx-cr8-store-exit", "vmx-flexpriority", "vmx-vnmi-pending", "vmx-movdr-exit", 1594 "vmx-io-exit", "vmx-io-bitmap", NULL, "vmx-mtf", 1595 "vmx-msr-bitmap", "vmx-monitor-exit", "vmx-pause-exit", "vmx-secondary-ctls", 1596 }, 1597 .msr = { 1598 .index = MSR_IA32_VMX_TRUE_PROCBASED_CTLS, 1599 } 1600 }, 1601 1602 [FEAT_VMX_SECONDARY_CTLS] = { 1603 .type = MSR_FEATURE_WORD, 1604 .feat_names = { 1605 "vmx-apicv-xapic", "vmx-ept", "vmx-desc-exit", "vmx-rdtscp-exit", 1606 "vmx-apicv-x2apic", "vmx-vpid", "vmx-wbinvd-exit", "vmx-unrestricted-guest", 1607 "vmx-apicv-register", "vmx-apicv-vid", "vmx-ple", "vmx-rdrand-exit", 1608 "vmx-invpcid-exit", "vmx-vmfunc", "vmx-shadow-vmcs", "vmx-encls-exit", 1609 "vmx-rdseed-exit", "vmx-pml", NULL, NULL, 1610 "vmx-xsaves", NULL, NULL, NULL, 1611 NULL, "vmx-tsc-scaling", "vmx-enable-user-wait-pause", NULL, 1612 NULL, NULL, NULL, NULL, 1613 }, 1614 .msr = { 1615 .index = MSR_IA32_VMX_PROCBASED_CTLS2, 1616 } 1617 }, 1618 1619 [FEAT_VMX_PINBASED_CTLS] = { 1620 .type = MSR_FEATURE_WORD, 1621 .feat_names = { 1622 "vmx-intr-exit", NULL, NULL, "vmx-nmi-exit", 1623 NULL, "vmx-vnmi", "vmx-preemption-timer", "vmx-posted-intr", 1624 NULL, NULL, NULL, NULL, 1625 NULL, NULL, NULL, NULL, 1626 NULL, NULL, NULL, NULL, 1627 NULL, NULL, NULL, NULL, 1628 NULL, NULL, NULL, NULL, 1629 NULL, NULL, NULL, NULL, 1630 }, 1631 .msr = { 1632 .index = MSR_IA32_VMX_TRUE_PINBASED_CTLS, 1633 } 1634 }, 1635 1636 [FEAT_VMX_EXIT_CTLS] = { 1637 .type = MSR_FEATURE_WORD, 1638 /* 1639 * VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE is copied from 1640 * the LM CPUID bit. 1641 */ 1642 .feat_names = { 1643 NULL, NULL, "vmx-exit-nosave-debugctl", NULL, 1644 NULL, NULL, NULL, NULL, 1645 NULL, NULL /* vmx-exit-host-addr-space-size */, NULL, NULL, 1646 "vmx-exit-load-perf-global-ctrl", NULL, NULL, "vmx-exit-ack-intr", 1647 NULL, NULL, "vmx-exit-save-pat", "vmx-exit-load-pat", 1648 "vmx-exit-save-efer", "vmx-exit-load-efer", 1649 "vmx-exit-save-preemption-timer", "vmx-exit-clear-bndcfgs", 1650 NULL, "vmx-exit-clear-rtit-ctl", NULL, NULL, 1651 NULL, "vmx-exit-load-pkrs", NULL, "vmx-exit-secondary-ctls", 1652 }, 1653 .msr = { 1654 .index = MSR_IA32_VMX_TRUE_EXIT_CTLS, 1655 } 1656 }, 1657 1658 [FEAT_VMX_ENTRY_CTLS] = { 1659 .type = MSR_FEATURE_WORD, 1660 .feat_names = { 1661 NULL, NULL, "vmx-entry-noload-debugctl", NULL, 1662 NULL, NULL, NULL, NULL, 1663 NULL, "vmx-entry-ia32e-mode", NULL, NULL, 1664 NULL, "vmx-entry-load-perf-global-ctrl", "vmx-entry-load-pat", "vmx-entry-load-efer", 1665 "vmx-entry-load-bndcfgs", NULL, "vmx-entry-load-rtit-ctl", NULL, 1666 NULL, NULL, "vmx-entry-load-pkrs", "vmx-entry-load-fred", 1667 NULL, NULL, NULL, NULL, 1668 NULL, NULL, NULL, NULL, 1669 }, 1670 .msr = { 1671 .index = MSR_IA32_VMX_TRUE_ENTRY_CTLS, 1672 } 1673 }, 1674 1675 [FEAT_VMX_MISC] = { 1676 .type = MSR_FEATURE_WORD, 1677 .feat_names = { 1678 NULL, NULL, NULL, NULL, 1679 NULL, "vmx-store-lma", "vmx-activity-hlt", "vmx-activity-shutdown", 1680 "vmx-activity-wait-sipi", NULL, NULL, NULL, 1681 NULL, NULL, NULL, NULL, 1682 NULL, NULL, NULL, NULL, 1683 NULL, NULL, NULL, NULL, 1684 NULL, NULL, NULL, NULL, 1685 NULL, "vmx-vmwrite-vmexit-fields", "vmx-zero-len-inject", NULL, 1686 }, 1687 .msr = { 1688 .index = MSR_IA32_VMX_MISC, 1689 } 1690 }, 1691 1692 [FEAT_VMX_EPT_VPID_CAPS] = { 1693 .type = MSR_FEATURE_WORD, 1694 .feat_names = { 1695 "vmx-ept-execonly", NULL, NULL, NULL, 1696 NULL, NULL, "vmx-page-walk-4", "vmx-page-walk-5", 1697 NULL, NULL, NULL, NULL, 1698 NULL, NULL, NULL, NULL, 1699 "vmx-ept-2mb", "vmx-ept-1gb", NULL, NULL, 1700 "vmx-invept", "vmx-eptad", "vmx-ept-advanced-exitinfo", NULL, 1701 NULL, "vmx-invept-single-context", "vmx-invept-all-context", NULL, 1702 NULL, NULL, NULL, NULL, 1703 "vmx-invvpid", NULL, NULL, NULL, 1704 NULL, NULL, NULL, NULL, 1705 "vmx-invvpid-single-addr", "vmx-invept-single-context", 1706 "vmx-invvpid-all-context", "vmx-invept-single-context-noglobals", 1707 NULL, NULL, NULL, NULL, 1708 NULL, NULL, NULL, NULL, 1709 NULL, NULL, NULL, NULL, 1710 NULL, NULL, NULL, NULL, 1711 NULL, NULL, NULL, NULL, 1712 }, 1713 .msr = { 1714 .index = MSR_IA32_VMX_EPT_VPID_CAP, 1715 } 1716 }, 1717 1718 [FEAT_VMX_BASIC] = { 1719 .type = MSR_FEATURE_WORD, 1720 .feat_names = { 1721 [54] = "vmx-ins-outs", 1722 [55] = "vmx-true-ctls", 1723 [56] = "vmx-any-errcode", 1724 [58] = "vmx-nested-exception", 1725 }, 1726 .msr = { 1727 .index = MSR_IA32_VMX_BASIC, 1728 }, 1729 /* Just to be safe - we don't support setting the MSEG version field. */ 1730 .no_autoenable_flags = MSR_VMX_BASIC_DUAL_MONITOR, 1731 }, 1732 1733 [FEAT_VMX_VMFUNC] = { 1734 .type = MSR_FEATURE_WORD, 1735 .feat_names = { 1736 [0] = "vmx-eptp-switching", 1737 }, 1738 .msr = { 1739 .index = MSR_IA32_VMX_VMFUNC, 1740 } 1741 }, 1742 1743 [FEAT_14_0_ECX] = { 1744 .type = CPUID_FEATURE_WORD, 1745 .feat_names = { 1746 NULL, NULL, NULL, NULL, 1747 NULL, NULL, NULL, NULL, 1748 NULL, NULL, NULL, NULL, 1749 NULL, NULL, NULL, NULL, 1750 NULL, NULL, NULL, NULL, 1751 NULL, NULL, NULL, NULL, 1752 NULL, NULL, NULL, NULL, 1753 NULL, NULL, NULL, "intel-pt-lip", 1754 }, 1755 .cpuid = { 1756 .eax = 0x14, 1757 .needs_ecx = true, .ecx = 0, 1758 .reg = R_ECX, 1759 }, 1760 .tcg_features = TCG_14_0_ECX_FEATURES, 1761 }, 1762 1763 [FEAT_SGX_12_0_EAX] = { 1764 .type = CPUID_FEATURE_WORD, 1765 .feat_names = { 1766 "sgx1", "sgx2", NULL, NULL, 1767 NULL, NULL, NULL, NULL, 1768 NULL, NULL, NULL, "sgx-edeccssa", 1769 NULL, NULL, NULL, NULL, 1770 NULL, NULL, NULL, NULL, 1771 NULL, NULL, NULL, NULL, 1772 NULL, NULL, NULL, NULL, 1773 NULL, NULL, NULL, NULL, 1774 }, 1775 .cpuid = { 1776 .eax = 0x12, 1777 .needs_ecx = true, .ecx = 0, 1778 .reg = R_EAX, 1779 }, 1780 .tcg_features = TCG_SGX_12_0_EAX_FEATURES, 1781 }, 1782 1783 [FEAT_SGX_12_0_EBX] = { 1784 .type = CPUID_FEATURE_WORD, 1785 .feat_names = { 1786 "sgx-exinfo" , NULL, NULL, NULL, 1787 NULL, NULL, NULL, NULL, 1788 NULL, NULL, NULL, NULL, 1789 NULL, NULL, NULL, NULL, 1790 NULL, NULL, NULL, NULL, 1791 NULL, NULL, NULL, NULL, 1792 NULL, NULL, NULL, NULL, 1793 NULL, NULL, NULL, NULL, 1794 }, 1795 .cpuid = { 1796 .eax = 0x12, 1797 .needs_ecx = true, .ecx = 0, 1798 .reg = R_EBX, 1799 }, 1800 .tcg_features = TCG_SGX_12_0_EBX_FEATURES, 1801 }, 1802 1803 [FEAT_SGX_12_1_EAX] = { 1804 .type = CPUID_FEATURE_WORD, 1805 .feat_names = { 1806 NULL, "sgx-debug", "sgx-mode64", NULL, 1807 "sgx-provisionkey", "sgx-tokenkey", NULL, "sgx-kss", 1808 NULL, NULL, "sgx-aex-notify", NULL, 1809 NULL, NULL, NULL, NULL, 1810 NULL, NULL, NULL, NULL, 1811 NULL, NULL, NULL, NULL, 1812 NULL, NULL, NULL, NULL, 1813 NULL, NULL, NULL, NULL, 1814 }, 1815 .cpuid = { 1816 .eax = 0x12, 1817 .needs_ecx = true, .ecx = 1, 1818 .reg = R_EAX, 1819 }, 1820 .tcg_features = TCG_SGX_12_1_EAX_FEATURES, 1821 }, 1822 }; 1823 1824 bool is_feature_word_cpuid(uint32_t feature, uint32_t index, int reg) 1825 { 1826 FeatureWordInfo *wi; 1827 FeatureWord w; 1828 1829 for (w = 0; w < FEATURE_WORDS; w++) { 1830 wi = &feature_word_info[w]; 1831 if (wi->type == CPUID_FEATURE_WORD && wi->cpuid.eax == feature && 1832 (!wi->cpuid.needs_ecx || wi->cpuid.ecx == index) && 1833 wi->cpuid.reg == reg) { 1834 return true; 1835 } 1836 } 1837 return false; 1838 } 1839 1840 static FeatureDep feature_dependencies[] = { 1841 { 1842 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_ARCH_CAPABILITIES }, 1843 .to = { FEAT_ARCH_CAPABILITIES, ~0ull }, 1844 }, 1845 { 1846 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_CORE_CAPABILITY }, 1847 .to = { FEAT_CORE_CAPABILITY, ~0ull }, 1848 }, 1849 { 1850 .from = { FEAT_1_ECX, CPUID_EXT_PDCM }, 1851 .to = { FEAT_PERF_CAPABILITIES, ~0ull }, 1852 }, 1853 { 1854 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1855 .to = { FEAT_VMX_PROCBASED_CTLS, ~0ull }, 1856 }, 1857 { 1858 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1859 .to = { FEAT_VMX_PINBASED_CTLS, ~0ull }, 1860 }, 1861 { 1862 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1863 .to = { FEAT_VMX_EXIT_CTLS, ~0ull }, 1864 }, 1865 { 1866 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1867 .to = { FEAT_VMX_ENTRY_CTLS, ~0ull }, 1868 }, 1869 { 1870 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1871 .to = { FEAT_VMX_MISC, ~0ull }, 1872 }, 1873 { 1874 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1875 .to = { FEAT_VMX_BASIC, ~0ull }, 1876 }, 1877 { 1878 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_LM }, 1879 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_IA32E_MODE }, 1880 }, 1881 { 1882 .from = { FEAT_VMX_PROCBASED_CTLS, VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS }, 1883 .to = { FEAT_VMX_SECONDARY_CTLS, ~0ull }, 1884 }, 1885 { 1886 .from = { FEAT_XSAVE, CPUID_XSAVE_XSAVES }, 1887 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_XSAVES }, 1888 }, 1889 { 1890 .from = { FEAT_1_ECX, CPUID_EXT_RDRAND }, 1891 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDRAND_EXITING }, 1892 }, 1893 { 1894 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INVPCID }, 1895 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_INVPCID }, 1896 }, 1897 { 1898 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_MPX }, 1899 .to = { FEAT_VMX_EXIT_CTLS, VMX_VM_EXIT_CLEAR_BNDCFGS }, 1900 }, 1901 { 1902 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_MPX }, 1903 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_LOAD_BNDCFGS }, 1904 }, 1905 { 1906 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_RDSEED }, 1907 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDSEED_EXITING }, 1908 }, 1909 { 1910 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT }, 1911 .to = { FEAT_14_0_ECX, ~0ull }, 1912 }, 1913 { 1914 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_RDTSCP }, 1915 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDTSCP }, 1916 }, 1917 { 1918 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT }, 1919 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull }, 1920 }, 1921 { 1922 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT }, 1923 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST }, 1924 }, 1925 { 1926 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VPID }, 1927 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull << 32 }, 1928 }, 1929 { 1930 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VMFUNC }, 1931 .to = { FEAT_VMX_VMFUNC, ~0ull }, 1932 }, 1933 { 1934 .from = { FEAT_8000_0001_ECX, CPUID_EXT3_SVM }, 1935 .to = { FEAT_SVM, ~0ull }, 1936 }, 1937 { 1938 .from = { FEAT_7_0_ECX, CPUID_7_0_ECX_WAITPKG }, 1939 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_USER_WAIT_PAUSE }, 1940 }, 1941 { 1942 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_LM }, 1943 .to = { FEAT_7_1_EAX, CPUID_7_1_EAX_FRED }, 1944 }, 1945 { 1946 .from = { FEAT_7_1_EAX, CPUID_7_1_EAX_LKGS }, 1947 .to = { FEAT_7_1_EAX, CPUID_7_1_EAX_FRED }, 1948 }, 1949 { 1950 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_SGX }, 1951 .to = { FEAT_7_0_ECX, CPUID_7_0_ECX_SGX_LC }, 1952 }, 1953 { 1954 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_SGX }, 1955 .to = { FEAT_SGX_12_0_EAX, ~0ull }, 1956 }, 1957 { 1958 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_SGX }, 1959 .to = { FEAT_SGX_12_0_EBX, ~0ull }, 1960 }, 1961 { 1962 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_SGX }, 1963 .to = { FEAT_SGX_12_1_EAX, ~0ull }, 1964 }, 1965 { 1966 .from = { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_128 }, 1967 .to = { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_256 }, 1968 }, 1969 { 1970 .from = { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_256 }, 1971 .to = { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_512 }, 1972 }, 1973 { 1974 .from = { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_VL_MASK }, 1975 .to = { FEAT_7_1_EDX, CPUID_7_1_EDX_AVX10 }, 1976 }, 1977 { 1978 .from = { FEAT_7_1_EDX, CPUID_7_1_EDX_AVX10 }, 1979 .to = { FEAT_24_0_EBX, ~0ull }, 1980 }, 1981 }; 1982 1983 typedef struct X86RegisterInfo32 { 1984 /* Name of register */ 1985 const char *name; 1986 /* QAPI enum value register */ 1987 X86CPURegister32 qapi_enum; 1988 } X86RegisterInfo32; 1989 1990 #define REGISTER(reg) \ 1991 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg } 1992 static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = { 1993 REGISTER(EAX), 1994 REGISTER(ECX), 1995 REGISTER(EDX), 1996 REGISTER(EBX), 1997 REGISTER(ESP), 1998 REGISTER(EBP), 1999 REGISTER(ESI), 2000 REGISTER(EDI), 2001 }; 2002 #undef REGISTER 2003 2004 ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUNT] = { 2005 [XSTATE_FP_BIT] = { 2006 /* x87 FP state component is always enabled if XSAVE is supported */ 2007 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE, 2008 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader), 2009 }, 2010 [XSTATE_SSE_BIT] = { 2011 /* SSE state component is always enabled if XSAVE is supported */ 2012 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE, 2013 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader), 2014 }, 2015 [XSTATE_YMM_BIT] = 2016 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX, 2017 .size = sizeof(XSaveAVX) }, 2018 [XSTATE_BNDREGS_BIT] = 2019 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX, 2020 .size = sizeof(XSaveBNDREG) }, 2021 [XSTATE_BNDCSR_BIT] = 2022 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX, 2023 .size = sizeof(XSaveBNDCSR) }, 2024 [XSTATE_OPMASK_BIT] = 2025 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 2026 .size = sizeof(XSaveOpmask) }, 2027 [XSTATE_ZMM_Hi256_BIT] = 2028 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 2029 .size = sizeof(XSaveZMM_Hi256) }, 2030 [XSTATE_Hi16_ZMM_BIT] = 2031 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 2032 .size = sizeof(XSaveHi16_ZMM) }, 2033 [XSTATE_PKRU_BIT] = 2034 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU, 2035 .size = sizeof(XSavePKRU) }, 2036 [XSTATE_ARCH_LBR_BIT] = { 2037 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_ARCH_LBR, 2038 .offset = 0 /*supervisor mode component, offset = 0 */, 2039 .size = sizeof(XSavesArchLBR) }, 2040 [XSTATE_XTILE_CFG_BIT] = { 2041 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_AMX_TILE, 2042 .size = sizeof(XSaveXTILECFG), 2043 }, 2044 [XSTATE_XTILE_DATA_BIT] = { 2045 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_AMX_TILE, 2046 .size = sizeof(XSaveXTILEDATA) 2047 }, 2048 }; 2049 2050 uint32_t xsave_area_size(uint64_t mask, bool compacted) 2051 { 2052 uint64_t ret = x86_ext_save_areas[0].size; 2053 const ExtSaveArea *esa; 2054 uint32_t offset = 0; 2055 int i; 2056 2057 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 2058 esa = &x86_ext_save_areas[i]; 2059 if ((mask >> i) & 1) { 2060 offset = compacted ? ret : esa->offset; 2061 ret = MAX(ret, offset + esa->size); 2062 } 2063 } 2064 return ret; 2065 } 2066 2067 static inline bool accel_uses_host_cpuid(void) 2068 { 2069 return !tcg_enabled() && !qtest_enabled(); 2070 } 2071 2072 static inline uint64_t x86_cpu_xsave_xcr0_components(X86CPU *cpu) 2073 { 2074 return ((uint64_t)cpu->env.features[FEAT_XSAVE_XCR0_HI]) << 32 | 2075 cpu->env.features[FEAT_XSAVE_XCR0_LO]; 2076 } 2077 2078 /* Return name of 32-bit register, from a R_* constant */ 2079 static const char *get_register_name_32(unsigned int reg) 2080 { 2081 if (reg >= CPU_NB_REGS32) { 2082 return NULL; 2083 } 2084 return x86_reg_info_32[reg].name; 2085 } 2086 2087 static inline uint64_t x86_cpu_xsave_xss_components(X86CPU *cpu) 2088 { 2089 return ((uint64_t)cpu->env.features[FEAT_XSAVE_XSS_HI]) << 32 | 2090 cpu->env.features[FEAT_XSAVE_XSS_LO]; 2091 } 2092 2093 /* 2094 * Returns the set of feature flags that are supported and migratable by 2095 * QEMU, for a given FeatureWord. 2096 */ 2097 static uint64_t x86_cpu_get_migratable_flags(X86CPU *cpu, FeatureWord w) 2098 { 2099 FeatureWordInfo *wi = &feature_word_info[w]; 2100 CPUX86State *env = &cpu->env; 2101 uint64_t r = 0; 2102 int i; 2103 2104 for (i = 0; i < 64; i++) { 2105 uint64_t f = 1ULL << i; 2106 2107 /* If the feature name is known, it is implicitly considered migratable, 2108 * unless it is explicitly set in unmigratable_flags */ 2109 if ((wi->migratable_flags & f) || 2110 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) { 2111 r |= f; 2112 } 2113 } 2114 2115 /* when tsc-khz is set explicitly, invtsc is migratable */ 2116 if ((w == FEAT_8000_0007_EDX) && env->user_tsc_khz) { 2117 r |= CPUID_APM_INVTSC; 2118 } 2119 2120 return r; 2121 } 2122 2123 void host_cpuid(uint32_t function, uint32_t count, 2124 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) 2125 { 2126 uint32_t vec[4]; 2127 2128 #ifdef __x86_64__ 2129 asm volatile("cpuid" 2130 : "=a"(vec[0]), "=b"(vec[1]), 2131 "=c"(vec[2]), "=d"(vec[3]) 2132 : "0"(function), "c"(count) : "cc"); 2133 #elif defined(__i386__) 2134 asm volatile("pusha \n\t" 2135 "cpuid \n\t" 2136 "mov %%eax, 0(%2) \n\t" 2137 "mov %%ebx, 4(%2) \n\t" 2138 "mov %%ecx, 8(%2) \n\t" 2139 "mov %%edx, 12(%2) \n\t" 2140 "popa" 2141 : : "a"(function), "c"(count), "S"(vec) 2142 : "memory", "cc"); 2143 #else 2144 abort(); 2145 #endif 2146 2147 if (eax) 2148 *eax = vec[0]; 2149 if (ebx) 2150 *ebx = vec[1]; 2151 if (ecx) 2152 *ecx = vec[2]; 2153 if (edx) 2154 *edx = vec[3]; 2155 } 2156 2157 /* CPU class name definitions: */ 2158 2159 /* Return type name for a given CPU model name 2160 * Caller is responsible for freeing the returned string. 2161 */ 2162 static char *x86_cpu_type_name(const char *model_name) 2163 { 2164 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name); 2165 } 2166 2167 static ObjectClass *x86_cpu_class_by_name(const char *cpu_model) 2168 { 2169 g_autofree char *typename = x86_cpu_type_name(cpu_model); 2170 return object_class_by_name(typename); 2171 } 2172 2173 static char *x86_cpu_class_get_model_name(X86CPUClass *cc) 2174 { 2175 const char *class_name = object_class_get_name(OBJECT_CLASS(cc)); 2176 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX)); 2177 return cpu_model_from_type(class_name); 2178 } 2179 2180 typedef struct X86CPUVersionDefinition { 2181 X86CPUVersion version; 2182 const char *alias; 2183 const char *note; 2184 PropValue *props; 2185 const CPUCaches *const cache_info; 2186 } X86CPUVersionDefinition; 2187 2188 /* Base definition for a CPU model */ 2189 typedef struct X86CPUDefinition { 2190 const char *name; 2191 uint32_t level; 2192 uint32_t xlevel; 2193 /* vendor is zero-terminated, 12 character ASCII string */ 2194 char vendor[CPUID_VENDOR_SZ + 1]; 2195 int family; 2196 int model; 2197 int stepping; 2198 uint8_t avx10_version; 2199 FeatureWordArray features; 2200 const char *model_id; 2201 const CPUCaches *const cache_info; 2202 /* 2203 * Definitions for alternative versions of CPU model. 2204 * List is terminated by item with version == 0. 2205 * If NULL, version 1 will be registered automatically. 2206 */ 2207 const X86CPUVersionDefinition *versions; 2208 const char *deprecation_note; 2209 } X86CPUDefinition; 2210 2211 /* Reference to a specific CPU model version */ 2212 struct X86CPUModel { 2213 /* Base CPU definition */ 2214 const X86CPUDefinition *cpudef; 2215 /* CPU model version */ 2216 X86CPUVersion version; 2217 const char *note; 2218 /* 2219 * If true, this is an alias CPU model. 2220 * This matters only for "-cpu help" and query-cpu-definitions 2221 */ 2222 bool is_alias; 2223 }; 2224 2225 /* Get full model name for CPU version */ 2226 static char *x86_cpu_versioned_model_name(const X86CPUDefinition *cpudef, 2227 X86CPUVersion version) 2228 { 2229 assert(version > 0); 2230 return g_strdup_printf("%s-v%d", cpudef->name, (int)version); 2231 } 2232 2233 static const X86CPUVersionDefinition * 2234 x86_cpu_def_get_versions(const X86CPUDefinition *def) 2235 { 2236 /* When X86CPUDefinition::versions is NULL, we register only v1 */ 2237 static const X86CPUVersionDefinition default_version_list[] = { 2238 { 1 }, 2239 { /* end of list */ } 2240 }; 2241 2242 return def->versions ?: default_version_list; 2243 } 2244 2245 static const CPUCaches epyc_cache_info = { 2246 .l1d_cache = &(CPUCacheInfo) { 2247 .type = DATA_CACHE, 2248 .level = 1, 2249 .size = 32 * KiB, 2250 .line_size = 64, 2251 .associativity = 8, 2252 .partitions = 1, 2253 .sets = 64, 2254 .lines_per_tag = 1, 2255 .self_init = 1, 2256 .no_invd_sharing = true, 2257 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2258 }, 2259 .l1i_cache = &(CPUCacheInfo) { 2260 .type = INSTRUCTION_CACHE, 2261 .level = 1, 2262 .size = 64 * KiB, 2263 .line_size = 64, 2264 .associativity = 4, 2265 .partitions = 1, 2266 .sets = 256, 2267 .lines_per_tag = 1, 2268 .self_init = 1, 2269 .no_invd_sharing = true, 2270 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2271 }, 2272 .l2_cache = &(CPUCacheInfo) { 2273 .type = UNIFIED_CACHE, 2274 .level = 2, 2275 .size = 512 * KiB, 2276 .line_size = 64, 2277 .associativity = 8, 2278 .partitions = 1, 2279 .sets = 1024, 2280 .lines_per_tag = 1, 2281 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2282 }, 2283 .l3_cache = &(CPUCacheInfo) { 2284 .type = UNIFIED_CACHE, 2285 .level = 3, 2286 .size = 8 * MiB, 2287 .line_size = 64, 2288 .associativity = 16, 2289 .partitions = 1, 2290 .sets = 8192, 2291 .lines_per_tag = 1, 2292 .self_init = true, 2293 .inclusive = true, 2294 .complex_indexing = true, 2295 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2296 }, 2297 }; 2298 2299 static CPUCaches epyc_v4_cache_info = { 2300 .l1d_cache = &(CPUCacheInfo) { 2301 .type = DATA_CACHE, 2302 .level = 1, 2303 .size = 32 * KiB, 2304 .line_size = 64, 2305 .associativity = 8, 2306 .partitions = 1, 2307 .sets = 64, 2308 .lines_per_tag = 1, 2309 .self_init = 1, 2310 .no_invd_sharing = true, 2311 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2312 }, 2313 .l1i_cache = &(CPUCacheInfo) { 2314 .type = INSTRUCTION_CACHE, 2315 .level = 1, 2316 .size = 64 * KiB, 2317 .line_size = 64, 2318 .associativity = 4, 2319 .partitions = 1, 2320 .sets = 256, 2321 .lines_per_tag = 1, 2322 .self_init = 1, 2323 .no_invd_sharing = true, 2324 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2325 }, 2326 .l2_cache = &(CPUCacheInfo) { 2327 .type = UNIFIED_CACHE, 2328 .level = 2, 2329 .size = 512 * KiB, 2330 .line_size = 64, 2331 .associativity = 8, 2332 .partitions = 1, 2333 .sets = 1024, 2334 .lines_per_tag = 1, 2335 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2336 }, 2337 .l3_cache = &(CPUCacheInfo) { 2338 .type = UNIFIED_CACHE, 2339 .level = 3, 2340 .size = 8 * MiB, 2341 .line_size = 64, 2342 .associativity = 16, 2343 .partitions = 1, 2344 .sets = 8192, 2345 .lines_per_tag = 1, 2346 .self_init = true, 2347 .inclusive = true, 2348 .complex_indexing = false, 2349 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2350 }, 2351 }; 2352 2353 static CPUCaches epyc_v5_cache_info = { 2354 .l1d_cache = &(CPUCacheInfo) { 2355 .type = DATA_CACHE, 2356 .level = 1, 2357 .size = 32 * KiB, 2358 .line_size = 64, 2359 .associativity = 8, 2360 .partitions = 1, 2361 .sets = 64, 2362 .lines_per_tag = 1, 2363 .self_init = true, 2364 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2365 }, 2366 .l1i_cache = &(CPUCacheInfo) { 2367 .type = INSTRUCTION_CACHE, 2368 .level = 1, 2369 .size = 64 * KiB, 2370 .line_size = 64, 2371 .associativity = 4, 2372 .partitions = 1, 2373 .sets = 256, 2374 .lines_per_tag = 1, 2375 .self_init = true, 2376 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2377 }, 2378 .l2_cache = &(CPUCacheInfo) { 2379 .type = UNIFIED_CACHE, 2380 .level = 2, 2381 .size = 512 * KiB, 2382 .line_size = 64, 2383 .associativity = 8, 2384 .partitions = 1, 2385 .sets = 1024, 2386 .lines_per_tag = 1, 2387 .self_init = true, 2388 .inclusive = true, 2389 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2390 }, 2391 .l3_cache = &(CPUCacheInfo) { 2392 .type = UNIFIED_CACHE, 2393 .level = 3, 2394 .size = 8 * MiB, 2395 .line_size = 64, 2396 .associativity = 16, 2397 .partitions = 1, 2398 .sets = 8192, 2399 .lines_per_tag = 1, 2400 .self_init = true, 2401 .no_invd_sharing = true, 2402 .complex_indexing = false, 2403 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2404 }, 2405 }; 2406 2407 static const CPUCaches epyc_rome_cache_info = { 2408 .l1d_cache = &(CPUCacheInfo) { 2409 .type = DATA_CACHE, 2410 .level = 1, 2411 .size = 32 * KiB, 2412 .line_size = 64, 2413 .associativity = 8, 2414 .partitions = 1, 2415 .sets = 64, 2416 .lines_per_tag = 1, 2417 .self_init = 1, 2418 .no_invd_sharing = true, 2419 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2420 }, 2421 .l1i_cache = &(CPUCacheInfo) { 2422 .type = INSTRUCTION_CACHE, 2423 .level = 1, 2424 .size = 32 * KiB, 2425 .line_size = 64, 2426 .associativity = 8, 2427 .partitions = 1, 2428 .sets = 64, 2429 .lines_per_tag = 1, 2430 .self_init = 1, 2431 .no_invd_sharing = true, 2432 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2433 }, 2434 .l2_cache = &(CPUCacheInfo) { 2435 .type = UNIFIED_CACHE, 2436 .level = 2, 2437 .size = 512 * KiB, 2438 .line_size = 64, 2439 .associativity = 8, 2440 .partitions = 1, 2441 .sets = 1024, 2442 .lines_per_tag = 1, 2443 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2444 }, 2445 .l3_cache = &(CPUCacheInfo) { 2446 .type = UNIFIED_CACHE, 2447 .level = 3, 2448 .size = 16 * MiB, 2449 .line_size = 64, 2450 .associativity = 16, 2451 .partitions = 1, 2452 .sets = 16384, 2453 .lines_per_tag = 1, 2454 .self_init = true, 2455 .inclusive = true, 2456 .complex_indexing = true, 2457 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2458 }, 2459 }; 2460 2461 static const CPUCaches epyc_rome_v3_cache_info = { 2462 .l1d_cache = &(CPUCacheInfo) { 2463 .type = DATA_CACHE, 2464 .level = 1, 2465 .size = 32 * KiB, 2466 .line_size = 64, 2467 .associativity = 8, 2468 .partitions = 1, 2469 .sets = 64, 2470 .lines_per_tag = 1, 2471 .self_init = 1, 2472 .no_invd_sharing = true, 2473 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2474 }, 2475 .l1i_cache = &(CPUCacheInfo) { 2476 .type = INSTRUCTION_CACHE, 2477 .level = 1, 2478 .size = 32 * KiB, 2479 .line_size = 64, 2480 .associativity = 8, 2481 .partitions = 1, 2482 .sets = 64, 2483 .lines_per_tag = 1, 2484 .self_init = 1, 2485 .no_invd_sharing = true, 2486 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2487 }, 2488 .l2_cache = &(CPUCacheInfo) { 2489 .type = UNIFIED_CACHE, 2490 .level = 2, 2491 .size = 512 * KiB, 2492 .line_size = 64, 2493 .associativity = 8, 2494 .partitions = 1, 2495 .sets = 1024, 2496 .lines_per_tag = 1, 2497 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2498 }, 2499 .l3_cache = &(CPUCacheInfo) { 2500 .type = UNIFIED_CACHE, 2501 .level = 3, 2502 .size = 16 * MiB, 2503 .line_size = 64, 2504 .associativity = 16, 2505 .partitions = 1, 2506 .sets = 16384, 2507 .lines_per_tag = 1, 2508 .self_init = true, 2509 .inclusive = true, 2510 .complex_indexing = false, 2511 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2512 }, 2513 }; 2514 2515 static const CPUCaches epyc_rome_v5_cache_info = { 2516 .l1d_cache = &(CPUCacheInfo) { 2517 .type = DATA_CACHE, 2518 .level = 1, 2519 .size = 32 * KiB, 2520 .line_size = 64, 2521 .associativity = 8, 2522 .partitions = 1, 2523 .sets = 64, 2524 .lines_per_tag = 1, 2525 .self_init = true, 2526 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2527 }, 2528 .l1i_cache = &(CPUCacheInfo) { 2529 .type = INSTRUCTION_CACHE, 2530 .level = 1, 2531 .size = 32 * KiB, 2532 .line_size = 64, 2533 .associativity = 8, 2534 .partitions = 1, 2535 .sets = 64, 2536 .lines_per_tag = 1, 2537 .self_init = true, 2538 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2539 }, 2540 .l2_cache = &(CPUCacheInfo) { 2541 .type = UNIFIED_CACHE, 2542 .level = 2, 2543 .size = 512 * KiB, 2544 .line_size = 64, 2545 .associativity = 8, 2546 .partitions = 1, 2547 .sets = 1024, 2548 .lines_per_tag = 1, 2549 .self_init = true, 2550 .inclusive = true, 2551 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2552 }, 2553 .l3_cache = &(CPUCacheInfo) { 2554 .type = UNIFIED_CACHE, 2555 .level = 3, 2556 .size = 16 * MiB, 2557 .line_size = 64, 2558 .associativity = 16, 2559 .partitions = 1, 2560 .sets = 16384, 2561 .lines_per_tag = 1, 2562 .self_init = true, 2563 .no_invd_sharing = true, 2564 .complex_indexing = false, 2565 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2566 }, 2567 }; 2568 2569 static const CPUCaches epyc_milan_cache_info = { 2570 .l1d_cache = &(CPUCacheInfo) { 2571 .type = DATA_CACHE, 2572 .level = 1, 2573 .size = 32 * KiB, 2574 .line_size = 64, 2575 .associativity = 8, 2576 .partitions = 1, 2577 .sets = 64, 2578 .lines_per_tag = 1, 2579 .self_init = 1, 2580 .no_invd_sharing = true, 2581 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2582 }, 2583 .l1i_cache = &(CPUCacheInfo) { 2584 .type = INSTRUCTION_CACHE, 2585 .level = 1, 2586 .size = 32 * KiB, 2587 .line_size = 64, 2588 .associativity = 8, 2589 .partitions = 1, 2590 .sets = 64, 2591 .lines_per_tag = 1, 2592 .self_init = 1, 2593 .no_invd_sharing = true, 2594 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2595 }, 2596 .l2_cache = &(CPUCacheInfo) { 2597 .type = UNIFIED_CACHE, 2598 .level = 2, 2599 .size = 512 * KiB, 2600 .line_size = 64, 2601 .associativity = 8, 2602 .partitions = 1, 2603 .sets = 1024, 2604 .lines_per_tag = 1, 2605 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2606 }, 2607 .l3_cache = &(CPUCacheInfo) { 2608 .type = UNIFIED_CACHE, 2609 .level = 3, 2610 .size = 32 * MiB, 2611 .line_size = 64, 2612 .associativity = 16, 2613 .partitions = 1, 2614 .sets = 32768, 2615 .lines_per_tag = 1, 2616 .self_init = true, 2617 .inclusive = true, 2618 .complex_indexing = true, 2619 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2620 }, 2621 }; 2622 2623 static const CPUCaches epyc_milan_v2_cache_info = { 2624 .l1d_cache = &(CPUCacheInfo) { 2625 .type = DATA_CACHE, 2626 .level = 1, 2627 .size = 32 * KiB, 2628 .line_size = 64, 2629 .associativity = 8, 2630 .partitions = 1, 2631 .sets = 64, 2632 .lines_per_tag = 1, 2633 .self_init = 1, 2634 .no_invd_sharing = true, 2635 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2636 }, 2637 .l1i_cache = &(CPUCacheInfo) { 2638 .type = INSTRUCTION_CACHE, 2639 .level = 1, 2640 .size = 32 * KiB, 2641 .line_size = 64, 2642 .associativity = 8, 2643 .partitions = 1, 2644 .sets = 64, 2645 .lines_per_tag = 1, 2646 .self_init = 1, 2647 .no_invd_sharing = true, 2648 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2649 }, 2650 .l2_cache = &(CPUCacheInfo) { 2651 .type = UNIFIED_CACHE, 2652 .level = 2, 2653 .size = 512 * KiB, 2654 .line_size = 64, 2655 .associativity = 8, 2656 .partitions = 1, 2657 .sets = 1024, 2658 .lines_per_tag = 1, 2659 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2660 }, 2661 .l3_cache = &(CPUCacheInfo) { 2662 .type = UNIFIED_CACHE, 2663 .level = 3, 2664 .size = 32 * MiB, 2665 .line_size = 64, 2666 .associativity = 16, 2667 .partitions = 1, 2668 .sets = 32768, 2669 .lines_per_tag = 1, 2670 .self_init = true, 2671 .inclusive = true, 2672 .complex_indexing = false, 2673 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2674 }, 2675 }; 2676 2677 static const CPUCaches epyc_milan_v3_cache_info = { 2678 .l1d_cache = &(CPUCacheInfo) { 2679 .type = DATA_CACHE, 2680 .level = 1, 2681 .size = 32 * KiB, 2682 .line_size = 64, 2683 .associativity = 8, 2684 .partitions = 1, 2685 .sets = 64, 2686 .lines_per_tag = 1, 2687 .self_init = true, 2688 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2689 }, 2690 .l1i_cache = &(CPUCacheInfo) { 2691 .type = INSTRUCTION_CACHE, 2692 .level = 1, 2693 .size = 32 * KiB, 2694 .line_size = 64, 2695 .associativity = 8, 2696 .partitions = 1, 2697 .sets = 64, 2698 .lines_per_tag = 1, 2699 .self_init = true, 2700 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2701 }, 2702 .l2_cache = &(CPUCacheInfo) { 2703 .type = UNIFIED_CACHE, 2704 .level = 2, 2705 .size = 512 * KiB, 2706 .line_size = 64, 2707 .associativity = 8, 2708 .partitions = 1, 2709 .sets = 1024, 2710 .lines_per_tag = 1, 2711 .self_init = true, 2712 .inclusive = true, 2713 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2714 }, 2715 .l3_cache = &(CPUCacheInfo) { 2716 .type = UNIFIED_CACHE, 2717 .level = 3, 2718 .size = 32 * MiB, 2719 .line_size = 64, 2720 .associativity = 16, 2721 .partitions = 1, 2722 .sets = 32768, 2723 .lines_per_tag = 1, 2724 .self_init = true, 2725 .no_invd_sharing = true, 2726 .complex_indexing = false, 2727 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2728 }, 2729 }; 2730 2731 static const CPUCaches epyc_genoa_cache_info = { 2732 .l1d_cache = &(CPUCacheInfo) { 2733 .type = DATA_CACHE, 2734 .level = 1, 2735 .size = 32 * KiB, 2736 .line_size = 64, 2737 .associativity = 8, 2738 .partitions = 1, 2739 .sets = 64, 2740 .lines_per_tag = 1, 2741 .self_init = 1, 2742 .no_invd_sharing = true, 2743 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2744 }, 2745 .l1i_cache = &(CPUCacheInfo) { 2746 .type = INSTRUCTION_CACHE, 2747 .level = 1, 2748 .size = 32 * KiB, 2749 .line_size = 64, 2750 .associativity = 8, 2751 .partitions = 1, 2752 .sets = 64, 2753 .lines_per_tag = 1, 2754 .self_init = 1, 2755 .no_invd_sharing = true, 2756 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2757 }, 2758 .l2_cache = &(CPUCacheInfo) { 2759 .type = UNIFIED_CACHE, 2760 .level = 2, 2761 .size = 1 * MiB, 2762 .line_size = 64, 2763 .associativity = 8, 2764 .partitions = 1, 2765 .sets = 2048, 2766 .lines_per_tag = 1, 2767 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2768 }, 2769 .l3_cache = &(CPUCacheInfo) { 2770 .type = UNIFIED_CACHE, 2771 .level = 3, 2772 .size = 32 * MiB, 2773 .line_size = 64, 2774 .associativity = 16, 2775 .partitions = 1, 2776 .sets = 32768, 2777 .lines_per_tag = 1, 2778 .self_init = true, 2779 .inclusive = true, 2780 .complex_indexing = false, 2781 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2782 }, 2783 }; 2784 2785 static const CPUCaches epyc_genoa_v2_cache_info = { 2786 .l1d_cache = &(CPUCacheInfo) { 2787 .type = DATA_CACHE, 2788 .level = 1, 2789 .size = 32 * KiB, 2790 .line_size = 64, 2791 .associativity = 8, 2792 .partitions = 1, 2793 .sets = 64, 2794 .lines_per_tag = 1, 2795 .self_init = true, 2796 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2797 }, 2798 .l1i_cache = &(CPUCacheInfo) { 2799 .type = INSTRUCTION_CACHE, 2800 .level = 1, 2801 .size = 32 * KiB, 2802 .line_size = 64, 2803 .associativity = 8, 2804 .partitions = 1, 2805 .sets = 64, 2806 .lines_per_tag = 1, 2807 .self_init = true, 2808 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2809 }, 2810 .l2_cache = &(CPUCacheInfo) { 2811 .type = UNIFIED_CACHE, 2812 .level = 2, 2813 .size = 1 * MiB, 2814 .line_size = 64, 2815 .associativity = 8, 2816 .partitions = 1, 2817 .sets = 2048, 2818 .lines_per_tag = 1, 2819 .self_init = true, 2820 .inclusive = true, 2821 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2822 }, 2823 .l3_cache = &(CPUCacheInfo) { 2824 .type = UNIFIED_CACHE, 2825 .level = 3, 2826 .size = 32 * MiB, 2827 .line_size = 64, 2828 .associativity = 16, 2829 .partitions = 1, 2830 .sets = 32768, 2831 .lines_per_tag = 1, 2832 .self_init = true, 2833 .no_invd_sharing = true, 2834 .complex_indexing = false, 2835 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2836 }, 2837 }; 2838 2839 static const CPUCaches epyc_turin_cache_info = { 2840 .l1d_cache = &(CPUCacheInfo) { 2841 .type = DATA_CACHE, 2842 .level = 1, 2843 .size = 48 * KiB, 2844 .line_size = 64, 2845 .associativity = 12, 2846 .partitions = 1, 2847 .sets = 64, 2848 .lines_per_tag = 1, 2849 .self_init = true, 2850 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2851 }, 2852 .l1i_cache = &(CPUCacheInfo) { 2853 .type = INSTRUCTION_CACHE, 2854 .level = 1, 2855 .size = 32 * KiB, 2856 .line_size = 64, 2857 .associativity = 8, 2858 .partitions = 1, 2859 .sets = 64, 2860 .lines_per_tag = 1, 2861 .self_init = true, 2862 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2863 }, 2864 .l2_cache = &(CPUCacheInfo) { 2865 .type = UNIFIED_CACHE, 2866 .level = 2, 2867 .size = 1 * MiB, 2868 .line_size = 64, 2869 .associativity = 16, 2870 .partitions = 1, 2871 .sets = 1024, 2872 .lines_per_tag = 1, 2873 .self_init = true, 2874 .inclusive = true, 2875 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2876 }, 2877 .l3_cache = &(CPUCacheInfo) { 2878 .type = UNIFIED_CACHE, 2879 .level = 3, 2880 .size = 32 * MiB, 2881 .line_size = 64, 2882 .associativity = 16, 2883 .partitions = 1, 2884 .sets = 32768, 2885 .lines_per_tag = 1, 2886 .self_init = true, 2887 .no_invd_sharing = true, 2888 .complex_indexing = false, 2889 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2890 } 2891 }; 2892 2893 static const CPUCaches xeon_spr_cache_info = { 2894 .l1d_cache = &(CPUCacheInfo) { 2895 /* CPUID 0x4.0x0.EAX */ 2896 .type = DATA_CACHE, 2897 .level = 1, 2898 .self_init = true, 2899 2900 /* CPUID 0x4.0x0.EBX */ 2901 .line_size = 64, 2902 .partitions = 1, 2903 .associativity = 12, 2904 2905 /* CPUID 0x4.0x0.ECX */ 2906 .sets = 64, 2907 2908 /* CPUID 0x4.0x0.EDX */ 2909 .no_invd_sharing = false, 2910 .inclusive = false, 2911 .complex_indexing = false, 2912 2913 .size = 48 * KiB, 2914 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2915 }, 2916 .l1i_cache = &(CPUCacheInfo) { 2917 /* CPUID 0x4.0x1.EAX */ 2918 .type = INSTRUCTION_CACHE, 2919 .level = 1, 2920 .self_init = true, 2921 2922 /* CPUID 0x4.0x1.EBX */ 2923 .line_size = 64, 2924 .partitions = 1, 2925 .associativity = 8, 2926 2927 /* CPUID 0x4.0x1.ECX */ 2928 .sets = 64, 2929 2930 /* CPUID 0x4.0x1.EDX */ 2931 .no_invd_sharing = false, 2932 .inclusive = false, 2933 .complex_indexing = false, 2934 2935 .size = 32 * KiB, 2936 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2937 }, 2938 .l2_cache = &(CPUCacheInfo) { 2939 /* CPUID 0x4.0x2.EAX */ 2940 .type = UNIFIED_CACHE, 2941 .level = 2, 2942 .self_init = true, 2943 2944 /* CPUID 0x4.0x2.EBX */ 2945 .line_size = 64, 2946 .partitions = 1, 2947 .associativity = 16, 2948 2949 /* CPUID 0x4.0x2.ECX */ 2950 .sets = 2048, 2951 2952 /* CPUID 0x4.0x2.EDX */ 2953 .no_invd_sharing = false, 2954 .inclusive = false, 2955 .complex_indexing = false, 2956 2957 .size = 2 * MiB, 2958 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2959 }, 2960 .l3_cache = &(CPUCacheInfo) { 2961 /* CPUID 0x4.0x3.EAX */ 2962 .type = UNIFIED_CACHE, 2963 .level = 3, 2964 .self_init = true, 2965 2966 /* CPUID 0x4.0x3.EBX */ 2967 .line_size = 64, 2968 .partitions = 1, 2969 .associativity = 15, 2970 2971 /* CPUID 0x4.0x3.ECX */ 2972 .sets = 65536, 2973 2974 /* CPUID 0x4.0x3.EDX */ 2975 .no_invd_sharing = false, 2976 .inclusive = false, 2977 .complex_indexing = true, 2978 2979 .size = 60 * MiB, 2980 .share_level = CPU_TOPOLOGY_LEVEL_SOCKET, 2981 }, 2982 }; 2983 2984 static const CPUCaches xeon_gnr_cache_info = { 2985 .l1d_cache = &(CPUCacheInfo) { 2986 /* CPUID 0x4.0x0.EAX */ 2987 .type = DATA_CACHE, 2988 .level = 1, 2989 .self_init = true, 2990 2991 /* CPUID 0x4.0x0.EBX */ 2992 .line_size = 64, 2993 .partitions = 1, 2994 .associativity = 12, 2995 2996 /* CPUID 0x4.0x0.ECX */ 2997 .sets = 64, 2998 2999 /* CPUID 0x4.0x0.EDX */ 3000 .no_invd_sharing = false, 3001 .inclusive = false, 3002 .complex_indexing = false, 3003 3004 .size = 48 * KiB, 3005 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 3006 }, 3007 .l1i_cache = &(CPUCacheInfo) { 3008 /* CPUID 0x4.0x1.EAX */ 3009 .type = INSTRUCTION_CACHE, 3010 .level = 1, 3011 .self_init = true, 3012 3013 /* CPUID 0x4.0x1.EBX */ 3014 .line_size = 64, 3015 .partitions = 1, 3016 .associativity = 16, 3017 3018 /* CPUID 0x4.0x1.ECX */ 3019 .sets = 64, 3020 3021 /* CPUID 0x4.0x1.EDX */ 3022 .no_invd_sharing = false, 3023 .inclusive = false, 3024 .complex_indexing = false, 3025 3026 .size = 64 * KiB, 3027 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 3028 }, 3029 .l2_cache = &(CPUCacheInfo) { 3030 /* CPUID 0x4.0x2.EAX */ 3031 .type = UNIFIED_CACHE, 3032 .level = 2, 3033 .self_init = true, 3034 3035 /* CPUID 0x4.0x2.EBX */ 3036 .line_size = 64, 3037 .partitions = 1, 3038 .associativity = 16, 3039 3040 /* CPUID 0x4.0x2.ECX */ 3041 .sets = 2048, 3042 3043 /* CPUID 0x4.0x2.EDX */ 3044 .no_invd_sharing = false, 3045 .inclusive = false, 3046 .complex_indexing = false, 3047 3048 .size = 2 * MiB, 3049 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 3050 }, 3051 .l3_cache = &(CPUCacheInfo) { 3052 /* CPUID 0x4.0x3.EAX */ 3053 .type = UNIFIED_CACHE, 3054 .level = 3, 3055 .self_init = true, 3056 3057 /* CPUID 0x4.0x3.EBX */ 3058 .line_size = 64, 3059 .partitions = 1, 3060 .associativity = 16, 3061 3062 /* CPUID 0x4.0x3.ECX */ 3063 .sets = 294912, 3064 3065 /* CPUID 0x4.0x3.EDX */ 3066 .no_invd_sharing = false, 3067 .inclusive = false, 3068 .complex_indexing = true, 3069 3070 .size = 288 * MiB, 3071 .share_level = CPU_TOPOLOGY_LEVEL_SOCKET, 3072 }, 3073 }; 3074 3075 static const CPUCaches xeon_srf_cache_info = { 3076 .l1d_cache = &(CPUCacheInfo) { 3077 /* CPUID 0x4.0x0.EAX */ 3078 .type = DATA_CACHE, 3079 .level = 1, 3080 .self_init = true, 3081 3082 /* CPUID 0x4.0x0.EBX */ 3083 .line_size = 64, 3084 .partitions = 1, 3085 .associativity = 8, 3086 3087 /* CPUID 0x4.0x0.ECX */ 3088 .sets = 64, 3089 3090 /* CPUID 0x4.0x0.EDX */ 3091 .no_invd_sharing = false, 3092 .inclusive = false, 3093 .complex_indexing = false, 3094 3095 .size = 32 * KiB, 3096 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 3097 }, 3098 .l1i_cache = &(CPUCacheInfo) { 3099 /* CPUID 0x4.0x1.EAX */ 3100 .type = INSTRUCTION_CACHE, 3101 .level = 1, 3102 .self_init = true, 3103 3104 /* CPUID 0x4.0x1.EBX */ 3105 .line_size = 64, 3106 .partitions = 1, 3107 .associativity = 8, 3108 3109 /* CPUID 0x4.0x1.ECX */ 3110 .sets = 128, 3111 3112 /* CPUID 0x4.0x1.EDX */ 3113 .no_invd_sharing = false, 3114 .inclusive = false, 3115 .complex_indexing = false, 3116 3117 .size = 64 * KiB, 3118 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 3119 }, 3120 .l2_cache = &(CPUCacheInfo) { 3121 /* CPUID 0x4.0x2.EAX */ 3122 .type = UNIFIED_CACHE, 3123 .level = 2, 3124 .self_init = true, 3125 3126 /* CPUID 0x4.0x2.EBX */ 3127 .line_size = 64, 3128 .partitions = 1, 3129 .associativity = 16, 3130 3131 /* CPUID 0x4.0x2.ECX */ 3132 .sets = 4096, 3133 3134 /* CPUID 0x4.0x2.EDX */ 3135 .no_invd_sharing = false, 3136 .inclusive = false, 3137 .complex_indexing = false, 3138 3139 .size = 4 * MiB, 3140 .share_level = CPU_TOPOLOGY_LEVEL_MODULE, 3141 }, 3142 .l3_cache = &(CPUCacheInfo) { 3143 /* CPUID 0x4.0x3.EAX */ 3144 .type = UNIFIED_CACHE, 3145 .level = 3, 3146 .self_init = true, 3147 3148 /* CPUID 0x4.0x3.EBX */ 3149 .line_size = 64, 3150 .partitions = 1, 3151 .associativity = 12, 3152 3153 /* CPUID 0x4.0x3.ECX */ 3154 .sets = 147456, 3155 3156 /* CPUID 0x4.0x3.EDX */ 3157 .no_invd_sharing = false, 3158 .inclusive = false, 3159 .complex_indexing = true, 3160 3161 .size = 108 * MiB, 3162 .share_level = CPU_TOPOLOGY_LEVEL_SOCKET, 3163 }, 3164 }; 3165 3166 static const CPUCaches yongfeng_cache_info = { 3167 .l1d_cache = &(CPUCacheInfo) { 3168 /* CPUID 0x4.0x0.EAX */ 3169 .type = DATA_CACHE, 3170 .level = 1, 3171 .self_init = true, 3172 3173 /* CPUID 0x4.0x0.EBX */ 3174 .line_size = 64, 3175 .partitions = 1, 3176 .associativity = 8, 3177 3178 /* CPUID 0x4.0x0.ECX */ 3179 .sets = 64, 3180 3181 /* CPUID 0x4.0x0.EDX */ 3182 .no_invd_sharing = false, 3183 .inclusive = false, 3184 .complex_indexing = false, 3185 3186 /* CPUID 0x80000005.ECX */ 3187 .lines_per_tag = 1, 3188 .size = 32 * KiB, 3189 3190 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 3191 }, 3192 .l1i_cache = &(CPUCacheInfo) { 3193 /* CPUID 0x4.0x1.EAX */ 3194 .type = INSTRUCTION_CACHE, 3195 .level = 1, 3196 .self_init = true, 3197 3198 /* CPUID 0x4.0x1.EBX */ 3199 .line_size = 64, 3200 .partitions = 1, 3201 .associativity = 16, 3202 3203 /* CPUID 0x4.0x1.ECX */ 3204 .sets = 64, 3205 3206 /* CPUID 0x4.0x1.EDX */ 3207 .no_invd_sharing = false, 3208 .inclusive = false, 3209 .complex_indexing = false, 3210 3211 /* CPUID 0x80000005.EDX */ 3212 .lines_per_tag = 1, 3213 .size = 64 * KiB, 3214 3215 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 3216 }, 3217 .l2_cache = &(CPUCacheInfo) { 3218 /* CPUID 0x4.0x2.EAX */ 3219 .type = UNIFIED_CACHE, 3220 .level = 2, 3221 .self_init = true, 3222 3223 /* CPUID 0x4.0x2.EBX */ 3224 .line_size = 64, 3225 .partitions = 1, 3226 .associativity = 8, 3227 3228 /* CPUID 0x4.0x2.ECX */ 3229 .sets = 512, 3230 3231 /* CPUID 0x4.0x2.EDX */ 3232 .no_invd_sharing = false, 3233 .inclusive = true, 3234 .complex_indexing = false, 3235 3236 /* CPUID 0x80000006.ECX */ 3237 .size = 256 * KiB, 3238 3239 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 3240 }, 3241 .l3_cache = &(CPUCacheInfo) { 3242 /* CPUID 0x4.0x3.EAX */ 3243 .type = UNIFIED_CACHE, 3244 .level = 3, 3245 .self_init = true, 3246 3247 /* CPUID 0x4.0x3.EBX */ 3248 .line_size = 64, 3249 .partitions = 1, 3250 .associativity = 16, 3251 3252 /* CPUID 0x4.0x3.ECX */ 3253 .sets = 8192, 3254 3255 /* CPUID 0x4.0x3.EDX */ 3256 .no_invd_sharing = true, 3257 .inclusive = true, 3258 .complex_indexing = false, 3259 3260 .size = 8 * MiB, 3261 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 3262 }, 3263 }; 3264 3265 /* The following VMX features are not supported by KVM and are left out in the 3266 * CPU definitions: 3267 * 3268 * Dual-monitor support (all processors) 3269 * Entry to SMM 3270 * Deactivate dual-monitor treatment 3271 * Number of CR3-target values 3272 * Shutdown activity state 3273 * Wait-for-SIPI activity state 3274 * PAUSE-loop exiting (Westmere and newer) 3275 * EPT-violation #VE (Broadwell and newer) 3276 * Inject event with insn length=0 (Skylake and newer) 3277 * Conceal non-root operation from PT 3278 * Conceal VM exits from PT 3279 * Conceal VM entries from PT 3280 * Enable ENCLS exiting 3281 * Mode-based execute control (XS/XU) 3282 * TSC scaling (Skylake Server and newer) 3283 * GPA translation for PT (IceLake and newer) 3284 * User wait and pause 3285 * ENCLV exiting 3286 * Load IA32_RTIT_CTL 3287 * Clear IA32_RTIT_CTL 3288 * Advanced VM-exit information for EPT violations 3289 * Sub-page write permissions 3290 * PT in VMX operation 3291 */ 3292 3293 static const X86CPUDefinition builtin_x86_defs[] = { 3294 { 3295 .name = "qemu64", 3296 .level = 0xd, 3297 .vendor = CPUID_VENDOR_AMD, 3298 .family = 15, 3299 .model = 107, 3300 .stepping = 1, 3301 .features[FEAT_1_EDX] = 3302 PPRO_FEATURES | 3303 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 3304 CPUID_PSE36, 3305 .features[FEAT_1_ECX] = 3306 CPUID_EXT_SSE3 | CPUID_EXT_CX16, 3307 .features[FEAT_8000_0001_EDX] = 3308 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 3309 .features[FEAT_8000_0001_ECX] = 3310 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM, 3311 .xlevel = 0x8000000A, 3312 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 3313 }, 3314 { 3315 .name = "phenom", 3316 .level = 5, 3317 .vendor = CPUID_VENDOR_AMD, 3318 .family = 16, 3319 .model = 2, 3320 .stepping = 3, 3321 /* Missing: CPUID_HT */ 3322 .features[FEAT_1_EDX] = 3323 PPRO_FEATURES | 3324 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 3325 CPUID_PSE36 | CPUID_VME, 3326 .features[FEAT_1_ECX] = 3327 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 | 3328 CPUID_EXT_POPCNT, 3329 .features[FEAT_8000_0001_EDX] = 3330 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | 3331 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT | 3332 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP, 3333 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, 3334 CPUID_EXT3_CR8LEG, 3335 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, 3336 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */ 3337 .features[FEAT_8000_0001_ECX] = 3338 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | 3339 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A, 3340 /* Missing: CPUID_SVM_LBRV */ 3341 .features[FEAT_SVM] = 3342 CPUID_SVM_NPT, 3343 .xlevel = 0x8000001A, 3344 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor" 3345 }, 3346 { 3347 .name = "core2duo", 3348 .level = 10, 3349 .vendor = CPUID_VENDOR_INTEL, 3350 .family = 6, 3351 .model = 15, 3352 .stepping = 11, 3353 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 3354 .features[FEAT_1_EDX] = 3355 PPRO_FEATURES | 3356 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 3357 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS, 3358 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST, 3359 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */ 3360 .features[FEAT_1_ECX] = 3361 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | 3362 CPUID_EXT_CX16, 3363 .features[FEAT_8000_0001_EDX] = 3364 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 3365 .features[FEAT_8000_0001_ECX] = 3366 CPUID_EXT3_LAHF_LM, 3367 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 3368 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 3369 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 3370 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 3371 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3372 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 3373 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3374 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3375 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3376 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3377 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3378 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3379 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3380 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3381 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3382 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3383 .features[FEAT_VMX_SECONDARY_CTLS] = 3384 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES, 3385 .xlevel = 0x80000008, 3386 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz", 3387 }, 3388 { 3389 .name = "kvm64", 3390 .level = 0xd, 3391 .vendor = CPUID_VENDOR_INTEL, 3392 .family = 15, 3393 .model = 6, 3394 .stepping = 1, 3395 /* Missing: CPUID_HT */ 3396 .features[FEAT_1_EDX] = 3397 PPRO_FEATURES | CPUID_VME | 3398 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 3399 CPUID_PSE36, 3400 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */ 3401 .features[FEAT_1_ECX] = 3402 CPUID_EXT_SSE3 | CPUID_EXT_CX16, 3403 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */ 3404 .features[FEAT_8000_0001_EDX] = 3405 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 3406 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, 3407 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A, 3408 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, 3409 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */ 3410 .features[FEAT_8000_0001_ECX] = 3411 0, 3412 /* VMX features from Cedar Mill/Prescott */ 3413 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 3414 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 3415 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 3416 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3417 VMX_PIN_BASED_NMI_EXITING, 3418 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3419 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3420 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3421 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3422 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3423 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3424 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3425 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING, 3426 .xlevel = 0x80000008, 3427 .model_id = "Common KVM processor" 3428 }, 3429 { 3430 .name = "qemu32", 3431 .level = 4, 3432 .vendor = CPUID_VENDOR_INTEL, 3433 .family = 6, 3434 .model = 6, 3435 .stepping = 3, 3436 .features[FEAT_1_EDX] = 3437 PPRO_FEATURES, 3438 .features[FEAT_1_ECX] = 3439 CPUID_EXT_SSE3, 3440 .xlevel = 0x80000004, 3441 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 3442 }, 3443 { 3444 .name = "kvm32", 3445 .level = 5, 3446 .vendor = CPUID_VENDOR_INTEL, 3447 .family = 15, 3448 .model = 6, 3449 .stepping = 1, 3450 .features[FEAT_1_EDX] = 3451 PPRO_FEATURES | CPUID_VME | 3452 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36, 3453 .features[FEAT_1_ECX] = 3454 CPUID_EXT_SSE3, 3455 .features[FEAT_8000_0001_ECX] = 3456 0, 3457 /* VMX features from Yonah */ 3458 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 3459 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 3460 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 3461 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3462 VMX_PIN_BASED_NMI_EXITING, 3463 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3464 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3465 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3466 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3467 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 3468 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 3469 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS, 3470 .xlevel = 0x80000008, 3471 .model_id = "Common 32-bit KVM processor" 3472 }, 3473 { 3474 .name = "coreduo", 3475 .level = 10, 3476 .vendor = CPUID_VENDOR_INTEL, 3477 .family = 6, 3478 .model = 14, 3479 .stepping = 8, 3480 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 3481 .features[FEAT_1_EDX] = 3482 PPRO_FEATURES | CPUID_VME | 3483 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI | 3484 CPUID_SS, 3485 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR, 3486 * CPUID_EXT_PDCM, CPUID_EXT_VMX */ 3487 .features[FEAT_1_ECX] = 3488 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR, 3489 .features[FEAT_8000_0001_EDX] = 3490 CPUID_EXT2_NX, 3491 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 3492 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 3493 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 3494 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3495 VMX_PIN_BASED_NMI_EXITING, 3496 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3497 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3498 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3499 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3500 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 3501 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 3502 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS, 3503 .xlevel = 0x80000008, 3504 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz", 3505 }, 3506 { 3507 .name = "486", 3508 .level = 1, 3509 .vendor = CPUID_VENDOR_INTEL, 3510 .family = 4, 3511 .model = 8, 3512 .stepping = 0, 3513 .features[FEAT_1_EDX] = 3514 I486_FEATURES, 3515 .xlevel = 0, 3516 .model_id = "", 3517 .cache_info = &legacy_intel_cpuid2_cache_info, 3518 }, 3519 { 3520 .name = "pentium", 3521 .level = 1, 3522 .vendor = CPUID_VENDOR_INTEL, 3523 .family = 5, 3524 .model = 4, 3525 .stepping = 3, 3526 .features[FEAT_1_EDX] = 3527 PENTIUM_FEATURES, 3528 .xlevel = 0, 3529 .model_id = "", 3530 .cache_info = &legacy_intel_cpuid2_cache_info, 3531 }, 3532 { 3533 .name = "pentium2", 3534 .level = 2, 3535 .vendor = CPUID_VENDOR_INTEL, 3536 .family = 6, 3537 .model = 5, 3538 .stepping = 2, 3539 .features[FEAT_1_EDX] = 3540 PENTIUM2_FEATURES, 3541 .xlevel = 0, 3542 .model_id = "", 3543 .cache_info = &legacy_intel_cpuid2_cache_info, 3544 }, 3545 { 3546 .name = "pentium3", 3547 .level = 3, 3548 .vendor = CPUID_VENDOR_INTEL, 3549 .family = 6, 3550 .model = 7, 3551 .stepping = 3, 3552 .features[FEAT_1_EDX] = 3553 PENTIUM3_FEATURES, 3554 .xlevel = 0, 3555 .model_id = "", 3556 .cache_info = &legacy_intel_cpuid2_cache_info, 3557 }, 3558 { 3559 .name = "athlon", 3560 .level = 2, 3561 .vendor = CPUID_VENDOR_AMD, 3562 .family = 6, 3563 .model = 2, 3564 .stepping = 3, 3565 .features[FEAT_1_EDX] = 3566 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR | 3567 CPUID_MCA, 3568 .features[FEAT_8000_0001_EDX] = 3569 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT, 3570 .xlevel = 0x80000008, 3571 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 3572 }, 3573 { 3574 .name = "n270", 3575 .level = 10, 3576 .vendor = CPUID_VENDOR_INTEL, 3577 .family = 6, 3578 .model = 28, 3579 .stepping = 2, 3580 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 3581 .features[FEAT_1_EDX] = 3582 PPRO_FEATURES | 3583 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | 3584 CPUID_ACPI | CPUID_SS, 3585 /* Some CPUs got no CPUID_SEP */ 3586 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2, 3587 * CPUID_EXT_XTPR */ 3588 .features[FEAT_1_ECX] = 3589 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | 3590 CPUID_EXT_MOVBE, 3591 .features[FEAT_8000_0001_EDX] = 3592 CPUID_EXT2_NX, 3593 .features[FEAT_8000_0001_ECX] = 3594 CPUID_EXT3_LAHF_LM, 3595 .xlevel = 0x80000008, 3596 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz", 3597 }, 3598 { 3599 .name = "Conroe", 3600 .level = 10, 3601 .vendor = CPUID_VENDOR_INTEL, 3602 .family = 6, 3603 .model = 15, 3604 .stepping = 3, 3605 .features[FEAT_1_EDX] = 3606 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3607 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3608 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3609 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3610 CPUID_DE | CPUID_FP87, 3611 .features[FEAT_1_ECX] = 3612 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, 3613 .features[FEAT_8000_0001_EDX] = 3614 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3615 .features[FEAT_8000_0001_ECX] = 3616 CPUID_EXT3_LAHF_LM, 3617 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 3618 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 3619 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 3620 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 3621 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3622 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 3623 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3624 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3625 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3626 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3627 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3628 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3629 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3630 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3631 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3632 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3633 .features[FEAT_VMX_SECONDARY_CTLS] = 3634 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES, 3635 .xlevel = 0x80000008, 3636 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)", 3637 }, 3638 { 3639 .name = "Penryn", 3640 .level = 10, 3641 .vendor = CPUID_VENDOR_INTEL, 3642 .family = 6, 3643 .model = 23, 3644 .stepping = 3, 3645 .features[FEAT_1_EDX] = 3646 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3647 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3648 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3649 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3650 CPUID_DE | CPUID_FP87, 3651 .features[FEAT_1_ECX] = 3652 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3653 CPUID_EXT_SSE3, 3654 .features[FEAT_8000_0001_EDX] = 3655 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3656 .features[FEAT_8000_0001_ECX] = 3657 CPUID_EXT3_LAHF_LM, 3658 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 3659 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3660 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, 3661 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT | 3662 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL, 3663 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 3664 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3665 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 3666 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3667 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3668 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3669 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3670 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3671 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3672 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3673 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3674 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3675 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3676 .features[FEAT_VMX_SECONDARY_CTLS] = 3677 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3678 VMX_SECONDARY_EXEC_WBINVD_EXITING, 3679 .xlevel = 0x80000008, 3680 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)", 3681 }, 3682 { 3683 .name = "Nehalem", 3684 .level = 11, 3685 .vendor = CPUID_VENDOR_INTEL, 3686 .family = 6, 3687 .model = 26, 3688 .stepping = 3, 3689 .features[FEAT_1_EDX] = 3690 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3691 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3692 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3693 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3694 CPUID_DE | CPUID_FP87, 3695 .features[FEAT_1_ECX] = 3696 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 3697 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, 3698 .features[FEAT_8000_0001_EDX] = 3699 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 3700 .features[FEAT_8000_0001_ECX] = 3701 CPUID_EXT3_LAHF_LM, 3702 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3703 MSR_VMX_BASIC_TRUE_CTLS, 3704 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3705 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3706 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3707 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3708 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3709 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3710 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3711 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3712 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3713 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 3714 .features[FEAT_VMX_EXIT_CTLS] = 3715 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3716 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3717 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3718 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3719 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3720 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 3721 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3722 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3723 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 3724 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3725 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3726 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3727 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3728 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3729 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3730 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3731 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3732 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3733 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3734 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3735 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3736 .features[FEAT_VMX_SECONDARY_CTLS] = 3737 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3738 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3739 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3740 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3741 VMX_SECONDARY_EXEC_ENABLE_VPID, 3742 .xlevel = 0x80000008, 3743 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)", 3744 .versions = (X86CPUVersionDefinition[]) { 3745 { .version = 1 }, 3746 { 3747 .version = 2, 3748 .alias = "Nehalem-IBRS", 3749 .props = (PropValue[]) { 3750 { "spec-ctrl", "on" }, 3751 { "model-id", 3752 "Intel Core i7 9xx (Nehalem Core i7, IBRS update)" }, 3753 { /* end of list */ } 3754 } 3755 }, 3756 { /* end of list */ } 3757 } 3758 }, 3759 { 3760 .name = "Westmere", 3761 .level = 11, 3762 .vendor = CPUID_VENDOR_INTEL, 3763 .family = 6, 3764 .model = 44, 3765 .stepping = 1, 3766 .features[FEAT_1_EDX] = 3767 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3768 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3769 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3770 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3771 CPUID_DE | CPUID_FP87, 3772 .features[FEAT_1_ECX] = 3773 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | 3774 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3775 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 3776 .features[FEAT_8000_0001_EDX] = 3777 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 3778 .features[FEAT_8000_0001_ECX] = 3779 CPUID_EXT3_LAHF_LM, 3780 .features[FEAT_6_EAX] = 3781 CPUID_6_EAX_ARAT, 3782 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3783 MSR_VMX_BASIC_TRUE_CTLS, 3784 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3785 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3786 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3787 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3788 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3789 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3790 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3791 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3792 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3793 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 3794 .features[FEAT_VMX_EXIT_CTLS] = 3795 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3796 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3797 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3798 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3799 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3800 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3801 MSR_VMX_MISC_STORE_LMA, 3802 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3803 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3804 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 3805 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3806 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3807 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3808 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3809 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3810 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3811 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3812 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3813 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3814 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3815 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3816 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3817 .features[FEAT_VMX_SECONDARY_CTLS] = 3818 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3819 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3820 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3821 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3822 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST, 3823 .xlevel = 0x80000008, 3824 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)", 3825 .versions = (X86CPUVersionDefinition[]) { 3826 { .version = 1 }, 3827 { 3828 .version = 2, 3829 .alias = "Westmere-IBRS", 3830 .props = (PropValue[]) { 3831 { "spec-ctrl", "on" }, 3832 { "model-id", 3833 "Westmere E56xx/L56xx/X56xx (IBRS update)" }, 3834 { /* end of list */ } 3835 } 3836 }, 3837 { /* end of list */ } 3838 } 3839 }, 3840 { 3841 .name = "SandyBridge", 3842 .level = 0xd, 3843 .vendor = CPUID_VENDOR_INTEL, 3844 .family = 6, 3845 .model = 42, 3846 .stepping = 1, 3847 .features[FEAT_1_EDX] = 3848 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3849 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3850 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3851 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3852 CPUID_DE | CPUID_FP87, 3853 .features[FEAT_1_ECX] = 3854 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3855 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | 3856 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 3857 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 3858 CPUID_EXT_SSE3, 3859 .features[FEAT_8000_0001_EDX] = 3860 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3861 CPUID_EXT2_SYSCALL, 3862 .features[FEAT_8000_0001_ECX] = 3863 CPUID_EXT3_LAHF_LM, 3864 .features[FEAT_XSAVE] = 3865 CPUID_XSAVE_XSAVEOPT, 3866 .features[FEAT_6_EAX] = 3867 CPUID_6_EAX_ARAT, 3868 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3869 MSR_VMX_BASIC_TRUE_CTLS, 3870 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3871 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3872 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3873 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3874 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3875 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3876 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3877 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3878 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3879 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 3880 .features[FEAT_VMX_EXIT_CTLS] = 3881 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3882 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3883 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3884 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3885 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3886 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3887 MSR_VMX_MISC_STORE_LMA, 3888 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3889 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3890 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 3891 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3892 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3893 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3894 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3895 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3896 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3897 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3898 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3899 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3900 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3901 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3902 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3903 .features[FEAT_VMX_SECONDARY_CTLS] = 3904 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3905 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3906 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3907 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3908 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST, 3909 .xlevel = 0x80000008, 3910 .model_id = "Intel Xeon E312xx (Sandy Bridge)", 3911 .versions = (X86CPUVersionDefinition[]) { 3912 { .version = 1 }, 3913 { 3914 .version = 2, 3915 .alias = "SandyBridge-IBRS", 3916 .props = (PropValue[]) { 3917 { "spec-ctrl", "on" }, 3918 { "model-id", 3919 "Intel Xeon E312xx (Sandy Bridge, IBRS update)" }, 3920 { /* end of list */ } 3921 } 3922 }, 3923 { /* end of list */ } 3924 } 3925 }, 3926 { 3927 .name = "IvyBridge", 3928 .level = 0xd, 3929 .vendor = CPUID_VENDOR_INTEL, 3930 .family = 6, 3931 .model = 58, 3932 .stepping = 9, 3933 .features[FEAT_1_EDX] = 3934 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3935 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3936 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3937 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3938 CPUID_DE | CPUID_FP87, 3939 .features[FEAT_1_ECX] = 3940 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3941 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | 3942 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 3943 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 3944 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3945 .features[FEAT_7_0_EBX] = 3946 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | 3947 CPUID_7_0_EBX_ERMS, 3948 .features[FEAT_8000_0001_EDX] = 3949 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3950 CPUID_EXT2_SYSCALL, 3951 .features[FEAT_8000_0001_ECX] = 3952 CPUID_EXT3_LAHF_LM, 3953 .features[FEAT_XSAVE] = 3954 CPUID_XSAVE_XSAVEOPT, 3955 .features[FEAT_6_EAX] = 3956 CPUID_6_EAX_ARAT, 3957 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3958 MSR_VMX_BASIC_TRUE_CTLS, 3959 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3960 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3961 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3962 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3963 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3964 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3965 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3966 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3967 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3968 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 3969 .features[FEAT_VMX_EXIT_CTLS] = 3970 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3971 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3972 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3973 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3974 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3975 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3976 MSR_VMX_MISC_STORE_LMA, 3977 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3978 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3979 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3980 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3981 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3982 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3983 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3984 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3985 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3986 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3987 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3988 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3989 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3990 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3991 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3992 .features[FEAT_VMX_SECONDARY_CTLS] = 3993 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3994 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3995 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3996 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3997 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3998 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3999 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4000 VMX_SECONDARY_EXEC_RDRAND_EXITING, 4001 .xlevel = 0x80000008, 4002 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)", 4003 .versions = (X86CPUVersionDefinition[]) { 4004 { .version = 1 }, 4005 { 4006 .version = 2, 4007 .alias = "IvyBridge-IBRS", 4008 .props = (PropValue[]) { 4009 { "spec-ctrl", "on" }, 4010 { "model-id", 4011 "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)" }, 4012 { /* end of list */ } 4013 } 4014 }, 4015 { /* end of list */ } 4016 } 4017 }, 4018 { 4019 .name = "Haswell", 4020 .level = 0xd, 4021 .vendor = CPUID_VENDOR_INTEL, 4022 .family = 6, 4023 .model = 60, 4024 .stepping = 4, 4025 .features[FEAT_1_EDX] = 4026 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4027 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4028 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4029 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4030 CPUID_DE | CPUID_FP87, 4031 .features[FEAT_1_ECX] = 4032 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 4033 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 4034 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 4035 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 4036 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 4037 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4038 .features[FEAT_8000_0001_EDX] = 4039 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 4040 CPUID_EXT2_SYSCALL, 4041 .features[FEAT_8000_0001_ECX] = 4042 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM, 4043 .features[FEAT_7_0_EBX] = 4044 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 4045 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 4046 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 4047 CPUID_7_0_EBX_RTM, 4048 .features[FEAT_XSAVE] = 4049 CPUID_XSAVE_XSAVEOPT, 4050 .features[FEAT_6_EAX] = 4051 CPUID_6_EAX_ARAT, 4052 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 4053 MSR_VMX_BASIC_TRUE_CTLS, 4054 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 4055 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 4056 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 4057 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 4058 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 4059 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 4060 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4061 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4062 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4063 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 4064 .features[FEAT_VMX_EXIT_CTLS] = 4065 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4066 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4067 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 4068 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4069 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4070 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 4071 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 4072 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 4073 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 4074 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 4075 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4076 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4077 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4078 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4079 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4080 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 4081 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 4082 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 4083 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 4084 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4085 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4086 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4087 .features[FEAT_VMX_SECONDARY_CTLS] = 4088 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4089 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 4090 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 4091 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4092 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4093 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4094 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4095 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4096 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS, 4097 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 4098 .xlevel = 0x80000008, 4099 .model_id = "Intel Core Processor (Haswell)", 4100 .versions = (X86CPUVersionDefinition[]) { 4101 { .version = 1 }, 4102 { 4103 .version = 2, 4104 .alias = "Haswell-noTSX", 4105 .props = (PropValue[]) { 4106 { "hle", "off" }, 4107 { "rtm", "off" }, 4108 { "stepping", "1" }, 4109 { "model-id", "Intel Core Processor (Haswell, no TSX)", }, 4110 { /* end of list */ } 4111 }, 4112 }, 4113 { 4114 .version = 3, 4115 .alias = "Haswell-IBRS", 4116 .props = (PropValue[]) { 4117 /* Restore TSX features removed by -v2 above */ 4118 { "hle", "on" }, 4119 { "rtm", "on" }, 4120 /* 4121 * Haswell and Haswell-IBRS had stepping=4 in 4122 * QEMU 4.0 and older 4123 */ 4124 { "stepping", "4" }, 4125 { "spec-ctrl", "on" }, 4126 { "model-id", 4127 "Intel Core Processor (Haswell, IBRS)" }, 4128 { /* end of list */ } 4129 } 4130 }, 4131 { 4132 .version = 4, 4133 .alias = "Haswell-noTSX-IBRS", 4134 .props = (PropValue[]) { 4135 { "hle", "off" }, 4136 { "rtm", "off" }, 4137 /* spec-ctrl was already enabled by -v3 above */ 4138 { "stepping", "1" }, 4139 { "model-id", 4140 "Intel Core Processor (Haswell, no TSX, IBRS)" }, 4141 { /* end of list */ } 4142 } 4143 }, 4144 { /* end of list */ } 4145 } 4146 }, 4147 { 4148 .name = "Broadwell", 4149 .level = 0xd, 4150 .vendor = CPUID_VENDOR_INTEL, 4151 .family = 6, 4152 .model = 61, 4153 .stepping = 2, 4154 .features[FEAT_1_EDX] = 4155 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4156 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4157 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4158 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4159 CPUID_DE | CPUID_FP87, 4160 .features[FEAT_1_ECX] = 4161 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 4162 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 4163 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 4164 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 4165 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 4166 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4167 .features[FEAT_8000_0001_EDX] = 4168 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 4169 CPUID_EXT2_SYSCALL, 4170 .features[FEAT_8000_0001_ECX] = 4171 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 4172 .features[FEAT_7_0_EBX] = 4173 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 4174 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 4175 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 4176 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 4177 CPUID_7_0_EBX_SMAP, 4178 .features[FEAT_XSAVE] = 4179 CPUID_XSAVE_XSAVEOPT, 4180 .features[FEAT_6_EAX] = 4181 CPUID_6_EAX_ARAT, 4182 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 4183 MSR_VMX_BASIC_TRUE_CTLS, 4184 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 4185 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 4186 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 4187 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 4188 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 4189 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 4190 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4191 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4192 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4193 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 4194 .features[FEAT_VMX_EXIT_CTLS] = 4195 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4196 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4197 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 4198 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4199 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4200 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 4201 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 4202 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 4203 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 4204 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 4205 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4206 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4207 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4208 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4209 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4210 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 4211 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 4212 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 4213 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 4214 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4215 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4216 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4217 .features[FEAT_VMX_SECONDARY_CTLS] = 4218 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4219 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 4220 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 4221 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4222 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4223 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4224 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4225 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4226 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4227 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 4228 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 4229 .xlevel = 0x80000008, 4230 .model_id = "Intel Core Processor (Broadwell)", 4231 .versions = (X86CPUVersionDefinition[]) { 4232 { .version = 1 }, 4233 { 4234 .version = 2, 4235 .alias = "Broadwell-noTSX", 4236 .props = (PropValue[]) { 4237 { "hle", "off" }, 4238 { "rtm", "off" }, 4239 { "model-id", "Intel Core Processor (Broadwell, no TSX)", }, 4240 { /* end of list */ } 4241 }, 4242 }, 4243 { 4244 .version = 3, 4245 .alias = "Broadwell-IBRS", 4246 .props = (PropValue[]) { 4247 /* Restore TSX features removed by -v2 above */ 4248 { "hle", "on" }, 4249 { "rtm", "on" }, 4250 { "spec-ctrl", "on" }, 4251 { "model-id", 4252 "Intel Core Processor (Broadwell, IBRS)" }, 4253 { /* end of list */ } 4254 } 4255 }, 4256 { 4257 .version = 4, 4258 .alias = "Broadwell-noTSX-IBRS", 4259 .props = (PropValue[]) { 4260 { "hle", "off" }, 4261 { "rtm", "off" }, 4262 /* spec-ctrl was already enabled by -v3 above */ 4263 { "model-id", 4264 "Intel Core Processor (Broadwell, no TSX, IBRS)" }, 4265 { /* end of list */ } 4266 } 4267 }, 4268 { /* end of list */ } 4269 } 4270 }, 4271 { 4272 .name = "Skylake-Client", 4273 .level = 0xd, 4274 .vendor = CPUID_VENDOR_INTEL, 4275 .family = 6, 4276 .model = 94, 4277 .stepping = 3, 4278 .features[FEAT_1_EDX] = 4279 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4280 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4281 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4282 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4283 CPUID_DE | CPUID_FP87, 4284 .features[FEAT_1_ECX] = 4285 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 4286 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 4287 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 4288 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 4289 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 4290 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4291 .features[FEAT_8000_0001_EDX] = 4292 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 4293 CPUID_EXT2_SYSCALL, 4294 .features[FEAT_8000_0001_ECX] = 4295 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 4296 .features[FEAT_7_0_EBX] = 4297 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 4298 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 4299 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 4300 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 4301 CPUID_7_0_EBX_SMAP, 4302 /* XSAVES is added in version 4 */ 4303 .features[FEAT_XSAVE] = 4304 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4305 CPUID_XSAVE_XGETBV1, 4306 .features[FEAT_6_EAX] = 4307 CPUID_6_EAX_ARAT, 4308 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 4309 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 4310 MSR_VMX_BASIC_TRUE_CTLS, 4311 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 4312 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 4313 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 4314 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 4315 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 4316 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 4317 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4318 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4319 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4320 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 4321 .features[FEAT_VMX_EXIT_CTLS] = 4322 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4323 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4324 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 4325 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4326 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4327 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 4328 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 4329 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 4330 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 4331 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 4332 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4333 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4334 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4335 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4336 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4337 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 4338 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 4339 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 4340 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 4341 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4342 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4343 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4344 .features[FEAT_VMX_SECONDARY_CTLS] = 4345 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4346 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 4347 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 4348 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4349 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4350 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4351 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 4352 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 4353 .xlevel = 0x80000008, 4354 .model_id = "Intel Core Processor (Skylake)", 4355 .versions = (X86CPUVersionDefinition[]) { 4356 { .version = 1 }, 4357 { 4358 .version = 2, 4359 .alias = "Skylake-Client-IBRS", 4360 .props = (PropValue[]) { 4361 { "spec-ctrl", "on" }, 4362 { "model-id", 4363 "Intel Core Processor (Skylake, IBRS)" }, 4364 { /* end of list */ } 4365 } 4366 }, 4367 { 4368 .version = 3, 4369 .alias = "Skylake-Client-noTSX-IBRS", 4370 .props = (PropValue[]) { 4371 { "hle", "off" }, 4372 { "rtm", "off" }, 4373 { "model-id", 4374 "Intel Core Processor (Skylake, IBRS, no TSX)" }, 4375 { /* end of list */ } 4376 } 4377 }, 4378 { 4379 .version = 4, 4380 .note = "IBRS, XSAVES, no TSX", 4381 .props = (PropValue[]) { 4382 { "xsaves", "on" }, 4383 { "vmx-xsaves", "on" }, 4384 { /* end of list */ } 4385 } 4386 }, 4387 { /* end of list */ } 4388 } 4389 }, 4390 { 4391 .name = "Skylake-Server", 4392 .level = 0xd, 4393 .vendor = CPUID_VENDOR_INTEL, 4394 .family = 6, 4395 .model = 85, 4396 .stepping = 4, 4397 .features[FEAT_1_EDX] = 4398 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4399 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4400 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4401 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4402 CPUID_DE | CPUID_FP87, 4403 .features[FEAT_1_ECX] = 4404 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 4405 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 4406 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 4407 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 4408 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 4409 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4410 .features[FEAT_8000_0001_EDX] = 4411 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 4412 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 4413 .features[FEAT_8000_0001_ECX] = 4414 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 4415 .features[FEAT_7_0_EBX] = 4416 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 4417 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 4418 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 4419 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 4420 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 4421 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 4422 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 4423 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 4424 .features[FEAT_7_0_ECX] = 4425 CPUID_7_0_ECX_PKU, 4426 /* XSAVES is added in version 5 */ 4427 .features[FEAT_XSAVE] = 4428 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4429 CPUID_XSAVE_XGETBV1, 4430 .features[FEAT_6_EAX] = 4431 CPUID_6_EAX_ARAT, 4432 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 4433 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 4434 MSR_VMX_BASIC_TRUE_CTLS, 4435 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 4436 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 4437 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 4438 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 4439 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 4440 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 4441 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4442 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4443 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4444 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 4445 .features[FEAT_VMX_EXIT_CTLS] = 4446 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4447 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4448 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 4449 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4450 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4451 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 4452 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 4453 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 4454 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 4455 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 4456 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4457 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4458 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4459 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4460 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4461 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 4462 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 4463 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 4464 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 4465 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4466 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4467 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4468 .features[FEAT_VMX_SECONDARY_CTLS] = 4469 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4470 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 4471 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 4472 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4473 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4474 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4475 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4476 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4477 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4478 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 4479 .xlevel = 0x80000008, 4480 .model_id = "Intel Xeon Processor (Skylake)", 4481 .versions = (X86CPUVersionDefinition[]) { 4482 { .version = 1 }, 4483 { 4484 .version = 2, 4485 .alias = "Skylake-Server-IBRS", 4486 .props = (PropValue[]) { 4487 /* clflushopt was not added to Skylake-Server-IBRS */ 4488 /* TODO: add -v3 including clflushopt */ 4489 { "clflushopt", "off" }, 4490 { "spec-ctrl", "on" }, 4491 { "model-id", 4492 "Intel Xeon Processor (Skylake, IBRS)" }, 4493 { /* end of list */ } 4494 } 4495 }, 4496 { 4497 .version = 3, 4498 .alias = "Skylake-Server-noTSX-IBRS", 4499 .props = (PropValue[]) { 4500 { "hle", "off" }, 4501 { "rtm", "off" }, 4502 { "model-id", 4503 "Intel Xeon Processor (Skylake, IBRS, no TSX)" }, 4504 { /* end of list */ } 4505 } 4506 }, 4507 { 4508 .version = 4, 4509 .note = "IBRS, EPT switching, no TSX", 4510 .props = (PropValue[]) { 4511 { "vmx-eptp-switching", "on" }, 4512 { /* end of list */ } 4513 } 4514 }, 4515 { 4516 .version = 5, 4517 .note = "IBRS, XSAVES, EPT switching, no TSX", 4518 .props = (PropValue[]) { 4519 { "xsaves", "on" }, 4520 { "vmx-xsaves", "on" }, 4521 { /* end of list */ } 4522 } 4523 }, 4524 { /* end of list */ } 4525 } 4526 }, 4527 { 4528 .name = "Cascadelake-Server", 4529 .level = 0xd, 4530 .vendor = CPUID_VENDOR_INTEL, 4531 .family = 6, 4532 .model = 85, 4533 .stepping = 6, 4534 .features[FEAT_1_EDX] = 4535 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4536 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4537 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4538 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4539 CPUID_DE | CPUID_FP87, 4540 .features[FEAT_1_ECX] = 4541 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 4542 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 4543 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 4544 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 4545 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 4546 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4547 .features[FEAT_8000_0001_EDX] = 4548 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 4549 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 4550 .features[FEAT_8000_0001_ECX] = 4551 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 4552 .features[FEAT_7_0_EBX] = 4553 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 4554 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 4555 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 4556 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 4557 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 4558 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 4559 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 4560 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 4561 .features[FEAT_7_0_ECX] = 4562 CPUID_7_0_ECX_PKU | 4563 CPUID_7_0_ECX_AVX512VNNI, 4564 .features[FEAT_7_0_EDX] = 4565 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4566 /* XSAVES is added in version 5 */ 4567 .features[FEAT_XSAVE] = 4568 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4569 CPUID_XSAVE_XGETBV1, 4570 .features[FEAT_6_EAX] = 4571 CPUID_6_EAX_ARAT, 4572 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 4573 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 4574 MSR_VMX_BASIC_TRUE_CTLS, 4575 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 4576 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 4577 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 4578 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 4579 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 4580 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 4581 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4582 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4583 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4584 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 4585 .features[FEAT_VMX_EXIT_CTLS] = 4586 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4587 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4588 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 4589 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4590 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4591 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 4592 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 4593 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 4594 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 4595 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 4596 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4597 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4598 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4599 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4600 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4601 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 4602 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 4603 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 4604 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 4605 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4606 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4607 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4608 .features[FEAT_VMX_SECONDARY_CTLS] = 4609 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4610 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 4611 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 4612 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4613 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4614 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4615 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4616 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4617 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4618 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 4619 .xlevel = 0x80000008, 4620 .model_id = "Intel Xeon Processor (Cascadelake)", 4621 .versions = (X86CPUVersionDefinition[]) { 4622 { .version = 1 }, 4623 { .version = 2, 4624 .note = "ARCH_CAPABILITIES", 4625 .props = (PropValue[]) { 4626 { "arch-capabilities", "on" }, 4627 { "rdctl-no", "on" }, 4628 { "ibrs-all", "on" }, 4629 { "skip-l1dfl-vmentry", "on" }, 4630 { "mds-no", "on" }, 4631 { /* end of list */ } 4632 }, 4633 }, 4634 { .version = 3, 4635 .alias = "Cascadelake-Server-noTSX", 4636 .note = "ARCH_CAPABILITIES, no TSX", 4637 .props = (PropValue[]) { 4638 { "hle", "off" }, 4639 { "rtm", "off" }, 4640 { /* end of list */ } 4641 }, 4642 }, 4643 { .version = 4, 4644 .note = "ARCH_CAPABILITIES, EPT switching, no TSX", 4645 .props = (PropValue[]) { 4646 { "vmx-eptp-switching", "on" }, 4647 { /* end of list */ } 4648 }, 4649 }, 4650 { .version = 5, 4651 .note = "ARCH_CAPABILITIES, EPT switching, XSAVES, no TSX", 4652 .props = (PropValue[]) { 4653 { "xsaves", "on" }, 4654 { "vmx-xsaves", "on" }, 4655 { /* end of list */ } 4656 }, 4657 }, 4658 { /* end of list */ } 4659 } 4660 }, 4661 { 4662 .name = "Cooperlake", 4663 .level = 0xd, 4664 .vendor = CPUID_VENDOR_INTEL, 4665 .family = 6, 4666 .model = 85, 4667 .stepping = 10, 4668 .features[FEAT_1_EDX] = 4669 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4670 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4671 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4672 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4673 CPUID_DE | CPUID_FP87, 4674 .features[FEAT_1_ECX] = 4675 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 4676 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 4677 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 4678 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 4679 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 4680 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4681 .features[FEAT_8000_0001_EDX] = 4682 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 4683 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 4684 .features[FEAT_8000_0001_ECX] = 4685 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 4686 .features[FEAT_7_0_EBX] = 4687 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 4688 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 4689 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 4690 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 4691 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 4692 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 4693 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 4694 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 4695 .features[FEAT_7_0_ECX] = 4696 CPUID_7_0_ECX_PKU | 4697 CPUID_7_0_ECX_AVX512VNNI, 4698 .features[FEAT_7_0_EDX] = 4699 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_STIBP | 4700 CPUID_7_0_EDX_SPEC_CTRL_SSBD | CPUID_7_0_EDX_ARCH_CAPABILITIES, 4701 .features[FEAT_ARCH_CAPABILITIES] = 4702 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 4703 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 4704 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO, 4705 .features[FEAT_7_1_EAX] = 4706 CPUID_7_1_EAX_AVX512_BF16, 4707 /* XSAVES is added in version 2 */ 4708 .features[FEAT_XSAVE] = 4709 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4710 CPUID_XSAVE_XGETBV1, 4711 .features[FEAT_6_EAX] = 4712 CPUID_6_EAX_ARAT, 4713 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 4714 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 4715 MSR_VMX_BASIC_TRUE_CTLS, 4716 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 4717 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 4718 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 4719 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 4720 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 4721 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 4722 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4723 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4724 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4725 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 4726 .features[FEAT_VMX_EXIT_CTLS] = 4727 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4728 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4729 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 4730 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4731 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4732 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 4733 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 4734 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 4735 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 4736 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 4737 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4738 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4739 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4740 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4741 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4742 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 4743 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 4744 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 4745 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 4746 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4747 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4748 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4749 .features[FEAT_VMX_SECONDARY_CTLS] = 4750 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4751 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 4752 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 4753 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4754 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4755 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4756 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4757 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4758 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4759 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 4760 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 4761 .xlevel = 0x80000008, 4762 .model_id = "Intel Xeon Processor (Cooperlake)", 4763 .versions = (X86CPUVersionDefinition[]) { 4764 { .version = 1 }, 4765 { .version = 2, 4766 .note = "XSAVES", 4767 .props = (PropValue[]) { 4768 { "xsaves", "on" }, 4769 { "vmx-xsaves", "on" }, 4770 { /* end of list */ } 4771 }, 4772 }, 4773 { /* end of list */ } 4774 } 4775 }, 4776 { 4777 .name = "Icelake-Server", 4778 .level = 0xd, 4779 .vendor = CPUID_VENDOR_INTEL, 4780 .family = 6, 4781 .model = 134, 4782 .stepping = 0, 4783 .features[FEAT_1_EDX] = 4784 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4785 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4786 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4787 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4788 CPUID_DE | CPUID_FP87, 4789 .features[FEAT_1_ECX] = 4790 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 4791 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 4792 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 4793 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 4794 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 4795 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4796 .features[FEAT_8000_0001_EDX] = 4797 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 4798 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 4799 .features[FEAT_8000_0001_ECX] = 4800 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 4801 .features[FEAT_8000_0008_EBX] = 4802 CPUID_8000_0008_EBX_WBNOINVD, 4803 .features[FEAT_7_0_EBX] = 4804 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 4805 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 4806 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 4807 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 4808 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 4809 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 4810 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 4811 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 4812 .features[FEAT_7_0_ECX] = 4813 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 4814 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 4815 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4816 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 4817 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57, 4818 .features[FEAT_7_0_EDX] = 4819 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4820 /* XSAVES is added in version 5 */ 4821 .features[FEAT_XSAVE] = 4822 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4823 CPUID_XSAVE_XGETBV1, 4824 .features[FEAT_6_EAX] = 4825 CPUID_6_EAX_ARAT, 4826 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 4827 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 4828 MSR_VMX_BASIC_TRUE_CTLS, 4829 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 4830 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 4831 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 4832 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 4833 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 4834 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 4835 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4836 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4837 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4838 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 4839 .features[FEAT_VMX_EXIT_CTLS] = 4840 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4841 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4842 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 4843 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4844 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4845 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 4846 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 4847 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 4848 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 4849 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 4850 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4851 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4852 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4853 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4854 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4855 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 4856 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 4857 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 4858 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 4859 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4860 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4861 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4862 .features[FEAT_VMX_SECONDARY_CTLS] = 4863 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4864 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 4865 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 4866 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4867 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4868 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4869 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4870 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4871 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS, 4872 .xlevel = 0x80000008, 4873 .model_id = "Intel Xeon Processor (Icelake)", 4874 .versions = (X86CPUVersionDefinition[]) { 4875 { .version = 1 }, 4876 { 4877 .version = 2, 4878 .note = "no TSX", 4879 .alias = "Icelake-Server-noTSX", 4880 .props = (PropValue[]) { 4881 { "hle", "off" }, 4882 { "rtm", "off" }, 4883 { /* end of list */ } 4884 }, 4885 }, 4886 { 4887 .version = 3, 4888 .props = (PropValue[]) { 4889 { "arch-capabilities", "on" }, 4890 { "rdctl-no", "on" }, 4891 { "ibrs-all", "on" }, 4892 { "skip-l1dfl-vmentry", "on" }, 4893 { "mds-no", "on" }, 4894 { "pschange-mc-no", "on" }, 4895 { "taa-no", "on" }, 4896 { /* end of list */ } 4897 }, 4898 }, 4899 { 4900 .version = 4, 4901 .props = (PropValue[]) { 4902 { "sha-ni", "on" }, 4903 { "avx512ifma", "on" }, 4904 { "rdpid", "on" }, 4905 { "fsrm", "on" }, 4906 { "vmx-rdseed-exit", "on" }, 4907 { "vmx-pml", "on" }, 4908 { "vmx-eptp-switching", "on" }, 4909 { "model", "106" }, 4910 { /* end of list */ } 4911 }, 4912 }, 4913 { 4914 .version = 5, 4915 .note = "XSAVES", 4916 .props = (PropValue[]) { 4917 { "xsaves", "on" }, 4918 { "vmx-xsaves", "on" }, 4919 { /* end of list */ } 4920 }, 4921 }, 4922 { 4923 .version = 6, 4924 .note = "5-level EPT", 4925 .props = (PropValue[]) { 4926 { "vmx-page-walk-5", "on" }, 4927 { /* end of list */ } 4928 }, 4929 }, 4930 { 4931 .version = 7, 4932 .note = "TSX, taa-no", 4933 .props = (PropValue[]) { 4934 /* Restore TSX features removed by -v2 above */ 4935 { "hle", "on" }, 4936 { "rtm", "on" }, 4937 { /* end of list */ } 4938 }, 4939 }, 4940 { /* end of list */ } 4941 } 4942 }, 4943 { 4944 .name = "SapphireRapids", 4945 .level = 0x20, 4946 .vendor = CPUID_VENDOR_INTEL, 4947 .family = 6, 4948 .model = 143, 4949 .stepping = 4, 4950 /* 4951 * please keep the ascending order so that we can have a clear view of 4952 * bit position of each feature. 4953 */ 4954 .features[FEAT_1_EDX] = 4955 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4956 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4957 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4958 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4959 CPUID_SSE | CPUID_SSE2, 4960 .features[FEAT_1_ECX] = 4961 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 4962 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 4963 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4964 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 4965 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4966 .features[FEAT_8000_0001_EDX] = 4967 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4968 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4969 .features[FEAT_8000_0001_ECX] = 4970 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 4971 .features[FEAT_8000_0008_EBX] = 4972 CPUID_8000_0008_EBX_WBNOINVD, 4973 .features[FEAT_7_0_EBX] = 4974 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_HLE | 4975 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | 4976 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RTM | 4977 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 4978 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | 4979 CPUID_7_0_EBX_AVX512IFMA | CPUID_7_0_EBX_CLFLUSHOPT | 4980 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | 4981 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, 4982 .features[FEAT_7_0_ECX] = 4983 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 4984 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 4985 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4986 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 4987 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | 4988 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT, 4989 .features[FEAT_7_0_EDX] = 4990 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 4991 CPUID_7_0_EDX_TSX_LDTRK | CPUID_7_0_EDX_AMX_BF16 | 4992 CPUID_7_0_EDX_AVX512_FP16 | CPUID_7_0_EDX_AMX_TILE | 4993 CPUID_7_0_EDX_AMX_INT8 | CPUID_7_0_EDX_SPEC_CTRL | 4994 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4995 .features[FEAT_ARCH_CAPABILITIES] = 4996 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 4997 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 4998 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO, 4999 .features[FEAT_XSAVE] = 5000 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5001 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES | CPUID_D_1_EAX_XFD, 5002 .features[FEAT_6_EAX] = 5003 CPUID_6_EAX_ARAT, 5004 .features[FEAT_7_1_EAX] = 5005 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_AVX512_BF16 | 5006 CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC, 5007 .features[FEAT_VMX_BASIC] = 5008 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 5009 .features[FEAT_VMX_ENTRY_CTLS] = 5010 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 5011 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 5012 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 5013 .features[FEAT_VMX_EPT_VPID_CAPS] = 5014 MSR_VMX_EPT_EXECONLY | 5015 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_PAGE_WALK_LENGTH_5 | 5016 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 5017 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 5018 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 5019 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 5020 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 5021 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 5022 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 5023 .features[FEAT_VMX_EXIT_CTLS] = 5024 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 5025 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 5026 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 5027 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 5028 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 5029 .features[FEAT_VMX_MISC] = 5030 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 5031 MSR_VMX_MISC_VMWRITE_VMEXIT, 5032 .features[FEAT_VMX_PINBASED_CTLS] = 5033 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 5034 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 5035 VMX_PIN_BASED_POSTED_INTR, 5036 .features[FEAT_VMX_PROCBASED_CTLS] = 5037 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 5038 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 5039 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 5040 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 5041 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 5042 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 5043 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 5044 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 5045 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 5046 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 5047 VMX_CPU_BASED_PAUSE_EXITING | 5048 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 5049 .features[FEAT_VMX_SECONDARY_CTLS] = 5050 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 5051 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 5052 VMX_SECONDARY_EXEC_RDTSCP | 5053 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 5054 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 5055 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 5056 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 5057 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 5058 VMX_SECONDARY_EXEC_RDRAND_EXITING | 5059 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 5060 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 5061 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 5062 VMX_SECONDARY_EXEC_XSAVES, 5063 .features[FEAT_VMX_VMFUNC] = 5064 MSR_VMX_VMFUNC_EPT_SWITCHING, 5065 .xlevel = 0x80000008, 5066 .model_id = "Intel Xeon Processor (SapphireRapids)", 5067 .versions = (X86CPUVersionDefinition[]) { 5068 { .version = 1 }, 5069 { 5070 .version = 2, 5071 .props = (PropValue[]) { 5072 { "sbdr-ssdp-no", "on" }, 5073 { "fbsdp-no", "on" }, 5074 { "psdp-no", "on" }, 5075 { /* end of list */ } 5076 } 5077 }, 5078 { 5079 .version = 3, 5080 .props = (PropValue[]) { 5081 { "ss", "on" }, 5082 { "tsc-adjust", "on" }, 5083 { "cldemote", "on" }, 5084 { "movdiri", "on" }, 5085 { "movdir64b", "on" }, 5086 { /* end of list */ } 5087 } 5088 }, 5089 { 5090 .version = 4, 5091 .note = "with spr-sp cache model and 0x1f leaf", 5092 .cache_info = &xeon_spr_cache_info, 5093 .props = (PropValue[]) { 5094 { "x-force-cpuid-0x1f", "on" }, 5095 { /* end of list */ }, 5096 } 5097 }, 5098 { /* end of list */ } 5099 } 5100 }, 5101 { 5102 .name = "GraniteRapids", 5103 .level = 0x20, 5104 .vendor = CPUID_VENDOR_INTEL, 5105 .family = 6, 5106 .model = 173, 5107 .stepping = 0, 5108 /* 5109 * please keep the ascending order so that we can have a clear view of 5110 * bit position of each feature. 5111 */ 5112 .features[FEAT_1_EDX] = 5113 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 5114 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 5115 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 5116 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 5117 CPUID_SSE | CPUID_SSE2, 5118 .features[FEAT_1_ECX] = 5119 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 5120 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 5121 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 5122 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 5123 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 5124 .features[FEAT_8000_0001_EDX] = 5125 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 5126 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 5127 .features[FEAT_8000_0001_ECX] = 5128 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 5129 .features[FEAT_8000_0008_EBX] = 5130 CPUID_8000_0008_EBX_WBNOINVD, 5131 .features[FEAT_7_0_EBX] = 5132 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_HLE | 5133 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | 5134 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RTM | 5135 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 5136 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | 5137 CPUID_7_0_EBX_AVX512IFMA | CPUID_7_0_EBX_CLFLUSHOPT | 5138 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | 5139 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, 5140 .features[FEAT_7_0_ECX] = 5141 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 5142 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 5143 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 5144 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 5145 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | 5146 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT, 5147 .features[FEAT_7_0_EDX] = 5148 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 5149 CPUID_7_0_EDX_TSX_LDTRK | CPUID_7_0_EDX_AMX_BF16 | 5150 CPUID_7_0_EDX_AVX512_FP16 | CPUID_7_0_EDX_AMX_TILE | 5151 CPUID_7_0_EDX_AMX_INT8 | CPUID_7_0_EDX_SPEC_CTRL | 5152 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 5153 .features[FEAT_ARCH_CAPABILITIES] = 5154 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 5155 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 5156 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO | 5157 MSR_ARCH_CAP_SBDR_SSDP_NO | MSR_ARCH_CAP_FBSDP_NO | 5158 MSR_ARCH_CAP_PSDP_NO | MSR_ARCH_CAP_PBRSB_NO, 5159 .features[FEAT_XSAVE] = 5160 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5161 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES | CPUID_D_1_EAX_XFD, 5162 .features[FEAT_6_EAX] = 5163 CPUID_6_EAX_ARAT, 5164 .features[FEAT_7_1_EAX] = 5165 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_AVX512_BF16 | 5166 CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC | 5167 CPUID_7_1_EAX_AMX_FP16, 5168 .features[FEAT_7_1_EDX] = 5169 CPUID_7_1_EDX_PREFETCHITI, 5170 .features[FEAT_7_2_EDX] = 5171 CPUID_7_2_EDX_MCDT_NO, 5172 .features[FEAT_VMX_BASIC] = 5173 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 5174 .features[FEAT_VMX_ENTRY_CTLS] = 5175 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 5176 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 5177 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 5178 .features[FEAT_VMX_EPT_VPID_CAPS] = 5179 MSR_VMX_EPT_EXECONLY | 5180 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_PAGE_WALK_LENGTH_5 | 5181 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 5182 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 5183 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 5184 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 5185 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 5186 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 5187 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 5188 .features[FEAT_VMX_EXIT_CTLS] = 5189 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 5190 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 5191 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 5192 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 5193 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 5194 .features[FEAT_VMX_MISC] = 5195 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 5196 MSR_VMX_MISC_VMWRITE_VMEXIT, 5197 .features[FEAT_VMX_PINBASED_CTLS] = 5198 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 5199 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 5200 VMX_PIN_BASED_POSTED_INTR, 5201 .features[FEAT_VMX_PROCBASED_CTLS] = 5202 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 5203 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 5204 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 5205 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 5206 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 5207 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 5208 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 5209 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 5210 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 5211 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 5212 VMX_CPU_BASED_PAUSE_EXITING | 5213 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 5214 .features[FEAT_VMX_SECONDARY_CTLS] = 5215 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 5216 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 5217 VMX_SECONDARY_EXEC_RDTSCP | 5218 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 5219 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 5220 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 5221 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 5222 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 5223 VMX_SECONDARY_EXEC_RDRAND_EXITING | 5224 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 5225 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 5226 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 5227 VMX_SECONDARY_EXEC_XSAVES, 5228 .features[FEAT_VMX_VMFUNC] = 5229 MSR_VMX_VMFUNC_EPT_SWITCHING, 5230 .xlevel = 0x80000008, 5231 .model_id = "Intel Xeon Processor (GraniteRapids)", 5232 .versions = (X86CPUVersionDefinition[]) { 5233 { .version = 1 }, 5234 { 5235 .version = 2, 5236 .props = (PropValue[]) { 5237 { "ss", "on" }, 5238 { "tsc-adjust", "on" }, 5239 { "cldemote", "on" }, 5240 { "movdiri", "on" }, 5241 { "movdir64b", "on" }, 5242 { "avx10", "on" }, 5243 { "avx10-128", "on" }, 5244 { "avx10-256", "on" }, 5245 { "avx10-512", "on" }, 5246 { "avx10-version", "1" }, 5247 { "stepping", "1" }, 5248 { /* end of list */ } 5249 } 5250 }, 5251 { 5252 .version = 3, 5253 .note = "with gnr-sp cache model and 0x1f leaf", 5254 .cache_info = &xeon_gnr_cache_info, 5255 .props = (PropValue[]) { 5256 { "x-force-cpuid-0x1f", "on" }, 5257 { /* end of list */ }, 5258 } 5259 }, 5260 { /* end of list */ }, 5261 }, 5262 }, 5263 { 5264 .name = "SierraForest", 5265 .level = 0x23, 5266 .vendor = CPUID_VENDOR_INTEL, 5267 .family = 6, 5268 .model = 175, 5269 .stepping = 0, 5270 /* 5271 * please keep the ascending order so that we can have a clear view of 5272 * bit position of each feature. 5273 */ 5274 .features[FEAT_1_EDX] = 5275 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 5276 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 5277 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 5278 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 5279 CPUID_SSE | CPUID_SSE2, 5280 .features[FEAT_1_ECX] = 5281 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 5282 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 5283 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 5284 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 5285 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 5286 .features[FEAT_8000_0001_EDX] = 5287 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 5288 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 5289 .features[FEAT_8000_0001_ECX] = 5290 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 5291 .features[FEAT_8000_0008_EBX] = 5292 CPUID_8000_0008_EBX_WBNOINVD, 5293 .features[FEAT_7_0_EBX] = 5294 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5295 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 5296 CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 5297 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB | 5298 CPUID_7_0_EBX_SHA_NI, 5299 .features[FEAT_7_0_ECX] = 5300 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_GFNI | 5301 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 5302 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT, 5303 .features[FEAT_7_0_EDX] = 5304 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 5305 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES | 5306 CPUID_7_0_EDX_SPEC_CTRL_SSBD, 5307 .features[FEAT_ARCH_CAPABILITIES] = 5308 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 5309 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 5310 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_SBDR_SSDP_NO | 5311 MSR_ARCH_CAP_FBSDP_NO | MSR_ARCH_CAP_PSDP_NO | 5312 MSR_ARCH_CAP_PBRSB_NO, 5313 .features[FEAT_XSAVE] = 5314 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5315 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 5316 .features[FEAT_6_EAX] = 5317 CPUID_6_EAX_ARAT, 5318 .features[FEAT_7_1_EAX] = 5319 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_CMPCCXADD | 5320 CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_AVX_IFMA, 5321 .features[FEAT_7_1_EDX] = 5322 CPUID_7_1_EDX_AVX_VNNI_INT8 | CPUID_7_1_EDX_AVX_NE_CONVERT, 5323 .features[FEAT_7_2_EDX] = 5324 CPUID_7_2_EDX_MCDT_NO, 5325 .features[FEAT_VMX_BASIC] = 5326 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 5327 .features[FEAT_VMX_ENTRY_CTLS] = 5328 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 5329 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 5330 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 5331 .features[FEAT_VMX_EPT_VPID_CAPS] = 5332 MSR_VMX_EPT_EXECONLY | MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | 5333 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 5334 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 5335 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 5336 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 5337 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 5338 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 5339 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 5340 .features[FEAT_VMX_EXIT_CTLS] = 5341 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 5342 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 5343 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 5344 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 5345 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 5346 .features[FEAT_VMX_MISC] = 5347 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 5348 MSR_VMX_MISC_VMWRITE_VMEXIT, 5349 .features[FEAT_VMX_PINBASED_CTLS] = 5350 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 5351 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 5352 VMX_PIN_BASED_POSTED_INTR, 5353 .features[FEAT_VMX_PROCBASED_CTLS] = 5354 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 5355 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 5356 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 5357 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 5358 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 5359 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 5360 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 5361 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 5362 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 5363 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 5364 VMX_CPU_BASED_PAUSE_EXITING | 5365 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 5366 .features[FEAT_VMX_SECONDARY_CTLS] = 5367 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 5368 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 5369 VMX_SECONDARY_EXEC_RDTSCP | 5370 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 5371 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 5372 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 5373 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 5374 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 5375 VMX_SECONDARY_EXEC_RDRAND_EXITING | 5376 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 5377 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 5378 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 5379 VMX_SECONDARY_EXEC_XSAVES, 5380 .features[FEAT_VMX_VMFUNC] = 5381 MSR_VMX_VMFUNC_EPT_SWITCHING, 5382 .xlevel = 0x80000008, 5383 .model_id = "Intel Xeon Processor (SierraForest)", 5384 .versions = (X86CPUVersionDefinition[]) { 5385 { .version = 1 }, 5386 { 5387 .version = 2, 5388 .props = (PropValue[]) { 5389 { "ss", "on" }, 5390 { "tsc-adjust", "on" }, 5391 { "cldemote", "on" }, 5392 { "movdiri", "on" }, 5393 { "movdir64b", "on" }, 5394 { "gds-no", "on" }, 5395 { "rfds-no", "on" }, 5396 { "lam", "on" }, 5397 { "intel-psfd", "on"}, 5398 { "ipred-ctrl", "on"}, 5399 { "rrsba-ctrl", "on"}, 5400 { "bhi-ctrl", "on"}, 5401 { "stepping", "3" }, 5402 { /* end of list */ } 5403 } 5404 }, 5405 { 5406 .version = 3, 5407 .note = "with srf-sp cache model and 0x1f leaf", 5408 .cache_info = &xeon_srf_cache_info, 5409 .props = (PropValue[]) { 5410 { "x-force-cpuid-0x1f", "on" }, 5411 { /* end of list */ }, 5412 } 5413 }, 5414 { /* end of list */ }, 5415 }, 5416 }, 5417 { 5418 .name = "ClearwaterForest", 5419 .level = 0x23, 5420 .xlevel = 0x80000008, 5421 .vendor = CPUID_VENDOR_INTEL, 5422 .family = 6, 5423 .model = 221, 5424 .stepping = 0, 5425 /* 5426 * please keep the ascending order so that we can have a clear view of 5427 * bit position of each feature. 5428 */ 5429 .features[FEAT_1_EDX] = 5430 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 5431 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 5432 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 5433 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 5434 CPUID_SSE | CPUID_SSE2 | CPUID_SS, 5435 .features[FEAT_1_ECX] = 5436 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 5437 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 5438 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 5439 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 5440 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 5441 .features[FEAT_8000_0001_EDX] = 5442 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 5443 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 5444 .features[FEAT_8000_0001_ECX] = 5445 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 5446 .features[FEAT_8000_0008_EBX] = 5447 CPUID_8000_0008_EBX_WBNOINVD, 5448 .features[FEAT_7_0_EBX] = 5449 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_TSC_ADJUST | 5450 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 5451 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 5452 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | 5453 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB | 5454 CPUID_7_0_EBX_SHA_NI, 5455 .features[FEAT_7_0_ECX] = 5456 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_GFNI | 5457 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 5458 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT | 5459 CPUID_7_0_ECX_CLDEMOTE | CPUID_7_0_ECX_MOVDIRI | 5460 CPUID_7_0_ECX_MOVDIR64B, 5461 .features[FEAT_7_0_EDX] = 5462 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 5463 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES | 5464 CPUID_7_0_EDX_SPEC_CTRL_SSBD, 5465 .features[FEAT_ARCH_CAPABILITIES] = 5466 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 5467 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 5468 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_SBDR_SSDP_NO | 5469 MSR_ARCH_CAP_FBSDP_NO | MSR_ARCH_CAP_PSDP_NO | 5470 MSR_ARCH_CAP_BHI_NO | MSR_ARCH_CAP_PBRSB_NO | 5471 MSR_ARCH_CAP_GDS_NO | MSR_ARCH_CAP_RFDS_NO, 5472 .features[FEAT_XSAVE] = 5473 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5474 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 5475 .features[FEAT_6_EAX] = 5476 CPUID_6_EAX_ARAT, 5477 .features[FEAT_7_1_EAX] = 5478 CPUID_7_1_EAX_SHA512 | CPUID_7_1_EAX_SM3 | CPUID_7_1_EAX_SM4 | 5479 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_CMPCCXADD | 5480 CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_AVX_IFMA | 5481 CPUID_7_1_EAX_LAM, 5482 .features[FEAT_7_1_EDX] = 5483 CPUID_7_1_EDX_AVX_VNNI_INT8 | CPUID_7_1_EDX_AVX_NE_CONVERT | 5484 CPUID_7_1_EDX_AVX_VNNI_INT16 | CPUID_7_1_EDX_PREFETCHITI, 5485 .features[FEAT_7_2_EDX] = 5486 CPUID_7_2_EDX_PSFD | CPUID_7_2_EDX_IPRED_CTRL | 5487 CPUID_7_2_EDX_RRSBA_CTRL | CPUID_7_2_EDX_DDPD_U | 5488 CPUID_7_2_EDX_BHI_CTRL | CPUID_7_2_EDX_MCDT_NO, 5489 .features[FEAT_VMX_BASIC] = 5490 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 5491 .features[FEAT_VMX_ENTRY_CTLS] = 5492 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 5493 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 5494 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 5495 .features[FEAT_VMX_EPT_VPID_CAPS] = 5496 MSR_VMX_EPT_EXECONLY | MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | 5497 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 5498 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 5499 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 5500 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 5501 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 5502 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 5503 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 5504 .features[FEAT_VMX_EXIT_CTLS] = 5505 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 5506 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 5507 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 5508 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 5509 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 5510 .features[FEAT_VMX_MISC] = 5511 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 5512 MSR_VMX_MISC_VMWRITE_VMEXIT, 5513 .features[FEAT_VMX_PINBASED_CTLS] = 5514 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 5515 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 5516 VMX_PIN_BASED_POSTED_INTR, 5517 .features[FEAT_VMX_PROCBASED_CTLS] = 5518 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 5519 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 5520 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 5521 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 5522 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 5523 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 5524 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 5525 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 5526 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 5527 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 5528 VMX_CPU_BASED_PAUSE_EXITING | 5529 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 5530 .features[FEAT_VMX_SECONDARY_CTLS] = 5531 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 5532 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 5533 VMX_SECONDARY_EXEC_RDTSCP | 5534 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 5535 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 5536 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 5537 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 5538 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 5539 VMX_SECONDARY_EXEC_RDRAND_EXITING | 5540 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 5541 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 5542 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 5543 VMX_SECONDARY_EXEC_XSAVES, 5544 .features[FEAT_VMX_VMFUNC] = 5545 MSR_VMX_VMFUNC_EPT_SWITCHING, 5546 .model_id = "Intel Xeon Processor (ClearwaterForest)", 5547 .versions = (X86CPUVersionDefinition[]) { 5548 { .version = 1 }, 5549 { /* end of list */ }, 5550 }, 5551 }, 5552 { 5553 .name = "Denverton", 5554 .level = 21, 5555 .vendor = CPUID_VENDOR_INTEL, 5556 .family = 6, 5557 .model = 95, 5558 .stepping = 1, 5559 .features[FEAT_1_EDX] = 5560 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 5561 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 5562 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 5563 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 5564 CPUID_SSE | CPUID_SSE2, 5565 .features[FEAT_1_ECX] = 5566 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR | 5567 CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_SSE41 | 5568 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 5569 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | 5570 CPUID_EXT_AES | CPUID_EXT_XSAVE | CPUID_EXT_RDRAND, 5571 .features[FEAT_8000_0001_EDX] = 5572 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 5573 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 5574 .features[FEAT_8000_0001_ECX] = 5575 CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 5576 .features[FEAT_7_0_EBX] = 5577 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_ERMS | 5578 CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_SMAP | 5579 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_SHA_NI, 5580 .features[FEAT_7_0_EDX] = 5581 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES | 5582 CPUID_7_0_EDX_SPEC_CTRL_SSBD, 5583 /* XSAVES is added in version 3 */ 5584 .features[FEAT_XSAVE] = 5585 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | CPUID_XSAVE_XGETBV1, 5586 .features[FEAT_6_EAX] = 5587 CPUID_6_EAX_ARAT, 5588 .features[FEAT_ARCH_CAPABILITIES] = 5589 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY, 5590 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 5591 MSR_VMX_BASIC_TRUE_CTLS, 5592 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 5593 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 5594 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 5595 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 5596 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 5597 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 5598 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 5599 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 5600 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 5601 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 5602 .features[FEAT_VMX_EXIT_CTLS] = 5603 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 5604 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 5605 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 5606 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 5607 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 5608 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 5609 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 5610 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 5611 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 5612 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 5613 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 5614 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 5615 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 5616 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 5617 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 5618 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 5619 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 5620 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 5621 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 5622 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 5623 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 5624 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 5625 .features[FEAT_VMX_SECONDARY_CTLS] = 5626 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 5627 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 5628 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 5629 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 5630 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 5631 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 5632 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 5633 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 5634 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 5635 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 5636 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 5637 .xlevel = 0x80000008, 5638 .model_id = "Intel Atom Processor (Denverton)", 5639 .versions = (X86CPUVersionDefinition[]) { 5640 { .version = 1 }, 5641 { 5642 .version = 2, 5643 .note = "no MPX, no MONITOR", 5644 .props = (PropValue[]) { 5645 { "monitor", "off" }, 5646 { "mpx", "off" }, 5647 { /* end of list */ }, 5648 }, 5649 }, 5650 { 5651 .version = 3, 5652 .note = "XSAVES, no MPX, no MONITOR", 5653 .props = (PropValue[]) { 5654 { "xsaves", "on" }, 5655 { "vmx-xsaves", "on" }, 5656 { /* end of list */ }, 5657 }, 5658 }, 5659 { /* end of list */ }, 5660 }, 5661 }, 5662 { 5663 .name = "Snowridge", 5664 .level = 27, 5665 .vendor = CPUID_VENDOR_INTEL, 5666 .family = 6, 5667 .model = 134, 5668 .stepping = 1, 5669 .features[FEAT_1_EDX] = 5670 /* missing: CPUID_PN CPUID_IA64 */ 5671 /* missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 5672 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | 5673 CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_MCE | 5674 CPUID_CX8 | CPUID_APIC | CPUID_SEP | 5675 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 5676 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | 5677 CPUID_MMX | 5678 CPUID_FXSR | CPUID_SSE | CPUID_SSE2, 5679 .features[FEAT_1_ECX] = 5680 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR | 5681 CPUID_EXT_SSSE3 | 5682 CPUID_EXT_CX16 | 5683 CPUID_EXT_SSE41 | 5684 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 5685 CPUID_EXT_POPCNT | 5686 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | CPUID_EXT_XSAVE | 5687 CPUID_EXT_RDRAND, 5688 .features[FEAT_8000_0001_EDX] = 5689 CPUID_EXT2_SYSCALL | 5690 CPUID_EXT2_NX | 5691 CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 5692 CPUID_EXT2_LM, 5693 .features[FEAT_8000_0001_ECX] = 5694 CPUID_EXT3_LAHF_LM | 5695 CPUID_EXT3_3DNOWPREFETCH, 5696 .features[FEAT_7_0_EBX] = 5697 CPUID_7_0_EBX_FSGSBASE | 5698 CPUID_7_0_EBX_SMEP | 5699 CPUID_7_0_EBX_ERMS | 5700 CPUID_7_0_EBX_MPX | /* missing bits 13, 15 */ 5701 CPUID_7_0_EBX_RDSEED | 5702 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 5703 CPUID_7_0_EBX_CLWB | 5704 CPUID_7_0_EBX_SHA_NI, 5705 .features[FEAT_7_0_ECX] = 5706 CPUID_7_0_ECX_UMIP | 5707 /* missing bit 5 */ 5708 CPUID_7_0_ECX_GFNI | 5709 CPUID_7_0_ECX_MOVDIRI | CPUID_7_0_ECX_CLDEMOTE | 5710 CPUID_7_0_ECX_MOVDIR64B, 5711 .features[FEAT_7_0_EDX] = 5712 CPUID_7_0_EDX_SPEC_CTRL | 5713 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD | 5714 CPUID_7_0_EDX_CORE_CAPABILITY, 5715 .features[FEAT_CORE_CAPABILITY] = 5716 MSR_CORE_CAP_SPLIT_LOCK_DETECT, 5717 /* XSAVES is added in version 3 */ 5718 .features[FEAT_XSAVE] = 5719 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5720 CPUID_XSAVE_XGETBV1, 5721 .features[FEAT_6_EAX] = 5722 CPUID_6_EAX_ARAT, 5723 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 5724 MSR_VMX_BASIC_TRUE_CTLS, 5725 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 5726 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 5727 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 5728 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 5729 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 5730 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 5731 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 5732 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 5733 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 5734 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 5735 .features[FEAT_VMX_EXIT_CTLS] = 5736 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 5737 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 5738 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 5739 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 5740 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 5741 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 5742 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 5743 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 5744 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 5745 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 5746 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 5747 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 5748 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 5749 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 5750 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 5751 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 5752 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 5753 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 5754 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 5755 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 5756 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 5757 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 5758 .features[FEAT_VMX_SECONDARY_CTLS] = 5759 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 5760 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 5761 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 5762 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 5763 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 5764 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 5765 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 5766 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 5767 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 5768 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 5769 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 5770 .xlevel = 0x80000008, 5771 .model_id = "Intel Atom Processor (SnowRidge)", 5772 .versions = (X86CPUVersionDefinition[]) { 5773 { .version = 1 }, 5774 { 5775 .version = 2, 5776 .props = (PropValue[]) { 5777 { "mpx", "off" }, 5778 { "model-id", "Intel Atom Processor (Snowridge, no MPX)" }, 5779 { /* end of list */ }, 5780 }, 5781 }, 5782 { 5783 .version = 3, 5784 .note = "XSAVES, no MPX", 5785 .props = (PropValue[]) { 5786 { "xsaves", "on" }, 5787 { "vmx-xsaves", "on" }, 5788 { /* end of list */ }, 5789 }, 5790 }, 5791 { 5792 .version = 4, 5793 .note = "no split lock detect, no core-capability", 5794 .props = (PropValue[]) { 5795 { "split-lock-detect", "off" }, 5796 { "core-capability", "off" }, 5797 { /* end of list */ }, 5798 }, 5799 }, 5800 { /* end of list */ }, 5801 }, 5802 }, 5803 { 5804 .name = "KnightsMill", 5805 .level = 0xd, 5806 .vendor = CPUID_VENDOR_INTEL, 5807 .family = 6, 5808 .model = 133, 5809 .stepping = 0, 5810 .features[FEAT_1_EDX] = 5811 CPUID_VME | CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | 5812 CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | 5813 CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | 5814 CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | 5815 CPUID_PSE | CPUID_DE | CPUID_FP87, 5816 .features[FEAT_1_ECX] = 5817 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 5818 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 5819 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 5820 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 5821 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 5822 CPUID_EXT_F16C | CPUID_EXT_RDRAND, 5823 .features[FEAT_8000_0001_EDX] = 5824 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 5825 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 5826 .features[FEAT_8000_0001_ECX] = 5827 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 5828 .features[FEAT_7_0_EBX] = 5829 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5830 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 5831 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_AVX512F | 5832 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_AVX512PF | 5833 CPUID_7_0_EBX_AVX512ER, 5834 .features[FEAT_7_0_ECX] = 5835 CPUID_7_0_ECX_AVX512_VPOPCNTDQ, 5836 .features[FEAT_7_0_EDX] = 5837 CPUID_7_0_EDX_AVX512_4VNNIW | CPUID_7_0_EDX_AVX512_4FMAPS, 5838 .features[FEAT_XSAVE] = 5839 CPUID_XSAVE_XSAVEOPT, 5840 .features[FEAT_6_EAX] = 5841 CPUID_6_EAX_ARAT, 5842 .xlevel = 0x80000008, 5843 .model_id = "Intel Xeon Phi Processor (Knights Mill)", 5844 }, 5845 { 5846 .name = "Opteron_G1", 5847 .level = 5, 5848 .vendor = CPUID_VENDOR_AMD, 5849 .family = 15, 5850 .model = 6, 5851 .stepping = 1, 5852 .features[FEAT_1_EDX] = 5853 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 5854 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 5855 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 5856 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 5857 CPUID_DE | CPUID_FP87, 5858 .features[FEAT_1_ECX] = 5859 CPUID_EXT_SSE3, 5860 .features[FEAT_8000_0001_EDX] = 5861 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 5862 .xlevel = 0x80000008, 5863 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)", 5864 }, 5865 { 5866 .name = "Opteron_G2", 5867 .level = 5, 5868 .vendor = CPUID_VENDOR_AMD, 5869 .family = 15, 5870 .model = 6, 5871 .stepping = 1, 5872 .features[FEAT_1_EDX] = 5873 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 5874 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 5875 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 5876 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 5877 CPUID_DE | CPUID_FP87, 5878 .features[FEAT_1_ECX] = 5879 CPUID_EXT_CX16 | CPUID_EXT_SSE3, 5880 .features[FEAT_8000_0001_EDX] = 5881 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 5882 .features[FEAT_8000_0001_ECX] = 5883 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, 5884 .xlevel = 0x80000008, 5885 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)", 5886 }, 5887 { 5888 .name = "Opteron_G3", 5889 .level = 5, 5890 .vendor = CPUID_VENDOR_AMD, 5891 .family = 16, 5892 .model = 2, 5893 .stepping = 3, 5894 .features[FEAT_1_EDX] = 5895 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 5896 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 5897 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 5898 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 5899 CPUID_DE | CPUID_FP87, 5900 .features[FEAT_1_ECX] = 5901 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR | 5902 CPUID_EXT_SSE3, 5903 .features[FEAT_8000_0001_EDX] = 5904 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL | 5905 CPUID_EXT2_RDTSCP, 5906 .features[FEAT_8000_0001_ECX] = 5907 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | 5908 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, 5909 .xlevel = 0x80000008, 5910 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)", 5911 }, 5912 { 5913 .name = "Opteron_G4", 5914 .level = 0xd, 5915 .vendor = CPUID_VENDOR_AMD, 5916 .family = 21, 5917 .model = 1, 5918 .stepping = 2, 5919 .features[FEAT_1_EDX] = 5920 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 5921 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 5922 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 5923 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 5924 CPUID_DE | CPUID_FP87, 5925 .features[FEAT_1_ECX] = 5926 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 5927 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5928 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 5929 CPUID_EXT_SSE3, 5930 .features[FEAT_8000_0001_EDX] = 5931 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX | 5932 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP, 5933 .features[FEAT_8000_0001_ECX] = 5934 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP | 5935 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | 5936 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | 5937 CPUID_EXT3_LAHF_LM, 5938 .features[FEAT_SVM] = 5939 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 5940 /* no xsaveopt! */ 5941 .xlevel = 0x8000001A, 5942 .model_id = "AMD Opteron 62xx class CPU", 5943 }, 5944 { 5945 .name = "Opteron_G5", 5946 .level = 0xd, 5947 .vendor = CPUID_VENDOR_AMD, 5948 .family = 21, 5949 .model = 2, 5950 .stepping = 0, 5951 .features[FEAT_1_EDX] = 5952 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 5953 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 5954 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 5955 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 5956 CPUID_DE | CPUID_FP87, 5957 .features[FEAT_1_ECX] = 5958 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE | 5959 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | 5960 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA | 5961 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 5962 .features[FEAT_8000_0001_EDX] = 5963 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX | 5964 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP, 5965 .features[FEAT_8000_0001_ECX] = 5966 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP | 5967 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | 5968 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | 5969 CPUID_EXT3_LAHF_LM, 5970 .features[FEAT_SVM] = 5971 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 5972 /* no xsaveopt! */ 5973 .xlevel = 0x8000001A, 5974 .model_id = "AMD Opteron 63xx class CPU", 5975 }, 5976 { 5977 .name = "EPYC", 5978 .level = 0xd, 5979 .vendor = CPUID_VENDOR_AMD, 5980 .family = 23, 5981 .model = 1, 5982 .stepping = 2, 5983 .features[FEAT_1_EDX] = 5984 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 5985 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 5986 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 5987 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 5988 CPUID_VME | CPUID_FP87, 5989 .features[FEAT_1_ECX] = 5990 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5991 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 5992 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5993 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 5994 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 5995 .features[FEAT_8000_0001_EDX] = 5996 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5997 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5998 CPUID_EXT2_SYSCALL, 5999 .features[FEAT_8000_0001_ECX] = 6000 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 6001 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 6002 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 6003 CPUID_EXT3_TOPOEXT, 6004 .features[FEAT_7_0_EBX] = 6005 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 6006 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 6007 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 6008 CPUID_7_0_EBX_SHA_NI, 6009 .features[FEAT_XSAVE] = 6010 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 6011 CPUID_XSAVE_XGETBV1, 6012 .features[FEAT_6_EAX] = 6013 CPUID_6_EAX_ARAT, 6014 .features[FEAT_SVM] = 6015 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 6016 .xlevel = 0x8000001E, 6017 .model_id = "AMD EPYC Processor", 6018 .cache_info = &epyc_cache_info, 6019 .versions = (X86CPUVersionDefinition[]) { 6020 { .version = 1 }, 6021 { 6022 .version = 2, 6023 .alias = "EPYC-IBPB", 6024 .props = (PropValue[]) { 6025 { "ibpb", "on" }, 6026 { "model-id", 6027 "AMD EPYC Processor (with IBPB)" }, 6028 { /* end of list */ } 6029 } 6030 }, 6031 { 6032 .version = 3, 6033 .props = (PropValue[]) { 6034 { "ibpb", "on" }, 6035 { "perfctr-core", "on" }, 6036 { "clzero", "on" }, 6037 { "xsaveerptr", "on" }, 6038 { "xsaves", "on" }, 6039 { "model-id", 6040 "AMD EPYC Processor" }, 6041 { /* end of list */ } 6042 } 6043 }, 6044 { 6045 .version = 4, 6046 .props = (PropValue[]) { 6047 { "model-id", 6048 "AMD EPYC-v4 Processor" }, 6049 { /* end of list */ } 6050 }, 6051 .cache_info = &epyc_v4_cache_info 6052 }, 6053 { 6054 .version = 5, 6055 .props = (PropValue[]) { 6056 { "overflow-recov", "on" }, 6057 { "succor", "on" }, 6058 { "lbrv", "on" }, 6059 { "tsc-scale", "on" }, 6060 { "vmcb-clean", "on" }, 6061 { "flushbyasid", "on" }, 6062 { "pause-filter", "on" }, 6063 { "pfthreshold", "on" }, 6064 { "v-vmsave-vmload", "on" }, 6065 { "vgif", "on" }, 6066 { "model-id", 6067 "AMD EPYC-v5 Processor" }, 6068 { /* end of list */ } 6069 }, 6070 .cache_info = &epyc_v5_cache_info 6071 }, 6072 { /* end of list */ } 6073 } 6074 }, 6075 { 6076 .name = "Dhyana", 6077 .level = 0xd, 6078 .vendor = CPUID_VENDOR_HYGON, 6079 .family = 24, 6080 .model = 0, 6081 .stepping = 1, 6082 .features[FEAT_1_EDX] = 6083 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 6084 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 6085 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 6086 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 6087 CPUID_VME | CPUID_FP87, 6088 .features[FEAT_1_ECX] = 6089 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 6090 CPUID_EXT_XSAVE | CPUID_EXT_POPCNT | 6091 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 6092 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 6093 CPUID_EXT_MONITOR | CPUID_EXT_SSE3, 6094 .features[FEAT_8000_0001_EDX] = 6095 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 6096 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 6097 CPUID_EXT2_SYSCALL, 6098 .features[FEAT_8000_0001_ECX] = 6099 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 6100 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 6101 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 6102 CPUID_EXT3_TOPOEXT, 6103 .features[FEAT_8000_0008_EBX] = 6104 CPUID_8000_0008_EBX_IBPB, 6105 .features[FEAT_7_0_EBX] = 6106 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 6107 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 6108 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT, 6109 /* XSAVES is added in version 2 */ 6110 .features[FEAT_XSAVE] = 6111 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 6112 CPUID_XSAVE_XGETBV1, 6113 .features[FEAT_6_EAX] = 6114 CPUID_6_EAX_ARAT, 6115 .features[FEAT_SVM] = 6116 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 6117 .xlevel = 0x8000001E, 6118 .model_id = "Hygon Dhyana Processor", 6119 .cache_info = &epyc_cache_info, 6120 .versions = (X86CPUVersionDefinition[]) { 6121 { .version = 1 }, 6122 { .version = 2, 6123 .note = "XSAVES", 6124 .props = (PropValue[]) { 6125 { "xsaves", "on" }, 6126 { /* end of list */ } 6127 }, 6128 }, 6129 { /* end of list */ } 6130 } 6131 }, 6132 { 6133 .name = "EPYC-Rome", 6134 .level = 0xd, 6135 .vendor = CPUID_VENDOR_AMD, 6136 .family = 23, 6137 .model = 49, 6138 .stepping = 0, 6139 .features[FEAT_1_EDX] = 6140 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 6141 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 6142 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 6143 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 6144 CPUID_VME | CPUID_FP87, 6145 .features[FEAT_1_ECX] = 6146 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 6147 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 6148 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 6149 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 6150 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 6151 .features[FEAT_8000_0001_EDX] = 6152 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 6153 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 6154 CPUID_EXT2_SYSCALL, 6155 .features[FEAT_8000_0001_ECX] = 6156 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 6157 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 6158 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 6159 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 6160 .features[FEAT_8000_0008_EBX] = 6161 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 6162 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 6163 CPUID_8000_0008_EBX_STIBP, 6164 .features[FEAT_7_0_EBX] = 6165 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 6166 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 6167 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 6168 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB, 6169 .features[FEAT_7_0_ECX] = 6170 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID, 6171 .features[FEAT_XSAVE] = 6172 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 6173 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 6174 .features[FEAT_6_EAX] = 6175 CPUID_6_EAX_ARAT, 6176 .features[FEAT_SVM] = 6177 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 6178 .xlevel = 0x8000001E, 6179 .model_id = "AMD EPYC-Rome Processor", 6180 .cache_info = &epyc_rome_cache_info, 6181 .versions = (X86CPUVersionDefinition[]) { 6182 { .version = 1 }, 6183 { 6184 .version = 2, 6185 .props = (PropValue[]) { 6186 { "ibrs", "on" }, 6187 { "amd-ssbd", "on" }, 6188 { /* end of list */ } 6189 } 6190 }, 6191 { 6192 .version = 3, 6193 .props = (PropValue[]) { 6194 { "model-id", 6195 "AMD EPYC-Rome-v3 Processor" }, 6196 { /* end of list */ } 6197 }, 6198 .cache_info = &epyc_rome_v3_cache_info 6199 }, 6200 { 6201 .version = 4, 6202 .props = (PropValue[]) { 6203 /* Erratum 1386 */ 6204 { "model-id", 6205 "AMD EPYC-Rome-v4 Processor (no XSAVES)" }, 6206 { "xsaves", "off" }, 6207 { /* end of list */ } 6208 }, 6209 }, 6210 { 6211 .version = 5, 6212 .props = (PropValue[]) { 6213 { "overflow-recov", "on" }, 6214 { "succor", "on" }, 6215 { "lbrv", "on" }, 6216 { "tsc-scale", "on" }, 6217 { "vmcb-clean", "on" }, 6218 { "flushbyasid", "on" }, 6219 { "pause-filter", "on" }, 6220 { "pfthreshold", "on" }, 6221 { "v-vmsave-vmload", "on" }, 6222 { "vgif", "on" }, 6223 { "model-id", 6224 "AMD EPYC-Rome-v5 Processor" }, 6225 { /* end of list */ } 6226 }, 6227 .cache_info = &epyc_rome_v5_cache_info 6228 }, 6229 { /* end of list */ } 6230 } 6231 }, 6232 { 6233 .name = "EPYC-Milan", 6234 .level = 0xd, 6235 .vendor = CPUID_VENDOR_AMD, 6236 .family = 25, 6237 .model = 1, 6238 .stepping = 1, 6239 .features[FEAT_1_EDX] = 6240 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 6241 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 6242 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 6243 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 6244 CPUID_VME | CPUID_FP87, 6245 .features[FEAT_1_ECX] = 6246 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 6247 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 6248 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 6249 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 6250 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 6251 CPUID_EXT_PCID, 6252 .features[FEAT_8000_0001_EDX] = 6253 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 6254 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 6255 CPUID_EXT2_SYSCALL, 6256 .features[FEAT_8000_0001_ECX] = 6257 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 6258 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 6259 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 6260 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 6261 .features[FEAT_8000_0008_EBX] = 6262 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 6263 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 6264 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | 6265 CPUID_8000_0008_EBX_AMD_SSBD, 6266 .features[FEAT_7_0_EBX] = 6267 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 6268 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 6269 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 6270 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_ERMS | 6271 CPUID_7_0_EBX_INVPCID, 6272 .features[FEAT_7_0_ECX] = 6273 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_PKU, 6274 .features[FEAT_7_0_EDX] = 6275 CPUID_7_0_EDX_FSRM, 6276 .features[FEAT_XSAVE] = 6277 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 6278 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 6279 .features[FEAT_6_EAX] = 6280 CPUID_6_EAX_ARAT, 6281 .features[FEAT_SVM] = 6282 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE | CPUID_SVM_SVME_ADDR_CHK, 6283 .xlevel = 0x8000001E, 6284 .model_id = "AMD EPYC-Milan Processor", 6285 .cache_info = &epyc_milan_cache_info, 6286 .versions = (X86CPUVersionDefinition[]) { 6287 { .version = 1 }, 6288 { 6289 .version = 2, 6290 .props = (PropValue[]) { 6291 { "model-id", 6292 "AMD EPYC-Milan-v2 Processor" }, 6293 { "vaes", "on" }, 6294 { "vpclmulqdq", "on" }, 6295 { "stibp-always-on", "on" }, 6296 { "amd-psfd", "on" }, 6297 { "no-nested-data-bp", "on" }, 6298 { "lfence-always-serializing", "on" }, 6299 { "null-sel-clr-base", "on" }, 6300 { /* end of list */ } 6301 }, 6302 .cache_info = &epyc_milan_v2_cache_info 6303 }, 6304 { 6305 .version = 3, 6306 .props = (PropValue[]) { 6307 { "overflow-recov", "on" }, 6308 { "succor", "on" }, 6309 { "lbrv", "on" }, 6310 { "tsc-scale", "on" }, 6311 { "vmcb-clean", "on" }, 6312 { "flushbyasid", "on" }, 6313 { "pause-filter", "on" }, 6314 { "pfthreshold", "on" }, 6315 { "v-vmsave-vmload", "on" }, 6316 { "vgif", "on" }, 6317 { "model-id", 6318 "AMD EPYC-Milan-v3 Processor" }, 6319 { /* end of list */ } 6320 }, 6321 .cache_info = &epyc_milan_v3_cache_info 6322 }, 6323 { /* end of list */ } 6324 } 6325 }, 6326 { 6327 .name = "EPYC-Genoa", 6328 .level = 0xd, 6329 .vendor = CPUID_VENDOR_AMD, 6330 .family = 25, 6331 .model = 17, 6332 .stepping = 0, 6333 .features[FEAT_1_EDX] = 6334 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 6335 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 6336 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 6337 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 6338 CPUID_VME | CPUID_FP87, 6339 .features[FEAT_1_ECX] = 6340 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 6341 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 6342 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 6343 CPUID_EXT_PCID | CPUID_EXT_CX16 | CPUID_EXT_FMA | 6344 CPUID_EXT_SSSE3 | CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | 6345 CPUID_EXT_SSE3, 6346 .features[FEAT_8000_0001_EDX] = 6347 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 6348 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 6349 CPUID_EXT2_SYSCALL, 6350 .features[FEAT_8000_0001_ECX] = 6351 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 6352 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 6353 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 6354 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 6355 .features[FEAT_8000_0008_EBX] = 6356 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 6357 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 6358 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | 6359 CPUID_8000_0008_EBX_STIBP_ALWAYS_ON | 6360 CPUID_8000_0008_EBX_AMD_SSBD | CPUID_8000_0008_EBX_AMD_PSFD, 6361 .features[FEAT_8000_0021_EAX] = 6362 CPUID_8000_0021_EAX_NO_NESTED_DATA_BP | 6363 CPUID_8000_0021_EAX_LFENCE_ALWAYS_SERIALIZING | 6364 CPUID_8000_0021_EAX_NULL_SEL_CLR_BASE | 6365 CPUID_8000_0021_EAX_AUTO_IBRS, 6366 .features[FEAT_7_0_EBX] = 6367 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 6368 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 6369 CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_AVX512F | 6370 CPUID_7_0_EBX_AVX512DQ | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 6371 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_AVX512IFMA | 6372 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB | 6373 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | 6374 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, 6375 .features[FEAT_7_0_ECX] = 6376 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 6377 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 6378 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 6379 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 6380 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | 6381 CPUID_7_0_ECX_RDPID, 6382 .features[FEAT_7_0_EDX] = 6383 CPUID_7_0_EDX_FSRM, 6384 .features[FEAT_7_1_EAX] = 6385 CPUID_7_1_EAX_AVX512_BF16, 6386 .features[FEAT_XSAVE] = 6387 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 6388 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 6389 .features[FEAT_6_EAX] = 6390 CPUID_6_EAX_ARAT, 6391 .features[FEAT_SVM] = 6392 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE | CPUID_SVM_VNMI | 6393 CPUID_SVM_SVME_ADDR_CHK, 6394 .xlevel = 0x80000022, 6395 .model_id = "AMD EPYC-Genoa Processor", 6396 .cache_info = &epyc_genoa_cache_info, 6397 .versions = (X86CPUVersionDefinition[]) { 6398 { .version = 1 }, 6399 { 6400 .version = 2, 6401 .props = (PropValue[]) { 6402 { "overflow-recov", "on" }, 6403 { "succor", "on" }, 6404 { "lbrv", "on" }, 6405 { "tsc-scale", "on" }, 6406 { "vmcb-clean", "on" }, 6407 { "flushbyasid", "on" }, 6408 { "pause-filter", "on" }, 6409 { "pfthreshold", "on" }, 6410 { "v-vmsave-vmload", "on" }, 6411 { "vgif", "on" }, 6412 { "fs-gs-base-ns", "on" }, 6413 { "perfmon-v2", "on" }, 6414 { "model-id", 6415 "AMD EPYC-Genoa-v2 Processor" }, 6416 { /* end of list */ } 6417 }, 6418 .cache_info = &epyc_genoa_v2_cache_info 6419 }, 6420 { /* end of list */ } 6421 } 6422 }, 6423 { 6424 .name = "YongFeng", 6425 .level = 0x1F, 6426 .vendor = CPUID_VENDOR_ZHAOXIN1, 6427 .family = 7, 6428 .model = 11, 6429 .stepping = 3, 6430 /* missing: CPUID_HT, CPUID_TM, CPUID_PBE */ 6431 .features[FEAT_1_EDX] = 6432 CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 6433 CPUID_ACPI | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | 6434 CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | 6435 CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | 6436 CPUID_PSE | CPUID_DE | CPUID_VME | CPUID_FP87, 6437 /* 6438 * missing: CPUID_EXT_OSXSAVE, CPUID_EXT_XTPR, CPUID_EXT_TM2, 6439 * CPUID_EXT_EST, CPUID_EXT_SMX, CPUID_EXT_VMX 6440 */ 6441 .features[FEAT_1_ECX] = 6442 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 6443 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_TSC_DEADLINE_TIMER | 6444 CPUID_EXT_POPCNT | CPUID_EXT_MOVBE | CPUID_EXT_X2APIC | 6445 CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | CPUID_EXT_PCID | 6446 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 6447 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 6448 .features[FEAT_7_0_EBX] = 6449 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_ADX | 6450 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_BMI2 | 6451 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_BMI1 | 6452 CPUID_7_0_EBX_FSGSBASE, 6453 /* missing: CPUID_7_0_ECX_OSPKE */ 6454 .features[FEAT_7_0_ECX] = 6455 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_UMIP, 6456 .features[FEAT_7_0_EDX] = 6457 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL, 6458 .features[FEAT_8000_0001_EDX] = 6459 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 6460 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 6461 .features[FEAT_8000_0001_ECX] = 6462 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM, 6463 .features[FEAT_8000_0007_EDX] = CPUID_APM_INVTSC, 6464 /* 6465 * TODO: When the Linux kernel introduces other existing definitions 6466 * for this leaf, remember to update the definitions here. 6467 */ 6468 .features[FEAT_C000_0001_EDX] = 6469 CPUID_C000_0001_EDX_PMM_EN | CPUID_C000_0001_EDX_PMM | 6470 CPUID_C000_0001_EDX_PHE_EN | CPUID_C000_0001_EDX_PHE | 6471 CPUID_C000_0001_EDX_ACE2 | 6472 CPUID_C000_0001_EDX_XCRYPT_EN | CPUID_C000_0001_EDX_XCRYPT | 6473 CPUID_C000_0001_EDX_XSTORE_EN | CPUID_C000_0001_EDX_XSTORE, 6474 .features[FEAT_XSAVE] = 6475 CPUID_XSAVE_XSAVEOPT, 6476 .features[FEAT_ARCH_CAPABILITIES] = 6477 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | 6478 MSR_ARCH_CAP_MDS_NO | MSR_ARCH_CAP_PSCHANGE_MC_NO | 6479 MSR_ARCH_CAP_SSB_NO, 6480 .features[FEAT_VMX_PROCBASED_CTLS] = 6481 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | VMX_CPU_BASED_HLT_EXITING | 6482 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_INVLPG_EXITING | 6483 VMX_CPU_BASED_MWAIT_EXITING | VMX_CPU_BASED_RDPMC_EXITING | 6484 VMX_CPU_BASED_RDTSC_EXITING | VMX_CPU_BASED_CR3_LOAD_EXITING | 6485 VMX_CPU_BASED_CR3_STORE_EXITING | VMX_CPU_BASED_CR8_LOAD_EXITING | 6486 VMX_CPU_BASED_CR8_STORE_EXITING | VMX_CPU_BASED_TPR_SHADOW | 6487 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_MOV_DR_EXITING | 6488 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 6489 VMX_CPU_BASED_MONITOR_TRAP_FLAG | VMX_CPU_BASED_USE_MSR_BITMAPS | 6490 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 6491 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 6492 /* 6493 * missing: VMX_SECONDARY_EXEC_PAUSE_LOOP_EXITING, 6494 * VMX_SECONDARY_EXEC_TSC_SCALING 6495 */ 6496 .features[FEAT_VMX_SECONDARY_CTLS] = 6497 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 6498 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 6499 VMX_SECONDARY_EXEC_RDTSCP | VMX_SECONDARY_EXEC_ENABLE_VPID | 6500 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 6501 VMX_SECONDARY_EXEC_WBINVD_EXITING | 6502 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 6503 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 6504 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 6505 VMX_SECONDARY_EXEC_RDRAND_EXITING | 6506 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 6507 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | 6508 VMX_SECONDARY_EXEC_SHADOW_VMCS | 6509 VMX_SECONDARY_EXEC_ENABLE_PML, 6510 .features[FEAT_VMX_PINBASED_CTLS] = 6511 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 6512 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 6513 VMX_PIN_BASED_POSTED_INTR, 6514 .features[FEAT_VMX_EXIT_CTLS] = 6515 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE | 6516 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 6517 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 6518 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 6519 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 6520 /* missing: VMX_VM_ENTRY_SMM, VMX_VM_ENTRY_DEACT_DUAL_MONITOR */ 6521 .features[FEAT_VMX_ENTRY_CTLS] = 6522 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 6523 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 6524 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 6525 /* 6526 * missing: MSR_VMX_MISC_ACTIVITY_SHUTDOWN, 6527 * MSR_VMX_MISC_ACTIVITY_WAIT_SIPI 6528 */ 6529 .features[FEAT_VMX_MISC] = 6530 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 6531 MSR_VMX_MISC_VMWRITE_VMEXIT, 6532 /* missing: MSR_VMX_EPT_UC */ 6533 .features[FEAT_VMX_EPT_VPID_CAPS] = 6534 MSR_VMX_EPT_EXECONLY | MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | 6535 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 6536 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 6537 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 6538 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID | 6539 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 6540 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 6541 .features[FEAT_VMX_BASIC] = 6542 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 6543 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 6544 .xlevel = 0x80000008, 6545 .model_id = "Zhaoxin YongFeng Processor", 6546 .versions = (X86CPUVersionDefinition[]) { 6547 { .version = 1 }, 6548 { 6549 .version = 2, 6550 .note = "with the correct model number", 6551 .props = (PropValue[]) { 6552 { "model", "0x5b" }, 6553 { /* end of list */ } 6554 } 6555 }, 6556 { 6557 .version = 3, 6558 .note = "with the cache model and 0x1f leaf", 6559 .cache_info = &yongfeng_cache_info, 6560 .props = (PropValue[]) { 6561 { "x-force-cpuid-0x1f", "on" }, 6562 { /* end of list */ }, 6563 } 6564 }, 6565 { /* end of list */ } 6566 } 6567 }, 6568 { 6569 .name = "EPYC-Turin", 6570 .level = 0xd, 6571 .vendor = CPUID_VENDOR_AMD, 6572 .family = 26, 6573 .model = 0, 6574 .stepping = 0, 6575 .features[FEAT_1_ECX] = 6576 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 6577 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 6578 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 6579 CPUID_EXT_PCID | CPUID_EXT_CX16 | CPUID_EXT_FMA | 6580 CPUID_EXT_SSSE3 | CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | 6581 CPUID_EXT_SSE3, 6582 .features[FEAT_1_EDX] = 6583 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 6584 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 6585 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 6586 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 6587 CPUID_VME | CPUID_FP87, 6588 .features[FEAT_6_EAX] = 6589 CPUID_6_EAX_ARAT, 6590 .features[FEAT_7_0_EBX] = 6591 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 6592 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 6593 CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_AVX512F | 6594 CPUID_7_0_EBX_AVX512DQ | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 6595 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_AVX512IFMA | 6596 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB | 6597 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | 6598 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, 6599 .features[FEAT_7_0_ECX] = 6600 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 6601 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 6602 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 6603 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 6604 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | 6605 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_MOVDIRI | 6606 CPUID_7_0_ECX_MOVDIR64B, 6607 .features[FEAT_7_0_EDX] = 6608 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_AVX512_VP2INTERSECT, 6609 .features[FEAT_7_1_EAX] = 6610 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_AVX512_BF16, 6611 .features[FEAT_8000_0001_ECX] = 6612 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 6613 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 6614 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 6615 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 6616 .features[FEAT_8000_0001_EDX] = 6617 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 6618 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 6619 CPUID_EXT2_SYSCALL, 6620 .features[FEAT_8000_0007_EBX] = 6621 CPUID_8000_0007_EBX_OVERFLOW_RECOV | CPUID_8000_0007_EBX_SUCCOR, 6622 .features[FEAT_8000_0008_EBX] = 6623 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 6624 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 6625 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | 6626 CPUID_8000_0008_EBX_STIBP_ALWAYS_ON | 6627 CPUID_8000_0008_EBX_AMD_SSBD | CPUID_8000_0008_EBX_AMD_PSFD, 6628 .features[FEAT_8000_0021_EAX] = 6629 CPUID_8000_0021_EAX_NO_NESTED_DATA_BP | 6630 CPUID_8000_0021_EAX_FS_GS_BASE_NS | 6631 CPUID_8000_0021_EAX_LFENCE_ALWAYS_SERIALIZING | 6632 CPUID_8000_0021_EAX_NULL_SEL_CLR_BASE | 6633 CPUID_8000_0021_EAX_AUTO_IBRS | CPUID_8000_0021_EAX_PREFETCHI | 6634 CPUID_8000_0021_EAX_SBPB | CPUID_8000_0021_EAX_IBPB_BRTYPE | 6635 CPUID_8000_0021_EAX_SRSO_USER_KERNEL_NO, 6636 .features[FEAT_8000_0022_EAX] = 6637 CPUID_8000_0022_EAX_PERFMON_V2, 6638 .features[FEAT_XSAVE] = 6639 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 6640 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 6641 .features[FEAT_SVM] = 6642 CPUID_SVM_NPT | CPUID_SVM_LBRV | CPUID_SVM_NRIPSAVE | 6643 CPUID_SVM_TSCSCALE | CPUID_SVM_VMCBCLEAN | CPUID_SVM_FLUSHASID | 6644 CPUID_SVM_PAUSEFILTER | CPUID_SVM_PFTHRESHOLD | 6645 CPUID_SVM_V_VMSAVE_VMLOAD | CPUID_SVM_VGIF | 6646 CPUID_SVM_VNMI | CPUID_SVM_SVME_ADDR_CHK, 6647 .xlevel = 0x80000022, 6648 .model_id = "AMD EPYC-Turin Processor", 6649 .cache_info = &epyc_turin_cache_info, 6650 }, 6651 }; 6652 6653 /* 6654 * We resolve CPU model aliases using -v1 when using "-machine 6655 * none", but this is just for compatibility while libvirt isn't 6656 * adapted to resolve CPU model versions before creating VMs. 6657 * See "Runnability guarantee of CPU models" at 6658 * docs/about/deprecated.rst. 6659 */ 6660 X86CPUVersion default_cpu_version = 1; 6661 6662 void x86_cpu_set_default_version(X86CPUVersion version) 6663 { 6664 /* Translating CPU_VERSION_AUTO to CPU_VERSION_AUTO doesn't make sense */ 6665 assert(version != CPU_VERSION_AUTO); 6666 default_cpu_version = version; 6667 } 6668 6669 static X86CPUVersion x86_cpu_model_last_version(const X86CPUModel *model) 6670 { 6671 int v = 0; 6672 const X86CPUVersionDefinition *vdef = 6673 x86_cpu_def_get_versions(model->cpudef); 6674 while (vdef->version) { 6675 v = vdef->version; 6676 vdef++; 6677 } 6678 return v; 6679 } 6680 6681 /* Return the actual version being used for a specific CPU model */ 6682 static X86CPUVersion x86_cpu_model_resolve_version(const X86CPUModel *model) 6683 { 6684 X86CPUVersion v = model->version; 6685 if (v == CPU_VERSION_AUTO) { 6686 v = default_cpu_version; 6687 } 6688 if (v == CPU_VERSION_LATEST) { 6689 return x86_cpu_model_last_version(model); 6690 } 6691 return v; 6692 } 6693 6694 static const Property max_x86_cpu_properties[] = { 6695 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true), 6696 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false), 6697 }; 6698 6699 static void max_x86_cpu_realize(DeviceState *dev, Error **errp) 6700 { 6701 Object *obj = OBJECT(dev); 6702 6703 if (!object_property_get_int(obj, "family", &error_abort)) { 6704 if (X86_CPU(obj)->env.features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 6705 object_property_set_int(obj, "family", 15, &error_abort); 6706 object_property_set_int(obj, "model", 107, &error_abort); 6707 object_property_set_int(obj, "stepping", 1, &error_abort); 6708 } else { 6709 object_property_set_int(obj, "family", 6, &error_abort); 6710 object_property_set_int(obj, "model", 6, &error_abort); 6711 object_property_set_int(obj, "stepping", 3, &error_abort); 6712 } 6713 } 6714 6715 x86_cpu_realizefn(dev, errp); 6716 } 6717 6718 static void max_x86_cpu_class_init(ObjectClass *oc, const void *data) 6719 { 6720 DeviceClass *dc = DEVICE_CLASS(oc); 6721 X86CPUClass *xcc = X86_CPU_CLASS(oc); 6722 6723 xcc->ordering = 9; 6724 6725 xcc->max_features = true; 6726 xcc->model_description = 6727 "Enables all features supported by the accelerator in the current host"; 6728 6729 device_class_set_props(dc, max_x86_cpu_properties); 6730 dc->realize = max_x86_cpu_realize; 6731 } 6732 6733 static void max_x86_cpu_initfn(Object *obj) 6734 { 6735 X86CPU *cpu = X86_CPU(obj); 6736 CPUX86State *env = &cpu->env; 6737 6738 /* 6739 * these defaults are used for TCG, other accelerators have overwritten 6740 * these values 6741 */ 6742 if (!env->cpuid_vendor1) { 6743 object_property_set_str(OBJECT(cpu), "vendor", CPUID_VENDOR_AMD, 6744 &error_abort); 6745 } 6746 if (!env->cpuid_model[0]) { 6747 object_property_set_str(OBJECT(cpu), "model-id", 6748 "QEMU TCG CPU version " QEMU_HW_VERSION, 6749 &error_abort); 6750 } 6751 } 6752 6753 static const TypeInfo max_x86_cpu_type_info = { 6754 .name = X86_CPU_TYPE_NAME("max"), 6755 .parent = TYPE_X86_CPU, 6756 .instance_init = max_x86_cpu_initfn, 6757 .class_init = max_x86_cpu_class_init, 6758 }; 6759 6760 static char *feature_word_description(FeatureWordInfo *f) 6761 { 6762 assert(f->type == CPUID_FEATURE_WORD || f->type == MSR_FEATURE_WORD); 6763 6764 switch (f->type) { 6765 case CPUID_FEATURE_WORD: 6766 { 6767 const char *reg = get_register_name_32(f->cpuid.reg); 6768 assert(reg); 6769 if (!f->cpuid.needs_ecx) { 6770 return g_strdup_printf("CPUID[eax=%02Xh].%s", f->cpuid.eax, reg); 6771 } else { 6772 return g_strdup_printf("CPUID[eax=%02Xh,ecx=%02Xh].%s", 6773 f->cpuid.eax, f->cpuid.ecx, reg); 6774 } 6775 } 6776 case MSR_FEATURE_WORD: 6777 return g_strdup_printf("MSR(%02Xh)", 6778 f->msr.index); 6779 } 6780 6781 return NULL; 6782 } 6783 6784 static bool x86_cpu_have_filtered_features(X86CPU *cpu) 6785 { 6786 FeatureWord w; 6787 6788 for (w = 0; w < FEATURE_WORDS; w++) { 6789 if (cpu->filtered_features[w]) { 6790 return true; 6791 } 6792 } 6793 6794 return false; 6795 } 6796 6797 void mark_unavailable_features(X86CPU *cpu, FeatureWord w, uint64_t mask, 6798 const char *verbose_prefix) 6799 { 6800 CPUX86State *env = &cpu->env; 6801 FeatureWordInfo *f = &feature_word_info[w]; 6802 int i; 6803 g_autofree char *feat_word_str = feature_word_description(f); 6804 6805 if (!cpu->force_features) { 6806 env->features[w] &= ~mask; 6807 } 6808 cpu->filtered_features[w] |= mask; 6809 6810 if (!verbose_prefix) { 6811 return; 6812 } 6813 6814 for (i = 0; i < 64; ++i) { 6815 if ((1ULL << i) & mask) { 6816 warn_report("%s: %s%s%s [bit %d]", 6817 verbose_prefix, 6818 feat_word_str, 6819 f->feat_names[i] ? "." : "", 6820 f->feat_names[i] ? f->feat_names[i] : "", i); 6821 } 6822 } 6823 } 6824 6825 void mark_forced_on_features(X86CPU *cpu, FeatureWord w, uint64_t mask, 6826 const char *verbose_prefix) 6827 { 6828 CPUX86State *env = &cpu->env; 6829 FeatureWordInfo *f = &feature_word_info[w]; 6830 int i; 6831 6832 if (!cpu->force_features) { 6833 env->features[w] |= mask; 6834 } 6835 6836 cpu->forced_on_features[w] |= mask; 6837 6838 if (!verbose_prefix) { 6839 return; 6840 } 6841 6842 for (i = 0; i < 64; ++i) { 6843 if ((1ULL << i) & mask) { 6844 g_autofree char *feat_word_str = feature_word_description(f); 6845 warn_report("%s: %s%s%s [bit %d]", 6846 verbose_prefix, 6847 feat_word_str, 6848 f->feat_names[i] ? "." : "", 6849 f->feat_names[i] ? f->feat_names[i] : "", i); 6850 } 6851 } 6852 } 6853 6854 static void x86_cpuid_version_get_family(Object *obj, Visitor *v, 6855 const char *name, void *opaque, 6856 Error **errp) 6857 { 6858 X86CPU *cpu = X86_CPU(obj); 6859 CPUX86State *env = &cpu->env; 6860 uint64_t value; 6861 6862 value = x86_cpu_family(env->cpuid_version); 6863 visit_type_uint64(v, name, &value, errp); 6864 } 6865 6866 static void x86_cpuid_version_set_family(Object *obj, Visitor *v, 6867 const char *name, void *opaque, 6868 Error **errp) 6869 { 6870 X86CPU *cpu = X86_CPU(obj); 6871 CPUX86State *env = &cpu->env; 6872 const uint64_t max = 0xff + 0xf; 6873 uint64_t value; 6874 6875 if (!visit_type_uint64(v, name, &value, errp)) { 6876 return; 6877 } 6878 if (value > max) { 6879 error_setg(errp, "parameter '%s' can be at most %" PRIu64, 6880 name ? name : "null", max); 6881 return; 6882 } 6883 6884 env->cpuid_version &= ~0xff00f00; 6885 if (value > 0x0f) { 6886 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20); 6887 } else { 6888 env->cpuid_version |= value << 8; 6889 } 6890 } 6891 6892 static void x86_cpuid_version_get_model(Object *obj, Visitor *v, 6893 const char *name, void *opaque, 6894 Error **errp) 6895 { 6896 X86CPU *cpu = X86_CPU(obj); 6897 CPUX86State *env = &cpu->env; 6898 uint64_t value; 6899 6900 value = x86_cpu_model(env->cpuid_version); 6901 visit_type_uint64(v, name, &value, errp); 6902 } 6903 6904 static void x86_cpuid_version_set_model(Object *obj, Visitor *v, 6905 const char *name, void *opaque, 6906 Error **errp) 6907 { 6908 X86CPU *cpu = X86_CPU(obj); 6909 CPUX86State *env = &cpu->env; 6910 const uint64_t max = 0xff; 6911 uint64_t value; 6912 6913 if (!visit_type_uint64(v, name, &value, errp)) { 6914 return; 6915 } 6916 if (value > max) { 6917 error_setg(errp, "parameter '%s' can be at most %" PRIu64, 6918 name ? name : "null", max); 6919 return; 6920 } 6921 6922 env->cpuid_version &= ~0xf00f0; 6923 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16); 6924 } 6925 6926 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v, 6927 const char *name, void *opaque, 6928 Error **errp) 6929 { 6930 X86CPU *cpu = X86_CPU(obj); 6931 CPUX86State *env = &cpu->env; 6932 uint64_t value; 6933 6934 value = x86_cpu_stepping(env->cpuid_version); 6935 visit_type_uint64(v, name, &value, errp); 6936 } 6937 6938 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v, 6939 const char *name, void *opaque, 6940 Error **errp) 6941 { 6942 X86CPU *cpu = X86_CPU(obj); 6943 CPUX86State *env = &cpu->env; 6944 const uint64_t max = 0xf; 6945 uint64_t value; 6946 6947 if (!visit_type_uint64(v, name, &value, errp)) { 6948 return; 6949 } 6950 if (value > max) { 6951 error_setg(errp, "parameter '%s' can be at most %" PRIu64, 6952 name ? name : "null", max); 6953 return; 6954 } 6955 6956 env->cpuid_version &= ~0xf; 6957 env->cpuid_version |= value & 0xf; 6958 } 6959 6960 static char *x86_cpuid_get_vendor(Object *obj, Error **errp) 6961 { 6962 X86CPU *cpu = X86_CPU(obj); 6963 CPUX86State *env = &cpu->env; 6964 char *value; 6965 6966 value = g_malloc(CPUID_VENDOR_SZ + 1); 6967 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2, 6968 env->cpuid_vendor3); 6969 return value; 6970 } 6971 6972 static void x86_cpuid_set_vendor(Object *obj, const char *value, 6973 Error **errp) 6974 { 6975 X86CPU *cpu = X86_CPU(obj); 6976 CPUX86State *env = &cpu->env; 6977 int i; 6978 6979 if (strlen(value) != CPUID_VENDOR_SZ) { 6980 error_setg(errp, "value of property 'vendor' must consist of" 6981 " exactly " stringify(CPUID_VENDOR_SZ) " characters"); 6982 return; 6983 } 6984 6985 env->cpuid_vendor1 = 0; 6986 env->cpuid_vendor2 = 0; 6987 env->cpuid_vendor3 = 0; 6988 for (i = 0; i < 4; i++) { 6989 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i); 6990 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i); 6991 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i); 6992 } 6993 } 6994 6995 static char *x86_cpuid_get_model_id(Object *obj, Error **errp) 6996 { 6997 X86CPU *cpu = X86_CPU(obj); 6998 CPUX86State *env = &cpu->env; 6999 char *value; 7000 int i; 7001 7002 value = g_malloc(CPUID_MODEL_ID_SZ + 1); 7003 for (i = 0; i < CPUID_MODEL_ID_SZ; i++) { 7004 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3)); 7005 } 7006 value[CPUID_MODEL_ID_SZ] = '\0'; 7007 return value; 7008 } 7009 7010 static void x86_cpuid_set_model_id(Object *obj, const char *model_id, 7011 Error **errp) 7012 { 7013 X86CPU *cpu = X86_CPU(obj); 7014 CPUX86State *env = &cpu->env; 7015 int c, len, i; 7016 7017 if (model_id == NULL) { 7018 model_id = ""; 7019 } 7020 len = strlen(model_id); 7021 memset(env->cpuid_model, 0, CPUID_MODEL_ID_SZ); 7022 for (i = 0; i < 48; i++) { 7023 if (i >= len) { 7024 c = '\0'; 7025 } else { 7026 c = (uint8_t)model_id[i]; 7027 } 7028 env->cpuid_model[i >> 2] |= c << (8 * (i & 3)); 7029 } 7030 } 7031 7032 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name, 7033 void *opaque, Error **errp) 7034 { 7035 X86CPU *cpu = X86_CPU(obj); 7036 int64_t value; 7037 7038 value = cpu->env.tsc_khz * 1000; 7039 visit_type_int(v, name, &value, errp); 7040 } 7041 7042 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name, 7043 void *opaque, Error **errp) 7044 { 7045 X86CPU *cpu = X86_CPU(obj); 7046 const int64_t max = INT64_MAX; 7047 int64_t value; 7048 7049 if (!visit_type_int(v, name, &value, errp)) { 7050 return; 7051 } 7052 if (value < 0 || value > max) { 7053 error_setg(errp, "parameter '%s' can be at most %" PRId64, 7054 name ? name : "null", max); 7055 return; 7056 } 7057 7058 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000; 7059 } 7060 7061 /* Generic getter for "feature-words" and "filtered-features" properties */ 7062 static void x86_cpu_get_feature_words(Object *obj, Visitor *v, 7063 const char *name, void *opaque, 7064 Error **errp) 7065 { 7066 uint64_t *array = (uint64_t *)opaque; 7067 FeatureWord w; 7068 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { }; 7069 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { }; 7070 X86CPUFeatureWordInfoList *list = NULL; 7071 7072 for (w = 0; w < FEATURE_WORDS; w++) { 7073 FeatureWordInfo *wi = &feature_word_info[w]; 7074 /* 7075 * We didn't have MSR features when "feature-words" was 7076 * introduced. Therefore skipped other type entries. 7077 */ 7078 if (wi->type != CPUID_FEATURE_WORD) { 7079 continue; 7080 } 7081 X86CPUFeatureWordInfo *qwi = &word_infos[w]; 7082 qwi->cpuid_input_eax = wi->cpuid.eax; 7083 qwi->has_cpuid_input_ecx = wi->cpuid.needs_ecx; 7084 qwi->cpuid_input_ecx = wi->cpuid.ecx; 7085 qwi->cpuid_register = x86_reg_info_32[wi->cpuid.reg].qapi_enum; 7086 qwi->features = array[w]; 7087 7088 /* List will be in reverse order, but order shouldn't matter */ 7089 list_entries[w].next = list; 7090 list_entries[w].value = &word_infos[w]; 7091 list = &list_entries[w]; 7092 } 7093 7094 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp); 7095 } 7096 7097 /* Convert all '_' in a feature string option name to '-', to make feature 7098 * name conform to QOM property naming rule, which uses '-' instead of '_'. 7099 */ 7100 static inline void feat2prop(char *s) 7101 { 7102 while ((s = strchr(s, '_'))) { 7103 *s = '-'; 7104 } 7105 } 7106 7107 /* Return the feature property name for a feature flag bit */ 7108 static const char *x86_cpu_feature_name(FeatureWord w, int bitnr) 7109 { 7110 const char *name; 7111 /* XSAVE components are automatically enabled by other features, 7112 * so return the original feature name instead 7113 */ 7114 if (w == FEAT_XSAVE_XCR0_LO || w == FEAT_XSAVE_XCR0_HI) { 7115 int comp = (w == FEAT_XSAVE_XCR0_HI) ? bitnr + 32 : bitnr; 7116 7117 if (comp < ARRAY_SIZE(x86_ext_save_areas) && 7118 x86_ext_save_areas[comp].bits) { 7119 w = x86_ext_save_areas[comp].feature; 7120 bitnr = ctz32(x86_ext_save_areas[comp].bits); 7121 } 7122 } 7123 7124 assert(bitnr < 64); 7125 assert(w < FEATURE_WORDS); 7126 name = feature_word_info[w].feat_names[bitnr]; 7127 assert(bitnr < 32 || !(name && feature_word_info[w].type == CPUID_FEATURE_WORD)); 7128 return name; 7129 } 7130 7131 /* Compatibility hack to maintain legacy +-feat semantic, 7132 * where +-feat overwrites any feature set by 7133 * feat=on|feat even if the later is parsed after +-feat 7134 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled) 7135 */ 7136 static GList *plus_features, *minus_features; 7137 7138 static gint compare_string(gconstpointer a, gconstpointer b) 7139 { 7140 return g_strcmp0(a, b); 7141 } 7142 7143 /* Parse "+feature,-feature,feature=foo" CPU feature string 7144 */ 7145 static void x86_cpu_parse_featurestr(const char *typename, char *features, 7146 Error **errp) 7147 { 7148 char *featurestr; /* Single 'key=value" string being parsed */ 7149 static bool cpu_globals_initialized; 7150 bool ambiguous = false; 7151 7152 if (cpu_globals_initialized) { 7153 return; 7154 } 7155 cpu_globals_initialized = true; 7156 7157 if (!features) { 7158 return; 7159 } 7160 7161 for (featurestr = strtok(features, ","); 7162 featurestr; 7163 featurestr = strtok(NULL, ",")) { 7164 const char *name; 7165 const char *val = NULL; 7166 char *eq = NULL; 7167 char num[32]; 7168 GlobalProperty *prop; 7169 7170 /* Compatibility syntax: */ 7171 if (featurestr[0] == '+') { 7172 plus_features = g_list_append(plus_features, 7173 g_strdup(featurestr + 1)); 7174 continue; 7175 } else if (featurestr[0] == '-') { 7176 minus_features = g_list_append(minus_features, 7177 g_strdup(featurestr + 1)); 7178 continue; 7179 } 7180 7181 eq = strchr(featurestr, '='); 7182 if (eq) { 7183 *eq++ = 0; 7184 val = eq; 7185 } else { 7186 val = "on"; 7187 } 7188 7189 feat2prop(featurestr); 7190 name = featurestr; 7191 7192 if (g_list_find_custom(plus_features, name, compare_string)) { 7193 warn_report("Ambiguous CPU model string. " 7194 "Don't mix both \"+%s\" and \"%s=%s\"", 7195 name, name, val); 7196 ambiguous = true; 7197 } 7198 if (g_list_find_custom(minus_features, name, compare_string)) { 7199 warn_report("Ambiguous CPU model string. " 7200 "Don't mix both \"-%s\" and \"%s=%s\"", 7201 name, name, val); 7202 ambiguous = true; 7203 } 7204 7205 /* Special case: */ 7206 if (!strcmp(name, "tsc-freq")) { 7207 int ret; 7208 uint64_t tsc_freq; 7209 7210 ret = qemu_strtosz_metric(val, NULL, &tsc_freq); 7211 if (ret < 0 || tsc_freq > INT64_MAX) { 7212 error_setg(errp, "bad numerical value %s", val); 7213 return; 7214 } 7215 snprintf(num, sizeof(num), "%" PRId64, tsc_freq); 7216 val = num; 7217 name = "tsc-frequency"; 7218 } 7219 7220 prop = g_new0(typeof(*prop), 1); 7221 prop->driver = typename; 7222 prop->property = g_strdup(name); 7223 prop->value = g_strdup(val); 7224 qdev_prop_register_global(prop); 7225 } 7226 7227 if (ambiguous) { 7228 warn_report("Compatibility of ambiguous CPU model " 7229 "strings won't be kept on future QEMU versions"); 7230 } 7231 } 7232 7233 static bool x86_cpu_filter_features(X86CPU *cpu, bool verbose); 7234 7235 /* Build a list with the name of all features on a feature word array */ 7236 static void x86_cpu_list_feature_names(FeatureWordArray features, 7237 strList **list) 7238 { 7239 strList **tail = list; 7240 FeatureWord w; 7241 7242 for (w = 0; w < FEATURE_WORDS; w++) { 7243 uint64_t filtered = features[w]; 7244 int i; 7245 for (i = 0; i < 64; i++) { 7246 if (filtered & (1ULL << i)) { 7247 QAPI_LIST_APPEND(tail, g_strdup(x86_cpu_feature_name(w, i))); 7248 } 7249 } 7250 } 7251 } 7252 7253 static void x86_cpu_get_unavailable_features(Object *obj, Visitor *v, 7254 const char *name, void *opaque, 7255 Error **errp) 7256 { 7257 X86CPU *xc = X86_CPU(obj); 7258 strList *result = NULL; 7259 7260 x86_cpu_list_feature_names(xc->filtered_features, &result); 7261 visit_type_strList(v, "unavailable-features", &result, errp); 7262 } 7263 7264 /* Print all cpuid feature names in featureset 7265 */ 7266 static void listflags(GList *features) 7267 { 7268 size_t len = 0; 7269 GList *tmp; 7270 7271 for (tmp = features; tmp; tmp = tmp->next) { 7272 const char *name = tmp->data; 7273 if ((len + strlen(name) + 1) >= 75) { 7274 qemu_printf("\n"); 7275 len = 0; 7276 } 7277 qemu_printf("%s%s", len == 0 ? " " : " ", name); 7278 len += strlen(name) + 1; 7279 } 7280 qemu_printf("\n"); 7281 } 7282 7283 /* Sort alphabetically by type name, respecting X86CPUClass::ordering. */ 7284 static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b, gpointer d) 7285 { 7286 ObjectClass *class_a = (ObjectClass *)a; 7287 ObjectClass *class_b = (ObjectClass *)b; 7288 X86CPUClass *cc_a = X86_CPU_CLASS(class_a); 7289 X86CPUClass *cc_b = X86_CPU_CLASS(class_b); 7290 int ret; 7291 7292 if (cc_a->ordering != cc_b->ordering) { 7293 ret = cc_a->ordering - cc_b->ordering; 7294 } else { 7295 g_autofree char *name_a = x86_cpu_class_get_model_name(cc_a); 7296 g_autofree char *name_b = x86_cpu_class_get_model_name(cc_b); 7297 ret = strcmp(name_a, name_b); 7298 } 7299 return ret; 7300 } 7301 7302 static GSList *get_sorted_cpu_model_list(void) 7303 { 7304 GSList *list = object_class_get_list(TYPE_X86_CPU, false); 7305 list = g_slist_sort_with_data(list, x86_cpu_list_compare, NULL); 7306 return list; 7307 } 7308 7309 static char *x86_cpu_class_get_model_id(X86CPUClass *xc) 7310 { 7311 Object *obj = object_new_with_class(OBJECT_CLASS(xc)); 7312 char *r = object_property_get_str(obj, "model-id", &error_abort); 7313 object_unref(obj); 7314 return r; 7315 } 7316 7317 static char *x86_cpu_class_get_alias_of(X86CPUClass *cc) 7318 { 7319 X86CPUVersion version; 7320 7321 if (!cc->model || !cc->model->is_alias) { 7322 return NULL; 7323 } 7324 version = x86_cpu_model_resolve_version(cc->model); 7325 if (version <= 0) { 7326 return NULL; 7327 } 7328 return x86_cpu_versioned_model_name(cc->model->cpudef, version); 7329 } 7330 7331 static void x86_cpu_list_entry(gpointer data, gpointer user_data) 7332 { 7333 ObjectClass *oc = data; 7334 X86CPUClass *cc = X86_CPU_CLASS(oc); 7335 g_autofree char *name = x86_cpu_class_get_model_name(cc); 7336 g_autofree char *desc = g_strdup(cc->model_description); 7337 g_autofree char *alias_of = x86_cpu_class_get_alias_of(cc); 7338 g_autofree char *model_id = x86_cpu_class_get_model_id(cc); 7339 7340 if (!desc && alias_of) { 7341 if (cc->model && cc->model->version == CPU_VERSION_AUTO) { 7342 desc = g_strdup("(alias configured by machine type)"); 7343 } else { 7344 desc = g_strdup_printf("(alias of %s)", alias_of); 7345 } 7346 } 7347 if (!desc && cc->model && cc->model->note) { 7348 desc = g_strdup_printf("%s [%s]", model_id, cc->model->note); 7349 } 7350 if (!desc) { 7351 desc = g_strdup(model_id); 7352 } 7353 7354 if (cc->model && cc->model->cpudef->deprecation_note) { 7355 g_autofree char *olddesc = desc; 7356 desc = g_strdup_printf("%s (deprecated)", olddesc); 7357 } 7358 7359 qemu_printf(" %-20s %s\n", name, desc); 7360 } 7361 7362 static gint strcmp_wrap(gconstpointer a, gconstpointer b, gpointer d) 7363 { 7364 return strcmp(a, b); 7365 } 7366 7367 /* list available CPU models and flags */ 7368 static void x86_cpu_list(void) 7369 { 7370 int i, j; 7371 GSList *list; 7372 GList *names = NULL; 7373 7374 qemu_printf("Available CPUs:\n"); 7375 list = get_sorted_cpu_model_list(); 7376 g_slist_foreach(list, x86_cpu_list_entry, NULL); 7377 g_slist_free(list); 7378 7379 names = NULL; 7380 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) { 7381 FeatureWordInfo *fw = &feature_word_info[i]; 7382 for (j = 0; j < 64; j++) { 7383 if (fw->feat_names[j]) { 7384 names = g_list_append(names, (gpointer)fw->feat_names[j]); 7385 } 7386 } 7387 } 7388 7389 names = g_list_sort_with_data(names, strcmp_wrap, NULL); 7390 7391 qemu_printf("\nRecognized CPUID flags:\n"); 7392 listflags(names); 7393 qemu_printf("\n"); 7394 g_list_free(names); 7395 } 7396 7397 #ifndef CONFIG_USER_ONLY 7398 7399 /* Check for missing features that may prevent the CPU class from 7400 * running using the current machine and accelerator. 7401 */ 7402 static void x86_cpu_class_check_missing_features(X86CPUClass *xcc, 7403 strList **list) 7404 { 7405 strList **tail = list; 7406 X86CPU *xc; 7407 Error *err = NULL; 7408 7409 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) { 7410 QAPI_LIST_APPEND(tail, g_strdup("kvm")); 7411 return; 7412 } 7413 7414 xc = X86_CPU(object_new_with_class(OBJECT_CLASS(xcc))); 7415 7416 x86_cpu_expand_features(xc, &err); 7417 if (err) { 7418 /* Errors at x86_cpu_expand_features should never happen, 7419 * but in case it does, just report the model as not 7420 * runnable at all using the "type" property. 7421 */ 7422 QAPI_LIST_APPEND(tail, g_strdup("type")); 7423 error_free(err); 7424 } 7425 7426 x86_cpu_filter_features(xc, false); 7427 7428 x86_cpu_list_feature_names(xc->filtered_features, tail); 7429 7430 object_unref(OBJECT(xc)); 7431 } 7432 7433 static void x86_cpu_definition_entry(gpointer data, gpointer user_data) 7434 { 7435 ObjectClass *oc = data; 7436 X86CPUClass *cc = X86_CPU_CLASS(oc); 7437 CpuDefinitionInfoList **cpu_list = user_data; 7438 CpuDefinitionInfo *info; 7439 7440 info = g_malloc0(sizeof(*info)); 7441 info->name = x86_cpu_class_get_model_name(cc); 7442 x86_cpu_class_check_missing_features(cc, &info->unavailable_features); 7443 info->has_unavailable_features = true; 7444 info->q_typename = g_strdup(object_class_get_name(oc)); 7445 info->migration_safe = cc->migration_safe; 7446 info->has_migration_safe = true; 7447 info->q_static = cc->static_model; 7448 if (cc->model && cc->model->cpudef->deprecation_note) { 7449 info->deprecated = true; 7450 } else { 7451 info->deprecated = false; 7452 } 7453 /* 7454 * Old machine types won't report aliases, so that alias translation 7455 * doesn't break compatibility with previous QEMU versions. 7456 */ 7457 if (default_cpu_version != CPU_VERSION_LEGACY) { 7458 info->alias_of = x86_cpu_class_get_alias_of(cc); 7459 } 7460 7461 QAPI_LIST_PREPEND(*cpu_list, info); 7462 } 7463 7464 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) 7465 { 7466 CpuDefinitionInfoList *cpu_list = NULL; 7467 GSList *list = get_sorted_cpu_model_list(); 7468 g_slist_foreach(list, x86_cpu_definition_entry, &cpu_list); 7469 g_slist_free(list); 7470 return cpu_list; 7471 } 7472 7473 #endif /* !CONFIG_USER_ONLY */ 7474 7475 uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w) 7476 { 7477 FeatureWordInfo *wi = &feature_word_info[w]; 7478 uint64_t r = 0; 7479 uint64_t unavail = 0; 7480 7481 if (kvm_enabled()) { 7482 switch (wi->type) { 7483 case CPUID_FEATURE_WORD: 7484 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid.eax, 7485 wi->cpuid.ecx, 7486 wi->cpuid.reg); 7487 break; 7488 case MSR_FEATURE_WORD: 7489 r = kvm_arch_get_supported_msr_feature(kvm_state, 7490 wi->msr.index); 7491 break; 7492 } 7493 } else if (hvf_enabled()) { 7494 if (wi->type != CPUID_FEATURE_WORD) { 7495 return 0; 7496 } 7497 r = hvf_get_supported_cpuid(wi->cpuid.eax, 7498 wi->cpuid.ecx, 7499 wi->cpuid.reg); 7500 } else if (tcg_enabled()) { 7501 r = wi->tcg_features; 7502 } else { 7503 return ~0; 7504 } 7505 7506 switch (w) { 7507 #ifndef TARGET_X86_64 7508 case FEAT_8000_0001_EDX: 7509 /* 7510 * 32-bit TCG can emulate 64-bit compatibility mode. If there is no 7511 * way for userspace to get out of its 32-bit jail, we can leave 7512 * the LM bit set. 7513 */ 7514 unavail = tcg_enabled() 7515 ? CPUID_EXT2_LM & ~CPUID_EXT2_KERNEL_FEATURES 7516 : CPUID_EXT2_LM; 7517 break; 7518 #endif 7519 7520 case FEAT_8000_0007_EBX: 7521 if (cpu && !IS_AMD_CPU(&cpu->env)) { 7522 /* Disable AMD machine check architecture for Intel CPU. */ 7523 unavail = ~0; 7524 } 7525 break; 7526 7527 case FEAT_7_0_EBX: 7528 #ifndef CONFIG_USER_ONLY 7529 if (!check_sgx_support()) { 7530 unavail = CPUID_7_0_EBX_SGX; 7531 } 7532 #endif 7533 break; 7534 case FEAT_7_0_ECX: 7535 #ifndef CONFIG_USER_ONLY 7536 if (!check_sgx_support()) { 7537 unavail = CPUID_7_0_ECX_SGX_LC; 7538 } 7539 #endif 7540 break; 7541 7542 default: 7543 break; 7544 } 7545 7546 r &= ~unavail; 7547 if (cpu && cpu->migratable) { 7548 r &= x86_cpu_get_migratable_flags(cpu, w); 7549 } 7550 return r; 7551 } 7552 7553 static void x86_cpu_get_supported_cpuid(uint32_t func, uint32_t index, 7554 uint32_t *eax, uint32_t *ebx, 7555 uint32_t *ecx, uint32_t *edx) 7556 { 7557 if (kvm_enabled()) { 7558 *eax = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EAX); 7559 *ebx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EBX); 7560 *ecx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_ECX); 7561 *edx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EDX); 7562 } else if (hvf_enabled()) { 7563 *eax = hvf_get_supported_cpuid(func, index, R_EAX); 7564 *ebx = hvf_get_supported_cpuid(func, index, R_EBX); 7565 *ecx = hvf_get_supported_cpuid(func, index, R_ECX); 7566 *edx = hvf_get_supported_cpuid(func, index, R_EDX); 7567 } else { 7568 *eax = 0; 7569 *ebx = 0; 7570 *ecx = 0; 7571 *edx = 0; 7572 } 7573 } 7574 7575 static void x86_cpu_get_cache_cpuid(uint32_t func, uint32_t index, 7576 uint32_t *eax, uint32_t *ebx, 7577 uint32_t *ecx, uint32_t *edx) 7578 { 7579 uint32_t level, unused; 7580 7581 /* Only return valid host leaves. */ 7582 switch (func) { 7583 case 2: 7584 case 4: 7585 host_cpuid(0, 0, &level, &unused, &unused, &unused); 7586 break; 7587 case 0x80000005: 7588 case 0x80000006: 7589 case 0x8000001d: 7590 host_cpuid(0x80000000, 0, &level, &unused, &unused, &unused); 7591 break; 7592 default: 7593 return; 7594 } 7595 7596 if (func > level) { 7597 *eax = 0; 7598 *ebx = 0; 7599 *ecx = 0; 7600 *edx = 0; 7601 } else { 7602 host_cpuid(func, index, eax, ebx, ecx, edx); 7603 } 7604 } 7605 7606 /* 7607 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 7608 */ 7609 void x86_cpu_apply_props(X86CPU *cpu, PropValue *props) 7610 { 7611 PropValue *pv; 7612 for (pv = props; pv->prop; pv++) { 7613 if (!pv->value) { 7614 continue; 7615 } 7616 object_property_parse(OBJECT(cpu), pv->prop, pv->value, 7617 &error_abort); 7618 } 7619 } 7620 7621 /* 7622 * Apply properties for the CPU model version specified in model. 7623 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 7624 */ 7625 7626 static void x86_cpu_apply_version_props(X86CPU *cpu, const X86CPUModel *model) 7627 { 7628 const X86CPUVersionDefinition *vdef; 7629 X86CPUVersion version = x86_cpu_model_resolve_version(model); 7630 7631 if (version == CPU_VERSION_LEGACY) { 7632 return; 7633 } 7634 7635 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) { 7636 PropValue *p; 7637 7638 for (p = vdef->props; p && p->prop; p++) { 7639 object_property_parse(OBJECT(cpu), p->prop, p->value, 7640 &error_abort); 7641 } 7642 7643 if (vdef->version == version) { 7644 break; 7645 } 7646 } 7647 7648 /* 7649 * If we reached the end of the list, version number was invalid 7650 */ 7651 assert(vdef->version == version); 7652 } 7653 7654 static const CPUCaches *x86_cpu_get_versioned_cache_info(X86CPU *cpu, 7655 const X86CPUModel *model) 7656 { 7657 const X86CPUVersionDefinition *vdef; 7658 X86CPUVersion version = x86_cpu_model_resolve_version(model); 7659 const CPUCaches *cache_info = model->cpudef->cache_info; 7660 7661 if (version == CPU_VERSION_LEGACY) { 7662 return cache_info; 7663 } 7664 7665 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) { 7666 if (vdef->cache_info) { 7667 cache_info = vdef->cache_info; 7668 } 7669 7670 if (vdef->version == version) { 7671 break; 7672 } 7673 } 7674 7675 assert(vdef->version == version); 7676 return cache_info; 7677 } 7678 7679 /* 7680 * Load data from X86CPUDefinition into a X86CPU object. 7681 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 7682 */ 7683 static void x86_cpu_load_model(X86CPU *cpu, const X86CPUModel *model) 7684 { 7685 const X86CPUDefinition *def = model->cpudef; 7686 CPUX86State *env = &cpu->env; 7687 FeatureWord w; 7688 7689 /*NOTE: any property set by this function should be returned by 7690 * x86_cpu_static_props(), so static expansion of 7691 * query-cpu-model-expansion is always complete. 7692 */ 7693 7694 /* CPU models only set _minimum_ values for level/xlevel: */ 7695 object_property_set_uint(OBJECT(cpu), "min-level", def->level, 7696 &error_abort); 7697 object_property_set_uint(OBJECT(cpu), "min-xlevel", def->xlevel, 7698 &error_abort); 7699 7700 object_property_set_int(OBJECT(cpu), "family", def->family, &error_abort); 7701 object_property_set_int(OBJECT(cpu), "model", def->model, &error_abort); 7702 object_property_set_int(OBJECT(cpu), "stepping", def->stepping, 7703 &error_abort); 7704 object_property_set_str(OBJECT(cpu), "model-id", def->model_id, 7705 &error_abort); 7706 for (w = 0; w < FEATURE_WORDS; w++) { 7707 env->features[w] = def->features[w]; 7708 } 7709 7710 /* legacy-cache defaults to 'off' if CPU model provides cache info */ 7711 cpu->legacy_cache = !x86_cpu_get_versioned_cache_info(cpu, model); 7712 7713 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR; 7714 7715 /* sysenter isn't supported in compatibility mode on AMD, 7716 * syscall isn't supported in compatibility mode on Intel. 7717 * Normally we advertise the actual CPU vendor, but you can 7718 * override this using the 'vendor' property if you want to use 7719 * KVM's sysenter/syscall emulation in compatibility mode and 7720 * when doing cross vendor migration 7721 */ 7722 7723 /* 7724 * vendor property is set here but then overloaded with the 7725 * host cpu vendor for KVM and HVF. 7726 */ 7727 object_property_set_str(OBJECT(cpu), "vendor", def->vendor, &error_abort); 7728 7729 object_property_set_uint(OBJECT(cpu), "avx10-version", def->avx10_version, 7730 &error_abort); 7731 7732 x86_cpu_apply_version_props(cpu, model); 7733 7734 /* 7735 * Properties in versioned CPU model are not user specified features. 7736 * We can simply clear env->user_features here since it will be filled later 7737 * in x86_cpu_expand_features() based on plus_features and minus_features. 7738 */ 7739 memset(&env->user_features, 0, sizeof(env->user_features)); 7740 } 7741 7742 static const gchar *x86_gdb_arch_name(CPUState *cs) 7743 { 7744 #ifdef TARGET_X86_64 7745 return "i386:x86-64"; 7746 #else 7747 return "i386"; 7748 #endif 7749 } 7750 7751 static void x86_cpu_cpudef_class_init(ObjectClass *oc, const void *data) 7752 { 7753 const X86CPUModel *model = data; 7754 X86CPUClass *xcc = X86_CPU_CLASS(oc); 7755 CPUClass *cc = CPU_CLASS(oc); 7756 7757 xcc->model = model; 7758 xcc->migration_safe = true; 7759 cc->deprecation_note = model->cpudef->deprecation_note; 7760 } 7761 7762 static void x86_register_cpu_model_type(const char *name, X86CPUModel *model) 7763 { 7764 g_autofree char *typename = x86_cpu_type_name(name); 7765 TypeInfo ti = { 7766 .name = typename, 7767 .parent = TYPE_X86_CPU, 7768 .class_init = x86_cpu_cpudef_class_init, 7769 .class_data = model, 7770 }; 7771 7772 type_register_static(&ti); 7773 } 7774 7775 7776 /* 7777 * register builtin_x86_defs; 7778 * "max", "base" and subclasses ("host") are not registered here. 7779 * See x86_cpu_register_types for all model registrations. 7780 */ 7781 static void x86_register_cpudef_types(const X86CPUDefinition *def) 7782 { 7783 X86CPUModel *m; 7784 const X86CPUVersionDefinition *vdef; 7785 7786 /* AMD aliases are handled at runtime based on CPUID vendor, so 7787 * they shouldn't be set on the CPU model table. 7788 */ 7789 assert(!(def->features[FEAT_8000_0001_EDX] & CPUID_EXT2_AMD_ALIASES)); 7790 /* catch mistakes instead of silently truncating model_id when too long */ 7791 assert(def->model_id && strlen(def->model_id) <= 48); 7792 7793 /* Unversioned model: */ 7794 m = g_new0(X86CPUModel, 1); 7795 m->cpudef = def; 7796 m->version = CPU_VERSION_AUTO; 7797 m->is_alias = true; 7798 x86_register_cpu_model_type(def->name, m); 7799 7800 /* Versioned models: */ 7801 7802 for (vdef = x86_cpu_def_get_versions(def); vdef->version; vdef++) { 7803 g_autofree char *name = 7804 x86_cpu_versioned_model_name(def, vdef->version); 7805 7806 m = g_new0(X86CPUModel, 1); 7807 m->cpudef = def; 7808 m->version = vdef->version; 7809 m->note = vdef->note; 7810 x86_register_cpu_model_type(name, m); 7811 7812 if (vdef->alias) { 7813 X86CPUModel *am = g_new0(X86CPUModel, 1); 7814 am->cpudef = def; 7815 am->version = vdef->version; 7816 am->is_alias = true; 7817 x86_register_cpu_model_type(vdef->alias, am); 7818 } 7819 } 7820 7821 } 7822 7823 uint32_t cpu_x86_virtual_addr_width(CPUX86State *env) 7824 { 7825 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57) { 7826 return 57; /* 57 bits virtual */ 7827 } else { 7828 return 48; /* 48 bits virtual */ 7829 } 7830 } 7831 7832 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, 7833 uint32_t *eax, uint32_t *ebx, 7834 uint32_t *ecx, uint32_t *edx) 7835 { 7836 X86CPU *cpu = env_archcpu(env); 7837 CPUState *cs = env_cpu(env); 7838 uint32_t limit; 7839 uint32_t signature[3]; 7840 X86CPUTopoInfo *topo_info = &env->topo_info; 7841 uint32_t threads_per_pkg; 7842 7843 threads_per_pkg = x86_threads_per_pkg(topo_info); 7844 7845 /* Calculate & apply limits for different index ranges */ 7846 if (index >= 0xC0000000) { 7847 limit = env->cpuid_xlevel2; 7848 } else if (index >= 0x80000000) { 7849 limit = env->cpuid_xlevel; 7850 } else if (index >= 0x40000000) { 7851 limit = 0x40000001; 7852 } else { 7853 limit = env->cpuid_level; 7854 } 7855 7856 if (index > limit) { 7857 /* Intel documentation states that invalid EAX input will 7858 * return the same information as EAX=cpuid_level 7859 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID) 7860 */ 7861 index = env->cpuid_level; 7862 } 7863 7864 switch(index) { 7865 case 0: 7866 *eax = env->cpuid_level; 7867 *ebx = env->cpuid_vendor1; 7868 *edx = env->cpuid_vendor2; 7869 *ecx = env->cpuid_vendor3; 7870 break; 7871 case 1: 7872 *eax = env->cpuid_version; 7873 *ebx = (cpu->apic_id << 24) | 7874 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */ 7875 *ecx = env->features[FEAT_1_ECX]; 7876 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) { 7877 *ecx |= CPUID_EXT_OSXSAVE; 7878 } 7879 *edx = env->features[FEAT_1_EDX]; 7880 if (threads_per_pkg > 1) { 7881 uint32_t num; 7882 7883 /* 7884 * For CPUID.01H.EBX[Bits 23-16], AMD requires logical processor 7885 * count, but Intel needs maximum number of addressable IDs for 7886 * logical processors per package. 7887 */ 7888 if ((IS_INTEL_CPU(env) || IS_ZHAOXIN_CPU(env))) { 7889 num = 1 << apicid_pkg_offset(topo_info); 7890 } else { 7891 num = threads_per_pkg; 7892 } 7893 7894 /* Fixup overflow: max value for bits 23-16 is 255. */ 7895 *ebx |= MIN(num, 255) << 16; 7896 } 7897 break; 7898 case 2: { /* cache info: needed for Pentium Pro compatibility */ 7899 const CPUCaches *caches; 7900 7901 if (env->enable_legacy_cpuid2_cache) { 7902 caches = &legacy_intel_cpuid2_cache_info; 7903 } else if (env->enable_legacy_vendor_cache) { 7904 caches = &legacy_intel_cache_info; 7905 } else { 7906 caches = &env->cache_info; 7907 } 7908 7909 if (cpu->cache_info_passthrough) { 7910 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 7911 break; 7912 } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { 7913 *eax = *ebx = *ecx = *edx = 0; 7914 break; 7915 } 7916 encode_cache_cpuid2(cpu, caches, eax, ebx, ecx, edx); 7917 break; 7918 } 7919 case 4: { 7920 const CPUCaches *caches; 7921 7922 if (env->enable_legacy_vendor_cache) { 7923 caches = &legacy_intel_cache_info; 7924 } else { 7925 caches = &env->cache_info; 7926 } 7927 7928 /* cache info: needed for Core compatibility */ 7929 if (cpu->cache_info_passthrough) { 7930 x86_cpu_get_cache_cpuid(index, count, eax, ebx, ecx, edx); 7931 /* 7932 * QEMU has its own number of cores/logical cpus, 7933 * set 24..14, 31..26 bit to configured values 7934 */ 7935 if (*eax & 31) { 7936 int host_vcpus_per_cache = 1 + ((*eax & 0x3FFC000) >> 14); 7937 7938 *eax &= ~0xFC000000; 7939 *eax |= MIN(max_core_ids_in_package(topo_info), 63) << 26; 7940 if (host_vcpus_per_cache > threads_per_pkg) { 7941 *eax &= ~0x3FFC000; 7942 7943 /* Share the cache at package level. */ 7944 *eax |= MIN(max_thread_ids_for_cache(topo_info, 7945 CPU_TOPOLOGY_LEVEL_SOCKET), 4095) << 14; 7946 } 7947 } 7948 } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { 7949 *eax = *ebx = *ecx = *edx = 0; 7950 } else { 7951 *eax = 0; 7952 7953 switch (count) { 7954 case 0: /* L1 dcache info */ 7955 encode_cache_cpuid4(caches->l1d_cache, topo_info, 7956 eax, ebx, ecx, edx); 7957 if (!cpu->l1_cache_per_core) { 7958 *eax &= ~MAKE_64BIT_MASK(14, 12); 7959 } 7960 break; 7961 case 1: /* L1 icache info */ 7962 encode_cache_cpuid4(caches->l1i_cache, topo_info, 7963 eax, ebx, ecx, edx); 7964 if (!cpu->l1_cache_per_core) { 7965 *eax &= ~MAKE_64BIT_MASK(14, 12); 7966 } 7967 break; 7968 case 2: /* L2 cache info */ 7969 encode_cache_cpuid4(caches->l2_cache, topo_info, 7970 eax, ebx, ecx, edx); 7971 break; 7972 case 3: /* L3 cache info */ 7973 if (cpu->enable_l3_cache) { 7974 encode_cache_cpuid4(caches->l3_cache, topo_info, 7975 eax, ebx, ecx, edx); 7976 break; 7977 } 7978 /* fall through */ 7979 default: /* end of info */ 7980 *eax = *ebx = *ecx = *edx = 0; 7981 break; 7982 } 7983 } 7984 break; 7985 } 7986 case 5: 7987 /* MONITOR/MWAIT Leaf */ 7988 *eax = cpu->mwait.eax; /* Smallest monitor-line size in bytes */ 7989 *ebx = cpu->mwait.ebx; /* Largest monitor-line size in bytes */ 7990 *ecx = cpu->mwait.ecx; /* flags */ 7991 *edx = cpu->mwait.edx; /* mwait substates */ 7992 break; 7993 case 6: 7994 /* Thermal and Power Leaf */ 7995 *eax = env->features[FEAT_6_EAX]; 7996 *ebx = 0; 7997 *ecx = 0; 7998 *edx = 0; 7999 break; 8000 case 7: 8001 /* Structured Extended Feature Flags Enumeration Leaf */ 8002 if (count == 0) { 8003 /* Maximum ECX value for sub-leaves */ 8004 *eax = env->cpuid_level_func7; 8005 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */ 8006 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */ 8007 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) { 8008 *ecx |= CPUID_7_0_ECX_OSPKE; 8009 } 8010 *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */ 8011 } else if (count == 1) { 8012 *eax = env->features[FEAT_7_1_EAX]; 8013 *ecx = env->features[FEAT_7_1_ECX]; 8014 *edx = env->features[FEAT_7_1_EDX]; 8015 *ebx = 0; 8016 } else if (count == 2) { 8017 *edx = env->features[FEAT_7_2_EDX]; 8018 *eax = 0; 8019 *ebx = 0; 8020 *ecx = 0; 8021 } else { 8022 *eax = 0; 8023 *ebx = 0; 8024 *ecx = 0; 8025 *edx = 0; 8026 } 8027 break; 8028 case 9: 8029 /* Direct Cache Access Information Leaf */ 8030 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */ 8031 *ebx = 0; 8032 *ecx = 0; 8033 *edx = 0; 8034 break; 8035 case 0xA: 8036 /* Architectural Performance Monitoring Leaf */ 8037 if (cpu->enable_pmu) { 8038 x86_cpu_get_supported_cpuid(0xA, count, eax, ebx, ecx, edx); 8039 } else { 8040 *eax = 0; 8041 *ebx = 0; 8042 *ecx = 0; 8043 *edx = 0; 8044 } 8045 break; 8046 case 0xB: 8047 /* Extended Topology Enumeration Leaf */ 8048 if (!cpu->enable_cpuid_0xb) { 8049 *eax = *ebx = *ecx = *edx = 0; 8050 break; 8051 } 8052 8053 *ecx = count & 0xff; 8054 *edx = cpu->apic_id; 8055 8056 switch (count) { 8057 case 0: 8058 *eax = apicid_core_offset(topo_info); 8059 *ebx = topo_info->threads_per_core; 8060 *ecx |= CPUID_B_ECX_TOPO_LEVEL_SMT << 8; 8061 break; 8062 case 1: 8063 *eax = apicid_pkg_offset(topo_info); 8064 *ebx = threads_per_pkg; 8065 *ecx |= CPUID_B_ECX_TOPO_LEVEL_CORE << 8; 8066 break; 8067 default: 8068 *eax = 0; 8069 *ebx = 0; 8070 *ecx |= CPUID_B_ECX_TOPO_LEVEL_INVALID << 8; 8071 } 8072 8073 assert(!(*eax & ~0x1f)); 8074 *ebx &= 0xffff; /* The count doesn't need to be reliable. */ 8075 break; 8076 case 0xD: { 8077 /* Processor Extended State */ 8078 *eax = 0; 8079 *ebx = 0; 8080 *ecx = 0; 8081 *edx = 0; 8082 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { 8083 break; 8084 } 8085 8086 if (count == 0) { 8087 *ecx = xsave_area_size(x86_cpu_xsave_xcr0_components(cpu), false); 8088 *eax = env->features[FEAT_XSAVE_XCR0_LO]; 8089 *edx = env->features[FEAT_XSAVE_XCR0_HI]; 8090 /* 8091 * The initial value of xcr0 and ebx == 0, On host without kvm 8092 * commit 412a3c41(e.g., CentOS 6), the ebx's value always == 0 8093 * even through guest update xcr0, this will crash some legacy guest 8094 * (e.g., CentOS 6), So set ebx == ecx to workaround it. 8095 */ 8096 *ebx = kvm_enabled() ? *ecx : xsave_area_size(env->xcr0, false); 8097 } else if (count == 1) { 8098 uint64_t xstate = x86_cpu_xsave_xcr0_components(cpu) | 8099 x86_cpu_xsave_xss_components(cpu); 8100 8101 *eax = env->features[FEAT_XSAVE]; 8102 *ebx = xsave_area_size(xstate, true); 8103 *ecx = env->features[FEAT_XSAVE_XSS_LO]; 8104 *edx = env->features[FEAT_XSAVE_XSS_HI]; 8105 if (kvm_enabled() && cpu->enable_pmu && 8106 (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR) && 8107 (*eax & CPUID_XSAVE_XSAVES)) { 8108 *ecx |= XSTATE_ARCH_LBR_MASK; 8109 } else { 8110 *ecx &= ~XSTATE_ARCH_LBR_MASK; 8111 } 8112 } else if (count == 0xf && cpu->enable_pmu 8113 && (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) { 8114 x86_cpu_get_supported_cpuid(0xD, count, eax, ebx, ecx, edx); 8115 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) { 8116 const ExtSaveArea *esa = &x86_ext_save_areas[count]; 8117 8118 if (x86_cpu_xsave_xcr0_components(cpu) & (1ULL << count)) { 8119 *eax = esa->size; 8120 *ebx = esa->offset; 8121 *ecx = esa->ecx & 8122 (ESA_FEATURE_ALIGN64_MASK | ESA_FEATURE_XFD_MASK); 8123 } else if (x86_cpu_xsave_xss_components(cpu) & (1ULL << count)) { 8124 *eax = esa->size; 8125 *ebx = 0; 8126 *ecx = 1; 8127 } 8128 } 8129 break; 8130 } 8131 case 0x12: 8132 #ifndef CONFIG_USER_ONLY 8133 if (!kvm_enabled() || 8134 !(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX)) { 8135 *eax = *ebx = *ecx = *edx = 0; 8136 break; 8137 } 8138 8139 /* 8140 * SGX sub-leafs CPUID.0x12.{0x2..N} enumerate EPC sections. Retrieve 8141 * the EPC properties, e.g. confidentiality and integrity, from the 8142 * host's first EPC section, i.e. assume there is one EPC section or 8143 * that all EPC sections have the same security properties. 8144 */ 8145 if (count > 1) { 8146 uint64_t epc_addr, epc_size; 8147 8148 if (sgx_epc_get_section(count - 2, &epc_addr, &epc_size)) { 8149 *eax = *ebx = *ecx = *edx = 0; 8150 break; 8151 } 8152 host_cpuid(index, 2, eax, ebx, ecx, edx); 8153 *eax = (uint32_t)(epc_addr & 0xfffff000) | 0x1; 8154 *ebx = (uint32_t)(epc_addr >> 32); 8155 *ecx = (uint32_t)(epc_size & 0xfffff000) | (*ecx & 0xf); 8156 *edx = (uint32_t)(epc_size >> 32); 8157 break; 8158 } 8159 8160 /* 8161 * SGX sub-leafs CPUID.0x12.{0x0,0x1} are heavily dependent on hardware 8162 * and KVM, i.e. QEMU cannot emulate features to override what KVM 8163 * supports. Features can be further restricted by userspace, but not 8164 * made more permissive. 8165 */ 8166 x86_cpu_get_supported_cpuid(0x12, count, eax, ebx, ecx, edx); 8167 8168 if (count == 0) { 8169 *eax &= env->features[FEAT_SGX_12_0_EAX]; 8170 *ebx &= env->features[FEAT_SGX_12_0_EBX]; 8171 } else { 8172 *eax &= env->features[FEAT_SGX_12_1_EAX]; 8173 *ebx &= 0; /* ebx reserve */ 8174 *ecx &= env->features[FEAT_XSAVE_XCR0_LO]; 8175 *edx &= env->features[FEAT_XSAVE_XCR0_HI]; 8176 8177 /* FP and SSE are always allowed regardless of XSAVE/XCR0. */ 8178 *ecx |= XSTATE_FP_MASK | XSTATE_SSE_MASK; 8179 8180 /* Access to PROVISIONKEY requires additional credentials. */ 8181 if ((*eax & (1U << 4)) && 8182 !kvm_enable_sgx_provisioning(cs->kvm_state)) { 8183 *eax &= ~(1U << 4); 8184 } 8185 } 8186 #endif 8187 break; 8188 case 0x14: { 8189 /* Intel Processor Trace Enumeration */ 8190 *eax = 0; 8191 *ebx = 0; 8192 *ecx = 0; 8193 *edx = 0; 8194 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) || 8195 !kvm_enabled()) { 8196 break; 8197 } 8198 8199 /* 8200 * If these are changed, they should stay in sync with 8201 * x86_cpu_filter_features(). 8202 */ 8203 if (count == 0) { 8204 *eax = INTEL_PT_MAX_SUBLEAF; 8205 *ebx = INTEL_PT_MINIMAL_EBX; 8206 *ecx = INTEL_PT_MINIMAL_ECX; 8207 if (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP) { 8208 *ecx |= CPUID_14_0_ECX_LIP; 8209 } 8210 } else if (count == 1) { 8211 *eax = INTEL_PT_MTC_BITMAP | INTEL_PT_ADDR_RANGES_NUM; 8212 *ebx = INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP; 8213 } 8214 break; 8215 } 8216 case 0x1C: 8217 if (cpu->enable_pmu && (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) { 8218 x86_cpu_get_supported_cpuid(0x1C, 0, eax, ebx, ecx, edx); 8219 *edx = 0; 8220 } 8221 break; 8222 case 0x1D: { 8223 /* AMX TILE, for now hardcoded for Sapphire Rapids*/ 8224 *eax = 0; 8225 *ebx = 0; 8226 *ecx = 0; 8227 *edx = 0; 8228 if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) { 8229 break; 8230 } 8231 8232 if (count == 0) { 8233 /* Highest numbered palette subleaf */ 8234 *eax = INTEL_AMX_TILE_MAX_SUBLEAF; 8235 } else if (count == 1) { 8236 *eax = INTEL_AMX_TOTAL_TILE_BYTES | 8237 (INTEL_AMX_BYTES_PER_TILE << 16); 8238 *ebx = INTEL_AMX_BYTES_PER_ROW | (INTEL_AMX_TILE_MAX_NAMES << 16); 8239 *ecx = INTEL_AMX_TILE_MAX_ROWS; 8240 } 8241 break; 8242 } 8243 case 0x1E: { 8244 /* AMX TMUL, for now hardcoded for Sapphire Rapids */ 8245 *eax = 0; 8246 *ebx = 0; 8247 *ecx = 0; 8248 *edx = 0; 8249 if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) { 8250 break; 8251 } 8252 8253 if (count == 0) { 8254 /* Highest numbered palette subleaf */ 8255 *ebx = INTEL_AMX_TMUL_MAX_K | (INTEL_AMX_TMUL_MAX_N << 8); 8256 } 8257 break; 8258 } 8259 case 0x1F: 8260 /* V2 Extended Topology Enumeration Leaf */ 8261 if (!x86_has_cpuid_0x1f(cpu)) { 8262 *eax = *ebx = *ecx = *edx = 0; 8263 break; 8264 } 8265 8266 encode_topo_cpuid1f(env, count, topo_info, eax, ebx, ecx, edx); 8267 break; 8268 case 0x24: { 8269 *eax = 0; 8270 *ebx = 0; 8271 *ecx = 0; 8272 *edx = 0; 8273 if ((env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) && count == 0) { 8274 *ebx = env->features[FEAT_24_0_EBX] | env->avx10_version; 8275 } 8276 break; 8277 } 8278 case 0x40000000: 8279 /* 8280 * CPUID code in kvm_arch_init_vcpu() ignores stuff 8281 * set here, but we restrict to TCG none the less. 8282 */ 8283 if (tcg_enabled() && cpu->expose_tcg) { 8284 memcpy(signature, "TCGTCGTCGTCG", 12); 8285 *eax = 0x40000001; 8286 *ebx = signature[0]; 8287 *ecx = signature[1]; 8288 *edx = signature[2]; 8289 } else { 8290 *eax = 0; 8291 *ebx = 0; 8292 *ecx = 0; 8293 *edx = 0; 8294 } 8295 break; 8296 case 0x40000001: 8297 *eax = 0; 8298 *ebx = 0; 8299 *ecx = 0; 8300 *edx = 0; 8301 break; 8302 case 0x80000000: 8303 *eax = env->cpuid_xlevel; 8304 8305 if (cpu->vendor_cpuid_only_v2 && 8306 (IS_INTEL_CPU(env) || IS_ZHAOXIN_CPU(env))) { 8307 *ebx = *ecx = *edx = 0; 8308 } else { 8309 *ebx = env->cpuid_vendor1; 8310 *edx = env->cpuid_vendor2; 8311 *ecx = env->cpuid_vendor3; 8312 } 8313 break; 8314 case 0x80000001: 8315 *eax = env->cpuid_version; 8316 *ebx = 0; 8317 *ecx = env->features[FEAT_8000_0001_ECX]; 8318 *edx = env->features[FEAT_8000_0001_EDX]; 8319 8320 if (tcg_enabled() && IS_INTEL_CPU(env) && 8321 !(env->hflags & HF_LMA_MASK)) { 8322 *edx &= ~CPUID_EXT2_SYSCALL; 8323 } 8324 break; 8325 case 0x80000002: 8326 case 0x80000003: 8327 case 0x80000004: 8328 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0]; 8329 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1]; 8330 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2]; 8331 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3]; 8332 break; 8333 case 0x80000005: { 8334 /* cache info (L1 cache/TLB Associativity Field) */ 8335 const CPUCaches *caches; 8336 8337 if (env->enable_legacy_vendor_cache) { 8338 caches = &legacy_amd_cache_info; 8339 } else { 8340 caches = &env->cache_info; 8341 } 8342 8343 if (cpu->cache_info_passthrough) { 8344 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 8345 break; 8346 } 8347 8348 if (cpu->vendor_cpuid_only_v2 && IS_INTEL_CPU(env)) { 8349 *eax = *ebx = *ecx = *edx = 0; 8350 break; 8351 } 8352 8353 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | 8354 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES); 8355 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | 8356 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES); 8357 *ecx = encode_cache_cpuid80000005(caches->l1d_cache); 8358 *edx = encode_cache_cpuid80000005(caches->l1i_cache); 8359 break; 8360 } 8361 case 0x80000006: { /* cache info (L2 cache/TLB/L3 cache) */ 8362 const CPUCaches *caches; 8363 8364 if (env->enable_legacy_vendor_cache) { 8365 caches = &legacy_amd_cache_info; 8366 } else { 8367 caches = &env->cache_info; 8368 } 8369 8370 if (cpu->cache_info_passthrough) { 8371 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 8372 break; 8373 } 8374 8375 if (cpu->vendor_cpuid_only_v2 && 8376 (IS_INTEL_CPU(env) || IS_ZHAOXIN_CPU(env))) { 8377 *eax = *ebx = 0; 8378 encode_cache_cpuid80000006(caches->l2_cache, 8379 NULL, ecx, edx); 8380 break; 8381 } 8382 8383 *eax = (X86_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | 8384 (L2_DTLB_2M_ENTRIES << 16) | 8385 (X86_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | 8386 (L2_ITLB_2M_ENTRIES); 8387 *ebx = (X86_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | 8388 (L2_DTLB_4K_ENTRIES << 16) | 8389 (X86_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | 8390 (L2_ITLB_4K_ENTRIES); 8391 8392 encode_cache_cpuid80000006(caches->l2_cache, 8393 cpu->enable_l3_cache ? 8394 caches->l3_cache : NULL, 8395 ecx, edx); 8396 break; 8397 } 8398 case 0x80000007: 8399 *eax = 0; 8400 if (cpu->vendor_cpuid_only_v2 && IS_INTEL_CPU(env)) { 8401 *ebx = 0; 8402 } else { 8403 *ebx = env->features[FEAT_8000_0007_EBX]; 8404 } 8405 *ecx = 0; 8406 *edx = env->features[FEAT_8000_0007_EDX]; 8407 break; 8408 case 0x80000008: 8409 /* virtual & phys address size in low 2 bytes. */ 8410 *eax = cpu->phys_bits; 8411 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 8412 /* 64 bit processor */ 8413 *eax |= (cpu_x86_virtual_addr_width(env) << 8); 8414 *eax |= (cpu->guest_phys_bits << 16); 8415 } 8416 *ebx = env->features[FEAT_8000_0008_EBX]; 8417 8418 /* 8419 * Don't emulate Bits [7:0] & Bits [15:12] for Intel/Zhaoxin, since 8420 * they're using 0x1f leaf. 8421 */ 8422 if (cpu->vendor_cpuid_only_v2 && 8423 (IS_INTEL_CPU(env) || IS_ZHAOXIN_CPU(env))) { 8424 *ecx = *edx = 0; 8425 break; 8426 } 8427 8428 if (threads_per_pkg > 1) { 8429 /* 8430 * Bits 15:12 is "The number of bits in the initial 8431 * Core::X86::Apic::ApicId[ApicId] value that indicate 8432 * thread ID within a package". 8433 * Bits 7:0 is "The number of threads in the package is NC+1" 8434 */ 8435 *ecx = (apicid_pkg_offset(topo_info) << 12) | 8436 (threads_per_pkg - 1); 8437 } else { 8438 *ecx = 0; 8439 } 8440 *edx = 0; 8441 break; 8442 case 0x8000000A: 8443 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { 8444 *eax = 0x00000001; /* SVM Revision */ 8445 *ebx = 0x00000010; /* nr of ASIDs */ 8446 *ecx = 0; 8447 *edx = env->features[FEAT_SVM]; /* optional features */ 8448 } else { 8449 *eax = 0; 8450 *ebx = 0; 8451 *ecx = 0; 8452 *edx = 0; 8453 } 8454 break; 8455 case 0x8000001D: 8456 *eax = 0; 8457 if (cpu->cache_info_passthrough) { 8458 x86_cpu_get_cache_cpuid(index, count, eax, ebx, ecx, edx); 8459 break; 8460 } 8461 switch (count) { 8462 case 0: /* L1 dcache info */ 8463 encode_cache_cpuid8000001d(env->cache_info.l1d_cache, 8464 topo_info, eax, ebx, ecx, edx); 8465 break; 8466 case 1: /* L1 icache info */ 8467 encode_cache_cpuid8000001d(env->cache_info.l1i_cache, 8468 topo_info, eax, ebx, ecx, edx); 8469 break; 8470 case 2: /* L2 cache info */ 8471 encode_cache_cpuid8000001d(env->cache_info.l2_cache, 8472 topo_info, eax, ebx, ecx, edx); 8473 break; 8474 case 3: /* L3 cache info */ 8475 encode_cache_cpuid8000001d(env->cache_info.l3_cache, 8476 topo_info, eax, ebx, ecx, edx); 8477 break; 8478 default: /* end of info */ 8479 *eax = *ebx = *ecx = *edx = 0; 8480 break; 8481 } 8482 if (cpu->amd_topoext_features_only) { 8483 *edx &= CACHE_NO_INVD_SHARING | CACHE_INCLUSIVE; 8484 } 8485 break; 8486 case 0x8000001E: 8487 if (cpu->core_id <= 255) { 8488 encode_topo_cpuid8000001e(cpu, topo_info, eax, ebx, ecx, edx); 8489 } else { 8490 *eax = 0; 8491 *ebx = 0; 8492 *ecx = 0; 8493 *edx = 0; 8494 } 8495 break; 8496 case 0x8000001F: 8497 *eax = *ebx = *ecx = *edx = 0; 8498 if (sev_enabled()) { 8499 *eax = 0x2; 8500 *eax |= sev_es_enabled() ? 0x8 : 0; 8501 *eax |= sev_snp_enabled() ? 0x10 : 0; 8502 *ebx = sev_get_cbit_position() & 0x3f; /* EBX[5:0] */ 8503 *ebx |= (sev_get_reduced_phys_bits() & 0x3f) << 6; /* EBX[11:6] */ 8504 } 8505 break; 8506 case 0x80000021: 8507 *eax = *ebx = *ecx = *edx = 0; 8508 *eax = env->features[FEAT_8000_0021_EAX]; 8509 *ebx = env->features[FEAT_8000_0021_EBX]; 8510 break; 8511 case 0x80000022: 8512 *eax = *ebx = *ecx = *edx = 0; 8513 /* AMD Extended Performance Monitoring and Debug */ 8514 if (kvm_enabled() && cpu->enable_pmu && 8515 (env->features[FEAT_8000_0022_EAX] & CPUID_8000_0022_EAX_PERFMON_V2)) { 8516 *eax |= CPUID_8000_0022_EAX_PERFMON_V2; 8517 *ebx |= kvm_arch_get_supported_cpuid(cs->kvm_state, index, count, 8518 R_EBX) & 0xf; 8519 } 8520 break; 8521 case 0xC0000000: 8522 *eax = env->cpuid_xlevel2; 8523 *ebx = 0; 8524 *ecx = 0; 8525 *edx = 0; 8526 break; 8527 case 0xC0000001: 8528 /* Support for VIA CPU's CPUID instruction */ 8529 *eax = env->cpuid_version; 8530 *ebx = 0; 8531 *ecx = 0; 8532 *edx = env->features[FEAT_C000_0001_EDX]; 8533 break; 8534 case 0xC0000002: 8535 case 0xC0000003: 8536 case 0xC0000004: 8537 /* Reserved for the future, and now filled with zero */ 8538 *eax = 0; 8539 *ebx = 0; 8540 *ecx = 0; 8541 *edx = 0; 8542 break; 8543 default: 8544 /* reserved values: zero */ 8545 *eax = 0; 8546 *ebx = 0; 8547 *ecx = 0; 8548 *edx = 0; 8549 break; 8550 } 8551 } 8552 8553 static void x86_cpu_set_sgxlepubkeyhash(CPUX86State *env) 8554 { 8555 #ifndef CONFIG_USER_ONLY 8556 /* Those default values are defined in Skylake HW */ 8557 env->msr_ia32_sgxlepubkeyhash[0] = 0xa6053e051270b7acULL; 8558 env->msr_ia32_sgxlepubkeyhash[1] = 0x6cfbe8ba8b3b413dULL; 8559 env->msr_ia32_sgxlepubkeyhash[2] = 0xc4916d99f2b3735dULL; 8560 env->msr_ia32_sgxlepubkeyhash[3] = 0xd4f8c05909f9bb3bULL; 8561 #endif 8562 } 8563 8564 static bool cpuid_has_xsave_feature(CPUX86State *env, const ExtSaveArea *esa) 8565 { 8566 if (!esa->size) { 8567 return false; 8568 } 8569 8570 if (env->features[esa->feature] & esa->bits) { 8571 return true; 8572 } 8573 if (esa->feature == FEAT_7_0_EBX && esa->bits == CPUID_7_0_EBX_AVX512F 8574 && (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10)) { 8575 return true; 8576 } 8577 8578 return false; 8579 } 8580 8581 static void x86_cpu_reset_hold(Object *obj, ResetType type) 8582 { 8583 CPUState *cs = CPU(obj); 8584 X86CPU *cpu = X86_CPU(cs); 8585 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj); 8586 CPUX86State *env = &cpu->env; 8587 target_ulong cr4; 8588 uint64_t xcr0; 8589 int i; 8590 8591 if (xcc->parent_phases.hold) { 8592 xcc->parent_phases.hold(obj, type); 8593 } 8594 8595 memset(env, 0, offsetof(CPUX86State, end_reset_fields)); 8596 8597 if (tcg_enabled()) { 8598 cpu_init_fp_statuses(env); 8599 } 8600 8601 env->old_exception = -1; 8602 8603 /* init to reset state */ 8604 env->int_ctl = 0; 8605 env->hflags2 |= HF2_GIF_MASK; 8606 env->hflags2 |= HF2_VGIF_MASK; 8607 env->hflags &= ~HF_GUEST_MASK; 8608 8609 cpu_x86_update_cr0(env, 0x60000010); 8610 env->a20_mask = ~0x0; 8611 env->smbase = 0x30000; 8612 env->msr_smi_count = 0; 8613 8614 env->idt.limit = 0xffff; 8615 env->gdt.limit = 0xffff; 8616 env->ldt.limit = 0xffff; 8617 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT); 8618 env->tr.limit = 0xffff; 8619 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT); 8620 8621 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff, 8622 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK | 8623 DESC_R_MASK | DESC_A_MASK); 8624 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff, 8625 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 8626 DESC_A_MASK); 8627 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff, 8628 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 8629 DESC_A_MASK); 8630 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff, 8631 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 8632 DESC_A_MASK); 8633 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff, 8634 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 8635 DESC_A_MASK); 8636 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff, 8637 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 8638 DESC_A_MASK); 8639 8640 env->eip = 0xfff0; 8641 env->regs[R_EDX] = env->cpuid_version; 8642 8643 env->eflags = 0x2; 8644 8645 /* FPU init */ 8646 for (i = 0; i < 8; i++) { 8647 env->fptags[i] = 1; 8648 } 8649 cpu_set_fpuc(env, 0x37f); 8650 8651 env->mxcsr = 0x1f80; 8652 /* All units are in INIT state. */ 8653 env->xstate_bv = 0; 8654 8655 env->pat = 0x0007040600070406ULL; 8656 8657 if (kvm_enabled()) { 8658 /* 8659 * KVM handles TSC = 0 specially and thinks we are hot-plugging 8660 * a new CPU, use 1 instead to force a reset. 8661 */ 8662 if (env->tsc != 0) { 8663 env->tsc = 1; 8664 } 8665 } else { 8666 env->tsc = 0; 8667 } 8668 8669 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT; 8670 if (env->features[FEAT_1_ECX] & CPUID_EXT_MONITOR) { 8671 env->msr_ia32_misc_enable |= MSR_IA32_MISC_ENABLE_MWAIT; 8672 } 8673 8674 memset(env->dr, 0, sizeof(env->dr)); 8675 env->dr[6] = DR6_FIXED_1; 8676 env->dr[7] = DR7_FIXED_1; 8677 cpu_breakpoint_remove_all(cs, BP_CPU); 8678 cpu_watchpoint_remove_all(cs, BP_CPU); 8679 8680 cr4 = 0; 8681 xcr0 = XSTATE_FP_MASK; 8682 8683 #ifdef CONFIG_USER_ONLY 8684 /* Enable all the features for user-mode. */ 8685 if (env->features[FEAT_1_EDX] & CPUID_SSE) { 8686 xcr0 |= XSTATE_SSE_MASK; 8687 } 8688 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 8689 const ExtSaveArea *esa = &x86_ext_save_areas[i]; 8690 if (!((1 << i) & CPUID_XSTATE_XCR0_MASK)) { 8691 continue; 8692 } 8693 if (cpuid_has_xsave_feature(env, esa)) { 8694 xcr0 |= 1ull << i; 8695 } 8696 } 8697 8698 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) { 8699 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK; 8700 } 8701 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) { 8702 cr4 |= CR4_FSGSBASE_MASK; 8703 } 8704 #endif 8705 8706 env->xcr0 = xcr0; 8707 cpu_x86_update_cr4(env, cr4); 8708 8709 /* 8710 * SDM 11.11.5 requires: 8711 * - IA32_MTRR_DEF_TYPE MSR.E = 0 8712 * - IA32_MTRR_PHYSMASKn.V = 0 8713 * All other bits are undefined. For simplification, zero it all. 8714 */ 8715 env->mtrr_deftype = 0; 8716 memset(env->mtrr_var, 0, sizeof(env->mtrr_var)); 8717 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed)); 8718 8719 env->interrupt_injected = -1; 8720 env->exception_nr = -1; 8721 env->exception_pending = 0; 8722 env->exception_injected = 0; 8723 env->exception_has_payload = false; 8724 env->exception_payload = 0; 8725 env->nmi_injected = false; 8726 env->triple_fault_pending = false; 8727 #if !defined(CONFIG_USER_ONLY) 8728 /* We hard-wire the BSP to the first CPU. */ 8729 apic_designate_bsp(cpu->apic_state, cs->cpu_index == 0); 8730 8731 cs->halted = !cpu_is_bsp(cpu); 8732 8733 if (kvm_enabled()) { 8734 kvm_arch_reset_vcpu(cpu); 8735 } 8736 8737 x86_cpu_set_sgxlepubkeyhash(env); 8738 8739 env->amd_tsc_scale_msr = MSR_AMD64_TSC_RATIO_DEFAULT; 8740 8741 #endif 8742 } 8743 8744 void x86_cpu_after_reset(X86CPU *cpu) 8745 { 8746 #ifndef CONFIG_USER_ONLY 8747 if (kvm_enabled()) { 8748 kvm_arch_after_reset_vcpu(cpu); 8749 } 8750 8751 if (cpu->apic_state) { 8752 device_cold_reset(cpu->apic_state); 8753 } 8754 #endif 8755 } 8756 8757 static void mce_init(X86CPU *cpu) 8758 { 8759 CPUX86State *cenv = &cpu->env; 8760 unsigned int bank; 8761 8762 if (x86_cpu_family(cenv->cpuid_version) >= 6 8763 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) == 8764 (CPUID_MCE | CPUID_MCA)) { 8765 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF | 8766 (cpu->enable_lmce ? MCG_LMCE_P : 0); 8767 cenv->mcg_ctl = ~(uint64_t)0; 8768 for (bank = 0; bank < MCE_BANKS_DEF; bank++) { 8769 cenv->mce_banks[bank * 4] = ~(uint64_t)0; 8770 } 8771 } 8772 } 8773 8774 static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value) 8775 { 8776 if (*min < value) { 8777 *min = value; 8778 } 8779 } 8780 8781 /* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */ 8782 static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w) 8783 { 8784 CPUX86State *env = &cpu->env; 8785 FeatureWordInfo *fi = &feature_word_info[w]; 8786 uint32_t eax = fi->cpuid.eax; 8787 uint32_t region = eax & 0xF0000000; 8788 8789 assert(feature_word_info[w].type == CPUID_FEATURE_WORD); 8790 if (!env->features[w]) { 8791 return; 8792 } 8793 8794 switch (region) { 8795 case 0x00000000: 8796 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax); 8797 break; 8798 case 0x80000000: 8799 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax); 8800 break; 8801 case 0xC0000000: 8802 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax); 8803 break; 8804 } 8805 8806 if (eax == 7) { 8807 x86_cpu_adjust_level(cpu, &env->cpuid_min_level_func7, 8808 fi->cpuid.ecx); 8809 } 8810 } 8811 8812 /* Calculate XSAVE components based on the configured CPU feature flags */ 8813 static void x86_cpu_enable_xsave_components(X86CPU *cpu) 8814 { 8815 CPUX86State *env = &cpu->env; 8816 int i; 8817 uint64_t mask; 8818 static bool request_perm; 8819 8820 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { 8821 env->features[FEAT_XSAVE_XCR0_LO] = 0; 8822 env->features[FEAT_XSAVE_XCR0_HI] = 0; 8823 env->features[FEAT_XSAVE_XSS_LO] = 0; 8824 env->features[FEAT_XSAVE_XSS_HI] = 0; 8825 return; 8826 } 8827 8828 mask = 0; 8829 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 8830 const ExtSaveArea *esa = &x86_ext_save_areas[i]; 8831 if (cpuid_has_xsave_feature(env, esa)) { 8832 mask |= (1ULL << i); 8833 } 8834 } 8835 8836 /* Only request permission for first vcpu */ 8837 if (kvm_enabled() && !request_perm) { 8838 kvm_request_xsave_components(cpu, mask); 8839 request_perm = true; 8840 } 8841 8842 env->features[FEAT_XSAVE_XCR0_LO] = mask & CPUID_XSTATE_XCR0_MASK; 8843 env->features[FEAT_XSAVE_XCR0_HI] = (mask & CPUID_XSTATE_XCR0_MASK) >> 32; 8844 env->features[FEAT_XSAVE_XSS_LO] = mask & CPUID_XSTATE_XSS_MASK; 8845 env->features[FEAT_XSAVE_XSS_HI] = (mask & CPUID_XSTATE_XSS_MASK) >> 32; 8846 } 8847 8848 /***** Steps involved on loading and filtering CPUID data 8849 * 8850 * When initializing and realizing a CPU object, the steps 8851 * involved in setting up CPUID data are: 8852 * 8853 * 1) Loading CPU model definition (X86CPUDefinition). This is 8854 * implemented by x86_cpu_load_model() and should be completely 8855 * transparent, as it is done automatically by instance_init. 8856 * No code should need to look at X86CPUDefinition structs 8857 * outside instance_init. 8858 * 8859 * 2) CPU expansion. This is done by realize before CPUID 8860 * filtering, and will make sure host/accelerator data is 8861 * loaded for CPU models that depend on host capabilities 8862 * (e.g. "host"). Done by x86_cpu_expand_features(). 8863 * 8864 * 3) CPUID filtering. This initializes extra data related to 8865 * CPUID, and checks if the host supports all capabilities 8866 * required by the CPU. Runnability of a CPU model is 8867 * determined at this step. Done by x86_cpu_filter_features(). 8868 * 8869 * Some operations don't require all steps to be performed. 8870 * More precisely: 8871 * 8872 * - CPU instance creation (instance_init) will run only CPU 8873 * model loading. CPU expansion can't run at instance_init-time 8874 * because host/accelerator data may be not available yet. 8875 * - CPU realization will perform both CPU model expansion and CPUID 8876 * filtering, and return an error in case one of them fails. 8877 * - query-cpu-definitions needs to run all 3 steps. It needs 8878 * to run CPUID filtering, as the 'unavailable-features' 8879 * field is set based on the filtering results. 8880 * - The query-cpu-model-expansion QMP command only needs to run 8881 * CPU model loading and CPU expansion. It should not filter 8882 * any CPUID data based on host capabilities. 8883 */ 8884 8885 /* Expand CPU configuration data, based on configured features 8886 * and host/accelerator capabilities when appropriate. 8887 */ 8888 void x86_cpu_expand_features(X86CPU *cpu, Error **errp) 8889 { 8890 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu); 8891 CPUX86State *env = &cpu->env; 8892 FeatureWord w; 8893 int i; 8894 GList *l; 8895 8896 for (l = plus_features; l; l = l->next) { 8897 const char *prop = l->data; 8898 if (!object_property_set_bool(OBJECT(cpu), prop, true, errp)) { 8899 return; 8900 } 8901 } 8902 8903 for (l = minus_features; l; l = l->next) { 8904 const char *prop = l->data; 8905 if (!object_property_set_bool(OBJECT(cpu), prop, false, errp)) { 8906 return; 8907 } 8908 } 8909 8910 /* TODO: Now xcc->max_features doesn't overwrite features 8911 * set using QOM properties, and we can convert 8912 * plus_features & minus_features to global properties 8913 * inside x86_cpu_parse_featurestr() too. 8914 */ 8915 if (xcc->max_features) { 8916 for (w = 0; w < FEATURE_WORDS; w++) { 8917 /* Override only features that weren't set explicitly 8918 * by the user. 8919 */ 8920 env->features[w] |= 8921 x86_cpu_get_supported_feature_word(cpu, w) & 8922 ~env->user_features[w] & 8923 ~feature_word_info[w].no_autoenable_flags; 8924 } 8925 8926 if ((env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) && !env->avx10_version) { 8927 uint32_t eax, ebx, ecx, edx; 8928 x86_cpu_get_supported_cpuid(0x24, 0, &eax, &ebx, &ecx, &edx); 8929 env->avx10_version = ebx & 0xff; 8930 } 8931 } 8932 8933 if (x86_threads_per_pkg(&env->topo_info) > 1) { 8934 env->features[FEAT_1_EDX] |= CPUID_HT; 8935 8936 /* 8937 * The Linux kernel checks for the CMPLegacy bit and 8938 * discards multiple thread information if it is set. 8939 * So don't set it here for Intel (and other processors 8940 * following Intel's behavior) to make Linux guests happy. 8941 */ 8942 if (!IS_INTEL_CPU(env) && !IS_ZHAOXIN_CPU(env)) { 8943 env->features[FEAT_8000_0001_ECX] |= CPUID_EXT3_CMP_LEG; 8944 } 8945 } 8946 8947 /* PDCM is fixed1 bit for TDX */ 8948 if (!cpu->enable_pmu && !is_tdx_vm()) { 8949 mark_unavailable_features(cpu, FEAT_1_ECX, 8950 env->user_features[FEAT_1_ECX] & CPUID_EXT_PDCM, 8951 "This feature is not available due to PMU being disabled"); 8952 env->features[FEAT_1_ECX] &= ~CPUID_EXT_PDCM; 8953 } 8954 8955 for (i = 0; i < ARRAY_SIZE(feature_dependencies); i++) { 8956 FeatureDep *d = &feature_dependencies[i]; 8957 if (!(env->features[d->from.index] & d->from.mask)) { 8958 uint64_t unavailable_features = env->features[d->to.index] & d->to.mask; 8959 8960 /* Not an error unless the dependent feature was added explicitly. */ 8961 mark_unavailable_features(cpu, d->to.index, 8962 unavailable_features & env->user_features[d->to.index], 8963 "This feature depends on other features that were not requested"); 8964 8965 env->features[d->to.index] &= ~unavailable_features; 8966 } 8967 } 8968 8969 if (!kvm_enabled() || !cpu->expose_kvm) { 8970 env->features[FEAT_KVM] = 0; 8971 } 8972 8973 x86_cpu_enable_xsave_components(cpu); 8974 8975 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */ 8976 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX); 8977 if (cpu->full_cpuid_auto_level) { 8978 x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX); 8979 x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX); 8980 x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX); 8981 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX); 8982 x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EAX); 8983 x86_cpu_adjust_feat_level(cpu, FEAT_7_1_ECX); 8984 x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EDX); 8985 x86_cpu_adjust_feat_level(cpu, FEAT_7_2_EDX); 8986 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX); 8987 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX); 8988 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX); 8989 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0008_EBX); 8990 x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX); 8991 x86_cpu_adjust_feat_level(cpu, FEAT_SVM); 8992 x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE); 8993 8994 /* Intel Processor Trace requires CPUID[0x14] */ 8995 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT)) { 8996 if (cpu->intel_pt_auto_level) { 8997 x86_cpu_adjust_level(cpu, &cpu->env.cpuid_min_level, 0x14); 8998 } else if (cpu->env.cpuid_min_level < 0x14) { 8999 mark_unavailable_features(cpu, FEAT_7_0_EBX, 9000 CPUID_7_0_EBX_INTEL_PT, 9001 "Intel PT need CPUID leaf 0x14, please set by \"-cpu ...,intel-pt=on,min-level=0x14\""); 9002 } 9003 } 9004 9005 /* 9006 * Intel CPU topology with multi-dies support requires CPUID[0x1F]. 9007 * For AMD Rome/Milan, cpuid level is 0x10, and guest OS should detect 9008 * extended toplogy by leaf 0xB. Only adjust it for Intel CPU, unless 9009 * cpu->vendor_cpuid_only has been unset for compatibility with older 9010 * machine types. 9011 */ 9012 if (x86_has_cpuid_0x1f(cpu) && 9013 (IS_INTEL_CPU(env) || !cpu->vendor_cpuid_only)) { 9014 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x1F); 9015 } 9016 9017 /* Advanced Vector Extensions 10 (AVX10) requires CPUID[0x24] */ 9018 if (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) { 9019 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x24); 9020 } 9021 9022 /* SVM requires CPUID[0x8000000A] */ 9023 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { 9024 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A); 9025 } 9026 9027 /* SEV requires CPUID[0x8000001F] */ 9028 if (sev_enabled()) { 9029 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F); 9030 } 9031 9032 if (env->features[FEAT_8000_0021_EAX]) { 9033 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x80000021); 9034 } 9035 9036 /* SGX requires CPUID[0x12] for EPC enumeration */ 9037 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX) { 9038 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x12); 9039 } 9040 } 9041 9042 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */ 9043 if (env->cpuid_level_func7 == UINT32_MAX) { 9044 env->cpuid_level_func7 = env->cpuid_min_level_func7; 9045 } 9046 if (env->cpuid_level == UINT32_MAX) { 9047 env->cpuid_level = env->cpuid_min_level; 9048 } 9049 if (env->cpuid_xlevel == UINT32_MAX) { 9050 env->cpuid_xlevel = env->cpuid_min_xlevel; 9051 } 9052 if (env->cpuid_xlevel2 == UINT32_MAX) { 9053 env->cpuid_xlevel2 = env->cpuid_min_xlevel2; 9054 } 9055 9056 if (kvm_enabled() && !kvm_hyperv_expand_features(cpu, errp)) { 9057 return; 9058 } 9059 } 9060 9061 /* 9062 * Finishes initialization of CPUID data, filters CPU feature 9063 * words based on host availability of each feature. 9064 * 9065 * Returns: true if any flag is not supported by the host, false otherwise. 9066 */ 9067 static bool x86_cpu_filter_features(X86CPU *cpu, bool verbose) 9068 { 9069 CPUX86State *env = &cpu->env; 9070 FeatureWord w; 9071 const char *prefix = NULL; 9072 bool have_filtered_features; 9073 9074 uint32_t eax_0, ebx_0, ecx_0, edx_0; 9075 uint32_t eax_1, ebx_1, ecx_1, edx_1; 9076 9077 if (verbose) { 9078 prefix = accel_uses_host_cpuid() 9079 ? "host doesn't support requested feature" 9080 : "TCG doesn't support requested feature"; 9081 } 9082 9083 for (w = 0; w < FEATURE_WORDS; w++) { 9084 uint64_t host_feat = 9085 x86_cpu_get_supported_feature_word(NULL, w); 9086 uint64_t requested_features = env->features[w]; 9087 uint64_t unavailable_features = requested_features & ~host_feat; 9088 mark_unavailable_features(cpu, w, unavailable_features, prefix); 9089 } 9090 9091 /* 9092 * Check that KVM actually allows the processor tracing features that 9093 * are advertised by cpu_x86_cpuid(). Keep these two in sync. 9094 */ 9095 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) && 9096 kvm_enabled()) { 9097 x86_cpu_get_supported_cpuid(0x14, 0, 9098 &eax_0, &ebx_0, &ecx_0, &edx_0); 9099 x86_cpu_get_supported_cpuid(0x14, 1, 9100 &eax_1, &ebx_1, &ecx_1, &edx_1); 9101 9102 if (!eax_0 || 9103 ((ebx_0 & INTEL_PT_MINIMAL_EBX) != INTEL_PT_MINIMAL_EBX) || 9104 ((ecx_0 & INTEL_PT_MINIMAL_ECX) != INTEL_PT_MINIMAL_ECX) || 9105 ((eax_1 & INTEL_PT_MTC_BITMAP) != INTEL_PT_MTC_BITMAP) || 9106 ((eax_1 & INTEL_PT_ADDR_RANGES_NUM_MASK) < 9107 INTEL_PT_ADDR_RANGES_NUM) || 9108 ((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) != 9109 (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) || 9110 ((ecx_0 & CPUID_14_0_ECX_LIP) != 9111 (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP))) { 9112 /* 9113 * Processor Trace capabilities aren't configurable, so if the 9114 * host can't emulate the capabilities we report on 9115 * cpu_x86_cpuid(), intel-pt can't be enabled on the current host. 9116 */ 9117 mark_unavailable_features(cpu, FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT, prefix); 9118 } 9119 } 9120 9121 have_filtered_features = x86_cpu_have_filtered_features(cpu); 9122 9123 if (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) { 9124 x86_cpu_get_supported_cpuid(0x24, 0, 9125 &eax_0, &ebx_0, &ecx_0, &edx_0); 9126 uint8_t version = ebx_0 & 0xff; 9127 9128 if (version < env->avx10_version) { 9129 if (prefix) { 9130 warn_report("%s: avx10.%d. Adjust to avx10.%d", 9131 prefix, env->avx10_version, version); 9132 } 9133 env->avx10_version = version; 9134 have_filtered_features = true; 9135 } 9136 } else if (env->avx10_version) { 9137 if (prefix) { 9138 warn_report("%s: avx10.%d.", prefix, env->avx10_version); 9139 } 9140 have_filtered_features = true; 9141 } 9142 9143 return have_filtered_features; 9144 } 9145 9146 static void x86_cpu_hyperv_realize(X86CPU *cpu) 9147 { 9148 size_t len; 9149 9150 /* Hyper-V vendor id */ 9151 if (!cpu->hyperv_vendor) { 9152 object_property_set_str(OBJECT(cpu), "hv-vendor-id", "Microsoft Hv", 9153 &error_abort); 9154 } 9155 len = strlen(cpu->hyperv_vendor); 9156 if (len > 12) { 9157 warn_report("hv-vendor-id truncated to 12 characters"); 9158 len = 12; 9159 } 9160 memset(cpu->hyperv_vendor_id, 0, 12); 9161 memcpy(cpu->hyperv_vendor_id, cpu->hyperv_vendor, len); 9162 9163 /* 'Hv#1' interface identification*/ 9164 cpu->hyperv_interface_id[0] = 0x31237648; 9165 cpu->hyperv_interface_id[1] = 0; 9166 cpu->hyperv_interface_id[2] = 0; 9167 cpu->hyperv_interface_id[3] = 0; 9168 9169 /* Hypervisor implementation limits */ 9170 cpu->hyperv_limits[0] = 64; 9171 cpu->hyperv_limits[1] = 0; 9172 cpu->hyperv_limits[2] = 0; 9173 } 9174 9175 #ifndef CONFIG_USER_ONLY 9176 static bool x86_cpu_update_smp_cache_topo(MachineState *ms, X86CPU *cpu, 9177 Error **errp) 9178 { 9179 CPUX86State *env = &cpu->env; 9180 CpuTopologyLevel level; 9181 9182 level = machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1D); 9183 if (level != CPU_TOPOLOGY_LEVEL_DEFAULT) { 9184 env->cache_info.l1d_cache->share_level = level; 9185 } else { 9186 machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1D, 9187 env->cache_info.l1d_cache->share_level); 9188 } 9189 9190 level = machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1I); 9191 if (level != CPU_TOPOLOGY_LEVEL_DEFAULT) { 9192 env->cache_info.l1i_cache->share_level = level; 9193 } else { 9194 machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1I, 9195 env->cache_info.l1i_cache->share_level); 9196 } 9197 9198 level = machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L2); 9199 if (level != CPU_TOPOLOGY_LEVEL_DEFAULT) { 9200 env->cache_info.l2_cache->share_level = level; 9201 } else { 9202 machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L2, 9203 env->cache_info.l2_cache->share_level); 9204 } 9205 9206 level = machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L3); 9207 if (level != CPU_TOPOLOGY_LEVEL_DEFAULT) { 9208 env->cache_info.l3_cache->share_level = level; 9209 } else { 9210 machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L3, 9211 env->cache_info.l3_cache->share_level); 9212 } 9213 9214 if (!machine_check_smp_cache(ms, errp)) { 9215 return false; 9216 } 9217 return true; 9218 } 9219 #endif 9220 9221 static void x86_cpu_realizefn(DeviceState *dev, Error **errp) 9222 { 9223 CPUState *cs = CPU(dev); 9224 X86CPU *cpu = X86_CPU(dev); 9225 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev); 9226 CPUX86State *env = &cpu->env; 9227 Error *local_err = NULL; 9228 unsigned requested_lbr_fmt; 9229 9230 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) 9231 /* Use pc-relative instructions in system-mode */ 9232 tcg_cflags_set(cs, CF_PCREL); 9233 #endif 9234 9235 /* 9236 * x-vendor-cpuid-only and v2 should be initernal only. But 9237 * QEMU doesn't support "internal" property. 9238 */ 9239 if (!cpu->vendor_cpuid_only && cpu->vendor_cpuid_only_v2) { 9240 error_setg(errp, "x-vendor-cpuid-only-v2 property " 9241 "depends on x-vendor-cpuid-only"); 9242 return; 9243 } 9244 9245 if (cpu->apic_id == UNASSIGNED_APIC_ID) { 9246 error_setg(errp, "apic-id property was not initialized properly"); 9247 return; 9248 } 9249 9250 /* 9251 * Process Hyper-V enlightenments. 9252 * Note: this currently has to happen before the expansion of CPU features. 9253 */ 9254 x86_cpu_hyperv_realize(cpu); 9255 9256 x86_cpu_expand_features(cpu, &local_err); 9257 if (local_err) { 9258 goto out; 9259 } 9260 9261 /* 9262 * Override env->features[FEAT_PERF_CAPABILITIES].LBR_FMT 9263 * with user-provided setting. 9264 */ 9265 if (cpu->lbr_fmt != ~PERF_CAP_LBR_FMT) { 9266 if ((cpu->lbr_fmt & PERF_CAP_LBR_FMT) != cpu->lbr_fmt) { 9267 error_setg(errp, "invalid lbr-fmt"); 9268 return; 9269 } 9270 env->features[FEAT_PERF_CAPABILITIES] &= ~PERF_CAP_LBR_FMT; 9271 env->features[FEAT_PERF_CAPABILITIES] |= cpu->lbr_fmt; 9272 } 9273 9274 /* 9275 * vPMU LBR is supported when 1) KVM is enabled 2) Option pmu=on and 9276 * 3)vPMU LBR format matches that of host setting. 9277 */ 9278 requested_lbr_fmt = 9279 env->features[FEAT_PERF_CAPABILITIES] & PERF_CAP_LBR_FMT; 9280 if (requested_lbr_fmt && kvm_enabled()) { 9281 uint64_t host_perf_cap = 9282 x86_cpu_get_supported_feature_word(NULL, FEAT_PERF_CAPABILITIES); 9283 unsigned host_lbr_fmt = host_perf_cap & PERF_CAP_LBR_FMT; 9284 9285 if (!cpu->enable_pmu) { 9286 error_setg(errp, "vPMU: LBR is unsupported without pmu=on"); 9287 return; 9288 } 9289 if (requested_lbr_fmt != host_lbr_fmt) { 9290 error_setg(errp, "vPMU: the lbr-fmt value (0x%x) does not match " 9291 "the host value (0x%x).", 9292 requested_lbr_fmt, host_lbr_fmt); 9293 return; 9294 } 9295 } 9296 9297 if (x86_cpu_filter_features(cpu, cpu->check_cpuid || cpu->enforce_cpuid)) { 9298 if (cpu->enforce_cpuid) { 9299 error_setg(&local_err, 9300 accel_uses_host_cpuid() ? 9301 "Host doesn't support requested features" : 9302 "TCG doesn't support requested features"); 9303 goto out; 9304 } 9305 } 9306 9307 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on 9308 * CPUID[1].EDX. 9309 */ 9310 if (IS_AMD_CPU(env)) { 9311 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES; 9312 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX] 9313 & CPUID_EXT2_AMD_ALIASES); 9314 } 9315 9316 x86_cpu_set_sgxlepubkeyhash(env); 9317 9318 /* 9319 * note: the call to the framework needs to happen after feature expansion, 9320 * but before the checks/modifications to ucode_rev, mwait, phys_bits. 9321 * These may be set by the accel-specific code, 9322 * and the results are subsequently checked / assumed in this function. 9323 */ 9324 cpu_exec_realizefn(cs, &local_err); 9325 if (local_err != NULL) { 9326 error_propagate(errp, local_err); 9327 return; 9328 } 9329 9330 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) { 9331 g_autofree char *name = x86_cpu_class_get_model_name(xcc); 9332 error_setg(&local_err, "CPU model '%s' requires KVM or HVF", name); 9333 goto out; 9334 } 9335 9336 if (cpu->guest_phys_bits == -1) { 9337 /* 9338 * If it was not set by the user, or by the accelerator via 9339 * cpu_exec_realizefn, clear. 9340 */ 9341 cpu->guest_phys_bits = 0; 9342 } 9343 9344 if (cpu->ucode_rev == 0) { 9345 /* 9346 * The default is the same as KVM's. Note that this check 9347 * needs to happen after the evenual setting of ucode_rev in 9348 * accel-specific code in cpu_exec_realizefn. 9349 */ 9350 if (IS_AMD_CPU(env)) { 9351 cpu->ucode_rev = 0x01000065; 9352 } else { 9353 cpu->ucode_rev = 0x100000000ULL; 9354 } 9355 } 9356 9357 /* 9358 * mwait extended info: needed for Core compatibility 9359 * We always wake on interrupt even if host does not have the capability. 9360 * 9361 * requires the accel-specific code in cpu_exec_realizefn to 9362 * have already acquired the CPUID data into cpu->mwait. 9363 */ 9364 cpu->mwait.ecx |= CPUID_MWAIT_EMX | CPUID_MWAIT_IBE; 9365 9366 /* 9367 * Most Intel and certain AMD CPUs support hyperthreading. Even though QEMU 9368 * fixes this issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX 9369 * based on inputs (sockets,cores,threads), it is still better to give 9370 * users a warning. 9371 */ 9372 if (IS_AMD_CPU(env) && 9373 !(env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) && 9374 env->topo_info.threads_per_core > 1) { 9375 warn_report_once("This family of AMD CPU doesn't support " 9376 "hyperthreading(%d). Please configure -smp " 9377 "options properly or try enabling topoext " 9378 "feature.", env->topo_info.threads_per_core); 9379 } 9380 9381 /* For 64bit systems think about the number of physical bits to present. 9382 * ideally this should be the same as the host; anything other than matching 9383 * the host can cause incorrect guest behaviour. 9384 * QEMU used to pick the magic value of 40 bits that corresponds to 9385 * consumer AMD devices but nothing else. 9386 * 9387 * Note that this code assumes features expansion has already been done 9388 * (as it checks for CPUID_EXT2_LM), and also assumes that potential 9389 * phys_bits adjustments to match the host have been already done in 9390 * accel-specific code in cpu_exec_realizefn. 9391 */ 9392 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 9393 if (cpu->phys_bits && 9394 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS || 9395 cpu->phys_bits < 32)) { 9396 error_setg(errp, "phys-bits should be between 32 and %u " 9397 " (but is %u)", 9398 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits); 9399 return; 9400 } 9401 /* 9402 * 0 means it was not explicitly set by the user (or by machine 9403 * compat_props or by the host code in host-cpu.c). 9404 * In this case, the default is the value used by TCG (40). 9405 */ 9406 if (cpu->phys_bits == 0) { 9407 cpu->phys_bits = TCG_PHYS_ADDR_BITS; 9408 } 9409 if (cpu->guest_phys_bits && 9410 (cpu->guest_phys_bits > cpu->phys_bits || 9411 cpu->guest_phys_bits < 32)) { 9412 error_setg(errp, "guest-phys-bits should be between 32 and %u " 9413 " (but is %u)", 9414 cpu->phys_bits, cpu->guest_phys_bits); 9415 return; 9416 } 9417 } else { 9418 /* For 32 bit systems don't use the user set value, but keep 9419 * phys_bits consistent with what we tell the guest. 9420 */ 9421 if (cpu->phys_bits != 0) { 9422 error_setg(errp, "phys-bits is not user-configurable in 32 bit"); 9423 return; 9424 } 9425 if (cpu->guest_phys_bits != 0) { 9426 error_setg(errp, "guest-phys-bits is not user-configurable in 32 bit"); 9427 return; 9428 } 9429 9430 if (env->features[FEAT_1_EDX] & (CPUID_PSE36 | CPUID_PAE)) { 9431 cpu->phys_bits = 36; 9432 } else { 9433 cpu->phys_bits = 32; 9434 } 9435 } 9436 9437 /* Cache information initialization */ 9438 if (!cpu->legacy_cache) { 9439 const CPUCaches *cache_info = 9440 x86_cpu_get_versioned_cache_info(cpu, xcc->model); 9441 9442 if (!xcc->model || !cache_info) { 9443 g_autofree char *name = x86_cpu_class_get_model_name(xcc); 9444 error_setg(errp, 9445 "CPU model '%s' doesn't support legacy-cache=off", name); 9446 return; 9447 } 9448 env->cache_info = *cache_info; 9449 } else { 9450 /* Build legacy cache information */ 9451 if (!cpu->consistent_cache) { 9452 env->enable_legacy_cpuid2_cache = true; 9453 } 9454 9455 if (!cpu->vendor_cpuid_only_v2) { 9456 env->enable_legacy_vendor_cache = true; 9457 } 9458 9459 if (IS_AMD_CPU(env)) { 9460 env->cache_info = legacy_amd_cache_info; 9461 } else { 9462 env->cache_info = legacy_intel_cache_info; 9463 } 9464 } 9465 9466 #ifndef CONFIG_USER_ONLY 9467 MachineState *ms = MACHINE(qdev_get_machine()); 9468 MachineClass *mc = MACHINE_GET_CLASS(ms); 9469 9470 if (mc->smp_props.has_caches) { 9471 if (!x86_cpu_update_smp_cache_topo(ms, cpu, errp)) { 9472 return; 9473 } 9474 } 9475 9476 qemu_register_reset(x86_cpu_machine_reset_cb, cpu); 9477 9478 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || ms->smp.cpus > 1) { 9479 x86_cpu_apic_create(cpu, &local_err); 9480 if (local_err != NULL) { 9481 goto out; 9482 } 9483 } 9484 #endif 9485 9486 mce_init(cpu); 9487 9488 x86_cpu_gdb_init(cs); 9489 qemu_init_vcpu(cs); 9490 9491 #ifndef CONFIG_USER_ONLY 9492 x86_cpu_apic_realize(cpu, &local_err); 9493 if (local_err != NULL) { 9494 goto out; 9495 } 9496 #endif /* !CONFIG_USER_ONLY */ 9497 cpu_reset(cs); 9498 9499 xcc->parent_realize(dev, &local_err); 9500 9501 out: 9502 if (local_err != NULL) { 9503 error_propagate(errp, local_err); 9504 return; 9505 } 9506 } 9507 9508 static void x86_cpu_unrealizefn(DeviceState *dev) 9509 { 9510 X86CPU *cpu = X86_CPU(dev); 9511 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev); 9512 9513 #ifndef CONFIG_USER_ONLY 9514 cpu_remove_sync(CPU(dev)); 9515 qemu_unregister_reset(x86_cpu_machine_reset_cb, dev); 9516 #endif 9517 9518 if (cpu->apic_state) { 9519 object_unparent(OBJECT(cpu->apic_state)); 9520 cpu->apic_state = NULL; 9521 } 9522 9523 xcc->parent_unrealize(dev); 9524 } 9525 9526 typedef struct BitProperty { 9527 FeatureWord w; 9528 uint64_t mask; 9529 } BitProperty; 9530 9531 static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name, 9532 void *opaque, Error **errp) 9533 { 9534 X86CPU *cpu = X86_CPU(obj); 9535 BitProperty *fp = opaque; 9536 uint64_t f = cpu->env.features[fp->w]; 9537 bool value = (f & fp->mask) == fp->mask; 9538 visit_type_bool(v, name, &value, errp); 9539 } 9540 9541 static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name, 9542 void *opaque, Error **errp) 9543 { 9544 DeviceState *dev = DEVICE(obj); 9545 X86CPU *cpu = X86_CPU(obj); 9546 BitProperty *fp = opaque; 9547 bool value; 9548 9549 if (dev->realized) { 9550 qdev_prop_set_after_realize(dev, name, errp); 9551 return; 9552 } 9553 9554 if (!visit_type_bool(v, name, &value, errp)) { 9555 return; 9556 } 9557 9558 if (value) { 9559 cpu->env.features[fp->w] |= fp->mask; 9560 } else { 9561 cpu->env.features[fp->w] &= ~fp->mask; 9562 } 9563 cpu->env.user_features[fp->w] |= fp->mask; 9564 } 9565 9566 /* Register a boolean property to get/set a single bit in a uint32_t field. 9567 * 9568 * The same property name can be registered multiple times to make it affect 9569 * multiple bits in the same FeatureWord. In that case, the getter will return 9570 * true only if all bits are set. 9571 */ 9572 static void x86_cpu_register_bit_prop(X86CPUClass *xcc, 9573 const char *prop_name, 9574 FeatureWord w, 9575 int bitnr) 9576 { 9577 ObjectClass *oc = OBJECT_CLASS(xcc); 9578 BitProperty *fp; 9579 ObjectProperty *op; 9580 uint64_t mask = (1ULL << bitnr); 9581 9582 op = object_class_property_find(oc, prop_name); 9583 if (op) { 9584 fp = op->opaque; 9585 assert(fp->w == w); 9586 fp->mask |= mask; 9587 } else { 9588 fp = g_new0(BitProperty, 1); 9589 fp->w = w; 9590 fp->mask = mask; 9591 object_class_property_add(oc, prop_name, "bool", 9592 x86_cpu_get_bit_prop, 9593 x86_cpu_set_bit_prop, 9594 NULL, fp); 9595 } 9596 } 9597 9598 static void x86_cpu_register_feature_bit_props(X86CPUClass *xcc, 9599 FeatureWord w, 9600 int bitnr) 9601 { 9602 FeatureWordInfo *fi = &feature_word_info[w]; 9603 const char *name = fi->feat_names[bitnr]; 9604 9605 if (!name) { 9606 return; 9607 } 9608 9609 /* Property names should use "-" instead of "_". 9610 * Old names containing underscores are registered as aliases 9611 * using object_property_add_alias() 9612 */ 9613 assert(!strchr(name, '_')); 9614 /* aliases don't use "|" delimiters anymore, they are registered 9615 * manually using object_property_add_alias() */ 9616 assert(!strchr(name, '|')); 9617 x86_cpu_register_bit_prop(xcc, name, w, bitnr); 9618 } 9619 9620 static void x86_cpu_post_initfn(Object *obj) 9621 { 9622 #ifndef CONFIG_USER_ONLY 9623 if (current_machine && current_machine->cgs) { 9624 x86_confidential_guest_cpu_instance_init( 9625 X86_CONFIDENTIAL_GUEST(current_machine->cgs), (CPU(obj))); 9626 } 9627 #endif 9628 } 9629 9630 static void x86_cpu_init_xsave(void) 9631 { 9632 static bool first = true; 9633 uint64_t supported_xcr0; 9634 int i; 9635 9636 if (first) { 9637 first = false; 9638 9639 supported_xcr0 = 9640 ((uint64_t) x86_cpu_get_supported_feature_word(NULL, FEAT_XSAVE_XCR0_HI) << 32) | 9641 x86_cpu_get_supported_feature_word(NULL, FEAT_XSAVE_XCR0_LO); 9642 9643 for (i = XSTATE_SSE_BIT + 1; i < XSAVE_STATE_AREA_COUNT; i++) { 9644 ExtSaveArea *esa = &x86_ext_save_areas[i]; 9645 9646 if (!(supported_xcr0 & (1 << i))) { 9647 esa->size = 0; 9648 } 9649 } 9650 } 9651 } 9652 9653 static void x86_cpu_init_default_topo(X86CPU *cpu) 9654 { 9655 CPUX86State *env = &cpu->env; 9656 9657 env->topo_info = (X86CPUTopoInfo) {1, 1, 1, 1}; 9658 9659 /* thread, core and socket levels are set by default. */ 9660 set_bit(CPU_TOPOLOGY_LEVEL_THREAD, env->avail_cpu_topo); 9661 set_bit(CPU_TOPOLOGY_LEVEL_CORE, env->avail_cpu_topo); 9662 set_bit(CPU_TOPOLOGY_LEVEL_SOCKET, env->avail_cpu_topo); 9663 } 9664 9665 static void x86_cpu_initfn(Object *obj) 9666 { 9667 X86CPU *cpu = X86_CPU(obj); 9668 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj); 9669 CPUX86State *env = &cpu->env; 9670 9671 x86_cpu_init_default_topo(cpu); 9672 9673 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo", 9674 x86_cpu_get_feature_words, 9675 NULL, NULL, (void *)env->features); 9676 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo", 9677 x86_cpu_get_feature_words, 9678 NULL, NULL, (void *)cpu->filtered_features); 9679 9680 object_property_add_alias(obj, "sse3", obj, "pni"); 9681 object_property_add_alias(obj, "pclmuldq", obj, "pclmulqdq"); 9682 object_property_add_alias(obj, "sse4-1", obj, "sse4.1"); 9683 object_property_add_alias(obj, "sse4-2", obj, "sse4.2"); 9684 object_property_add_alias(obj, "xd", obj, "nx"); 9685 object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt"); 9686 object_property_add_alias(obj, "i64", obj, "lm"); 9687 9688 object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl"); 9689 object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust"); 9690 object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt"); 9691 object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm"); 9692 object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy"); 9693 object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr"); 9694 object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core"); 9695 object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb"); 9696 object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay"); 9697 object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu"); 9698 object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf"); 9699 object_property_add_alias(obj, "kvm_asyncpf_int", obj, "kvm-asyncpf-int"); 9700 object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time"); 9701 object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi"); 9702 object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt"); 9703 object_property_add_alias(obj, "kvm_poll_control", obj, "kvm-poll-control"); 9704 object_property_add_alias(obj, "svm_lock", obj, "svm-lock"); 9705 object_property_add_alias(obj, "nrip_save", obj, "nrip-save"); 9706 object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale"); 9707 object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean"); 9708 object_property_add_alias(obj, "pause_filter", obj, "pause-filter"); 9709 object_property_add_alias(obj, "sse4_1", obj, "sse4.1"); 9710 object_property_add_alias(obj, "sse4_2", obj, "sse4.2"); 9711 9712 object_property_add_alias(obj, "hv-apicv", obj, "hv-avic"); 9713 cpu->lbr_fmt = ~PERF_CAP_LBR_FMT; 9714 object_property_add_alias(obj, "lbr_fmt", obj, "lbr-fmt"); 9715 9716 if (xcc->model) { 9717 x86_cpu_load_model(cpu, xcc->model); 9718 } 9719 9720 /* 9721 * accel's cpu_instance_init may have the xsave check, 9722 * so x86_ext_save_areas[] must be initialized before this. 9723 */ 9724 x86_cpu_init_xsave(); 9725 accel_cpu_instance_init(CPU(obj)); 9726 } 9727 9728 static int64_t x86_cpu_get_arch_id(CPUState *cs) 9729 { 9730 X86CPU *cpu = X86_CPU(cs); 9731 9732 return cpu->apic_id; 9733 } 9734 9735 #if !defined(CONFIG_USER_ONLY) 9736 static bool x86_cpu_get_paging_enabled(const CPUState *cs) 9737 { 9738 X86CPU *cpu = X86_CPU(cs); 9739 9740 return cpu->env.cr[0] & CR0_PG_MASK; 9741 } 9742 #endif /* !CONFIG_USER_ONLY */ 9743 9744 static void x86_cpu_set_pc(CPUState *cs, vaddr value) 9745 { 9746 X86CPU *cpu = X86_CPU(cs); 9747 9748 cpu->env.eip = value; 9749 } 9750 9751 static vaddr x86_cpu_get_pc(CPUState *cs) 9752 { 9753 X86CPU *cpu = X86_CPU(cs); 9754 9755 /* Match cpu_get_tb_cpu_state. */ 9756 return cpu->env.eip + cpu->env.segs[R_CS].base; 9757 } 9758 9759 #if !defined(CONFIG_USER_ONLY) 9760 int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request) 9761 { 9762 X86CPU *cpu = X86_CPU(cs); 9763 CPUX86State *env = &cpu->env; 9764 9765 if (interrupt_request & CPU_INTERRUPT_POLL) { 9766 return CPU_INTERRUPT_POLL; 9767 } 9768 if (interrupt_request & CPU_INTERRUPT_SIPI) { 9769 return CPU_INTERRUPT_SIPI; 9770 } 9771 9772 if (env->hflags2 & HF2_GIF_MASK) { 9773 if ((interrupt_request & CPU_INTERRUPT_SMI) && 9774 !(env->hflags & HF_SMM_MASK)) { 9775 return CPU_INTERRUPT_SMI; 9776 } else if ((interrupt_request & CPU_INTERRUPT_NMI) && 9777 !(env->hflags2 & HF2_NMI_MASK)) { 9778 return CPU_INTERRUPT_NMI; 9779 } else if (interrupt_request & CPU_INTERRUPT_MCE) { 9780 return CPU_INTERRUPT_MCE; 9781 } else if ((interrupt_request & CPU_INTERRUPT_HARD) && 9782 (((env->hflags2 & HF2_VINTR_MASK) && 9783 (env->hflags2 & HF2_HIF_MASK)) || 9784 (!(env->hflags2 & HF2_VINTR_MASK) && 9785 (env->eflags & IF_MASK && 9786 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) { 9787 return CPU_INTERRUPT_HARD; 9788 } else if (env->hflags2 & HF2_VGIF_MASK) { 9789 if((interrupt_request & CPU_INTERRUPT_VIRQ) && 9790 (env->eflags & IF_MASK) && 9791 !(env->hflags & HF_INHIBIT_IRQ_MASK)) { 9792 return CPU_INTERRUPT_VIRQ; 9793 } 9794 } 9795 } 9796 9797 return 0; 9798 } 9799 9800 static bool x86_cpu_has_work(CPUState *cs) 9801 { 9802 return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0; 9803 } 9804 #endif /* !CONFIG_USER_ONLY */ 9805 9806 static void x86_disas_set_info(CPUState *cs, disassemble_info *info) 9807 { 9808 X86CPU *cpu = X86_CPU(cs); 9809 CPUX86State *env = &cpu->env; 9810 9811 info->endian = BFD_ENDIAN_LITTLE; 9812 info->mach = (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64 9813 : env->hflags & HF_CS32_MASK ? bfd_mach_i386_i386 9814 : bfd_mach_i386_i8086); 9815 9816 info->cap_arch = CS_ARCH_X86; 9817 info->cap_mode = (env->hflags & HF_CS64_MASK ? CS_MODE_64 9818 : env->hflags & HF_CS32_MASK ? CS_MODE_32 9819 : CS_MODE_16); 9820 info->cap_insn_unit = 1; 9821 info->cap_insn_split = 8; 9822 } 9823 9824 void x86_update_hflags(CPUX86State *env) 9825 { 9826 uint32_t hflags; 9827 #define HFLAG_COPY_MASK \ 9828 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \ 9829 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \ 9830 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \ 9831 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK) 9832 9833 hflags = env->hflags & HFLAG_COPY_MASK; 9834 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK; 9835 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT); 9836 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) & 9837 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK); 9838 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK)); 9839 9840 if (env->cr[4] & CR4_OSFXSR_MASK) { 9841 hflags |= HF_OSFXSR_MASK; 9842 } 9843 9844 if (env->efer & MSR_EFER_LMA) { 9845 hflags |= HF_LMA_MASK; 9846 } 9847 9848 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) { 9849 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; 9850 } else { 9851 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >> 9852 (DESC_B_SHIFT - HF_CS32_SHIFT); 9853 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >> 9854 (DESC_B_SHIFT - HF_SS32_SHIFT); 9855 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) || 9856 !(hflags & HF_CS32_MASK)) { 9857 hflags |= HF_ADDSEG_MASK; 9858 } else { 9859 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base | 9860 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT; 9861 } 9862 } 9863 env->hflags = hflags; 9864 } 9865 9866 static const Property x86_cpu_properties[] = { 9867 #ifdef CONFIG_USER_ONLY 9868 /* apic_id = 0 by default for *-user, see commit 9886e834 */ 9869 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0), 9870 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0), 9871 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0), 9872 DEFINE_PROP_INT32("module-id", X86CPU, module_id, 0), 9873 DEFINE_PROP_INT32("die-id", X86CPU, die_id, 0), 9874 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0), 9875 #else 9876 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID), 9877 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1), 9878 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1), 9879 DEFINE_PROP_INT32("module-id", X86CPU, module_id, -1), 9880 DEFINE_PROP_INT32("die-id", X86CPU, die_id, -1), 9881 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1), 9882 #endif 9883 DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID), 9884 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false), 9885 DEFINE_PROP_UINT64_CHECKMASK("lbr-fmt", X86CPU, lbr_fmt, PERF_CAP_LBR_FMT), 9886 9887 DEFINE_PROP_UINT32("hv-spinlocks", X86CPU, hyperv_spinlock_attempts, 9888 HYPERV_SPINLOCK_NEVER_NOTIFY), 9889 DEFINE_PROP_BIT64("hv-relaxed", X86CPU, hyperv_features, 9890 HYPERV_FEAT_RELAXED, 0), 9891 DEFINE_PROP_BIT64("hv-vapic", X86CPU, hyperv_features, 9892 HYPERV_FEAT_VAPIC, 0), 9893 DEFINE_PROP_BIT64("hv-time", X86CPU, hyperv_features, 9894 HYPERV_FEAT_TIME, 0), 9895 DEFINE_PROP_BIT64("hv-crash", X86CPU, hyperv_features, 9896 HYPERV_FEAT_CRASH, 0), 9897 DEFINE_PROP_BIT64("hv-reset", X86CPU, hyperv_features, 9898 HYPERV_FEAT_RESET, 0), 9899 DEFINE_PROP_BIT64("hv-vpindex", X86CPU, hyperv_features, 9900 HYPERV_FEAT_VPINDEX, 0), 9901 DEFINE_PROP_BIT64("hv-runtime", X86CPU, hyperv_features, 9902 HYPERV_FEAT_RUNTIME, 0), 9903 DEFINE_PROP_BIT64("hv-synic", X86CPU, hyperv_features, 9904 HYPERV_FEAT_SYNIC, 0), 9905 DEFINE_PROP_BIT64("hv-stimer", X86CPU, hyperv_features, 9906 HYPERV_FEAT_STIMER, 0), 9907 DEFINE_PROP_BIT64("hv-frequencies", X86CPU, hyperv_features, 9908 HYPERV_FEAT_FREQUENCIES, 0), 9909 DEFINE_PROP_BIT64("hv-reenlightenment", X86CPU, hyperv_features, 9910 HYPERV_FEAT_REENLIGHTENMENT, 0), 9911 DEFINE_PROP_BIT64("hv-tlbflush", X86CPU, hyperv_features, 9912 HYPERV_FEAT_TLBFLUSH, 0), 9913 DEFINE_PROP_BIT64("hv-evmcs", X86CPU, hyperv_features, 9914 HYPERV_FEAT_EVMCS, 0), 9915 DEFINE_PROP_BIT64("hv-ipi", X86CPU, hyperv_features, 9916 HYPERV_FEAT_IPI, 0), 9917 DEFINE_PROP_BIT64("hv-stimer-direct", X86CPU, hyperv_features, 9918 HYPERV_FEAT_STIMER_DIRECT, 0), 9919 DEFINE_PROP_BIT64("hv-avic", X86CPU, hyperv_features, 9920 HYPERV_FEAT_AVIC, 0), 9921 DEFINE_PROP_BIT64("hv-emsr-bitmap", X86CPU, hyperv_features, 9922 HYPERV_FEAT_MSR_BITMAP, 0), 9923 DEFINE_PROP_BIT64("hv-xmm-input", X86CPU, hyperv_features, 9924 HYPERV_FEAT_XMM_INPUT, 0), 9925 DEFINE_PROP_BIT64("hv-tlbflush-ext", X86CPU, hyperv_features, 9926 HYPERV_FEAT_TLBFLUSH_EXT, 0), 9927 DEFINE_PROP_BIT64("hv-tlbflush-direct", X86CPU, hyperv_features, 9928 HYPERV_FEAT_TLBFLUSH_DIRECT, 0), 9929 DEFINE_PROP_ON_OFF_AUTO("hv-no-nonarch-coresharing", X86CPU, 9930 hyperv_no_nonarch_cs, ON_OFF_AUTO_OFF), 9931 #ifdef CONFIG_SYNDBG 9932 DEFINE_PROP_BIT64("hv-syndbg", X86CPU, hyperv_features, 9933 HYPERV_FEAT_SYNDBG, 0), 9934 #endif 9935 DEFINE_PROP_BOOL("hv-passthrough", X86CPU, hyperv_passthrough, false), 9936 DEFINE_PROP_BOOL("hv-enforce-cpuid", X86CPU, hyperv_enforce_cpuid, false), 9937 9938 /* WS2008R2 identify by default */ 9939 DEFINE_PROP_UINT32("hv-version-id-build", X86CPU, hyperv_ver_id_build, 9940 0x3839), 9941 DEFINE_PROP_UINT16("hv-version-id-major", X86CPU, hyperv_ver_id_major, 9942 0x000A), 9943 DEFINE_PROP_UINT16("hv-version-id-minor", X86CPU, hyperv_ver_id_minor, 9944 0x0000), 9945 DEFINE_PROP_UINT32("hv-version-id-spack", X86CPU, hyperv_ver_id_sp, 0), 9946 DEFINE_PROP_UINT8("hv-version-id-sbranch", X86CPU, hyperv_ver_id_sb, 0), 9947 DEFINE_PROP_UINT32("hv-version-id-snumber", X86CPU, hyperv_ver_id_sn, 0), 9948 9949 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true), 9950 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false), 9951 DEFINE_PROP_BOOL("x-force-features", X86CPU, force_features, false), 9952 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true), 9953 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0), 9954 DEFINE_PROP_UINT32("guest-phys-bits", X86CPU, guest_phys_bits, -1), 9955 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false), 9956 DEFINE_PROP_UINT8("host-phys-bits-limit", X86CPU, host_phys_bits_limit, 0), 9957 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true), 9958 DEFINE_PROP_UINT32("level-func7", X86CPU, env.cpuid_level_func7, 9959 UINT32_MAX), 9960 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX), 9961 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX), 9962 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX), 9963 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0), 9964 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0), 9965 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0), 9966 DEFINE_PROP_UINT8("avx10-version", X86CPU, env.avx10_version, 0), 9967 DEFINE_PROP_UINT64("ucode-rev", X86CPU, ucode_rev, 0), 9968 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true), 9969 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor), 9970 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true), 9971 DEFINE_PROP_BOOL("x-vendor-cpuid-only", X86CPU, vendor_cpuid_only, true), 9972 DEFINE_PROP_BOOL("x-vendor-cpuid-only-v2", X86CPU, vendor_cpuid_only_v2, true), 9973 DEFINE_PROP_BOOL("x-amd-topoext-features-only", X86CPU, amd_topoext_features_only, true), 9974 DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false), 9975 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true), 9976 DEFINE_PROP_BOOL("kvm-pv-enforce-cpuid", X86CPU, kvm_pv_enforce_cpuid, 9977 false), 9978 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true), 9979 DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true), 9980 DEFINE_PROP_BOOL("x-migrate-smi-count", X86CPU, migrate_smi_count, 9981 true), 9982 /* 9983 * lecacy_cache defaults to true unless the CPU model provides its 9984 * own cache information (see x86_cpu_load_def()). 9985 */ 9986 DEFINE_PROP_BOOL("legacy-cache", X86CPU, legacy_cache, true), 9987 DEFINE_PROP_BOOL("x-consistent-cache", X86CPU, consistent_cache, true), 9988 DEFINE_PROP_BOOL("legacy-multi-node", X86CPU, legacy_multi_node, false), 9989 DEFINE_PROP_BOOL("xen-vapic", X86CPU, xen_vapic, false), 9990 9991 /* 9992 * From "Requirements for Implementing the Microsoft 9993 * Hypervisor Interface": 9994 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs 9995 * 9996 * "Starting with Windows Server 2012 and Windows 8, if 9997 * CPUID.40000005.EAX contains a value of -1, Windows assumes that 9998 * the hypervisor imposes no specific limit to the number of VPs. 9999 * In this case, Windows Server 2012 guest VMs may use more than 10000 * 64 VPs, up to the maximum supported number of processors applicable 10001 * to the specific Windows version being used." 10002 */ 10003 DEFINE_PROP_INT32("x-hv-max-vps", X86CPU, hv_max_vps, -1), 10004 DEFINE_PROP_BOOL("x-hv-synic-kvm-only", X86CPU, hyperv_synic_kvm_only, 10005 false), 10006 DEFINE_PROP_BOOL("x-intel-pt-auto-level", X86CPU, intel_pt_auto_level, 10007 true), 10008 DEFINE_PROP_BOOL("x-l1-cache-per-thread", X86CPU, l1_cache_per_core, true), 10009 DEFINE_PROP_BOOL("x-force-cpuid-0x1f", X86CPU, force_cpuid_0x1f, false), 10010 }; 10011 10012 #ifndef CONFIG_USER_ONLY 10013 #include "hw/core/sysemu-cpu-ops.h" 10014 10015 static const struct SysemuCPUOps i386_sysemu_ops = { 10016 .has_work = x86_cpu_has_work, 10017 .get_memory_mapping = x86_cpu_get_memory_mapping, 10018 .get_paging_enabled = x86_cpu_get_paging_enabled, 10019 .get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug, 10020 .asidx_from_attrs = x86_asidx_from_attrs, 10021 .get_crash_info = x86_cpu_get_crash_info, 10022 .write_elf32_note = x86_cpu_write_elf32_note, 10023 .write_elf64_note = x86_cpu_write_elf64_note, 10024 .write_elf32_qemunote = x86_cpu_write_elf32_qemunote, 10025 .write_elf64_qemunote = x86_cpu_write_elf64_qemunote, 10026 .legacy_vmsd = &vmstate_x86_cpu, 10027 }; 10028 #endif 10029 10030 static void x86_cpu_common_class_init(ObjectClass *oc, const void *data) 10031 { 10032 X86CPUClass *xcc = X86_CPU_CLASS(oc); 10033 CPUClass *cc = CPU_CLASS(oc); 10034 DeviceClass *dc = DEVICE_CLASS(oc); 10035 ResettableClass *rc = RESETTABLE_CLASS(oc); 10036 FeatureWord w; 10037 10038 device_class_set_parent_realize(dc, x86_cpu_realizefn, 10039 &xcc->parent_realize); 10040 device_class_set_parent_unrealize(dc, x86_cpu_unrealizefn, 10041 &xcc->parent_unrealize); 10042 device_class_set_props(dc, x86_cpu_properties); 10043 10044 resettable_class_set_parent_phases(rc, NULL, x86_cpu_reset_hold, NULL, 10045 &xcc->parent_phases); 10046 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP; 10047 10048 cc->class_by_name = x86_cpu_class_by_name; 10049 cc->list_cpus = x86_cpu_list; 10050 cc->parse_features = x86_cpu_parse_featurestr; 10051 cc->dump_state = x86_cpu_dump_state; 10052 cc->set_pc = x86_cpu_set_pc; 10053 cc->get_pc = x86_cpu_get_pc; 10054 cc->gdb_read_register = x86_cpu_gdb_read_register; 10055 cc->gdb_write_register = x86_cpu_gdb_write_register; 10056 cc->get_arch_id = x86_cpu_get_arch_id; 10057 10058 #ifndef CONFIG_USER_ONLY 10059 cc->sysemu_ops = &i386_sysemu_ops; 10060 #endif /* !CONFIG_USER_ONLY */ 10061 #ifdef CONFIG_TCG 10062 cc->tcg_ops = &x86_tcg_ops; 10063 #endif /* CONFIG_TCG */ 10064 10065 cc->gdb_arch_name = x86_gdb_arch_name; 10066 #ifdef TARGET_X86_64 10067 cc->gdb_core_xml_file = "i386-64bit.xml"; 10068 #else 10069 cc->gdb_core_xml_file = "i386-32bit.xml"; 10070 #endif 10071 cc->disas_set_info = x86_disas_set_info; 10072 10073 dc->user_creatable = true; 10074 10075 object_class_property_add(oc, "family", "int", 10076 x86_cpuid_version_get_family, 10077 x86_cpuid_version_set_family, NULL, NULL); 10078 object_class_property_add(oc, "model", "int", 10079 x86_cpuid_version_get_model, 10080 x86_cpuid_version_set_model, NULL, NULL); 10081 object_class_property_add(oc, "stepping", "int", 10082 x86_cpuid_version_get_stepping, 10083 x86_cpuid_version_set_stepping, NULL, NULL); 10084 object_class_property_add_str(oc, "vendor", 10085 x86_cpuid_get_vendor, 10086 x86_cpuid_set_vendor); 10087 object_class_property_add_str(oc, "model-id", 10088 x86_cpuid_get_model_id, 10089 x86_cpuid_set_model_id); 10090 object_class_property_add(oc, "tsc-frequency", "int", 10091 x86_cpuid_get_tsc_freq, 10092 x86_cpuid_set_tsc_freq, NULL, NULL); 10093 /* 10094 * The "unavailable-features" property has the same semantics as 10095 * CpuDefinitionInfo.unavailable-features on the "query-cpu-definitions" 10096 * QMP command: they list the features that would have prevented the 10097 * CPU from running if the "enforce" flag was set. 10098 */ 10099 object_class_property_add(oc, "unavailable-features", "strList", 10100 x86_cpu_get_unavailable_features, 10101 NULL, NULL, NULL); 10102 10103 #if !defined(CONFIG_USER_ONLY) 10104 object_class_property_add(oc, "crash-information", "GuestPanicInformation", 10105 x86_cpu_get_crash_info_qom, NULL, NULL, NULL); 10106 #endif 10107 10108 for (w = 0; w < FEATURE_WORDS; w++) { 10109 int bitnr; 10110 for (bitnr = 0; bitnr < 64; bitnr++) { 10111 x86_cpu_register_feature_bit_props(xcc, w, bitnr); 10112 } 10113 } 10114 } 10115 10116 static const TypeInfo x86_cpu_type_info = { 10117 .name = TYPE_X86_CPU, 10118 .parent = TYPE_CPU, 10119 .instance_size = sizeof(X86CPU), 10120 .instance_align = __alignof(X86CPU), 10121 .instance_init = x86_cpu_initfn, 10122 .instance_post_init = x86_cpu_post_initfn, 10123 10124 .abstract = true, 10125 .class_size = sizeof(X86CPUClass), 10126 .class_init = x86_cpu_common_class_init, 10127 }; 10128 10129 /* "base" CPU model, used by query-cpu-model-expansion */ 10130 static void x86_cpu_base_class_init(ObjectClass *oc, const void *data) 10131 { 10132 X86CPUClass *xcc = X86_CPU_CLASS(oc); 10133 10134 xcc->static_model = true; 10135 xcc->migration_safe = true; 10136 xcc->model_description = "base CPU model type with no features enabled"; 10137 xcc->ordering = 8; 10138 } 10139 10140 static const TypeInfo x86_base_cpu_type_info = { 10141 .name = X86_CPU_TYPE_NAME("base"), 10142 .parent = TYPE_X86_CPU, 10143 .class_init = x86_cpu_base_class_init, 10144 }; 10145 10146 static void x86_cpu_register_types(void) 10147 { 10148 int i; 10149 10150 type_register_static(&x86_cpu_type_info); 10151 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) { 10152 x86_register_cpudef_types(&builtin_x86_defs[i]); 10153 } 10154 type_register_static(&max_x86_cpu_type_info); 10155 type_register_static(&x86_base_cpu_type_info); 10156 } 10157 10158 type_init(x86_cpu_register_types) 10159