1 /* 2 * i386 CPUID, CPU class, definitions, models 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/units.h" 22 #include "qemu/cutils.h" 23 #include "qemu/qemu-print.h" 24 #include "qemu/hw-version.h" 25 #include "cpu.h" 26 #include "tcg/helper-tcg.h" 27 #include "sysemu/reset.h" 28 #include "sysemu/hvf.h" 29 #include "kvm/kvm_i386.h" 30 #include "sev.h" 31 #include "qapi/error.h" 32 #include "qemu/error-report.h" 33 #include "qapi/qapi-visit-machine.h" 34 #include "qapi/qmp/qerror.h" 35 #include "standard-headers/asm-x86/kvm_para.h" 36 #include "hw/qdev-properties.h" 37 #include "hw/i386/topology.h" 38 #ifndef CONFIG_USER_ONLY 39 #include "qapi/qapi-commands-machine-target.h" 40 #include "exec/address-spaces.h" 41 #include "hw/boards.h" 42 #include "hw/i386/sgx-epc.h" 43 #endif 44 45 #include "disas/capstone.h" 46 #include "cpu-internal.h" 47 48 static void x86_cpu_realizefn(DeviceState *dev, Error **errp); 49 50 /* Helpers for building CPUID[2] descriptors: */ 51 52 struct CPUID2CacheDescriptorInfo { 53 enum CacheType type; 54 int level; 55 int size; 56 int line_size; 57 int associativity; 58 }; 59 60 /* 61 * Known CPUID 2 cache descriptors. 62 * From Intel SDM Volume 2A, CPUID instruction 63 */ 64 struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = { 65 [0x06] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 8 * KiB, 66 .associativity = 4, .line_size = 32, }, 67 [0x08] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 16 * KiB, 68 .associativity = 4, .line_size = 32, }, 69 [0x09] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB, 70 .associativity = 4, .line_size = 64, }, 71 [0x0A] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB, 72 .associativity = 2, .line_size = 32, }, 73 [0x0C] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 74 .associativity = 4, .line_size = 32, }, 75 [0x0D] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 76 .associativity = 4, .line_size = 64, }, 77 [0x0E] = { .level = 1, .type = DATA_CACHE, .size = 24 * KiB, 78 .associativity = 6, .line_size = 64, }, 79 [0x1D] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB, 80 .associativity = 2, .line_size = 64, }, 81 [0x21] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 82 .associativity = 8, .line_size = 64, }, 83 /* lines per sector is not supported cpuid2_cache_descriptor(), 84 * so descriptors 0x22, 0x23 are not included 85 */ 86 [0x24] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 87 .associativity = 16, .line_size = 64, }, 88 /* lines per sector is not supported cpuid2_cache_descriptor(), 89 * so descriptors 0x25, 0x20 are not included 90 */ 91 [0x2C] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB, 92 .associativity = 8, .line_size = 64, }, 93 [0x30] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB, 94 .associativity = 8, .line_size = 64, }, 95 [0x41] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB, 96 .associativity = 4, .line_size = 32, }, 97 [0x42] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 98 .associativity = 4, .line_size = 32, }, 99 [0x43] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 100 .associativity = 4, .line_size = 32, }, 101 [0x44] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 102 .associativity = 4, .line_size = 32, }, 103 [0x45] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 104 .associativity = 4, .line_size = 32, }, 105 [0x46] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 106 .associativity = 4, .line_size = 64, }, 107 [0x47] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 108 .associativity = 8, .line_size = 64, }, 109 [0x48] = { .level = 2, .type = UNIFIED_CACHE, .size = 3 * MiB, 110 .associativity = 12, .line_size = 64, }, 111 /* Descriptor 0x49 depends on CPU family/model, so it is not included */ 112 [0x4A] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB, 113 .associativity = 12, .line_size = 64, }, 114 [0x4B] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 115 .associativity = 16, .line_size = 64, }, 116 [0x4C] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB, 117 .associativity = 12, .line_size = 64, }, 118 [0x4D] = { .level = 3, .type = UNIFIED_CACHE, .size = 16 * MiB, 119 .associativity = 16, .line_size = 64, }, 120 [0x4E] = { .level = 2, .type = UNIFIED_CACHE, .size = 6 * MiB, 121 .associativity = 24, .line_size = 64, }, 122 [0x60] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 123 .associativity = 8, .line_size = 64, }, 124 [0x66] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB, 125 .associativity = 4, .line_size = 64, }, 126 [0x67] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 127 .associativity = 4, .line_size = 64, }, 128 [0x68] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB, 129 .associativity = 4, .line_size = 64, }, 130 [0x78] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 131 .associativity = 4, .line_size = 64, }, 132 /* lines per sector is not supported cpuid2_cache_descriptor(), 133 * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included. 134 */ 135 [0x7D] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 136 .associativity = 8, .line_size = 64, }, 137 [0x7F] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 138 .associativity = 2, .line_size = 64, }, 139 [0x80] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 140 .associativity = 8, .line_size = 64, }, 141 [0x82] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 142 .associativity = 8, .line_size = 32, }, 143 [0x83] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 144 .associativity = 8, .line_size = 32, }, 145 [0x84] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 146 .associativity = 8, .line_size = 32, }, 147 [0x85] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 148 .associativity = 8, .line_size = 32, }, 149 [0x86] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 150 .associativity = 4, .line_size = 64, }, 151 [0x87] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 152 .associativity = 8, .line_size = 64, }, 153 [0xD0] = { .level = 3, .type = UNIFIED_CACHE, .size = 512 * KiB, 154 .associativity = 4, .line_size = 64, }, 155 [0xD1] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB, 156 .associativity = 4, .line_size = 64, }, 157 [0xD2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 158 .associativity = 4, .line_size = 64, }, 159 [0xD6] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB, 160 .associativity = 8, .line_size = 64, }, 161 [0xD7] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 162 .associativity = 8, .line_size = 64, }, 163 [0xD8] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 164 .associativity = 8, .line_size = 64, }, 165 [0xDC] = { .level = 3, .type = UNIFIED_CACHE, .size = 1.5 * MiB, 166 .associativity = 12, .line_size = 64, }, 167 [0xDD] = { .level = 3, .type = UNIFIED_CACHE, .size = 3 * MiB, 168 .associativity = 12, .line_size = 64, }, 169 [0xDE] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB, 170 .associativity = 12, .line_size = 64, }, 171 [0xE2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 172 .associativity = 16, .line_size = 64, }, 173 [0xE3] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 174 .associativity = 16, .line_size = 64, }, 175 [0xE4] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 176 .associativity = 16, .line_size = 64, }, 177 [0xEA] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB, 178 .associativity = 24, .line_size = 64, }, 179 [0xEB] = { .level = 3, .type = UNIFIED_CACHE, .size = 18 * MiB, 180 .associativity = 24, .line_size = 64, }, 181 [0xEC] = { .level = 3, .type = UNIFIED_CACHE, .size = 24 * MiB, 182 .associativity = 24, .line_size = 64, }, 183 }; 184 185 /* 186 * "CPUID leaf 2 does not report cache descriptor information, 187 * use CPUID leaf 4 to query cache parameters" 188 */ 189 #define CACHE_DESCRIPTOR_UNAVAILABLE 0xFF 190 191 /* 192 * Return a CPUID 2 cache descriptor for a given cache. 193 * If no known descriptor is found, return CACHE_DESCRIPTOR_UNAVAILABLE 194 */ 195 static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache) 196 { 197 int i; 198 199 assert(cache->size > 0); 200 assert(cache->level > 0); 201 assert(cache->line_size > 0); 202 assert(cache->associativity > 0); 203 for (i = 0; i < ARRAY_SIZE(cpuid2_cache_descriptors); i++) { 204 struct CPUID2CacheDescriptorInfo *d = &cpuid2_cache_descriptors[i]; 205 if (d->level == cache->level && d->type == cache->type && 206 d->size == cache->size && d->line_size == cache->line_size && 207 d->associativity == cache->associativity) { 208 return i; 209 } 210 } 211 212 return CACHE_DESCRIPTOR_UNAVAILABLE; 213 } 214 215 /* CPUID Leaf 4 constants: */ 216 217 /* EAX: */ 218 #define CACHE_TYPE_D 1 219 #define CACHE_TYPE_I 2 220 #define CACHE_TYPE_UNIFIED 3 221 222 #define CACHE_LEVEL(l) (l << 5) 223 224 #define CACHE_SELF_INIT_LEVEL (1 << 8) 225 226 /* EDX: */ 227 #define CACHE_NO_INVD_SHARING (1 << 0) 228 #define CACHE_INCLUSIVE (1 << 1) 229 #define CACHE_COMPLEX_IDX (1 << 2) 230 231 /* Encode CacheType for CPUID[4].EAX */ 232 #define CACHE_TYPE(t) (((t) == DATA_CACHE) ? CACHE_TYPE_D : \ 233 ((t) == INSTRUCTION_CACHE) ? CACHE_TYPE_I : \ 234 ((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \ 235 0 /* Invalid value */) 236 237 238 /* Encode cache info for CPUID[4] */ 239 static void encode_cache_cpuid4(CPUCacheInfo *cache, 240 int num_apic_ids, int num_cores, 241 uint32_t *eax, uint32_t *ebx, 242 uint32_t *ecx, uint32_t *edx) 243 { 244 assert(cache->size == cache->line_size * cache->associativity * 245 cache->partitions * cache->sets); 246 247 assert(num_apic_ids > 0); 248 *eax = CACHE_TYPE(cache->type) | 249 CACHE_LEVEL(cache->level) | 250 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) | 251 ((num_cores - 1) << 26) | 252 ((num_apic_ids - 1) << 14); 253 254 assert(cache->line_size > 0); 255 assert(cache->partitions > 0); 256 assert(cache->associativity > 0); 257 /* We don't implement fully-associative caches */ 258 assert(cache->associativity < cache->sets); 259 *ebx = (cache->line_size - 1) | 260 ((cache->partitions - 1) << 12) | 261 ((cache->associativity - 1) << 22); 262 263 assert(cache->sets > 0); 264 *ecx = cache->sets - 1; 265 266 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) | 267 (cache->inclusive ? CACHE_INCLUSIVE : 0) | 268 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); 269 } 270 271 /* Encode cache info for CPUID[0x80000005].ECX or CPUID[0x80000005].EDX */ 272 static uint32_t encode_cache_cpuid80000005(CPUCacheInfo *cache) 273 { 274 assert(cache->size % 1024 == 0); 275 assert(cache->lines_per_tag > 0); 276 assert(cache->associativity > 0); 277 assert(cache->line_size > 0); 278 return ((cache->size / 1024) << 24) | (cache->associativity << 16) | 279 (cache->lines_per_tag << 8) | (cache->line_size); 280 } 281 282 #define ASSOC_FULL 0xFF 283 284 /* AMD associativity encoding used on CPUID Leaf 0x80000006: */ 285 #define AMD_ENC_ASSOC(a) (a <= 1 ? a : \ 286 a == 2 ? 0x2 : \ 287 a == 4 ? 0x4 : \ 288 a == 8 ? 0x6 : \ 289 a == 16 ? 0x8 : \ 290 a == 32 ? 0xA : \ 291 a == 48 ? 0xB : \ 292 a == 64 ? 0xC : \ 293 a == 96 ? 0xD : \ 294 a == 128 ? 0xE : \ 295 a == ASSOC_FULL ? 0xF : \ 296 0 /* invalid value */) 297 298 /* 299 * Encode cache info for CPUID[0x80000006].ECX and CPUID[0x80000006].EDX 300 * @l3 can be NULL. 301 */ 302 static void encode_cache_cpuid80000006(CPUCacheInfo *l2, 303 CPUCacheInfo *l3, 304 uint32_t *ecx, uint32_t *edx) 305 { 306 assert(l2->size % 1024 == 0); 307 assert(l2->associativity > 0); 308 assert(l2->lines_per_tag > 0); 309 assert(l2->line_size > 0); 310 *ecx = ((l2->size / 1024) << 16) | 311 (AMD_ENC_ASSOC(l2->associativity) << 12) | 312 (l2->lines_per_tag << 8) | (l2->line_size); 313 314 if (l3) { 315 assert(l3->size % (512 * 1024) == 0); 316 assert(l3->associativity > 0); 317 assert(l3->lines_per_tag > 0); 318 assert(l3->line_size > 0); 319 *edx = ((l3->size / (512 * 1024)) << 18) | 320 (AMD_ENC_ASSOC(l3->associativity) << 12) | 321 (l3->lines_per_tag << 8) | (l3->line_size); 322 } else { 323 *edx = 0; 324 } 325 } 326 327 /* Encode cache info for CPUID[8000001D] */ 328 static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, 329 X86CPUTopoInfo *topo_info, 330 uint32_t *eax, uint32_t *ebx, 331 uint32_t *ecx, uint32_t *edx) 332 { 333 uint32_t l3_threads; 334 assert(cache->size == cache->line_size * cache->associativity * 335 cache->partitions * cache->sets); 336 337 *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) | 338 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0); 339 340 /* L3 is shared among multiple cores */ 341 if (cache->level == 3) { 342 l3_threads = topo_info->cores_per_die * topo_info->threads_per_core; 343 *eax |= (l3_threads - 1) << 14; 344 } else { 345 *eax |= ((topo_info->threads_per_core - 1) << 14); 346 } 347 348 assert(cache->line_size > 0); 349 assert(cache->partitions > 0); 350 assert(cache->associativity > 0); 351 /* We don't implement fully-associative caches */ 352 assert(cache->associativity < cache->sets); 353 *ebx = (cache->line_size - 1) | 354 ((cache->partitions - 1) << 12) | 355 ((cache->associativity - 1) << 22); 356 357 assert(cache->sets > 0); 358 *ecx = cache->sets - 1; 359 360 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) | 361 (cache->inclusive ? CACHE_INCLUSIVE : 0) | 362 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); 363 } 364 365 /* Encode cache info for CPUID[8000001E] */ 366 static void encode_topo_cpuid8000001e(X86CPU *cpu, X86CPUTopoInfo *topo_info, 367 uint32_t *eax, uint32_t *ebx, 368 uint32_t *ecx, uint32_t *edx) 369 { 370 X86CPUTopoIDs topo_ids; 371 372 x86_topo_ids_from_apicid(cpu->apic_id, topo_info, &topo_ids); 373 374 *eax = cpu->apic_id; 375 376 /* 377 * CPUID_Fn8000001E_EBX [Core Identifiers] (CoreId) 378 * Read-only. Reset: 0000_XXXXh. 379 * See Core::X86::Cpuid::ExtApicId. 380 * Core::X86::Cpuid::CoreId_lthree[1:0]_core[3:0]_thread[1:0]; 381 * Bits Description 382 * 31:16 Reserved. 383 * 15:8 ThreadsPerCore: threads per core. Read-only. Reset: XXh. 384 * The number of threads per core is ThreadsPerCore+1. 385 * 7:0 CoreId: core ID. Read-only. Reset: XXh. 386 * 387 * NOTE: CoreId is already part of apic_id. Just use it. We can 388 * use all the 8 bits to represent the core_id here. 389 */ 390 *ebx = ((topo_info->threads_per_core - 1) << 8) | (topo_ids.core_id & 0xFF); 391 392 /* 393 * CPUID_Fn8000001E_ECX [Node Identifiers] (NodeId) 394 * Read-only. Reset: 0000_0XXXh. 395 * Core::X86::Cpuid::NodeId_lthree[1:0]_core[3:0]_thread[1:0]; 396 * Bits Description 397 * 31:11 Reserved. 398 * 10:8 NodesPerProcessor: Node per processor. Read-only. Reset: XXXb. 399 * ValidValues: 400 * Value Description 401 * 000b 1 node per processor. 402 * 001b 2 nodes per processor. 403 * 010b Reserved. 404 * 011b 4 nodes per processor. 405 * 111b-100b Reserved. 406 * 7:0 NodeId: Node ID. Read-only. Reset: XXh. 407 * 408 * NOTE: Hardware reserves 3 bits for number of nodes per processor. 409 * But users can create more nodes than the actual hardware can 410 * support. To genaralize we can use all the upper 8 bits for nodes. 411 * NodeId is combination of node and socket_id which is already decoded 412 * in apic_id. Just use it by shifting. 413 */ 414 *ecx = ((topo_info->dies_per_pkg - 1) << 8) | 415 ((cpu->apic_id >> apicid_die_offset(topo_info)) & 0xFF); 416 417 *edx = 0; 418 } 419 420 /* 421 * Definitions of the hardcoded cache entries we expose: 422 * These are legacy cache values. If there is a need to change any 423 * of these values please use builtin_x86_defs 424 */ 425 426 /* L1 data cache: */ 427 static CPUCacheInfo legacy_l1d_cache = { 428 .type = DATA_CACHE, 429 .level = 1, 430 .size = 32 * KiB, 431 .self_init = 1, 432 .line_size = 64, 433 .associativity = 8, 434 .sets = 64, 435 .partitions = 1, 436 .no_invd_sharing = true, 437 }; 438 439 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ 440 static CPUCacheInfo legacy_l1d_cache_amd = { 441 .type = DATA_CACHE, 442 .level = 1, 443 .size = 64 * KiB, 444 .self_init = 1, 445 .line_size = 64, 446 .associativity = 2, 447 .sets = 512, 448 .partitions = 1, 449 .lines_per_tag = 1, 450 .no_invd_sharing = true, 451 }; 452 453 /* L1 instruction cache: */ 454 static CPUCacheInfo legacy_l1i_cache = { 455 .type = INSTRUCTION_CACHE, 456 .level = 1, 457 .size = 32 * KiB, 458 .self_init = 1, 459 .line_size = 64, 460 .associativity = 8, 461 .sets = 64, 462 .partitions = 1, 463 .no_invd_sharing = true, 464 }; 465 466 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ 467 static CPUCacheInfo legacy_l1i_cache_amd = { 468 .type = INSTRUCTION_CACHE, 469 .level = 1, 470 .size = 64 * KiB, 471 .self_init = 1, 472 .line_size = 64, 473 .associativity = 2, 474 .sets = 512, 475 .partitions = 1, 476 .lines_per_tag = 1, 477 .no_invd_sharing = true, 478 }; 479 480 /* Level 2 unified cache: */ 481 static CPUCacheInfo legacy_l2_cache = { 482 .type = UNIFIED_CACHE, 483 .level = 2, 484 .size = 4 * MiB, 485 .self_init = 1, 486 .line_size = 64, 487 .associativity = 16, 488 .sets = 4096, 489 .partitions = 1, 490 .no_invd_sharing = true, 491 }; 492 493 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */ 494 static CPUCacheInfo legacy_l2_cache_cpuid2 = { 495 .type = UNIFIED_CACHE, 496 .level = 2, 497 .size = 2 * MiB, 498 .line_size = 64, 499 .associativity = 8, 500 }; 501 502 503 /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */ 504 static CPUCacheInfo legacy_l2_cache_amd = { 505 .type = UNIFIED_CACHE, 506 .level = 2, 507 .size = 512 * KiB, 508 .line_size = 64, 509 .lines_per_tag = 1, 510 .associativity = 16, 511 .sets = 512, 512 .partitions = 1, 513 }; 514 515 /* Level 3 unified cache: */ 516 static CPUCacheInfo legacy_l3_cache = { 517 .type = UNIFIED_CACHE, 518 .level = 3, 519 .size = 16 * MiB, 520 .line_size = 64, 521 .associativity = 16, 522 .sets = 16384, 523 .partitions = 1, 524 .lines_per_tag = 1, 525 .self_init = true, 526 .inclusive = true, 527 .complex_indexing = true, 528 }; 529 530 /* TLB definitions: */ 531 532 #define L1_DTLB_2M_ASSOC 1 533 #define L1_DTLB_2M_ENTRIES 255 534 #define L1_DTLB_4K_ASSOC 1 535 #define L1_DTLB_4K_ENTRIES 255 536 537 #define L1_ITLB_2M_ASSOC 1 538 #define L1_ITLB_2M_ENTRIES 255 539 #define L1_ITLB_4K_ASSOC 1 540 #define L1_ITLB_4K_ENTRIES 255 541 542 #define L2_DTLB_2M_ASSOC 0 /* disabled */ 543 #define L2_DTLB_2M_ENTRIES 0 /* disabled */ 544 #define L2_DTLB_4K_ASSOC 4 545 #define L2_DTLB_4K_ENTRIES 512 546 547 #define L2_ITLB_2M_ASSOC 0 /* disabled */ 548 #define L2_ITLB_2M_ENTRIES 0 /* disabled */ 549 #define L2_ITLB_4K_ASSOC 4 550 #define L2_ITLB_4K_ENTRIES 512 551 552 /* CPUID Leaf 0x14 constants: */ 553 #define INTEL_PT_MAX_SUBLEAF 0x1 554 /* 555 * bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MATCH 556 * MSR can be accessed; 557 * bit[01]: Support Configurable PSB and Cycle-Accurate Mode; 558 * bit[02]: Support IP Filtering, TraceStop filtering, and preservation 559 * of Intel PT MSRs across warm reset; 560 * bit[03]: Support MTC timing packet and suppression of COFI-based packets; 561 */ 562 #define INTEL_PT_MINIMAL_EBX 0xf 563 /* 564 * bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 and 565 * IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be 566 * accessed; 567 * bit[01]: ToPA tables can hold any number of output entries, up to the 568 * maximum allowed by the MaskOrTableOffset field of 569 * IA32_RTIT_OUTPUT_MASK_PTRS; 570 * bit[02]: Support Single-Range Output scheme; 571 */ 572 #define INTEL_PT_MINIMAL_ECX 0x7 573 /* generated packets which contain IP payloads have LIP values */ 574 #define INTEL_PT_IP_LIP (1 << 31) 575 #define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */ 576 #define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3 577 #define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */ 578 #define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */ 579 #define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */ 580 581 /* CPUID Leaf 0x1D constants: */ 582 #define INTEL_AMX_TILE_MAX_SUBLEAF 0x1 583 #define INTEL_AMX_TOTAL_TILE_BYTES 0x2000 584 #define INTEL_AMX_BYTES_PER_TILE 0x400 585 #define INTEL_AMX_BYTES_PER_ROW 0x40 586 #define INTEL_AMX_TILE_MAX_NAMES 0x8 587 #define INTEL_AMX_TILE_MAX_ROWS 0x10 588 589 /* CPUID Leaf 0x1E constants: */ 590 #define INTEL_AMX_TMUL_MAX_K 0x10 591 #define INTEL_AMX_TMUL_MAX_N 0x40 592 593 void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1, 594 uint32_t vendor2, uint32_t vendor3) 595 { 596 int i; 597 for (i = 0; i < 4; i++) { 598 dst[i] = vendor1 >> (8 * i); 599 dst[i + 4] = vendor2 >> (8 * i); 600 dst[i + 8] = vendor3 >> (8 * i); 601 } 602 dst[CPUID_VENDOR_SZ] = '\0'; 603 } 604 605 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE) 606 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \ 607 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC) 608 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \ 609 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ 610 CPUID_PSE36 | CPUID_FXSR) 611 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE) 612 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \ 613 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \ 614 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \ 615 CPUID_PAE | CPUID_SEP | CPUID_APIC) 616 617 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \ 618 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \ 619 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ 620 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \ 621 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE) 622 /* partly implemented: 623 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */ 624 /* missing: 625 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */ 626 627 /* 628 * Kernel-only features that can be shown to usermode programs even if 629 * they aren't actually supported by TCG, because qemu-user only runs 630 * in CPL=3; remove them if they are ever implemented for system emulation. 631 */ 632 #if defined CONFIG_USER_ONLY 633 #define CPUID_EXT_KERNEL_FEATURES (CPUID_EXT_PCID | CPUID_EXT_TSC_DEADLINE_TIMER | \ 634 CPUID_EXT_X2APIC) 635 #else 636 #define CPUID_EXT_KERNEL_FEATURES 0 637 #endif 638 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \ 639 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \ 640 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \ 641 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \ 642 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR | \ 643 CPUID_EXT_RDRAND | CPUID_EXT_AVX | CPUID_EXT_F16C | \ 644 CPUID_EXT_FMA | CPUID_EXT_KERNEL_FEATURES) 645 /* missing: 646 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX, 647 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, 648 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA, 649 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER */ 650 651 #ifdef TARGET_X86_64 652 #define TCG_EXT2_X86_64_FEATURES CPUID_EXT2_LM 653 #else 654 #define TCG_EXT2_X86_64_FEATURES 0 655 #endif 656 657 /* 658 * CPUID_*_KERNEL_FEATURES denotes bits and features that are not usable 659 * in usermode or by 32-bit programs. Those are added to supported 660 * TCG features unconditionally in user-mode emulation mode. This may 661 * indeed seem strange or incorrect, but it works because code running 662 * under usermode emulation cannot access them. 663 * 664 * Even for long mode, qemu-i386 is not running "a userspace program on a 665 * 32-bit CPU"; it's running "a userspace program with a 32-bit code segment" 666 * and therefore using the 32-bit ABI; the CPU itself might be 64-bit 667 * but again the difference is only visible in kernel mode. 668 */ 669 #if defined CONFIG_LINUX_USER 670 #define CPUID_EXT2_KERNEL_FEATURES (CPUID_EXT2_LM | CPUID_EXT2_FFXSR) 671 #elif defined CONFIG_USER_ONLY 672 /* FIXME: Long mode not yet supported for i386 bsd-user */ 673 #define CPUID_EXT2_KERNEL_FEATURES CPUID_EXT2_FFXSR 674 #else 675 #define CPUID_EXT2_KERNEL_FEATURES 0 676 #endif 677 678 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \ 679 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \ 680 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \ 681 CPUID_EXT2_SYSCALL | TCG_EXT2_X86_64_FEATURES | \ 682 CPUID_EXT2_KERNEL_FEATURES) 683 684 #if defined CONFIG_USER_ONLY 685 #define CPUID_EXT3_KERNEL_FEATURES CPUID_EXT3_OSVW 686 #else 687 #define CPUID_EXT3_KERNEL_FEATURES 0 688 #endif 689 690 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \ 691 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A | \ 692 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_KERNEL_FEATURES) 693 694 #define TCG_EXT4_FEATURES 0 695 696 #if defined CONFIG_USER_ONLY 697 #define CPUID_SVM_KERNEL_FEATURES (CPUID_SVM_NRIPSAVE | CPUID_SVM_VNMI) 698 #else 699 #define CPUID_SVM_KERNEL_FEATURES 0 700 #endif 701 #define TCG_SVM_FEATURES (CPUID_SVM_NPT | CPUID_SVM_VGIF | \ 702 CPUID_SVM_SVME_ADDR_CHK | CPUID_SVM_KERNEL_FEATURES) 703 704 #define TCG_KVM_FEATURES 0 705 706 #if defined CONFIG_USER_ONLY 707 #define CPUID_7_0_EBX_KERNEL_FEATURES CPUID_7_0_EBX_INVPCID 708 #else 709 #define CPUID_7_0_EBX_KERNEL_FEATURES 0 710 #endif 711 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \ 712 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \ 713 CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \ 714 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \ 715 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_RDSEED | \ 716 CPUID_7_0_EBX_KERNEL_FEATURES) 717 /* missing: 718 CPUID_7_0_EBX_HLE 719 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM */ 720 721 #if defined CONFIG_SOFTMMU || defined CONFIG_LINUX 722 #define TCG_7_0_ECX_RDPID CPUID_7_0_ECX_RDPID 723 #else 724 #define TCG_7_0_ECX_RDPID 0 725 #endif 726 #define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | \ 727 /* CPUID_7_0_ECX_OSPKE is dynamic */ \ 728 CPUID_7_0_ECX_LA57 | CPUID_7_0_ECX_PKS | CPUID_7_0_ECX_VAES | \ 729 TCG_7_0_ECX_RDPID) 730 731 #if defined CONFIG_USER_ONLY 732 #define CPUID_7_0_EDX_KERNEL_FEATURES (CPUID_7_0_EDX_SPEC_CTRL | \ 733 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD) 734 #else 735 #define CPUID_7_0_EDX_KERNEL_FEATURES 0 736 #endif 737 #define TCG_7_0_EDX_FEATURES (CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_KERNEL_FEATURES) 738 739 #define TCG_7_1_EAX_FEATURES (CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | \ 740 CPUID_7_1_EAX_FSRC) 741 #define TCG_7_1_EDX_FEATURES 0 742 #define TCG_APM_FEATURES 0 743 #define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT 744 #define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1) 745 /* missing: 746 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */ 747 #define TCG_14_0_ECX_FEATURES 0 748 #define TCG_SGX_12_0_EAX_FEATURES 0 749 #define TCG_SGX_12_0_EBX_FEATURES 0 750 #define TCG_SGX_12_1_EAX_FEATURES 0 751 752 #if defined CONFIG_USER_ONLY 753 #define CPUID_8000_0008_EBX_KERNEL_FEATURES (CPUID_8000_0008_EBX_IBPB | \ 754 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | \ 755 CPUID_8000_0008_EBX_STIBP_ALWAYS_ON | CPUID_8000_0008_EBX_AMD_SSBD | \ 756 CPUID_8000_0008_EBX_AMD_PSFD) 757 #else 758 #define CPUID_8000_0008_EBX_KERNEL_FEATURES 0 759 #endif 760 761 #define TCG_8000_0008_EBX (CPUID_8000_0008_EBX_XSAVEERPTR | \ 762 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_KERNEL_FEATURES) 763 764 FeatureWordInfo feature_word_info[FEATURE_WORDS] = { 765 [FEAT_1_EDX] = { 766 .type = CPUID_FEATURE_WORD, 767 .feat_names = { 768 "fpu", "vme", "de", "pse", 769 "tsc", "msr", "pae", "mce", 770 "cx8", "apic", NULL, "sep", 771 "mtrr", "pge", "mca", "cmov", 772 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */, 773 NULL, "ds" /* Intel dts */, "acpi", "mmx", 774 "fxsr", "sse", "sse2", "ss", 775 "ht" /* Intel htt */, "tm", "ia64", "pbe", 776 }, 777 .cpuid = {.eax = 1, .reg = R_EDX, }, 778 .tcg_features = TCG_FEATURES, 779 }, 780 [FEAT_1_ECX] = { 781 .type = CPUID_FEATURE_WORD, 782 .feat_names = { 783 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor", 784 "ds-cpl", "vmx", "smx", "est", 785 "tm2", "ssse3", "cid", NULL, 786 "fma", "cx16", "xtpr", "pdcm", 787 NULL, "pcid", "dca", "sse4.1", 788 "sse4.2", "x2apic", "movbe", "popcnt", 789 "tsc-deadline", "aes", "xsave", NULL /* osxsave */, 790 "avx", "f16c", "rdrand", "hypervisor", 791 }, 792 .cpuid = { .eax = 1, .reg = R_ECX, }, 793 .tcg_features = TCG_EXT_FEATURES, 794 }, 795 /* Feature names that are already defined on feature_name[] but 796 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their 797 * names on feat_names below. They are copied automatically 798 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD. 799 */ 800 [FEAT_8000_0001_EDX] = { 801 .type = CPUID_FEATURE_WORD, 802 .feat_names = { 803 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */, 804 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */, 805 NULL /* cx8 */, NULL /* apic */, NULL, "syscall", 806 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */, 807 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */, 808 "nx", NULL, "mmxext", NULL /* mmx */, 809 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp", 810 NULL, "lm", "3dnowext", "3dnow", 811 }, 812 .cpuid = { .eax = 0x80000001, .reg = R_EDX, }, 813 .tcg_features = TCG_EXT2_FEATURES, 814 }, 815 [FEAT_8000_0001_ECX] = { 816 .type = CPUID_FEATURE_WORD, 817 .feat_names = { 818 "lahf-lm", "cmp-legacy", "svm", "extapic", 819 "cr8legacy", "abm", "sse4a", "misalignsse", 820 "3dnowprefetch", "osvw", "ibs", "xop", 821 "skinit", "wdt", NULL, "lwp", 822 "fma4", "tce", NULL, "nodeid-msr", 823 NULL, "tbm", "topoext", "perfctr-core", 824 "perfctr-nb", NULL, NULL, NULL, 825 NULL, NULL, NULL, NULL, 826 }, 827 .cpuid = { .eax = 0x80000001, .reg = R_ECX, }, 828 .tcg_features = TCG_EXT3_FEATURES, 829 /* 830 * TOPOEXT is always allowed but can't be enabled blindly by 831 * "-cpu host", as it requires consistent cache topology info 832 * to be provided so it doesn't confuse guests. 833 */ 834 .no_autoenable_flags = CPUID_EXT3_TOPOEXT, 835 }, 836 [FEAT_C000_0001_EDX] = { 837 .type = CPUID_FEATURE_WORD, 838 .feat_names = { 839 NULL, NULL, "xstore", "xstore-en", 840 NULL, NULL, "xcrypt", "xcrypt-en", 841 "ace2", "ace2-en", "phe", "phe-en", 842 "pmm", "pmm-en", NULL, NULL, 843 NULL, NULL, NULL, NULL, 844 NULL, NULL, NULL, NULL, 845 NULL, NULL, NULL, NULL, 846 NULL, NULL, NULL, NULL, 847 }, 848 .cpuid = { .eax = 0xC0000001, .reg = R_EDX, }, 849 .tcg_features = TCG_EXT4_FEATURES, 850 }, 851 [FEAT_KVM] = { 852 .type = CPUID_FEATURE_WORD, 853 .feat_names = { 854 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock", 855 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt", 856 NULL, "kvm-pv-tlb-flush", NULL, "kvm-pv-ipi", 857 "kvm-poll-control", "kvm-pv-sched-yield", "kvm-asyncpf-int", "kvm-msi-ext-dest-id", 858 NULL, NULL, NULL, NULL, 859 NULL, NULL, NULL, NULL, 860 "kvmclock-stable-bit", NULL, NULL, NULL, 861 NULL, NULL, NULL, NULL, 862 }, 863 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EAX, }, 864 .tcg_features = TCG_KVM_FEATURES, 865 }, 866 [FEAT_KVM_HINTS] = { 867 .type = CPUID_FEATURE_WORD, 868 .feat_names = { 869 "kvm-hint-dedicated", NULL, NULL, NULL, 870 NULL, NULL, NULL, NULL, 871 NULL, NULL, NULL, NULL, 872 NULL, NULL, NULL, NULL, 873 NULL, NULL, NULL, NULL, 874 NULL, NULL, NULL, NULL, 875 NULL, NULL, NULL, NULL, 876 NULL, NULL, NULL, NULL, 877 }, 878 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EDX, }, 879 .tcg_features = TCG_KVM_FEATURES, 880 /* 881 * KVM hints aren't auto-enabled by -cpu host, they need to be 882 * explicitly enabled in the command-line. 883 */ 884 .no_autoenable_flags = ~0U, 885 }, 886 [FEAT_SVM] = { 887 .type = CPUID_FEATURE_WORD, 888 .feat_names = { 889 "npt", "lbrv", "svm-lock", "nrip-save", 890 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists", 891 NULL, NULL, "pause-filter", NULL, 892 "pfthreshold", "avic", NULL, "v-vmsave-vmload", 893 "vgif", NULL, NULL, NULL, 894 NULL, NULL, NULL, NULL, 895 NULL, "vnmi", NULL, NULL, 896 "svme-addr-chk", NULL, NULL, NULL, 897 }, 898 .cpuid = { .eax = 0x8000000A, .reg = R_EDX, }, 899 .tcg_features = TCG_SVM_FEATURES, 900 }, 901 [FEAT_7_0_EBX] = { 902 .type = CPUID_FEATURE_WORD, 903 .feat_names = { 904 "fsgsbase", "tsc-adjust", "sgx", "bmi1", 905 "hle", "avx2", NULL, "smep", 906 "bmi2", "erms", "invpcid", "rtm", 907 NULL, NULL, "mpx", NULL, 908 "avx512f", "avx512dq", "rdseed", "adx", 909 "smap", "avx512ifma", "pcommit", "clflushopt", 910 "clwb", "intel-pt", "avx512pf", "avx512er", 911 "avx512cd", "sha-ni", "avx512bw", "avx512vl", 912 }, 913 .cpuid = { 914 .eax = 7, 915 .needs_ecx = true, .ecx = 0, 916 .reg = R_EBX, 917 }, 918 .tcg_features = TCG_7_0_EBX_FEATURES, 919 }, 920 [FEAT_7_0_ECX] = { 921 .type = CPUID_FEATURE_WORD, 922 .feat_names = { 923 NULL, "avx512vbmi", "umip", "pku", 924 NULL /* ospke */, "waitpkg", "avx512vbmi2", NULL, 925 "gfni", "vaes", "vpclmulqdq", "avx512vnni", 926 "avx512bitalg", NULL, "avx512-vpopcntdq", NULL, 927 "la57", NULL, NULL, NULL, 928 NULL, NULL, "rdpid", NULL, 929 "bus-lock-detect", "cldemote", NULL, "movdiri", 930 "movdir64b", NULL, "sgxlc", "pks", 931 }, 932 .cpuid = { 933 .eax = 7, 934 .needs_ecx = true, .ecx = 0, 935 .reg = R_ECX, 936 }, 937 .tcg_features = TCG_7_0_ECX_FEATURES, 938 }, 939 [FEAT_7_0_EDX] = { 940 .type = CPUID_FEATURE_WORD, 941 .feat_names = { 942 NULL, NULL, "avx512-4vnniw", "avx512-4fmaps", 943 "fsrm", NULL, NULL, NULL, 944 "avx512-vp2intersect", NULL, "md-clear", NULL, 945 NULL, NULL, "serialize", NULL, 946 "tsx-ldtrk", NULL, NULL /* pconfig */, "arch-lbr", 947 NULL, NULL, "amx-bf16", "avx512-fp16", 948 "amx-tile", "amx-int8", "spec-ctrl", "stibp", 949 "flush-l1d", "arch-capabilities", "core-capability", "ssbd", 950 }, 951 .cpuid = { 952 .eax = 7, 953 .needs_ecx = true, .ecx = 0, 954 .reg = R_EDX, 955 }, 956 .tcg_features = TCG_7_0_EDX_FEATURES, 957 }, 958 [FEAT_7_1_EAX] = { 959 .type = CPUID_FEATURE_WORD, 960 .feat_names = { 961 NULL, NULL, NULL, NULL, 962 "avx-vnni", "avx512-bf16", NULL, "cmpccxadd", 963 NULL, NULL, "fzrm", "fsrs", 964 "fsrc", NULL, NULL, NULL, 965 NULL, NULL, NULL, NULL, 966 NULL, "amx-fp16", NULL, "avx-ifma", 967 NULL, NULL, NULL, NULL, 968 NULL, NULL, NULL, NULL, 969 }, 970 .cpuid = { 971 .eax = 7, 972 .needs_ecx = true, .ecx = 1, 973 .reg = R_EAX, 974 }, 975 .tcg_features = TCG_7_1_EAX_FEATURES, 976 }, 977 [FEAT_7_1_EDX] = { 978 .type = CPUID_FEATURE_WORD, 979 .feat_names = { 980 NULL, NULL, NULL, NULL, 981 "avx-vnni-int8", "avx-ne-convert", NULL, NULL, 982 NULL, NULL, NULL, NULL, 983 NULL, NULL, "prefetchiti", NULL, 984 NULL, NULL, NULL, NULL, 985 NULL, NULL, NULL, NULL, 986 NULL, NULL, NULL, NULL, 987 NULL, NULL, NULL, NULL, 988 }, 989 .cpuid = { 990 .eax = 7, 991 .needs_ecx = true, .ecx = 1, 992 .reg = R_EDX, 993 }, 994 .tcg_features = TCG_7_1_EDX_FEATURES, 995 }, 996 [FEAT_8000_0007_EDX] = { 997 .type = CPUID_FEATURE_WORD, 998 .feat_names = { 999 NULL, NULL, NULL, NULL, 1000 NULL, NULL, NULL, NULL, 1001 "invtsc", NULL, NULL, NULL, 1002 NULL, NULL, NULL, NULL, 1003 NULL, NULL, NULL, NULL, 1004 NULL, NULL, NULL, NULL, 1005 NULL, NULL, NULL, NULL, 1006 NULL, NULL, NULL, NULL, 1007 }, 1008 .cpuid = { .eax = 0x80000007, .reg = R_EDX, }, 1009 .tcg_features = TCG_APM_FEATURES, 1010 .unmigratable_flags = CPUID_APM_INVTSC, 1011 }, 1012 [FEAT_8000_0008_EBX] = { 1013 .type = CPUID_FEATURE_WORD, 1014 .feat_names = { 1015 "clzero", NULL, "xsaveerptr", NULL, 1016 NULL, NULL, NULL, NULL, 1017 NULL, "wbnoinvd", NULL, NULL, 1018 "ibpb", NULL, "ibrs", "amd-stibp", 1019 NULL, "stibp-always-on", NULL, NULL, 1020 NULL, NULL, NULL, NULL, 1021 "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL, 1022 "amd-psfd", NULL, NULL, NULL, 1023 }, 1024 .cpuid = { .eax = 0x80000008, .reg = R_EBX, }, 1025 .tcg_features = TCG_8000_0008_EBX, 1026 .unmigratable_flags = 0, 1027 }, 1028 [FEAT_8000_0021_EAX] = { 1029 .type = CPUID_FEATURE_WORD, 1030 .feat_names = { 1031 "no-nested-data-bp", NULL, "lfence-always-serializing", NULL, 1032 NULL, NULL, "null-sel-clr-base", NULL, 1033 "auto-ibrs", NULL, NULL, NULL, 1034 NULL, NULL, NULL, NULL, 1035 NULL, NULL, NULL, NULL, 1036 NULL, NULL, NULL, NULL, 1037 NULL, NULL, NULL, NULL, 1038 NULL, NULL, NULL, NULL, 1039 }, 1040 .cpuid = { .eax = 0x80000021, .reg = R_EAX, }, 1041 .tcg_features = 0, 1042 .unmigratable_flags = 0, 1043 }, 1044 [FEAT_XSAVE] = { 1045 .type = CPUID_FEATURE_WORD, 1046 .feat_names = { 1047 "xsaveopt", "xsavec", "xgetbv1", "xsaves", 1048 "xfd", NULL, NULL, NULL, 1049 NULL, NULL, NULL, NULL, 1050 NULL, NULL, NULL, NULL, 1051 NULL, NULL, NULL, NULL, 1052 NULL, NULL, NULL, NULL, 1053 NULL, NULL, NULL, NULL, 1054 NULL, NULL, NULL, NULL, 1055 }, 1056 .cpuid = { 1057 .eax = 0xd, 1058 .needs_ecx = true, .ecx = 1, 1059 .reg = R_EAX, 1060 }, 1061 .tcg_features = TCG_XSAVE_FEATURES, 1062 }, 1063 [FEAT_XSAVE_XSS_LO] = { 1064 .type = CPUID_FEATURE_WORD, 1065 .feat_names = { 1066 NULL, NULL, NULL, NULL, 1067 NULL, NULL, NULL, NULL, 1068 NULL, NULL, NULL, NULL, 1069 NULL, NULL, NULL, NULL, 1070 NULL, NULL, NULL, NULL, 1071 NULL, NULL, NULL, NULL, 1072 NULL, NULL, NULL, NULL, 1073 NULL, NULL, NULL, NULL, 1074 }, 1075 .cpuid = { 1076 .eax = 0xD, 1077 .needs_ecx = true, 1078 .ecx = 1, 1079 .reg = R_ECX, 1080 }, 1081 }, 1082 [FEAT_XSAVE_XSS_HI] = { 1083 .type = CPUID_FEATURE_WORD, 1084 .cpuid = { 1085 .eax = 0xD, 1086 .needs_ecx = true, 1087 .ecx = 1, 1088 .reg = R_EDX 1089 }, 1090 }, 1091 [FEAT_6_EAX] = { 1092 .type = CPUID_FEATURE_WORD, 1093 .feat_names = { 1094 NULL, NULL, "arat", NULL, 1095 NULL, NULL, NULL, NULL, 1096 NULL, NULL, NULL, NULL, 1097 NULL, NULL, NULL, NULL, 1098 NULL, NULL, NULL, NULL, 1099 NULL, NULL, NULL, NULL, 1100 NULL, NULL, NULL, NULL, 1101 NULL, NULL, NULL, NULL, 1102 }, 1103 .cpuid = { .eax = 6, .reg = R_EAX, }, 1104 .tcg_features = TCG_6_EAX_FEATURES, 1105 }, 1106 [FEAT_XSAVE_XCR0_LO] = { 1107 .type = CPUID_FEATURE_WORD, 1108 .cpuid = { 1109 .eax = 0xD, 1110 .needs_ecx = true, .ecx = 0, 1111 .reg = R_EAX, 1112 }, 1113 .tcg_features = ~0U, 1114 .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK | 1115 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK | 1116 XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK | 1117 XSTATE_PKRU_MASK, 1118 }, 1119 [FEAT_XSAVE_XCR0_HI] = { 1120 .type = CPUID_FEATURE_WORD, 1121 .cpuid = { 1122 .eax = 0xD, 1123 .needs_ecx = true, .ecx = 0, 1124 .reg = R_EDX, 1125 }, 1126 .tcg_features = ~0U, 1127 }, 1128 /*Below are MSR exposed features*/ 1129 [FEAT_ARCH_CAPABILITIES] = { 1130 .type = MSR_FEATURE_WORD, 1131 .feat_names = { 1132 "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry", 1133 "ssb-no", "mds-no", "pschange-mc-no", "tsx-ctrl", 1134 "taa-no", NULL, NULL, NULL, 1135 NULL, "sbdr-ssdp-no", "fbsdp-no", "psdp-no", 1136 NULL, "fb-clear", NULL, NULL, 1137 NULL, NULL, NULL, NULL, 1138 "pbrsb-no", NULL, NULL, NULL, 1139 NULL, NULL, NULL, NULL, 1140 }, 1141 .msr = { 1142 .index = MSR_IA32_ARCH_CAPABILITIES, 1143 }, 1144 /* 1145 * FEAT_ARCH_CAPABILITIES only affects a read-only MSR, which 1146 * cannot be read from user mode. Therefore, it has no impact 1147 > on any user-mode operation, and warnings about unsupported 1148 * features do not matter. 1149 */ 1150 .tcg_features = ~0U, 1151 }, 1152 [FEAT_CORE_CAPABILITY] = { 1153 .type = MSR_FEATURE_WORD, 1154 .feat_names = { 1155 NULL, NULL, NULL, NULL, 1156 NULL, "split-lock-detect", NULL, NULL, 1157 NULL, NULL, NULL, NULL, 1158 NULL, NULL, NULL, NULL, 1159 NULL, NULL, NULL, NULL, 1160 NULL, NULL, NULL, NULL, 1161 NULL, NULL, NULL, NULL, 1162 NULL, NULL, NULL, NULL, 1163 }, 1164 .msr = { 1165 .index = MSR_IA32_CORE_CAPABILITY, 1166 }, 1167 }, 1168 [FEAT_PERF_CAPABILITIES] = { 1169 .type = MSR_FEATURE_WORD, 1170 .feat_names = { 1171 NULL, NULL, NULL, NULL, 1172 NULL, NULL, NULL, NULL, 1173 NULL, NULL, NULL, NULL, 1174 NULL, "full-width-write", NULL, NULL, 1175 NULL, NULL, NULL, NULL, 1176 NULL, NULL, NULL, NULL, 1177 NULL, NULL, NULL, NULL, 1178 NULL, NULL, NULL, NULL, 1179 }, 1180 .msr = { 1181 .index = MSR_IA32_PERF_CAPABILITIES, 1182 }, 1183 }, 1184 1185 [FEAT_VMX_PROCBASED_CTLS] = { 1186 .type = MSR_FEATURE_WORD, 1187 .feat_names = { 1188 NULL, NULL, "vmx-vintr-pending", "vmx-tsc-offset", 1189 NULL, NULL, NULL, "vmx-hlt-exit", 1190 NULL, "vmx-invlpg-exit", "vmx-mwait-exit", "vmx-rdpmc-exit", 1191 "vmx-rdtsc-exit", NULL, NULL, "vmx-cr3-load-noexit", 1192 "vmx-cr3-store-noexit", NULL, NULL, "vmx-cr8-load-exit", 1193 "vmx-cr8-store-exit", "vmx-flexpriority", "vmx-vnmi-pending", "vmx-movdr-exit", 1194 "vmx-io-exit", "vmx-io-bitmap", NULL, "vmx-mtf", 1195 "vmx-msr-bitmap", "vmx-monitor-exit", "vmx-pause-exit", "vmx-secondary-ctls", 1196 }, 1197 .msr = { 1198 .index = MSR_IA32_VMX_TRUE_PROCBASED_CTLS, 1199 } 1200 }, 1201 1202 [FEAT_VMX_SECONDARY_CTLS] = { 1203 .type = MSR_FEATURE_WORD, 1204 .feat_names = { 1205 "vmx-apicv-xapic", "vmx-ept", "vmx-desc-exit", "vmx-rdtscp-exit", 1206 "vmx-apicv-x2apic", "vmx-vpid", "vmx-wbinvd-exit", "vmx-unrestricted-guest", 1207 "vmx-apicv-register", "vmx-apicv-vid", "vmx-ple", "vmx-rdrand-exit", 1208 "vmx-invpcid-exit", "vmx-vmfunc", "vmx-shadow-vmcs", "vmx-encls-exit", 1209 "vmx-rdseed-exit", "vmx-pml", NULL, NULL, 1210 "vmx-xsaves", NULL, NULL, NULL, 1211 NULL, "vmx-tsc-scaling", NULL, NULL, 1212 NULL, NULL, NULL, NULL, 1213 }, 1214 .msr = { 1215 .index = MSR_IA32_VMX_PROCBASED_CTLS2, 1216 } 1217 }, 1218 1219 [FEAT_VMX_PINBASED_CTLS] = { 1220 .type = MSR_FEATURE_WORD, 1221 .feat_names = { 1222 "vmx-intr-exit", NULL, NULL, "vmx-nmi-exit", 1223 NULL, "vmx-vnmi", "vmx-preemption-timer", "vmx-posted-intr", 1224 NULL, NULL, NULL, NULL, 1225 NULL, NULL, NULL, NULL, 1226 NULL, NULL, NULL, NULL, 1227 NULL, NULL, NULL, NULL, 1228 NULL, NULL, NULL, NULL, 1229 NULL, NULL, NULL, NULL, 1230 }, 1231 .msr = { 1232 .index = MSR_IA32_VMX_TRUE_PINBASED_CTLS, 1233 } 1234 }, 1235 1236 [FEAT_VMX_EXIT_CTLS] = { 1237 .type = MSR_FEATURE_WORD, 1238 /* 1239 * VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE is copied from 1240 * the LM CPUID bit. 1241 */ 1242 .feat_names = { 1243 NULL, NULL, "vmx-exit-nosave-debugctl", NULL, 1244 NULL, NULL, NULL, NULL, 1245 NULL, NULL /* vmx-exit-host-addr-space-size */, NULL, NULL, 1246 "vmx-exit-load-perf-global-ctrl", NULL, NULL, "vmx-exit-ack-intr", 1247 NULL, NULL, "vmx-exit-save-pat", "vmx-exit-load-pat", 1248 "vmx-exit-save-efer", "vmx-exit-load-efer", 1249 "vmx-exit-save-preemption-timer", "vmx-exit-clear-bndcfgs", 1250 NULL, "vmx-exit-clear-rtit-ctl", NULL, NULL, 1251 NULL, "vmx-exit-load-pkrs", NULL, NULL, 1252 }, 1253 .msr = { 1254 .index = MSR_IA32_VMX_TRUE_EXIT_CTLS, 1255 } 1256 }, 1257 1258 [FEAT_VMX_ENTRY_CTLS] = { 1259 .type = MSR_FEATURE_WORD, 1260 .feat_names = { 1261 NULL, NULL, "vmx-entry-noload-debugctl", NULL, 1262 NULL, NULL, NULL, NULL, 1263 NULL, "vmx-entry-ia32e-mode", NULL, NULL, 1264 NULL, "vmx-entry-load-perf-global-ctrl", "vmx-entry-load-pat", "vmx-entry-load-efer", 1265 "vmx-entry-load-bndcfgs", NULL, "vmx-entry-load-rtit-ctl", NULL, 1266 NULL, NULL, "vmx-entry-load-pkrs", NULL, 1267 NULL, NULL, NULL, NULL, 1268 NULL, NULL, NULL, NULL, 1269 }, 1270 .msr = { 1271 .index = MSR_IA32_VMX_TRUE_ENTRY_CTLS, 1272 } 1273 }, 1274 1275 [FEAT_VMX_MISC] = { 1276 .type = MSR_FEATURE_WORD, 1277 .feat_names = { 1278 NULL, NULL, NULL, NULL, 1279 NULL, "vmx-store-lma", "vmx-activity-hlt", "vmx-activity-shutdown", 1280 "vmx-activity-wait-sipi", NULL, NULL, NULL, 1281 NULL, NULL, NULL, NULL, 1282 NULL, NULL, NULL, NULL, 1283 NULL, NULL, NULL, NULL, 1284 NULL, NULL, NULL, NULL, 1285 NULL, "vmx-vmwrite-vmexit-fields", "vmx-zero-len-inject", NULL, 1286 }, 1287 .msr = { 1288 .index = MSR_IA32_VMX_MISC, 1289 } 1290 }, 1291 1292 [FEAT_VMX_EPT_VPID_CAPS] = { 1293 .type = MSR_FEATURE_WORD, 1294 .feat_names = { 1295 "vmx-ept-execonly", NULL, NULL, NULL, 1296 NULL, NULL, "vmx-page-walk-4", "vmx-page-walk-5", 1297 NULL, NULL, NULL, NULL, 1298 NULL, NULL, NULL, NULL, 1299 "vmx-ept-2mb", "vmx-ept-1gb", NULL, NULL, 1300 "vmx-invept", "vmx-eptad", "vmx-ept-advanced-exitinfo", NULL, 1301 NULL, "vmx-invept-single-context", "vmx-invept-all-context", NULL, 1302 NULL, NULL, NULL, NULL, 1303 "vmx-invvpid", NULL, NULL, NULL, 1304 NULL, NULL, NULL, NULL, 1305 "vmx-invvpid-single-addr", "vmx-invept-single-context", 1306 "vmx-invvpid-all-context", "vmx-invept-single-context-noglobals", 1307 NULL, NULL, NULL, NULL, 1308 NULL, NULL, NULL, NULL, 1309 NULL, NULL, NULL, NULL, 1310 NULL, NULL, NULL, NULL, 1311 NULL, NULL, NULL, NULL, 1312 }, 1313 .msr = { 1314 .index = MSR_IA32_VMX_EPT_VPID_CAP, 1315 } 1316 }, 1317 1318 [FEAT_VMX_BASIC] = { 1319 .type = MSR_FEATURE_WORD, 1320 .feat_names = { 1321 [54] = "vmx-ins-outs", 1322 [55] = "vmx-true-ctls", 1323 }, 1324 .msr = { 1325 .index = MSR_IA32_VMX_BASIC, 1326 }, 1327 /* Just to be safe - we don't support setting the MSEG version field. */ 1328 .no_autoenable_flags = MSR_VMX_BASIC_DUAL_MONITOR, 1329 }, 1330 1331 [FEAT_VMX_VMFUNC] = { 1332 .type = MSR_FEATURE_WORD, 1333 .feat_names = { 1334 [0] = "vmx-eptp-switching", 1335 }, 1336 .msr = { 1337 .index = MSR_IA32_VMX_VMFUNC, 1338 } 1339 }, 1340 1341 [FEAT_14_0_ECX] = { 1342 .type = CPUID_FEATURE_WORD, 1343 .feat_names = { 1344 NULL, NULL, NULL, NULL, 1345 NULL, NULL, NULL, NULL, 1346 NULL, NULL, NULL, NULL, 1347 NULL, NULL, NULL, NULL, 1348 NULL, NULL, NULL, NULL, 1349 NULL, NULL, NULL, NULL, 1350 NULL, NULL, NULL, NULL, 1351 NULL, NULL, NULL, "intel-pt-lip", 1352 }, 1353 .cpuid = { 1354 .eax = 0x14, 1355 .needs_ecx = true, .ecx = 0, 1356 .reg = R_ECX, 1357 }, 1358 .tcg_features = TCG_14_0_ECX_FEATURES, 1359 }, 1360 1361 [FEAT_SGX_12_0_EAX] = { 1362 .type = CPUID_FEATURE_WORD, 1363 .feat_names = { 1364 "sgx1", "sgx2", NULL, NULL, 1365 NULL, NULL, NULL, NULL, 1366 NULL, NULL, NULL, "sgx-edeccssa", 1367 NULL, NULL, NULL, NULL, 1368 NULL, NULL, NULL, NULL, 1369 NULL, NULL, NULL, NULL, 1370 NULL, NULL, NULL, NULL, 1371 NULL, NULL, NULL, NULL, 1372 }, 1373 .cpuid = { 1374 .eax = 0x12, 1375 .needs_ecx = true, .ecx = 0, 1376 .reg = R_EAX, 1377 }, 1378 .tcg_features = TCG_SGX_12_0_EAX_FEATURES, 1379 }, 1380 1381 [FEAT_SGX_12_0_EBX] = { 1382 .type = CPUID_FEATURE_WORD, 1383 .feat_names = { 1384 "sgx-exinfo" , NULL, NULL, NULL, 1385 NULL, NULL, NULL, NULL, 1386 NULL, NULL, NULL, NULL, 1387 NULL, NULL, NULL, NULL, 1388 NULL, NULL, NULL, NULL, 1389 NULL, NULL, NULL, NULL, 1390 NULL, NULL, NULL, NULL, 1391 NULL, NULL, NULL, NULL, 1392 }, 1393 .cpuid = { 1394 .eax = 0x12, 1395 .needs_ecx = true, .ecx = 0, 1396 .reg = R_EBX, 1397 }, 1398 .tcg_features = TCG_SGX_12_0_EBX_FEATURES, 1399 }, 1400 1401 [FEAT_SGX_12_1_EAX] = { 1402 .type = CPUID_FEATURE_WORD, 1403 .feat_names = { 1404 NULL, "sgx-debug", "sgx-mode64", NULL, 1405 "sgx-provisionkey", "sgx-tokenkey", NULL, "sgx-kss", 1406 NULL, NULL, "sgx-aex-notify", NULL, 1407 NULL, NULL, NULL, NULL, 1408 NULL, NULL, NULL, NULL, 1409 NULL, NULL, NULL, NULL, 1410 NULL, NULL, NULL, NULL, 1411 NULL, NULL, NULL, NULL, 1412 }, 1413 .cpuid = { 1414 .eax = 0x12, 1415 .needs_ecx = true, .ecx = 1, 1416 .reg = R_EAX, 1417 }, 1418 .tcg_features = TCG_SGX_12_1_EAX_FEATURES, 1419 }, 1420 }; 1421 1422 typedef struct FeatureMask { 1423 FeatureWord index; 1424 uint64_t mask; 1425 } FeatureMask; 1426 1427 typedef struct FeatureDep { 1428 FeatureMask from, to; 1429 } FeatureDep; 1430 1431 static FeatureDep feature_dependencies[] = { 1432 { 1433 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_ARCH_CAPABILITIES }, 1434 .to = { FEAT_ARCH_CAPABILITIES, ~0ull }, 1435 }, 1436 { 1437 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_CORE_CAPABILITY }, 1438 .to = { FEAT_CORE_CAPABILITY, ~0ull }, 1439 }, 1440 { 1441 .from = { FEAT_1_ECX, CPUID_EXT_PDCM }, 1442 .to = { FEAT_PERF_CAPABILITIES, ~0ull }, 1443 }, 1444 { 1445 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1446 .to = { FEAT_VMX_PROCBASED_CTLS, ~0ull }, 1447 }, 1448 { 1449 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1450 .to = { FEAT_VMX_PINBASED_CTLS, ~0ull }, 1451 }, 1452 { 1453 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1454 .to = { FEAT_VMX_EXIT_CTLS, ~0ull }, 1455 }, 1456 { 1457 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1458 .to = { FEAT_VMX_ENTRY_CTLS, ~0ull }, 1459 }, 1460 { 1461 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1462 .to = { FEAT_VMX_MISC, ~0ull }, 1463 }, 1464 { 1465 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1466 .to = { FEAT_VMX_BASIC, ~0ull }, 1467 }, 1468 { 1469 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_LM }, 1470 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_IA32E_MODE }, 1471 }, 1472 { 1473 .from = { FEAT_VMX_PROCBASED_CTLS, VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS }, 1474 .to = { FEAT_VMX_SECONDARY_CTLS, ~0ull }, 1475 }, 1476 { 1477 .from = { FEAT_XSAVE, CPUID_XSAVE_XSAVES }, 1478 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_XSAVES }, 1479 }, 1480 { 1481 .from = { FEAT_1_ECX, CPUID_EXT_RDRAND }, 1482 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDRAND_EXITING }, 1483 }, 1484 { 1485 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INVPCID }, 1486 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_INVPCID }, 1487 }, 1488 { 1489 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_MPX }, 1490 .to = { FEAT_VMX_EXIT_CTLS, VMX_VM_EXIT_CLEAR_BNDCFGS }, 1491 }, 1492 { 1493 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_MPX }, 1494 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_LOAD_BNDCFGS }, 1495 }, 1496 { 1497 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_RDSEED }, 1498 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDSEED_EXITING }, 1499 }, 1500 { 1501 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT }, 1502 .to = { FEAT_14_0_ECX, ~0ull }, 1503 }, 1504 { 1505 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_RDTSCP }, 1506 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDTSCP }, 1507 }, 1508 { 1509 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT }, 1510 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull }, 1511 }, 1512 { 1513 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT }, 1514 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST }, 1515 }, 1516 { 1517 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VPID }, 1518 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull << 32 }, 1519 }, 1520 { 1521 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VMFUNC }, 1522 .to = { FEAT_VMX_VMFUNC, ~0ull }, 1523 }, 1524 { 1525 .from = { FEAT_8000_0001_ECX, CPUID_EXT3_SVM }, 1526 .to = { FEAT_SVM, ~0ull }, 1527 }, 1528 }; 1529 1530 typedef struct X86RegisterInfo32 { 1531 /* Name of register */ 1532 const char *name; 1533 /* QAPI enum value register */ 1534 X86CPURegister32 qapi_enum; 1535 } X86RegisterInfo32; 1536 1537 #define REGISTER(reg) \ 1538 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg } 1539 static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = { 1540 REGISTER(EAX), 1541 REGISTER(ECX), 1542 REGISTER(EDX), 1543 REGISTER(EBX), 1544 REGISTER(ESP), 1545 REGISTER(EBP), 1546 REGISTER(ESI), 1547 REGISTER(EDI), 1548 }; 1549 #undef REGISTER 1550 1551 /* CPUID feature bits available in XSS */ 1552 #define CPUID_XSTATE_XSS_MASK (XSTATE_ARCH_LBR_MASK) 1553 1554 ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUNT] = { 1555 [XSTATE_FP_BIT] = { 1556 /* x87 FP state component is always enabled if XSAVE is supported */ 1557 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE, 1558 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader), 1559 }, 1560 [XSTATE_SSE_BIT] = { 1561 /* SSE state component is always enabled if XSAVE is supported */ 1562 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE, 1563 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader), 1564 }, 1565 [XSTATE_YMM_BIT] = 1566 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX, 1567 .size = sizeof(XSaveAVX) }, 1568 [XSTATE_BNDREGS_BIT] = 1569 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX, 1570 .size = sizeof(XSaveBNDREG) }, 1571 [XSTATE_BNDCSR_BIT] = 1572 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX, 1573 .size = sizeof(XSaveBNDCSR) }, 1574 [XSTATE_OPMASK_BIT] = 1575 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1576 .size = sizeof(XSaveOpmask) }, 1577 [XSTATE_ZMM_Hi256_BIT] = 1578 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1579 .size = sizeof(XSaveZMM_Hi256) }, 1580 [XSTATE_Hi16_ZMM_BIT] = 1581 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1582 .size = sizeof(XSaveHi16_ZMM) }, 1583 [XSTATE_PKRU_BIT] = 1584 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU, 1585 .size = sizeof(XSavePKRU) }, 1586 [XSTATE_ARCH_LBR_BIT] = { 1587 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_ARCH_LBR, 1588 .offset = 0 /*supervisor mode component, offset = 0 */, 1589 .size = sizeof(XSavesArchLBR) }, 1590 [XSTATE_XTILE_CFG_BIT] = { 1591 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_AMX_TILE, 1592 .size = sizeof(XSaveXTILECFG), 1593 }, 1594 [XSTATE_XTILE_DATA_BIT] = { 1595 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_AMX_TILE, 1596 .size = sizeof(XSaveXTILEDATA) 1597 }, 1598 }; 1599 1600 uint32_t xsave_area_size(uint64_t mask, bool compacted) 1601 { 1602 uint64_t ret = x86_ext_save_areas[0].size; 1603 const ExtSaveArea *esa; 1604 uint32_t offset = 0; 1605 int i; 1606 1607 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 1608 esa = &x86_ext_save_areas[i]; 1609 if ((mask >> i) & 1) { 1610 offset = compacted ? ret : esa->offset; 1611 ret = MAX(ret, offset + esa->size); 1612 } 1613 } 1614 return ret; 1615 } 1616 1617 static inline bool accel_uses_host_cpuid(void) 1618 { 1619 return kvm_enabled() || hvf_enabled(); 1620 } 1621 1622 static inline uint64_t x86_cpu_xsave_xcr0_components(X86CPU *cpu) 1623 { 1624 return ((uint64_t)cpu->env.features[FEAT_XSAVE_XCR0_HI]) << 32 | 1625 cpu->env.features[FEAT_XSAVE_XCR0_LO]; 1626 } 1627 1628 /* Return name of 32-bit register, from a R_* constant */ 1629 static const char *get_register_name_32(unsigned int reg) 1630 { 1631 if (reg >= CPU_NB_REGS32) { 1632 return NULL; 1633 } 1634 return x86_reg_info_32[reg].name; 1635 } 1636 1637 static inline uint64_t x86_cpu_xsave_xss_components(X86CPU *cpu) 1638 { 1639 return ((uint64_t)cpu->env.features[FEAT_XSAVE_XSS_HI]) << 32 | 1640 cpu->env.features[FEAT_XSAVE_XSS_LO]; 1641 } 1642 1643 /* 1644 * Returns the set of feature flags that are supported and migratable by 1645 * QEMU, for a given FeatureWord. 1646 */ 1647 static uint64_t x86_cpu_get_migratable_flags(FeatureWord w) 1648 { 1649 FeatureWordInfo *wi = &feature_word_info[w]; 1650 uint64_t r = 0; 1651 int i; 1652 1653 for (i = 0; i < 64; i++) { 1654 uint64_t f = 1ULL << i; 1655 1656 /* If the feature name is known, it is implicitly considered migratable, 1657 * unless it is explicitly set in unmigratable_flags */ 1658 if ((wi->migratable_flags & f) || 1659 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) { 1660 r |= f; 1661 } 1662 } 1663 return r; 1664 } 1665 1666 void host_cpuid(uint32_t function, uint32_t count, 1667 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) 1668 { 1669 uint32_t vec[4]; 1670 1671 #ifdef __x86_64__ 1672 asm volatile("cpuid" 1673 : "=a"(vec[0]), "=b"(vec[1]), 1674 "=c"(vec[2]), "=d"(vec[3]) 1675 : "0"(function), "c"(count) : "cc"); 1676 #elif defined(__i386__) 1677 asm volatile("pusha \n\t" 1678 "cpuid \n\t" 1679 "mov %%eax, 0(%2) \n\t" 1680 "mov %%ebx, 4(%2) \n\t" 1681 "mov %%ecx, 8(%2) \n\t" 1682 "mov %%edx, 12(%2) \n\t" 1683 "popa" 1684 : : "a"(function), "c"(count), "S"(vec) 1685 : "memory", "cc"); 1686 #else 1687 abort(); 1688 #endif 1689 1690 if (eax) 1691 *eax = vec[0]; 1692 if (ebx) 1693 *ebx = vec[1]; 1694 if (ecx) 1695 *ecx = vec[2]; 1696 if (edx) 1697 *edx = vec[3]; 1698 } 1699 1700 /* CPU class name definitions: */ 1701 1702 /* Return type name for a given CPU model name 1703 * Caller is responsible for freeing the returned string. 1704 */ 1705 static char *x86_cpu_type_name(const char *model_name) 1706 { 1707 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name); 1708 } 1709 1710 static ObjectClass *x86_cpu_class_by_name(const char *cpu_model) 1711 { 1712 g_autofree char *typename = x86_cpu_type_name(cpu_model); 1713 return object_class_by_name(typename); 1714 } 1715 1716 static char *x86_cpu_class_get_model_name(X86CPUClass *cc) 1717 { 1718 const char *class_name = object_class_get_name(OBJECT_CLASS(cc)); 1719 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX)); 1720 return g_strndup(class_name, 1721 strlen(class_name) - strlen(X86_CPU_TYPE_SUFFIX)); 1722 } 1723 1724 typedef struct X86CPUVersionDefinition { 1725 X86CPUVersion version; 1726 const char *alias; 1727 const char *note; 1728 PropValue *props; 1729 const CPUCaches *const cache_info; 1730 } X86CPUVersionDefinition; 1731 1732 /* Base definition for a CPU model */ 1733 typedef struct X86CPUDefinition { 1734 const char *name; 1735 uint32_t level; 1736 uint32_t xlevel; 1737 /* vendor is zero-terminated, 12 character ASCII string */ 1738 char vendor[CPUID_VENDOR_SZ + 1]; 1739 int family; 1740 int model; 1741 int stepping; 1742 FeatureWordArray features; 1743 const char *model_id; 1744 const CPUCaches *const cache_info; 1745 /* 1746 * Definitions for alternative versions of CPU model. 1747 * List is terminated by item with version == 0. 1748 * If NULL, version 1 will be registered automatically. 1749 */ 1750 const X86CPUVersionDefinition *versions; 1751 const char *deprecation_note; 1752 } X86CPUDefinition; 1753 1754 /* Reference to a specific CPU model version */ 1755 struct X86CPUModel { 1756 /* Base CPU definition */ 1757 const X86CPUDefinition *cpudef; 1758 /* CPU model version */ 1759 X86CPUVersion version; 1760 const char *note; 1761 /* 1762 * If true, this is an alias CPU model. 1763 * This matters only for "-cpu help" and query-cpu-definitions 1764 */ 1765 bool is_alias; 1766 }; 1767 1768 /* Get full model name for CPU version */ 1769 static char *x86_cpu_versioned_model_name(const X86CPUDefinition *cpudef, 1770 X86CPUVersion version) 1771 { 1772 assert(version > 0); 1773 return g_strdup_printf("%s-v%d", cpudef->name, (int)version); 1774 } 1775 1776 static const X86CPUVersionDefinition * 1777 x86_cpu_def_get_versions(const X86CPUDefinition *def) 1778 { 1779 /* When X86CPUDefinition::versions is NULL, we register only v1 */ 1780 static const X86CPUVersionDefinition default_version_list[] = { 1781 { 1 }, 1782 { /* end of list */ } 1783 }; 1784 1785 return def->versions ?: default_version_list; 1786 } 1787 1788 static const CPUCaches epyc_cache_info = { 1789 .l1d_cache = &(CPUCacheInfo) { 1790 .type = DATA_CACHE, 1791 .level = 1, 1792 .size = 32 * KiB, 1793 .line_size = 64, 1794 .associativity = 8, 1795 .partitions = 1, 1796 .sets = 64, 1797 .lines_per_tag = 1, 1798 .self_init = 1, 1799 .no_invd_sharing = true, 1800 }, 1801 .l1i_cache = &(CPUCacheInfo) { 1802 .type = INSTRUCTION_CACHE, 1803 .level = 1, 1804 .size = 64 * KiB, 1805 .line_size = 64, 1806 .associativity = 4, 1807 .partitions = 1, 1808 .sets = 256, 1809 .lines_per_tag = 1, 1810 .self_init = 1, 1811 .no_invd_sharing = true, 1812 }, 1813 .l2_cache = &(CPUCacheInfo) { 1814 .type = UNIFIED_CACHE, 1815 .level = 2, 1816 .size = 512 * KiB, 1817 .line_size = 64, 1818 .associativity = 8, 1819 .partitions = 1, 1820 .sets = 1024, 1821 .lines_per_tag = 1, 1822 }, 1823 .l3_cache = &(CPUCacheInfo) { 1824 .type = UNIFIED_CACHE, 1825 .level = 3, 1826 .size = 8 * MiB, 1827 .line_size = 64, 1828 .associativity = 16, 1829 .partitions = 1, 1830 .sets = 8192, 1831 .lines_per_tag = 1, 1832 .self_init = true, 1833 .inclusive = true, 1834 .complex_indexing = true, 1835 }, 1836 }; 1837 1838 static CPUCaches epyc_v4_cache_info = { 1839 .l1d_cache = &(CPUCacheInfo) { 1840 .type = DATA_CACHE, 1841 .level = 1, 1842 .size = 32 * KiB, 1843 .line_size = 64, 1844 .associativity = 8, 1845 .partitions = 1, 1846 .sets = 64, 1847 .lines_per_tag = 1, 1848 .self_init = 1, 1849 .no_invd_sharing = true, 1850 }, 1851 .l1i_cache = &(CPUCacheInfo) { 1852 .type = INSTRUCTION_CACHE, 1853 .level = 1, 1854 .size = 64 * KiB, 1855 .line_size = 64, 1856 .associativity = 4, 1857 .partitions = 1, 1858 .sets = 256, 1859 .lines_per_tag = 1, 1860 .self_init = 1, 1861 .no_invd_sharing = true, 1862 }, 1863 .l2_cache = &(CPUCacheInfo) { 1864 .type = UNIFIED_CACHE, 1865 .level = 2, 1866 .size = 512 * KiB, 1867 .line_size = 64, 1868 .associativity = 8, 1869 .partitions = 1, 1870 .sets = 1024, 1871 .lines_per_tag = 1, 1872 }, 1873 .l3_cache = &(CPUCacheInfo) { 1874 .type = UNIFIED_CACHE, 1875 .level = 3, 1876 .size = 8 * MiB, 1877 .line_size = 64, 1878 .associativity = 16, 1879 .partitions = 1, 1880 .sets = 8192, 1881 .lines_per_tag = 1, 1882 .self_init = true, 1883 .inclusive = true, 1884 .complex_indexing = false, 1885 }, 1886 }; 1887 1888 static const CPUCaches epyc_rome_cache_info = { 1889 .l1d_cache = &(CPUCacheInfo) { 1890 .type = DATA_CACHE, 1891 .level = 1, 1892 .size = 32 * KiB, 1893 .line_size = 64, 1894 .associativity = 8, 1895 .partitions = 1, 1896 .sets = 64, 1897 .lines_per_tag = 1, 1898 .self_init = 1, 1899 .no_invd_sharing = true, 1900 }, 1901 .l1i_cache = &(CPUCacheInfo) { 1902 .type = INSTRUCTION_CACHE, 1903 .level = 1, 1904 .size = 32 * KiB, 1905 .line_size = 64, 1906 .associativity = 8, 1907 .partitions = 1, 1908 .sets = 64, 1909 .lines_per_tag = 1, 1910 .self_init = 1, 1911 .no_invd_sharing = true, 1912 }, 1913 .l2_cache = &(CPUCacheInfo) { 1914 .type = UNIFIED_CACHE, 1915 .level = 2, 1916 .size = 512 * KiB, 1917 .line_size = 64, 1918 .associativity = 8, 1919 .partitions = 1, 1920 .sets = 1024, 1921 .lines_per_tag = 1, 1922 }, 1923 .l3_cache = &(CPUCacheInfo) { 1924 .type = UNIFIED_CACHE, 1925 .level = 3, 1926 .size = 16 * MiB, 1927 .line_size = 64, 1928 .associativity = 16, 1929 .partitions = 1, 1930 .sets = 16384, 1931 .lines_per_tag = 1, 1932 .self_init = true, 1933 .inclusive = true, 1934 .complex_indexing = true, 1935 }, 1936 }; 1937 1938 static const CPUCaches epyc_rome_v3_cache_info = { 1939 .l1d_cache = &(CPUCacheInfo) { 1940 .type = DATA_CACHE, 1941 .level = 1, 1942 .size = 32 * KiB, 1943 .line_size = 64, 1944 .associativity = 8, 1945 .partitions = 1, 1946 .sets = 64, 1947 .lines_per_tag = 1, 1948 .self_init = 1, 1949 .no_invd_sharing = true, 1950 }, 1951 .l1i_cache = &(CPUCacheInfo) { 1952 .type = INSTRUCTION_CACHE, 1953 .level = 1, 1954 .size = 32 * KiB, 1955 .line_size = 64, 1956 .associativity = 8, 1957 .partitions = 1, 1958 .sets = 64, 1959 .lines_per_tag = 1, 1960 .self_init = 1, 1961 .no_invd_sharing = true, 1962 }, 1963 .l2_cache = &(CPUCacheInfo) { 1964 .type = UNIFIED_CACHE, 1965 .level = 2, 1966 .size = 512 * KiB, 1967 .line_size = 64, 1968 .associativity = 8, 1969 .partitions = 1, 1970 .sets = 1024, 1971 .lines_per_tag = 1, 1972 }, 1973 .l3_cache = &(CPUCacheInfo) { 1974 .type = UNIFIED_CACHE, 1975 .level = 3, 1976 .size = 16 * MiB, 1977 .line_size = 64, 1978 .associativity = 16, 1979 .partitions = 1, 1980 .sets = 16384, 1981 .lines_per_tag = 1, 1982 .self_init = true, 1983 .inclusive = true, 1984 .complex_indexing = false, 1985 }, 1986 }; 1987 1988 static const CPUCaches epyc_milan_cache_info = { 1989 .l1d_cache = &(CPUCacheInfo) { 1990 .type = DATA_CACHE, 1991 .level = 1, 1992 .size = 32 * KiB, 1993 .line_size = 64, 1994 .associativity = 8, 1995 .partitions = 1, 1996 .sets = 64, 1997 .lines_per_tag = 1, 1998 .self_init = 1, 1999 .no_invd_sharing = true, 2000 }, 2001 .l1i_cache = &(CPUCacheInfo) { 2002 .type = INSTRUCTION_CACHE, 2003 .level = 1, 2004 .size = 32 * KiB, 2005 .line_size = 64, 2006 .associativity = 8, 2007 .partitions = 1, 2008 .sets = 64, 2009 .lines_per_tag = 1, 2010 .self_init = 1, 2011 .no_invd_sharing = true, 2012 }, 2013 .l2_cache = &(CPUCacheInfo) { 2014 .type = UNIFIED_CACHE, 2015 .level = 2, 2016 .size = 512 * KiB, 2017 .line_size = 64, 2018 .associativity = 8, 2019 .partitions = 1, 2020 .sets = 1024, 2021 .lines_per_tag = 1, 2022 }, 2023 .l3_cache = &(CPUCacheInfo) { 2024 .type = UNIFIED_CACHE, 2025 .level = 3, 2026 .size = 32 * MiB, 2027 .line_size = 64, 2028 .associativity = 16, 2029 .partitions = 1, 2030 .sets = 32768, 2031 .lines_per_tag = 1, 2032 .self_init = true, 2033 .inclusive = true, 2034 .complex_indexing = true, 2035 }, 2036 }; 2037 2038 static const CPUCaches epyc_milan_v2_cache_info = { 2039 .l1d_cache = &(CPUCacheInfo) { 2040 .type = DATA_CACHE, 2041 .level = 1, 2042 .size = 32 * KiB, 2043 .line_size = 64, 2044 .associativity = 8, 2045 .partitions = 1, 2046 .sets = 64, 2047 .lines_per_tag = 1, 2048 .self_init = 1, 2049 .no_invd_sharing = true, 2050 }, 2051 .l1i_cache = &(CPUCacheInfo) { 2052 .type = INSTRUCTION_CACHE, 2053 .level = 1, 2054 .size = 32 * KiB, 2055 .line_size = 64, 2056 .associativity = 8, 2057 .partitions = 1, 2058 .sets = 64, 2059 .lines_per_tag = 1, 2060 .self_init = 1, 2061 .no_invd_sharing = true, 2062 }, 2063 .l2_cache = &(CPUCacheInfo) { 2064 .type = UNIFIED_CACHE, 2065 .level = 2, 2066 .size = 512 * KiB, 2067 .line_size = 64, 2068 .associativity = 8, 2069 .partitions = 1, 2070 .sets = 1024, 2071 .lines_per_tag = 1, 2072 }, 2073 .l3_cache = &(CPUCacheInfo) { 2074 .type = UNIFIED_CACHE, 2075 .level = 3, 2076 .size = 32 * MiB, 2077 .line_size = 64, 2078 .associativity = 16, 2079 .partitions = 1, 2080 .sets = 32768, 2081 .lines_per_tag = 1, 2082 .self_init = true, 2083 .inclusive = true, 2084 .complex_indexing = false, 2085 }, 2086 }; 2087 2088 static const CPUCaches epyc_genoa_cache_info = { 2089 .l1d_cache = &(CPUCacheInfo) { 2090 .type = DATA_CACHE, 2091 .level = 1, 2092 .size = 32 * KiB, 2093 .line_size = 64, 2094 .associativity = 8, 2095 .partitions = 1, 2096 .sets = 64, 2097 .lines_per_tag = 1, 2098 .self_init = 1, 2099 .no_invd_sharing = true, 2100 }, 2101 .l1i_cache = &(CPUCacheInfo) { 2102 .type = INSTRUCTION_CACHE, 2103 .level = 1, 2104 .size = 32 * KiB, 2105 .line_size = 64, 2106 .associativity = 8, 2107 .partitions = 1, 2108 .sets = 64, 2109 .lines_per_tag = 1, 2110 .self_init = 1, 2111 .no_invd_sharing = true, 2112 }, 2113 .l2_cache = &(CPUCacheInfo) { 2114 .type = UNIFIED_CACHE, 2115 .level = 2, 2116 .size = 1 * MiB, 2117 .line_size = 64, 2118 .associativity = 8, 2119 .partitions = 1, 2120 .sets = 2048, 2121 .lines_per_tag = 1, 2122 }, 2123 .l3_cache = &(CPUCacheInfo) { 2124 .type = UNIFIED_CACHE, 2125 .level = 3, 2126 .size = 32 * MiB, 2127 .line_size = 64, 2128 .associativity = 16, 2129 .partitions = 1, 2130 .sets = 32768, 2131 .lines_per_tag = 1, 2132 .self_init = true, 2133 .inclusive = true, 2134 .complex_indexing = false, 2135 }, 2136 }; 2137 2138 /* The following VMX features are not supported by KVM and are left out in the 2139 * CPU definitions: 2140 * 2141 * Dual-monitor support (all processors) 2142 * Entry to SMM 2143 * Deactivate dual-monitor treatment 2144 * Number of CR3-target values 2145 * Shutdown activity state 2146 * Wait-for-SIPI activity state 2147 * PAUSE-loop exiting (Westmere and newer) 2148 * EPT-violation #VE (Broadwell and newer) 2149 * Inject event with insn length=0 (Skylake and newer) 2150 * Conceal non-root operation from PT 2151 * Conceal VM exits from PT 2152 * Conceal VM entries from PT 2153 * Enable ENCLS exiting 2154 * Mode-based execute control (XS/XU) 2155 s TSC scaling (Skylake Server and newer) 2156 * GPA translation for PT (IceLake and newer) 2157 * User wait and pause 2158 * ENCLV exiting 2159 * Load IA32_RTIT_CTL 2160 * Clear IA32_RTIT_CTL 2161 * Advanced VM-exit information for EPT violations 2162 * Sub-page write permissions 2163 * PT in VMX operation 2164 */ 2165 2166 static const X86CPUDefinition builtin_x86_defs[] = { 2167 { 2168 .name = "qemu64", 2169 .level = 0xd, 2170 .vendor = CPUID_VENDOR_AMD, 2171 .family = 15, 2172 .model = 107, 2173 .stepping = 1, 2174 .features[FEAT_1_EDX] = 2175 PPRO_FEATURES | 2176 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2177 CPUID_PSE36, 2178 .features[FEAT_1_ECX] = 2179 CPUID_EXT_SSE3 | CPUID_EXT_CX16, 2180 .features[FEAT_8000_0001_EDX] = 2181 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2182 .features[FEAT_8000_0001_ECX] = 2183 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM, 2184 .xlevel = 0x8000000A, 2185 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 2186 }, 2187 { 2188 .name = "phenom", 2189 .level = 5, 2190 .vendor = CPUID_VENDOR_AMD, 2191 .family = 16, 2192 .model = 2, 2193 .stepping = 3, 2194 /* Missing: CPUID_HT */ 2195 .features[FEAT_1_EDX] = 2196 PPRO_FEATURES | 2197 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2198 CPUID_PSE36 | CPUID_VME, 2199 .features[FEAT_1_ECX] = 2200 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 | 2201 CPUID_EXT_POPCNT, 2202 .features[FEAT_8000_0001_EDX] = 2203 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | 2204 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT | 2205 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP, 2206 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, 2207 CPUID_EXT3_CR8LEG, 2208 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, 2209 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */ 2210 .features[FEAT_8000_0001_ECX] = 2211 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | 2212 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A, 2213 /* Missing: CPUID_SVM_LBRV */ 2214 .features[FEAT_SVM] = 2215 CPUID_SVM_NPT, 2216 .xlevel = 0x8000001A, 2217 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor" 2218 }, 2219 { 2220 .name = "core2duo", 2221 .level = 10, 2222 .vendor = CPUID_VENDOR_INTEL, 2223 .family = 6, 2224 .model = 15, 2225 .stepping = 11, 2226 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2227 .features[FEAT_1_EDX] = 2228 PPRO_FEATURES | 2229 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2230 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS, 2231 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST, 2232 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */ 2233 .features[FEAT_1_ECX] = 2234 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | 2235 CPUID_EXT_CX16, 2236 .features[FEAT_8000_0001_EDX] = 2237 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2238 .features[FEAT_8000_0001_ECX] = 2239 CPUID_EXT3_LAHF_LM, 2240 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2241 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2242 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2243 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2244 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2245 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2246 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2247 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2248 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2249 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2250 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2251 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2252 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2253 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2254 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2255 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2256 .features[FEAT_VMX_SECONDARY_CTLS] = 2257 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES, 2258 .xlevel = 0x80000008, 2259 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz", 2260 }, 2261 { 2262 .name = "kvm64", 2263 .level = 0xd, 2264 .vendor = CPUID_VENDOR_INTEL, 2265 .family = 15, 2266 .model = 6, 2267 .stepping = 1, 2268 /* Missing: CPUID_HT */ 2269 .features[FEAT_1_EDX] = 2270 PPRO_FEATURES | CPUID_VME | 2271 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2272 CPUID_PSE36, 2273 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */ 2274 .features[FEAT_1_ECX] = 2275 CPUID_EXT_SSE3 | CPUID_EXT_CX16, 2276 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */ 2277 .features[FEAT_8000_0001_EDX] = 2278 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2279 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, 2280 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A, 2281 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, 2282 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */ 2283 .features[FEAT_8000_0001_ECX] = 2284 0, 2285 /* VMX features from Cedar Mill/Prescott */ 2286 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2287 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2288 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2289 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2290 VMX_PIN_BASED_NMI_EXITING, 2291 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2292 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2293 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2294 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2295 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2296 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2297 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2298 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING, 2299 .xlevel = 0x80000008, 2300 .model_id = "Common KVM processor" 2301 }, 2302 { 2303 .name = "qemu32", 2304 .level = 4, 2305 .vendor = CPUID_VENDOR_INTEL, 2306 .family = 6, 2307 .model = 6, 2308 .stepping = 3, 2309 .features[FEAT_1_EDX] = 2310 PPRO_FEATURES, 2311 .features[FEAT_1_ECX] = 2312 CPUID_EXT_SSE3, 2313 .xlevel = 0x80000004, 2314 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 2315 }, 2316 { 2317 .name = "kvm32", 2318 .level = 5, 2319 .vendor = CPUID_VENDOR_INTEL, 2320 .family = 15, 2321 .model = 6, 2322 .stepping = 1, 2323 .features[FEAT_1_EDX] = 2324 PPRO_FEATURES | CPUID_VME | 2325 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36, 2326 .features[FEAT_1_ECX] = 2327 CPUID_EXT_SSE3, 2328 .features[FEAT_8000_0001_ECX] = 2329 0, 2330 /* VMX features from Yonah */ 2331 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2332 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2333 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2334 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2335 VMX_PIN_BASED_NMI_EXITING, 2336 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2337 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2338 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2339 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2340 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 2341 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 2342 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS, 2343 .xlevel = 0x80000008, 2344 .model_id = "Common 32-bit KVM processor" 2345 }, 2346 { 2347 .name = "coreduo", 2348 .level = 10, 2349 .vendor = CPUID_VENDOR_INTEL, 2350 .family = 6, 2351 .model = 14, 2352 .stepping = 8, 2353 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2354 .features[FEAT_1_EDX] = 2355 PPRO_FEATURES | CPUID_VME | 2356 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI | 2357 CPUID_SS, 2358 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR, 2359 * CPUID_EXT_PDCM, CPUID_EXT_VMX */ 2360 .features[FEAT_1_ECX] = 2361 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR, 2362 .features[FEAT_8000_0001_EDX] = 2363 CPUID_EXT2_NX, 2364 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2365 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2366 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2367 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2368 VMX_PIN_BASED_NMI_EXITING, 2369 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2370 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2371 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2372 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2373 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 2374 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 2375 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS, 2376 .xlevel = 0x80000008, 2377 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz", 2378 }, 2379 { 2380 .name = "486", 2381 .level = 1, 2382 .vendor = CPUID_VENDOR_INTEL, 2383 .family = 4, 2384 .model = 8, 2385 .stepping = 0, 2386 .features[FEAT_1_EDX] = 2387 I486_FEATURES, 2388 .xlevel = 0, 2389 .model_id = "", 2390 }, 2391 { 2392 .name = "pentium", 2393 .level = 1, 2394 .vendor = CPUID_VENDOR_INTEL, 2395 .family = 5, 2396 .model = 4, 2397 .stepping = 3, 2398 .features[FEAT_1_EDX] = 2399 PENTIUM_FEATURES, 2400 .xlevel = 0, 2401 .model_id = "", 2402 }, 2403 { 2404 .name = "pentium2", 2405 .level = 2, 2406 .vendor = CPUID_VENDOR_INTEL, 2407 .family = 6, 2408 .model = 5, 2409 .stepping = 2, 2410 .features[FEAT_1_EDX] = 2411 PENTIUM2_FEATURES, 2412 .xlevel = 0, 2413 .model_id = "", 2414 }, 2415 { 2416 .name = "pentium3", 2417 .level = 3, 2418 .vendor = CPUID_VENDOR_INTEL, 2419 .family = 6, 2420 .model = 7, 2421 .stepping = 3, 2422 .features[FEAT_1_EDX] = 2423 PENTIUM3_FEATURES, 2424 .xlevel = 0, 2425 .model_id = "", 2426 }, 2427 { 2428 .name = "athlon", 2429 .level = 2, 2430 .vendor = CPUID_VENDOR_AMD, 2431 .family = 6, 2432 .model = 2, 2433 .stepping = 3, 2434 .features[FEAT_1_EDX] = 2435 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR | 2436 CPUID_MCA, 2437 .features[FEAT_8000_0001_EDX] = 2438 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT, 2439 .xlevel = 0x80000008, 2440 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 2441 }, 2442 { 2443 .name = "n270", 2444 .level = 10, 2445 .vendor = CPUID_VENDOR_INTEL, 2446 .family = 6, 2447 .model = 28, 2448 .stepping = 2, 2449 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2450 .features[FEAT_1_EDX] = 2451 PPRO_FEATURES | 2452 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | 2453 CPUID_ACPI | CPUID_SS, 2454 /* Some CPUs got no CPUID_SEP */ 2455 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2, 2456 * CPUID_EXT_XTPR */ 2457 .features[FEAT_1_ECX] = 2458 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | 2459 CPUID_EXT_MOVBE, 2460 .features[FEAT_8000_0001_EDX] = 2461 CPUID_EXT2_NX, 2462 .features[FEAT_8000_0001_ECX] = 2463 CPUID_EXT3_LAHF_LM, 2464 .xlevel = 0x80000008, 2465 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz", 2466 }, 2467 { 2468 .name = "Conroe", 2469 .level = 10, 2470 .vendor = CPUID_VENDOR_INTEL, 2471 .family = 6, 2472 .model = 15, 2473 .stepping = 3, 2474 .features[FEAT_1_EDX] = 2475 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2476 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2477 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2478 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2479 CPUID_DE | CPUID_FP87, 2480 .features[FEAT_1_ECX] = 2481 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, 2482 .features[FEAT_8000_0001_EDX] = 2483 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 2484 .features[FEAT_8000_0001_ECX] = 2485 CPUID_EXT3_LAHF_LM, 2486 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2487 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2488 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2489 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2490 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2491 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2492 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2493 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2494 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2495 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2496 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2497 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2498 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2499 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2500 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2501 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2502 .features[FEAT_VMX_SECONDARY_CTLS] = 2503 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES, 2504 .xlevel = 0x80000008, 2505 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)", 2506 }, 2507 { 2508 .name = "Penryn", 2509 .level = 10, 2510 .vendor = CPUID_VENDOR_INTEL, 2511 .family = 6, 2512 .model = 23, 2513 .stepping = 3, 2514 .features[FEAT_1_EDX] = 2515 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2516 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2517 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2518 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2519 CPUID_DE | CPUID_FP87, 2520 .features[FEAT_1_ECX] = 2521 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2522 CPUID_EXT_SSE3, 2523 .features[FEAT_8000_0001_EDX] = 2524 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 2525 .features[FEAT_8000_0001_ECX] = 2526 CPUID_EXT3_LAHF_LM, 2527 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2528 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2529 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, 2530 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT | 2531 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL, 2532 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2533 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2534 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2535 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2536 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2537 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2538 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2539 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2540 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2541 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2542 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2543 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2544 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2545 .features[FEAT_VMX_SECONDARY_CTLS] = 2546 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2547 VMX_SECONDARY_EXEC_WBINVD_EXITING, 2548 .xlevel = 0x80000008, 2549 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)", 2550 }, 2551 { 2552 .name = "Nehalem", 2553 .level = 11, 2554 .vendor = CPUID_VENDOR_INTEL, 2555 .family = 6, 2556 .model = 26, 2557 .stepping = 3, 2558 .features[FEAT_1_EDX] = 2559 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2560 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2561 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2562 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2563 CPUID_DE | CPUID_FP87, 2564 .features[FEAT_1_ECX] = 2565 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 2566 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, 2567 .features[FEAT_8000_0001_EDX] = 2568 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2569 .features[FEAT_8000_0001_ECX] = 2570 CPUID_EXT3_LAHF_LM, 2571 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2572 MSR_VMX_BASIC_TRUE_CTLS, 2573 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2574 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2575 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2576 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2577 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2578 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2579 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2580 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2581 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2582 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2583 .features[FEAT_VMX_EXIT_CTLS] = 2584 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2585 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2586 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2587 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2588 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2589 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2590 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2591 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2592 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2593 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2594 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2595 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2596 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2597 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2598 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2599 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2600 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2601 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2602 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2603 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2604 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2605 .features[FEAT_VMX_SECONDARY_CTLS] = 2606 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2607 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2608 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2609 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2610 VMX_SECONDARY_EXEC_ENABLE_VPID, 2611 .xlevel = 0x80000008, 2612 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)", 2613 .versions = (X86CPUVersionDefinition[]) { 2614 { .version = 1 }, 2615 { 2616 .version = 2, 2617 .alias = "Nehalem-IBRS", 2618 .props = (PropValue[]) { 2619 { "spec-ctrl", "on" }, 2620 { "model-id", 2621 "Intel Core i7 9xx (Nehalem Core i7, IBRS update)" }, 2622 { /* end of list */ } 2623 } 2624 }, 2625 { /* end of list */ } 2626 } 2627 }, 2628 { 2629 .name = "Westmere", 2630 .level = 11, 2631 .vendor = CPUID_VENDOR_INTEL, 2632 .family = 6, 2633 .model = 44, 2634 .stepping = 1, 2635 .features[FEAT_1_EDX] = 2636 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2637 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2638 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2639 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2640 CPUID_DE | CPUID_FP87, 2641 .features[FEAT_1_ECX] = 2642 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | 2643 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2644 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 2645 .features[FEAT_8000_0001_EDX] = 2646 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2647 .features[FEAT_8000_0001_ECX] = 2648 CPUID_EXT3_LAHF_LM, 2649 .features[FEAT_6_EAX] = 2650 CPUID_6_EAX_ARAT, 2651 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2652 MSR_VMX_BASIC_TRUE_CTLS, 2653 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2654 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2655 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2656 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2657 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2658 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2659 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2660 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2661 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2662 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2663 .features[FEAT_VMX_EXIT_CTLS] = 2664 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2665 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2666 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2667 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2668 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2669 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2670 MSR_VMX_MISC_STORE_LMA, 2671 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2672 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2673 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2674 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2675 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2676 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2677 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2678 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2679 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2680 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2681 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2682 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2683 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2684 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2685 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2686 .features[FEAT_VMX_SECONDARY_CTLS] = 2687 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2688 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2689 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2690 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2691 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST, 2692 .xlevel = 0x80000008, 2693 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)", 2694 .versions = (X86CPUVersionDefinition[]) { 2695 { .version = 1 }, 2696 { 2697 .version = 2, 2698 .alias = "Westmere-IBRS", 2699 .props = (PropValue[]) { 2700 { "spec-ctrl", "on" }, 2701 { "model-id", 2702 "Westmere E56xx/L56xx/X56xx (IBRS update)" }, 2703 { /* end of list */ } 2704 } 2705 }, 2706 { /* end of list */ } 2707 } 2708 }, 2709 { 2710 .name = "SandyBridge", 2711 .level = 0xd, 2712 .vendor = CPUID_VENDOR_INTEL, 2713 .family = 6, 2714 .model = 42, 2715 .stepping = 1, 2716 .features[FEAT_1_EDX] = 2717 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2718 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2719 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2720 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2721 CPUID_DE | CPUID_FP87, 2722 .features[FEAT_1_ECX] = 2723 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2724 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | 2725 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 2726 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 2727 CPUID_EXT_SSE3, 2728 .features[FEAT_8000_0001_EDX] = 2729 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 2730 CPUID_EXT2_SYSCALL, 2731 .features[FEAT_8000_0001_ECX] = 2732 CPUID_EXT3_LAHF_LM, 2733 .features[FEAT_XSAVE] = 2734 CPUID_XSAVE_XSAVEOPT, 2735 .features[FEAT_6_EAX] = 2736 CPUID_6_EAX_ARAT, 2737 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2738 MSR_VMX_BASIC_TRUE_CTLS, 2739 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2740 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2741 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2742 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2743 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2744 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2745 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2746 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2747 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2748 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2749 .features[FEAT_VMX_EXIT_CTLS] = 2750 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2751 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2752 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2753 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2754 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2755 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2756 MSR_VMX_MISC_STORE_LMA, 2757 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2758 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2759 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2760 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2761 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2762 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2763 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2764 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2765 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2766 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2767 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2768 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2769 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2770 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2771 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2772 .features[FEAT_VMX_SECONDARY_CTLS] = 2773 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2774 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2775 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2776 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2777 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST, 2778 .xlevel = 0x80000008, 2779 .model_id = "Intel Xeon E312xx (Sandy Bridge)", 2780 .versions = (X86CPUVersionDefinition[]) { 2781 { .version = 1 }, 2782 { 2783 .version = 2, 2784 .alias = "SandyBridge-IBRS", 2785 .props = (PropValue[]) { 2786 { "spec-ctrl", "on" }, 2787 { "model-id", 2788 "Intel Xeon E312xx (Sandy Bridge, IBRS update)" }, 2789 { /* end of list */ } 2790 } 2791 }, 2792 { /* end of list */ } 2793 } 2794 }, 2795 { 2796 .name = "IvyBridge", 2797 .level = 0xd, 2798 .vendor = CPUID_VENDOR_INTEL, 2799 .family = 6, 2800 .model = 58, 2801 .stepping = 9, 2802 .features[FEAT_1_EDX] = 2803 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2804 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2805 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2806 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2807 CPUID_DE | CPUID_FP87, 2808 .features[FEAT_1_ECX] = 2809 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2810 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | 2811 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 2812 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 2813 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 2814 .features[FEAT_7_0_EBX] = 2815 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | 2816 CPUID_7_0_EBX_ERMS, 2817 .features[FEAT_8000_0001_EDX] = 2818 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 2819 CPUID_EXT2_SYSCALL, 2820 .features[FEAT_8000_0001_ECX] = 2821 CPUID_EXT3_LAHF_LM, 2822 .features[FEAT_XSAVE] = 2823 CPUID_XSAVE_XSAVEOPT, 2824 .features[FEAT_6_EAX] = 2825 CPUID_6_EAX_ARAT, 2826 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2827 MSR_VMX_BASIC_TRUE_CTLS, 2828 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2829 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2830 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2831 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2832 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2833 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2834 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2835 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2836 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2837 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2838 .features[FEAT_VMX_EXIT_CTLS] = 2839 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2840 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2841 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2842 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2843 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2844 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2845 MSR_VMX_MISC_STORE_LMA, 2846 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2847 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2848 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 2849 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2850 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2851 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2852 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2853 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2854 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2855 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2856 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2857 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2858 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2859 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2860 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2861 .features[FEAT_VMX_SECONDARY_CTLS] = 2862 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2863 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2864 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2865 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2866 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 2867 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 2868 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 2869 VMX_SECONDARY_EXEC_RDRAND_EXITING, 2870 .xlevel = 0x80000008, 2871 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)", 2872 .versions = (X86CPUVersionDefinition[]) { 2873 { .version = 1 }, 2874 { 2875 .version = 2, 2876 .alias = "IvyBridge-IBRS", 2877 .props = (PropValue[]) { 2878 { "spec-ctrl", "on" }, 2879 { "model-id", 2880 "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)" }, 2881 { /* end of list */ } 2882 } 2883 }, 2884 { /* end of list */ } 2885 } 2886 }, 2887 { 2888 .name = "Haswell", 2889 .level = 0xd, 2890 .vendor = CPUID_VENDOR_INTEL, 2891 .family = 6, 2892 .model = 60, 2893 .stepping = 4, 2894 .features[FEAT_1_EDX] = 2895 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2896 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2897 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2898 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2899 CPUID_DE | CPUID_FP87, 2900 .features[FEAT_1_ECX] = 2901 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2902 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 2903 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2904 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 2905 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 2906 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 2907 .features[FEAT_8000_0001_EDX] = 2908 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 2909 CPUID_EXT2_SYSCALL, 2910 .features[FEAT_8000_0001_ECX] = 2911 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM, 2912 .features[FEAT_7_0_EBX] = 2913 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 2914 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 2915 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 2916 CPUID_7_0_EBX_RTM, 2917 .features[FEAT_XSAVE] = 2918 CPUID_XSAVE_XSAVEOPT, 2919 .features[FEAT_6_EAX] = 2920 CPUID_6_EAX_ARAT, 2921 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2922 MSR_VMX_BASIC_TRUE_CTLS, 2923 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2924 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2925 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2926 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2927 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2928 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2929 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2930 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2931 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2932 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 2933 .features[FEAT_VMX_EXIT_CTLS] = 2934 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2935 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2936 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2937 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2938 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2939 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2940 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 2941 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2942 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2943 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 2944 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2945 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2946 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2947 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2948 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2949 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2950 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2951 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2952 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2953 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2954 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2955 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2956 .features[FEAT_VMX_SECONDARY_CTLS] = 2957 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2958 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2959 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2960 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2961 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 2962 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 2963 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 2964 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 2965 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS, 2966 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 2967 .xlevel = 0x80000008, 2968 .model_id = "Intel Core Processor (Haswell)", 2969 .versions = (X86CPUVersionDefinition[]) { 2970 { .version = 1 }, 2971 { 2972 .version = 2, 2973 .alias = "Haswell-noTSX", 2974 .props = (PropValue[]) { 2975 { "hle", "off" }, 2976 { "rtm", "off" }, 2977 { "stepping", "1" }, 2978 { "model-id", "Intel Core Processor (Haswell, no TSX)", }, 2979 { /* end of list */ } 2980 }, 2981 }, 2982 { 2983 .version = 3, 2984 .alias = "Haswell-IBRS", 2985 .props = (PropValue[]) { 2986 /* Restore TSX features removed by -v2 above */ 2987 { "hle", "on" }, 2988 { "rtm", "on" }, 2989 /* 2990 * Haswell and Haswell-IBRS had stepping=4 in 2991 * QEMU 4.0 and older 2992 */ 2993 { "stepping", "4" }, 2994 { "spec-ctrl", "on" }, 2995 { "model-id", 2996 "Intel Core Processor (Haswell, IBRS)" }, 2997 { /* end of list */ } 2998 } 2999 }, 3000 { 3001 .version = 4, 3002 .alias = "Haswell-noTSX-IBRS", 3003 .props = (PropValue[]) { 3004 { "hle", "off" }, 3005 { "rtm", "off" }, 3006 /* spec-ctrl was already enabled by -v3 above */ 3007 { "stepping", "1" }, 3008 { "model-id", 3009 "Intel Core Processor (Haswell, no TSX, IBRS)" }, 3010 { /* end of list */ } 3011 } 3012 }, 3013 { /* end of list */ } 3014 } 3015 }, 3016 { 3017 .name = "Broadwell", 3018 .level = 0xd, 3019 .vendor = CPUID_VENDOR_INTEL, 3020 .family = 6, 3021 .model = 61, 3022 .stepping = 2, 3023 .features[FEAT_1_EDX] = 3024 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3025 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3026 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3027 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3028 CPUID_DE | CPUID_FP87, 3029 .features[FEAT_1_ECX] = 3030 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3031 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3032 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3033 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3034 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3035 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3036 .features[FEAT_8000_0001_EDX] = 3037 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3038 CPUID_EXT2_SYSCALL, 3039 .features[FEAT_8000_0001_ECX] = 3040 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3041 .features[FEAT_7_0_EBX] = 3042 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3043 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3044 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3045 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3046 CPUID_7_0_EBX_SMAP, 3047 .features[FEAT_XSAVE] = 3048 CPUID_XSAVE_XSAVEOPT, 3049 .features[FEAT_6_EAX] = 3050 CPUID_6_EAX_ARAT, 3051 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3052 MSR_VMX_BASIC_TRUE_CTLS, 3053 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3054 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3055 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3056 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3057 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3058 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3059 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3060 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3061 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3062 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3063 .features[FEAT_VMX_EXIT_CTLS] = 3064 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3065 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3066 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3067 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3068 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3069 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3070 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3071 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3072 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3073 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3074 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3075 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3076 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3077 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3078 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3079 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3080 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3081 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3082 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3083 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3084 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3085 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3086 .features[FEAT_VMX_SECONDARY_CTLS] = 3087 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3088 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3089 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3090 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3091 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3092 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3093 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3094 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3095 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3096 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3097 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3098 .xlevel = 0x80000008, 3099 .model_id = "Intel Core Processor (Broadwell)", 3100 .versions = (X86CPUVersionDefinition[]) { 3101 { .version = 1 }, 3102 { 3103 .version = 2, 3104 .alias = "Broadwell-noTSX", 3105 .props = (PropValue[]) { 3106 { "hle", "off" }, 3107 { "rtm", "off" }, 3108 { "model-id", "Intel Core Processor (Broadwell, no TSX)", }, 3109 { /* end of list */ } 3110 }, 3111 }, 3112 { 3113 .version = 3, 3114 .alias = "Broadwell-IBRS", 3115 .props = (PropValue[]) { 3116 /* Restore TSX features removed by -v2 above */ 3117 { "hle", "on" }, 3118 { "rtm", "on" }, 3119 { "spec-ctrl", "on" }, 3120 { "model-id", 3121 "Intel Core Processor (Broadwell, IBRS)" }, 3122 { /* end of list */ } 3123 } 3124 }, 3125 { 3126 .version = 4, 3127 .alias = "Broadwell-noTSX-IBRS", 3128 .props = (PropValue[]) { 3129 { "hle", "off" }, 3130 { "rtm", "off" }, 3131 /* spec-ctrl was already enabled by -v3 above */ 3132 { "model-id", 3133 "Intel Core Processor (Broadwell, no TSX, IBRS)" }, 3134 { /* end of list */ } 3135 } 3136 }, 3137 { /* end of list */ } 3138 } 3139 }, 3140 { 3141 .name = "Skylake-Client", 3142 .level = 0xd, 3143 .vendor = CPUID_VENDOR_INTEL, 3144 .family = 6, 3145 .model = 94, 3146 .stepping = 3, 3147 .features[FEAT_1_EDX] = 3148 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3149 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3150 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3151 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3152 CPUID_DE | CPUID_FP87, 3153 .features[FEAT_1_ECX] = 3154 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3155 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3156 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3157 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3158 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3159 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3160 .features[FEAT_8000_0001_EDX] = 3161 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3162 CPUID_EXT2_SYSCALL, 3163 .features[FEAT_8000_0001_ECX] = 3164 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3165 .features[FEAT_7_0_EBX] = 3166 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3167 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3168 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3169 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3170 CPUID_7_0_EBX_SMAP, 3171 /* XSAVES is added in version 4 */ 3172 .features[FEAT_XSAVE] = 3173 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3174 CPUID_XSAVE_XGETBV1, 3175 .features[FEAT_6_EAX] = 3176 CPUID_6_EAX_ARAT, 3177 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3178 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3179 MSR_VMX_BASIC_TRUE_CTLS, 3180 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3181 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3182 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3183 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3184 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3185 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3186 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3187 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3188 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3189 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3190 .features[FEAT_VMX_EXIT_CTLS] = 3191 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3192 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3193 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3194 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3195 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3196 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3197 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3198 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3199 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3200 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 3201 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3202 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3203 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3204 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3205 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3206 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3207 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3208 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3209 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3210 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3211 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3212 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3213 .features[FEAT_VMX_SECONDARY_CTLS] = 3214 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3215 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3216 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3217 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3218 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3219 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3220 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3221 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3222 .xlevel = 0x80000008, 3223 .model_id = "Intel Core Processor (Skylake)", 3224 .versions = (X86CPUVersionDefinition[]) { 3225 { .version = 1 }, 3226 { 3227 .version = 2, 3228 .alias = "Skylake-Client-IBRS", 3229 .props = (PropValue[]) { 3230 { "spec-ctrl", "on" }, 3231 { "model-id", 3232 "Intel Core Processor (Skylake, IBRS)" }, 3233 { /* end of list */ } 3234 } 3235 }, 3236 { 3237 .version = 3, 3238 .alias = "Skylake-Client-noTSX-IBRS", 3239 .props = (PropValue[]) { 3240 { "hle", "off" }, 3241 { "rtm", "off" }, 3242 { "model-id", 3243 "Intel Core Processor (Skylake, IBRS, no TSX)" }, 3244 { /* end of list */ } 3245 } 3246 }, 3247 { 3248 .version = 4, 3249 .note = "IBRS, XSAVES, no TSX", 3250 .props = (PropValue[]) { 3251 { "xsaves", "on" }, 3252 { "vmx-xsaves", "on" }, 3253 { /* end of list */ } 3254 } 3255 }, 3256 { /* end of list */ } 3257 } 3258 }, 3259 { 3260 .name = "Skylake-Server", 3261 .level = 0xd, 3262 .vendor = CPUID_VENDOR_INTEL, 3263 .family = 6, 3264 .model = 85, 3265 .stepping = 4, 3266 .features[FEAT_1_EDX] = 3267 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3268 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3269 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3270 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3271 CPUID_DE | CPUID_FP87, 3272 .features[FEAT_1_ECX] = 3273 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3274 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3275 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3276 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3277 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3278 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3279 .features[FEAT_8000_0001_EDX] = 3280 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3281 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3282 .features[FEAT_8000_0001_ECX] = 3283 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3284 .features[FEAT_7_0_EBX] = 3285 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3286 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3287 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3288 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3289 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3290 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3291 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3292 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3293 .features[FEAT_7_0_ECX] = 3294 CPUID_7_0_ECX_PKU, 3295 /* XSAVES is added in version 5 */ 3296 .features[FEAT_XSAVE] = 3297 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3298 CPUID_XSAVE_XGETBV1, 3299 .features[FEAT_6_EAX] = 3300 CPUID_6_EAX_ARAT, 3301 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3302 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3303 MSR_VMX_BASIC_TRUE_CTLS, 3304 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3305 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3306 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3307 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3308 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3309 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3310 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3311 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3312 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3313 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3314 .features[FEAT_VMX_EXIT_CTLS] = 3315 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3316 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3317 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3318 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3319 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3320 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3321 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3322 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3323 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3324 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3325 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3326 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3327 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3328 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3329 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3330 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3331 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3332 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3333 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3334 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3335 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3336 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3337 .features[FEAT_VMX_SECONDARY_CTLS] = 3338 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3339 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3340 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3341 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3342 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3343 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3344 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3345 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3346 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3347 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3348 .xlevel = 0x80000008, 3349 .model_id = "Intel Xeon Processor (Skylake)", 3350 .versions = (X86CPUVersionDefinition[]) { 3351 { .version = 1 }, 3352 { 3353 .version = 2, 3354 .alias = "Skylake-Server-IBRS", 3355 .props = (PropValue[]) { 3356 /* clflushopt was not added to Skylake-Server-IBRS */ 3357 /* TODO: add -v3 including clflushopt */ 3358 { "clflushopt", "off" }, 3359 { "spec-ctrl", "on" }, 3360 { "model-id", 3361 "Intel Xeon Processor (Skylake, IBRS)" }, 3362 { /* end of list */ } 3363 } 3364 }, 3365 { 3366 .version = 3, 3367 .alias = "Skylake-Server-noTSX-IBRS", 3368 .props = (PropValue[]) { 3369 { "hle", "off" }, 3370 { "rtm", "off" }, 3371 { "model-id", 3372 "Intel Xeon Processor (Skylake, IBRS, no TSX)" }, 3373 { /* end of list */ } 3374 } 3375 }, 3376 { 3377 .version = 4, 3378 .props = (PropValue[]) { 3379 { "vmx-eptp-switching", "on" }, 3380 { /* end of list */ } 3381 } 3382 }, 3383 { 3384 .version = 5, 3385 .note = "IBRS, XSAVES, EPT switching, no TSX", 3386 .props = (PropValue[]) { 3387 { "xsaves", "on" }, 3388 { "vmx-xsaves", "on" }, 3389 { /* end of list */ } 3390 } 3391 }, 3392 { /* end of list */ } 3393 } 3394 }, 3395 { 3396 .name = "Cascadelake-Server", 3397 .level = 0xd, 3398 .vendor = CPUID_VENDOR_INTEL, 3399 .family = 6, 3400 .model = 85, 3401 .stepping = 6, 3402 .features[FEAT_1_EDX] = 3403 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3404 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3405 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3406 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3407 CPUID_DE | CPUID_FP87, 3408 .features[FEAT_1_ECX] = 3409 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3410 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3411 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3412 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3413 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3414 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3415 .features[FEAT_8000_0001_EDX] = 3416 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3417 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3418 .features[FEAT_8000_0001_ECX] = 3419 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3420 .features[FEAT_7_0_EBX] = 3421 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3422 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3423 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3424 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3425 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3426 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3427 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3428 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3429 .features[FEAT_7_0_ECX] = 3430 CPUID_7_0_ECX_PKU | 3431 CPUID_7_0_ECX_AVX512VNNI, 3432 .features[FEAT_7_0_EDX] = 3433 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 3434 /* XSAVES is added in version 5 */ 3435 .features[FEAT_XSAVE] = 3436 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3437 CPUID_XSAVE_XGETBV1, 3438 .features[FEAT_6_EAX] = 3439 CPUID_6_EAX_ARAT, 3440 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3441 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3442 MSR_VMX_BASIC_TRUE_CTLS, 3443 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3444 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3445 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3446 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3447 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3448 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3449 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3450 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3451 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3452 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3453 .features[FEAT_VMX_EXIT_CTLS] = 3454 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3455 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3456 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3457 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3458 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3459 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3460 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3461 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3462 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3463 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3464 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3465 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3466 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3467 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3468 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3469 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3470 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3471 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3472 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3473 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3474 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3475 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3476 .features[FEAT_VMX_SECONDARY_CTLS] = 3477 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3478 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3479 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3480 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3481 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3482 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3483 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3484 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3485 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3486 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3487 .xlevel = 0x80000008, 3488 .model_id = "Intel Xeon Processor (Cascadelake)", 3489 .versions = (X86CPUVersionDefinition[]) { 3490 { .version = 1 }, 3491 { .version = 2, 3492 .note = "ARCH_CAPABILITIES", 3493 .props = (PropValue[]) { 3494 { "arch-capabilities", "on" }, 3495 { "rdctl-no", "on" }, 3496 { "ibrs-all", "on" }, 3497 { "skip-l1dfl-vmentry", "on" }, 3498 { "mds-no", "on" }, 3499 { /* end of list */ } 3500 }, 3501 }, 3502 { .version = 3, 3503 .alias = "Cascadelake-Server-noTSX", 3504 .note = "ARCH_CAPABILITIES, no TSX", 3505 .props = (PropValue[]) { 3506 { "hle", "off" }, 3507 { "rtm", "off" }, 3508 { /* end of list */ } 3509 }, 3510 }, 3511 { .version = 4, 3512 .note = "ARCH_CAPABILITIES, no TSX", 3513 .props = (PropValue[]) { 3514 { "vmx-eptp-switching", "on" }, 3515 { /* end of list */ } 3516 }, 3517 }, 3518 { .version = 5, 3519 .note = "ARCH_CAPABILITIES, EPT switching, XSAVES, no TSX", 3520 .props = (PropValue[]) { 3521 { "xsaves", "on" }, 3522 { "vmx-xsaves", "on" }, 3523 { /* end of list */ } 3524 }, 3525 }, 3526 { /* end of list */ } 3527 } 3528 }, 3529 { 3530 .name = "Cooperlake", 3531 .level = 0xd, 3532 .vendor = CPUID_VENDOR_INTEL, 3533 .family = 6, 3534 .model = 85, 3535 .stepping = 10, 3536 .features[FEAT_1_EDX] = 3537 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3538 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3539 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3540 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3541 CPUID_DE | CPUID_FP87, 3542 .features[FEAT_1_ECX] = 3543 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3544 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3545 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3546 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3547 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3548 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3549 .features[FEAT_8000_0001_EDX] = 3550 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3551 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3552 .features[FEAT_8000_0001_ECX] = 3553 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3554 .features[FEAT_7_0_EBX] = 3555 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3556 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3557 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3558 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3559 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3560 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3561 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3562 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3563 .features[FEAT_7_0_ECX] = 3564 CPUID_7_0_ECX_PKU | 3565 CPUID_7_0_ECX_AVX512VNNI, 3566 .features[FEAT_7_0_EDX] = 3567 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_STIBP | 3568 CPUID_7_0_EDX_SPEC_CTRL_SSBD | CPUID_7_0_EDX_ARCH_CAPABILITIES, 3569 .features[FEAT_ARCH_CAPABILITIES] = 3570 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 3571 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 3572 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO, 3573 .features[FEAT_7_1_EAX] = 3574 CPUID_7_1_EAX_AVX512_BF16, 3575 /* XSAVES is added in version 2 */ 3576 .features[FEAT_XSAVE] = 3577 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3578 CPUID_XSAVE_XGETBV1, 3579 .features[FEAT_6_EAX] = 3580 CPUID_6_EAX_ARAT, 3581 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3582 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3583 MSR_VMX_BASIC_TRUE_CTLS, 3584 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3585 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3586 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3587 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3588 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3589 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3590 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3591 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3592 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3593 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3594 .features[FEAT_VMX_EXIT_CTLS] = 3595 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3596 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3597 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3598 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3599 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3600 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3601 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3602 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3603 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3604 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3605 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3606 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3607 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3608 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3609 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3610 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3611 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3612 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3613 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3614 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3615 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3616 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3617 .features[FEAT_VMX_SECONDARY_CTLS] = 3618 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3619 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3620 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3621 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3622 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3623 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3624 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3625 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3626 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3627 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3628 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3629 .xlevel = 0x80000008, 3630 .model_id = "Intel Xeon Processor (Cooperlake)", 3631 .versions = (X86CPUVersionDefinition[]) { 3632 { .version = 1 }, 3633 { .version = 2, 3634 .note = "XSAVES", 3635 .props = (PropValue[]) { 3636 { "xsaves", "on" }, 3637 { "vmx-xsaves", "on" }, 3638 { /* end of list */ } 3639 }, 3640 }, 3641 { /* end of list */ } 3642 } 3643 }, 3644 { 3645 .name = "Icelake-Server", 3646 .level = 0xd, 3647 .vendor = CPUID_VENDOR_INTEL, 3648 .family = 6, 3649 .model = 134, 3650 .stepping = 0, 3651 .features[FEAT_1_EDX] = 3652 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3653 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3654 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3655 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3656 CPUID_DE | CPUID_FP87, 3657 .features[FEAT_1_ECX] = 3658 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3659 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3660 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3661 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3662 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3663 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3664 .features[FEAT_8000_0001_EDX] = 3665 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3666 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3667 .features[FEAT_8000_0001_ECX] = 3668 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3669 .features[FEAT_8000_0008_EBX] = 3670 CPUID_8000_0008_EBX_WBNOINVD, 3671 .features[FEAT_7_0_EBX] = 3672 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3673 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3674 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3675 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3676 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3677 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3678 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3679 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3680 .features[FEAT_7_0_ECX] = 3681 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 3682 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 3683 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 3684 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 3685 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57, 3686 .features[FEAT_7_0_EDX] = 3687 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 3688 /* XSAVES is added in version 5 */ 3689 .features[FEAT_XSAVE] = 3690 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3691 CPUID_XSAVE_XGETBV1, 3692 .features[FEAT_6_EAX] = 3693 CPUID_6_EAX_ARAT, 3694 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3695 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3696 MSR_VMX_BASIC_TRUE_CTLS, 3697 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3698 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3699 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3700 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3701 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3702 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3703 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3704 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3705 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3706 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3707 .features[FEAT_VMX_EXIT_CTLS] = 3708 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3709 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3710 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3711 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3712 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3713 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3714 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3715 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3716 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3717 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3718 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3719 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3720 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3721 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3722 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3723 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3724 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3725 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3726 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3727 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3728 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3729 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3730 .features[FEAT_VMX_SECONDARY_CTLS] = 3731 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3732 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3733 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3734 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3735 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3736 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3737 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3738 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3739 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS, 3740 .xlevel = 0x80000008, 3741 .model_id = "Intel Xeon Processor (Icelake)", 3742 .versions = (X86CPUVersionDefinition[]) { 3743 { .version = 1 }, 3744 { 3745 .version = 2, 3746 .note = "no TSX", 3747 .alias = "Icelake-Server-noTSX", 3748 .props = (PropValue[]) { 3749 { "hle", "off" }, 3750 { "rtm", "off" }, 3751 { /* end of list */ } 3752 }, 3753 }, 3754 { 3755 .version = 3, 3756 .props = (PropValue[]) { 3757 { "arch-capabilities", "on" }, 3758 { "rdctl-no", "on" }, 3759 { "ibrs-all", "on" }, 3760 { "skip-l1dfl-vmentry", "on" }, 3761 { "mds-no", "on" }, 3762 { "pschange-mc-no", "on" }, 3763 { "taa-no", "on" }, 3764 { /* end of list */ } 3765 }, 3766 }, 3767 { 3768 .version = 4, 3769 .props = (PropValue[]) { 3770 { "sha-ni", "on" }, 3771 { "avx512ifma", "on" }, 3772 { "rdpid", "on" }, 3773 { "fsrm", "on" }, 3774 { "vmx-rdseed-exit", "on" }, 3775 { "vmx-pml", "on" }, 3776 { "vmx-eptp-switching", "on" }, 3777 { "model", "106" }, 3778 { /* end of list */ } 3779 }, 3780 }, 3781 { 3782 .version = 5, 3783 .note = "XSAVES", 3784 .props = (PropValue[]) { 3785 { "xsaves", "on" }, 3786 { "vmx-xsaves", "on" }, 3787 { /* end of list */ } 3788 }, 3789 }, 3790 { 3791 .version = 6, 3792 .note = "5-level EPT", 3793 .props = (PropValue[]) { 3794 { "vmx-page-walk-5", "on" }, 3795 { /* end of list */ } 3796 }, 3797 }, 3798 { /* end of list */ } 3799 } 3800 }, 3801 { 3802 .name = "SapphireRapids", 3803 .level = 0x20, 3804 .vendor = CPUID_VENDOR_INTEL, 3805 .family = 6, 3806 .model = 143, 3807 .stepping = 4, 3808 /* 3809 * please keep the ascending order so that we can have a clear view of 3810 * bit position of each feature. 3811 */ 3812 .features[FEAT_1_EDX] = 3813 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 3814 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 3815 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 3816 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 3817 CPUID_SSE | CPUID_SSE2, 3818 .features[FEAT_1_ECX] = 3819 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 3820 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 3821 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 3822 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 3823 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3824 .features[FEAT_8000_0001_EDX] = 3825 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 3826 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 3827 .features[FEAT_8000_0001_ECX] = 3828 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 3829 .features[FEAT_8000_0008_EBX] = 3830 CPUID_8000_0008_EBX_WBNOINVD, 3831 .features[FEAT_7_0_EBX] = 3832 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_HLE | 3833 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | 3834 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RTM | 3835 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3836 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | 3837 CPUID_7_0_EBX_AVX512IFMA | CPUID_7_0_EBX_CLFLUSHOPT | 3838 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | 3839 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, 3840 .features[FEAT_7_0_ECX] = 3841 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 3842 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 3843 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 3844 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 3845 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | 3846 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT, 3847 .features[FEAT_7_0_EDX] = 3848 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 3849 CPUID_7_0_EDX_TSX_LDTRK | CPUID_7_0_EDX_AMX_BF16 | 3850 CPUID_7_0_EDX_AVX512_FP16 | CPUID_7_0_EDX_AMX_TILE | 3851 CPUID_7_0_EDX_AMX_INT8 | CPUID_7_0_EDX_SPEC_CTRL | 3852 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 3853 .features[FEAT_ARCH_CAPABILITIES] = 3854 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 3855 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 3856 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO, 3857 .features[FEAT_XSAVE] = 3858 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3859 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES | CPUID_D_1_EAX_XFD, 3860 .features[FEAT_6_EAX] = 3861 CPUID_6_EAX_ARAT, 3862 .features[FEAT_7_1_EAX] = 3863 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_AVX512_BF16 | 3864 CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC, 3865 .features[FEAT_VMX_BASIC] = 3866 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 3867 .features[FEAT_VMX_ENTRY_CTLS] = 3868 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 3869 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 3870 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 3871 .features[FEAT_VMX_EPT_VPID_CAPS] = 3872 MSR_VMX_EPT_EXECONLY | 3873 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_PAGE_WALK_LENGTH_5 | 3874 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 3875 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 3876 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3877 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3878 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 3879 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3880 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 3881 .features[FEAT_VMX_EXIT_CTLS] = 3882 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3883 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3884 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 3885 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3886 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3887 .features[FEAT_VMX_MISC] = 3888 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 3889 MSR_VMX_MISC_VMWRITE_VMEXIT, 3890 .features[FEAT_VMX_PINBASED_CTLS] = 3891 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 3892 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 3893 VMX_PIN_BASED_POSTED_INTR, 3894 .features[FEAT_VMX_PROCBASED_CTLS] = 3895 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3896 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3897 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3898 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3899 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3900 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3901 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 3902 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 3903 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3904 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 3905 VMX_CPU_BASED_PAUSE_EXITING | 3906 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3907 .features[FEAT_VMX_SECONDARY_CTLS] = 3908 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3909 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 3910 VMX_SECONDARY_EXEC_RDTSCP | 3911 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3912 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 3913 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3914 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3915 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3916 VMX_SECONDARY_EXEC_RDRAND_EXITING | 3917 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3918 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3919 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 3920 VMX_SECONDARY_EXEC_XSAVES, 3921 .features[FEAT_VMX_VMFUNC] = 3922 MSR_VMX_VMFUNC_EPT_SWITCHING, 3923 .xlevel = 0x80000008, 3924 .model_id = "Intel Xeon Processor (SapphireRapids)", 3925 .versions = (X86CPUVersionDefinition[]) { 3926 { .version = 1 }, 3927 { /* end of list */ }, 3928 }, 3929 }, 3930 { 3931 .name = "Denverton", 3932 .level = 21, 3933 .vendor = CPUID_VENDOR_INTEL, 3934 .family = 6, 3935 .model = 95, 3936 .stepping = 1, 3937 .features[FEAT_1_EDX] = 3938 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 3939 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 3940 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 3941 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 3942 CPUID_SSE | CPUID_SSE2, 3943 .features[FEAT_1_ECX] = 3944 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR | 3945 CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_SSE41 | 3946 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 3947 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | 3948 CPUID_EXT_AES | CPUID_EXT_XSAVE | CPUID_EXT_RDRAND, 3949 .features[FEAT_8000_0001_EDX] = 3950 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 3951 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 3952 .features[FEAT_8000_0001_ECX] = 3953 CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3954 .features[FEAT_7_0_EBX] = 3955 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_ERMS | 3956 CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_SMAP | 3957 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_SHA_NI, 3958 .features[FEAT_7_0_EDX] = 3959 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES | 3960 CPUID_7_0_EDX_SPEC_CTRL_SSBD, 3961 /* XSAVES is added in version 3 */ 3962 .features[FEAT_XSAVE] = 3963 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | CPUID_XSAVE_XGETBV1, 3964 .features[FEAT_6_EAX] = 3965 CPUID_6_EAX_ARAT, 3966 .features[FEAT_ARCH_CAPABILITIES] = 3967 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY, 3968 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3969 MSR_VMX_BASIC_TRUE_CTLS, 3970 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3971 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3972 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3973 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3974 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3975 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3976 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3977 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3978 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3979 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3980 .features[FEAT_VMX_EXIT_CTLS] = 3981 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3982 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3983 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3984 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3985 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3986 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3987 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3988 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3989 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3990 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3991 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3992 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3993 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3994 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3995 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3996 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3997 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3998 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3999 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 4000 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4001 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4002 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4003 .features[FEAT_VMX_SECONDARY_CTLS] = 4004 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4005 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 4006 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 4007 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4008 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4009 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4010 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4011 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4012 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4013 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 4014 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 4015 .xlevel = 0x80000008, 4016 .model_id = "Intel Atom Processor (Denverton)", 4017 .versions = (X86CPUVersionDefinition[]) { 4018 { .version = 1 }, 4019 { 4020 .version = 2, 4021 .note = "no MPX, no MONITOR", 4022 .props = (PropValue[]) { 4023 { "monitor", "off" }, 4024 { "mpx", "off" }, 4025 { /* end of list */ }, 4026 }, 4027 }, 4028 { 4029 .version = 3, 4030 .note = "XSAVES, no MPX, no MONITOR", 4031 .props = (PropValue[]) { 4032 { "xsaves", "on" }, 4033 { "vmx-xsaves", "on" }, 4034 { /* end of list */ }, 4035 }, 4036 }, 4037 { /* end of list */ }, 4038 }, 4039 }, 4040 { 4041 .name = "Snowridge", 4042 .level = 27, 4043 .vendor = CPUID_VENDOR_INTEL, 4044 .family = 6, 4045 .model = 134, 4046 .stepping = 1, 4047 .features[FEAT_1_EDX] = 4048 /* missing: CPUID_PN CPUID_IA64 */ 4049 /* missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 4050 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | 4051 CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_MCE | 4052 CPUID_CX8 | CPUID_APIC | CPUID_SEP | 4053 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4054 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | 4055 CPUID_MMX | 4056 CPUID_FXSR | CPUID_SSE | CPUID_SSE2, 4057 .features[FEAT_1_ECX] = 4058 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR | 4059 CPUID_EXT_SSSE3 | 4060 CPUID_EXT_CX16 | 4061 CPUID_EXT_SSE41 | 4062 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4063 CPUID_EXT_POPCNT | 4064 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | CPUID_EXT_XSAVE | 4065 CPUID_EXT_RDRAND, 4066 .features[FEAT_8000_0001_EDX] = 4067 CPUID_EXT2_SYSCALL | 4068 CPUID_EXT2_NX | 4069 CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 4070 CPUID_EXT2_LM, 4071 .features[FEAT_8000_0001_ECX] = 4072 CPUID_EXT3_LAHF_LM | 4073 CPUID_EXT3_3DNOWPREFETCH, 4074 .features[FEAT_7_0_EBX] = 4075 CPUID_7_0_EBX_FSGSBASE | 4076 CPUID_7_0_EBX_SMEP | 4077 CPUID_7_0_EBX_ERMS | 4078 CPUID_7_0_EBX_MPX | /* missing bits 13, 15 */ 4079 CPUID_7_0_EBX_RDSEED | 4080 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 4081 CPUID_7_0_EBX_CLWB | 4082 CPUID_7_0_EBX_SHA_NI, 4083 .features[FEAT_7_0_ECX] = 4084 CPUID_7_0_ECX_UMIP | 4085 /* missing bit 5 */ 4086 CPUID_7_0_ECX_GFNI | 4087 CPUID_7_0_ECX_MOVDIRI | CPUID_7_0_ECX_CLDEMOTE | 4088 CPUID_7_0_ECX_MOVDIR64B, 4089 .features[FEAT_7_0_EDX] = 4090 CPUID_7_0_EDX_SPEC_CTRL | 4091 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD | 4092 CPUID_7_0_EDX_CORE_CAPABILITY, 4093 .features[FEAT_CORE_CAPABILITY] = 4094 MSR_CORE_CAP_SPLIT_LOCK_DETECT, 4095 /* XSAVES is added in version 3 */ 4096 .features[FEAT_XSAVE] = 4097 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4098 CPUID_XSAVE_XGETBV1, 4099 .features[FEAT_6_EAX] = 4100 CPUID_6_EAX_ARAT, 4101 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 4102 MSR_VMX_BASIC_TRUE_CTLS, 4103 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 4104 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 4105 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 4106 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 4107 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 4108 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 4109 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4110 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4111 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4112 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 4113 .features[FEAT_VMX_EXIT_CTLS] = 4114 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4115 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4116 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 4117 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4118 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4119 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 4120 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 4121 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 4122 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 4123 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 4124 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4125 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4126 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4127 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4128 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4129 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 4130 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 4131 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 4132 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 4133 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4134 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4135 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4136 .features[FEAT_VMX_SECONDARY_CTLS] = 4137 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4138 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 4139 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 4140 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4141 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4142 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4143 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4144 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4145 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4146 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 4147 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 4148 .xlevel = 0x80000008, 4149 .model_id = "Intel Atom Processor (SnowRidge)", 4150 .versions = (X86CPUVersionDefinition[]) { 4151 { .version = 1 }, 4152 { 4153 .version = 2, 4154 .props = (PropValue[]) { 4155 { "mpx", "off" }, 4156 { "model-id", "Intel Atom Processor (Snowridge, no MPX)" }, 4157 { /* end of list */ }, 4158 }, 4159 }, 4160 { 4161 .version = 3, 4162 .note = "XSAVES, no MPX", 4163 .props = (PropValue[]) { 4164 { "xsaves", "on" }, 4165 { "vmx-xsaves", "on" }, 4166 { /* end of list */ }, 4167 }, 4168 }, 4169 { 4170 .version = 4, 4171 .note = "no split lock detect, no core-capability", 4172 .props = (PropValue[]) { 4173 { "split-lock-detect", "off" }, 4174 { "core-capability", "off" }, 4175 { /* end of list */ }, 4176 }, 4177 }, 4178 { /* end of list */ }, 4179 }, 4180 }, 4181 { 4182 .name = "KnightsMill", 4183 .level = 0xd, 4184 .vendor = CPUID_VENDOR_INTEL, 4185 .family = 6, 4186 .model = 133, 4187 .stepping = 0, 4188 .features[FEAT_1_EDX] = 4189 CPUID_VME | CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | 4190 CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | 4191 CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | 4192 CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | 4193 CPUID_PSE | CPUID_DE | CPUID_FP87, 4194 .features[FEAT_1_ECX] = 4195 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 4196 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 4197 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 4198 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 4199 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 4200 CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4201 .features[FEAT_8000_0001_EDX] = 4202 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 4203 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 4204 .features[FEAT_8000_0001_ECX] = 4205 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 4206 .features[FEAT_7_0_EBX] = 4207 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4208 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 4209 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_AVX512F | 4210 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_AVX512PF | 4211 CPUID_7_0_EBX_AVX512ER, 4212 .features[FEAT_7_0_ECX] = 4213 CPUID_7_0_ECX_AVX512_VPOPCNTDQ, 4214 .features[FEAT_7_0_EDX] = 4215 CPUID_7_0_EDX_AVX512_4VNNIW | CPUID_7_0_EDX_AVX512_4FMAPS, 4216 .features[FEAT_XSAVE] = 4217 CPUID_XSAVE_XSAVEOPT, 4218 .features[FEAT_6_EAX] = 4219 CPUID_6_EAX_ARAT, 4220 .xlevel = 0x80000008, 4221 .model_id = "Intel Xeon Phi Processor (Knights Mill)", 4222 }, 4223 { 4224 .name = "Opteron_G1", 4225 .level = 5, 4226 .vendor = CPUID_VENDOR_AMD, 4227 .family = 15, 4228 .model = 6, 4229 .stepping = 1, 4230 .features[FEAT_1_EDX] = 4231 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4232 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4233 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4234 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4235 CPUID_DE | CPUID_FP87, 4236 .features[FEAT_1_ECX] = 4237 CPUID_EXT_SSE3, 4238 .features[FEAT_8000_0001_EDX] = 4239 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 4240 .xlevel = 0x80000008, 4241 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)", 4242 }, 4243 { 4244 .name = "Opteron_G2", 4245 .level = 5, 4246 .vendor = CPUID_VENDOR_AMD, 4247 .family = 15, 4248 .model = 6, 4249 .stepping = 1, 4250 .features[FEAT_1_EDX] = 4251 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4252 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4253 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4254 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4255 CPUID_DE | CPUID_FP87, 4256 .features[FEAT_1_ECX] = 4257 CPUID_EXT_CX16 | CPUID_EXT_SSE3, 4258 .features[FEAT_8000_0001_EDX] = 4259 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 4260 .features[FEAT_8000_0001_ECX] = 4261 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, 4262 .xlevel = 0x80000008, 4263 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)", 4264 }, 4265 { 4266 .name = "Opteron_G3", 4267 .level = 5, 4268 .vendor = CPUID_VENDOR_AMD, 4269 .family = 16, 4270 .model = 2, 4271 .stepping = 3, 4272 .features[FEAT_1_EDX] = 4273 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4274 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4275 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4276 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4277 CPUID_DE | CPUID_FP87, 4278 .features[FEAT_1_ECX] = 4279 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR | 4280 CPUID_EXT_SSE3, 4281 .features[FEAT_8000_0001_EDX] = 4282 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL | 4283 CPUID_EXT2_RDTSCP, 4284 .features[FEAT_8000_0001_ECX] = 4285 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | 4286 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, 4287 .xlevel = 0x80000008, 4288 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)", 4289 }, 4290 { 4291 .name = "Opteron_G4", 4292 .level = 0xd, 4293 .vendor = CPUID_VENDOR_AMD, 4294 .family = 21, 4295 .model = 1, 4296 .stepping = 2, 4297 .features[FEAT_1_EDX] = 4298 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4299 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4300 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4301 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4302 CPUID_DE | CPUID_FP87, 4303 .features[FEAT_1_ECX] = 4304 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 4305 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 4306 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 4307 CPUID_EXT_SSE3, 4308 .features[FEAT_8000_0001_EDX] = 4309 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX | 4310 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP, 4311 .features[FEAT_8000_0001_ECX] = 4312 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP | 4313 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | 4314 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | 4315 CPUID_EXT3_LAHF_LM, 4316 .features[FEAT_SVM] = 4317 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 4318 /* no xsaveopt! */ 4319 .xlevel = 0x8000001A, 4320 .model_id = "AMD Opteron 62xx class CPU", 4321 }, 4322 { 4323 .name = "Opteron_G5", 4324 .level = 0xd, 4325 .vendor = CPUID_VENDOR_AMD, 4326 .family = 21, 4327 .model = 2, 4328 .stepping = 0, 4329 .features[FEAT_1_EDX] = 4330 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4331 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4332 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4333 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4334 CPUID_DE | CPUID_FP87, 4335 .features[FEAT_1_ECX] = 4336 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE | 4337 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | 4338 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA | 4339 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 4340 .features[FEAT_8000_0001_EDX] = 4341 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX | 4342 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP, 4343 .features[FEAT_8000_0001_ECX] = 4344 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP | 4345 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | 4346 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | 4347 CPUID_EXT3_LAHF_LM, 4348 .features[FEAT_SVM] = 4349 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 4350 /* no xsaveopt! */ 4351 .xlevel = 0x8000001A, 4352 .model_id = "AMD Opteron 63xx class CPU", 4353 }, 4354 { 4355 .name = "EPYC", 4356 .level = 0xd, 4357 .vendor = CPUID_VENDOR_AMD, 4358 .family = 23, 4359 .model = 1, 4360 .stepping = 2, 4361 .features[FEAT_1_EDX] = 4362 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 4363 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 4364 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 4365 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 4366 CPUID_VME | CPUID_FP87, 4367 .features[FEAT_1_ECX] = 4368 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 4369 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 4370 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 4371 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 4372 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 4373 .features[FEAT_8000_0001_EDX] = 4374 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 4375 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 4376 CPUID_EXT2_SYSCALL, 4377 .features[FEAT_8000_0001_ECX] = 4378 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 4379 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 4380 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 4381 CPUID_EXT3_TOPOEXT, 4382 .features[FEAT_7_0_EBX] = 4383 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4384 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 4385 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 4386 CPUID_7_0_EBX_SHA_NI, 4387 .features[FEAT_XSAVE] = 4388 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4389 CPUID_XSAVE_XGETBV1, 4390 .features[FEAT_6_EAX] = 4391 CPUID_6_EAX_ARAT, 4392 .features[FEAT_SVM] = 4393 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 4394 .xlevel = 0x8000001E, 4395 .model_id = "AMD EPYC Processor", 4396 .cache_info = &epyc_cache_info, 4397 .versions = (X86CPUVersionDefinition[]) { 4398 { .version = 1 }, 4399 { 4400 .version = 2, 4401 .alias = "EPYC-IBPB", 4402 .props = (PropValue[]) { 4403 { "ibpb", "on" }, 4404 { "model-id", 4405 "AMD EPYC Processor (with IBPB)" }, 4406 { /* end of list */ } 4407 } 4408 }, 4409 { 4410 .version = 3, 4411 .props = (PropValue[]) { 4412 { "ibpb", "on" }, 4413 { "perfctr-core", "on" }, 4414 { "clzero", "on" }, 4415 { "xsaveerptr", "on" }, 4416 { "xsaves", "on" }, 4417 { "model-id", 4418 "AMD EPYC Processor" }, 4419 { /* end of list */ } 4420 } 4421 }, 4422 { 4423 .version = 4, 4424 .props = (PropValue[]) { 4425 { "model-id", 4426 "AMD EPYC-v4 Processor" }, 4427 { /* end of list */ } 4428 }, 4429 .cache_info = &epyc_v4_cache_info 4430 }, 4431 { /* end of list */ } 4432 } 4433 }, 4434 { 4435 .name = "Dhyana", 4436 .level = 0xd, 4437 .vendor = CPUID_VENDOR_HYGON, 4438 .family = 24, 4439 .model = 0, 4440 .stepping = 1, 4441 .features[FEAT_1_EDX] = 4442 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 4443 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 4444 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 4445 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 4446 CPUID_VME | CPUID_FP87, 4447 .features[FEAT_1_ECX] = 4448 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 4449 CPUID_EXT_XSAVE | CPUID_EXT_POPCNT | 4450 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 4451 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 4452 CPUID_EXT_MONITOR | CPUID_EXT_SSE3, 4453 .features[FEAT_8000_0001_EDX] = 4454 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 4455 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 4456 CPUID_EXT2_SYSCALL, 4457 .features[FEAT_8000_0001_ECX] = 4458 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 4459 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 4460 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 4461 CPUID_EXT3_TOPOEXT, 4462 .features[FEAT_8000_0008_EBX] = 4463 CPUID_8000_0008_EBX_IBPB, 4464 .features[FEAT_7_0_EBX] = 4465 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4466 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 4467 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT, 4468 /* XSAVES is added in version 2 */ 4469 .features[FEAT_XSAVE] = 4470 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4471 CPUID_XSAVE_XGETBV1, 4472 .features[FEAT_6_EAX] = 4473 CPUID_6_EAX_ARAT, 4474 .features[FEAT_SVM] = 4475 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 4476 .xlevel = 0x8000001E, 4477 .model_id = "Hygon Dhyana Processor", 4478 .cache_info = &epyc_cache_info, 4479 .versions = (X86CPUVersionDefinition[]) { 4480 { .version = 1 }, 4481 { .version = 2, 4482 .note = "XSAVES", 4483 .props = (PropValue[]) { 4484 { "xsaves", "on" }, 4485 { /* end of list */ } 4486 }, 4487 }, 4488 { /* end of list */ } 4489 } 4490 }, 4491 { 4492 .name = "EPYC-Rome", 4493 .level = 0xd, 4494 .vendor = CPUID_VENDOR_AMD, 4495 .family = 23, 4496 .model = 49, 4497 .stepping = 0, 4498 .features[FEAT_1_EDX] = 4499 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 4500 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 4501 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 4502 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 4503 CPUID_VME | CPUID_FP87, 4504 .features[FEAT_1_ECX] = 4505 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 4506 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 4507 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 4508 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 4509 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 4510 .features[FEAT_8000_0001_EDX] = 4511 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 4512 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 4513 CPUID_EXT2_SYSCALL, 4514 .features[FEAT_8000_0001_ECX] = 4515 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 4516 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 4517 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 4518 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 4519 .features[FEAT_8000_0008_EBX] = 4520 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 4521 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 4522 CPUID_8000_0008_EBX_STIBP, 4523 .features[FEAT_7_0_EBX] = 4524 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4525 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 4526 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 4527 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB, 4528 .features[FEAT_7_0_ECX] = 4529 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID, 4530 .features[FEAT_XSAVE] = 4531 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4532 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 4533 .features[FEAT_6_EAX] = 4534 CPUID_6_EAX_ARAT, 4535 .features[FEAT_SVM] = 4536 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 4537 .xlevel = 0x8000001E, 4538 .model_id = "AMD EPYC-Rome Processor", 4539 .cache_info = &epyc_rome_cache_info, 4540 .versions = (X86CPUVersionDefinition[]) { 4541 { .version = 1 }, 4542 { 4543 .version = 2, 4544 .props = (PropValue[]) { 4545 { "ibrs", "on" }, 4546 { "amd-ssbd", "on" }, 4547 { /* end of list */ } 4548 } 4549 }, 4550 { 4551 .version = 3, 4552 .props = (PropValue[]) { 4553 { "model-id", 4554 "AMD EPYC-Rome-v3 Processor" }, 4555 { /* end of list */ } 4556 }, 4557 .cache_info = &epyc_rome_v3_cache_info 4558 }, 4559 { 4560 .version = 4, 4561 .props = (PropValue[]) { 4562 /* Erratum 1386 */ 4563 { "model-id", 4564 "AMD EPYC-Rome-v4 Processor (no XSAVES)" }, 4565 { "xsaves", "off" }, 4566 { /* end of list */ } 4567 }, 4568 }, 4569 { /* end of list */ } 4570 } 4571 }, 4572 { 4573 .name = "EPYC-Milan", 4574 .level = 0xd, 4575 .vendor = CPUID_VENDOR_AMD, 4576 .family = 25, 4577 .model = 1, 4578 .stepping = 1, 4579 .features[FEAT_1_EDX] = 4580 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 4581 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 4582 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 4583 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 4584 CPUID_VME | CPUID_FP87, 4585 .features[FEAT_1_ECX] = 4586 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 4587 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 4588 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 4589 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 4590 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 4591 CPUID_EXT_PCID, 4592 .features[FEAT_8000_0001_EDX] = 4593 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 4594 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 4595 CPUID_EXT2_SYSCALL, 4596 .features[FEAT_8000_0001_ECX] = 4597 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 4598 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 4599 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 4600 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 4601 .features[FEAT_8000_0008_EBX] = 4602 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 4603 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 4604 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | 4605 CPUID_8000_0008_EBX_AMD_SSBD, 4606 .features[FEAT_7_0_EBX] = 4607 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4608 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 4609 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 4610 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_ERMS | 4611 CPUID_7_0_EBX_INVPCID, 4612 .features[FEAT_7_0_ECX] = 4613 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_PKU, 4614 .features[FEAT_7_0_EDX] = 4615 CPUID_7_0_EDX_FSRM, 4616 .features[FEAT_XSAVE] = 4617 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4618 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 4619 .features[FEAT_6_EAX] = 4620 CPUID_6_EAX_ARAT, 4621 .features[FEAT_SVM] = 4622 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE | CPUID_SVM_SVME_ADDR_CHK, 4623 .xlevel = 0x8000001E, 4624 .model_id = "AMD EPYC-Milan Processor", 4625 .cache_info = &epyc_milan_cache_info, 4626 .versions = (X86CPUVersionDefinition[]) { 4627 { .version = 1 }, 4628 { 4629 .version = 2, 4630 .props = (PropValue[]) { 4631 { "model-id", 4632 "AMD EPYC-Milan-v2 Processor" }, 4633 { "vaes", "on" }, 4634 { "vpclmulqdq", "on" }, 4635 { "stibp-always-on", "on" }, 4636 { "amd-psfd", "on" }, 4637 { "no-nested-data-bp", "on" }, 4638 { "lfence-always-serializing", "on" }, 4639 { "null-sel-clr-base", "on" }, 4640 { /* end of list */ } 4641 }, 4642 .cache_info = &epyc_milan_v2_cache_info 4643 }, 4644 { /* end of list */ } 4645 } 4646 }, 4647 { 4648 .name = "EPYC-Genoa", 4649 .level = 0xd, 4650 .vendor = CPUID_VENDOR_AMD, 4651 .family = 25, 4652 .model = 17, 4653 .stepping = 0, 4654 .features[FEAT_1_EDX] = 4655 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 4656 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 4657 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 4658 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 4659 CPUID_VME | CPUID_FP87, 4660 .features[FEAT_1_ECX] = 4661 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 4662 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 4663 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 4664 CPUID_EXT_PCID | CPUID_EXT_CX16 | CPUID_EXT_FMA | 4665 CPUID_EXT_SSSE3 | CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | 4666 CPUID_EXT_SSE3, 4667 .features[FEAT_8000_0001_EDX] = 4668 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 4669 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 4670 CPUID_EXT2_SYSCALL, 4671 .features[FEAT_8000_0001_ECX] = 4672 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 4673 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 4674 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 4675 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 4676 .features[FEAT_8000_0008_EBX] = 4677 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 4678 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 4679 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | 4680 CPUID_8000_0008_EBX_STIBP_ALWAYS_ON | 4681 CPUID_8000_0008_EBX_AMD_SSBD | CPUID_8000_0008_EBX_AMD_PSFD, 4682 .features[FEAT_8000_0021_EAX] = 4683 CPUID_8000_0021_EAX_No_NESTED_DATA_BP | 4684 CPUID_8000_0021_EAX_LFENCE_ALWAYS_SERIALIZING | 4685 CPUID_8000_0021_EAX_NULL_SEL_CLR_BASE | 4686 CPUID_8000_0021_EAX_AUTO_IBRS, 4687 .features[FEAT_7_0_EBX] = 4688 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4689 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 4690 CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_AVX512F | 4691 CPUID_7_0_EBX_AVX512DQ | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 4692 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_AVX512IFMA | 4693 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB | 4694 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | 4695 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, 4696 .features[FEAT_7_0_ECX] = 4697 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 4698 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 4699 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4700 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 4701 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | 4702 CPUID_7_0_ECX_RDPID, 4703 .features[FEAT_7_0_EDX] = 4704 CPUID_7_0_EDX_FSRM, 4705 .features[FEAT_7_1_EAX] = 4706 CPUID_7_1_EAX_AVX512_BF16, 4707 .features[FEAT_XSAVE] = 4708 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4709 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 4710 .features[FEAT_6_EAX] = 4711 CPUID_6_EAX_ARAT, 4712 .features[FEAT_SVM] = 4713 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE | CPUID_SVM_VNMI | 4714 CPUID_SVM_SVME_ADDR_CHK, 4715 .xlevel = 0x80000022, 4716 .model_id = "AMD EPYC-Genoa Processor", 4717 .cache_info = &epyc_genoa_cache_info, 4718 }, 4719 }; 4720 4721 /* 4722 * We resolve CPU model aliases using -v1 when using "-machine 4723 * none", but this is just for compatibility while libvirt isn't 4724 * adapted to resolve CPU model versions before creating VMs. 4725 * See "Runnability guarantee of CPU models" at 4726 * docs/about/deprecated.rst. 4727 */ 4728 X86CPUVersion default_cpu_version = 1; 4729 4730 void x86_cpu_set_default_version(X86CPUVersion version) 4731 { 4732 /* Translating CPU_VERSION_AUTO to CPU_VERSION_AUTO doesn't make sense */ 4733 assert(version != CPU_VERSION_AUTO); 4734 default_cpu_version = version; 4735 } 4736 4737 static X86CPUVersion x86_cpu_model_last_version(const X86CPUModel *model) 4738 { 4739 int v = 0; 4740 const X86CPUVersionDefinition *vdef = 4741 x86_cpu_def_get_versions(model->cpudef); 4742 while (vdef->version) { 4743 v = vdef->version; 4744 vdef++; 4745 } 4746 return v; 4747 } 4748 4749 /* Return the actual version being used for a specific CPU model */ 4750 static X86CPUVersion x86_cpu_model_resolve_version(const X86CPUModel *model) 4751 { 4752 X86CPUVersion v = model->version; 4753 if (v == CPU_VERSION_AUTO) { 4754 v = default_cpu_version; 4755 } 4756 if (v == CPU_VERSION_LATEST) { 4757 return x86_cpu_model_last_version(model); 4758 } 4759 return v; 4760 } 4761 4762 static Property max_x86_cpu_properties[] = { 4763 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true), 4764 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false), 4765 DEFINE_PROP_END_OF_LIST() 4766 }; 4767 4768 static void max_x86_cpu_realize(DeviceState *dev, Error **errp) 4769 { 4770 Object *obj = OBJECT(dev); 4771 4772 if (!object_property_get_int(obj, "family", &error_abort)) { 4773 if (X86_CPU(obj)->env.features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 4774 object_property_set_int(obj, "family", 15, &error_abort); 4775 object_property_set_int(obj, "model", 107, &error_abort); 4776 object_property_set_int(obj, "stepping", 1, &error_abort); 4777 } else { 4778 object_property_set_int(obj, "family", 6, &error_abort); 4779 object_property_set_int(obj, "model", 6, &error_abort); 4780 object_property_set_int(obj, "stepping", 3, &error_abort); 4781 } 4782 } 4783 4784 x86_cpu_realizefn(dev, errp); 4785 } 4786 4787 static void max_x86_cpu_class_init(ObjectClass *oc, void *data) 4788 { 4789 DeviceClass *dc = DEVICE_CLASS(oc); 4790 X86CPUClass *xcc = X86_CPU_CLASS(oc); 4791 4792 xcc->ordering = 9; 4793 4794 xcc->model_description = 4795 "Enables all features supported by the accelerator in the current host"; 4796 4797 device_class_set_props(dc, max_x86_cpu_properties); 4798 dc->realize = max_x86_cpu_realize; 4799 } 4800 4801 static void max_x86_cpu_initfn(Object *obj) 4802 { 4803 X86CPU *cpu = X86_CPU(obj); 4804 4805 /* We can't fill the features array here because we don't know yet if 4806 * "migratable" is true or false. 4807 */ 4808 cpu->max_features = true; 4809 object_property_set_bool(OBJECT(cpu), "pmu", true, &error_abort); 4810 4811 /* 4812 * these defaults are used for TCG and all other accelerators 4813 * besides KVM and HVF, which overwrite these values 4814 */ 4815 object_property_set_str(OBJECT(cpu), "vendor", CPUID_VENDOR_AMD, 4816 &error_abort); 4817 object_property_set_str(OBJECT(cpu), "model-id", 4818 "QEMU TCG CPU version " QEMU_HW_VERSION, 4819 &error_abort); 4820 } 4821 4822 static const TypeInfo max_x86_cpu_type_info = { 4823 .name = X86_CPU_TYPE_NAME("max"), 4824 .parent = TYPE_X86_CPU, 4825 .instance_init = max_x86_cpu_initfn, 4826 .class_init = max_x86_cpu_class_init, 4827 }; 4828 4829 static char *feature_word_description(FeatureWordInfo *f, uint32_t bit) 4830 { 4831 assert(f->type == CPUID_FEATURE_WORD || f->type == MSR_FEATURE_WORD); 4832 4833 switch (f->type) { 4834 case CPUID_FEATURE_WORD: 4835 { 4836 const char *reg = get_register_name_32(f->cpuid.reg); 4837 assert(reg); 4838 return g_strdup_printf("CPUID.%02XH:%s", 4839 f->cpuid.eax, reg); 4840 } 4841 case MSR_FEATURE_WORD: 4842 return g_strdup_printf("MSR(%02XH)", 4843 f->msr.index); 4844 } 4845 4846 return NULL; 4847 } 4848 4849 static bool x86_cpu_have_filtered_features(X86CPU *cpu) 4850 { 4851 FeatureWord w; 4852 4853 for (w = 0; w < FEATURE_WORDS; w++) { 4854 if (cpu->filtered_features[w]) { 4855 return true; 4856 } 4857 } 4858 4859 return false; 4860 } 4861 4862 static void mark_unavailable_features(X86CPU *cpu, FeatureWord w, uint64_t mask, 4863 const char *verbose_prefix) 4864 { 4865 CPUX86State *env = &cpu->env; 4866 FeatureWordInfo *f = &feature_word_info[w]; 4867 int i; 4868 4869 if (!cpu->force_features) { 4870 env->features[w] &= ~mask; 4871 } 4872 cpu->filtered_features[w] |= mask; 4873 4874 if (!verbose_prefix) { 4875 return; 4876 } 4877 4878 for (i = 0; i < 64; ++i) { 4879 if ((1ULL << i) & mask) { 4880 g_autofree char *feat_word_str = feature_word_description(f, i); 4881 warn_report("%s: %s%s%s [bit %d]", 4882 verbose_prefix, 4883 feat_word_str, 4884 f->feat_names[i] ? "." : "", 4885 f->feat_names[i] ? f->feat_names[i] : "", i); 4886 } 4887 } 4888 } 4889 4890 static void x86_cpuid_version_get_family(Object *obj, Visitor *v, 4891 const char *name, void *opaque, 4892 Error **errp) 4893 { 4894 X86CPU *cpu = X86_CPU(obj); 4895 CPUX86State *env = &cpu->env; 4896 int64_t value; 4897 4898 value = (env->cpuid_version >> 8) & 0xf; 4899 if (value == 0xf) { 4900 value += (env->cpuid_version >> 20) & 0xff; 4901 } 4902 visit_type_int(v, name, &value, errp); 4903 } 4904 4905 static void x86_cpuid_version_set_family(Object *obj, Visitor *v, 4906 const char *name, void *opaque, 4907 Error **errp) 4908 { 4909 X86CPU *cpu = X86_CPU(obj); 4910 CPUX86State *env = &cpu->env; 4911 const int64_t min = 0; 4912 const int64_t max = 0xff + 0xf; 4913 int64_t value; 4914 4915 if (!visit_type_int(v, name, &value, errp)) { 4916 return; 4917 } 4918 if (value < min || value > max) { 4919 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", 4920 name ? name : "null", value, min, max); 4921 return; 4922 } 4923 4924 env->cpuid_version &= ~0xff00f00; 4925 if (value > 0x0f) { 4926 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20); 4927 } else { 4928 env->cpuid_version |= value << 8; 4929 } 4930 } 4931 4932 static void x86_cpuid_version_get_model(Object *obj, Visitor *v, 4933 const char *name, void *opaque, 4934 Error **errp) 4935 { 4936 X86CPU *cpu = X86_CPU(obj); 4937 CPUX86State *env = &cpu->env; 4938 int64_t value; 4939 4940 value = (env->cpuid_version >> 4) & 0xf; 4941 value |= ((env->cpuid_version >> 16) & 0xf) << 4; 4942 visit_type_int(v, name, &value, errp); 4943 } 4944 4945 static void x86_cpuid_version_set_model(Object *obj, Visitor *v, 4946 const char *name, void *opaque, 4947 Error **errp) 4948 { 4949 X86CPU *cpu = X86_CPU(obj); 4950 CPUX86State *env = &cpu->env; 4951 const int64_t min = 0; 4952 const int64_t max = 0xff; 4953 int64_t value; 4954 4955 if (!visit_type_int(v, name, &value, errp)) { 4956 return; 4957 } 4958 if (value < min || value > max) { 4959 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", 4960 name ? name : "null", value, min, max); 4961 return; 4962 } 4963 4964 env->cpuid_version &= ~0xf00f0; 4965 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16); 4966 } 4967 4968 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v, 4969 const char *name, void *opaque, 4970 Error **errp) 4971 { 4972 X86CPU *cpu = X86_CPU(obj); 4973 CPUX86State *env = &cpu->env; 4974 int64_t value; 4975 4976 value = env->cpuid_version & 0xf; 4977 visit_type_int(v, name, &value, errp); 4978 } 4979 4980 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v, 4981 const char *name, void *opaque, 4982 Error **errp) 4983 { 4984 X86CPU *cpu = X86_CPU(obj); 4985 CPUX86State *env = &cpu->env; 4986 const int64_t min = 0; 4987 const int64_t max = 0xf; 4988 int64_t value; 4989 4990 if (!visit_type_int(v, name, &value, errp)) { 4991 return; 4992 } 4993 if (value < min || value > max) { 4994 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", 4995 name ? name : "null", value, min, max); 4996 return; 4997 } 4998 4999 env->cpuid_version &= ~0xf; 5000 env->cpuid_version |= value & 0xf; 5001 } 5002 5003 static char *x86_cpuid_get_vendor(Object *obj, Error **errp) 5004 { 5005 X86CPU *cpu = X86_CPU(obj); 5006 CPUX86State *env = &cpu->env; 5007 char *value; 5008 5009 value = g_malloc(CPUID_VENDOR_SZ + 1); 5010 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2, 5011 env->cpuid_vendor3); 5012 return value; 5013 } 5014 5015 static void x86_cpuid_set_vendor(Object *obj, const char *value, 5016 Error **errp) 5017 { 5018 X86CPU *cpu = X86_CPU(obj); 5019 CPUX86State *env = &cpu->env; 5020 int i; 5021 5022 if (strlen(value) != CPUID_VENDOR_SZ) { 5023 error_setg(errp, QERR_PROPERTY_VALUE_BAD, "", "vendor", value); 5024 return; 5025 } 5026 5027 env->cpuid_vendor1 = 0; 5028 env->cpuid_vendor2 = 0; 5029 env->cpuid_vendor3 = 0; 5030 for (i = 0; i < 4; i++) { 5031 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i); 5032 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i); 5033 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i); 5034 } 5035 } 5036 5037 static char *x86_cpuid_get_model_id(Object *obj, Error **errp) 5038 { 5039 X86CPU *cpu = X86_CPU(obj); 5040 CPUX86State *env = &cpu->env; 5041 char *value; 5042 int i; 5043 5044 value = g_malloc(48 + 1); 5045 for (i = 0; i < 48; i++) { 5046 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3)); 5047 } 5048 value[48] = '\0'; 5049 return value; 5050 } 5051 5052 static void x86_cpuid_set_model_id(Object *obj, const char *model_id, 5053 Error **errp) 5054 { 5055 X86CPU *cpu = X86_CPU(obj); 5056 CPUX86State *env = &cpu->env; 5057 int c, len, i; 5058 5059 if (model_id == NULL) { 5060 model_id = ""; 5061 } 5062 len = strlen(model_id); 5063 memset(env->cpuid_model, 0, 48); 5064 for (i = 0; i < 48; i++) { 5065 if (i >= len) { 5066 c = '\0'; 5067 } else { 5068 c = (uint8_t)model_id[i]; 5069 } 5070 env->cpuid_model[i >> 2] |= c << (8 * (i & 3)); 5071 } 5072 } 5073 5074 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name, 5075 void *opaque, Error **errp) 5076 { 5077 X86CPU *cpu = X86_CPU(obj); 5078 int64_t value; 5079 5080 value = cpu->env.tsc_khz * 1000; 5081 visit_type_int(v, name, &value, errp); 5082 } 5083 5084 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name, 5085 void *opaque, Error **errp) 5086 { 5087 X86CPU *cpu = X86_CPU(obj); 5088 const int64_t min = 0; 5089 const int64_t max = INT64_MAX; 5090 int64_t value; 5091 5092 if (!visit_type_int(v, name, &value, errp)) { 5093 return; 5094 } 5095 if (value < min || value > max) { 5096 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", 5097 name ? name : "null", value, min, max); 5098 return; 5099 } 5100 5101 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000; 5102 } 5103 5104 /* Generic getter for "feature-words" and "filtered-features" properties */ 5105 static void x86_cpu_get_feature_words(Object *obj, Visitor *v, 5106 const char *name, void *opaque, 5107 Error **errp) 5108 { 5109 uint64_t *array = (uint64_t *)opaque; 5110 FeatureWord w; 5111 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { }; 5112 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { }; 5113 X86CPUFeatureWordInfoList *list = NULL; 5114 5115 for (w = 0; w < FEATURE_WORDS; w++) { 5116 FeatureWordInfo *wi = &feature_word_info[w]; 5117 /* 5118 * We didn't have MSR features when "feature-words" was 5119 * introduced. Therefore skipped other type entries. 5120 */ 5121 if (wi->type != CPUID_FEATURE_WORD) { 5122 continue; 5123 } 5124 X86CPUFeatureWordInfo *qwi = &word_infos[w]; 5125 qwi->cpuid_input_eax = wi->cpuid.eax; 5126 qwi->has_cpuid_input_ecx = wi->cpuid.needs_ecx; 5127 qwi->cpuid_input_ecx = wi->cpuid.ecx; 5128 qwi->cpuid_register = x86_reg_info_32[wi->cpuid.reg].qapi_enum; 5129 qwi->features = array[w]; 5130 5131 /* List will be in reverse order, but order shouldn't matter */ 5132 list_entries[w].next = list; 5133 list_entries[w].value = &word_infos[w]; 5134 list = &list_entries[w]; 5135 } 5136 5137 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp); 5138 } 5139 5140 /* Convert all '_' in a feature string option name to '-', to make feature 5141 * name conform to QOM property naming rule, which uses '-' instead of '_'. 5142 */ 5143 static inline void feat2prop(char *s) 5144 { 5145 while ((s = strchr(s, '_'))) { 5146 *s = '-'; 5147 } 5148 } 5149 5150 /* Return the feature property name for a feature flag bit */ 5151 static const char *x86_cpu_feature_name(FeatureWord w, int bitnr) 5152 { 5153 const char *name; 5154 /* XSAVE components are automatically enabled by other features, 5155 * so return the original feature name instead 5156 */ 5157 if (w == FEAT_XSAVE_XCR0_LO || w == FEAT_XSAVE_XCR0_HI) { 5158 int comp = (w == FEAT_XSAVE_XCR0_HI) ? bitnr + 32 : bitnr; 5159 5160 if (comp < ARRAY_SIZE(x86_ext_save_areas) && 5161 x86_ext_save_areas[comp].bits) { 5162 w = x86_ext_save_areas[comp].feature; 5163 bitnr = ctz32(x86_ext_save_areas[comp].bits); 5164 } 5165 } 5166 5167 assert(bitnr < 64); 5168 assert(w < FEATURE_WORDS); 5169 name = feature_word_info[w].feat_names[bitnr]; 5170 assert(bitnr < 32 || !(name && feature_word_info[w].type == CPUID_FEATURE_WORD)); 5171 return name; 5172 } 5173 5174 /* Compatibily hack to maintain legacy +-feat semantic, 5175 * where +-feat overwrites any feature set by 5176 * feat=on|feat even if the later is parsed after +-feat 5177 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled) 5178 */ 5179 static GList *plus_features, *minus_features; 5180 5181 static gint compare_string(gconstpointer a, gconstpointer b) 5182 { 5183 return g_strcmp0(a, b); 5184 } 5185 5186 /* Parse "+feature,-feature,feature=foo" CPU feature string 5187 */ 5188 static void x86_cpu_parse_featurestr(const char *typename, char *features, 5189 Error **errp) 5190 { 5191 char *featurestr; /* Single 'key=value" string being parsed */ 5192 static bool cpu_globals_initialized; 5193 bool ambiguous = false; 5194 5195 if (cpu_globals_initialized) { 5196 return; 5197 } 5198 cpu_globals_initialized = true; 5199 5200 if (!features) { 5201 return; 5202 } 5203 5204 for (featurestr = strtok(features, ","); 5205 featurestr; 5206 featurestr = strtok(NULL, ",")) { 5207 const char *name; 5208 const char *val = NULL; 5209 char *eq = NULL; 5210 char num[32]; 5211 GlobalProperty *prop; 5212 5213 /* Compatibility syntax: */ 5214 if (featurestr[0] == '+') { 5215 plus_features = g_list_append(plus_features, 5216 g_strdup(featurestr + 1)); 5217 continue; 5218 } else if (featurestr[0] == '-') { 5219 minus_features = g_list_append(minus_features, 5220 g_strdup(featurestr + 1)); 5221 continue; 5222 } 5223 5224 eq = strchr(featurestr, '='); 5225 if (eq) { 5226 *eq++ = 0; 5227 val = eq; 5228 } else { 5229 val = "on"; 5230 } 5231 5232 feat2prop(featurestr); 5233 name = featurestr; 5234 5235 if (g_list_find_custom(plus_features, name, compare_string)) { 5236 warn_report("Ambiguous CPU model string. " 5237 "Don't mix both \"+%s\" and \"%s=%s\"", 5238 name, name, val); 5239 ambiguous = true; 5240 } 5241 if (g_list_find_custom(minus_features, name, compare_string)) { 5242 warn_report("Ambiguous CPU model string. " 5243 "Don't mix both \"-%s\" and \"%s=%s\"", 5244 name, name, val); 5245 ambiguous = true; 5246 } 5247 5248 /* Special case: */ 5249 if (!strcmp(name, "tsc-freq")) { 5250 int ret; 5251 uint64_t tsc_freq; 5252 5253 ret = qemu_strtosz_metric(val, NULL, &tsc_freq); 5254 if (ret < 0 || tsc_freq > INT64_MAX) { 5255 error_setg(errp, "bad numerical value %s", val); 5256 return; 5257 } 5258 snprintf(num, sizeof(num), "%" PRId64, tsc_freq); 5259 val = num; 5260 name = "tsc-frequency"; 5261 } 5262 5263 prop = g_new0(typeof(*prop), 1); 5264 prop->driver = typename; 5265 prop->property = g_strdup(name); 5266 prop->value = g_strdup(val); 5267 qdev_prop_register_global(prop); 5268 } 5269 5270 if (ambiguous) { 5271 warn_report("Compatibility of ambiguous CPU model " 5272 "strings won't be kept on future QEMU versions"); 5273 } 5274 } 5275 5276 static void x86_cpu_filter_features(X86CPU *cpu, bool verbose); 5277 5278 /* Build a list with the name of all features on a feature word array */ 5279 static void x86_cpu_list_feature_names(FeatureWordArray features, 5280 strList **list) 5281 { 5282 strList **tail = list; 5283 FeatureWord w; 5284 5285 for (w = 0; w < FEATURE_WORDS; w++) { 5286 uint64_t filtered = features[w]; 5287 int i; 5288 for (i = 0; i < 64; i++) { 5289 if (filtered & (1ULL << i)) { 5290 QAPI_LIST_APPEND(tail, g_strdup(x86_cpu_feature_name(w, i))); 5291 } 5292 } 5293 } 5294 } 5295 5296 static void x86_cpu_get_unavailable_features(Object *obj, Visitor *v, 5297 const char *name, void *opaque, 5298 Error **errp) 5299 { 5300 X86CPU *xc = X86_CPU(obj); 5301 strList *result = NULL; 5302 5303 x86_cpu_list_feature_names(xc->filtered_features, &result); 5304 visit_type_strList(v, "unavailable-features", &result, errp); 5305 } 5306 5307 /* Print all cpuid feature names in featureset 5308 */ 5309 static void listflags(GList *features) 5310 { 5311 size_t len = 0; 5312 GList *tmp; 5313 5314 for (tmp = features; tmp; tmp = tmp->next) { 5315 const char *name = tmp->data; 5316 if ((len + strlen(name) + 1) >= 75) { 5317 qemu_printf("\n"); 5318 len = 0; 5319 } 5320 qemu_printf("%s%s", len == 0 ? " " : " ", name); 5321 len += strlen(name) + 1; 5322 } 5323 qemu_printf("\n"); 5324 } 5325 5326 /* Sort alphabetically by type name, respecting X86CPUClass::ordering. */ 5327 static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b) 5328 { 5329 ObjectClass *class_a = (ObjectClass *)a; 5330 ObjectClass *class_b = (ObjectClass *)b; 5331 X86CPUClass *cc_a = X86_CPU_CLASS(class_a); 5332 X86CPUClass *cc_b = X86_CPU_CLASS(class_b); 5333 int ret; 5334 5335 if (cc_a->ordering != cc_b->ordering) { 5336 ret = cc_a->ordering - cc_b->ordering; 5337 } else { 5338 g_autofree char *name_a = x86_cpu_class_get_model_name(cc_a); 5339 g_autofree char *name_b = x86_cpu_class_get_model_name(cc_b); 5340 ret = strcmp(name_a, name_b); 5341 } 5342 return ret; 5343 } 5344 5345 static GSList *get_sorted_cpu_model_list(void) 5346 { 5347 GSList *list = object_class_get_list(TYPE_X86_CPU, false); 5348 list = g_slist_sort(list, x86_cpu_list_compare); 5349 return list; 5350 } 5351 5352 static char *x86_cpu_class_get_model_id(X86CPUClass *xc) 5353 { 5354 Object *obj = object_new_with_class(OBJECT_CLASS(xc)); 5355 char *r = object_property_get_str(obj, "model-id", &error_abort); 5356 object_unref(obj); 5357 return r; 5358 } 5359 5360 static char *x86_cpu_class_get_alias_of(X86CPUClass *cc) 5361 { 5362 X86CPUVersion version; 5363 5364 if (!cc->model || !cc->model->is_alias) { 5365 return NULL; 5366 } 5367 version = x86_cpu_model_resolve_version(cc->model); 5368 if (version <= 0) { 5369 return NULL; 5370 } 5371 return x86_cpu_versioned_model_name(cc->model->cpudef, version); 5372 } 5373 5374 static void x86_cpu_list_entry(gpointer data, gpointer user_data) 5375 { 5376 ObjectClass *oc = data; 5377 X86CPUClass *cc = X86_CPU_CLASS(oc); 5378 g_autofree char *name = x86_cpu_class_get_model_name(cc); 5379 g_autofree char *desc = g_strdup(cc->model_description); 5380 g_autofree char *alias_of = x86_cpu_class_get_alias_of(cc); 5381 g_autofree char *model_id = x86_cpu_class_get_model_id(cc); 5382 5383 if (!desc && alias_of) { 5384 if (cc->model && cc->model->version == CPU_VERSION_AUTO) { 5385 desc = g_strdup("(alias configured by machine type)"); 5386 } else { 5387 desc = g_strdup_printf("(alias of %s)", alias_of); 5388 } 5389 } 5390 if (!desc && cc->model && cc->model->note) { 5391 desc = g_strdup_printf("%s [%s]", model_id, cc->model->note); 5392 } 5393 if (!desc) { 5394 desc = g_strdup_printf("%s", model_id); 5395 } 5396 5397 if (cc->model && cc->model->cpudef->deprecation_note) { 5398 g_autofree char *olddesc = desc; 5399 desc = g_strdup_printf("%s (deprecated)", olddesc); 5400 } 5401 5402 qemu_printf("x86 %-20s %s\n", name, desc); 5403 } 5404 5405 /* list available CPU models and flags */ 5406 void x86_cpu_list(void) 5407 { 5408 int i, j; 5409 GSList *list; 5410 GList *names = NULL; 5411 5412 qemu_printf("Available CPUs:\n"); 5413 list = get_sorted_cpu_model_list(); 5414 g_slist_foreach(list, x86_cpu_list_entry, NULL); 5415 g_slist_free(list); 5416 5417 names = NULL; 5418 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) { 5419 FeatureWordInfo *fw = &feature_word_info[i]; 5420 for (j = 0; j < 64; j++) { 5421 if (fw->feat_names[j]) { 5422 names = g_list_append(names, (gpointer)fw->feat_names[j]); 5423 } 5424 } 5425 } 5426 5427 names = g_list_sort(names, (GCompareFunc)strcmp); 5428 5429 qemu_printf("\nRecognized CPUID flags:\n"); 5430 listflags(names); 5431 qemu_printf("\n"); 5432 g_list_free(names); 5433 } 5434 5435 #ifndef CONFIG_USER_ONLY 5436 5437 /* Check for missing features that may prevent the CPU class from 5438 * running using the current machine and accelerator. 5439 */ 5440 static void x86_cpu_class_check_missing_features(X86CPUClass *xcc, 5441 strList **list) 5442 { 5443 strList **tail = list; 5444 X86CPU *xc; 5445 Error *err = NULL; 5446 5447 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) { 5448 QAPI_LIST_APPEND(tail, g_strdup("kvm")); 5449 return; 5450 } 5451 5452 xc = X86_CPU(object_new_with_class(OBJECT_CLASS(xcc))); 5453 5454 x86_cpu_expand_features(xc, &err); 5455 if (err) { 5456 /* Errors at x86_cpu_expand_features should never happen, 5457 * but in case it does, just report the model as not 5458 * runnable at all using the "type" property. 5459 */ 5460 QAPI_LIST_APPEND(tail, g_strdup("type")); 5461 error_free(err); 5462 } 5463 5464 x86_cpu_filter_features(xc, false); 5465 5466 x86_cpu_list_feature_names(xc->filtered_features, tail); 5467 5468 object_unref(OBJECT(xc)); 5469 } 5470 5471 static void x86_cpu_definition_entry(gpointer data, gpointer user_data) 5472 { 5473 ObjectClass *oc = data; 5474 X86CPUClass *cc = X86_CPU_CLASS(oc); 5475 CpuDefinitionInfoList **cpu_list = user_data; 5476 CpuDefinitionInfo *info; 5477 5478 info = g_malloc0(sizeof(*info)); 5479 info->name = x86_cpu_class_get_model_name(cc); 5480 x86_cpu_class_check_missing_features(cc, &info->unavailable_features); 5481 info->has_unavailable_features = true; 5482 info->q_typename = g_strdup(object_class_get_name(oc)); 5483 info->migration_safe = cc->migration_safe; 5484 info->has_migration_safe = true; 5485 info->q_static = cc->static_model; 5486 if (cc->model && cc->model->cpudef->deprecation_note) { 5487 info->deprecated = true; 5488 } else { 5489 info->deprecated = false; 5490 } 5491 /* 5492 * Old machine types won't report aliases, so that alias translation 5493 * doesn't break compatibility with previous QEMU versions. 5494 */ 5495 if (default_cpu_version != CPU_VERSION_LEGACY) { 5496 info->alias_of = x86_cpu_class_get_alias_of(cc); 5497 } 5498 5499 QAPI_LIST_PREPEND(*cpu_list, info); 5500 } 5501 5502 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) 5503 { 5504 CpuDefinitionInfoList *cpu_list = NULL; 5505 GSList *list = get_sorted_cpu_model_list(); 5506 g_slist_foreach(list, x86_cpu_definition_entry, &cpu_list); 5507 g_slist_free(list); 5508 return cpu_list; 5509 } 5510 5511 #endif /* !CONFIG_USER_ONLY */ 5512 5513 uint64_t x86_cpu_get_supported_feature_word(FeatureWord w, 5514 bool migratable_only) 5515 { 5516 FeatureWordInfo *wi = &feature_word_info[w]; 5517 uint64_t r = 0; 5518 5519 if (kvm_enabled()) { 5520 switch (wi->type) { 5521 case CPUID_FEATURE_WORD: 5522 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid.eax, 5523 wi->cpuid.ecx, 5524 wi->cpuid.reg); 5525 break; 5526 case MSR_FEATURE_WORD: 5527 r = kvm_arch_get_supported_msr_feature(kvm_state, 5528 wi->msr.index); 5529 break; 5530 } 5531 } else if (hvf_enabled()) { 5532 if (wi->type != CPUID_FEATURE_WORD) { 5533 return 0; 5534 } 5535 r = hvf_get_supported_cpuid(wi->cpuid.eax, 5536 wi->cpuid.ecx, 5537 wi->cpuid.reg); 5538 } else if (tcg_enabled()) { 5539 r = wi->tcg_features; 5540 } else { 5541 return ~0; 5542 } 5543 #ifndef TARGET_X86_64 5544 if (w == FEAT_8000_0001_EDX) { 5545 /* 5546 * 32-bit TCG can emulate 64-bit compatibility mode. If there is no 5547 * way for userspace to get out of its 32-bit jail, we can leave 5548 * the LM bit set. 5549 */ 5550 uint32_t unavail = tcg_enabled() 5551 ? CPUID_EXT2_LM & ~CPUID_EXT2_KERNEL_FEATURES 5552 : CPUID_EXT2_LM; 5553 r &= ~unavail; 5554 } 5555 #endif 5556 if (migratable_only) { 5557 r &= x86_cpu_get_migratable_flags(w); 5558 } 5559 return r; 5560 } 5561 5562 static void x86_cpu_get_supported_cpuid(uint32_t func, uint32_t index, 5563 uint32_t *eax, uint32_t *ebx, 5564 uint32_t *ecx, uint32_t *edx) 5565 { 5566 if (kvm_enabled()) { 5567 *eax = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EAX); 5568 *ebx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EBX); 5569 *ecx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_ECX); 5570 *edx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EDX); 5571 } else if (hvf_enabled()) { 5572 *eax = hvf_get_supported_cpuid(func, index, R_EAX); 5573 *ebx = hvf_get_supported_cpuid(func, index, R_EBX); 5574 *ecx = hvf_get_supported_cpuid(func, index, R_ECX); 5575 *edx = hvf_get_supported_cpuid(func, index, R_EDX); 5576 } else { 5577 *eax = 0; 5578 *ebx = 0; 5579 *ecx = 0; 5580 *edx = 0; 5581 } 5582 } 5583 5584 static void x86_cpu_get_cache_cpuid(uint32_t func, uint32_t index, 5585 uint32_t *eax, uint32_t *ebx, 5586 uint32_t *ecx, uint32_t *edx) 5587 { 5588 uint32_t level, unused; 5589 5590 /* Only return valid host leaves. */ 5591 switch (func) { 5592 case 2: 5593 case 4: 5594 host_cpuid(0, 0, &level, &unused, &unused, &unused); 5595 break; 5596 case 0x80000005: 5597 case 0x80000006: 5598 case 0x8000001d: 5599 host_cpuid(0x80000000, 0, &level, &unused, &unused, &unused); 5600 break; 5601 default: 5602 return; 5603 } 5604 5605 if (func > level) { 5606 *eax = 0; 5607 *ebx = 0; 5608 *ecx = 0; 5609 *edx = 0; 5610 } else { 5611 host_cpuid(func, index, eax, ebx, ecx, edx); 5612 } 5613 } 5614 5615 /* 5616 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 5617 */ 5618 void x86_cpu_apply_props(X86CPU *cpu, PropValue *props) 5619 { 5620 PropValue *pv; 5621 for (pv = props; pv->prop; pv++) { 5622 if (!pv->value) { 5623 continue; 5624 } 5625 object_property_parse(OBJECT(cpu), pv->prop, pv->value, 5626 &error_abort); 5627 } 5628 } 5629 5630 /* 5631 * Apply properties for the CPU model version specified in model. 5632 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 5633 */ 5634 5635 static void x86_cpu_apply_version_props(X86CPU *cpu, X86CPUModel *model) 5636 { 5637 const X86CPUVersionDefinition *vdef; 5638 X86CPUVersion version = x86_cpu_model_resolve_version(model); 5639 5640 if (version == CPU_VERSION_LEGACY) { 5641 return; 5642 } 5643 5644 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) { 5645 PropValue *p; 5646 5647 for (p = vdef->props; p && p->prop; p++) { 5648 object_property_parse(OBJECT(cpu), p->prop, p->value, 5649 &error_abort); 5650 } 5651 5652 if (vdef->version == version) { 5653 break; 5654 } 5655 } 5656 5657 /* 5658 * If we reached the end of the list, version number was invalid 5659 */ 5660 assert(vdef->version == version); 5661 } 5662 5663 static const CPUCaches *x86_cpu_get_versioned_cache_info(X86CPU *cpu, 5664 X86CPUModel *model) 5665 { 5666 const X86CPUVersionDefinition *vdef; 5667 X86CPUVersion version = x86_cpu_model_resolve_version(model); 5668 const CPUCaches *cache_info = model->cpudef->cache_info; 5669 5670 if (version == CPU_VERSION_LEGACY) { 5671 return cache_info; 5672 } 5673 5674 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) { 5675 if (vdef->cache_info) { 5676 cache_info = vdef->cache_info; 5677 } 5678 5679 if (vdef->version == version) { 5680 break; 5681 } 5682 } 5683 5684 assert(vdef->version == version); 5685 return cache_info; 5686 } 5687 5688 /* 5689 * Load data from X86CPUDefinition into a X86CPU object. 5690 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 5691 */ 5692 static void x86_cpu_load_model(X86CPU *cpu, X86CPUModel *model) 5693 { 5694 const X86CPUDefinition *def = model->cpudef; 5695 CPUX86State *env = &cpu->env; 5696 FeatureWord w; 5697 5698 /*NOTE: any property set by this function should be returned by 5699 * x86_cpu_static_props(), so static expansion of 5700 * query-cpu-model-expansion is always complete. 5701 */ 5702 5703 /* CPU models only set _minimum_ values for level/xlevel: */ 5704 object_property_set_uint(OBJECT(cpu), "min-level", def->level, 5705 &error_abort); 5706 object_property_set_uint(OBJECT(cpu), "min-xlevel", def->xlevel, 5707 &error_abort); 5708 5709 object_property_set_int(OBJECT(cpu), "family", def->family, &error_abort); 5710 object_property_set_int(OBJECT(cpu), "model", def->model, &error_abort); 5711 object_property_set_int(OBJECT(cpu), "stepping", def->stepping, 5712 &error_abort); 5713 object_property_set_str(OBJECT(cpu), "model-id", def->model_id, 5714 &error_abort); 5715 for (w = 0; w < FEATURE_WORDS; w++) { 5716 env->features[w] = def->features[w]; 5717 } 5718 5719 /* legacy-cache defaults to 'off' if CPU model provides cache info */ 5720 cpu->legacy_cache = !x86_cpu_get_versioned_cache_info(cpu, model); 5721 5722 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR; 5723 5724 /* sysenter isn't supported in compatibility mode on AMD, 5725 * syscall isn't supported in compatibility mode on Intel. 5726 * Normally we advertise the actual CPU vendor, but you can 5727 * override this using the 'vendor' property if you want to use 5728 * KVM's sysenter/syscall emulation in compatibility mode and 5729 * when doing cross vendor migration 5730 */ 5731 5732 /* 5733 * vendor property is set here but then overloaded with the 5734 * host cpu vendor for KVM and HVF. 5735 */ 5736 object_property_set_str(OBJECT(cpu), "vendor", def->vendor, &error_abort); 5737 5738 x86_cpu_apply_version_props(cpu, model); 5739 5740 /* 5741 * Properties in versioned CPU model are not user specified features. 5742 * We can simply clear env->user_features here since it will be filled later 5743 * in x86_cpu_expand_features() based on plus_features and minus_features. 5744 */ 5745 memset(&env->user_features, 0, sizeof(env->user_features)); 5746 } 5747 5748 static gchar *x86_gdb_arch_name(CPUState *cs) 5749 { 5750 #ifdef TARGET_X86_64 5751 return g_strdup("i386:x86-64"); 5752 #else 5753 return g_strdup("i386"); 5754 #endif 5755 } 5756 5757 static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data) 5758 { 5759 X86CPUModel *model = data; 5760 X86CPUClass *xcc = X86_CPU_CLASS(oc); 5761 CPUClass *cc = CPU_CLASS(oc); 5762 5763 xcc->model = model; 5764 xcc->migration_safe = true; 5765 cc->deprecation_note = model->cpudef->deprecation_note; 5766 } 5767 5768 static void x86_register_cpu_model_type(const char *name, X86CPUModel *model) 5769 { 5770 g_autofree char *typename = x86_cpu_type_name(name); 5771 TypeInfo ti = { 5772 .name = typename, 5773 .parent = TYPE_X86_CPU, 5774 .class_init = x86_cpu_cpudef_class_init, 5775 .class_data = model, 5776 }; 5777 5778 type_register(&ti); 5779 } 5780 5781 5782 /* 5783 * register builtin_x86_defs; 5784 * "max", "base" and subclasses ("host") are not registered here. 5785 * See x86_cpu_register_types for all model registrations. 5786 */ 5787 static void x86_register_cpudef_types(const X86CPUDefinition *def) 5788 { 5789 X86CPUModel *m; 5790 const X86CPUVersionDefinition *vdef; 5791 5792 /* AMD aliases are handled at runtime based on CPUID vendor, so 5793 * they shouldn't be set on the CPU model table. 5794 */ 5795 assert(!(def->features[FEAT_8000_0001_EDX] & CPUID_EXT2_AMD_ALIASES)); 5796 /* catch mistakes instead of silently truncating model_id when too long */ 5797 assert(def->model_id && strlen(def->model_id) <= 48); 5798 5799 /* Unversioned model: */ 5800 m = g_new0(X86CPUModel, 1); 5801 m->cpudef = def; 5802 m->version = CPU_VERSION_AUTO; 5803 m->is_alias = true; 5804 x86_register_cpu_model_type(def->name, m); 5805 5806 /* Versioned models: */ 5807 5808 for (vdef = x86_cpu_def_get_versions(def); vdef->version; vdef++) { 5809 X86CPUModel *m = g_new0(X86CPUModel, 1); 5810 g_autofree char *name = 5811 x86_cpu_versioned_model_name(def, vdef->version); 5812 m->cpudef = def; 5813 m->version = vdef->version; 5814 m->note = vdef->note; 5815 x86_register_cpu_model_type(name, m); 5816 5817 if (vdef->alias) { 5818 X86CPUModel *am = g_new0(X86CPUModel, 1); 5819 am->cpudef = def; 5820 am->version = vdef->version; 5821 am->is_alias = true; 5822 x86_register_cpu_model_type(vdef->alias, am); 5823 } 5824 } 5825 5826 } 5827 5828 uint32_t cpu_x86_virtual_addr_width(CPUX86State *env) 5829 { 5830 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57) { 5831 return 57; /* 57 bits virtual */ 5832 } else { 5833 return 48; /* 48 bits virtual */ 5834 } 5835 } 5836 5837 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, 5838 uint32_t *eax, uint32_t *ebx, 5839 uint32_t *ecx, uint32_t *edx) 5840 { 5841 X86CPU *cpu = env_archcpu(env); 5842 CPUState *cs = env_cpu(env); 5843 uint32_t die_offset; 5844 uint32_t limit; 5845 uint32_t signature[3]; 5846 X86CPUTopoInfo topo_info; 5847 5848 topo_info.dies_per_pkg = env->nr_dies; 5849 topo_info.cores_per_die = cs->nr_cores; 5850 topo_info.threads_per_core = cs->nr_threads; 5851 5852 /* Calculate & apply limits for different index ranges */ 5853 if (index >= 0xC0000000) { 5854 limit = env->cpuid_xlevel2; 5855 } else if (index >= 0x80000000) { 5856 limit = env->cpuid_xlevel; 5857 } else if (index >= 0x40000000) { 5858 limit = 0x40000001; 5859 } else { 5860 limit = env->cpuid_level; 5861 } 5862 5863 if (index > limit) { 5864 /* Intel documentation states that invalid EAX input will 5865 * return the same information as EAX=cpuid_level 5866 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID) 5867 */ 5868 index = env->cpuid_level; 5869 } 5870 5871 switch(index) { 5872 case 0: 5873 *eax = env->cpuid_level; 5874 *ebx = env->cpuid_vendor1; 5875 *edx = env->cpuid_vendor2; 5876 *ecx = env->cpuid_vendor3; 5877 break; 5878 case 1: 5879 *eax = env->cpuid_version; 5880 *ebx = (cpu->apic_id << 24) | 5881 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */ 5882 *ecx = env->features[FEAT_1_ECX]; 5883 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) { 5884 *ecx |= CPUID_EXT_OSXSAVE; 5885 } 5886 *edx = env->features[FEAT_1_EDX]; 5887 if (cs->nr_cores * cs->nr_threads > 1) { 5888 *ebx |= (cs->nr_cores * cs->nr_threads) << 16; 5889 *edx |= CPUID_HT; 5890 } 5891 if (!cpu->enable_pmu) { 5892 *ecx &= ~CPUID_EXT_PDCM; 5893 } 5894 break; 5895 case 2: 5896 /* cache info: needed for Pentium Pro compatibility */ 5897 if (cpu->cache_info_passthrough) { 5898 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 5899 break; 5900 } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { 5901 *eax = *ebx = *ecx = *edx = 0; 5902 break; 5903 } 5904 *eax = 1; /* Number of CPUID[EAX=2] calls required */ 5905 *ebx = 0; 5906 if (!cpu->enable_l3_cache) { 5907 *ecx = 0; 5908 } else { 5909 *ecx = cpuid2_cache_descriptor(env->cache_info_cpuid2.l3_cache); 5910 } 5911 *edx = (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1d_cache) << 16) | 5912 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1i_cache) << 8) | 5913 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l2_cache)); 5914 break; 5915 case 4: 5916 /* cache info: needed for Core compatibility */ 5917 if (cpu->cache_info_passthrough) { 5918 x86_cpu_get_cache_cpuid(index, count, eax, ebx, ecx, edx); 5919 /* 5920 * QEMU has its own number of cores/logical cpus, 5921 * set 24..14, 31..26 bit to configured values 5922 */ 5923 if (*eax & 31) { 5924 int host_vcpus_per_cache = 1 + ((*eax & 0x3FFC000) >> 14); 5925 int vcpus_per_socket = env->nr_dies * cs->nr_cores * 5926 cs->nr_threads; 5927 if (cs->nr_cores > 1) { 5928 *eax &= ~0xFC000000; 5929 *eax |= (pow2ceil(cs->nr_cores) - 1) << 26; 5930 } 5931 if (host_vcpus_per_cache > vcpus_per_socket) { 5932 *eax &= ~0x3FFC000; 5933 *eax |= (pow2ceil(vcpus_per_socket) - 1) << 14; 5934 } 5935 } 5936 } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { 5937 *eax = *ebx = *ecx = *edx = 0; 5938 } else { 5939 *eax = 0; 5940 switch (count) { 5941 case 0: /* L1 dcache info */ 5942 encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache, 5943 1, cs->nr_cores, 5944 eax, ebx, ecx, edx); 5945 break; 5946 case 1: /* L1 icache info */ 5947 encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache, 5948 1, cs->nr_cores, 5949 eax, ebx, ecx, edx); 5950 break; 5951 case 2: /* L2 cache info */ 5952 encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache, 5953 cs->nr_threads, cs->nr_cores, 5954 eax, ebx, ecx, edx); 5955 break; 5956 case 3: /* L3 cache info */ 5957 die_offset = apicid_die_offset(&topo_info); 5958 if (cpu->enable_l3_cache) { 5959 encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache, 5960 (1 << die_offset), cs->nr_cores, 5961 eax, ebx, ecx, edx); 5962 break; 5963 } 5964 /* fall through */ 5965 default: /* end of info */ 5966 *eax = *ebx = *ecx = *edx = 0; 5967 break; 5968 } 5969 } 5970 break; 5971 case 5: 5972 /* MONITOR/MWAIT Leaf */ 5973 *eax = cpu->mwait.eax; /* Smallest monitor-line size in bytes */ 5974 *ebx = cpu->mwait.ebx; /* Largest monitor-line size in bytes */ 5975 *ecx = cpu->mwait.ecx; /* flags */ 5976 *edx = cpu->mwait.edx; /* mwait substates */ 5977 break; 5978 case 6: 5979 /* Thermal and Power Leaf */ 5980 *eax = env->features[FEAT_6_EAX]; 5981 *ebx = 0; 5982 *ecx = 0; 5983 *edx = 0; 5984 break; 5985 case 7: 5986 /* Structured Extended Feature Flags Enumeration Leaf */ 5987 if (count == 0) { 5988 /* Maximum ECX value for sub-leaves */ 5989 *eax = env->cpuid_level_func7; 5990 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */ 5991 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */ 5992 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) { 5993 *ecx |= CPUID_7_0_ECX_OSPKE; 5994 } 5995 *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */ 5996 5997 /* 5998 * SGX cannot be emulated in software. If hardware does not 5999 * support enabling SGX and/or SGX flexible launch control, 6000 * then we need to update the VM's CPUID values accordingly. 6001 */ 6002 if ((*ebx & CPUID_7_0_EBX_SGX) && 6003 (!kvm_enabled() || 6004 !(kvm_arch_get_supported_cpuid(cs->kvm_state, 0x7, 0, R_EBX) & 6005 CPUID_7_0_EBX_SGX))) { 6006 *ebx &= ~CPUID_7_0_EBX_SGX; 6007 } 6008 6009 if ((*ecx & CPUID_7_0_ECX_SGX_LC) && 6010 (!(*ebx & CPUID_7_0_EBX_SGX) || !kvm_enabled() || 6011 !(kvm_arch_get_supported_cpuid(cs->kvm_state, 0x7, 0, R_ECX) & 6012 CPUID_7_0_ECX_SGX_LC))) { 6013 *ecx &= ~CPUID_7_0_ECX_SGX_LC; 6014 } 6015 } else if (count == 1) { 6016 *eax = env->features[FEAT_7_1_EAX]; 6017 *edx = env->features[FEAT_7_1_EDX]; 6018 *ebx = 0; 6019 *ecx = 0; 6020 } else { 6021 *eax = 0; 6022 *ebx = 0; 6023 *ecx = 0; 6024 *edx = 0; 6025 } 6026 break; 6027 case 9: 6028 /* Direct Cache Access Information Leaf */ 6029 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */ 6030 *ebx = 0; 6031 *ecx = 0; 6032 *edx = 0; 6033 break; 6034 case 0xA: 6035 /* Architectural Performance Monitoring Leaf */ 6036 if (accel_uses_host_cpuid() && cpu->enable_pmu) { 6037 x86_cpu_get_supported_cpuid(0xA, count, eax, ebx, ecx, edx); 6038 } else { 6039 *eax = 0; 6040 *ebx = 0; 6041 *ecx = 0; 6042 *edx = 0; 6043 } 6044 break; 6045 case 0xB: 6046 /* Extended Topology Enumeration Leaf */ 6047 if (!cpu->enable_cpuid_0xb) { 6048 *eax = *ebx = *ecx = *edx = 0; 6049 break; 6050 } 6051 6052 *ecx = count & 0xff; 6053 *edx = cpu->apic_id; 6054 6055 switch (count) { 6056 case 0: 6057 *eax = apicid_core_offset(&topo_info); 6058 *ebx = cs->nr_threads; 6059 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT; 6060 break; 6061 case 1: 6062 *eax = apicid_pkg_offset(&topo_info); 6063 *ebx = cs->nr_cores * cs->nr_threads; 6064 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE; 6065 break; 6066 default: 6067 *eax = 0; 6068 *ebx = 0; 6069 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID; 6070 } 6071 6072 assert(!(*eax & ~0x1f)); 6073 *ebx &= 0xffff; /* The count doesn't need to be reliable. */ 6074 break; 6075 case 0x1C: 6076 if (accel_uses_host_cpuid() && cpu->enable_pmu && 6077 (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) { 6078 x86_cpu_get_supported_cpuid(0x1C, 0, eax, ebx, ecx, edx); 6079 *edx = 0; 6080 } 6081 break; 6082 case 0x1F: 6083 /* V2 Extended Topology Enumeration Leaf */ 6084 if (env->nr_dies < 2) { 6085 *eax = *ebx = *ecx = *edx = 0; 6086 break; 6087 } 6088 6089 *ecx = count & 0xff; 6090 *edx = cpu->apic_id; 6091 switch (count) { 6092 case 0: 6093 *eax = apicid_core_offset(&topo_info); 6094 *ebx = cs->nr_threads; 6095 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT; 6096 break; 6097 case 1: 6098 *eax = apicid_die_offset(&topo_info); 6099 *ebx = cs->nr_cores * cs->nr_threads; 6100 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE; 6101 break; 6102 case 2: 6103 *eax = apicid_pkg_offset(&topo_info); 6104 *ebx = env->nr_dies * cs->nr_cores * cs->nr_threads; 6105 *ecx |= CPUID_TOPOLOGY_LEVEL_DIE; 6106 break; 6107 default: 6108 *eax = 0; 6109 *ebx = 0; 6110 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID; 6111 } 6112 assert(!(*eax & ~0x1f)); 6113 *ebx &= 0xffff; /* The count doesn't need to be reliable. */ 6114 break; 6115 case 0xD: { 6116 /* Processor Extended State */ 6117 *eax = 0; 6118 *ebx = 0; 6119 *ecx = 0; 6120 *edx = 0; 6121 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { 6122 break; 6123 } 6124 6125 if (count == 0) { 6126 *ecx = xsave_area_size(x86_cpu_xsave_xcr0_components(cpu), false); 6127 *eax = env->features[FEAT_XSAVE_XCR0_LO]; 6128 *edx = env->features[FEAT_XSAVE_XCR0_HI]; 6129 /* 6130 * The initial value of xcr0 and ebx == 0, On host without kvm 6131 * commit 412a3c41(e.g., CentOS 6), the ebx's value always == 0 6132 * even through guest update xcr0, this will crash some legacy guest 6133 * (e.g., CentOS 6), So set ebx == ecx to workaroud it. 6134 */ 6135 *ebx = kvm_enabled() ? *ecx : xsave_area_size(env->xcr0, false); 6136 } else if (count == 1) { 6137 uint64_t xstate = x86_cpu_xsave_xcr0_components(cpu) | 6138 x86_cpu_xsave_xss_components(cpu); 6139 6140 *eax = env->features[FEAT_XSAVE]; 6141 *ebx = xsave_area_size(xstate, true); 6142 *ecx = env->features[FEAT_XSAVE_XSS_LO]; 6143 *edx = env->features[FEAT_XSAVE_XSS_HI]; 6144 if (kvm_enabled() && cpu->enable_pmu && 6145 (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR) && 6146 (*eax & CPUID_XSAVE_XSAVES)) { 6147 *ecx |= XSTATE_ARCH_LBR_MASK; 6148 } else { 6149 *ecx &= ~XSTATE_ARCH_LBR_MASK; 6150 } 6151 } else if (count == 0xf && 6152 accel_uses_host_cpuid() && cpu->enable_pmu && 6153 (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) { 6154 x86_cpu_get_supported_cpuid(0xD, count, eax, ebx, ecx, edx); 6155 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) { 6156 const ExtSaveArea *esa = &x86_ext_save_areas[count]; 6157 6158 if (x86_cpu_xsave_xcr0_components(cpu) & (1ULL << count)) { 6159 *eax = esa->size; 6160 *ebx = esa->offset; 6161 *ecx = esa->ecx & 6162 (ESA_FEATURE_ALIGN64_MASK | ESA_FEATURE_XFD_MASK); 6163 } else if (x86_cpu_xsave_xss_components(cpu) & (1ULL << count)) { 6164 *eax = esa->size; 6165 *ebx = 0; 6166 *ecx = 1; 6167 } 6168 } 6169 break; 6170 } 6171 case 0x12: 6172 #ifndef CONFIG_USER_ONLY 6173 if (!kvm_enabled() || 6174 !(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX)) { 6175 *eax = *ebx = *ecx = *edx = 0; 6176 break; 6177 } 6178 6179 /* 6180 * SGX sub-leafs CPUID.0x12.{0x2..N} enumerate EPC sections. Retrieve 6181 * the EPC properties, e.g. confidentiality and integrity, from the 6182 * host's first EPC section, i.e. assume there is one EPC section or 6183 * that all EPC sections have the same security properties. 6184 */ 6185 if (count > 1) { 6186 uint64_t epc_addr, epc_size; 6187 6188 if (sgx_epc_get_section(count - 2, &epc_addr, &epc_size)) { 6189 *eax = *ebx = *ecx = *edx = 0; 6190 break; 6191 } 6192 host_cpuid(index, 2, eax, ebx, ecx, edx); 6193 *eax = (uint32_t)(epc_addr & 0xfffff000) | 0x1; 6194 *ebx = (uint32_t)(epc_addr >> 32); 6195 *ecx = (uint32_t)(epc_size & 0xfffff000) | (*ecx & 0xf); 6196 *edx = (uint32_t)(epc_size >> 32); 6197 break; 6198 } 6199 6200 /* 6201 * SGX sub-leafs CPUID.0x12.{0x0,0x1} are heavily dependent on hardware 6202 * and KVM, i.e. QEMU cannot emulate features to override what KVM 6203 * supports. Features can be further restricted by userspace, but not 6204 * made more permissive. 6205 */ 6206 x86_cpu_get_supported_cpuid(0x12, count, eax, ebx, ecx, edx); 6207 6208 if (count == 0) { 6209 *eax &= env->features[FEAT_SGX_12_0_EAX]; 6210 *ebx &= env->features[FEAT_SGX_12_0_EBX]; 6211 } else { 6212 *eax &= env->features[FEAT_SGX_12_1_EAX]; 6213 *ebx &= 0; /* ebx reserve */ 6214 *ecx &= env->features[FEAT_XSAVE_XCR0_LO]; 6215 *edx &= env->features[FEAT_XSAVE_XCR0_HI]; 6216 6217 /* FP and SSE are always allowed regardless of XSAVE/XCR0. */ 6218 *ecx |= XSTATE_FP_MASK | XSTATE_SSE_MASK; 6219 6220 /* Access to PROVISIONKEY requires additional credentials. */ 6221 if ((*eax & (1U << 4)) && 6222 !kvm_enable_sgx_provisioning(cs->kvm_state)) { 6223 *eax &= ~(1U << 4); 6224 } 6225 } 6226 #endif 6227 break; 6228 case 0x14: { 6229 /* Intel Processor Trace Enumeration */ 6230 *eax = 0; 6231 *ebx = 0; 6232 *ecx = 0; 6233 *edx = 0; 6234 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) || 6235 !kvm_enabled()) { 6236 break; 6237 } 6238 6239 if (count == 0) { 6240 *eax = INTEL_PT_MAX_SUBLEAF; 6241 *ebx = INTEL_PT_MINIMAL_EBX; 6242 *ecx = INTEL_PT_MINIMAL_ECX; 6243 if (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP) { 6244 *ecx |= CPUID_14_0_ECX_LIP; 6245 } 6246 } else if (count == 1) { 6247 *eax = INTEL_PT_MTC_BITMAP | INTEL_PT_ADDR_RANGES_NUM; 6248 *ebx = INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP; 6249 } 6250 break; 6251 } 6252 case 0x1D: { 6253 /* AMX TILE, for now hardcoded for Sapphire Rapids*/ 6254 *eax = 0; 6255 *ebx = 0; 6256 *ecx = 0; 6257 *edx = 0; 6258 if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) { 6259 break; 6260 } 6261 6262 if (count == 0) { 6263 /* Highest numbered palette subleaf */ 6264 *eax = INTEL_AMX_TILE_MAX_SUBLEAF; 6265 } else if (count == 1) { 6266 *eax = INTEL_AMX_TOTAL_TILE_BYTES | 6267 (INTEL_AMX_BYTES_PER_TILE << 16); 6268 *ebx = INTEL_AMX_BYTES_PER_ROW | (INTEL_AMX_TILE_MAX_NAMES << 16); 6269 *ecx = INTEL_AMX_TILE_MAX_ROWS; 6270 } 6271 break; 6272 } 6273 case 0x1E: { 6274 /* AMX TMUL, for now hardcoded for Sapphire Rapids */ 6275 *eax = 0; 6276 *ebx = 0; 6277 *ecx = 0; 6278 *edx = 0; 6279 if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) { 6280 break; 6281 } 6282 6283 if (count == 0) { 6284 /* Highest numbered palette subleaf */ 6285 *ebx = INTEL_AMX_TMUL_MAX_K | (INTEL_AMX_TMUL_MAX_N << 8); 6286 } 6287 break; 6288 } 6289 case 0x40000000: 6290 /* 6291 * CPUID code in kvm_arch_init_vcpu() ignores stuff 6292 * set here, but we restrict to TCG none the less. 6293 */ 6294 if (tcg_enabled() && cpu->expose_tcg) { 6295 memcpy(signature, "TCGTCGTCGTCG", 12); 6296 *eax = 0x40000001; 6297 *ebx = signature[0]; 6298 *ecx = signature[1]; 6299 *edx = signature[2]; 6300 } else { 6301 *eax = 0; 6302 *ebx = 0; 6303 *ecx = 0; 6304 *edx = 0; 6305 } 6306 break; 6307 case 0x40000001: 6308 *eax = 0; 6309 *ebx = 0; 6310 *ecx = 0; 6311 *edx = 0; 6312 break; 6313 case 0x80000000: 6314 *eax = env->cpuid_xlevel; 6315 *ebx = env->cpuid_vendor1; 6316 *edx = env->cpuid_vendor2; 6317 *ecx = env->cpuid_vendor3; 6318 break; 6319 case 0x80000001: 6320 *eax = env->cpuid_version; 6321 *ebx = 0; 6322 *ecx = env->features[FEAT_8000_0001_ECX]; 6323 *edx = env->features[FEAT_8000_0001_EDX]; 6324 6325 /* The Linux kernel checks for the CMPLegacy bit and 6326 * discards multiple thread information if it is set. 6327 * So don't set it here for Intel to make Linux guests happy. 6328 */ 6329 if (cs->nr_cores * cs->nr_threads > 1) { 6330 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 || 6331 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 || 6332 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) { 6333 *ecx |= 1 << 1; /* CmpLegacy bit */ 6334 } 6335 } 6336 if (tcg_enabled() && env->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && 6337 !(env->hflags & HF_LMA_MASK)) { 6338 *edx &= ~CPUID_EXT2_SYSCALL; 6339 } 6340 break; 6341 case 0x80000002: 6342 case 0x80000003: 6343 case 0x80000004: 6344 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0]; 6345 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1]; 6346 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2]; 6347 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3]; 6348 break; 6349 case 0x80000005: 6350 /* cache info (L1 cache) */ 6351 if (cpu->cache_info_passthrough) { 6352 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 6353 break; 6354 } 6355 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | 6356 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES); 6357 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | 6358 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES); 6359 *ecx = encode_cache_cpuid80000005(env->cache_info_amd.l1d_cache); 6360 *edx = encode_cache_cpuid80000005(env->cache_info_amd.l1i_cache); 6361 break; 6362 case 0x80000006: 6363 /* cache info (L2 cache) */ 6364 if (cpu->cache_info_passthrough) { 6365 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 6366 break; 6367 } 6368 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | 6369 (L2_DTLB_2M_ENTRIES << 16) | 6370 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | 6371 (L2_ITLB_2M_ENTRIES); 6372 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | 6373 (L2_DTLB_4K_ENTRIES << 16) | 6374 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | 6375 (L2_ITLB_4K_ENTRIES); 6376 encode_cache_cpuid80000006(env->cache_info_amd.l2_cache, 6377 cpu->enable_l3_cache ? 6378 env->cache_info_amd.l3_cache : NULL, 6379 ecx, edx); 6380 break; 6381 case 0x80000007: 6382 *eax = 0; 6383 *ebx = 0; 6384 *ecx = 0; 6385 *edx = env->features[FEAT_8000_0007_EDX]; 6386 break; 6387 case 0x80000008: 6388 /* virtual & phys address size in low 2 bytes. */ 6389 *eax = cpu->phys_bits; 6390 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 6391 /* 64 bit processor */ 6392 *eax |= (cpu_x86_virtual_addr_width(env) << 8); 6393 } 6394 *ebx = env->features[FEAT_8000_0008_EBX]; 6395 if (cs->nr_cores * cs->nr_threads > 1) { 6396 /* 6397 * Bits 15:12 is "The number of bits in the initial 6398 * Core::X86::Apic::ApicId[ApicId] value that indicate 6399 * thread ID within a package". 6400 * Bits 7:0 is "The number of threads in the package is NC+1" 6401 */ 6402 *ecx = (apicid_pkg_offset(&topo_info) << 12) | 6403 ((cs->nr_cores * cs->nr_threads) - 1); 6404 } else { 6405 *ecx = 0; 6406 } 6407 *edx = 0; 6408 break; 6409 case 0x8000000A: 6410 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { 6411 *eax = 0x00000001; /* SVM Revision */ 6412 *ebx = 0x00000010; /* nr of ASIDs */ 6413 *ecx = 0; 6414 *edx = env->features[FEAT_SVM]; /* optional features */ 6415 } else { 6416 *eax = 0; 6417 *ebx = 0; 6418 *ecx = 0; 6419 *edx = 0; 6420 } 6421 break; 6422 case 0x8000001D: 6423 *eax = 0; 6424 if (cpu->cache_info_passthrough) { 6425 x86_cpu_get_cache_cpuid(index, count, eax, ebx, ecx, edx); 6426 break; 6427 } 6428 switch (count) { 6429 case 0: /* L1 dcache info */ 6430 encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache, 6431 &topo_info, eax, ebx, ecx, edx); 6432 break; 6433 case 1: /* L1 icache info */ 6434 encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache, 6435 &topo_info, eax, ebx, ecx, edx); 6436 break; 6437 case 2: /* L2 cache info */ 6438 encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache, 6439 &topo_info, eax, ebx, ecx, edx); 6440 break; 6441 case 3: /* L3 cache info */ 6442 encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache, 6443 &topo_info, eax, ebx, ecx, edx); 6444 break; 6445 default: /* end of info */ 6446 *eax = *ebx = *ecx = *edx = 0; 6447 break; 6448 } 6449 break; 6450 case 0x8000001E: 6451 if (cpu->core_id <= 255) { 6452 encode_topo_cpuid8000001e(cpu, &topo_info, eax, ebx, ecx, edx); 6453 } else { 6454 *eax = 0; 6455 *ebx = 0; 6456 *ecx = 0; 6457 *edx = 0; 6458 } 6459 break; 6460 case 0xC0000000: 6461 *eax = env->cpuid_xlevel2; 6462 *ebx = 0; 6463 *ecx = 0; 6464 *edx = 0; 6465 break; 6466 case 0xC0000001: 6467 /* Support for VIA CPU's CPUID instruction */ 6468 *eax = env->cpuid_version; 6469 *ebx = 0; 6470 *ecx = 0; 6471 *edx = env->features[FEAT_C000_0001_EDX]; 6472 break; 6473 case 0xC0000002: 6474 case 0xC0000003: 6475 case 0xC0000004: 6476 /* Reserved for the future, and now filled with zero */ 6477 *eax = 0; 6478 *ebx = 0; 6479 *ecx = 0; 6480 *edx = 0; 6481 break; 6482 case 0x8000001F: 6483 *eax = *ebx = *ecx = *edx = 0; 6484 if (sev_enabled()) { 6485 *eax = 0x2; 6486 *eax |= sev_es_enabled() ? 0x8 : 0; 6487 *ebx = sev_get_cbit_position() & 0x3f; /* EBX[5:0] */ 6488 *ebx |= (sev_get_reduced_phys_bits() & 0x3f) << 6; /* EBX[11:6] */ 6489 } 6490 break; 6491 case 0x80000021: 6492 *eax = env->features[FEAT_8000_0021_EAX]; 6493 *ebx = *ecx = *edx = 0; 6494 break; 6495 default: 6496 /* reserved values: zero */ 6497 *eax = 0; 6498 *ebx = 0; 6499 *ecx = 0; 6500 *edx = 0; 6501 break; 6502 } 6503 } 6504 6505 static void x86_cpu_set_sgxlepubkeyhash(CPUX86State *env) 6506 { 6507 #ifndef CONFIG_USER_ONLY 6508 /* Those default values are defined in Skylake HW */ 6509 env->msr_ia32_sgxlepubkeyhash[0] = 0xa6053e051270b7acULL; 6510 env->msr_ia32_sgxlepubkeyhash[1] = 0x6cfbe8ba8b3b413dULL; 6511 env->msr_ia32_sgxlepubkeyhash[2] = 0xc4916d99f2b3735dULL; 6512 env->msr_ia32_sgxlepubkeyhash[3] = 0xd4f8c05909f9bb3bULL; 6513 #endif 6514 } 6515 6516 static void x86_cpu_reset_hold(Object *obj) 6517 { 6518 CPUState *s = CPU(obj); 6519 X86CPU *cpu = X86_CPU(s); 6520 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu); 6521 CPUX86State *env = &cpu->env; 6522 target_ulong cr4; 6523 uint64_t xcr0; 6524 int i; 6525 6526 if (xcc->parent_phases.hold) { 6527 xcc->parent_phases.hold(obj); 6528 } 6529 6530 memset(env, 0, offsetof(CPUX86State, end_reset_fields)); 6531 6532 env->old_exception = -1; 6533 6534 /* init to reset state */ 6535 env->int_ctl = 0; 6536 env->hflags2 |= HF2_GIF_MASK; 6537 env->hflags2 |= HF2_VGIF_MASK; 6538 env->hflags &= ~HF_GUEST_MASK; 6539 6540 cpu_x86_update_cr0(env, 0x60000010); 6541 env->a20_mask = ~0x0; 6542 env->smbase = 0x30000; 6543 env->msr_smi_count = 0; 6544 6545 env->idt.limit = 0xffff; 6546 env->gdt.limit = 0xffff; 6547 env->ldt.limit = 0xffff; 6548 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT); 6549 env->tr.limit = 0xffff; 6550 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT); 6551 6552 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff, 6553 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK | 6554 DESC_R_MASK | DESC_A_MASK); 6555 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff, 6556 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 6557 DESC_A_MASK); 6558 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff, 6559 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 6560 DESC_A_MASK); 6561 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff, 6562 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 6563 DESC_A_MASK); 6564 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff, 6565 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 6566 DESC_A_MASK); 6567 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff, 6568 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 6569 DESC_A_MASK); 6570 6571 env->eip = 0xfff0; 6572 env->regs[R_EDX] = env->cpuid_version; 6573 6574 env->eflags = 0x2; 6575 6576 /* FPU init */ 6577 for (i = 0; i < 8; i++) { 6578 env->fptags[i] = 1; 6579 } 6580 cpu_set_fpuc(env, 0x37f); 6581 6582 env->mxcsr = 0x1f80; 6583 /* All units are in INIT state. */ 6584 env->xstate_bv = 0; 6585 6586 env->pat = 0x0007040600070406ULL; 6587 6588 if (kvm_enabled()) { 6589 /* 6590 * KVM handles TSC = 0 specially and thinks we are hot-plugging 6591 * a new CPU, use 1 instead to force a reset. 6592 */ 6593 if (env->tsc != 0) { 6594 env->tsc = 1; 6595 } 6596 } else { 6597 env->tsc = 0; 6598 } 6599 6600 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT; 6601 if (env->features[FEAT_1_ECX] & CPUID_EXT_MONITOR) { 6602 env->msr_ia32_misc_enable |= MSR_IA32_MISC_ENABLE_MWAIT; 6603 } 6604 6605 memset(env->dr, 0, sizeof(env->dr)); 6606 env->dr[6] = DR6_FIXED_1; 6607 env->dr[7] = DR7_FIXED_1; 6608 cpu_breakpoint_remove_all(s, BP_CPU); 6609 cpu_watchpoint_remove_all(s, BP_CPU); 6610 6611 cr4 = 0; 6612 xcr0 = XSTATE_FP_MASK; 6613 6614 #ifdef CONFIG_USER_ONLY 6615 /* Enable all the features for user-mode. */ 6616 if (env->features[FEAT_1_EDX] & CPUID_SSE) { 6617 xcr0 |= XSTATE_SSE_MASK; 6618 } 6619 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 6620 const ExtSaveArea *esa = &x86_ext_save_areas[i]; 6621 if (!((1 << i) & CPUID_XSTATE_XCR0_MASK)) { 6622 continue; 6623 } 6624 if (env->features[esa->feature] & esa->bits) { 6625 xcr0 |= 1ull << i; 6626 } 6627 } 6628 6629 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) { 6630 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK; 6631 } 6632 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) { 6633 cr4 |= CR4_FSGSBASE_MASK; 6634 } 6635 #endif 6636 6637 env->xcr0 = xcr0; 6638 cpu_x86_update_cr4(env, cr4); 6639 6640 /* 6641 * SDM 11.11.5 requires: 6642 * - IA32_MTRR_DEF_TYPE MSR.E = 0 6643 * - IA32_MTRR_PHYSMASKn.V = 0 6644 * All other bits are undefined. For simplification, zero it all. 6645 */ 6646 env->mtrr_deftype = 0; 6647 memset(env->mtrr_var, 0, sizeof(env->mtrr_var)); 6648 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed)); 6649 6650 env->interrupt_injected = -1; 6651 env->exception_nr = -1; 6652 env->exception_pending = 0; 6653 env->exception_injected = 0; 6654 env->exception_has_payload = false; 6655 env->exception_payload = 0; 6656 env->nmi_injected = false; 6657 env->triple_fault_pending = false; 6658 #if !defined(CONFIG_USER_ONLY) 6659 /* We hard-wire the BSP to the first CPU. */ 6660 apic_designate_bsp(cpu->apic_state, s->cpu_index == 0); 6661 6662 s->halted = !cpu_is_bsp(cpu); 6663 6664 if (kvm_enabled()) { 6665 kvm_arch_reset_vcpu(cpu); 6666 } 6667 6668 x86_cpu_set_sgxlepubkeyhash(env); 6669 6670 env->amd_tsc_scale_msr = MSR_AMD64_TSC_RATIO_DEFAULT; 6671 6672 #endif 6673 } 6674 6675 void x86_cpu_after_reset(X86CPU *cpu) 6676 { 6677 #ifndef CONFIG_USER_ONLY 6678 if (kvm_enabled()) { 6679 kvm_arch_after_reset_vcpu(cpu); 6680 } 6681 6682 if (cpu->apic_state) { 6683 device_cold_reset(cpu->apic_state); 6684 } 6685 #endif 6686 } 6687 6688 static void mce_init(X86CPU *cpu) 6689 { 6690 CPUX86State *cenv = &cpu->env; 6691 unsigned int bank; 6692 6693 if (((cenv->cpuid_version >> 8) & 0xf) >= 6 6694 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) == 6695 (CPUID_MCE | CPUID_MCA)) { 6696 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF | 6697 (cpu->enable_lmce ? MCG_LMCE_P : 0); 6698 cenv->mcg_ctl = ~(uint64_t)0; 6699 for (bank = 0; bank < MCE_BANKS_DEF; bank++) { 6700 cenv->mce_banks[bank * 4] = ~(uint64_t)0; 6701 } 6702 } 6703 } 6704 6705 static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value) 6706 { 6707 if (*min < value) { 6708 *min = value; 6709 } 6710 } 6711 6712 /* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */ 6713 static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w) 6714 { 6715 CPUX86State *env = &cpu->env; 6716 FeatureWordInfo *fi = &feature_word_info[w]; 6717 uint32_t eax = fi->cpuid.eax; 6718 uint32_t region = eax & 0xF0000000; 6719 6720 assert(feature_word_info[w].type == CPUID_FEATURE_WORD); 6721 if (!env->features[w]) { 6722 return; 6723 } 6724 6725 switch (region) { 6726 case 0x00000000: 6727 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax); 6728 break; 6729 case 0x80000000: 6730 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax); 6731 break; 6732 case 0xC0000000: 6733 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax); 6734 break; 6735 } 6736 6737 if (eax == 7) { 6738 x86_cpu_adjust_level(cpu, &env->cpuid_min_level_func7, 6739 fi->cpuid.ecx); 6740 } 6741 } 6742 6743 /* Calculate XSAVE components based on the configured CPU feature flags */ 6744 static void x86_cpu_enable_xsave_components(X86CPU *cpu) 6745 { 6746 CPUX86State *env = &cpu->env; 6747 int i; 6748 uint64_t mask; 6749 static bool request_perm; 6750 6751 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { 6752 env->features[FEAT_XSAVE_XCR0_LO] = 0; 6753 env->features[FEAT_XSAVE_XCR0_HI] = 0; 6754 return; 6755 } 6756 6757 mask = 0; 6758 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 6759 const ExtSaveArea *esa = &x86_ext_save_areas[i]; 6760 if (env->features[esa->feature] & esa->bits) { 6761 mask |= (1ULL << i); 6762 } 6763 } 6764 6765 /* Only request permission for first vcpu */ 6766 if (kvm_enabled() && !request_perm) { 6767 kvm_request_xsave_components(cpu, mask); 6768 request_perm = true; 6769 } 6770 6771 env->features[FEAT_XSAVE_XCR0_LO] = mask & CPUID_XSTATE_XCR0_MASK; 6772 env->features[FEAT_XSAVE_XCR0_HI] = mask >> 32; 6773 env->features[FEAT_XSAVE_XSS_LO] = mask & CPUID_XSTATE_XSS_MASK; 6774 env->features[FEAT_XSAVE_XSS_HI] = mask >> 32; 6775 } 6776 6777 /***** Steps involved on loading and filtering CPUID data 6778 * 6779 * When initializing and realizing a CPU object, the steps 6780 * involved in setting up CPUID data are: 6781 * 6782 * 1) Loading CPU model definition (X86CPUDefinition). This is 6783 * implemented by x86_cpu_load_model() and should be completely 6784 * transparent, as it is done automatically by instance_init. 6785 * No code should need to look at X86CPUDefinition structs 6786 * outside instance_init. 6787 * 6788 * 2) CPU expansion. This is done by realize before CPUID 6789 * filtering, and will make sure host/accelerator data is 6790 * loaded for CPU models that depend on host capabilities 6791 * (e.g. "host"). Done by x86_cpu_expand_features(). 6792 * 6793 * 3) CPUID filtering. This initializes extra data related to 6794 * CPUID, and checks if the host supports all capabilities 6795 * required by the CPU. Runnability of a CPU model is 6796 * determined at this step. Done by x86_cpu_filter_features(). 6797 * 6798 * Some operations don't require all steps to be performed. 6799 * More precisely: 6800 * 6801 * - CPU instance creation (instance_init) will run only CPU 6802 * model loading. CPU expansion can't run at instance_init-time 6803 * because host/accelerator data may be not available yet. 6804 * - CPU realization will perform both CPU model expansion and CPUID 6805 * filtering, and return an error in case one of them fails. 6806 * - query-cpu-definitions needs to run all 3 steps. It needs 6807 * to run CPUID filtering, as the 'unavailable-features' 6808 * field is set based on the filtering results. 6809 * - The query-cpu-model-expansion QMP command only needs to run 6810 * CPU model loading and CPU expansion. It should not filter 6811 * any CPUID data based on host capabilities. 6812 */ 6813 6814 /* Expand CPU configuration data, based on configured features 6815 * and host/accelerator capabilities when appropriate. 6816 */ 6817 void x86_cpu_expand_features(X86CPU *cpu, Error **errp) 6818 { 6819 CPUX86State *env = &cpu->env; 6820 FeatureWord w; 6821 int i; 6822 GList *l; 6823 6824 for (l = plus_features; l; l = l->next) { 6825 const char *prop = l->data; 6826 if (!object_property_set_bool(OBJECT(cpu), prop, true, errp)) { 6827 return; 6828 } 6829 } 6830 6831 for (l = minus_features; l; l = l->next) { 6832 const char *prop = l->data; 6833 if (!object_property_set_bool(OBJECT(cpu), prop, false, errp)) { 6834 return; 6835 } 6836 } 6837 6838 /*TODO: Now cpu->max_features doesn't overwrite features 6839 * set using QOM properties, and we can convert 6840 * plus_features & minus_features to global properties 6841 * inside x86_cpu_parse_featurestr() too. 6842 */ 6843 if (cpu->max_features) { 6844 for (w = 0; w < FEATURE_WORDS; w++) { 6845 /* Override only features that weren't set explicitly 6846 * by the user. 6847 */ 6848 env->features[w] |= 6849 x86_cpu_get_supported_feature_word(w, cpu->migratable) & 6850 ~env->user_features[w] & 6851 ~feature_word_info[w].no_autoenable_flags; 6852 } 6853 } 6854 6855 for (i = 0; i < ARRAY_SIZE(feature_dependencies); i++) { 6856 FeatureDep *d = &feature_dependencies[i]; 6857 if (!(env->features[d->from.index] & d->from.mask)) { 6858 uint64_t unavailable_features = env->features[d->to.index] & d->to.mask; 6859 6860 /* Not an error unless the dependent feature was added explicitly. */ 6861 mark_unavailable_features(cpu, d->to.index, 6862 unavailable_features & env->user_features[d->to.index], 6863 "This feature depends on other features that were not requested"); 6864 6865 env->features[d->to.index] &= ~unavailable_features; 6866 } 6867 } 6868 6869 if (!kvm_enabled() || !cpu->expose_kvm) { 6870 env->features[FEAT_KVM] = 0; 6871 } 6872 6873 x86_cpu_enable_xsave_components(cpu); 6874 6875 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */ 6876 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX); 6877 if (cpu->full_cpuid_auto_level) { 6878 x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX); 6879 x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX); 6880 x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX); 6881 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX); 6882 x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EAX); 6883 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX); 6884 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX); 6885 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX); 6886 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0008_EBX); 6887 x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX); 6888 x86_cpu_adjust_feat_level(cpu, FEAT_SVM); 6889 x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE); 6890 6891 /* Intel Processor Trace requires CPUID[0x14] */ 6892 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT)) { 6893 if (cpu->intel_pt_auto_level) { 6894 x86_cpu_adjust_level(cpu, &cpu->env.cpuid_min_level, 0x14); 6895 } else if (cpu->env.cpuid_min_level < 0x14) { 6896 mark_unavailable_features(cpu, FEAT_7_0_EBX, 6897 CPUID_7_0_EBX_INTEL_PT, 6898 "Intel PT need CPUID leaf 0x14, please set by \"-cpu ...,intel-pt=on,min-level=0x14\""); 6899 } 6900 } 6901 6902 /* 6903 * Intel CPU topology with multi-dies support requires CPUID[0x1F]. 6904 * For AMD Rome/Milan, cpuid level is 0x10, and guest OS should detect 6905 * extended toplogy by leaf 0xB. Only adjust it for Intel CPU, unless 6906 * cpu->vendor_cpuid_only has been unset for compatibility with older 6907 * machine types. 6908 */ 6909 if ((env->nr_dies > 1) && 6910 (IS_INTEL_CPU(env) || !cpu->vendor_cpuid_only)) { 6911 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x1F); 6912 } 6913 6914 /* SVM requires CPUID[0x8000000A] */ 6915 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { 6916 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A); 6917 } 6918 6919 /* SEV requires CPUID[0x8000001F] */ 6920 if (sev_enabled()) { 6921 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F); 6922 } 6923 6924 if (env->features[FEAT_8000_0021_EAX]) { 6925 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x80000021); 6926 } 6927 6928 /* SGX requires CPUID[0x12] for EPC enumeration */ 6929 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX) { 6930 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x12); 6931 } 6932 } 6933 6934 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */ 6935 if (env->cpuid_level_func7 == UINT32_MAX) { 6936 env->cpuid_level_func7 = env->cpuid_min_level_func7; 6937 } 6938 if (env->cpuid_level == UINT32_MAX) { 6939 env->cpuid_level = env->cpuid_min_level; 6940 } 6941 if (env->cpuid_xlevel == UINT32_MAX) { 6942 env->cpuid_xlevel = env->cpuid_min_xlevel; 6943 } 6944 if (env->cpuid_xlevel2 == UINT32_MAX) { 6945 env->cpuid_xlevel2 = env->cpuid_min_xlevel2; 6946 } 6947 6948 if (kvm_enabled()) { 6949 kvm_hyperv_expand_features(cpu, errp); 6950 } 6951 } 6952 6953 /* 6954 * Finishes initialization of CPUID data, filters CPU feature 6955 * words based on host availability of each feature. 6956 * 6957 * Returns: 0 if all flags are supported by the host, non-zero otherwise. 6958 */ 6959 static void x86_cpu_filter_features(X86CPU *cpu, bool verbose) 6960 { 6961 CPUX86State *env = &cpu->env; 6962 FeatureWord w; 6963 const char *prefix = NULL; 6964 6965 if (verbose) { 6966 prefix = accel_uses_host_cpuid() 6967 ? "host doesn't support requested feature" 6968 : "TCG doesn't support requested feature"; 6969 } 6970 6971 for (w = 0; w < FEATURE_WORDS; w++) { 6972 uint64_t host_feat = 6973 x86_cpu_get_supported_feature_word(w, false); 6974 uint64_t requested_features = env->features[w]; 6975 uint64_t unavailable_features = requested_features & ~host_feat; 6976 mark_unavailable_features(cpu, w, unavailable_features, prefix); 6977 } 6978 6979 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) && 6980 kvm_enabled()) { 6981 KVMState *s = CPU(cpu)->kvm_state; 6982 uint32_t eax_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EAX); 6983 uint32_t ebx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EBX); 6984 uint32_t ecx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_ECX); 6985 uint32_t eax_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EAX); 6986 uint32_t ebx_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EBX); 6987 6988 if (!eax_0 || 6989 ((ebx_0 & INTEL_PT_MINIMAL_EBX) != INTEL_PT_MINIMAL_EBX) || 6990 ((ecx_0 & INTEL_PT_MINIMAL_ECX) != INTEL_PT_MINIMAL_ECX) || 6991 ((eax_1 & INTEL_PT_MTC_BITMAP) != INTEL_PT_MTC_BITMAP) || 6992 ((eax_1 & INTEL_PT_ADDR_RANGES_NUM_MASK) < 6993 INTEL_PT_ADDR_RANGES_NUM) || 6994 ((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) != 6995 (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) || 6996 ((ecx_0 & CPUID_14_0_ECX_LIP) != 6997 (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP))) { 6998 /* 6999 * Processor Trace capabilities aren't configurable, so if the 7000 * host can't emulate the capabilities we report on 7001 * cpu_x86_cpuid(), intel-pt can't be enabled on the current host. 7002 */ 7003 mark_unavailable_features(cpu, FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT, prefix); 7004 } 7005 } 7006 } 7007 7008 static void x86_cpu_hyperv_realize(X86CPU *cpu) 7009 { 7010 size_t len; 7011 7012 /* Hyper-V vendor id */ 7013 if (!cpu->hyperv_vendor) { 7014 object_property_set_str(OBJECT(cpu), "hv-vendor-id", "Microsoft Hv", 7015 &error_abort); 7016 } 7017 len = strlen(cpu->hyperv_vendor); 7018 if (len > 12) { 7019 warn_report("hv-vendor-id truncated to 12 characters"); 7020 len = 12; 7021 } 7022 memset(cpu->hyperv_vendor_id, 0, 12); 7023 memcpy(cpu->hyperv_vendor_id, cpu->hyperv_vendor, len); 7024 7025 /* 'Hv#1' interface identification*/ 7026 cpu->hyperv_interface_id[0] = 0x31237648; 7027 cpu->hyperv_interface_id[1] = 0; 7028 cpu->hyperv_interface_id[2] = 0; 7029 cpu->hyperv_interface_id[3] = 0; 7030 7031 /* Hypervisor implementation limits */ 7032 cpu->hyperv_limits[0] = 64; 7033 cpu->hyperv_limits[1] = 0; 7034 cpu->hyperv_limits[2] = 0; 7035 } 7036 7037 static void x86_cpu_realizefn(DeviceState *dev, Error **errp) 7038 { 7039 CPUState *cs = CPU(dev); 7040 X86CPU *cpu = X86_CPU(dev); 7041 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev); 7042 CPUX86State *env = &cpu->env; 7043 Error *local_err = NULL; 7044 static bool ht_warned; 7045 unsigned requested_lbr_fmt; 7046 7047 /* Use pc-relative instructions in system-mode */ 7048 #ifndef CONFIG_USER_ONLY 7049 cs->tcg_cflags |= CF_PCREL; 7050 #endif 7051 7052 if (cpu->apic_id == UNASSIGNED_APIC_ID) { 7053 error_setg(errp, "apic-id property was not initialized properly"); 7054 return; 7055 } 7056 7057 /* 7058 * Process Hyper-V enlightenments. 7059 * Note: this currently has to happen before the expansion of CPU features. 7060 */ 7061 x86_cpu_hyperv_realize(cpu); 7062 7063 x86_cpu_expand_features(cpu, &local_err); 7064 if (local_err) { 7065 goto out; 7066 } 7067 7068 /* 7069 * Override env->features[FEAT_PERF_CAPABILITIES].LBR_FMT 7070 * with user-provided setting. 7071 */ 7072 if (cpu->lbr_fmt != ~PERF_CAP_LBR_FMT) { 7073 if ((cpu->lbr_fmt & PERF_CAP_LBR_FMT) != cpu->lbr_fmt) { 7074 error_setg(errp, "invalid lbr-fmt"); 7075 return; 7076 } 7077 env->features[FEAT_PERF_CAPABILITIES] &= ~PERF_CAP_LBR_FMT; 7078 env->features[FEAT_PERF_CAPABILITIES] |= cpu->lbr_fmt; 7079 } 7080 7081 /* 7082 * vPMU LBR is supported when 1) KVM is enabled 2) Option pmu=on and 7083 * 3)vPMU LBR format matches that of host setting. 7084 */ 7085 requested_lbr_fmt = 7086 env->features[FEAT_PERF_CAPABILITIES] & PERF_CAP_LBR_FMT; 7087 if (requested_lbr_fmt && kvm_enabled()) { 7088 uint64_t host_perf_cap = 7089 x86_cpu_get_supported_feature_word(FEAT_PERF_CAPABILITIES, false); 7090 unsigned host_lbr_fmt = host_perf_cap & PERF_CAP_LBR_FMT; 7091 7092 if (!cpu->enable_pmu) { 7093 error_setg(errp, "vPMU: LBR is unsupported without pmu=on"); 7094 return; 7095 } 7096 if (requested_lbr_fmt != host_lbr_fmt) { 7097 error_setg(errp, "vPMU: the lbr-fmt value (0x%x) does not match " 7098 "the host value (0x%x).", 7099 requested_lbr_fmt, host_lbr_fmt); 7100 return; 7101 } 7102 } 7103 7104 x86_cpu_filter_features(cpu, cpu->check_cpuid || cpu->enforce_cpuid); 7105 7106 if (cpu->enforce_cpuid && x86_cpu_have_filtered_features(cpu)) { 7107 error_setg(&local_err, 7108 accel_uses_host_cpuid() ? 7109 "Host doesn't support requested features" : 7110 "TCG doesn't support requested features"); 7111 goto out; 7112 } 7113 7114 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on 7115 * CPUID[1].EDX. 7116 */ 7117 if (IS_AMD_CPU(env)) { 7118 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES; 7119 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX] 7120 & CPUID_EXT2_AMD_ALIASES); 7121 } 7122 7123 x86_cpu_set_sgxlepubkeyhash(env); 7124 7125 /* 7126 * note: the call to the framework needs to happen after feature expansion, 7127 * but before the checks/modifications to ucode_rev, mwait, phys_bits. 7128 * These may be set by the accel-specific code, 7129 * and the results are subsequently checked / assumed in this function. 7130 */ 7131 cpu_exec_realizefn(cs, &local_err); 7132 if (local_err != NULL) { 7133 error_propagate(errp, local_err); 7134 return; 7135 } 7136 7137 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) { 7138 g_autofree char *name = x86_cpu_class_get_model_name(xcc); 7139 error_setg(&local_err, "CPU model '%s' requires KVM or HVF", name); 7140 goto out; 7141 } 7142 7143 if (cpu->ucode_rev == 0) { 7144 /* 7145 * The default is the same as KVM's. Note that this check 7146 * needs to happen after the evenual setting of ucode_rev in 7147 * accel-specific code in cpu_exec_realizefn. 7148 */ 7149 if (IS_AMD_CPU(env)) { 7150 cpu->ucode_rev = 0x01000065; 7151 } else { 7152 cpu->ucode_rev = 0x100000000ULL; 7153 } 7154 } 7155 7156 /* 7157 * mwait extended info: needed for Core compatibility 7158 * We always wake on interrupt even if host does not have the capability. 7159 * 7160 * requires the accel-specific code in cpu_exec_realizefn to 7161 * have already acquired the CPUID data into cpu->mwait. 7162 */ 7163 cpu->mwait.ecx |= CPUID_MWAIT_EMX | CPUID_MWAIT_IBE; 7164 7165 /* For 64bit systems think about the number of physical bits to present. 7166 * ideally this should be the same as the host; anything other than matching 7167 * the host can cause incorrect guest behaviour. 7168 * QEMU used to pick the magic value of 40 bits that corresponds to 7169 * consumer AMD devices but nothing else. 7170 * 7171 * Note that this code assumes features expansion has already been done 7172 * (as it checks for CPUID_EXT2_LM), and also assumes that potential 7173 * phys_bits adjustments to match the host have been already done in 7174 * accel-specific code in cpu_exec_realizefn. 7175 */ 7176 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 7177 if (cpu->phys_bits && 7178 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS || 7179 cpu->phys_bits < 32)) { 7180 error_setg(errp, "phys-bits should be between 32 and %u " 7181 " (but is %u)", 7182 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits); 7183 return; 7184 } 7185 /* 7186 * 0 means it was not explicitly set by the user (or by machine 7187 * compat_props or by the host code in host-cpu.c). 7188 * In this case, the default is the value used by TCG (40). 7189 */ 7190 if (cpu->phys_bits == 0) { 7191 cpu->phys_bits = TCG_PHYS_ADDR_BITS; 7192 } 7193 } else { 7194 /* For 32 bit systems don't use the user set value, but keep 7195 * phys_bits consistent with what we tell the guest. 7196 */ 7197 if (cpu->phys_bits != 0) { 7198 error_setg(errp, "phys-bits is not user-configurable in 32 bit"); 7199 return; 7200 } 7201 7202 if (env->features[FEAT_1_EDX] & CPUID_PSE36) { 7203 cpu->phys_bits = 36; 7204 } else { 7205 cpu->phys_bits = 32; 7206 } 7207 } 7208 7209 /* Cache information initialization */ 7210 if (!cpu->legacy_cache) { 7211 const CPUCaches *cache_info = 7212 x86_cpu_get_versioned_cache_info(cpu, xcc->model); 7213 7214 if (!xcc->model || !cache_info) { 7215 g_autofree char *name = x86_cpu_class_get_model_name(xcc); 7216 error_setg(errp, 7217 "CPU model '%s' doesn't support legacy-cache=off", name); 7218 return; 7219 } 7220 env->cache_info_cpuid2 = env->cache_info_cpuid4 = env->cache_info_amd = 7221 *cache_info; 7222 } else { 7223 /* Build legacy cache information */ 7224 env->cache_info_cpuid2.l1d_cache = &legacy_l1d_cache; 7225 env->cache_info_cpuid2.l1i_cache = &legacy_l1i_cache; 7226 env->cache_info_cpuid2.l2_cache = &legacy_l2_cache_cpuid2; 7227 env->cache_info_cpuid2.l3_cache = &legacy_l3_cache; 7228 7229 env->cache_info_cpuid4.l1d_cache = &legacy_l1d_cache; 7230 env->cache_info_cpuid4.l1i_cache = &legacy_l1i_cache; 7231 env->cache_info_cpuid4.l2_cache = &legacy_l2_cache; 7232 env->cache_info_cpuid4.l3_cache = &legacy_l3_cache; 7233 7234 env->cache_info_amd.l1d_cache = &legacy_l1d_cache_amd; 7235 env->cache_info_amd.l1i_cache = &legacy_l1i_cache_amd; 7236 env->cache_info_amd.l2_cache = &legacy_l2_cache_amd; 7237 env->cache_info_amd.l3_cache = &legacy_l3_cache; 7238 } 7239 7240 #ifndef CONFIG_USER_ONLY 7241 MachineState *ms = MACHINE(qdev_get_machine()); 7242 qemu_register_reset(x86_cpu_machine_reset_cb, cpu); 7243 7244 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || ms->smp.cpus > 1) { 7245 x86_cpu_apic_create(cpu, &local_err); 7246 if (local_err != NULL) { 7247 goto out; 7248 } 7249 } 7250 #endif 7251 7252 mce_init(cpu); 7253 7254 qemu_init_vcpu(cs); 7255 7256 /* 7257 * Most Intel and certain AMD CPUs support hyperthreading. Even though QEMU 7258 * fixes this issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX 7259 * based on inputs (sockets,cores,threads), it is still better to give 7260 * users a warning. 7261 * 7262 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise 7263 * cs->nr_threads hasn't be populated yet and the checking is incorrect. 7264 */ 7265 if (IS_AMD_CPU(env) && 7266 !(env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) && 7267 cs->nr_threads > 1 && !ht_warned) { 7268 warn_report("This family of AMD CPU doesn't support " 7269 "hyperthreading(%d)", 7270 cs->nr_threads); 7271 error_printf("Please configure -smp options properly" 7272 " or try enabling topoext feature.\n"); 7273 ht_warned = true; 7274 } 7275 7276 #ifndef CONFIG_USER_ONLY 7277 x86_cpu_apic_realize(cpu, &local_err); 7278 if (local_err != NULL) { 7279 goto out; 7280 } 7281 #endif /* !CONFIG_USER_ONLY */ 7282 cpu_reset(cs); 7283 7284 xcc->parent_realize(dev, &local_err); 7285 7286 out: 7287 if (local_err != NULL) { 7288 error_propagate(errp, local_err); 7289 return; 7290 } 7291 } 7292 7293 static void x86_cpu_unrealizefn(DeviceState *dev) 7294 { 7295 X86CPU *cpu = X86_CPU(dev); 7296 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev); 7297 7298 #ifndef CONFIG_USER_ONLY 7299 cpu_remove_sync(CPU(dev)); 7300 qemu_unregister_reset(x86_cpu_machine_reset_cb, dev); 7301 #endif 7302 7303 if (cpu->apic_state) { 7304 object_unparent(OBJECT(cpu->apic_state)); 7305 cpu->apic_state = NULL; 7306 } 7307 7308 xcc->parent_unrealize(dev); 7309 } 7310 7311 typedef struct BitProperty { 7312 FeatureWord w; 7313 uint64_t mask; 7314 } BitProperty; 7315 7316 static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name, 7317 void *opaque, Error **errp) 7318 { 7319 X86CPU *cpu = X86_CPU(obj); 7320 BitProperty *fp = opaque; 7321 uint64_t f = cpu->env.features[fp->w]; 7322 bool value = (f & fp->mask) == fp->mask; 7323 visit_type_bool(v, name, &value, errp); 7324 } 7325 7326 static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name, 7327 void *opaque, Error **errp) 7328 { 7329 DeviceState *dev = DEVICE(obj); 7330 X86CPU *cpu = X86_CPU(obj); 7331 BitProperty *fp = opaque; 7332 bool value; 7333 7334 if (dev->realized) { 7335 qdev_prop_set_after_realize(dev, name, errp); 7336 return; 7337 } 7338 7339 if (!visit_type_bool(v, name, &value, errp)) { 7340 return; 7341 } 7342 7343 if (value) { 7344 cpu->env.features[fp->w] |= fp->mask; 7345 } else { 7346 cpu->env.features[fp->w] &= ~fp->mask; 7347 } 7348 cpu->env.user_features[fp->w] |= fp->mask; 7349 } 7350 7351 /* Register a boolean property to get/set a single bit in a uint32_t field. 7352 * 7353 * The same property name can be registered multiple times to make it affect 7354 * multiple bits in the same FeatureWord. In that case, the getter will return 7355 * true only if all bits are set. 7356 */ 7357 static void x86_cpu_register_bit_prop(X86CPUClass *xcc, 7358 const char *prop_name, 7359 FeatureWord w, 7360 int bitnr) 7361 { 7362 ObjectClass *oc = OBJECT_CLASS(xcc); 7363 BitProperty *fp; 7364 ObjectProperty *op; 7365 uint64_t mask = (1ULL << bitnr); 7366 7367 op = object_class_property_find(oc, prop_name); 7368 if (op) { 7369 fp = op->opaque; 7370 assert(fp->w == w); 7371 fp->mask |= mask; 7372 } else { 7373 fp = g_new0(BitProperty, 1); 7374 fp->w = w; 7375 fp->mask = mask; 7376 object_class_property_add(oc, prop_name, "bool", 7377 x86_cpu_get_bit_prop, 7378 x86_cpu_set_bit_prop, 7379 NULL, fp); 7380 } 7381 } 7382 7383 static void x86_cpu_register_feature_bit_props(X86CPUClass *xcc, 7384 FeatureWord w, 7385 int bitnr) 7386 { 7387 FeatureWordInfo *fi = &feature_word_info[w]; 7388 const char *name = fi->feat_names[bitnr]; 7389 7390 if (!name) { 7391 return; 7392 } 7393 7394 /* Property names should use "-" instead of "_". 7395 * Old names containing underscores are registered as aliases 7396 * using object_property_add_alias() 7397 */ 7398 assert(!strchr(name, '_')); 7399 /* aliases don't use "|" delimiters anymore, they are registered 7400 * manually using object_property_add_alias() */ 7401 assert(!strchr(name, '|')); 7402 x86_cpu_register_bit_prop(xcc, name, w, bitnr); 7403 } 7404 7405 static void x86_cpu_post_initfn(Object *obj) 7406 { 7407 accel_cpu_instance_init(CPU(obj)); 7408 } 7409 7410 static void x86_cpu_initfn(Object *obj) 7411 { 7412 X86CPU *cpu = X86_CPU(obj); 7413 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj); 7414 CPUX86State *env = &cpu->env; 7415 7416 env->nr_dies = 1; 7417 cpu_set_cpustate_pointers(cpu); 7418 7419 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo", 7420 x86_cpu_get_feature_words, 7421 NULL, NULL, (void *)env->features); 7422 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo", 7423 x86_cpu_get_feature_words, 7424 NULL, NULL, (void *)cpu->filtered_features); 7425 7426 object_property_add_alias(obj, "sse3", obj, "pni"); 7427 object_property_add_alias(obj, "pclmuldq", obj, "pclmulqdq"); 7428 object_property_add_alias(obj, "sse4-1", obj, "sse4.1"); 7429 object_property_add_alias(obj, "sse4-2", obj, "sse4.2"); 7430 object_property_add_alias(obj, "xd", obj, "nx"); 7431 object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt"); 7432 object_property_add_alias(obj, "i64", obj, "lm"); 7433 7434 object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl"); 7435 object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust"); 7436 object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt"); 7437 object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm"); 7438 object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy"); 7439 object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr"); 7440 object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core"); 7441 object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb"); 7442 object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay"); 7443 object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu"); 7444 object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf"); 7445 object_property_add_alias(obj, "kvm_asyncpf_int", obj, "kvm-asyncpf-int"); 7446 object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time"); 7447 object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi"); 7448 object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt"); 7449 object_property_add_alias(obj, "kvm_poll_control", obj, "kvm-poll-control"); 7450 object_property_add_alias(obj, "svm_lock", obj, "svm-lock"); 7451 object_property_add_alias(obj, "nrip_save", obj, "nrip-save"); 7452 object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale"); 7453 object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean"); 7454 object_property_add_alias(obj, "pause_filter", obj, "pause-filter"); 7455 object_property_add_alias(obj, "sse4_1", obj, "sse4.1"); 7456 object_property_add_alias(obj, "sse4_2", obj, "sse4.2"); 7457 7458 object_property_add_alias(obj, "hv-apicv", obj, "hv-avic"); 7459 cpu->lbr_fmt = ~PERF_CAP_LBR_FMT; 7460 object_property_add_alias(obj, "lbr_fmt", obj, "lbr-fmt"); 7461 7462 if (xcc->model) { 7463 x86_cpu_load_model(cpu, xcc->model); 7464 } 7465 } 7466 7467 static int64_t x86_cpu_get_arch_id(CPUState *cs) 7468 { 7469 X86CPU *cpu = X86_CPU(cs); 7470 7471 return cpu->apic_id; 7472 } 7473 7474 #if !defined(CONFIG_USER_ONLY) 7475 static bool x86_cpu_get_paging_enabled(const CPUState *cs) 7476 { 7477 X86CPU *cpu = X86_CPU(cs); 7478 7479 return cpu->env.cr[0] & CR0_PG_MASK; 7480 } 7481 #endif /* !CONFIG_USER_ONLY */ 7482 7483 static void x86_cpu_set_pc(CPUState *cs, vaddr value) 7484 { 7485 X86CPU *cpu = X86_CPU(cs); 7486 7487 cpu->env.eip = value; 7488 } 7489 7490 static vaddr x86_cpu_get_pc(CPUState *cs) 7491 { 7492 X86CPU *cpu = X86_CPU(cs); 7493 7494 /* Match cpu_get_tb_cpu_state. */ 7495 return cpu->env.eip + cpu->env.segs[R_CS].base; 7496 } 7497 7498 int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request) 7499 { 7500 X86CPU *cpu = X86_CPU(cs); 7501 CPUX86State *env = &cpu->env; 7502 7503 #if !defined(CONFIG_USER_ONLY) 7504 if (interrupt_request & CPU_INTERRUPT_POLL) { 7505 return CPU_INTERRUPT_POLL; 7506 } 7507 #endif 7508 if (interrupt_request & CPU_INTERRUPT_SIPI) { 7509 return CPU_INTERRUPT_SIPI; 7510 } 7511 7512 if (env->hflags2 & HF2_GIF_MASK) { 7513 if ((interrupt_request & CPU_INTERRUPT_SMI) && 7514 !(env->hflags & HF_SMM_MASK)) { 7515 return CPU_INTERRUPT_SMI; 7516 } else if ((interrupt_request & CPU_INTERRUPT_NMI) && 7517 !(env->hflags2 & HF2_NMI_MASK)) { 7518 return CPU_INTERRUPT_NMI; 7519 } else if (interrupt_request & CPU_INTERRUPT_MCE) { 7520 return CPU_INTERRUPT_MCE; 7521 } else if ((interrupt_request & CPU_INTERRUPT_HARD) && 7522 (((env->hflags2 & HF2_VINTR_MASK) && 7523 (env->hflags2 & HF2_HIF_MASK)) || 7524 (!(env->hflags2 & HF2_VINTR_MASK) && 7525 (env->eflags & IF_MASK && 7526 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) { 7527 return CPU_INTERRUPT_HARD; 7528 #if !defined(CONFIG_USER_ONLY) 7529 } else if (env->hflags2 & HF2_VGIF_MASK) { 7530 if((interrupt_request & CPU_INTERRUPT_VIRQ) && 7531 (env->eflags & IF_MASK) && 7532 !(env->hflags & HF_INHIBIT_IRQ_MASK)) { 7533 return CPU_INTERRUPT_VIRQ; 7534 } 7535 #endif 7536 } 7537 } 7538 7539 return 0; 7540 } 7541 7542 static bool x86_cpu_has_work(CPUState *cs) 7543 { 7544 return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0; 7545 } 7546 7547 static void x86_disas_set_info(CPUState *cs, disassemble_info *info) 7548 { 7549 X86CPU *cpu = X86_CPU(cs); 7550 CPUX86State *env = &cpu->env; 7551 7552 info->mach = (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64 7553 : env->hflags & HF_CS32_MASK ? bfd_mach_i386_i386 7554 : bfd_mach_i386_i8086); 7555 7556 info->cap_arch = CS_ARCH_X86; 7557 info->cap_mode = (env->hflags & HF_CS64_MASK ? CS_MODE_64 7558 : env->hflags & HF_CS32_MASK ? CS_MODE_32 7559 : CS_MODE_16); 7560 info->cap_insn_unit = 1; 7561 info->cap_insn_split = 8; 7562 } 7563 7564 void x86_update_hflags(CPUX86State *env) 7565 { 7566 uint32_t hflags; 7567 #define HFLAG_COPY_MASK \ 7568 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \ 7569 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \ 7570 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \ 7571 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK) 7572 7573 hflags = env->hflags & HFLAG_COPY_MASK; 7574 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK; 7575 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT); 7576 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) & 7577 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK); 7578 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK)); 7579 7580 if (env->cr[4] & CR4_OSFXSR_MASK) { 7581 hflags |= HF_OSFXSR_MASK; 7582 } 7583 7584 if (env->efer & MSR_EFER_LMA) { 7585 hflags |= HF_LMA_MASK; 7586 } 7587 7588 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) { 7589 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; 7590 } else { 7591 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >> 7592 (DESC_B_SHIFT - HF_CS32_SHIFT); 7593 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >> 7594 (DESC_B_SHIFT - HF_SS32_SHIFT); 7595 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) || 7596 !(hflags & HF_CS32_MASK)) { 7597 hflags |= HF_ADDSEG_MASK; 7598 } else { 7599 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base | 7600 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT; 7601 } 7602 } 7603 env->hflags = hflags; 7604 } 7605 7606 static Property x86_cpu_properties[] = { 7607 #ifdef CONFIG_USER_ONLY 7608 /* apic_id = 0 by default for *-user, see commit 9886e834 */ 7609 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0), 7610 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0), 7611 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0), 7612 DEFINE_PROP_INT32("die-id", X86CPU, die_id, 0), 7613 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0), 7614 #else 7615 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID), 7616 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1), 7617 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1), 7618 DEFINE_PROP_INT32("die-id", X86CPU, die_id, -1), 7619 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1), 7620 #endif 7621 DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID), 7622 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false), 7623 DEFINE_PROP_UINT64_CHECKMASK("lbr-fmt", X86CPU, lbr_fmt, PERF_CAP_LBR_FMT), 7624 7625 DEFINE_PROP_UINT32("hv-spinlocks", X86CPU, hyperv_spinlock_attempts, 7626 HYPERV_SPINLOCK_NEVER_NOTIFY), 7627 DEFINE_PROP_BIT64("hv-relaxed", X86CPU, hyperv_features, 7628 HYPERV_FEAT_RELAXED, 0), 7629 DEFINE_PROP_BIT64("hv-vapic", X86CPU, hyperv_features, 7630 HYPERV_FEAT_VAPIC, 0), 7631 DEFINE_PROP_BIT64("hv-time", X86CPU, hyperv_features, 7632 HYPERV_FEAT_TIME, 0), 7633 DEFINE_PROP_BIT64("hv-crash", X86CPU, hyperv_features, 7634 HYPERV_FEAT_CRASH, 0), 7635 DEFINE_PROP_BIT64("hv-reset", X86CPU, hyperv_features, 7636 HYPERV_FEAT_RESET, 0), 7637 DEFINE_PROP_BIT64("hv-vpindex", X86CPU, hyperv_features, 7638 HYPERV_FEAT_VPINDEX, 0), 7639 DEFINE_PROP_BIT64("hv-runtime", X86CPU, hyperv_features, 7640 HYPERV_FEAT_RUNTIME, 0), 7641 DEFINE_PROP_BIT64("hv-synic", X86CPU, hyperv_features, 7642 HYPERV_FEAT_SYNIC, 0), 7643 DEFINE_PROP_BIT64("hv-stimer", X86CPU, hyperv_features, 7644 HYPERV_FEAT_STIMER, 0), 7645 DEFINE_PROP_BIT64("hv-frequencies", X86CPU, hyperv_features, 7646 HYPERV_FEAT_FREQUENCIES, 0), 7647 DEFINE_PROP_BIT64("hv-reenlightenment", X86CPU, hyperv_features, 7648 HYPERV_FEAT_REENLIGHTENMENT, 0), 7649 DEFINE_PROP_BIT64("hv-tlbflush", X86CPU, hyperv_features, 7650 HYPERV_FEAT_TLBFLUSH, 0), 7651 DEFINE_PROP_BIT64("hv-evmcs", X86CPU, hyperv_features, 7652 HYPERV_FEAT_EVMCS, 0), 7653 DEFINE_PROP_BIT64("hv-ipi", X86CPU, hyperv_features, 7654 HYPERV_FEAT_IPI, 0), 7655 DEFINE_PROP_BIT64("hv-stimer-direct", X86CPU, hyperv_features, 7656 HYPERV_FEAT_STIMER_DIRECT, 0), 7657 DEFINE_PROP_BIT64("hv-avic", X86CPU, hyperv_features, 7658 HYPERV_FEAT_AVIC, 0), 7659 DEFINE_PROP_BIT64("hv-emsr-bitmap", X86CPU, hyperv_features, 7660 HYPERV_FEAT_MSR_BITMAP, 0), 7661 DEFINE_PROP_BIT64("hv-xmm-input", X86CPU, hyperv_features, 7662 HYPERV_FEAT_XMM_INPUT, 0), 7663 DEFINE_PROP_BIT64("hv-tlbflush-ext", X86CPU, hyperv_features, 7664 HYPERV_FEAT_TLBFLUSH_EXT, 0), 7665 DEFINE_PROP_BIT64("hv-tlbflush-direct", X86CPU, hyperv_features, 7666 HYPERV_FEAT_TLBFLUSH_DIRECT, 0), 7667 DEFINE_PROP_ON_OFF_AUTO("hv-no-nonarch-coresharing", X86CPU, 7668 hyperv_no_nonarch_cs, ON_OFF_AUTO_OFF), 7669 DEFINE_PROP_BIT64("hv-syndbg", X86CPU, hyperv_features, 7670 HYPERV_FEAT_SYNDBG, 0), 7671 DEFINE_PROP_BOOL("hv-passthrough", X86CPU, hyperv_passthrough, false), 7672 DEFINE_PROP_BOOL("hv-enforce-cpuid", X86CPU, hyperv_enforce_cpuid, false), 7673 7674 /* WS2008R2 identify by default */ 7675 DEFINE_PROP_UINT32("hv-version-id-build", X86CPU, hyperv_ver_id_build, 7676 0x3839), 7677 DEFINE_PROP_UINT16("hv-version-id-major", X86CPU, hyperv_ver_id_major, 7678 0x000A), 7679 DEFINE_PROP_UINT16("hv-version-id-minor", X86CPU, hyperv_ver_id_minor, 7680 0x0000), 7681 DEFINE_PROP_UINT32("hv-version-id-spack", X86CPU, hyperv_ver_id_sp, 0), 7682 DEFINE_PROP_UINT8("hv-version-id-sbranch", X86CPU, hyperv_ver_id_sb, 0), 7683 DEFINE_PROP_UINT32("hv-version-id-snumber", X86CPU, hyperv_ver_id_sn, 0), 7684 7685 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true), 7686 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false), 7687 DEFINE_PROP_BOOL("x-force-features", X86CPU, force_features, false), 7688 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true), 7689 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0), 7690 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false), 7691 DEFINE_PROP_UINT8("host-phys-bits-limit", X86CPU, host_phys_bits_limit, 0), 7692 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true), 7693 DEFINE_PROP_UINT32("level-func7", X86CPU, env.cpuid_level_func7, 7694 UINT32_MAX), 7695 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX), 7696 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX), 7697 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX), 7698 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0), 7699 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0), 7700 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0), 7701 DEFINE_PROP_UINT64("ucode-rev", X86CPU, ucode_rev, 0), 7702 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true), 7703 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor), 7704 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true), 7705 DEFINE_PROP_BOOL("x-vendor-cpuid-only", X86CPU, vendor_cpuid_only, true), 7706 DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false), 7707 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true), 7708 DEFINE_PROP_BOOL("kvm-no-smi-migration", X86CPU, kvm_no_smi_migration, 7709 false), 7710 DEFINE_PROP_BOOL("kvm-pv-enforce-cpuid", X86CPU, kvm_pv_enforce_cpuid, 7711 false), 7712 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true), 7713 DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true), 7714 DEFINE_PROP_BOOL("x-migrate-smi-count", X86CPU, migrate_smi_count, 7715 true), 7716 /* 7717 * lecacy_cache defaults to true unless the CPU model provides its 7718 * own cache information (see x86_cpu_load_def()). 7719 */ 7720 DEFINE_PROP_BOOL("legacy-cache", X86CPU, legacy_cache, true), 7721 DEFINE_PROP_BOOL("xen-vapic", X86CPU, xen_vapic, false), 7722 7723 /* 7724 * From "Requirements for Implementing the Microsoft 7725 * Hypervisor Interface": 7726 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs 7727 * 7728 * "Starting with Windows Server 2012 and Windows 8, if 7729 * CPUID.40000005.EAX contains a value of -1, Windows assumes that 7730 * the hypervisor imposes no specific limit to the number of VPs. 7731 * In this case, Windows Server 2012 guest VMs may use more than 7732 * 64 VPs, up to the maximum supported number of processors applicable 7733 * to the specific Windows version being used." 7734 */ 7735 DEFINE_PROP_INT32("x-hv-max-vps", X86CPU, hv_max_vps, -1), 7736 DEFINE_PROP_BOOL("x-hv-synic-kvm-only", X86CPU, hyperv_synic_kvm_only, 7737 false), 7738 DEFINE_PROP_BOOL("x-intel-pt-auto-level", X86CPU, intel_pt_auto_level, 7739 true), 7740 DEFINE_PROP_END_OF_LIST() 7741 }; 7742 7743 #ifndef CONFIG_USER_ONLY 7744 #include "hw/core/sysemu-cpu-ops.h" 7745 7746 static const struct SysemuCPUOps i386_sysemu_ops = { 7747 .get_memory_mapping = x86_cpu_get_memory_mapping, 7748 .get_paging_enabled = x86_cpu_get_paging_enabled, 7749 .get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug, 7750 .asidx_from_attrs = x86_asidx_from_attrs, 7751 .get_crash_info = x86_cpu_get_crash_info, 7752 .write_elf32_note = x86_cpu_write_elf32_note, 7753 .write_elf64_note = x86_cpu_write_elf64_note, 7754 .write_elf32_qemunote = x86_cpu_write_elf32_qemunote, 7755 .write_elf64_qemunote = x86_cpu_write_elf64_qemunote, 7756 .legacy_vmsd = &vmstate_x86_cpu, 7757 }; 7758 #endif 7759 7760 static void x86_cpu_common_class_init(ObjectClass *oc, void *data) 7761 { 7762 X86CPUClass *xcc = X86_CPU_CLASS(oc); 7763 CPUClass *cc = CPU_CLASS(oc); 7764 DeviceClass *dc = DEVICE_CLASS(oc); 7765 ResettableClass *rc = RESETTABLE_CLASS(oc); 7766 FeatureWord w; 7767 7768 device_class_set_parent_realize(dc, x86_cpu_realizefn, 7769 &xcc->parent_realize); 7770 device_class_set_parent_unrealize(dc, x86_cpu_unrealizefn, 7771 &xcc->parent_unrealize); 7772 device_class_set_props(dc, x86_cpu_properties); 7773 7774 resettable_class_set_parent_phases(rc, NULL, x86_cpu_reset_hold, NULL, 7775 &xcc->parent_phases); 7776 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP; 7777 7778 cc->class_by_name = x86_cpu_class_by_name; 7779 cc->parse_features = x86_cpu_parse_featurestr; 7780 cc->has_work = x86_cpu_has_work; 7781 cc->dump_state = x86_cpu_dump_state; 7782 cc->set_pc = x86_cpu_set_pc; 7783 cc->get_pc = x86_cpu_get_pc; 7784 cc->gdb_read_register = x86_cpu_gdb_read_register; 7785 cc->gdb_write_register = x86_cpu_gdb_write_register; 7786 cc->get_arch_id = x86_cpu_get_arch_id; 7787 7788 #ifndef CONFIG_USER_ONLY 7789 cc->sysemu_ops = &i386_sysemu_ops; 7790 #endif /* !CONFIG_USER_ONLY */ 7791 7792 cc->gdb_arch_name = x86_gdb_arch_name; 7793 #ifdef TARGET_X86_64 7794 cc->gdb_core_xml_file = "i386-64bit.xml"; 7795 cc->gdb_num_core_regs = 66; 7796 #else 7797 cc->gdb_core_xml_file = "i386-32bit.xml"; 7798 cc->gdb_num_core_regs = 50; 7799 #endif 7800 cc->disas_set_info = x86_disas_set_info; 7801 7802 dc->user_creatable = true; 7803 7804 object_class_property_add(oc, "family", "int", 7805 x86_cpuid_version_get_family, 7806 x86_cpuid_version_set_family, NULL, NULL); 7807 object_class_property_add(oc, "model", "int", 7808 x86_cpuid_version_get_model, 7809 x86_cpuid_version_set_model, NULL, NULL); 7810 object_class_property_add(oc, "stepping", "int", 7811 x86_cpuid_version_get_stepping, 7812 x86_cpuid_version_set_stepping, NULL, NULL); 7813 object_class_property_add_str(oc, "vendor", 7814 x86_cpuid_get_vendor, 7815 x86_cpuid_set_vendor); 7816 object_class_property_add_str(oc, "model-id", 7817 x86_cpuid_get_model_id, 7818 x86_cpuid_set_model_id); 7819 object_class_property_add(oc, "tsc-frequency", "int", 7820 x86_cpuid_get_tsc_freq, 7821 x86_cpuid_set_tsc_freq, NULL, NULL); 7822 /* 7823 * The "unavailable-features" property has the same semantics as 7824 * CpuDefinitionInfo.unavailable-features on the "query-cpu-definitions" 7825 * QMP command: they list the features that would have prevented the 7826 * CPU from running if the "enforce" flag was set. 7827 */ 7828 object_class_property_add(oc, "unavailable-features", "strList", 7829 x86_cpu_get_unavailable_features, 7830 NULL, NULL, NULL); 7831 7832 #if !defined(CONFIG_USER_ONLY) 7833 object_class_property_add(oc, "crash-information", "GuestPanicInformation", 7834 x86_cpu_get_crash_info_qom, NULL, NULL, NULL); 7835 #endif 7836 7837 for (w = 0; w < FEATURE_WORDS; w++) { 7838 int bitnr; 7839 for (bitnr = 0; bitnr < 64; bitnr++) { 7840 x86_cpu_register_feature_bit_props(xcc, w, bitnr); 7841 } 7842 } 7843 } 7844 7845 static const TypeInfo x86_cpu_type_info = { 7846 .name = TYPE_X86_CPU, 7847 .parent = TYPE_CPU, 7848 .instance_size = sizeof(X86CPU), 7849 .instance_init = x86_cpu_initfn, 7850 .instance_post_init = x86_cpu_post_initfn, 7851 7852 .abstract = true, 7853 .class_size = sizeof(X86CPUClass), 7854 .class_init = x86_cpu_common_class_init, 7855 }; 7856 7857 /* "base" CPU model, used by query-cpu-model-expansion */ 7858 static void x86_cpu_base_class_init(ObjectClass *oc, void *data) 7859 { 7860 X86CPUClass *xcc = X86_CPU_CLASS(oc); 7861 7862 xcc->static_model = true; 7863 xcc->migration_safe = true; 7864 xcc->model_description = "base CPU model type with no features enabled"; 7865 xcc->ordering = 8; 7866 } 7867 7868 static const TypeInfo x86_base_cpu_type_info = { 7869 .name = X86_CPU_TYPE_NAME("base"), 7870 .parent = TYPE_X86_CPU, 7871 .class_init = x86_cpu_base_class_init, 7872 }; 7873 7874 static void x86_cpu_register_types(void) 7875 { 7876 int i; 7877 7878 type_register_static(&x86_cpu_type_info); 7879 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) { 7880 x86_register_cpudef_types(&builtin_x86_defs[i]); 7881 } 7882 type_register_static(&max_x86_cpu_type_info); 7883 type_register_static(&x86_base_cpu_type_info); 7884 } 7885 7886 type_init(x86_cpu_register_types) 7887