1 /* 2 * i386 CPUID, CPU class, definitions, models 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/units.h" 22 #include "qemu/cutils.h" 23 #include "qemu/qemu-print.h" 24 #include "qemu/hw-version.h" 25 #include "cpu.h" 26 #include "tcg/helper-tcg.h" 27 #include "sysemu/hvf.h" 28 #include "hvf/hvf-i386.h" 29 #include "kvm/kvm_i386.h" 30 #include "sev.h" 31 #include "qapi/error.h" 32 #include "qemu/error-report.h" 33 #include "qapi/qapi-visit-machine.h" 34 #include "standard-headers/asm-x86/kvm_para.h" 35 #include "hw/qdev-properties.h" 36 #include "hw/i386/topology.h" 37 #ifndef CONFIG_USER_ONLY 38 #include "sysemu/reset.h" 39 #include "qapi/qapi-commands-machine-target.h" 40 #include "exec/address-spaces.h" 41 #include "hw/boards.h" 42 #include "hw/i386/sgx-epc.h" 43 #endif 44 45 #include "disas/capstone.h" 46 #include "cpu-internal.h" 47 48 static void x86_cpu_realizefn(DeviceState *dev, Error **errp); 49 50 /* Helpers for building CPUID[2] descriptors: */ 51 52 struct CPUID2CacheDescriptorInfo { 53 enum CacheType type; 54 int level; 55 int size; 56 int line_size; 57 int associativity; 58 }; 59 60 /* 61 * Known CPUID 2 cache descriptors. 62 * From Intel SDM Volume 2A, CPUID instruction 63 */ 64 struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = { 65 [0x06] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 8 * KiB, 66 .associativity = 4, .line_size = 32, }, 67 [0x08] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 16 * KiB, 68 .associativity = 4, .line_size = 32, }, 69 [0x09] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB, 70 .associativity = 4, .line_size = 64, }, 71 [0x0A] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB, 72 .associativity = 2, .line_size = 32, }, 73 [0x0C] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 74 .associativity = 4, .line_size = 32, }, 75 [0x0D] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 76 .associativity = 4, .line_size = 64, }, 77 [0x0E] = { .level = 1, .type = DATA_CACHE, .size = 24 * KiB, 78 .associativity = 6, .line_size = 64, }, 79 [0x1D] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB, 80 .associativity = 2, .line_size = 64, }, 81 [0x21] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 82 .associativity = 8, .line_size = 64, }, 83 /* lines per sector is not supported cpuid2_cache_descriptor(), 84 * so descriptors 0x22, 0x23 are not included 85 */ 86 [0x24] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 87 .associativity = 16, .line_size = 64, }, 88 /* lines per sector is not supported cpuid2_cache_descriptor(), 89 * so descriptors 0x25, 0x20 are not included 90 */ 91 [0x2C] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB, 92 .associativity = 8, .line_size = 64, }, 93 [0x30] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB, 94 .associativity = 8, .line_size = 64, }, 95 [0x41] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB, 96 .associativity = 4, .line_size = 32, }, 97 [0x42] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 98 .associativity = 4, .line_size = 32, }, 99 [0x43] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 100 .associativity = 4, .line_size = 32, }, 101 [0x44] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 102 .associativity = 4, .line_size = 32, }, 103 [0x45] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 104 .associativity = 4, .line_size = 32, }, 105 [0x46] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 106 .associativity = 4, .line_size = 64, }, 107 [0x47] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 108 .associativity = 8, .line_size = 64, }, 109 [0x48] = { .level = 2, .type = UNIFIED_CACHE, .size = 3 * MiB, 110 .associativity = 12, .line_size = 64, }, 111 /* Descriptor 0x49 depends on CPU family/model, so it is not included */ 112 [0x4A] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB, 113 .associativity = 12, .line_size = 64, }, 114 [0x4B] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 115 .associativity = 16, .line_size = 64, }, 116 [0x4C] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB, 117 .associativity = 12, .line_size = 64, }, 118 [0x4D] = { .level = 3, .type = UNIFIED_CACHE, .size = 16 * MiB, 119 .associativity = 16, .line_size = 64, }, 120 [0x4E] = { .level = 2, .type = UNIFIED_CACHE, .size = 6 * MiB, 121 .associativity = 24, .line_size = 64, }, 122 [0x60] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 123 .associativity = 8, .line_size = 64, }, 124 [0x66] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB, 125 .associativity = 4, .line_size = 64, }, 126 [0x67] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 127 .associativity = 4, .line_size = 64, }, 128 [0x68] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB, 129 .associativity = 4, .line_size = 64, }, 130 [0x78] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 131 .associativity = 4, .line_size = 64, }, 132 /* lines per sector is not supported cpuid2_cache_descriptor(), 133 * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included. 134 */ 135 [0x7D] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 136 .associativity = 8, .line_size = 64, }, 137 [0x7F] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 138 .associativity = 2, .line_size = 64, }, 139 [0x80] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 140 .associativity = 8, .line_size = 64, }, 141 [0x82] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 142 .associativity = 8, .line_size = 32, }, 143 [0x83] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 144 .associativity = 8, .line_size = 32, }, 145 [0x84] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 146 .associativity = 8, .line_size = 32, }, 147 [0x85] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 148 .associativity = 8, .line_size = 32, }, 149 [0x86] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 150 .associativity = 4, .line_size = 64, }, 151 [0x87] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 152 .associativity = 8, .line_size = 64, }, 153 [0xD0] = { .level = 3, .type = UNIFIED_CACHE, .size = 512 * KiB, 154 .associativity = 4, .line_size = 64, }, 155 [0xD1] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB, 156 .associativity = 4, .line_size = 64, }, 157 [0xD2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 158 .associativity = 4, .line_size = 64, }, 159 [0xD6] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB, 160 .associativity = 8, .line_size = 64, }, 161 [0xD7] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 162 .associativity = 8, .line_size = 64, }, 163 [0xD8] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 164 .associativity = 8, .line_size = 64, }, 165 [0xDC] = { .level = 3, .type = UNIFIED_CACHE, .size = 1.5 * MiB, 166 .associativity = 12, .line_size = 64, }, 167 [0xDD] = { .level = 3, .type = UNIFIED_CACHE, .size = 3 * MiB, 168 .associativity = 12, .line_size = 64, }, 169 [0xDE] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB, 170 .associativity = 12, .line_size = 64, }, 171 [0xE2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 172 .associativity = 16, .line_size = 64, }, 173 [0xE3] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 174 .associativity = 16, .line_size = 64, }, 175 [0xE4] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 176 .associativity = 16, .line_size = 64, }, 177 [0xEA] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB, 178 .associativity = 24, .line_size = 64, }, 179 [0xEB] = { .level = 3, .type = UNIFIED_CACHE, .size = 18 * MiB, 180 .associativity = 24, .line_size = 64, }, 181 [0xEC] = { .level = 3, .type = UNIFIED_CACHE, .size = 24 * MiB, 182 .associativity = 24, .line_size = 64, }, 183 }; 184 185 /* 186 * "CPUID leaf 2 does not report cache descriptor information, 187 * use CPUID leaf 4 to query cache parameters" 188 */ 189 #define CACHE_DESCRIPTOR_UNAVAILABLE 0xFF 190 191 /* 192 * Return a CPUID 2 cache descriptor for a given cache. 193 * If no known descriptor is found, return CACHE_DESCRIPTOR_UNAVAILABLE 194 */ 195 static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache) 196 { 197 int i; 198 199 assert(cache->size > 0); 200 assert(cache->level > 0); 201 assert(cache->line_size > 0); 202 assert(cache->associativity > 0); 203 for (i = 0; i < ARRAY_SIZE(cpuid2_cache_descriptors); i++) { 204 struct CPUID2CacheDescriptorInfo *d = &cpuid2_cache_descriptors[i]; 205 if (d->level == cache->level && d->type == cache->type && 206 d->size == cache->size && d->line_size == cache->line_size && 207 d->associativity == cache->associativity) { 208 return i; 209 } 210 } 211 212 return CACHE_DESCRIPTOR_UNAVAILABLE; 213 } 214 215 /* CPUID Leaf 4 constants: */ 216 217 /* EAX: */ 218 #define CACHE_TYPE_D 1 219 #define CACHE_TYPE_I 2 220 #define CACHE_TYPE_UNIFIED 3 221 222 #define CACHE_LEVEL(l) (l << 5) 223 224 #define CACHE_SELF_INIT_LEVEL (1 << 8) 225 226 /* EDX: */ 227 #define CACHE_NO_INVD_SHARING (1 << 0) 228 #define CACHE_INCLUSIVE (1 << 1) 229 #define CACHE_COMPLEX_IDX (1 << 2) 230 231 /* Encode CacheType for CPUID[4].EAX */ 232 #define CACHE_TYPE(t) (((t) == DATA_CACHE) ? CACHE_TYPE_D : \ 233 ((t) == INSTRUCTION_CACHE) ? CACHE_TYPE_I : \ 234 ((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \ 235 0 /* Invalid value */) 236 237 static uint32_t max_thread_ids_for_cache(X86CPUTopoInfo *topo_info, 238 enum CPUTopoLevel share_level) 239 { 240 uint32_t num_ids = 0; 241 242 switch (share_level) { 243 case CPU_TOPO_LEVEL_CORE: 244 num_ids = 1 << apicid_core_offset(topo_info); 245 break; 246 case CPU_TOPO_LEVEL_DIE: 247 num_ids = 1 << apicid_die_offset(topo_info); 248 break; 249 case CPU_TOPO_LEVEL_PACKAGE: 250 num_ids = 1 << apicid_pkg_offset(topo_info); 251 break; 252 default: 253 /* 254 * Currently there is no use case for SMT and MODULE, so use 255 * assert directly to facilitate debugging. 256 */ 257 g_assert_not_reached(); 258 } 259 260 return num_ids - 1; 261 } 262 263 static uint32_t max_core_ids_in_package(X86CPUTopoInfo *topo_info) 264 { 265 uint32_t num_cores = 1 << (apicid_pkg_offset(topo_info) - 266 apicid_core_offset(topo_info)); 267 return num_cores - 1; 268 } 269 270 /* Encode cache info for CPUID[4] */ 271 static void encode_cache_cpuid4(CPUCacheInfo *cache, 272 X86CPUTopoInfo *topo_info, 273 uint32_t *eax, uint32_t *ebx, 274 uint32_t *ecx, uint32_t *edx) 275 { 276 assert(cache->size == cache->line_size * cache->associativity * 277 cache->partitions * cache->sets); 278 279 *eax = CACHE_TYPE(cache->type) | 280 CACHE_LEVEL(cache->level) | 281 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) | 282 (max_core_ids_in_package(topo_info) << 26) | 283 (max_thread_ids_for_cache(topo_info, cache->share_level) << 14); 284 285 assert(cache->line_size > 0); 286 assert(cache->partitions > 0); 287 assert(cache->associativity > 0); 288 /* We don't implement fully-associative caches */ 289 assert(cache->associativity < cache->sets); 290 *ebx = (cache->line_size - 1) | 291 ((cache->partitions - 1) << 12) | 292 ((cache->associativity - 1) << 22); 293 294 assert(cache->sets > 0); 295 *ecx = cache->sets - 1; 296 297 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) | 298 (cache->inclusive ? CACHE_INCLUSIVE : 0) | 299 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); 300 } 301 302 static uint32_t num_threads_by_topo_level(X86CPUTopoInfo *topo_info, 303 enum CPUTopoLevel topo_level) 304 { 305 switch (topo_level) { 306 case CPU_TOPO_LEVEL_SMT: 307 return 1; 308 case CPU_TOPO_LEVEL_CORE: 309 return topo_info->threads_per_core; 310 case CPU_TOPO_LEVEL_MODULE: 311 return topo_info->threads_per_core * topo_info->cores_per_module; 312 case CPU_TOPO_LEVEL_DIE: 313 return topo_info->threads_per_core * topo_info->cores_per_module * 314 topo_info->modules_per_die; 315 case CPU_TOPO_LEVEL_PACKAGE: 316 return topo_info->threads_per_core * topo_info->cores_per_module * 317 topo_info->modules_per_die * topo_info->dies_per_pkg; 318 default: 319 g_assert_not_reached(); 320 } 321 return 0; 322 } 323 324 static uint32_t apicid_offset_by_topo_level(X86CPUTopoInfo *topo_info, 325 enum CPUTopoLevel topo_level) 326 { 327 switch (topo_level) { 328 case CPU_TOPO_LEVEL_SMT: 329 return 0; 330 case CPU_TOPO_LEVEL_CORE: 331 return apicid_core_offset(topo_info); 332 case CPU_TOPO_LEVEL_MODULE: 333 return apicid_module_offset(topo_info); 334 case CPU_TOPO_LEVEL_DIE: 335 return apicid_die_offset(topo_info); 336 case CPU_TOPO_LEVEL_PACKAGE: 337 return apicid_pkg_offset(topo_info); 338 default: 339 g_assert_not_reached(); 340 } 341 return 0; 342 } 343 344 static uint32_t cpuid1f_topo_type(enum CPUTopoLevel topo_level) 345 { 346 switch (topo_level) { 347 case CPU_TOPO_LEVEL_INVALID: 348 return CPUID_1F_ECX_TOPO_LEVEL_INVALID; 349 case CPU_TOPO_LEVEL_SMT: 350 return CPUID_1F_ECX_TOPO_LEVEL_SMT; 351 case CPU_TOPO_LEVEL_CORE: 352 return CPUID_1F_ECX_TOPO_LEVEL_CORE; 353 case CPU_TOPO_LEVEL_MODULE: 354 return CPUID_1F_ECX_TOPO_LEVEL_MODULE; 355 case CPU_TOPO_LEVEL_DIE: 356 return CPUID_1F_ECX_TOPO_LEVEL_DIE; 357 default: 358 /* Other types are not supported in QEMU. */ 359 g_assert_not_reached(); 360 } 361 return 0; 362 } 363 364 static void encode_topo_cpuid1f(CPUX86State *env, uint32_t count, 365 X86CPUTopoInfo *topo_info, 366 uint32_t *eax, uint32_t *ebx, 367 uint32_t *ecx, uint32_t *edx) 368 { 369 X86CPU *cpu = env_archcpu(env); 370 unsigned long level, next_level; 371 uint32_t num_threads_next_level, offset_next_level; 372 373 assert(count + 1 < CPU_TOPO_LEVEL_MAX); 374 375 /* 376 * Find the No.(count + 1) topology level in avail_cpu_topo bitmap. 377 * The search starts from bit 1 (CPU_TOPO_LEVEL_INVALID + 1). 378 */ 379 level = CPU_TOPO_LEVEL_INVALID; 380 for (int i = 0; i <= count; i++) { 381 level = find_next_bit(env->avail_cpu_topo, 382 CPU_TOPO_LEVEL_PACKAGE, 383 level + 1); 384 385 /* 386 * CPUID[0x1f] doesn't explicitly encode the package level, 387 * and it just encodes the invalid level (all fields are 0) 388 * into the last subleaf of 0x1f. 389 */ 390 if (level == CPU_TOPO_LEVEL_PACKAGE) { 391 level = CPU_TOPO_LEVEL_INVALID; 392 break; 393 } 394 } 395 396 if (level == CPU_TOPO_LEVEL_INVALID) { 397 num_threads_next_level = 0; 398 offset_next_level = 0; 399 } else { 400 next_level = find_next_bit(env->avail_cpu_topo, 401 CPU_TOPO_LEVEL_PACKAGE, 402 level + 1); 403 num_threads_next_level = num_threads_by_topo_level(topo_info, 404 next_level); 405 offset_next_level = apicid_offset_by_topo_level(topo_info, 406 next_level); 407 } 408 409 *eax = offset_next_level; 410 /* The count (bits 15-00) doesn't need to be reliable. */ 411 *ebx = num_threads_next_level & 0xffff; 412 *ecx = (count & 0xff) | (cpuid1f_topo_type(level) << 8); 413 *edx = cpu->apic_id; 414 415 assert(!(*eax & ~0x1f)); 416 } 417 418 /* Encode cache info for CPUID[0x80000005].ECX or CPUID[0x80000005].EDX */ 419 static uint32_t encode_cache_cpuid80000005(CPUCacheInfo *cache) 420 { 421 assert(cache->size % 1024 == 0); 422 assert(cache->lines_per_tag > 0); 423 assert(cache->associativity > 0); 424 assert(cache->line_size > 0); 425 return ((cache->size / 1024) << 24) | (cache->associativity << 16) | 426 (cache->lines_per_tag << 8) | (cache->line_size); 427 } 428 429 #define ASSOC_FULL 0xFF 430 431 /* AMD associativity encoding used on CPUID Leaf 0x80000006: */ 432 #define AMD_ENC_ASSOC(a) (a <= 1 ? a : \ 433 a == 2 ? 0x2 : \ 434 a == 4 ? 0x4 : \ 435 a == 8 ? 0x6 : \ 436 a == 16 ? 0x8 : \ 437 a == 32 ? 0xA : \ 438 a == 48 ? 0xB : \ 439 a == 64 ? 0xC : \ 440 a == 96 ? 0xD : \ 441 a == 128 ? 0xE : \ 442 a == ASSOC_FULL ? 0xF : \ 443 0 /* invalid value */) 444 445 /* 446 * Encode cache info for CPUID[0x80000006].ECX and CPUID[0x80000006].EDX 447 * @l3 can be NULL. 448 */ 449 static void encode_cache_cpuid80000006(CPUCacheInfo *l2, 450 CPUCacheInfo *l3, 451 uint32_t *ecx, uint32_t *edx) 452 { 453 assert(l2->size % 1024 == 0); 454 assert(l2->associativity > 0); 455 assert(l2->lines_per_tag > 0); 456 assert(l2->line_size > 0); 457 *ecx = ((l2->size / 1024) << 16) | 458 (AMD_ENC_ASSOC(l2->associativity) << 12) | 459 (l2->lines_per_tag << 8) | (l2->line_size); 460 461 if (l3) { 462 assert(l3->size % (512 * 1024) == 0); 463 assert(l3->associativity > 0); 464 assert(l3->lines_per_tag > 0); 465 assert(l3->line_size > 0); 466 *edx = ((l3->size / (512 * 1024)) << 18) | 467 (AMD_ENC_ASSOC(l3->associativity) << 12) | 468 (l3->lines_per_tag << 8) | (l3->line_size); 469 } else { 470 *edx = 0; 471 } 472 } 473 474 /* Encode cache info for CPUID[8000001D] */ 475 static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, 476 X86CPUTopoInfo *topo_info, 477 uint32_t *eax, uint32_t *ebx, 478 uint32_t *ecx, uint32_t *edx) 479 { 480 assert(cache->size == cache->line_size * cache->associativity * 481 cache->partitions * cache->sets); 482 483 *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) | 484 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0); 485 *eax |= max_thread_ids_for_cache(topo_info, cache->share_level) << 14; 486 487 assert(cache->line_size > 0); 488 assert(cache->partitions > 0); 489 assert(cache->associativity > 0); 490 /* We don't implement fully-associative caches */ 491 assert(cache->associativity < cache->sets); 492 *ebx = (cache->line_size - 1) | 493 ((cache->partitions - 1) << 12) | 494 ((cache->associativity - 1) << 22); 495 496 assert(cache->sets > 0); 497 *ecx = cache->sets - 1; 498 499 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) | 500 (cache->inclusive ? CACHE_INCLUSIVE : 0) | 501 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); 502 } 503 504 /* Encode cache info for CPUID[8000001E] */ 505 static void encode_topo_cpuid8000001e(X86CPU *cpu, X86CPUTopoInfo *topo_info, 506 uint32_t *eax, uint32_t *ebx, 507 uint32_t *ecx, uint32_t *edx) 508 { 509 X86CPUTopoIDs topo_ids; 510 511 x86_topo_ids_from_apicid(cpu->apic_id, topo_info, &topo_ids); 512 513 *eax = cpu->apic_id; 514 515 /* 516 * CPUID_Fn8000001E_EBX [Core Identifiers] (CoreId) 517 * Read-only. Reset: 0000_XXXXh. 518 * See Core::X86::Cpuid::ExtApicId. 519 * Core::X86::Cpuid::CoreId_lthree[1:0]_core[3:0]_thread[1:0]; 520 * Bits Description 521 * 31:16 Reserved. 522 * 15:8 ThreadsPerCore: threads per core. Read-only. Reset: XXh. 523 * The number of threads per core is ThreadsPerCore+1. 524 * 7:0 CoreId: core ID. Read-only. Reset: XXh. 525 * 526 * NOTE: CoreId is already part of apic_id. Just use it. We can 527 * use all the 8 bits to represent the core_id here. 528 */ 529 *ebx = ((topo_info->threads_per_core - 1) << 8) | (topo_ids.core_id & 0xFF); 530 531 /* 532 * CPUID_Fn8000001E_ECX [Node Identifiers] (NodeId) 533 * Read-only. Reset: 0000_0XXXh. 534 * Core::X86::Cpuid::NodeId_lthree[1:0]_core[3:0]_thread[1:0]; 535 * Bits Description 536 * 31:11 Reserved. 537 * 10:8 NodesPerProcessor: Node per processor. Read-only. Reset: XXXb. 538 * ValidValues: 539 * Value Description 540 * 0h 1 node per processor. 541 * 7h-1h Reserved. 542 * 7:0 NodeId: Node ID. Read-only. Reset: XXh. 543 * 544 * NOTE: Hardware reserves 3 bits for number of nodes per processor. 545 * But users can create more nodes than the actual hardware can 546 * support. To genaralize we can use all the upper 8 bits for nodes. 547 * NodeId is combination of node and socket_id which is already decoded 548 * in apic_id. Just use it by shifting. 549 */ 550 if (cpu->legacy_multi_node) { 551 *ecx = ((topo_info->dies_per_pkg - 1) << 8) | 552 ((cpu->apic_id >> apicid_die_offset(topo_info)) & 0xFF); 553 } else { 554 *ecx = (cpu->apic_id >> apicid_pkg_offset(topo_info)) & 0xFF; 555 } 556 557 *edx = 0; 558 } 559 560 /* 561 * Definitions of the hardcoded cache entries we expose: 562 * These are legacy cache values. If there is a need to change any 563 * of these values please use builtin_x86_defs 564 */ 565 566 /* L1 data cache: */ 567 static CPUCacheInfo legacy_l1d_cache = { 568 .type = DATA_CACHE, 569 .level = 1, 570 .size = 32 * KiB, 571 .self_init = 1, 572 .line_size = 64, 573 .associativity = 8, 574 .sets = 64, 575 .partitions = 1, 576 .no_invd_sharing = true, 577 .share_level = CPU_TOPO_LEVEL_CORE, 578 }; 579 580 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ 581 static CPUCacheInfo legacy_l1d_cache_amd = { 582 .type = DATA_CACHE, 583 .level = 1, 584 .size = 64 * KiB, 585 .self_init = 1, 586 .line_size = 64, 587 .associativity = 2, 588 .sets = 512, 589 .partitions = 1, 590 .lines_per_tag = 1, 591 .no_invd_sharing = true, 592 .share_level = CPU_TOPO_LEVEL_CORE, 593 }; 594 595 /* L1 instruction cache: */ 596 static CPUCacheInfo legacy_l1i_cache = { 597 .type = INSTRUCTION_CACHE, 598 .level = 1, 599 .size = 32 * KiB, 600 .self_init = 1, 601 .line_size = 64, 602 .associativity = 8, 603 .sets = 64, 604 .partitions = 1, 605 .no_invd_sharing = true, 606 .share_level = CPU_TOPO_LEVEL_CORE, 607 }; 608 609 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ 610 static CPUCacheInfo legacy_l1i_cache_amd = { 611 .type = INSTRUCTION_CACHE, 612 .level = 1, 613 .size = 64 * KiB, 614 .self_init = 1, 615 .line_size = 64, 616 .associativity = 2, 617 .sets = 512, 618 .partitions = 1, 619 .lines_per_tag = 1, 620 .no_invd_sharing = true, 621 .share_level = CPU_TOPO_LEVEL_CORE, 622 }; 623 624 /* Level 2 unified cache: */ 625 static CPUCacheInfo legacy_l2_cache = { 626 .type = UNIFIED_CACHE, 627 .level = 2, 628 .size = 4 * MiB, 629 .self_init = 1, 630 .line_size = 64, 631 .associativity = 16, 632 .sets = 4096, 633 .partitions = 1, 634 .no_invd_sharing = true, 635 .share_level = CPU_TOPO_LEVEL_CORE, 636 }; 637 638 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */ 639 static CPUCacheInfo legacy_l2_cache_cpuid2 = { 640 .type = UNIFIED_CACHE, 641 .level = 2, 642 .size = 2 * MiB, 643 .line_size = 64, 644 .associativity = 8, 645 .share_level = CPU_TOPO_LEVEL_INVALID, 646 }; 647 648 649 /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */ 650 static CPUCacheInfo legacy_l2_cache_amd = { 651 .type = UNIFIED_CACHE, 652 .level = 2, 653 .size = 512 * KiB, 654 .line_size = 64, 655 .lines_per_tag = 1, 656 .associativity = 16, 657 .sets = 512, 658 .partitions = 1, 659 .share_level = CPU_TOPO_LEVEL_CORE, 660 }; 661 662 /* Level 3 unified cache: */ 663 static CPUCacheInfo legacy_l3_cache = { 664 .type = UNIFIED_CACHE, 665 .level = 3, 666 .size = 16 * MiB, 667 .line_size = 64, 668 .associativity = 16, 669 .sets = 16384, 670 .partitions = 1, 671 .lines_per_tag = 1, 672 .self_init = true, 673 .inclusive = true, 674 .complex_indexing = true, 675 .share_level = CPU_TOPO_LEVEL_DIE, 676 }; 677 678 /* TLB definitions: */ 679 680 #define L1_DTLB_2M_ASSOC 1 681 #define L1_DTLB_2M_ENTRIES 255 682 #define L1_DTLB_4K_ASSOC 1 683 #define L1_DTLB_4K_ENTRIES 255 684 685 #define L1_ITLB_2M_ASSOC 1 686 #define L1_ITLB_2M_ENTRIES 255 687 #define L1_ITLB_4K_ASSOC 1 688 #define L1_ITLB_4K_ENTRIES 255 689 690 #define L2_DTLB_2M_ASSOC 0 /* disabled */ 691 #define L2_DTLB_2M_ENTRIES 0 /* disabled */ 692 #define L2_DTLB_4K_ASSOC 4 693 #define L2_DTLB_4K_ENTRIES 512 694 695 #define L2_ITLB_2M_ASSOC 0 /* disabled */ 696 #define L2_ITLB_2M_ENTRIES 0 /* disabled */ 697 #define L2_ITLB_4K_ASSOC 4 698 #define L2_ITLB_4K_ENTRIES 512 699 700 /* CPUID Leaf 0x14 constants: */ 701 #define INTEL_PT_MAX_SUBLEAF 0x1 702 /* 703 * bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MATCH 704 * MSR can be accessed; 705 * bit[01]: Support Configurable PSB and Cycle-Accurate Mode; 706 * bit[02]: Support IP Filtering, TraceStop filtering, and preservation 707 * of Intel PT MSRs across warm reset; 708 * bit[03]: Support MTC timing packet and suppression of COFI-based packets; 709 */ 710 #define INTEL_PT_MINIMAL_EBX 0xf 711 /* 712 * bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 and 713 * IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be 714 * accessed; 715 * bit[01]: ToPA tables can hold any number of output entries, up to the 716 * maximum allowed by the MaskOrTableOffset field of 717 * IA32_RTIT_OUTPUT_MASK_PTRS; 718 * bit[02]: Support Single-Range Output scheme; 719 */ 720 #define INTEL_PT_MINIMAL_ECX 0x7 721 /* generated packets which contain IP payloads have LIP values */ 722 #define INTEL_PT_IP_LIP (1 << 31) 723 #define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */ 724 #define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3 725 #define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */ 726 #define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */ 727 #define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */ 728 729 /* CPUID Leaf 0x1D constants: */ 730 #define INTEL_AMX_TILE_MAX_SUBLEAF 0x1 731 #define INTEL_AMX_TOTAL_TILE_BYTES 0x2000 732 #define INTEL_AMX_BYTES_PER_TILE 0x400 733 #define INTEL_AMX_BYTES_PER_ROW 0x40 734 #define INTEL_AMX_TILE_MAX_NAMES 0x8 735 #define INTEL_AMX_TILE_MAX_ROWS 0x10 736 737 /* CPUID Leaf 0x1E constants: */ 738 #define INTEL_AMX_TMUL_MAX_K 0x10 739 #define INTEL_AMX_TMUL_MAX_N 0x40 740 741 void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1, 742 uint32_t vendor2, uint32_t vendor3) 743 { 744 int i; 745 for (i = 0; i < 4; i++) { 746 dst[i] = vendor1 >> (8 * i); 747 dst[i + 4] = vendor2 >> (8 * i); 748 dst[i + 8] = vendor3 >> (8 * i); 749 } 750 dst[CPUID_VENDOR_SZ] = '\0'; 751 } 752 753 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE) 754 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \ 755 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC) 756 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \ 757 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ 758 CPUID_PSE36 | CPUID_FXSR) 759 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE) 760 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \ 761 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \ 762 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \ 763 CPUID_PAE | CPUID_SEP | CPUID_APIC) 764 765 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \ 766 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \ 767 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ 768 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \ 769 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE) 770 /* partly implemented: 771 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */ 772 /* missing: 773 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */ 774 775 /* 776 * Kernel-only features that can be shown to usermode programs even if 777 * they aren't actually supported by TCG, because qemu-user only runs 778 * in CPL=3; remove them if they are ever implemented for system emulation. 779 */ 780 #if defined CONFIG_USER_ONLY 781 #define CPUID_EXT_KERNEL_FEATURES \ 782 (CPUID_EXT_PCID | CPUID_EXT_TSC_DEADLINE_TIMER) 783 #else 784 #define CPUID_EXT_KERNEL_FEATURES 0 785 #endif 786 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \ 787 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \ 788 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \ 789 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \ 790 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR | \ 791 CPUID_EXT_RDRAND | CPUID_EXT_AVX | CPUID_EXT_F16C | \ 792 CPUID_EXT_FMA | CPUID_EXT_X2APIC | CPUID_EXT_KERNEL_FEATURES) 793 /* missing: 794 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX, 795 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, 796 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA, 797 CPUID_EXT_TSC_DEADLINE_TIMER 798 */ 799 800 #ifdef TARGET_X86_64 801 #define TCG_EXT2_X86_64_FEATURES CPUID_EXT2_LM 802 #else 803 #define TCG_EXT2_X86_64_FEATURES 0 804 #endif 805 806 /* 807 * CPUID_*_KERNEL_FEATURES denotes bits and features that are not usable 808 * in usermode or by 32-bit programs. Those are added to supported 809 * TCG features unconditionally in user-mode emulation mode. This may 810 * indeed seem strange or incorrect, but it works because code running 811 * under usermode emulation cannot access them. 812 * 813 * Even for long mode, qemu-i386 is not running "a userspace program on a 814 * 32-bit CPU"; it's running "a userspace program with a 32-bit code segment" 815 * and therefore using the 32-bit ABI; the CPU itself might be 64-bit 816 * but again the difference is only visible in kernel mode. 817 */ 818 #if defined CONFIG_LINUX_USER 819 #define CPUID_EXT2_KERNEL_FEATURES (CPUID_EXT2_LM | CPUID_EXT2_FFXSR) 820 #elif defined CONFIG_USER_ONLY 821 /* FIXME: Long mode not yet supported for i386 bsd-user */ 822 #define CPUID_EXT2_KERNEL_FEATURES CPUID_EXT2_FFXSR 823 #else 824 #define CPUID_EXT2_KERNEL_FEATURES 0 825 #endif 826 827 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \ 828 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \ 829 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \ 830 CPUID_EXT2_SYSCALL | TCG_EXT2_X86_64_FEATURES | \ 831 CPUID_EXT2_KERNEL_FEATURES) 832 833 #if defined CONFIG_USER_ONLY 834 #define CPUID_EXT3_KERNEL_FEATURES CPUID_EXT3_OSVW 835 #else 836 #define CPUID_EXT3_KERNEL_FEATURES 0 837 #endif 838 839 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \ 840 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A | \ 841 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_KERNEL_FEATURES) 842 843 #define TCG_EXT4_FEATURES 0 844 845 #if defined CONFIG_USER_ONLY 846 #define CPUID_SVM_KERNEL_FEATURES (CPUID_SVM_NRIPSAVE | CPUID_SVM_VNMI) 847 #else 848 #define CPUID_SVM_KERNEL_FEATURES 0 849 #endif 850 #define TCG_SVM_FEATURES (CPUID_SVM_NPT | CPUID_SVM_VGIF | \ 851 CPUID_SVM_SVME_ADDR_CHK | CPUID_SVM_KERNEL_FEATURES) 852 853 #define TCG_KVM_FEATURES 0 854 855 #if defined CONFIG_USER_ONLY 856 #define CPUID_7_0_EBX_KERNEL_FEATURES CPUID_7_0_EBX_INVPCID 857 #else 858 #define CPUID_7_0_EBX_KERNEL_FEATURES 0 859 #endif 860 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \ 861 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \ 862 CPUID_7_0_EBX_CLFLUSHOPT | \ 863 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \ 864 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_RDSEED | \ 865 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_KERNEL_FEATURES) 866 /* missing: 867 CPUID_7_0_EBX_HLE 868 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM */ 869 870 #if !defined CONFIG_USER_ONLY || defined CONFIG_LINUX 871 #define TCG_7_0_ECX_RDPID CPUID_7_0_ECX_RDPID 872 #else 873 #define TCG_7_0_ECX_RDPID 0 874 #endif 875 #define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | \ 876 /* CPUID_7_0_ECX_OSPKE is dynamic */ \ 877 CPUID_7_0_ECX_LA57 | CPUID_7_0_ECX_PKS | CPUID_7_0_ECX_VAES | \ 878 TCG_7_0_ECX_RDPID) 879 880 #if defined CONFIG_USER_ONLY 881 #define CPUID_7_0_EDX_KERNEL_FEATURES (CPUID_7_0_EDX_SPEC_CTRL | \ 882 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD) 883 #else 884 #define CPUID_7_0_EDX_KERNEL_FEATURES 0 885 #endif 886 #define TCG_7_0_EDX_FEATURES (CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_KERNEL_FEATURES) 887 888 #define TCG_7_1_EAX_FEATURES (CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | \ 889 CPUID_7_1_EAX_FSRC | CPUID_7_1_EAX_CMPCCXADD) 890 #define TCG_7_1_EDX_FEATURES 0 891 #define TCG_7_2_EDX_FEATURES 0 892 #define TCG_APM_FEATURES 0 893 #define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT 894 #define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1) 895 /* missing: 896 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */ 897 #define TCG_14_0_ECX_FEATURES 0 898 #define TCG_SGX_12_0_EAX_FEATURES 0 899 #define TCG_SGX_12_0_EBX_FEATURES 0 900 #define TCG_SGX_12_1_EAX_FEATURES 0 901 902 #if defined CONFIG_USER_ONLY 903 #define CPUID_8000_0008_EBX_KERNEL_FEATURES (CPUID_8000_0008_EBX_IBPB | \ 904 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | \ 905 CPUID_8000_0008_EBX_STIBP_ALWAYS_ON | CPUID_8000_0008_EBX_AMD_SSBD | \ 906 CPUID_8000_0008_EBX_AMD_PSFD) 907 #else 908 #define CPUID_8000_0008_EBX_KERNEL_FEATURES 0 909 #endif 910 911 #define TCG_8000_0008_EBX (CPUID_8000_0008_EBX_XSAVEERPTR | \ 912 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_KERNEL_FEATURES) 913 914 FeatureWordInfo feature_word_info[FEATURE_WORDS] = { 915 [FEAT_1_EDX] = { 916 .type = CPUID_FEATURE_WORD, 917 .feat_names = { 918 "fpu", "vme", "de", "pse", 919 "tsc", "msr", "pae", "mce", 920 "cx8", "apic", NULL, "sep", 921 "mtrr", "pge", "mca", "cmov", 922 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */, 923 NULL, "ds" /* Intel dts */, "acpi", "mmx", 924 "fxsr", "sse", "sse2", "ss", 925 "ht" /* Intel htt */, "tm", "ia64", "pbe", 926 }, 927 .cpuid = {.eax = 1, .reg = R_EDX, }, 928 .tcg_features = TCG_FEATURES, 929 .no_autoenable_flags = CPUID_HT, 930 }, 931 [FEAT_1_ECX] = { 932 .type = CPUID_FEATURE_WORD, 933 .feat_names = { 934 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor", 935 "ds-cpl", "vmx", "smx", "est", 936 "tm2", "ssse3", "cid", NULL, 937 "fma", "cx16", "xtpr", "pdcm", 938 NULL, "pcid", "dca", "sse4.1", 939 "sse4.2", "x2apic", "movbe", "popcnt", 940 "tsc-deadline", "aes", "xsave", NULL /* osxsave */, 941 "avx", "f16c", "rdrand", "hypervisor", 942 }, 943 .cpuid = { .eax = 1, .reg = R_ECX, }, 944 .tcg_features = TCG_EXT_FEATURES, 945 }, 946 /* Feature names that are already defined on feature_name[] but 947 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their 948 * names on feat_names below. They are copied automatically 949 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD. 950 */ 951 [FEAT_8000_0001_EDX] = { 952 .type = CPUID_FEATURE_WORD, 953 .feat_names = { 954 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */, 955 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */, 956 NULL /* cx8 */, NULL /* apic */, NULL, "syscall", 957 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */, 958 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */, 959 "nx", NULL, "mmxext", NULL /* mmx */, 960 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp", 961 NULL, "lm", "3dnowext", "3dnow", 962 }, 963 .cpuid = { .eax = 0x80000001, .reg = R_EDX, }, 964 .tcg_features = TCG_EXT2_FEATURES, 965 }, 966 [FEAT_8000_0001_ECX] = { 967 .type = CPUID_FEATURE_WORD, 968 .feat_names = { 969 "lahf-lm", "cmp-legacy", "svm", "extapic", 970 "cr8legacy", "abm", "sse4a", "misalignsse", 971 "3dnowprefetch", "osvw", "ibs", "xop", 972 "skinit", "wdt", NULL, "lwp", 973 "fma4", "tce", NULL, "nodeid-msr", 974 NULL, "tbm", "topoext", "perfctr-core", 975 "perfctr-nb", NULL, NULL, NULL, 976 NULL, NULL, NULL, NULL, 977 }, 978 .cpuid = { .eax = 0x80000001, .reg = R_ECX, }, 979 .tcg_features = TCG_EXT3_FEATURES, 980 /* 981 * TOPOEXT is always allowed but can't be enabled blindly by 982 * "-cpu host", as it requires consistent cache topology info 983 * to be provided so it doesn't confuse guests. 984 */ 985 .no_autoenable_flags = CPUID_EXT3_TOPOEXT, 986 }, 987 [FEAT_C000_0001_EDX] = { 988 .type = CPUID_FEATURE_WORD, 989 .feat_names = { 990 NULL, NULL, "xstore", "xstore-en", 991 NULL, NULL, "xcrypt", "xcrypt-en", 992 "ace2", "ace2-en", "phe", "phe-en", 993 "pmm", "pmm-en", NULL, NULL, 994 NULL, NULL, NULL, NULL, 995 NULL, NULL, NULL, NULL, 996 NULL, NULL, NULL, NULL, 997 NULL, NULL, NULL, NULL, 998 }, 999 .cpuid = { .eax = 0xC0000001, .reg = R_EDX, }, 1000 .tcg_features = TCG_EXT4_FEATURES, 1001 }, 1002 [FEAT_KVM] = { 1003 .type = CPUID_FEATURE_WORD, 1004 .feat_names = { 1005 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock", 1006 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt", 1007 NULL, "kvm-pv-tlb-flush", "kvm-asyncpf-vmexit", "kvm-pv-ipi", 1008 "kvm-poll-control", "kvm-pv-sched-yield", "kvm-asyncpf-int", "kvm-msi-ext-dest-id", 1009 NULL, NULL, NULL, NULL, 1010 NULL, NULL, NULL, NULL, 1011 "kvmclock-stable-bit", NULL, NULL, NULL, 1012 NULL, NULL, NULL, NULL, 1013 }, 1014 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EAX, }, 1015 .tcg_features = TCG_KVM_FEATURES, 1016 }, 1017 [FEAT_KVM_HINTS] = { 1018 .type = CPUID_FEATURE_WORD, 1019 .feat_names = { 1020 "kvm-hint-dedicated", NULL, NULL, NULL, 1021 NULL, NULL, NULL, NULL, 1022 NULL, NULL, NULL, NULL, 1023 NULL, NULL, NULL, NULL, 1024 NULL, NULL, NULL, NULL, 1025 NULL, NULL, NULL, NULL, 1026 NULL, NULL, NULL, NULL, 1027 NULL, NULL, NULL, NULL, 1028 }, 1029 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EDX, }, 1030 .tcg_features = TCG_KVM_FEATURES, 1031 /* 1032 * KVM hints aren't auto-enabled by -cpu host, they need to be 1033 * explicitly enabled in the command-line. 1034 */ 1035 .no_autoenable_flags = ~0U, 1036 }, 1037 [FEAT_SVM] = { 1038 .type = CPUID_FEATURE_WORD, 1039 .feat_names = { 1040 "npt", "lbrv", "svm-lock", "nrip-save", 1041 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists", 1042 NULL, NULL, "pause-filter", NULL, 1043 "pfthreshold", "avic", NULL, "v-vmsave-vmload", 1044 "vgif", NULL, NULL, NULL, 1045 NULL, NULL, NULL, NULL, 1046 NULL, "vnmi", NULL, NULL, 1047 "svme-addr-chk", NULL, NULL, NULL, 1048 }, 1049 .cpuid = { .eax = 0x8000000A, .reg = R_EDX, }, 1050 .tcg_features = TCG_SVM_FEATURES, 1051 }, 1052 [FEAT_7_0_EBX] = { 1053 .type = CPUID_FEATURE_WORD, 1054 .feat_names = { 1055 "fsgsbase", "tsc-adjust", "sgx", "bmi1", 1056 "hle", "avx2", NULL, "smep", 1057 "bmi2", "erms", "invpcid", "rtm", 1058 NULL, NULL, "mpx", NULL, 1059 "avx512f", "avx512dq", "rdseed", "adx", 1060 "smap", "avx512ifma", "pcommit", "clflushopt", 1061 "clwb", "intel-pt", "avx512pf", "avx512er", 1062 "avx512cd", "sha-ni", "avx512bw", "avx512vl", 1063 }, 1064 .cpuid = { 1065 .eax = 7, 1066 .needs_ecx = true, .ecx = 0, 1067 .reg = R_EBX, 1068 }, 1069 .tcg_features = TCG_7_0_EBX_FEATURES, 1070 }, 1071 [FEAT_7_0_ECX] = { 1072 .type = CPUID_FEATURE_WORD, 1073 .feat_names = { 1074 NULL, "avx512vbmi", "umip", "pku", 1075 NULL /* ospke */, "waitpkg", "avx512vbmi2", NULL, 1076 "gfni", "vaes", "vpclmulqdq", "avx512vnni", 1077 "avx512bitalg", NULL, "avx512-vpopcntdq", NULL, 1078 "la57", NULL, NULL, NULL, 1079 NULL, NULL, "rdpid", NULL, 1080 "bus-lock-detect", "cldemote", NULL, "movdiri", 1081 "movdir64b", NULL, "sgxlc", "pks", 1082 }, 1083 .cpuid = { 1084 .eax = 7, 1085 .needs_ecx = true, .ecx = 0, 1086 .reg = R_ECX, 1087 }, 1088 .tcg_features = TCG_7_0_ECX_FEATURES, 1089 }, 1090 [FEAT_7_0_EDX] = { 1091 .type = CPUID_FEATURE_WORD, 1092 .feat_names = { 1093 NULL, NULL, "avx512-4vnniw", "avx512-4fmaps", 1094 "fsrm", NULL, NULL, NULL, 1095 "avx512-vp2intersect", NULL, "md-clear", NULL, 1096 NULL, NULL, "serialize", NULL, 1097 "tsx-ldtrk", NULL, NULL /* pconfig */, "arch-lbr", 1098 NULL, NULL, "amx-bf16", "avx512-fp16", 1099 "amx-tile", "amx-int8", "spec-ctrl", "stibp", 1100 "flush-l1d", "arch-capabilities", "core-capability", "ssbd", 1101 }, 1102 .cpuid = { 1103 .eax = 7, 1104 .needs_ecx = true, .ecx = 0, 1105 .reg = R_EDX, 1106 }, 1107 .tcg_features = TCG_7_0_EDX_FEATURES, 1108 }, 1109 [FEAT_7_1_EAX] = { 1110 .type = CPUID_FEATURE_WORD, 1111 .feat_names = { 1112 NULL, NULL, NULL, NULL, 1113 "avx-vnni", "avx512-bf16", NULL, "cmpccxadd", 1114 NULL, NULL, "fzrm", "fsrs", 1115 "fsrc", NULL, NULL, NULL, 1116 NULL, "fred", "lkgs", "wrmsrns", 1117 NULL, "amx-fp16", NULL, "avx-ifma", 1118 NULL, NULL, "lam", NULL, 1119 NULL, NULL, NULL, NULL, 1120 }, 1121 .cpuid = { 1122 .eax = 7, 1123 .needs_ecx = true, .ecx = 1, 1124 .reg = R_EAX, 1125 }, 1126 .tcg_features = TCG_7_1_EAX_FEATURES, 1127 }, 1128 [FEAT_7_1_EDX] = { 1129 .type = CPUID_FEATURE_WORD, 1130 .feat_names = { 1131 NULL, NULL, NULL, NULL, 1132 "avx-vnni-int8", "avx-ne-convert", NULL, NULL, 1133 "amx-complex", NULL, "avx-vnni-int16", NULL, 1134 NULL, NULL, "prefetchiti", NULL, 1135 NULL, NULL, NULL, NULL, 1136 NULL, NULL, NULL, NULL, 1137 NULL, NULL, NULL, NULL, 1138 NULL, NULL, NULL, NULL, 1139 }, 1140 .cpuid = { 1141 .eax = 7, 1142 .needs_ecx = true, .ecx = 1, 1143 .reg = R_EDX, 1144 }, 1145 .tcg_features = TCG_7_1_EDX_FEATURES, 1146 }, 1147 [FEAT_7_2_EDX] = { 1148 .type = CPUID_FEATURE_WORD, 1149 .feat_names = { 1150 NULL, NULL, NULL, NULL, 1151 NULL, "mcdt-no", NULL, NULL, 1152 NULL, NULL, NULL, NULL, 1153 NULL, NULL, NULL, NULL, 1154 NULL, NULL, NULL, NULL, 1155 NULL, NULL, NULL, NULL, 1156 NULL, NULL, NULL, NULL, 1157 NULL, NULL, NULL, NULL, 1158 }, 1159 .cpuid = { 1160 .eax = 7, 1161 .needs_ecx = true, .ecx = 2, 1162 .reg = R_EDX, 1163 }, 1164 .tcg_features = TCG_7_2_EDX_FEATURES, 1165 }, 1166 [FEAT_8000_0007_EDX] = { 1167 .type = CPUID_FEATURE_WORD, 1168 .feat_names = { 1169 NULL, NULL, NULL, NULL, 1170 NULL, NULL, NULL, NULL, 1171 "invtsc", NULL, NULL, NULL, 1172 NULL, NULL, NULL, NULL, 1173 NULL, NULL, NULL, NULL, 1174 NULL, NULL, NULL, NULL, 1175 NULL, NULL, NULL, NULL, 1176 NULL, NULL, NULL, NULL, 1177 }, 1178 .cpuid = { .eax = 0x80000007, .reg = R_EDX, }, 1179 .tcg_features = TCG_APM_FEATURES, 1180 .unmigratable_flags = CPUID_APM_INVTSC, 1181 }, 1182 [FEAT_8000_0007_EBX] = { 1183 .type = CPUID_FEATURE_WORD, 1184 .feat_names = { 1185 "overflow-recov", "succor", NULL, NULL, 1186 NULL, NULL, NULL, NULL, 1187 NULL, NULL, NULL, NULL, 1188 NULL, NULL, NULL, NULL, 1189 NULL, NULL, NULL, NULL, 1190 NULL, NULL, NULL, NULL, 1191 NULL, NULL, NULL, NULL, 1192 NULL, NULL, NULL, NULL, 1193 }, 1194 .cpuid = { .eax = 0x80000007, .reg = R_EBX, }, 1195 .tcg_features = 0, 1196 .unmigratable_flags = 0, 1197 }, 1198 [FEAT_8000_0008_EBX] = { 1199 .type = CPUID_FEATURE_WORD, 1200 .feat_names = { 1201 "clzero", NULL, "xsaveerptr", NULL, 1202 NULL, NULL, NULL, NULL, 1203 NULL, "wbnoinvd", NULL, NULL, 1204 "ibpb", NULL, "ibrs", "amd-stibp", 1205 NULL, "stibp-always-on", NULL, NULL, 1206 NULL, NULL, NULL, NULL, 1207 "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL, 1208 "amd-psfd", NULL, NULL, NULL, 1209 }, 1210 .cpuid = { .eax = 0x80000008, .reg = R_EBX, }, 1211 .tcg_features = TCG_8000_0008_EBX, 1212 .unmigratable_flags = 0, 1213 }, 1214 [FEAT_8000_0021_EAX] = { 1215 .type = CPUID_FEATURE_WORD, 1216 .feat_names = { 1217 "no-nested-data-bp", NULL, "lfence-always-serializing", NULL, 1218 NULL, NULL, "null-sel-clr-base", NULL, 1219 "auto-ibrs", NULL, NULL, NULL, 1220 NULL, NULL, NULL, NULL, 1221 NULL, NULL, NULL, NULL, 1222 NULL, NULL, NULL, NULL, 1223 NULL, NULL, NULL, "sbpb", 1224 "ibpb-brtype", NULL, NULL, NULL, 1225 }, 1226 .cpuid = { .eax = 0x80000021, .reg = R_EAX, }, 1227 .tcg_features = 0, 1228 .unmigratable_flags = 0, 1229 }, 1230 [FEAT_XSAVE] = { 1231 .type = CPUID_FEATURE_WORD, 1232 .feat_names = { 1233 "xsaveopt", "xsavec", "xgetbv1", "xsaves", 1234 "xfd", NULL, NULL, NULL, 1235 NULL, NULL, NULL, NULL, 1236 NULL, NULL, NULL, NULL, 1237 NULL, NULL, NULL, NULL, 1238 NULL, NULL, NULL, NULL, 1239 NULL, NULL, NULL, NULL, 1240 NULL, NULL, NULL, NULL, 1241 }, 1242 .cpuid = { 1243 .eax = 0xd, 1244 .needs_ecx = true, .ecx = 1, 1245 .reg = R_EAX, 1246 }, 1247 .tcg_features = TCG_XSAVE_FEATURES, 1248 }, 1249 [FEAT_XSAVE_XSS_LO] = { 1250 .type = CPUID_FEATURE_WORD, 1251 .feat_names = { 1252 NULL, NULL, NULL, NULL, 1253 NULL, NULL, NULL, NULL, 1254 NULL, NULL, NULL, NULL, 1255 NULL, NULL, NULL, NULL, 1256 NULL, NULL, NULL, NULL, 1257 NULL, NULL, NULL, NULL, 1258 NULL, NULL, NULL, NULL, 1259 NULL, NULL, NULL, NULL, 1260 }, 1261 .cpuid = { 1262 .eax = 0xD, 1263 .needs_ecx = true, 1264 .ecx = 1, 1265 .reg = R_ECX, 1266 }, 1267 }, 1268 [FEAT_XSAVE_XSS_HI] = { 1269 .type = CPUID_FEATURE_WORD, 1270 .cpuid = { 1271 .eax = 0xD, 1272 .needs_ecx = true, 1273 .ecx = 1, 1274 .reg = R_EDX 1275 }, 1276 }, 1277 [FEAT_6_EAX] = { 1278 .type = CPUID_FEATURE_WORD, 1279 .feat_names = { 1280 NULL, NULL, "arat", NULL, 1281 NULL, NULL, NULL, NULL, 1282 NULL, NULL, NULL, NULL, 1283 NULL, NULL, NULL, NULL, 1284 NULL, NULL, NULL, NULL, 1285 NULL, NULL, NULL, NULL, 1286 NULL, NULL, NULL, NULL, 1287 NULL, NULL, NULL, NULL, 1288 }, 1289 .cpuid = { .eax = 6, .reg = R_EAX, }, 1290 .tcg_features = TCG_6_EAX_FEATURES, 1291 }, 1292 [FEAT_XSAVE_XCR0_LO] = { 1293 .type = CPUID_FEATURE_WORD, 1294 .cpuid = { 1295 .eax = 0xD, 1296 .needs_ecx = true, .ecx = 0, 1297 .reg = R_EAX, 1298 }, 1299 .tcg_features = ~0U, 1300 .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK | 1301 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK | 1302 XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK | 1303 XSTATE_PKRU_MASK, 1304 }, 1305 [FEAT_XSAVE_XCR0_HI] = { 1306 .type = CPUID_FEATURE_WORD, 1307 .cpuid = { 1308 .eax = 0xD, 1309 .needs_ecx = true, .ecx = 0, 1310 .reg = R_EDX, 1311 }, 1312 .tcg_features = ~0U, 1313 }, 1314 /*Below are MSR exposed features*/ 1315 [FEAT_ARCH_CAPABILITIES] = { 1316 .type = MSR_FEATURE_WORD, 1317 .feat_names = { 1318 "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry", 1319 "ssb-no", "mds-no", "pschange-mc-no", "tsx-ctrl", 1320 "taa-no", NULL, NULL, NULL, 1321 NULL, "sbdr-ssdp-no", "fbsdp-no", "psdp-no", 1322 NULL, "fb-clear", NULL, NULL, 1323 NULL, NULL, NULL, NULL, 1324 "pbrsb-no", NULL, "gds-no", "rfds-no", 1325 "rfds-clear", NULL, NULL, NULL, 1326 }, 1327 .msr = { 1328 .index = MSR_IA32_ARCH_CAPABILITIES, 1329 }, 1330 /* 1331 * FEAT_ARCH_CAPABILITIES only affects a read-only MSR, which 1332 * cannot be read from user mode. Therefore, it has no impact 1333 > on any user-mode operation, and warnings about unsupported 1334 * features do not matter. 1335 */ 1336 .tcg_features = ~0U, 1337 }, 1338 [FEAT_CORE_CAPABILITY] = { 1339 .type = MSR_FEATURE_WORD, 1340 .feat_names = { 1341 NULL, NULL, NULL, NULL, 1342 NULL, "split-lock-detect", NULL, NULL, 1343 NULL, NULL, NULL, NULL, 1344 NULL, NULL, NULL, NULL, 1345 NULL, NULL, NULL, NULL, 1346 NULL, NULL, NULL, NULL, 1347 NULL, NULL, NULL, NULL, 1348 NULL, NULL, NULL, NULL, 1349 }, 1350 .msr = { 1351 .index = MSR_IA32_CORE_CAPABILITY, 1352 }, 1353 }, 1354 [FEAT_PERF_CAPABILITIES] = { 1355 .type = MSR_FEATURE_WORD, 1356 .feat_names = { 1357 NULL, NULL, NULL, NULL, 1358 NULL, NULL, NULL, NULL, 1359 NULL, NULL, NULL, NULL, 1360 NULL, "full-width-write", NULL, NULL, 1361 NULL, NULL, NULL, NULL, 1362 NULL, NULL, NULL, NULL, 1363 NULL, NULL, NULL, NULL, 1364 NULL, NULL, NULL, NULL, 1365 }, 1366 .msr = { 1367 .index = MSR_IA32_PERF_CAPABILITIES, 1368 }, 1369 }, 1370 1371 [FEAT_VMX_PROCBASED_CTLS] = { 1372 .type = MSR_FEATURE_WORD, 1373 .feat_names = { 1374 NULL, NULL, "vmx-vintr-pending", "vmx-tsc-offset", 1375 NULL, NULL, NULL, "vmx-hlt-exit", 1376 NULL, "vmx-invlpg-exit", "vmx-mwait-exit", "vmx-rdpmc-exit", 1377 "vmx-rdtsc-exit", NULL, NULL, "vmx-cr3-load-noexit", 1378 "vmx-cr3-store-noexit", NULL, NULL, "vmx-cr8-load-exit", 1379 "vmx-cr8-store-exit", "vmx-flexpriority", "vmx-vnmi-pending", "vmx-movdr-exit", 1380 "vmx-io-exit", "vmx-io-bitmap", NULL, "vmx-mtf", 1381 "vmx-msr-bitmap", "vmx-monitor-exit", "vmx-pause-exit", "vmx-secondary-ctls", 1382 }, 1383 .msr = { 1384 .index = MSR_IA32_VMX_TRUE_PROCBASED_CTLS, 1385 } 1386 }, 1387 1388 [FEAT_VMX_SECONDARY_CTLS] = { 1389 .type = MSR_FEATURE_WORD, 1390 .feat_names = { 1391 "vmx-apicv-xapic", "vmx-ept", "vmx-desc-exit", "vmx-rdtscp-exit", 1392 "vmx-apicv-x2apic", "vmx-vpid", "vmx-wbinvd-exit", "vmx-unrestricted-guest", 1393 "vmx-apicv-register", "vmx-apicv-vid", "vmx-ple", "vmx-rdrand-exit", 1394 "vmx-invpcid-exit", "vmx-vmfunc", "vmx-shadow-vmcs", "vmx-encls-exit", 1395 "vmx-rdseed-exit", "vmx-pml", NULL, NULL, 1396 "vmx-xsaves", NULL, NULL, NULL, 1397 NULL, "vmx-tsc-scaling", "vmx-enable-user-wait-pause", NULL, 1398 NULL, NULL, NULL, NULL, 1399 }, 1400 .msr = { 1401 .index = MSR_IA32_VMX_PROCBASED_CTLS2, 1402 } 1403 }, 1404 1405 [FEAT_VMX_PINBASED_CTLS] = { 1406 .type = MSR_FEATURE_WORD, 1407 .feat_names = { 1408 "vmx-intr-exit", NULL, NULL, "vmx-nmi-exit", 1409 NULL, "vmx-vnmi", "vmx-preemption-timer", "vmx-posted-intr", 1410 NULL, NULL, NULL, NULL, 1411 NULL, NULL, NULL, NULL, 1412 NULL, NULL, NULL, NULL, 1413 NULL, NULL, NULL, NULL, 1414 NULL, NULL, NULL, NULL, 1415 NULL, NULL, NULL, NULL, 1416 }, 1417 .msr = { 1418 .index = MSR_IA32_VMX_TRUE_PINBASED_CTLS, 1419 } 1420 }, 1421 1422 [FEAT_VMX_EXIT_CTLS] = { 1423 .type = MSR_FEATURE_WORD, 1424 /* 1425 * VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE is copied from 1426 * the LM CPUID bit. 1427 */ 1428 .feat_names = { 1429 NULL, NULL, "vmx-exit-nosave-debugctl", NULL, 1430 NULL, NULL, NULL, NULL, 1431 NULL, NULL /* vmx-exit-host-addr-space-size */, NULL, NULL, 1432 "vmx-exit-load-perf-global-ctrl", NULL, NULL, "vmx-exit-ack-intr", 1433 NULL, NULL, "vmx-exit-save-pat", "vmx-exit-load-pat", 1434 "vmx-exit-save-efer", "vmx-exit-load-efer", 1435 "vmx-exit-save-preemption-timer", "vmx-exit-clear-bndcfgs", 1436 NULL, "vmx-exit-clear-rtit-ctl", NULL, NULL, 1437 NULL, "vmx-exit-load-pkrs", NULL, "vmx-exit-secondary-ctls", 1438 }, 1439 .msr = { 1440 .index = MSR_IA32_VMX_TRUE_EXIT_CTLS, 1441 } 1442 }, 1443 1444 [FEAT_VMX_ENTRY_CTLS] = { 1445 .type = MSR_FEATURE_WORD, 1446 .feat_names = { 1447 NULL, NULL, "vmx-entry-noload-debugctl", NULL, 1448 NULL, NULL, NULL, NULL, 1449 NULL, "vmx-entry-ia32e-mode", NULL, NULL, 1450 NULL, "vmx-entry-load-perf-global-ctrl", "vmx-entry-load-pat", "vmx-entry-load-efer", 1451 "vmx-entry-load-bndcfgs", NULL, "vmx-entry-load-rtit-ctl", NULL, 1452 NULL, NULL, "vmx-entry-load-pkrs", "vmx-entry-load-fred", 1453 NULL, NULL, NULL, NULL, 1454 NULL, NULL, NULL, NULL, 1455 }, 1456 .msr = { 1457 .index = MSR_IA32_VMX_TRUE_ENTRY_CTLS, 1458 } 1459 }, 1460 1461 [FEAT_VMX_MISC] = { 1462 .type = MSR_FEATURE_WORD, 1463 .feat_names = { 1464 NULL, NULL, NULL, NULL, 1465 NULL, "vmx-store-lma", "vmx-activity-hlt", "vmx-activity-shutdown", 1466 "vmx-activity-wait-sipi", NULL, NULL, NULL, 1467 NULL, NULL, NULL, NULL, 1468 NULL, NULL, NULL, NULL, 1469 NULL, NULL, NULL, NULL, 1470 NULL, NULL, NULL, NULL, 1471 NULL, "vmx-vmwrite-vmexit-fields", "vmx-zero-len-inject", NULL, 1472 }, 1473 .msr = { 1474 .index = MSR_IA32_VMX_MISC, 1475 } 1476 }, 1477 1478 [FEAT_VMX_EPT_VPID_CAPS] = { 1479 .type = MSR_FEATURE_WORD, 1480 .feat_names = { 1481 "vmx-ept-execonly", NULL, NULL, NULL, 1482 NULL, NULL, "vmx-page-walk-4", "vmx-page-walk-5", 1483 NULL, NULL, NULL, NULL, 1484 NULL, NULL, NULL, NULL, 1485 "vmx-ept-2mb", "vmx-ept-1gb", NULL, NULL, 1486 "vmx-invept", "vmx-eptad", "vmx-ept-advanced-exitinfo", NULL, 1487 NULL, "vmx-invept-single-context", "vmx-invept-all-context", NULL, 1488 NULL, NULL, NULL, NULL, 1489 "vmx-invvpid", NULL, NULL, NULL, 1490 NULL, NULL, NULL, NULL, 1491 "vmx-invvpid-single-addr", "vmx-invept-single-context", 1492 "vmx-invvpid-all-context", "vmx-invept-single-context-noglobals", 1493 NULL, NULL, NULL, NULL, 1494 NULL, NULL, NULL, NULL, 1495 NULL, NULL, NULL, NULL, 1496 NULL, NULL, NULL, NULL, 1497 NULL, NULL, NULL, NULL, 1498 }, 1499 .msr = { 1500 .index = MSR_IA32_VMX_EPT_VPID_CAP, 1501 } 1502 }, 1503 1504 [FEAT_VMX_BASIC] = { 1505 .type = MSR_FEATURE_WORD, 1506 .feat_names = { 1507 [54] = "vmx-ins-outs", 1508 [55] = "vmx-true-ctls", 1509 [56] = "vmx-any-errcode", 1510 [58] = "vmx-nested-exception", 1511 }, 1512 .msr = { 1513 .index = MSR_IA32_VMX_BASIC, 1514 }, 1515 /* Just to be safe - we don't support setting the MSEG version field. */ 1516 .no_autoenable_flags = MSR_VMX_BASIC_DUAL_MONITOR, 1517 }, 1518 1519 [FEAT_VMX_VMFUNC] = { 1520 .type = MSR_FEATURE_WORD, 1521 .feat_names = { 1522 [0] = "vmx-eptp-switching", 1523 }, 1524 .msr = { 1525 .index = MSR_IA32_VMX_VMFUNC, 1526 } 1527 }, 1528 1529 [FEAT_14_0_ECX] = { 1530 .type = CPUID_FEATURE_WORD, 1531 .feat_names = { 1532 NULL, NULL, NULL, NULL, 1533 NULL, NULL, NULL, NULL, 1534 NULL, NULL, NULL, NULL, 1535 NULL, NULL, NULL, NULL, 1536 NULL, NULL, NULL, NULL, 1537 NULL, NULL, NULL, NULL, 1538 NULL, NULL, NULL, NULL, 1539 NULL, NULL, NULL, "intel-pt-lip", 1540 }, 1541 .cpuid = { 1542 .eax = 0x14, 1543 .needs_ecx = true, .ecx = 0, 1544 .reg = R_ECX, 1545 }, 1546 .tcg_features = TCG_14_0_ECX_FEATURES, 1547 }, 1548 1549 [FEAT_SGX_12_0_EAX] = { 1550 .type = CPUID_FEATURE_WORD, 1551 .feat_names = { 1552 "sgx1", "sgx2", NULL, NULL, 1553 NULL, NULL, NULL, NULL, 1554 NULL, NULL, NULL, "sgx-edeccssa", 1555 NULL, NULL, NULL, NULL, 1556 NULL, NULL, NULL, NULL, 1557 NULL, NULL, NULL, NULL, 1558 NULL, NULL, NULL, NULL, 1559 NULL, NULL, NULL, NULL, 1560 }, 1561 .cpuid = { 1562 .eax = 0x12, 1563 .needs_ecx = true, .ecx = 0, 1564 .reg = R_EAX, 1565 }, 1566 .tcg_features = TCG_SGX_12_0_EAX_FEATURES, 1567 }, 1568 1569 [FEAT_SGX_12_0_EBX] = { 1570 .type = CPUID_FEATURE_WORD, 1571 .feat_names = { 1572 "sgx-exinfo" , NULL, NULL, NULL, 1573 NULL, NULL, NULL, NULL, 1574 NULL, NULL, NULL, NULL, 1575 NULL, NULL, NULL, NULL, 1576 NULL, NULL, NULL, NULL, 1577 NULL, NULL, NULL, NULL, 1578 NULL, NULL, NULL, NULL, 1579 NULL, NULL, NULL, NULL, 1580 }, 1581 .cpuid = { 1582 .eax = 0x12, 1583 .needs_ecx = true, .ecx = 0, 1584 .reg = R_EBX, 1585 }, 1586 .tcg_features = TCG_SGX_12_0_EBX_FEATURES, 1587 }, 1588 1589 [FEAT_SGX_12_1_EAX] = { 1590 .type = CPUID_FEATURE_WORD, 1591 .feat_names = { 1592 NULL, "sgx-debug", "sgx-mode64", NULL, 1593 "sgx-provisionkey", "sgx-tokenkey", NULL, "sgx-kss", 1594 NULL, NULL, "sgx-aex-notify", NULL, 1595 NULL, NULL, NULL, NULL, 1596 NULL, NULL, NULL, NULL, 1597 NULL, NULL, NULL, NULL, 1598 NULL, NULL, NULL, NULL, 1599 NULL, NULL, NULL, NULL, 1600 }, 1601 .cpuid = { 1602 .eax = 0x12, 1603 .needs_ecx = true, .ecx = 1, 1604 .reg = R_EAX, 1605 }, 1606 .tcg_features = TCG_SGX_12_1_EAX_FEATURES, 1607 }, 1608 }; 1609 1610 typedef struct FeatureMask { 1611 FeatureWord index; 1612 uint64_t mask; 1613 } FeatureMask; 1614 1615 typedef struct FeatureDep { 1616 FeatureMask from, to; 1617 } FeatureDep; 1618 1619 static FeatureDep feature_dependencies[] = { 1620 { 1621 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_ARCH_CAPABILITIES }, 1622 .to = { FEAT_ARCH_CAPABILITIES, ~0ull }, 1623 }, 1624 { 1625 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_CORE_CAPABILITY }, 1626 .to = { FEAT_CORE_CAPABILITY, ~0ull }, 1627 }, 1628 { 1629 .from = { FEAT_1_ECX, CPUID_EXT_PDCM }, 1630 .to = { FEAT_PERF_CAPABILITIES, ~0ull }, 1631 }, 1632 { 1633 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1634 .to = { FEAT_VMX_PROCBASED_CTLS, ~0ull }, 1635 }, 1636 { 1637 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1638 .to = { FEAT_VMX_PINBASED_CTLS, ~0ull }, 1639 }, 1640 { 1641 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1642 .to = { FEAT_VMX_EXIT_CTLS, ~0ull }, 1643 }, 1644 { 1645 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1646 .to = { FEAT_VMX_ENTRY_CTLS, ~0ull }, 1647 }, 1648 { 1649 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1650 .to = { FEAT_VMX_MISC, ~0ull }, 1651 }, 1652 { 1653 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1654 .to = { FEAT_VMX_BASIC, ~0ull }, 1655 }, 1656 { 1657 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_LM }, 1658 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_IA32E_MODE }, 1659 }, 1660 { 1661 .from = { FEAT_VMX_PROCBASED_CTLS, VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS }, 1662 .to = { FEAT_VMX_SECONDARY_CTLS, ~0ull }, 1663 }, 1664 { 1665 .from = { FEAT_XSAVE, CPUID_XSAVE_XSAVES }, 1666 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_XSAVES }, 1667 }, 1668 { 1669 .from = { FEAT_1_ECX, CPUID_EXT_RDRAND }, 1670 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDRAND_EXITING }, 1671 }, 1672 { 1673 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INVPCID }, 1674 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_INVPCID }, 1675 }, 1676 { 1677 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_MPX }, 1678 .to = { FEAT_VMX_EXIT_CTLS, VMX_VM_EXIT_CLEAR_BNDCFGS }, 1679 }, 1680 { 1681 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_MPX }, 1682 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_LOAD_BNDCFGS }, 1683 }, 1684 { 1685 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_RDSEED }, 1686 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDSEED_EXITING }, 1687 }, 1688 { 1689 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT }, 1690 .to = { FEAT_14_0_ECX, ~0ull }, 1691 }, 1692 { 1693 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_RDTSCP }, 1694 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDTSCP }, 1695 }, 1696 { 1697 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT }, 1698 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull }, 1699 }, 1700 { 1701 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT }, 1702 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST }, 1703 }, 1704 { 1705 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VPID }, 1706 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull << 32 }, 1707 }, 1708 { 1709 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VMFUNC }, 1710 .to = { FEAT_VMX_VMFUNC, ~0ull }, 1711 }, 1712 { 1713 .from = { FEAT_8000_0001_ECX, CPUID_EXT3_SVM }, 1714 .to = { FEAT_SVM, ~0ull }, 1715 }, 1716 { 1717 .from = { FEAT_7_0_ECX, CPUID_7_0_ECX_WAITPKG }, 1718 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_USER_WAIT_PAUSE }, 1719 }, 1720 { 1721 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_LM }, 1722 .to = { FEAT_7_1_EAX, CPUID_7_1_EAX_FRED }, 1723 }, 1724 { 1725 .from = { FEAT_7_1_EAX, CPUID_7_1_EAX_LKGS }, 1726 .to = { FEAT_7_1_EAX, CPUID_7_1_EAX_FRED }, 1727 }, 1728 { 1729 .from = { FEAT_7_1_EAX, CPUID_7_1_EAX_WRMSRNS }, 1730 .to = { FEAT_7_1_EAX, CPUID_7_1_EAX_FRED }, 1731 }, 1732 { 1733 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_SGX }, 1734 .to = { FEAT_7_0_ECX, CPUID_7_0_ECX_SGX_LC }, 1735 }, 1736 { 1737 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_SGX }, 1738 .to = { FEAT_SGX_12_0_EAX, ~0ull }, 1739 }, 1740 { 1741 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_SGX }, 1742 .to = { FEAT_SGX_12_0_EBX, ~0ull }, 1743 }, 1744 { 1745 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_SGX }, 1746 .to = { FEAT_SGX_12_1_EAX, ~0ull }, 1747 }, 1748 }; 1749 1750 typedef struct X86RegisterInfo32 { 1751 /* Name of register */ 1752 const char *name; 1753 /* QAPI enum value register */ 1754 X86CPURegister32 qapi_enum; 1755 } X86RegisterInfo32; 1756 1757 #define REGISTER(reg) \ 1758 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg } 1759 static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = { 1760 REGISTER(EAX), 1761 REGISTER(ECX), 1762 REGISTER(EDX), 1763 REGISTER(EBX), 1764 REGISTER(ESP), 1765 REGISTER(EBP), 1766 REGISTER(ESI), 1767 REGISTER(EDI), 1768 }; 1769 #undef REGISTER 1770 1771 /* CPUID feature bits available in XSS */ 1772 #define CPUID_XSTATE_XSS_MASK (XSTATE_ARCH_LBR_MASK) 1773 1774 ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUNT] = { 1775 [XSTATE_FP_BIT] = { 1776 /* x87 FP state component is always enabled if XSAVE is supported */ 1777 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE, 1778 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader), 1779 }, 1780 [XSTATE_SSE_BIT] = { 1781 /* SSE state component is always enabled if XSAVE is supported */ 1782 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE, 1783 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader), 1784 }, 1785 [XSTATE_YMM_BIT] = 1786 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX, 1787 .size = sizeof(XSaveAVX) }, 1788 [XSTATE_BNDREGS_BIT] = 1789 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX, 1790 .size = sizeof(XSaveBNDREG) }, 1791 [XSTATE_BNDCSR_BIT] = 1792 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX, 1793 .size = sizeof(XSaveBNDCSR) }, 1794 [XSTATE_OPMASK_BIT] = 1795 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1796 .size = sizeof(XSaveOpmask) }, 1797 [XSTATE_ZMM_Hi256_BIT] = 1798 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1799 .size = sizeof(XSaveZMM_Hi256) }, 1800 [XSTATE_Hi16_ZMM_BIT] = 1801 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1802 .size = sizeof(XSaveHi16_ZMM) }, 1803 [XSTATE_PKRU_BIT] = 1804 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU, 1805 .size = sizeof(XSavePKRU) }, 1806 [XSTATE_ARCH_LBR_BIT] = { 1807 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_ARCH_LBR, 1808 .offset = 0 /*supervisor mode component, offset = 0 */, 1809 .size = sizeof(XSavesArchLBR) }, 1810 [XSTATE_XTILE_CFG_BIT] = { 1811 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_AMX_TILE, 1812 .size = sizeof(XSaveXTILECFG), 1813 }, 1814 [XSTATE_XTILE_DATA_BIT] = { 1815 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_AMX_TILE, 1816 .size = sizeof(XSaveXTILEDATA) 1817 }, 1818 }; 1819 1820 uint32_t xsave_area_size(uint64_t mask, bool compacted) 1821 { 1822 uint64_t ret = x86_ext_save_areas[0].size; 1823 const ExtSaveArea *esa; 1824 uint32_t offset = 0; 1825 int i; 1826 1827 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 1828 esa = &x86_ext_save_areas[i]; 1829 if ((mask >> i) & 1) { 1830 offset = compacted ? ret : esa->offset; 1831 ret = MAX(ret, offset + esa->size); 1832 } 1833 } 1834 return ret; 1835 } 1836 1837 static inline bool accel_uses_host_cpuid(void) 1838 { 1839 return kvm_enabled() || hvf_enabled(); 1840 } 1841 1842 static inline uint64_t x86_cpu_xsave_xcr0_components(X86CPU *cpu) 1843 { 1844 return ((uint64_t)cpu->env.features[FEAT_XSAVE_XCR0_HI]) << 32 | 1845 cpu->env.features[FEAT_XSAVE_XCR0_LO]; 1846 } 1847 1848 /* Return name of 32-bit register, from a R_* constant */ 1849 static const char *get_register_name_32(unsigned int reg) 1850 { 1851 if (reg >= CPU_NB_REGS32) { 1852 return NULL; 1853 } 1854 return x86_reg_info_32[reg].name; 1855 } 1856 1857 static inline uint64_t x86_cpu_xsave_xss_components(X86CPU *cpu) 1858 { 1859 return ((uint64_t)cpu->env.features[FEAT_XSAVE_XSS_HI]) << 32 | 1860 cpu->env.features[FEAT_XSAVE_XSS_LO]; 1861 } 1862 1863 /* 1864 * Returns the set of feature flags that are supported and migratable by 1865 * QEMU, for a given FeatureWord. 1866 */ 1867 static uint64_t x86_cpu_get_migratable_flags(FeatureWord w) 1868 { 1869 FeatureWordInfo *wi = &feature_word_info[w]; 1870 uint64_t r = 0; 1871 int i; 1872 1873 for (i = 0; i < 64; i++) { 1874 uint64_t f = 1ULL << i; 1875 1876 /* If the feature name is known, it is implicitly considered migratable, 1877 * unless it is explicitly set in unmigratable_flags */ 1878 if ((wi->migratable_flags & f) || 1879 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) { 1880 r |= f; 1881 } 1882 } 1883 return r; 1884 } 1885 1886 void host_cpuid(uint32_t function, uint32_t count, 1887 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) 1888 { 1889 uint32_t vec[4]; 1890 1891 #ifdef __x86_64__ 1892 asm volatile("cpuid" 1893 : "=a"(vec[0]), "=b"(vec[1]), 1894 "=c"(vec[2]), "=d"(vec[3]) 1895 : "0"(function), "c"(count) : "cc"); 1896 #elif defined(__i386__) 1897 asm volatile("pusha \n\t" 1898 "cpuid \n\t" 1899 "mov %%eax, 0(%2) \n\t" 1900 "mov %%ebx, 4(%2) \n\t" 1901 "mov %%ecx, 8(%2) \n\t" 1902 "mov %%edx, 12(%2) \n\t" 1903 "popa" 1904 : : "a"(function), "c"(count), "S"(vec) 1905 : "memory", "cc"); 1906 #else 1907 abort(); 1908 #endif 1909 1910 if (eax) 1911 *eax = vec[0]; 1912 if (ebx) 1913 *ebx = vec[1]; 1914 if (ecx) 1915 *ecx = vec[2]; 1916 if (edx) 1917 *edx = vec[3]; 1918 } 1919 1920 /* CPU class name definitions: */ 1921 1922 /* Return type name for a given CPU model name 1923 * Caller is responsible for freeing the returned string. 1924 */ 1925 static char *x86_cpu_type_name(const char *model_name) 1926 { 1927 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name); 1928 } 1929 1930 static ObjectClass *x86_cpu_class_by_name(const char *cpu_model) 1931 { 1932 g_autofree char *typename = x86_cpu_type_name(cpu_model); 1933 return object_class_by_name(typename); 1934 } 1935 1936 static char *x86_cpu_class_get_model_name(X86CPUClass *cc) 1937 { 1938 const char *class_name = object_class_get_name(OBJECT_CLASS(cc)); 1939 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX)); 1940 return cpu_model_from_type(class_name); 1941 } 1942 1943 typedef struct X86CPUVersionDefinition { 1944 X86CPUVersion version; 1945 const char *alias; 1946 const char *note; 1947 PropValue *props; 1948 const CPUCaches *const cache_info; 1949 } X86CPUVersionDefinition; 1950 1951 /* Base definition for a CPU model */ 1952 typedef struct X86CPUDefinition { 1953 const char *name; 1954 uint32_t level; 1955 uint32_t xlevel; 1956 /* vendor is zero-terminated, 12 character ASCII string */ 1957 char vendor[CPUID_VENDOR_SZ + 1]; 1958 int family; 1959 int model; 1960 int stepping; 1961 FeatureWordArray features; 1962 const char *model_id; 1963 const CPUCaches *const cache_info; 1964 /* 1965 * Definitions for alternative versions of CPU model. 1966 * List is terminated by item with version == 0. 1967 * If NULL, version 1 will be registered automatically. 1968 */ 1969 const X86CPUVersionDefinition *versions; 1970 const char *deprecation_note; 1971 } X86CPUDefinition; 1972 1973 /* Reference to a specific CPU model version */ 1974 struct X86CPUModel { 1975 /* Base CPU definition */ 1976 const X86CPUDefinition *cpudef; 1977 /* CPU model version */ 1978 X86CPUVersion version; 1979 const char *note; 1980 /* 1981 * If true, this is an alias CPU model. 1982 * This matters only for "-cpu help" and query-cpu-definitions 1983 */ 1984 bool is_alias; 1985 }; 1986 1987 /* Get full model name for CPU version */ 1988 static char *x86_cpu_versioned_model_name(const X86CPUDefinition *cpudef, 1989 X86CPUVersion version) 1990 { 1991 assert(version > 0); 1992 return g_strdup_printf("%s-v%d", cpudef->name, (int)version); 1993 } 1994 1995 static const X86CPUVersionDefinition * 1996 x86_cpu_def_get_versions(const X86CPUDefinition *def) 1997 { 1998 /* When X86CPUDefinition::versions is NULL, we register only v1 */ 1999 static const X86CPUVersionDefinition default_version_list[] = { 2000 { 1 }, 2001 { /* end of list */ } 2002 }; 2003 2004 return def->versions ?: default_version_list; 2005 } 2006 2007 static const CPUCaches epyc_cache_info = { 2008 .l1d_cache = &(CPUCacheInfo) { 2009 .type = DATA_CACHE, 2010 .level = 1, 2011 .size = 32 * KiB, 2012 .line_size = 64, 2013 .associativity = 8, 2014 .partitions = 1, 2015 .sets = 64, 2016 .lines_per_tag = 1, 2017 .self_init = 1, 2018 .no_invd_sharing = true, 2019 .share_level = CPU_TOPO_LEVEL_CORE, 2020 }, 2021 .l1i_cache = &(CPUCacheInfo) { 2022 .type = INSTRUCTION_CACHE, 2023 .level = 1, 2024 .size = 64 * KiB, 2025 .line_size = 64, 2026 .associativity = 4, 2027 .partitions = 1, 2028 .sets = 256, 2029 .lines_per_tag = 1, 2030 .self_init = 1, 2031 .no_invd_sharing = true, 2032 .share_level = CPU_TOPO_LEVEL_CORE, 2033 }, 2034 .l2_cache = &(CPUCacheInfo) { 2035 .type = UNIFIED_CACHE, 2036 .level = 2, 2037 .size = 512 * KiB, 2038 .line_size = 64, 2039 .associativity = 8, 2040 .partitions = 1, 2041 .sets = 1024, 2042 .lines_per_tag = 1, 2043 .share_level = CPU_TOPO_LEVEL_CORE, 2044 }, 2045 .l3_cache = &(CPUCacheInfo) { 2046 .type = UNIFIED_CACHE, 2047 .level = 3, 2048 .size = 8 * MiB, 2049 .line_size = 64, 2050 .associativity = 16, 2051 .partitions = 1, 2052 .sets = 8192, 2053 .lines_per_tag = 1, 2054 .self_init = true, 2055 .inclusive = true, 2056 .complex_indexing = true, 2057 .share_level = CPU_TOPO_LEVEL_DIE, 2058 }, 2059 }; 2060 2061 static CPUCaches epyc_v4_cache_info = { 2062 .l1d_cache = &(CPUCacheInfo) { 2063 .type = DATA_CACHE, 2064 .level = 1, 2065 .size = 32 * KiB, 2066 .line_size = 64, 2067 .associativity = 8, 2068 .partitions = 1, 2069 .sets = 64, 2070 .lines_per_tag = 1, 2071 .self_init = 1, 2072 .no_invd_sharing = true, 2073 .share_level = CPU_TOPO_LEVEL_CORE, 2074 }, 2075 .l1i_cache = &(CPUCacheInfo) { 2076 .type = INSTRUCTION_CACHE, 2077 .level = 1, 2078 .size = 64 * KiB, 2079 .line_size = 64, 2080 .associativity = 4, 2081 .partitions = 1, 2082 .sets = 256, 2083 .lines_per_tag = 1, 2084 .self_init = 1, 2085 .no_invd_sharing = true, 2086 .share_level = CPU_TOPO_LEVEL_CORE, 2087 }, 2088 .l2_cache = &(CPUCacheInfo) { 2089 .type = UNIFIED_CACHE, 2090 .level = 2, 2091 .size = 512 * KiB, 2092 .line_size = 64, 2093 .associativity = 8, 2094 .partitions = 1, 2095 .sets = 1024, 2096 .lines_per_tag = 1, 2097 .share_level = CPU_TOPO_LEVEL_CORE, 2098 }, 2099 .l3_cache = &(CPUCacheInfo) { 2100 .type = UNIFIED_CACHE, 2101 .level = 3, 2102 .size = 8 * MiB, 2103 .line_size = 64, 2104 .associativity = 16, 2105 .partitions = 1, 2106 .sets = 8192, 2107 .lines_per_tag = 1, 2108 .self_init = true, 2109 .inclusive = true, 2110 .complex_indexing = false, 2111 .share_level = CPU_TOPO_LEVEL_DIE, 2112 }, 2113 }; 2114 2115 static const CPUCaches epyc_rome_cache_info = { 2116 .l1d_cache = &(CPUCacheInfo) { 2117 .type = DATA_CACHE, 2118 .level = 1, 2119 .size = 32 * KiB, 2120 .line_size = 64, 2121 .associativity = 8, 2122 .partitions = 1, 2123 .sets = 64, 2124 .lines_per_tag = 1, 2125 .self_init = 1, 2126 .no_invd_sharing = true, 2127 .share_level = CPU_TOPO_LEVEL_CORE, 2128 }, 2129 .l1i_cache = &(CPUCacheInfo) { 2130 .type = INSTRUCTION_CACHE, 2131 .level = 1, 2132 .size = 32 * KiB, 2133 .line_size = 64, 2134 .associativity = 8, 2135 .partitions = 1, 2136 .sets = 64, 2137 .lines_per_tag = 1, 2138 .self_init = 1, 2139 .no_invd_sharing = true, 2140 .share_level = CPU_TOPO_LEVEL_CORE, 2141 }, 2142 .l2_cache = &(CPUCacheInfo) { 2143 .type = UNIFIED_CACHE, 2144 .level = 2, 2145 .size = 512 * KiB, 2146 .line_size = 64, 2147 .associativity = 8, 2148 .partitions = 1, 2149 .sets = 1024, 2150 .lines_per_tag = 1, 2151 .share_level = CPU_TOPO_LEVEL_CORE, 2152 }, 2153 .l3_cache = &(CPUCacheInfo) { 2154 .type = UNIFIED_CACHE, 2155 .level = 3, 2156 .size = 16 * MiB, 2157 .line_size = 64, 2158 .associativity = 16, 2159 .partitions = 1, 2160 .sets = 16384, 2161 .lines_per_tag = 1, 2162 .self_init = true, 2163 .inclusive = true, 2164 .complex_indexing = true, 2165 .share_level = CPU_TOPO_LEVEL_DIE, 2166 }, 2167 }; 2168 2169 static const CPUCaches epyc_rome_v3_cache_info = { 2170 .l1d_cache = &(CPUCacheInfo) { 2171 .type = DATA_CACHE, 2172 .level = 1, 2173 .size = 32 * KiB, 2174 .line_size = 64, 2175 .associativity = 8, 2176 .partitions = 1, 2177 .sets = 64, 2178 .lines_per_tag = 1, 2179 .self_init = 1, 2180 .no_invd_sharing = true, 2181 .share_level = CPU_TOPO_LEVEL_CORE, 2182 }, 2183 .l1i_cache = &(CPUCacheInfo) { 2184 .type = INSTRUCTION_CACHE, 2185 .level = 1, 2186 .size = 32 * KiB, 2187 .line_size = 64, 2188 .associativity = 8, 2189 .partitions = 1, 2190 .sets = 64, 2191 .lines_per_tag = 1, 2192 .self_init = 1, 2193 .no_invd_sharing = true, 2194 .share_level = CPU_TOPO_LEVEL_CORE, 2195 }, 2196 .l2_cache = &(CPUCacheInfo) { 2197 .type = UNIFIED_CACHE, 2198 .level = 2, 2199 .size = 512 * KiB, 2200 .line_size = 64, 2201 .associativity = 8, 2202 .partitions = 1, 2203 .sets = 1024, 2204 .lines_per_tag = 1, 2205 .share_level = CPU_TOPO_LEVEL_CORE, 2206 }, 2207 .l3_cache = &(CPUCacheInfo) { 2208 .type = UNIFIED_CACHE, 2209 .level = 3, 2210 .size = 16 * MiB, 2211 .line_size = 64, 2212 .associativity = 16, 2213 .partitions = 1, 2214 .sets = 16384, 2215 .lines_per_tag = 1, 2216 .self_init = true, 2217 .inclusive = true, 2218 .complex_indexing = false, 2219 .share_level = CPU_TOPO_LEVEL_DIE, 2220 }, 2221 }; 2222 2223 static const CPUCaches epyc_milan_cache_info = { 2224 .l1d_cache = &(CPUCacheInfo) { 2225 .type = DATA_CACHE, 2226 .level = 1, 2227 .size = 32 * KiB, 2228 .line_size = 64, 2229 .associativity = 8, 2230 .partitions = 1, 2231 .sets = 64, 2232 .lines_per_tag = 1, 2233 .self_init = 1, 2234 .no_invd_sharing = true, 2235 .share_level = CPU_TOPO_LEVEL_CORE, 2236 }, 2237 .l1i_cache = &(CPUCacheInfo) { 2238 .type = INSTRUCTION_CACHE, 2239 .level = 1, 2240 .size = 32 * KiB, 2241 .line_size = 64, 2242 .associativity = 8, 2243 .partitions = 1, 2244 .sets = 64, 2245 .lines_per_tag = 1, 2246 .self_init = 1, 2247 .no_invd_sharing = true, 2248 .share_level = CPU_TOPO_LEVEL_CORE, 2249 }, 2250 .l2_cache = &(CPUCacheInfo) { 2251 .type = UNIFIED_CACHE, 2252 .level = 2, 2253 .size = 512 * KiB, 2254 .line_size = 64, 2255 .associativity = 8, 2256 .partitions = 1, 2257 .sets = 1024, 2258 .lines_per_tag = 1, 2259 .share_level = CPU_TOPO_LEVEL_CORE, 2260 }, 2261 .l3_cache = &(CPUCacheInfo) { 2262 .type = UNIFIED_CACHE, 2263 .level = 3, 2264 .size = 32 * MiB, 2265 .line_size = 64, 2266 .associativity = 16, 2267 .partitions = 1, 2268 .sets = 32768, 2269 .lines_per_tag = 1, 2270 .self_init = true, 2271 .inclusive = true, 2272 .complex_indexing = true, 2273 .share_level = CPU_TOPO_LEVEL_DIE, 2274 }, 2275 }; 2276 2277 static const CPUCaches epyc_milan_v2_cache_info = { 2278 .l1d_cache = &(CPUCacheInfo) { 2279 .type = DATA_CACHE, 2280 .level = 1, 2281 .size = 32 * KiB, 2282 .line_size = 64, 2283 .associativity = 8, 2284 .partitions = 1, 2285 .sets = 64, 2286 .lines_per_tag = 1, 2287 .self_init = 1, 2288 .no_invd_sharing = true, 2289 .share_level = CPU_TOPO_LEVEL_CORE, 2290 }, 2291 .l1i_cache = &(CPUCacheInfo) { 2292 .type = INSTRUCTION_CACHE, 2293 .level = 1, 2294 .size = 32 * KiB, 2295 .line_size = 64, 2296 .associativity = 8, 2297 .partitions = 1, 2298 .sets = 64, 2299 .lines_per_tag = 1, 2300 .self_init = 1, 2301 .no_invd_sharing = true, 2302 .share_level = CPU_TOPO_LEVEL_CORE, 2303 }, 2304 .l2_cache = &(CPUCacheInfo) { 2305 .type = UNIFIED_CACHE, 2306 .level = 2, 2307 .size = 512 * KiB, 2308 .line_size = 64, 2309 .associativity = 8, 2310 .partitions = 1, 2311 .sets = 1024, 2312 .lines_per_tag = 1, 2313 .share_level = CPU_TOPO_LEVEL_CORE, 2314 }, 2315 .l3_cache = &(CPUCacheInfo) { 2316 .type = UNIFIED_CACHE, 2317 .level = 3, 2318 .size = 32 * MiB, 2319 .line_size = 64, 2320 .associativity = 16, 2321 .partitions = 1, 2322 .sets = 32768, 2323 .lines_per_tag = 1, 2324 .self_init = true, 2325 .inclusive = true, 2326 .complex_indexing = false, 2327 .share_level = CPU_TOPO_LEVEL_DIE, 2328 }, 2329 }; 2330 2331 static const CPUCaches epyc_genoa_cache_info = { 2332 .l1d_cache = &(CPUCacheInfo) { 2333 .type = DATA_CACHE, 2334 .level = 1, 2335 .size = 32 * KiB, 2336 .line_size = 64, 2337 .associativity = 8, 2338 .partitions = 1, 2339 .sets = 64, 2340 .lines_per_tag = 1, 2341 .self_init = 1, 2342 .no_invd_sharing = true, 2343 .share_level = CPU_TOPO_LEVEL_CORE, 2344 }, 2345 .l1i_cache = &(CPUCacheInfo) { 2346 .type = INSTRUCTION_CACHE, 2347 .level = 1, 2348 .size = 32 * KiB, 2349 .line_size = 64, 2350 .associativity = 8, 2351 .partitions = 1, 2352 .sets = 64, 2353 .lines_per_tag = 1, 2354 .self_init = 1, 2355 .no_invd_sharing = true, 2356 .share_level = CPU_TOPO_LEVEL_CORE, 2357 }, 2358 .l2_cache = &(CPUCacheInfo) { 2359 .type = UNIFIED_CACHE, 2360 .level = 2, 2361 .size = 1 * MiB, 2362 .line_size = 64, 2363 .associativity = 8, 2364 .partitions = 1, 2365 .sets = 2048, 2366 .lines_per_tag = 1, 2367 .share_level = CPU_TOPO_LEVEL_CORE, 2368 }, 2369 .l3_cache = &(CPUCacheInfo) { 2370 .type = UNIFIED_CACHE, 2371 .level = 3, 2372 .size = 32 * MiB, 2373 .line_size = 64, 2374 .associativity = 16, 2375 .partitions = 1, 2376 .sets = 32768, 2377 .lines_per_tag = 1, 2378 .self_init = true, 2379 .inclusive = true, 2380 .complex_indexing = false, 2381 .share_level = CPU_TOPO_LEVEL_DIE, 2382 }, 2383 }; 2384 2385 /* The following VMX features are not supported by KVM and are left out in the 2386 * CPU definitions: 2387 * 2388 * Dual-monitor support (all processors) 2389 * Entry to SMM 2390 * Deactivate dual-monitor treatment 2391 * Number of CR3-target values 2392 * Shutdown activity state 2393 * Wait-for-SIPI activity state 2394 * PAUSE-loop exiting (Westmere and newer) 2395 * EPT-violation #VE (Broadwell and newer) 2396 * Inject event with insn length=0 (Skylake and newer) 2397 * Conceal non-root operation from PT 2398 * Conceal VM exits from PT 2399 * Conceal VM entries from PT 2400 * Enable ENCLS exiting 2401 * Mode-based execute control (XS/XU) 2402 * TSC scaling (Skylake Server and newer) 2403 * GPA translation for PT (IceLake and newer) 2404 * User wait and pause 2405 * ENCLV exiting 2406 * Load IA32_RTIT_CTL 2407 * Clear IA32_RTIT_CTL 2408 * Advanced VM-exit information for EPT violations 2409 * Sub-page write permissions 2410 * PT in VMX operation 2411 */ 2412 2413 static const X86CPUDefinition builtin_x86_defs[] = { 2414 { 2415 .name = "qemu64", 2416 .level = 0xd, 2417 .vendor = CPUID_VENDOR_AMD, 2418 .family = 15, 2419 .model = 107, 2420 .stepping = 1, 2421 .features[FEAT_1_EDX] = 2422 PPRO_FEATURES | 2423 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2424 CPUID_PSE36, 2425 .features[FEAT_1_ECX] = 2426 CPUID_EXT_SSE3 | CPUID_EXT_CX16, 2427 .features[FEAT_8000_0001_EDX] = 2428 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2429 .features[FEAT_8000_0001_ECX] = 2430 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM, 2431 .xlevel = 0x8000000A, 2432 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 2433 }, 2434 { 2435 .name = "phenom", 2436 .level = 5, 2437 .vendor = CPUID_VENDOR_AMD, 2438 .family = 16, 2439 .model = 2, 2440 .stepping = 3, 2441 /* Missing: CPUID_HT */ 2442 .features[FEAT_1_EDX] = 2443 PPRO_FEATURES | 2444 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2445 CPUID_PSE36 | CPUID_VME, 2446 .features[FEAT_1_ECX] = 2447 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 | 2448 CPUID_EXT_POPCNT, 2449 .features[FEAT_8000_0001_EDX] = 2450 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | 2451 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT | 2452 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP, 2453 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, 2454 CPUID_EXT3_CR8LEG, 2455 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, 2456 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */ 2457 .features[FEAT_8000_0001_ECX] = 2458 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | 2459 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A, 2460 /* Missing: CPUID_SVM_LBRV */ 2461 .features[FEAT_SVM] = 2462 CPUID_SVM_NPT, 2463 .xlevel = 0x8000001A, 2464 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor" 2465 }, 2466 { 2467 .name = "core2duo", 2468 .level = 10, 2469 .vendor = CPUID_VENDOR_INTEL, 2470 .family = 6, 2471 .model = 15, 2472 .stepping = 11, 2473 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2474 .features[FEAT_1_EDX] = 2475 PPRO_FEATURES | 2476 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2477 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS, 2478 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST, 2479 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */ 2480 .features[FEAT_1_ECX] = 2481 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | 2482 CPUID_EXT_CX16, 2483 .features[FEAT_8000_0001_EDX] = 2484 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2485 .features[FEAT_8000_0001_ECX] = 2486 CPUID_EXT3_LAHF_LM, 2487 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2488 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2489 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2490 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2491 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2492 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2493 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2494 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2495 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2496 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2497 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2498 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2499 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2500 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2501 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2502 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2503 .features[FEAT_VMX_SECONDARY_CTLS] = 2504 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES, 2505 .xlevel = 0x80000008, 2506 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz", 2507 }, 2508 { 2509 .name = "kvm64", 2510 .level = 0xd, 2511 .vendor = CPUID_VENDOR_INTEL, 2512 .family = 15, 2513 .model = 6, 2514 .stepping = 1, 2515 /* Missing: CPUID_HT */ 2516 .features[FEAT_1_EDX] = 2517 PPRO_FEATURES | CPUID_VME | 2518 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2519 CPUID_PSE36, 2520 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */ 2521 .features[FEAT_1_ECX] = 2522 CPUID_EXT_SSE3 | CPUID_EXT_CX16, 2523 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */ 2524 .features[FEAT_8000_0001_EDX] = 2525 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2526 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, 2527 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A, 2528 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, 2529 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */ 2530 .features[FEAT_8000_0001_ECX] = 2531 0, 2532 /* VMX features from Cedar Mill/Prescott */ 2533 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2534 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2535 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2536 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2537 VMX_PIN_BASED_NMI_EXITING, 2538 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2539 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2540 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2541 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2542 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2543 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2544 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2545 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING, 2546 .xlevel = 0x80000008, 2547 .model_id = "Common KVM processor" 2548 }, 2549 { 2550 .name = "qemu32", 2551 .level = 4, 2552 .vendor = CPUID_VENDOR_INTEL, 2553 .family = 6, 2554 .model = 6, 2555 .stepping = 3, 2556 .features[FEAT_1_EDX] = 2557 PPRO_FEATURES, 2558 .features[FEAT_1_ECX] = 2559 CPUID_EXT_SSE3, 2560 .xlevel = 0x80000004, 2561 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 2562 }, 2563 { 2564 .name = "kvm32", 2565 .level = 5, 2566 .vendor = CPUID_VENDOR_INTEL, 2567 .family = 15, 2568 .model = 6, 2569 .stepping = 1, 2570 .features[FEAT_1_EDX] = 2571 PPRO_FEATURES | CPUID_VME | 2572 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36, 2573 .features[FEAT_1_ECX] = 2574 CPUID_EXT_SSE3, 2575 .features[FEAT_8000_0001_ECX] = 2576 0, 2577 /* VMX features from Yonah */ 2578 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2579 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2580 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2581 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2582 VMX_PIN_BASED_NMI_EXITING, 2583 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2584 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2585 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2586 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2587 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 2588 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 2589 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS, 2590 .xlevel = 0x80000008, 2591 .model_id = "Common 32-bit KVM processor" 2592 }, 2593 { 2594 .name = "coreduo", 2595 .level = 10, 2596 .vendor = CPUID_VENDOR_INTEL, 2597 .family = 6, 2598 .model = 14, 2599 .stepping = 8, 2600 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2601 .features[FEAT_1_EDX] = 2602 PPRO_FEATURES | CPUID_VME | 2603 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI | 2604 CPUID_SS, 2605 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR, 2606 * CPUID_EXT_PDCM, CPUID_EXT_VMX */ 2607 .features[FEAT_1_ECX] = 2608 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR, 2609 .features[FEAT_8000_0001_EDX] = 2610 CPUID_EXT2_NX, 2611 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2612 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2613 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2614 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2615 VMX_PIN_BASED_NMI_EXITING, 2616 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2617 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2618 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2619 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2620 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 2621 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 2622 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS, 2623 .xlevel = 0x80000008, 2624 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz", 2625 }, 2626 { 2627 .name = "486", 2628 .level = 1, 2629 .vendor = CPUID_VENDOR_INTEL, 2630 .family = 4, 2631 .model = 8, 2632 .stepping = 0, 2633 .features[FEAT_1_EDX] = 2634 I486_FEATURES, 2635 .xlevel = 0, 2636 .model_id = "", 2637 }, 2638 { 2639 .name = "pentium", 2640 .level = 1, 2641 .vendor = CPUID_VENDOR_INTEL, 2642 .family = 5, 2643 .model = 4, 2644 .stepping = 3, 2645 .features[FEAT_1_EDX] = 2646 PENTIUM_FEATURES, 2647 .xlevel = 0, 2648 .model_id = "", 2649 }, 2650 { 2651 .name = "pentium2", 2652 .level = 2, 2653 .vendor = CPUID_VENDOR_INTEL, 2654 .family = 6, 2655 .model = 5, 2656 .stepping = 2, 2657 .features[FEAT_1_EDX] = 2658 PENTIUM2_FEATURES, 2659 .xlevel = 0, 2660 .model_id = "", 2661 }, 2662 { 2663 .name = "pentium3", 2664 .level = 3, 2665 .vendor = CPUID_VENDOR_INTEL, 2666 .family = 6, 2667 .model = 7, 2668 .stepping = 3, 2669 .features[FEAT_1_EDX] = 2670 PENTIUM3_FEATURES, 2671 .xlevel = 0, 2672 .model_id = "", 2673 }, 2674 { 2675 .name = "athlon", 2676 .level = 2, 2677 .vendor = CPUID_VENDOR_AMD, 2678 .family = 6, 2679 .model = 2, 2680 .stepping = 3, 2681 .features[FEAT_1_EDX] = 2682 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR | 2683 CPUID_MCA, 2684 .features[FEAT_8000_0001_EDX] = 2685 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT, 2686 .xlevel = 0x80000008, 2687 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 2688 }, 2689 { 2690 .name = "n270", 2691 .level = 10, 2692 .vendor = CPUID_VENDOR_INTEL, 2693 .family = 6, 2694 .model = 28, 2695 .stepping = 2, 2696 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2697 .features[FEAT_1_EDX] = 2698 PPRO_FEATURES | 2699 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | 2700 CPUID_ACPI | CPUID_SS, 2701 /* Some CPUs got no CPUID_SEP */ 2702 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2, 2703 * CPUID_EXT_XTPR */ 2704 .features[FEAT_1_ECX] = 2705 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | 2706 CPUID_EXT_MOVBE, 2707 .features[FEAT_8000_0001_EDX] = 2708 CPUID_EXT2_NX, 2709 .features[FEAT_8000_0001_ECX] = 2710 CPUID_EXT3_LAHF_LM, 2711 .xlevel = 0x80000008, 2712 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz", 2713 }, 2714 { 2715 .name = "Conroe", 2716 .level = 10, 2717 .vendor = CPUID_VENDOR_INTEL, 2718 .family = 6, 2719 .model = 15, 2720 .stepping = 3, 2721 .features[FEAT_1_EDX] = 2722 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2723 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2724 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2725 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2726 CPUID_DE | CPUID_FP87, 2727 .features[FEAT_1_ECX] = 2728 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, 2729 .features[FEAT_8000_0001_EDX] = 2730 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 2731 .features[FEAT_8000_0001_ECX] = 2732 CPUID_EXT3_LAHF_LM, 2733 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2734 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2735 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2736 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2737 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2738 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2739 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2740 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2741 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2742 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2743 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2744 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2745 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2746 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2747 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2748 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2749 .features[FEAT_VMX_SECONDARY_CTLS] = 2750 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES, 2751 .xlevel = 0x80000008, 2752 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)", 2753 }, 2754 { 2755 .name = "Penryn", 2756 .level = 10, 2757 .vendor = CPUID_VENDOR_INTEL, 2758 .family = 6, 2759 .model = 23, 2760 .stepping = 3, 2761 .features[FEAT_1_EDX] = 2762 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2763 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2764 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2765 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2766 CPUID_DE | CPUID_FP87, 2767 .features[FEAT_1_ECX] = 2768 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2769 CPUID_EXT_SSE3, 2770 .features[FEAT_8000_0001_EDX] = 2771 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 2772 .features[FEAT_8000_0001_ECX] = 2773 CPUID_EXT3_LAHF_LM, 2774 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2775 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2776 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, 2777 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT | 2778 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL, 2779 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2780 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2781 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2782 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2783 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2784 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2785 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2786 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2787 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2788 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2789 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2790 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2791 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2792 .features[FEAT_VMX_SECONDARY_CTLS] = 2793 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2794 VMX_SECONDARY_EXEC_WBINVD_EXITING, 2795 .xlevel = 0x80000008, 2796 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)", 2797 }, 2798 { 2799 .name = "Nehalem", 2800 .level = 11, 2801 .vendor = CPUID_VENDOR_INTEL, 2802 .family = 6, 2803 .model = 26, 2804 .stepping = 3, 2805 .features[FEAT_1_EDX] = 2806 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2807 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2808 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2809 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2810 CPUID_DE | CPUID_FP87, 2811 .features[FEAT_1_ECX] = 2812 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 2813 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, 2814 .features[FEAT_8000_0001_EDX] = 2815 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2816 .features[FEAT_8000_0001_ECX] = 2817 CPUID_EXT3_LAHF_LM, 2818 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2819 MSR_VMX_BASIC_TRUE_CTLS, 2820 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2821 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2822 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2823 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2824 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2825 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2826 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2827 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2828 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2829 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2830 .features[FEAT_VMX_EXIT_CTLS] = 2831 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2832 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2833 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2834 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2835 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2836 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2837 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2838 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2839 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2840 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2841 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2842 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2843 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2844 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2845 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2846 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2847 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2848 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2849 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2850 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2851 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2852 .features[FEAT_VMX_SECONDARY_CTLS] = 2853 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2854 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2855 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2856 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2857 VMX_SECONDARY_EXEC_ENABLE_VPID, 2858 .xlevel = 0x80000008, 2859 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)", 2860 .versions = (X86CPUVersionDefinition[]) { 2861 { .version = 1 }, 2862 { 2863 .version = 2, 2864 .alias = "Nehalem-IBRS", 2865 .props = (PropValue[]) { 2866 { "spec-ctrl", "on" }, 2867 { "model-id", 2868 "Intel Core i7 9xx (Nehalem Core i7, IBRS update)" }, 2869 { /* end of list */ } 2870 } 2871 }, 2872 { /* end of list */ } 2873 } 2874 }, 2875 { 2876 .name = "Westmere", 2877 .level = 11, 2878 .vendor = CPUID_VENDOR_INTEL, 2879 .family = 6, 2880 .model = 44, 2881 .stepping = 1, 2882 .features[FEAT_1_EDX] = 2883 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2884 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2885 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2886 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2887 CPUID_DE | CPUID_FP87, 2888 .features[FEAT_1_ECX] = 2889 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | 2890 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2891 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 2892 .features[FEAT_8000_0001_EDX] = 2893 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2894 .features[FEAT_8000_0001_ECX] = 2895 CPUID_EXT3_LAHF_LM, 2896 .features[FEAT_6_EAX] = 2897 CPUID_6_EAX_ARAT, 2898 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2899 MSR_VMX_BASIC_TRUE_CTLS, 2900 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2901 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2902 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2903 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2904 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2905 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2906 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2907 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2908 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2909 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2910 .features[FEAT_VMX_EXIT_CTLS] = 2911 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2912 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2913 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2914 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2915 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2916 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2917 MSR_VMX_MISC_STORE_LMA, 2918 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2919 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2920 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2921 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2922 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2923 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2924 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2925 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2926 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2927 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2928 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2929 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2930 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2931 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2932 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2933 .features[FEAT_VMX_SECONDARY_CTLS] = 2934 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2935 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2936 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2937 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2938 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST, 2939 .xlevel = 0x80000008, 2940 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)", 2941 .versions = (X86CPUVersionDefinition[]) { 2942 { .version = 1 }, 2943 { 2944 .version = 2, 2945 .alias = "Westmere-IBRS", 2946 .props = (PropValue[]) { 2947 { "spec-ctrl", "on" }, 2948 { "model-id", 2949 "Westmere E56xx/L56xx/X56xx (IBRS update)" }, 2950 { /* end of list */ } 2951 } 2952 }, 2953 { /* end of list */ } 2954 } 2955 }, 2956 { 2957 .name = "SandyBridge", 2958 .level = 0xd, 2959 .vendor = CPUID_VENDOR_INTEL, 2960 .family = 6, 2961 .model = 42, 2962 .stepping = 1, 2963 .features[FEAT_1_EDX] = 2964 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2965 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2966 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2967 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2968 CPUID_DE | CPUID_FP87, 2969 .features[FEAT_1_ECX] = 2970 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2971 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | 2972 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 2973 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 2974 CPUID_EXT_SSE3, 2975 .features[FEAT_8000_0001_EDX] = 2976 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 2977 CPUID_EXT2_SYSCALL, 2978 .features[FEAT_8000_0001_ECX] = 2979 CPUID_EXT3_LAHF_LM, 2980 .features[FEAT_XSAVE] = 2981 CPUID_XSAVE_XSAVEOPT, 2982 .features[FEAT_6_EAX] = 2983 CPUID_6_EAX_ARAT, 2984 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2985 MSR_VMX_BASIC_TRUE_CTLS, 2986 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2987 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2988 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2989 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2990 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2991 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2992 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2993 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2994 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2995 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2996 .features[FEAT_VMX_EXIT_CTLS] = 2997 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2998 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2999 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3000 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3001 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3002 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3003 MSR_VMX_MISC_STORE_LMA, 3004 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3005 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3006 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 3007 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3008 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3009 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3010 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3011 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3012 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3013 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3014 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3015 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3016 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3017 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3018 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3019 .features[FEAT_VMX_SECONDARY_CTLS] = 3020 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3021 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3022 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3023 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3024 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST, 3025 .xlevel = 0x80000008, 3026 .model_id = "Intel Xeon E312xx (Sandy Bridge)", 3027 .versions = (X86CPUVersionDefinition[]) { 3028 { .version = 1 }, 3029 { 3030 .version = 2, 3031 .alias = "SandyBridge-IBRS", 3032 .props = (PropValue[]) { 3033 { "spec-ctrl", "on" }, 3034 { "model-id", 3035 "Intel Xeon E312xx (Sandy Bridge, IBRS update)" }, 3036 { /* end of list */ } 3037 } 3038 }, 3039 { /* end of list */ } 3040 } 3041 }, 3042 { 3043 .name = "IvyBridge", 3044 .level = 0xd, 3045 .vendor = CPUID_VENDOR_INTEL, 3046 .family = 6, 3047 .model = 58, 3048 .stepping = 9, 3049 .features[FEAT_1_EDX] = 3050 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3051 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3052 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3053 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3054 CPUID_DE | CPUID_FP87, 3055 .features[FEAT_1_ECX] = 3056 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3057 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | 3058 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 3059 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 3060 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3061 .features[FEAT_7_0_EBX] = 3062 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | 3063 CPUID_7_0_EBX_ERMS, 3064 .features[FEAT_8000_0001_EDX] = 3065 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3066 CPUID_EXT2_SYSCALL, 3067 .features[FEAT_8000_0001_ECX] = 3068 CPUID_EXT3_LAHF_LM, 3069 .features[FEAT_XSAVE] = 3070 CPUID_XSAVE_XSAVEOPT, 3071 .features[FEAT_6_EAX] = 3072 CPUID_6_EAX_ARAT, 3073 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3074 MSR_VMX_BASIC_TRUE_CTLS, 3075 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3076 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3077 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3078 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3079 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3080 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3081 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3082 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3083 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3084 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 3085 .features[FEAT_VMX_EXIT_CTLS] = 3086 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3087 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3088 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3089 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3090 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3091 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3092 MSR_VMX_MISC_STORE_LMA, 3093 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3094 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3095 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3096 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3097 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3098 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3099 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3100 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3101 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3102 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3103 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3104 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3105 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3106 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3107 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3108 .features[FEAT_VMX_SECONDARY_CTLS] = 3109 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3110 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3111 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3112 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3113 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3114 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3115 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3116 VMX_SECONDARY_EXEC_RDRAND_EXITING, 3117 .xlevel = 0x80000008, 3118 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)", 3119 .versions = (X86CPUVersionDefinition[]) { 3120 { .version = 1 }, 3121 { 3122 .version = 2, 3123 .alias = "IvyBridge-IBRS", 3124 .props = (PropValue[]) { 3125 { "spec-ctrl", "on" }, 3126 { "model-id", 3127 "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)" }, 3128 { /* end of list */ } 3129 } 3130 }, 3131 { /* end of list */ } 3132 } 3133 }, 3134 { 3135 .name = "Haswell", 3136 .level = 0xd, 3137 .vendor = CPUID_VENDOR_INTEL, 3138 .family = 6, 3139 .model = 60, 3140 .stepping = 4, 3141 .features[FEAT_1_EDX] = 3142 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3143 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3144 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3145 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3146 CPUID_DE | CPUID_FP87, 3147 .features[FEAT_1_ECX] = 3148 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3149 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3150 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3151 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3152 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3153 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3154 .features[FEAT_8000_0001_EDX] = 3155 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3156 CPUID_EXT2_SYSCALL, 3157 .features[FEAT_8000_0001_ECX] = 3158 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM, 3159 .features[FEAT_7_0_EBX] = 3160 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3161 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3162 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3163 CPUID_7_0_EBX_RTM, 3164 .features[FEAT_XSAVE] = 3165 CPUID_XSAVE_XSAVEOPT, 3166 .features[FEAT_6_EAX] = 3167 CPUID_6_EAX_ARAT, 3168 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3169 MSR_VMX_BASIC_TRUE_CTLS, 3170 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3171 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3172 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3173 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3174 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3175 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3176 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3177 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3178 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3179 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3180 .features[FEAT_VMX_EXIT_CTLS] = 3181 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3182 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3183 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3184 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3185 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3186 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3187 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3188 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3189 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3190 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3191 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3192 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3193 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3194 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3195 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3196 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3197 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3198 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3199 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3200 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3201 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3202 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3203 .features[FEAT_VMX_SECONDARY_CTLS] = 3204 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3205 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3206 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3207 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3208 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3209 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3210 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3211 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3212 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS, 3213 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3214 .xlevel = 0x80000008, 3215 .model_id = "Intel Core Processor (Haswell)", 3216 .versions = (X86CPUVersionDefinition[]) { 3217 { .version = 1 }, 3218 { 3219 .version = 2, 3220 .alias = "Haswell-noTSX", 3221 .props = (PropValue[]) { 3222 { "hle", "off" }, 3223 { "rtm", "off" }, 3224 { "stepping", "1" }, 3225 { "model-id", "Intel Core Processor (Haswell, no TSX)", }, 3226 { /* end of list */ } 3227 }, 3228 }, 3229 { 3230 .version = 3, 3231 .alias = "Haswell-IBRS", 3232 .props = (PropValue[]) { 3233 /* Restore TSX features removed by -v2 above */ 3234 { "hle", "on" }, 3235 { "rtm", "on" }, 3236 /* 3237 * Haswell and Haswell-IBRS had stepping=4 in 3238 * QEMU 4.0 and older 3239 */ 3240 { "stepping", "4" }, 3241 { "spec-ctrl", "on" }, 3242 { "model-id", 3243 "Intel Core Processor (Haswell, IBRS)" }, 3244 { /* end of list */ } 3245 } 3246 }, 3247 { 3248 .version = 4, 3249 .alias = "Haswell-noTSX-IBRS", 3250 .props = (PropValue[]) { 3251 { "hle", "off" }, 3252 { "rtm", "off" }, 3253 /* spec-ctrl was already enabled by -v3 above */ 3254 { "stepping", "1" }, 3255 { "model-id", 3256 "Intel Core Processor (Haswell, no TSX, IBRS)" }, 3257 { /* end of list */ } 3258 } 3259 }, 3260 { /* end of list */ } 3261 } 3262 }, 3263 { 3264 .name = "Broadwell", 3265 .level = 0xd, 3266 .vendor = CPUID_VENDOR_INTEL, 3267 .family = 6, 3268 .model = 61, 3269 .stepping = 2, 3270 .features[FEAT_1_EDX] = 3271 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3272 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3273 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3274 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3275 CPUID_DE | CPUID_FP87, 3276 .features[FEAT_1_ECX] = 3277 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3278 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3279 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3280 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3281 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3282 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3283 .features[FEAT_8000_0001_EDX] = 3284 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3285 CPUID_EXT2_SYSCALL, 3286 .features[FEAT_8000_0001_ECX] = 3287 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3288 .features[FEAT_7_0_EBX] = 3289 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3290 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3291 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3292 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3293 CPUID_7_0_EBX_SMAP, 3294 .features[FEAT_XSAVE] = 3295 CPUID_XSAVE_XSAVEOPT, 3296 .features[FEAT_6_EAX] = 3297 CPUID_6_EAX_ARAT, 3298 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3299 MSR_VMX_BASIC_TRUE_CTLS, 3300 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3301 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3302 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3303 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3304 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3305 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3306 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3307 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3308 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3309 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3310 .features[FEAT_VMX_EXIT_CTLS] = 3311 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3312 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3313 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3314 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3315 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3316 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3317 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3318 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3319 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3320 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3321 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3322 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3323 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3324 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3325 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3326 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3327 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3328 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3329 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3330 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3331 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3332 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3333 .features[FEAT_VMX_SECONDARY_CTLS] = 3334 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3335 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3336 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3337 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3338 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3339 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3340 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3341 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3342 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3343 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3344 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3345 .xlevel = 0x80000008, 3346 .model_id = "Intel Core Processor (Broadwell)", 3347 .versions = (X86CPUVersionDefinition[]) { 3348 { .version = 1 }, 3349 { 3350 .version = 2, 3351 .alias = "Broadwell-noTSX", 3352 .props = (PropValue[]) { 3353 { "hle", "off" }, 3354 { "rtm", "off" }, 3355 { "model-id", "Intel Core Processor (Broadwell, no TSX)", }, 3356 { /* end of list */ } 3357 }, 3358 }, 3359 { 3360 .version = 3, 3361 .alias = "Broadwell-IBRS", 3362 .props = (PropValue[]) { 3363 /* Restore TSX features removed by -v2 above */ 3364 { "hle", "on" }, 3365 { "rtm", "on" }, 3366 { "spec-ctrl", "on" }, 3367 { "model-id", 3368 "Intel Core Processor (Broadwell, IBRS)" }, 3369 { /* end of list */ } 3370 } 3371 }, 3372 { 3373 .version = 4, 3374 .alias = "Broadwell-noTSX-IBRS", 3375 .props = (PropValue[]) { 3376 { "hle", "off" }, 3377 { "rtm", "off" }, 3378 /* spec-ctrl was already enabled by -v3 above */ 3379 { "model-id", 3380 "Intel Core Processor (Broadwell, no TSX, IBRS)" }, 3381 { /* end of list */ } 3382 } 3383 }, 3384 { /* end of list */ } 3385 } 3386 }, 3387 { 3388 .name = "Skylake-Client", 3389 .level = 0xd, 3390 .vendor = CPUID_VENDOR_INTEL, 3391 .family = 6, 3392 .model = 94, 3393 .stepping = 3, 3394 .features[FEAT_1_EDX] = 3395 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3396 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3397 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3398 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3399 CPUID_DE | CPUID_FP87, 3400 .features[FEAT_1_ECX] = 3401 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3402 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3403 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3404 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3405 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3406 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3407 .features[FEAT_8000_0001_EDX] = 3408 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3409 CPUID_EXT2_SYSCALL, 3410 .features[FEAT_8000_0001_ECX] = 3411 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3412 .features[FEAT_7_0_EBX] = 3413 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3414 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3415 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3416 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3417 CPUID_7_0_EBX_SMAP, 3418 /* XSAVES is added in version 4 */ 3419 .features[FEAT_XSAVE] = 3420 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3421 CPUID_XSAVE_XGETBV1, 3422 .features[FEAT_6_EAX] = 3423 CPUID_6_EAX_ARAT, 3424 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3425 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3426 MSR_VMX_BASIC_TRUE_CTLS, 3427 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3428 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3429 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3430 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3431 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3432 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3433 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3434 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3435 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3436 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3437 .features[FEAT_VMX_EXIT_CTLS] = 3438 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3439 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3440 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3441 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3442 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3443 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3444 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3445 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3446 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3447 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 3448 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3449 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3450 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3451 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3452 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3453 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3454 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3455 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3456 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3457 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3458 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3459 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3460 .features[FEAT_VMX_SECONDARY_CTLS] = 3461 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3462 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3463 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3464 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3465 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3466 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3467 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3468 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3469 .xlevel = 0x80000008, 3470 .model_id = "Intel Core Processor (Skylake)", 3471 .versions = (X86CPUVersionDefinition[]) { 3472 { .version = 1 }, 3473 { 3474 .version = 2, 3475 .alias = "Skylake-Client-IBRS", 3476 .props = (PropValue[]) { 3477 { "spec-ctrl", "on" }, 3478 { "model-id", 3479 "Intel Core Processor (Skylake, IBRS)" }, 3480 { /* end of list */ } 3481 } 3482 }, 3483 { 3484 .version = 3, 3485 .alias = "Skylake-Client-noTSX-IBRS", 3486 .props = (PropValue[]) { 3487 { "hle", "off" }, 3488 { "rtm", "off" }, 3489 { "model-id", 3490 "Intel Core Processor (Skylake, IBRS, no TSX)" }, 3491 { /* end of list */ } 3492 } 3493 }, 3494 { 3495 .version = 4, 3496 .note = "IBRS, XSAVES, no TSX", 3497 .props = (PropValue[]) { 3498 { "xsaves", "on" }, 3499 { "vmx-xsaves", "on" }, 3500 { /* end of list */ } 3501 } 3502 }, 3503 { /* end of list */ } 3504 } 3505 }, 3506 { 3507 .name = "Skylake-Server", 3508 .level = 0xd, 3509 .vendor = CPUID_VENDOR_INTEL, 3510 .family = 6, 3511 .model = 85, 3512 .stepping = 4, 3513 .features[FEAT_1_EDX] = 3514 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3515 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3516 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3517 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3518 CPUID_DE | CPUID_FP87, 3519 .features[FEAT_1_ECX] = 3520 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3521 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3522 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3523 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3524 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3525 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3526 .features[FEAT_8000_0001_EDX] = 3527 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3528 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3529 .features[FEAT_8000_0001_ECX] = 3530 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3531 .features[FEAT_7_0_EBX] = 3532 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3533 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3534 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3535 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3536 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3537 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3538 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3539 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3540 .features[FEAT_7_0_ECX] = 3541 CPUID_7_0_ECX_PKU, 3542 /* XSAVES is added in version 5 */ 3543 .features[FEAT_XSAVE] = 3544 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3545 CPUID_XSAVE_XGETBV1, 3546 .features[FEAT_6_EAX] = 3547 CPUID_6_EAX_ARAT, 3548 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3549 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3550 MSR_VMX_BASIC_TRUE_CTLS, 3551 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3552 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3553 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3554 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3555 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3556 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3557 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3558 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3559 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3560 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3561 .features[FEAT_VMX_EXIT_CTLS] = 3562 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3563 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3564 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3565 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3566 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3567 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3568 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3569 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3570 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3571 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3572 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3573 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3574 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3575 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3576 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3577 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3578 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3579 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3580 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3581 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3582 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3583 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3584 .features[FEAT_VMX_SECONDARY_CTLS] = 3585 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3586 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3587 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3588 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3589 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3590 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3591 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3592 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3593 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3594 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3595 .xlevel = 0x80000008, 3596 .model_id = "Intel Xeon Processor (Skylake)", 3597 .versions = (X86CPUVersionDefinition[]) { 3598 { .version = 1 }, 3599 { 3600 .version = 2, 3601 .alias = "Skylake-Server-IBRS", 3602 .props = (PropValue[]) { 3603 /* clflushopt was not added to Skylake-Server-IBRS */ 3604 /* TODO: add -v3 including clflushopt */ 3605 { "clflushopt", "off" }, 3606 { "spec-ctrl", "on" }, 3607 { "model-id", 3608 "Intel Xeon Processor (Skylake, IBRS)" }, 3609 { /* end of list */ } 3610 } 3611 }, 3612 { 3613 .version = 3, 3614 .alias = "Skylake-Server-noTSX-IBRS", 3615 .props = (PropValue[]) { 3616 { "hle", "off" }, 3617 { "rtm", "off" }, 3618 { "model-id", 3619 "Intel Xeon Processor (Skylake, IBRS, no TSX)" }, 3620 { /* end of list */ } 3621 } 3622 }, 3623 { 3624 .version = 4, 3625 .props = (PropValue[]) { 3626 { "vmx-eptp-switching", "on" }, 3627 { /* end of list */ } 3628 } 3629 }, 3630 { 3631 .version = 5, 3632 .note = "IBRS, XSAVES, EPT switching, no TSX", 3633 .props = (PropValue[]) { 3634 { "xsaves", "on" }, 3635 { "vmx-xsaves", "on" }, 3636 { /* end of list */ } 3637 } 3638 }, 3639 { /* end of list */ } 3640 } 3641 }, 3642 { 3643 .name = "Cascadelake-Server", 3644 .level = 0xd, 3645 .vendor = CPUID_VENDOR_INTEL, 3646 .family = 6, 3647 .model = 85, 3648 .stepping = 6, 3649 .features[FEAT_1_EDX] = 3650 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3651 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3652 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3653 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3654 CPUID_DE | CPUID_FP87, 3655 .features[FEAT_1_ECX] = 3656 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3657 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3658 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3659 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3660 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3661 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3662 .features[FEAT_8000_0001_EDX] = 3663 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3664 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3665 .features[FEAT_8000_0001_ECX] = 3666 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3667 .features[FEAT_7_0_EBX] = 3668 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3669 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3670 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3671 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3672 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3673 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3674 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3675 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3676 .features[FEAT_7_0_ECX] = 3677 CPUID_7_0_ECX_PKU | 3678 CPUID_7_0_ECX_AVX512VNNI, 3679 .features[FEAT_7_0_EDX] = 3680 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 3681 /* XSAVES is added in version 5 */ 3682 .features[FEAT_XSAVE] = 3683 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3684 CPUID_XSAVE_XGETBV1, 3685 .features[FEAT_6_EAX] = 3686 CPUID_6_EAX_ARAT, 3687 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3688 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3689 MSR_VMX_BASIC_TRUE_CTLS, 3690 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3691 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3692 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3693 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3694 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3695 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3696 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3697 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3698 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3699 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3700 .features[FEAT_VMX_EXIT_CTLS] = 3701 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3702 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3703 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3704 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3705 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3706 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3707 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3708 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3709 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3710 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3711 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3712 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3713 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3714 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3715 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3716 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3717 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3718 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3719 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3720 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3721 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3722 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3723 .features[FEAT_VMX_SECONDARY_CTLS] = 3724 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3725 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3726 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3727 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3728 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3729 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3730 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3731 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3732 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3733 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3734 .xlevel = 0x80000008, 3735 .model_id = "Intel Xeon Processor (Cascadelake)", 3736 .versions = (X86CPUVersionDefinition[]) { 3737 { .version = 1 }, 3738 { .version = 2, 3739 .note = "ARCH_CAPABILITIES", 3740 .props = (PropValue[]) { 3741 { "arch-capabilities", "on" }, 3742 { "rdctl-no", "on" }, 3743 { "ibrs-all", "on" }, 3744 { "skip-l1dfl-vmentry", "on" }, 3745 { "mds-no", "on" }, 3746 { /* end of list */ } 3747 }, 3748 }, 3749 { .version = 3, 3750 .alias = "Cascadelake-Server-noTSX", 3751 .note = "ARCH_CAPABILITIES, no TSX", 3752 .props = (PropValue[]) { 3753 { "hle", "off" }, 3754 { "rtm", "off" }, 3755 { /* end of list */ } 3756 }, 3757 }, 3758 { .version = 4, 3759 .note = "ARCH_CAPABILITIES, no TSX", 3760 .props = (PropValue[]) { 3761 { "vmx-eptp-switching", "on" }, 3762 { /* end of list */ } 3763 }, 3764 }, 3765 { .version = 5, 3766 .note = "ARCH_CAPABILITIES, EPT switching, XSAVES, no TSX", 3767 .props = (PropValue[]) { 3768 { "xsaves", "on" }, 3769 { "vmx-xsaves", "on" }, 3770 { /* end of list */ } 3771 }, 3772 }, 3773 { /* end of list */ } 3774 } 3775 }, 3776 { 3777 .name = "Cooperlake", 3778 .level = 0xd, 3779 .vendor = CPUID_VENDOR_INTEL, 3780 .family = 6, 3781 .model = 85, 3782 .stepping = 10, 3783 .features[FEAT_1_EDX] = 3784 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3785 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3786 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3787 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3788 CPUID_DE | CPUID_FP87, 3789 .features[FEAT_1_ECX] = 3790 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3791 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3792 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3793 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3794 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3795 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3796 .features[FEAT_8000_0001_EDX] = 3797 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3798 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3799 .features[FEAT_8000_0001_ECX] = 3800 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3801 .features[FEAT_7_0_EBX] = 3802 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3803 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3804 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3805 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3806 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3807 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3808 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3809 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3810 .features[FEAT_7_0_ECX] = 3811 CPUID_7_0_ECX_PKU | 3812 CPUID_7_0_ECX_AVX512VNNI, 3813 .features[FEAT_7_0_EDX] = 3814 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_STIBP | 3815 CPUID_7_0_EDX_SPEC_CTRL_SSBD | CPUID_7_0_EDX_ARCH_CAPABILITIES, 3816 .features[FEAT_ARCH_CAPABILITIES] = 3817 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 3818 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 3819 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO, 3820 .features[FEAT_7_1_EAX] = 3821 CPUID_7_1_EAX_AVX512_BF16, 3822 /* XSAVES is added in version 2 */ 3823 .features[FEAT_XSAVE] = 3824 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3825 CPUID_XSAVE_XGETBV1, 3826 .features[FEAT_6_EAX] = 3827 CPUID_6_EAX_ARAT, 3828 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3829 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3830 MSR_VMX_BASIC_TRUE_CTLS, 3831 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3832 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3833 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3834 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3835 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3836 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3837 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3838 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3839 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3840 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3841 .features[FEAT_VMX_EXIT_CTLS] = 3842 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3843 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3844 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3845 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3846 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3847 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3848 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3849 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3850 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3851 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3852 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3853 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3854 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3855 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3856 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3857 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3858 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3859 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3860 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3861 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3862 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3863 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3864 .features[FEAT_VMX_SECONDARY_CTLS] = 3865 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3866 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3867 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3868 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3869 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3870 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3871 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3872 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3873 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3874 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3875 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3876 .xlevel = 0x80000008, 3877 .model_id = "Intel Xeon Processor (Cooperlake)", 3878 .versions = (X86CPUVersionDefinition[]) { 3879 { .version = 1 }, 3880 { .version = 2, 3881 .note = "XSAVES", 3882 .props = (PropValue[]) { 3883 { "xsaves", "on" }, 3884 { "vmx-xsaves", "on" }, 3885 { /* end of list */ } 3886 }, 3887 }, 3888 { /* end of list */ } 3889 } 3890 }, 3891 { 3892 .name = "Icelake-Server", 3893 .level = 0xd, 3894 .vendor = CPUID_VENDOR_INTEL, 3895 .family = 6, 3896 .model = 134, 3897 .stepping = 0, 3898 .features[FEAT_1_EDX] = 3899 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3900 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3901 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3902 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3903 CPUID_DE | CPUID_FP87, 3904 .features[FEAT_1_ECX] = 3905 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3906 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3907 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3908 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3909 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3910 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3911 .features[FEAT_8000_0001_EDX] = 3912 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3913 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3914 .features[FEAT_8000_0001_ECX] = 3915 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3916 .features[FEAT_8000_0008_EBX] = 3917 CPUID_8000_0008_EBX_WBNOINVD, 3918 .features[FEAT_7_0_EBX] = 3919 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3920 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3921 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3922 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3923 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3924 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3925 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3926 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3927 .features[FEAT_7_0_ECX] = 3928 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 3929 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 3930 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 3931 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 3932 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57, 3933 .features[FEAT_7_0_EDX] = 3934 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 3935 /* XSAVES is added in version 5 */ 3936 .features[FEAT_XSAVE] = 3937 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3938 CPUID_XSAVE_XGETBV1, 3939 .features[FEAT_6_EAX] = 3940 CPUID_6_EAX_ARAT, 3941 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3942 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3943 MSR_VMX_BASIC_TRUE_CTLS, 3944 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3945 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3946 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3947 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3948 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3949 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3950 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3951 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3952 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3953 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3954 .features[FEAT_VMX_EXIT_CTLS] = 3955 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3956 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3957 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3958 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3959 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3960 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3961 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3962 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3963 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3964 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3965 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3966 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3967 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3968 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3969 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3970 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3971 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3972 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3973 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3974 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3975 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3976 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3977 .features[FEAT_VMX_SECONDARY_CTLS] = 3978 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3979 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3980 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3981 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3982 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3983 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3984 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3985 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3986 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS, 3987 .xlevel = 0x80000008, 3988 .model_id = "Intel Xeon Processor (Icelake)", 3989 .versions = (X86CPUVersionDefinition[]) { 3990 { .version = 1 }, 3991 { 3992 .version = 2, 3993 .note = "no TSX", 3994 .alias = "Icelake-Server-noTSX", 3995 .props = (PropValue[]) { 3996 { "hle", "off" }, 3997 { "rtm", "off" }, 3998 { /* end of list */ } 3999 }, 4000 }, 4001 { 4002 .version = 3, 4003 .props = (PropValue[]) { 4004 { "arch-capabilities", "on" }, 4005 { "rdctl-no", "on" }, 4006 { "ibrs-all", "on" }, 4007 { "skip-l1dfl-vmentry", "on" }, 4008 { "mds-no", "on" }, 4009 { "pschange-mc-no", "on" }, 4010 { "taa-no", "on" }, 4011 { /* end of list */ } 4012 }, 4013 }, 4014 { 4015 .version = 4, 4016 .props = (PropValue[]) { 4017 { "sha-ni", "on" }, 4018 { "avx512ifma", "on" }, 4019 { "rdpid", "on" }, 4020 { "fsrm", "on" }, 4021 { "vmx-rdseed-exit", "on" }, 4022 { "vmx-pml", "on" }, 4023 { "vmx-eptp-switching", "on" }, 4024 { "model", "106" }, 4025 { /* end of list */ } 4026 }, 4027 }, 4028 { 4029 .version = 5, 4030 .note = "XSAVES", 4031 .props = (PropValue[]) { 4032 { "xsaves", "on" }, 4033 { "vmx-xsaves", "on" }, 4034 { /* end of list */ } 4035 }, 4036 }, 4037 { 4038 .version = 6, 4039 .note = "5-level EPT", 4040 .props = (PropValue[]) { 4041 { "vmx-page-walk-5", "on" }, 4042 { /* end of list */ } 4043 }, 4044 }, 4045 { 4046 .version = 7, 4047 .note = "TSX, taa-no", 4048 .props = (PropValue[]) { 4049 /* Restore TSX features removed by -v2 above */ 4050 { "hle", "on" }, 4051 { "rtm", "on" }, 4052 { /* end of list */ } 4053 }, 4054 }, 4055 { /* end of list */ } 4056 } 4057 }, 4058 { 4059 .name = "SapphireRapids", 4060 .level = 0x20, 4061 .vendor = CPUID_VENDOR_INTEL, 4062 .family = 6, 4063 .model = 143, 4064 .stepping = 4, 4065 /* 4066 * please keep the ascending order so that we can have a clear view of 4067 * bit position of each feature. 4068 */ 4069 .features[FEAT_1_EDX] = 4070 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4071 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4072 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4073 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4074 CPUID_SSE | CPUID_SSE2, 4075 .features[FEAT_1_ECX] = 4076 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 4077 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 4078 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4079 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 4080 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4081 .features[FEAT_8000_0001_EDX] = 4082 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4083 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4084 .features[FEAT_8000_0001_ECX] = 4085 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 4086 .features[FEAT_8000_0008_EBX] = 4087 CPUID_8000_0008_EBX_WBNOINVD, 4088 .features[FEAT_7_0_EBX] = 4089 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_HLE | 4090 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | 4091 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RTM | 4092 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 4093 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | 4094 CPUID_7_0_EBX_AVX512IFMA | CPUID_7_0_EBX_CLFLUSHOPT | 4095 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | 4096 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, 4097 .features[FEAT_7_0_ECX] = 4098 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 4099 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 4100 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4101 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 4102 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | 4103 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT, 4104 .features[FEAT_7_0_EDX] = 4105 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 4106 CPUID_7_0_EDX_TSX_LDTRK | CPUID_7_0_EDX_AMX_BF16 | 4107 CPUID_7_0_EDX_AVX512_FP16 | CPUID_7_0_EDX_AMX_TILE | 4108 CPUID_7_0_EDX_AMX_INT8 | CPUID_7_0_EDX_SPEC_CTRL | 4109 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4110 .features[FEAT_ARCH_CAPABILITIES] = 4111 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 4112 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 4113 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO, 4114 .features[FEAT_XSAVE] = 4115 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4116 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES | CPUID_D_1_EAX_XFD, 4117 .features[FEAT_6_EAX] = 4118 CPUID_6_EAX_ARAT, 4119 .features[FEAT_7_1_EAX] = 4120 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_AVX512_BF16 | 4121 CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC, 4122 .features[FEAT_VMX_BASIC] = 4123 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 4124 .features[FEAT_VMX_ENTRY_CTLS] = 4125 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 4126 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 4127 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 4128 .features[FEAT_VMX_EPT_VPID_CAPS] = 4129 MSR_VMX_EPT_EXECONLY | 4130 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_PAGE_WALK_LENGTH_5 | 4131 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 4132 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 4133 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4134 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4135 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 4136 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4137 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 4138 .features[FEAT_VMX_EXIT_CTLS] = 4139 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4140 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4141 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 4142 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4143 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4144 .features[FEAT_VMX_MISC] = 4145 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 4146 MSR_VMX_MISC_VMWRITE_VMEXIT, 4147 .features[FEAT_VMX_PINBASED_CTLS] = 4148 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 4149 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 4150 VMX_PIN_BASED_POSTED_INTR, 4151 .features[FEAT_VMX_PROCBASED_CTLS] = 4152 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4153 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4154 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4155 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4156 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4157 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4158 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 4159 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 4160 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4161 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 4162 VMX_CPU_BASED_PAUSE_EXITING | 4163 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4164 .features[FEAT_VMX_SECONDARY_CTLS] = 4165 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4166 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 4167 VMX_SECONDARY_EXEC_RDTSCP | 4168 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4169 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 4170 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4171 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4172 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4173 VMX_SECONDARY_EXEC_RDRAND_EXITING | 4174 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4175 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4176 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 4177 VMX_SECONDARY_EXEC_XSAVES, 4178 .features[FEAT_VMX_VMFUNC] = 4179 MSR_VMX_VMFUNC_EPT_SWITCHING, 4180 .xlevel = 0x80000008, 4181 .model_id = "Intel Xeon Processor (SapphireRapids)", 4182 .versions = (X86CPUVersionDefinition[]) { 4183 { .version = 1 }, 4184 { 4185 .version = 2, 4186 .props = (PropValue[]) { 4187 { "sbdr-ssdp-no", "on" }, 4188 { "fbsdp-no", "on" }, 4189 { "psdp-no", "on" }, 4190 { /* end of list */ } 4191 } 4192 }, 4193 { 4194 .version = 3, 4195 .props = (PropValue[]) { 4196 { "ss", "on" }, 4197 { "tsc-adjust", "on" }, 4198 { "cldemote", "on" }, 4199 { "movdiri", "on" }, 4200 { "movdir64b", "on" }, 4201 { /* end of list */ } 4202 } 4203 }, 4204 { /* end of list */ } 4205 } 4206 }, 4207 { 4208 .name = "GraniteRapids", 4209 .level = 0x20, 4210 .vendor = CPUID_VENDOR_INTEL, 4211 .family = 6, 4212 .model = 173, 4213 .stepping = 0, 4214 /* 4215 * please keep the ascending order so that we can have a clear view of 4216 * bit position of each feature. 4217 */ 4218 .features[FEAT_1_EDX] = 4219 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4220 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4221 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4222 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4223 CPUID_SSE | CPUID_SSE2, 4224 .features[FEAT_1_ECX] = 4225 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 4226 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 4227 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4228 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 4229 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4230 .features[FEAT_8000_0001_EDX] = 4231 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4232 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4233 .features[FEAT_8000_0001_ECX] = 4234 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 4235 .features[FEAT_8000_0008_EBX] = 4236 CPUID_8000_0008_EBX_WBNOINVD, 4237 .features[FEAT_7_0_EBX] = 4238 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_HLE | 4239 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | 4240 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RTM | 4241 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 4242 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | 4243 CPUID_7_0_EBX_AVX512IFMA | CPUID_7_0_EBX_CLFLUSHOPT | 4244 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | 4245 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, 4246 .features[FEAT_7_0_ECX] = 4247 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 4248 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 4249 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4250 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 4251 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | 4252 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT, 4253 .features[FEAT_7_0_EDX] = 4254 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 4255 CPUID_7_0_EDX_TSX_LDTRK | CPUID_7_0_EDX_AMX_BF16 | 4256 CPUID_7_0_EDX_AVX512_FP16 | CPUID_7_0_EDX_AMX_TILE | 4257 CPUID_7_0_EDX_AMX_INT8 | CPUID_7_0_EDX_SPEC_CTRL | 4258 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4259 .features[FEAT_ARCH_CAPABILITIES] = 4260 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 4261 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 4262 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO | 4263 MSR_ARCH_CAP_SBDR_SSDP_NO | MSR_ARCH_CAP_FBSDP_NO | 4264 MSR_ARCH_CAP_PSDP_NO | MSR_ARCH_CAP_PBRSB_NO, 4265 .features[FEAT_XSAVE] = 4266 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4267 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES | CPUID_D_1_EAX_XFD, 4268 .features[FEAT_6_EAX] = 4269 CPUID_6_EAX_ARAT, 4270 .features[FEAT_7_1_EAX] = 4271 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_AVX512_BF16 | 4272 CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC | 4273 CPUID_7_1_EAX_AMX_FP16, 4274 .features[FEAT_7_1_EDX] = 4275 CPUID_7_1_EDX_PREFETCHITI, 4276 .features[FEAT_7_2_EDX] = 4277 CPUID_7_2_EDX_MCDT_NO, 4278 .features[FEAT_VMX_BASIC] = 4279 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 4280 .features[FEAT_VMX_ENTRY_CTLS] = 4281 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 4282 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 4283 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 4284 .features[FEAT_VMX_EPT_VPID_CAPS] = 4285 MSR_VMX_EPT_EXECONLY | 4286 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_PAGE_WALK_LENGTH_5 | 4287 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 4288 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 4289 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4290 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4291 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 4292 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4293 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 4294 .features[FEAT_VMX_EXIT_CTLS] = 4295 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4296 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4297 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 4298 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4299 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4300 .features[FEAT_VMX_MISC] = 4301 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 4302 MSR_VMX_MISC_VMWRITE_VMEXIT, 4303 .features[FEAT_VMX_PINBASED_CTLS] = 4304 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 4305 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 4306 VMX_PIN_BASED_POSTED_INTR, 4307 .features[FEAT_VMX_PROCBASED_CTLS] = 4308 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4309 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4310 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4311 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4312 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4313 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4314 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 4315 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 4316 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4317 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 4318 VMX_CPU_BASED_PAUSE_EXITING | 4319 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4320 .features[FEAT_VMX_SECONDARY_CTLS] = 4321 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4322 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 4323 VMX_SECONDARY_EXEC_RDTSCP | 4324 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4325 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 4326 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4327 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4328 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4329 VMX_SECONDARY_EXEC_RDRAND_EXITING | 4330 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4331 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4332 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 4333 VMX_SECONDARY_EXEC_XSAVES, 4334 .features[FEAT_VMX_VMFUNC] = 4335 MSR_VMX_VMFUNC_EPT_SWITCHING, 4336 .xlevel = 0x80000008, 4337 .model_id = "Intel Xeon Processor (GraniteRapids)", 4338 .versions = (X86CPUVersionDefinition[]) { 4339 { .version = 1 }, 4340 { /* end of list */ }, 4341 }, 4342 }, 4343 { 4344 .name = "SierraForest", 4345 .level = 0x23, 4346 .vendor = CPUID_VENDOR_INTEL, 4347 .family = 6, 4348 .model = 175, 4349 .stepping = 0, 4350 /* 4351 * please keep the ascending order so that we can have a clear view of 4352 * bit position of each feature. 4353 */ 4354 .features[FEAT_1_EDX] = 4355 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4356 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4357 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4358 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4359 CPUID_SSE | CPUID_SSE2, 4360 .features[FEAT_1_ECX] = 4361 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 4362 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 4363 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4364 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 4365 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4366 .features[FEAT_8000_0001_EDX] = 4367 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4368 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4369 .features[FEAT_8000_0001_ECX] = 4370 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 4371 .features[FEAT_8000_0008_EBX] = 4372 CPUID_8000_0008_EBX_WBNOINVD, 4373 .features[FEAT_7_0_EBX] = 4374 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4375 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 4376 CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 4377 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB | 4378 CPUID_7_0_EBX_SHA_NI, 4379 .features[FEAT_7_0_ECX] = 4380 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_GFNI | 4381 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4382 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT, 4383 .features[FEAT_7_0_EDX] = 4384 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 4385 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES | 4386 CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4387 .features[FEAT_ARCH_CAPABILITIES] = 4388 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 4389 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 4390 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_SBDR_SSDP_NO | 4391 MSR_ARCH_CAP_FBSDP_NO | MSR_ARCH_CAP_PSDP_NO | 4392 MSR_ARCH_CAP_PBRSB_NO, 4393 .features[FEAT_XSAVE] = 4394 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4395 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 4396 .features[FEAT_6_EAX] = 4397 CPUID_6_EAX_ARAT, 4398 .features[FEAT_7_1_EAX] = 4399 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_CMPCCXADD | 4400 CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_AVX_IFMA, 4401 .features[FEAT_7_1_EDX] = 4402 CPUID_7_1_EDX_AVX_VNNI_INT8 | CPUID_7_1_EDX_AVX_NE_CONVERT, 4403 .features[FEAT_7_2_EDX] = 4404 CPUID_7_2_EDX_MCDT_NO, 4405 .features[FEAT_VMX_BASIC] = 4406 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 4407 .features[FEAT_VMX_ENTRY_CTLS] = 4408 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 4409 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 4410 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 4411 .features[FEAT_VMX_EPT_VPID_CAPS] = 4412 MSR_VMX_EPT_EXECONLY | MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | 4413 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 4414 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 4415 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4416 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4417 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 4418 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4419 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 4420 .features[FEAT_VMX_EXIT_CTLS] = 4421 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4422 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4423 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 4424 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4425 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4426 .features[FEAT_VMX_MISC] = 4427 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 4428 MSR_VMX_MISC_VMWRITE_VMEXIT, 4429 .features[FEAT_VMX_PINBASED_CTLS] = 4430 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 4431 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 4432 VMX_PIN_BASED_POSTED_INTR, 4433 .features[FEAT_VMX_PROCBASED_CTLS] = 4434 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4435 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4436 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4437 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4438 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4439 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4440 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 4441 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 4442 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4443 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 4444 VMX_CPU_BASED_PAUSE_EXITING | 4445 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4446 .features[FEAT_VMX_SECONDARY_CTLS] = 4447 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4448 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 4449 VMX_SECONDARY_EXEC_RDTSCP | 4450 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4451 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 4452 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4453 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4454 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4455 VMX_SECONDARY_EXEC_RDRAND_EXITING | 4456 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4457 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4458 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 4459 VMX_SECONDARY_EXEC_XSAVES, 4460 .features[FEAT_VMX_VMFUNC] = 4461 MSR_VMX_VMFUNC_EPT_SWITCHING, 4462 .xlevel = 0x80000008, 4463 .model_id = "Intel Xeon Processor (SierraForest)", 4464 .versions = (X86CPUVersionDefinition[]) { 4465 { .version = 1 }, 4466 { /* end of list */ }, 4467 }, 4468 }, 4469 { 4470 .name = "Denverton", 4471 .level = 21, 4472 .vendor = CPUID_VENDOR_INTEL, 4473 .family = 6, 4474 .model = 95, 4475 .stepping = 1, 4476 .features[FEAT_1_EDX] = 4477 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4478 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4479 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4480 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4481 CPUID_SSE | CPUID_SSE2, 4482 .features[FEAT_1_ECX] = 4483 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR | 4484 CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_SSE41 | 4485 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4486 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | 4487 CPUID_EXT_AES | CPUID_EXT_XSAVE | CPUID_EXT_RDRAND, 4488 .features[FEAT_8000_0001_EDX] = 4489 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4490 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4491 .features[FEAT_8000_0001_ECX] = 4492 CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 4493 .features[FEAT_7_0_EBX] = 4494 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_ERMS | 4495 CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_SMAP | 4496 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_SHA_NI, 4497 .features[FEAT_7_0_EDX] = 4498 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES | 4499 CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4500 /* XSAVES is added in version 3 */ 4501 .features[FEAT_XSAVE] = 4502 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | CPUID_XSAVE_XGETBV1, 4503 .features[FEAT_6_EAX] = 4504 CPUID_6_EAX_ARAT, 4505 .features[FEAT_ARCH_CAPABILITIES] = 4506 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY, 4507 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 4508 MSR_VMX_BASIC_TRUE_CTLS, 4509 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 4510 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 4511 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 4512 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 4513 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 4514 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 4515 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4516 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4517 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4518 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 4519 .features[FEAT_VMX_EXIT_CTLS] = 4520 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4521 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4522 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 4523 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4524 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4525 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 4526 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 4527 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 4528 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 4529 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 4530 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4531 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4532 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4533 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4534 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4535 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 4536 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 4537 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 4538 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 4539 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4540 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4541 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4542 .features[FEAT_VMX_SECONDARY_CTLS] = 4543 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4544 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 4545 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 4546 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4547 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4548 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4549 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4550 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4551 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4552 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 4553 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 4554 .xlevel = 0x80000008, 4555 .model_id = "Intel Atom Processor (Denverton)", 4556 .versions = (X86CPUVersionDefinition[]) { 4557 { .version = 1 }, 4558 { 4559 .version = 2, 4560 .note = "no MPX, no MONITOR", 4561 .props = (PropValue[]) { 4562 { "monitor", "off" }, 4563 { "mpx", "off" }, 4564 { /* end of list */ }, 4565 }, 4566 }, 4567 { 4568 .version = 3, 4569 .note = "XSAVES, no MPX, no MONITOR", 4570 .props = (PropValue[]) { 4571 { "xsaves", "on" }, 4572 { "vmx-xsaves", "on" }, 4573 { /* end of list */ }, 4574 }, 4575 }, 4576 { /* end of list */ }, 4577 }, 4578 }, 4579 { 4580 .name = "Snowridge", 4581 .level = 27, 4582 .vendor = CPUID_VENDOR_INTEL, 4583 .family = 6, 4584 .model = 134, 4585 .stepping = 1, 4586 .features[FEAT_1_EDX] = 4587 /* missing: CPUID_PN CPUID_IA64 */ 4588 /* missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 4589 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | 4590 CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_MCE | 4591 CPUID_CX8 | CPUID_APIC | CPUID_SEP | 4592 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4593 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | 4594 CPUID_MMX | 4595 CPUID_FXSR | CPUID_SSE | CPUID_SSE2, 4596 .features[FEAT_1_ECX] = 4597 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR | 4598 CPUID_EXT_SSSE3 | 4599 CPUID_EXT_CX16 | 4600 CPUID_EXT_SSE41 | 4601 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4602 CPUID_EXT_POPCNT | 4603 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | CPUID_EXT_XSAVE | 4604 CPUID_EXT_RDRAND, 4605 .features[FEAT_8000_0001_EDX] = 4606 CPUID_EXT2_SYSCALL | 4607 CPUID_EXT2_NX | 4608 CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 4609 CPUID_EXT2_LM, 4610 .features[FEAT_8000_0001_ECX] = 4611 CPUID_EXT3_LAHF_LM | 4612 CPUID_EXT3_3DNOWPREFETCH, 4613 .features[FEAT_7_0_EBX] = 4614 CPUID_7_0_EBX_FSGSBASE | 4615 CPUID_7_0_EBX_SMEP | 4616 CPUID_7_0_EBX_ERMS | 4617 CPUID_7_0_EBX_MPX | /* missing bits 13, 15 */ 4618 CPUID_7_0_EBX_RDSEED | 4619 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 4620 CPUID_7_0_EBX_CLWB | 4621 CPUID_7_0_EBX_SHA_NI, 4622 .features[FEAT_7_0_ECX] = 4623 CPUID_7_0_ECX_UMIP | 4624 /* missing bit 5 */ 4625 CPUID_7_0_ECX_GFNI | 4626 CPUID_7_0_ECX_MOVDIRI | CPUID_7_0_ECX_CLDEMOTE | 4627 CPUID_7_0_ECX_MOVDIR64B, 4628 .features[FEAT_7_0_EDX] = 4629 CPUID_7_0_EDX_SPEC_CTRL | 4630 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD | 4631 CPUID_7_0_EDX_CORE_CAPABILITY, 4632 .features[FEAT_CORE_CAPABILITY] = 4633 MSR_CORE_CAP_SPLIT_LOCK_DETECT, 4634 /* XSAVES is added in version 3 */ 4635 .features[FEAT_XSAVE] = 4636 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4637 CPUID_XSAVE_XGETBV1, 4638 .features[FEAT_6_EAX] = 4639 CPUID_6_EAX_ARAT, 4640 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 4641 MSR_VMX_BASIC_TRUE_CTLS, 4642 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 4643 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 4644 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 4645 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 4646 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 4647 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 4648 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4649 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4650 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4651 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 4652 .features[FEAT_VMX_EXIT_CTLS] = 4653 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4654 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4655 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 4656 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4657 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4658 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 4659 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 4660 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 4661 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 4662 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 4663 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4664 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4665 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4666 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4667 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4668 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 4669 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 4670 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 4671 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 4672 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4673 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4674 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4675 .features[FEAT_VMX_SECONDARY_CTLS] = 4676 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4677 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 4678 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 4679 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4680 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4681 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4682 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4683 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4684 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4685 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 4686 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 4687 .xlevel = 0x80000008, 4688 .model_id = "Intel Atom Processor (SnowRidge)", 4689 .versions = (X86CPUVersionDefinition[]) { 4690 { .version = 1 }, 4691 { 4692 .version = 2, 4693 .props = (PropValue[]) { 4694 { "mpx", "off" }, 4695 { "model-id", "Intel Atom Processor (Snowridge, no MPX)" }, 4696 { /* end of list */ }, 4697 }, 4698 }, 4699 { 4700 .version = 3, 4701 .note = "XSAVES, no MPX", 4702 .props = (PropValue[]) { 4703 { "xsaves", "on" }, 4704 { "vmx-xsaves", "on" }, 4705 { /* end of list */ }, 4706 }, 4707 }, 4708 { 4709 .version = 4, 4710 .note = "no split lock detect, no core-capability", 4711 .props = (PropValue[]) { 4712 { "split-lock-detect", "off" }, 4713 { "core-capability", "off" }, 4714 { /* end of list */ }, 4715 }, 4716 }, 4717 { /* end of list */ }, 4718 }, 4719 }, 4720 { 4721 .name = "KnightsMill", 4722 .level = 0xd, 4723 .vendor = CPUID_VENDOR_INTEL, 4724 .family = 6, 4725 .model = 133, 4726 .stepping = 0, 4727 .features[FEAT_1_EDX] = 4728 CPUID_VME | CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | 4729 CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | 4730 CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | 4731 CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | 4732 CPUID_PSE | CPUID_DE | CPUID_FP87, 4733 .features[FEAT_1_ECX] = 4734 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 4735 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 4736 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 4737 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 4738 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 4739 CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4740 .features[FEAT_8000_0001_EDX] = 4741 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 4742 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 4743 .features[FEAT_8000_0001_ECX] = 4744 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 4745 .features[FEAT_7_0_EBX] = 4746 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4747 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 4748 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_AVX512F | 4749 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_AVX512PF | 4750 CPUID_7_0_EBX_AVX512ER, 4751 .features[FEAT_7_0_ECX] = 4752 CPUID_7_0_ECX_AVX512_VPOPCNTDQ, 4753 .features[FEAT_7_0_EDX] = 4754 CPUID_7_0_EDX_AVX512_4VNNIW | CPUID_7_0_EDX_AVX512_4FMAPS, 4755 .features[FEAT_XSAVE] = 4756 CPUID_XSAVE_XSAVEOPT, 4757 .features[FEAT_6_EAX] = 4758 CPUID_6_EAX_ARAT, 4759 .xlevel = 0x80000008, 4760 .model_id = "Intel Xeon Phi Processor (Knights Mill)", 4761 }, 4762 { 4763 .name = "Opteron_G1", 4764 .level = 5, 4765 .vendor = CPUID_VENDOR_AMD, 4766 .family = 15, 4767 .model = 6, 4768 .stepping = 1, 4769 .features[FEAT_1_EDX] = 4770 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4771 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4772 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4773 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4774 CPUID_DE | CPUID_FP87, 4775 .features[FEAT_1_ECX] = 4776 CPUID_EXT_SSE3, 4777 .features[FEAT_8000_0001_EDX] = 4778 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 4779 .xlevel = 0x80000008, 4780 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)", 4781 }, 4782 { 4783 .name = "Opteron_G2", 4784 .level = 5, 4785 .vendor = CPUID_VENDOR_AMD, 4786 .family = 15, 4787 .model = 6, 4788 .stepping = 1, 4789 .features[FEAT_1_EDX] = 4790 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4791 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4792 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4793 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4794 CPUID_DE | CPUID_FP87, 4795 .features[FEAT_1_ECX] = 4796 CPUID_EXT_CX16 | CPUID_EXT_SSE3, 4797 .features[FEAT_8000_0001_EDX] = 4798 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 4799 .features[FEAT_8000_0001_ECX] = 4800 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, 4801 .xlevel = 0x80000008, 4802 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)", 4803 }, 4804 { 4805 .name = "Opteron_G3", 4806 .level = 5, 4807 .vendor = CPUID_VENDOR_AMD, 4808 .family = 16, 4809 .model = 2, 4810 .stepping = 3, 4811 .features[FEAT_1_EDX] = 4812 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4813 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4814 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4815 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4816 CPUID_DE | CPUID_FP87, 4817 .features[FEAT_1_ECX] = 4818 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR | 4819 CPUID_EXT_SSE3, 4820 .features[FEAT_8000_0001_EDX] = 4821 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL | 4822 CPUID_EXT2_RDTSCP, 4823 .features[FEAT_8000_0001_ECX] = 4824 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | 4825 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, 4826 .xlevel = 0x80000008, 4827 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)", 4828 }, 4829 { 4830 .name = "Opteron_G4", 4831 .level = 0xd, 4832 .vendor = CPUID_VENDOR_AMD, 4833 .family = 21, 4834 .model = 1, 4835 .stepping = 2, 4836 .features[FEAT_1_EDX] = 4837 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4838 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4839 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4840 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4841 CPUID_DE | CPUID_FP87, 4842 .features[FEAT_1_ECX] = 4843 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 4844 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 4845 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 4846 CPUID_EXT_SSE3, 4847 .features[FEAT_8000_0001_EDX] = 4848 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX | 4849 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP, 4850 .features[FEAT_8000_0001_ECX] = 4851 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP | 4852 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | 4853 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | 4854 CPUID_EXT3_LAHF_LM, 4855 .features[FEAT_SVM] = 4856 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 4857 /* no xsaveopt! */ 4858 .xlevel = 0x8000001A, 4859 .model_id = "AMD Opteron 62xx class CPU", 4860 }, 4861 { 4862 .name = "Opteron_G5", 4863 .level = 0xd, 4864 .vendor = CPUID_VENDOR_AMD, 4865 .family = 21, 4866 .model = 2, 4867 .stepping = 0, 4868 .features[FEAT_1_EDX] = 4869 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4870 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4871 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4872 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4873 CPUID_DE | CPUID_FP87, 4874 .features[FEAT_1_ECX] = 4875 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE | 4876 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | 4877 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA | 4878 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 4879 .features[FEAT_8000_0001_EDX] = 4880 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX | 4881 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP, 4882 .features[FEAT_8000_0001_ECX] = 4883 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP | 4884 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | 4885 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | 4886 CPUID_EXT3_LAHF_LM, 4887 .features[FEAT_SVM] = 4888 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 4889 /* no xsaveopt! */ 4890 .xlevel = 0x8000001A, 4891 .model_id = "AMD Opteron 63xx class CPU", 4892 }, 4893 { 4894 .name = "EPYC", 4895 .level = 0xd, 4896 .vendor = CPUID_VENDOR_AMD, 4897 .family = 23, 4898 .model = 1, 4899 .stepping = 2, 4900 .features[FEAT_1_EDX] = 4901 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 4902 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 4903 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 4904 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 4905 CPUID_VME | CPUID_FP87, 4906 .features[FEAT_1_ECX] = 4907 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 4908 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 4909 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 4910 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 4911 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 4912 .features[FEAT_8000_0001_EDX] = 4913 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 4914 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 4915 CPUID_EXT2_SYSCALL, 4916 .features[FEAT_8000_0001_ECX] = 4917 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 4918 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 4919 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 4920 CPUID_EXT3_TOPOEXT, 4921 .features[FEAT_7_0_EBX] = 4922 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4923 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 4924 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 4925 CPUID_7_0_EBX_SHA_NI, 4926 .features[FEAT_XSAVE] = 4927 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4928 CPUID_XSAVE_XGETBV1, 4929 .features[FEAT_6_EAX] = 4930 CPUID_6_EAX_ARAT, 4931 .features[FEAT_SVM] = 4932 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 4933 .xlevel = 0x8000001E, 4934 .model_id = "AMD EPYC Processor", 4935 .cache_info = &epyc_cache_info, 4936 .versions = (X86CPUVersionDefinition[]) { 4937 { .version = 1 }, 4938 { 4939 .version = 2, 4940 .alias = "EPYC-IBPB", 4941 .props = (PropValue[]) { 4942 { "ibpb", "on" }, 4943 { "model-id", 4944 "AMD EPYC Processor (with IBPB)" }, 4945 { /* end of list */ } 4946 } 4947 }, 4948 { 4949 .version = 3, 4950 .props = (PropValue[]) { 4951 { "ibpb", "on" }, 4952 { "perfctr-core", "on" }, 4953 { "clzero", "on" }, 4954 { "xsaveerptr", "on" }, 4955 { "xsaves", "on" }, 4956 { "model-id", 4957 "AMD EPYC Processor" }, 4958 { /* end of list */ } 4959 } 4960 }, 4961 { 4962 .version = 4, 4963 .props = (PropValue[]) { 4964 { "model-id", 4965 "AMD EPYC-v4 Processor" }, 4966 { /* end of list */ } 4967 }, 4968 .cache_info = &epyc_v4_cache_info 4969 }, 4970 { /* end of list */ } 4971 } 4972 }, 4973 { 4974 .name = "Dhyana", 4975 .level = 0xd, 4976 .vendor = CPUID_VENDOR_HYGON, 4977 .family = 24, 4978 .model = 0, 4979 .stepping = 1, 4980 .features[FEAT_1_EDX] = 4981 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 4982 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 4983 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 4984 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 4985 CPUID_VME | CPUID_FP87, 4986 .features[FEAT_1_ECX] = 4987 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 4988 CPUID_EXT_XSAVE | CPUID_EXT_POPCNT | 4989 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 4990 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 4991 CPUID_EXT_MONITOR | CPUID_EXT_SSE3, 4992 .features[FEAT_8000_0001_EDX] = 4993 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 4994 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 4995 CPUID_EXT2_SYSCALL, 4996 .features[FEAT_8000_0001_ECX] = 4997 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 4998 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 4999 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5000 CPUID_EXT3_TOPOEXT, 5001 .features[FEAT_8000_0008_EBX] = 5002 CPUID_8000_0008_EBX_IBPB, 5003 .features[FEAT_7_0_EBX] = 5004 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5005 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 5006 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT, 5007 /* XSAVES is added in version 2 */ 5008 .features[FEAT_XSAVE] = 5009 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5010 CPUID_XSAVE_XGETBV1, 5011 .features[FEAT_6_EAX] = 5012 CPUID_6_EAX_ARAT, 5013 .features[FEAT_SVM] = 5014 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 5015 .xlevel = 0x8000001E, 5016 .model_id = "Hygon Dhyana Processor", 5017 .cache_info = &epyc_cache_info, 5018 .versions = (X86CPUVersionDefinition[]) { 5019 { .version = 1 }, 5020 { .version = 2, 5021 .note = "XSAVES", 5022 .props = (PropValue[]) { 5023 { "xsaves", "on" }, 5024 { /* end of list */ } 5025 }, 5026 }, 5027 { /* end of list */ } 5028 } 5029 }, 5030 { 5031 .name = "EPYC-Rome", 5032 .level = 0xd, 5033 .vendor = CPUID_VENDOR_AMD, 5034 .family = 23, 5035 .model = 49, 5036 .stepping = 0, 5037 .features[FEAT_1_EDX] = 5038 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 5039 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 5040 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 5041 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 5042 CPUID_VME | CPUID_FP87, 5043 .features[FEAT_1_ECX] = 5044 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5045 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 5046 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5047 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 5048 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 5049 .features[FEAT_8000_0001_EDX] = 5050 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5051 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5052 CPUID_EXT2_SYSCALL, 5053 .features[FEAT_8000_0001_ECX] = 5054 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5055 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5056 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5057 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 5058 .features[FEAT_8000_0008_EBX] = 5059 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 5060 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 5061 CPUID_8000_0008_EBX_STIBP, 5062 .features[FEAT_7_0_EBX] = 5063 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5064 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 5065 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 5066 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB, 5067 .features[FEAT_7_0_ECX] = 5068 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID, 5069 .features[FEAT_XSAVE] = 5070 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5071 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 5072 .features[FEAT_6_EAX] = 5073 CPUID_6_EAX_ARAT, 5074 .features[FEAT_SVM] = 5075 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 5076 .xlevel = 0x8000001E, 5077 .model_id = "AMD EPYC-Rome Processor", 5078 .cache_info = &epyc_rome_cache_info, 5079 .versions = (X86CPUVersionDefinition[]) { 5080 { .version = 1 }, 5081 { 5082 .version = 2, 5083 .props = (PropValue[]) { 5084 { "ibrs", "on" }, 5085 { "amd-ssbd", "on" }, 5086 { /* end of list */ } 5087 } 5088 }, 5089 { 5090 .version = 3, 5091 .props = (PropValue[]) { 5092 { "model-id", 5093 "AMD EPYC-Rome-v3 Processor" }, 5094 { /* end of list */ } 5095 }, 5096 .cache_info = &epyc_rome_v3_cache_info 5097 }, 5098 { 5099 .version = 4, 5100 .props = (PropValue[]) { 5101 /* Erratum 1386 */ 5102 { "model-id", 5103 "AMD EPYC-Rome-v4 Processor (no XSAVES)" }, 5104 { "xsaves", "off" }, 5105 { /* end of list */ } 5106 }, 5107 }, 5108 { /* end of list */ } 5109 } 5110 }, 5111 { 5112 .name = "EPYC-Milan", 5113 .level = 0xd, 5114 .vendor = CPUID_VENDOR_AMD, 5115 .family = 25, 5116 .model = 1, 5117 .stepping = 1, 5118 .features[FEAT_1_EDX] = 5119 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 5120 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 5121 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 5122 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 5123 CPUID_VME | CPUID_FP87, 5124 .features[FEAT_1_ECX] = 5125 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5126 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 5127 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5128 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 5129 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 5130 CPUID_EXT_PCID, 5131 .features[FEAT_8000_0001_EDX] = 5132 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5133 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5134 CPUID_EXT2_SYSCALL, 5135 .features[FEAT_8000_0001_ECX] = 5136 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5137 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5138 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5139 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 5140 .features[FEAT_8000_0008_EBX] = 5141 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 5142 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 5143 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | 5144 CPUID_8000_0008_EBX_AMD_SSBD, 5145 .features[FEAT_7_0_EBX] = 5146 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5147 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 5148 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 5149 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_ERMS | 5150 CPUID_7_0_EBX_INVPCID, 5151 .features[FEAT_7_0_ECX] = 5152 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_PKU, 5153 .features[FEAT_7_0_EDX] = 5154 CPUID_7_0_EDX_FSRM, 5155 .features[FEAT_XSAVE] = 5156 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5157 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 5158 .features[FEAT_6_EAX] = 5159 CPUID_6_EAX_ARAT, 5160 .features[FEAT_SVM] = 5161 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE | CPUID_SVM_SVME_ADDR_CHK, 5162 .xlevel = 0x8000001E, 5163 .model_id = "AMD EPYC-Milan Processor", 5164 .cache_info = &epyc_milan_cache_info, 5165 .versions = (X86CPUVersionDefinition[]) { 5166 { .version = 1 }, 5167 { 5168 .version = 2, 5169 .props = (PropValue[]) { 5170 { "model-id", 5171 "AMD EPYC-Milan-v2 Processor" }, 5172 { "vaes", "on" }, 5173 { "vpclmulqdq", "on" }, 5174 { "stibp-always-on", "on" }, 5175 { "amd-psfd", "on" }, 5176 { "no-nested-data-bp", "on" }, 5177 { "lfence-always-serializing", "on" }, 5178 { "null-sel-clr-base", "on" }, 5179 { /* end of list */ } 5180 }, 5181 .cache_info = &epyc_milan_v2_cache_info 5182 }, 5183 { /* end of list */ } 5184 } 5185 }, 5186 { 5187 .name = "EPYC-Genoa", 5188 .level = 0xd, 5189 .vendor = CPUID_VENDOR_AMD, 5190 .family = 25, 5191 .model = 17, 5192 .stepping = 0, 5193 .features[FEAT_1_EDX] = 5194 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 5195 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 5196 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 5197 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 5198 CPUID_VME | CPUID_FP87, 5199 .features[FEAT_1_ECX] = 5200 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5201 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 5202 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5203 CPUID_EXT_PCID | CPUID_EXT_CX16 | CPUID_EXT_FMA | 5204 CPUID_EXT_SSSE3 | CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | 5205 CPUID_EXT_SSE3, 5206 .features[FEAT_8000_0001_EDX] = 5207 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5208 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5209 CPUID_EXT2_SYSCALL, 5210 .features[FEAT_8000_0001_ECX] = 5211 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5212 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5213 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5214 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 5215 .features[FEAT_8000_0008_EBX] = 5216 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 5217 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 5218 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | 5219 CPUID_8000_0008_EBX_STIBP_ALWAYS_ON | 5220 CPUID_8000_0008_EBX_AMD_SSBD | CPUID_8000_0008_EBX_AMD_PSFD, 5221 .features[FEAT_8000_0021_EAX] = 5222 CPUID_8000_0021_EAX_No_NESTED_DATA_BP | 5223 CPUID_8000_0021_EAX_LFENCE_ALWAYS_SERIALIZING | 5224 CPUID_8000_0021_EAX_NULL_SEL_CLR_BASE | 5225 CPUID_8000_0021_EAX_AUTO_IBRS, 5226 .features[FEAT_7_0_EBX] = 5227 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5228 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 5229 CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_AVX512F | 5230 CPUID_7_0_EBX_AVX512DQ | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 5231 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_AVX512IFMA | 5232 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB | 5233 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | 5234 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, 5235 .features[FEAT_7_0_ECX] = 5236 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 5237 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 5238 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 5239 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 5240 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | 5241 CPUID_7_0_ECX_RDPID, 5242 .features[FEAT_7_0_EDX] = 5243 CPUID_7_0_EDX_FSRM, 5244 .features[FEAT_7_1_EAX] = 5245 CPUID_7_1_EAX_AVX512_BF16, 5246 .features[FEAT_XSAVE] = 5247 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5248 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 5249 .features[FEAT_6_EAX] = 5250 CPUID_6_EAX_ARAT, 5251 .features[FEAT_SVM] = 5252 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE | CPUID_SVM_VNMI | 5253 CPUID_SVM_SVME_ADDR_CHK, 5254 .xlevel = 0x80000022, 5255 .model_id = "AMD EPYC-Genoa Processor", 5256 .cache_info = &epyc_genoa_cache_info, 5257 }, 5258 }; 5259 5260 /* 5261 * We resolve CPU model aliases using -v1 when using "-machine 5262 * none", but this is just for compatibility while libvirt isn't 5263 * adapted to resolve CPU model versions before creating VMs. 5264 * See "Runnability guarantee of CPU models" at 5265 * docs/about/deprecated.rst. 5266 */ 5267 X86CPUVersion default_cpu_version = 1; 5268 5269 void x86_cpu_set_default_version(X86CPUVersion version) 5270 { 5271 /* Translating CPU_VERSION_AUTO to CPU_VERSION_AUTO doesn't make sense */ 5272 assert(version != CPU_VERSION_AUTO); 5273 default_cpu_version = version; 5274 } 5275 5276 static X86CPUVersion x86_cpu_model_last_version(const X86CPUModel *model) 5277 { 5278 int v = 0; 5279 const X86CPUVersionDefinition *vdef = 5280 x86_cpu_def_get_versions(model->cpudef); 5281 while (vdef->version) { 5282 v = vdef->version; 5283 vdef++; 5284 } 5285 return v; 5286 } 5287 5288 /* Return the actual version being used for a specific CPU model */ 5289 static X86CPUVersion x86_cpu_model_resolve_version(const X86CPUModel *model) 5290 { 5291 X86CPUVersion v = model->version; 5292 if (v == CPU_VERSION_AUTO) { 5293 v = default_cpu_version; 5294 } 5295 if (v == CPU_VERSION_LATEST) { 5296 return x86_cpu_model_last_version(model); 5297 } 5298 return v; 5299 } 5300 5301 static Property max_x86_cpu_properties[] = { 5302 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true), 5303 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false), 5304 DEFINE_PROP_END_OF_LIST() 5305 }; 5306 5307 static void max_x86_cpu_realize(DeviceState *dev, Error **errp) 5308 { 5309 Object *obj = OBJECT(dev); 5310 5311 if (!object_property_get_int(obj, "family", &error_abort)) { 5312 if (X86_CPU(obj)->env.features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 5313 object_property_set_int(obj, "family", 15, &error_abort); 5314 object_property_set_int(obj, "model", 107, &error_abort); 5315 object_property_set_int(obj, "stepping", 1, &error_abort); 5316 } else { 5317 object_property_set_int(obj, "family", 6, &error_abort); 5318 object_property_set_int(obj, "model", 6, &error_abort); 5319 object_property_set_int(obj, "stepping", 3, &error_abort); 5320 } 5321 } 5322 5323 x86_cpu_realizefn(dev, errp); 5324 } 5325 5326 static void max_x86_cpu_class_init(ObjectClass *oc, void *data) 5327 { 5328 DeviceClass *dc = DEVICE_CLASS(oc); 5329 X86CPUClass *xcc = X86_CPU_CLASS(oc); 5330 5331 xcc->ordering = 9; 5332 5333 xcc->model_description = 5334 "Enables all features supported by the accelerator in the current host"; 5335 5336 device_class_set_props(dc, max_x86_cpu_properties); 5337 dc->realize = max_x86_cpu_realize; 5338 } 5339 5340 static void max_x86_cpu_initfn(Object *obj) 5341 { 5342 X86CPU *cpu = X86_CPU(obj); 5343 5344 /* We can't fill the features array here because we don't know yet if 5345 * "migratable" is true or false. 5346 */ 5347 cpu->max_features = true; 5348 object_property_set_bool(OBJECT(cpu), "pmu", true, &error_abort); 5349 5350 /* 5351 * these defaults are used for TCG and all other accelerators 5352 * besides KVM and HVF, which overwrite these values 5353 */ 5354 object_property_set_str(OBJECT(cpu), "vendor", CPUID_VENDOR_AMD, 5355 &error_abort); 5356 object_property_set_str(OBJECT(cpu), "model-id", 5357 "QEMU TCG CPU version " QEMU_HW_VERSION, 5358 &error_abort); 5359 } 5360 5361 static const TypeInfo max_x86_cpu_type_info = { 5362 .name = X86_CPU_TYPE_NAME("max"), 5363 .parent = TYPE_X86_CPU, 5364 .instance_init = max_x86_cpu_initfn, 5365 .class_init = max_x86_cpu_class_init, 5366 }; 5367 5368 static char *feature_word_description(FeatureWordInfo *f, uint32_t bit) 5369 { 5370 assert(f->type == CPUID_FEATURE_WORD || f->type == MSR_FEATURE_WORD); 5371 5372 switch (f->type) { 5373 case CPUID_FEATURE_WORD: 5374 { 5375 const char *reg = get_register_name_32(f->cpuid.reg); 5376 assert(reg); 5377 return g_strdup_printf("CPUID.%02XH:%s", 5378 f->cpuid.eax, reg); 5379 } 5380 case MSR_FEATURE_WORD: 5381 return g_strdup_printf("MSR(%02XH)", 5382 f->msr.index); 5383 } 5384 5385 return NULL; 5386 } 5387 5388 static bool x86_cpu_have_filtered_features(X86CPU *cpu) 5389 { 5390 FeatureWord w; 5391 5392 for (w = 0; w < FEATURE_WORDS; w++) { 5393 if (cpu->filtered_features[w]) { 5394 return true; 5395 } 5396 } 5397 5398 return false; 5399 } 5400 5401 static void mark_unavailable_features(X86CPU *cpu, FeatureWord w, uint64_t mask, 5402 const char *verbose_prefix) 5403 { 5404 CPUX86State *env = &cpu->env; 5405 FeatureWordInfo *f = &feature_word_info[w]; 5406 int i; 5407 5408 if (!cpu->force_features) { 5409 env->features[w] &= ~mask; 5410 } 5411 cpu->filtered_features[w] |= mask; 5412 5413 if (!verbose_prefix) { 5414 return; 5415 } 5416 5417 for (i = 0; i < 64; ++i) { 5418 if ((1ULL << i) & mask) { 5419 g_autofree char *feat_word_str = feature_word_description(f, i); 5420 warn_report("%s: %s%s%s [bit %d]", 5421 verbose_prefix, 5422 feat_word_str, 5423 f->feat_names[i] ? "." : "", 5424 f->feat_names[i] ? f->feat_names[i] : "", i); 5425 } 5426 } 5427 } 5428 5429 static void x86_cpuid_version_get_family(Object *obj, Visitor *v, 5430 const char *name, void *opaque, 5431 Error **errp) 5432 { 5433 X86CPU *cpu = X86_CPU(obj); 5434 CPUX86State *env = &cpu->env; 5435 uint64_t value; 5436 5437 value = (env->cpuid_version >> 8) & 0xf; 5438 if (value == 0xf) { 5439 value += (env->cpuid_version >> 20) & 0xff; 5440 } 5441 visit_type_uint64(v, name, &value, errp); 5442 } 5443 5444 static void x86_cpuid_version_set_family(Object *obj, Visitor *v, 5445 const char *name, void *opaque, 5446 Error **errp) 5447 { 5448 X86CPU *cpu = X86_CPU(obj); 5449 CPUX86State *env = &cpu->env; 5450 const uint64_t max = 0xff + 0xf; 5451 uint64_t value; 5452 5453 if (!visit_type_uint64(v, name, &value, errp)) { 5454 return; 5455 } 5456 if (value > max) { 5457 error_setg(errp, "parameter '%s' can be at most %" PRIu64, 5458 name ? name : "null", max); 5459 return; 5460 } 5461 5462 env->cpuid_version &= ~0xff00f00; 5463 if (value > 0x0f) { 5464 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20); 5465 } else { 5466 env->cpuid_version |= value << 8; 5467 } 5468 } 5469 5470 static void x86_cpuid_version_get_model(Object *obj, Visitor *v, 5471 const char *name, void *opaque, 5472 Error **errp) 5473 { 5474 X86CPU *cpu = X86_CPU(obj); 5475 CPUX86State *env = &cpu->env; 5476 uint64_t value; 5477 5478 value = (env->cpuid_version >> 4) & 0xf; 5479 value |= ((env->cpuid_version >> 16) & 0xf) << 4; 5480 visit_type_uint64(v, name, &value, errp); 5481 } 5482 5483 static void x86_cpuid_version_set_model(Object *obj, Visitor *v, 5484 const char *name, void *opaque, 5485 Error **errp) 5486 { 5487 X86CPU *cpu = X86_CPU(obj); 5488 CPUX86State *env = &cpu->env; 5489 const uint64_t max = 0xff; 5490 uint64_t value; 5491 5492 if (!visit_type_uint64(v, name, &value, errp)) { 5493 return; 5494 } 5495 if (value > max) { 5496 error_setg(errp, "parameter '%s' can be at most %" PRIu64, 5497 name ? name : "null", max); 5498 return; 5499 } 5500 5501 env->cpuid_version &= ~0xf00f0; 5502 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16); 5503 } 5504 5505 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v, 5506 const char *name, void *opaque, 5507 Error **errp) 5508 { 5509 X86CPU *cpu = X86_CPU(obj); 5510 CPUX86State *env = &cpu->env; 5511 uint64_t value; 5512 5513 value = env->cpuid_version & 0xf; 5514 visit_type_uint64(v, name, &value, errp); 5515 } 5516 5517 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v, 5518 const char *name, void *opaque, 5519 Error **errp) 5520 { 5521 X86CPU *cpu = X86_CPU(obj); 5522 CPUX86State *env = &cpu->env; 5523 const uint64_t max = 0xf; 5524 uint64_t value; 5525 5526 if (!visit_type_uint64(v, name, &value, errp)) { 5527 return; 5528 } 5529 if (value > max) { 5530 error_setg(errp, "parameter '%s' can be at most %" PRIu64, 5531 name ? name : "null", max); 5532 return; 5533 } 5534 5535 env->cpuid_version &= ~0xf; 5536 env->cpuid_version |= value & 0xf; 5537 } 5538 5539 static char *x86_cpuid_get_vendor(Object *obj, Error **errp) 5540 { 5541 X86CPU *cpu = X86_CPU(obj); 5542 CPUX86State *env = &cpu->env; 5543 char *value; 5544 5545 value = g_malloc(CPUID_VENDOR_SZ + 1); 5546 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2, 5547 env->cpuid_vendor3); 5548 return value; 5549 } 5550 5551 static void x86_cpuid_set_vendor(Object *obj, const char *value, 5552 Error **errp) 5553 { 5554 X86CPU *cpu = X86_CPU(obj); 5555 CPUX86State *env = &cpu->env; 5556 int i; 5557 5558 if (strlen(value) != CPUID_VENDOR_SZ) { 5559 error_setg(errp, "value of property 'vendor' must consist of" 5560 " exactly " stringify(CPUID_VENDOR_SZ) " characters"); 5561 return; 5562 } 5563 5564 env->cpuid_vendor1 = 0; 5565 env->cpuid_vendor2 = 0; 5566 env->cpuid_vendor3 = 0; 5567 for (i = 0; i < 4; i++) { 5568 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i); 5569 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i); 5570 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i); 5571 } 5572 } 5573 5574 static char *x86_cpuid_get_model_id(Object *obj, Error **errp) 5575 { 5576 X86CPU *cpu = X86_CPU(obj); 5577 CPUX86State *env = &cpu->env; 5578 char *value; 5579 int i; 5580 5581 value = g_malloc(48 + 1); 5582 for (i = 0; i < 48; i++) { 5583 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3)); 5584 } 5585 value[48] = '\0'; 5586 return value; 5587 } 5588 5589 static void x86_cpuid_set_model_id(Object *obj, const char *model_id, 5590 Error **errp) 5591 { 5592 X86CPU *cpu = X86_CPU(obj); 5593 CPUX86State *env = &cpu->env; 5594 int c, len, i; 5595 5596 if (model_id == NULL) { 5597 model_id = ""; 5598 } 5599 len = strlen(model_id); 5600 memset(env->cpuid_model, 0, 48); 5601 for (i = 0; i < 48; i++) { 5602 if (i >= len) { 5603 c = '\0'; 5604 } else { 5605 c = (uint8_t)model_id[i]; 5606 } 5607 env->cpuid_model[i >> 2] |= c << (8 * (i & 3)); 5608 } 5609 } 5610 5611 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name, 5612 void *opaque, Error **errp) 5613 { 5614 X86CPU *cpu = X86_CPU(obj); 5615 int64_t value; 5616 5617 value = cpu->env.tsc_khz * 1000; 5618 visit_type_int(v, name, &value, errp); 5619 } 5620 5621 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name, 5622 void *opaque, Error **errp) 5623 { 5624 X86CPU *cpu = X86_CPU(obj); 5625 const int64_t max = INT64_MAX; 5626 int64_t value; 5627 5628 if (!visit_type_int(v, name, &value, errp)) { 5629 return; 5630 } 5631 if (value < 0 || value > max) { 5632 error_setg(errp, "parameter '%s' can be at most %" PRId64, 5633 name ? name : "null", max); 5634 return; 5635 } 5636 5637 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000; 5638 } 5639 5640 /* Generic getter for "feature-words" and "filtered-features" properties */ 5641 static void x86_cpu_get_feature_words(Object *obj, Visitor *v, 5642 const char *name, void *opaque, 5643 Error **errp) 5644 { 5645 uint64_t *array = (uint64_t *)opaque; 5646 FeatureWord w; 5647 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { }; 5648 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { }; 5649 X86CPUFeatureWordInfoList *list = NULL; 5650 5651 for (w = 0; w < FEATURE_WORDS; w++) { 5652 FeatureWordInfo *wi = &feature_word_info[w]; 5653 /* 5654 * We didn't have MSR features when "feature-words" was 5655 * introduced. Therefore skipped other type entries. 5656 */ 5657 if (wi->type != CPUID_FEATURE_WORD) { 5658 continue; 5659 } 5660 X86CPUFeatureWordInfo *qwi = &word_infos[w]; 5661 qwi->cpuid_input_eax = wi->cpuid.eax; 5662 qwi->has_cpuid_input_ecx = wi->cpuid.needs_ecx; 5663 qwi->cpuid_input_ecx = wi->cpuid.ecx; 5664 qwi->cpuid_register = x86_reg_info_32[wi->cpuid.reg].qapi_enum; 5665 qwi->features = array[w]; 5666 5667 /* List will be in reverse order, but order shouldn't matter */ 5668 list_entries[w].next = list; 5669 list_entries[w].value = &word_infos[w]; 5670 list = &list_entries[w]; 5671 } 5672 5673 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp); 5674 } 5675 5676 /* Convert all '_' in a feature string option name to '-', to make feature 5677 * name conform to QOM property naming rule, which uses '-' instead of '_'. 5678 */ 5679 static inline void feat2prop(char *s) 5680 { 5681 while ((s = strchr(s, '_'))) { 5682 *s = '-'; 5683 } 5684 } 5685 5686 /* Return the feature property name for a feature flag bit */ 5687 static const char *x86_cpu_feature_name(FeatureWord w, int bitnr) 5688 { 5689 const char *name; 5690 /* XSAVE components are automatically enabled by other features, 5691 * so return the original feature name instead 5692 */ 5693 if (w == FEAT_XSAVE_XCR0_LO || w == FEAT_XSAVE_XCR0_HI) { 5694 int comp = (w == FEAT_XSAVE_XCR0_HI) ? bitnr + 32 : bitnr; 5695 5696 if (comp < ARRAY_SIZE(x86_ext_save_areas) && 5697 x86_ext_save_areas[comp].bits) { 5698 w = x86_ext_save_areas[comp].feature; 5699 bitnr = ctz32(x86_ext_save_areas[comp].bits); 5700 } 5701 } 5702 5703 assert(bitnr < 64); 5704 assert(w < FEATURE_WORDS); 5705 name = feature_word_info[w].feat_names[bitnr]; 5706 assert(bitnr < 32 || !(name && feature_word_info[w].type == CPUID_FEATURE_WORD)); 5707 return name; 5708 } 5709 5710 /* Compatibility hack to maintain legacy +-feat semantic, 5711 * where +-feat overwrites any feature set by 5712 * feat=on|feat even if the later is parsed after +-feat 5713 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled) 5714 */ 5715 static GList *plus_features, *minus_features; 5716 5717 static gint compare_string(gconstpointer a, gconstpointer b) 5718 { 5719 return g_strcmp0(a, b); 5720 } 5721 5722 /* Parse "+feature,-feature,feature=foo" CPU feature string 5723 */ 5724 static void x86_cpu_parse_featurestr(const char *typename, char *features, 5725 Error **errp) 5726 { 5727 char *featurestr; /* Single 'key=value" string being parsed */ 5728 static bool cpu_globals_initialized; 5729 bool ambiguous = false; 5730 5731 if (cpu_globals_initialized) { 5732 return; 5733 } 5734 cpu_globals_initialized = true; 5735 5736 if (!features) { 5737 return; 5738 } 5739 5740 for (featurestr = strtok(features, ","); 5741 featurestr; 5742 featurestr = strtok(NULL, ",")) { 5743 const char *name; 5744 const char *val = NULL; 5745 char *eq = NULL; 5746 char num[32]; 5747 GlobalProperty *prop; 5748 5749 /* Compatibility syntax: */ 5750 if (featurestr[0] == '+') { 5751 plus_features = g_list_append(plus_features, 5752 g_strdup(featurestr + 1)); 5753 continue; 5754 } else if (featurestr[0] == '-') { 5755 minus_features = g_list_append(minus_features, 5756 g_strdup(featurestr + 1)); 5757 continue; 5758 } 5759 5760 eq = strchr(featurestr, '='); 5761 if (eq) { 5762 *eq++ = 0; 5763 val = eq; 5764 } else { 5765 val = "on"; 5766 } 5767 5768 feat2prop(featurestr); 5769 name = featurestr; 5770 5771 if (g_list_find_custom(plus_features, name, compare_string)) { 5772 warn_report("Ambiguous CPU model string. " 5773 "Don't mix both \"+%s\" and \"%s=%s\"", 5774 name, name, val); 5775 ambiguous = true; 5776 } 5777 if (g_list_find_custom(minus_features, name, compare_string)) { 5778 warn_report("Ambiguous CPU model string. " 5779 "Don't mix both \"-%s\" and \"%s=%s\"", 5780 name, name, val); 5781 ambiguous = true; 5782 } 5783 5784 /* Special case: */ 5785 if (!strcmp(name, "tsc-freq")) { 5786 int ret; 5787 uint64_t tsc_freq; 5788 5789 ret = qemu_strtosz_metric(val, NULL, &tsc_freq); 5790 if (ret < 0 || tsc_freq > INT64_MAX) { 5791 error_setg(errp, "bad numerical value %s", val); 5792 return; 5793 } 5794 snprintf(num, sizeof(num), "%" PRId64, tsc_freq); 5795 val = num; 5796 name = "tsc-frequency"; 5797 } 5798 5799 prop = g_new0(typeof(*prop), 1); 5800 prop->driver = typename; 5801 prop->property = g_strdup(name); 5802 prop->value = g_strdup(val); 5803 qdev_prop_register_global(prop); 5804 } 5805 5806 if (ambiguous) { 5807 warn_report("Compatibility of ambiguous CPU model " 5808 "strings won't be kept on future QEMU versions"); 5809 } 5810 } 5811 5812 static void x86_cpu_filter_features(X86CPU *cpu, bool verbose); 5813 5814 /* Build a list with the name of all features on a feature word array */ 5815 static void x86_cpu_list_feature_names(FeatureWordArray features, 5816 strList **list) 5817 { 5818 strList **tail = list; 5819 FeatureWord w; 5820 5821 for (w = 0; w < FEATURE_WORDS; w++) { 5822 uint64_t filtered = features[w]; 5823 int i; 5824 for (i = 0; i < 64; i++) { 5825 if (filtered & (1ULL << i)) { 5826 QAPI_LIST_APPEND(tail, g_strdup(x86_cpu_feature_name(w, i))); 5827 } 5828 } 5829 } 5830 } 5831 5832 static void x86_cpu_get_unavailable_features(Object *obj, Visitor *v, 5833 const char *name, void *opaque, 5834 Error **errp) 5835 { 5836 X86CPU *xc = X86_CPU(obj); 5837 strList *result = NULL; 5838 5839 x86_cpu_list_feature_names(xc->filtered_features, &result); 5840 visit_type_strList(v, "unavailable-features", &result, errp); 5841 } 5842 5843 /* Print all cpuid feature names in featureset 5844 */ 5845 static void listflags(GList *features) 5846 { 5847 size_t len = 0; 5848 GList *tmp; 5849 5850 for (tmp = features; tmp; tmp = tmp->next) { 5851 const char *name = tmp->data; 5852 if ((len + strlen(name) + 1) >= 75) { 5853 qemu_printf("\n"); 5854 len = 0; 5855 } 5856 qemu_printf("%s%s", len == 0 ? " " : " ", name); 5857 len += strlen(name) + 1; 5858 } 5859 qemu_printf("\n"); 5860 } 5861 5862 /* Sort alphabetically by type name, respecting X86CPUClass::ordering. */ 5863 static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b) 5864 { 5865 ObjectClass *class_a = (ObjectClass *)a; 5866 ObjectClass *class_b = (ObjectClass *)b; 5867 X86CPUClass *cc_a = X86_CPU_CLASS(class_a); 5868 X86CPUClass *cc_b = X86_CPU_CLASS(class_b); 5869 int ret; 5870 5871 if (cc_a->ordering != cc_b->ordering) { 5872 ret = cc_a->ordering - cc_b->ordering; 5873 } else { 5874 g_autofree char *name_a = x86_cpu_class_get_model_name(cc_a); 5875 g_autofree char *name_b = x86_cpu_class_get_model_name(cc_b); 5876 ret = strcmp(name_a, name_b); 5877 } 5878 return ret; 5879 } 5880 5881 static GSList *get_sorted_cpu_model_list(void) 5882 { 5883 GSList *list = object_class_get_list(TYPE_X86_CPU, false); 5884 list = g_slist_sort(list, x86_cpu_list_compare); 5885 return list; 5886 } 5887 5888 static char *x86_cpu_class_get_model_id(X86CPUClass *xc) 5889 { 5890 Object *obj = object_new_with_class(OBJECT_CLASS(xc)); 5891 char *r = object_property_get_str(obj, "model-id", &error_abort); 5892 object_unref(obj); 5893 return r; 5894 } 5895 5896 static char *x86_cpu_class_get_alias_of(X86CPUClass *cc) 5897 { 5898 X86CPUVersion version; 5899 5900 if (!cc->model || !cc->model->is_alias) { 5901 return NULL; 5902 } 5903 version = x86_cpu_model_resolve_version(cc->model); 5904 if (version <= 0) { 5905 return NULL; 5906 } 5907 return x86_cpu_versioned_model_name(cc->model->cpudef, version); 5908 } 5909 5910 static void x86_cpu_list_entry(gpointer data, gpointer user_data) 5911 { 5912 ObjectClass *oc = data; 5913 X86CPUClass *cc = X86_CPU_CLASS(oc); 5914 g_autofree char *name = x86_cpu_class_get_model_name(cc); 5915 g_autofree char *desc = g_strdup(cc->model_description); 5916 g_autofree char *alias_of = x86_cpu_class_get_alias_of(cc); 5917 g_autofree char *model_id = x86_cpu_class_get_model_id(cc); 5918 5919 if (!desc && alias_of) { 5920 if (cc->model && cc->model->version == CPU_VERSION_AUTO) { 5921 desc = g_strdup("(alias configured by machine type)"); 5922 } else { 5923 desc = g_strdup_printf("(alias of %s)", alias_of); 5924 } 5925 } 5926 if (!desc && cc->model && cc->model->note) { 5927 desc = g_strdup_printf("%s [%s]", model_id, cc->model->note); 5928 } 5929 if (!desc) { 5930 desc = g_strdup_printf("%s", model_id); 5931 } 5932 5933 if (cc->model && cc->model->cpudef->deprecation_note) { 5934 g_autofree char *olddesc = desc; 5935 desc = g_strdup_printf("%s (deprecated)", olddesc); 5936 } 5937 5938 qemu_printf(" %-20s %s\n", name, desc); 5939 } 5940 5941 /* list available CPU models and flags */ 5942 void x86_cpu_list(void) 5943 { 5944 int i, j; 5945 GSList *list; 5946 GList *names = NULL; 5947 5948 qemu_printf("Available CPUs:\n"); 5949 list = get_sorted_cpu_model_list(); 5950 g_slist_foreach(list, x86_cpu_list_entry, NULL); 5951 g_slist_free(list); 5952 5953 names = NULL; 5954 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) { 5955 FeatureWordInfo *fw = &feature_word_info[i]; 5956 for (j = 0; j < 64; j++) { 5957 if (fw->feat_names[j]) { 5958 names = g_list_append(names, (gpointer)fw->feat_names[j]); 5959 } 5960 } 5961 } 5962 5963 names = g_list_sort(names, (GCompareFunc)strcmp); 5964 5965 qemu_printf("\nRecognized CPUID flags:\n"); 5966 listflags(names); 5967 qemu_printf("\n"); 5968 g_list_free(names); 5969 } 5970 5971 #ifndef CONFIG_USER_ONLY 5972 5973 /* Check for missing features that may prevent the CPU class from 5974 * running using the current machine and accelerator. 5975 */ 5976 static void x86_cpu_class_check_missing_features(X86CPUClass *xcc, 5977 strList **list) 5978 { 5979 strList **tail = list; 5980 X86CPU *xc; 5981 Error *err = NULL; 5982 5983 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) { 5984 QAPI_LIST_APPEND(tail, g_strdup("kvm")); 5985 return; 5986 } 5987 5988 xc = X86_CPU(object_new_with_class(OBJECT_CLASS(xcc))); 5989 5990 x86_cpu_expand_features(xc, &err); 5991 if (err) { 5992 /* Errors at x86_cpu_expand_features should never happen, 5993 * but in case it does, just report the model as not 5994 * runnable at all using the "type" property. 5995 */ 5996 QAPI_LIST_APPEND(tail, g_strdup("type")); 5997 error_free(err); 5998 } 5999 6000 x86_cpu_filter_features(xc, false); 6001 6002 x86_cpu_list_feature_names(xc->filtered_features, tail); 6003 6004 object_unref(OBJECT(xc)); 6005 } 6006 6007 static void x86_cpu_definition_entry(gpointer data, gpointer user_data) 6008 { 6009 ObjectClass *oc = data; 6010 X86CPUClass *cc = X86_CPU_CLASS(oc); 6011 CpuDefinitionInfoList **cpu_list = user_data; 6012 CpuDefinitionInfo *info; 6013 6014 info = g_malloc0(sizeof(*info)); 6015 info->name = x86_cpu_class_get_model_name(cc); 6016 x86_cpu_class_check_missing_features(cc, &info->unavailable_features); 6017 info->has_unavailable_features = true; 6018 info->q_typename = g_strdup(object_class_get_name(oc)); 6019 info->migration_safe = cc->migration_safe; 6020 info->has_migration_safe = true; 6021 info->q_static = cc->static_model; 6022 if (cc->model && cc->model->cpudef->deprecation_note) { 6023 info->deprecated = true; 6024 } else { 6025 info->deprecated = false; 6026 } 6027 /* 6028 * Old machine types won't report aliases, so that alias translation 6029 * doesn't break compatibility with previous QEMU versions. 6030 */ 6031 if (default_cpu_version != CPU_VERSION_LEGACY) { 6032 info->alias_of = x86_cpu_class_get_alias_of(cc); 6033 } 6034 6035 QAPI_LIST_PREPEND(*cpu_list, info); 6036 } 6037 6038 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) 6039 { 6040 CpuDefinitionInfoList *cpu_list = NULL; 6041 GSList *list = get_sorted_cpu_model_list(); 6042 g_slist_foreach(list, x86_cpu_definition_entry, &cpu_list); 6043 g_slist_free(list); 6044 return cpu_list; 6045 } 6046 6047 #endif /* !CONFIG_USER_ONLY */ 6048 6049 uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w) 6050 { 6051 FeatureWordInfo *wi = &feature_word_info[w]; 6052 uint64_t r = 0; 6053 uint64_t unavail = 0; 6054 6055 if (kvm_enabled()) { 6056 switch (wi->type) { 6057 case CPUID_FEATURE_WORD: 6058 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid.eax, 6059 wi->cpuid.ecx, 6060 wi->cpuid.reg); 6061 break; 6062 case MSR_FEATURE_WORD: 6063 r = kvm_arch_get_supported_msr_feature(kvm_state, 6064 wi->msr.index); 6065 break; 6066 } 6067 } else if (hvf_enabled()) { 6068 if (wi->type != CPUID_FEATURE_WORD) { 6069 return 0; 6070 } 6071 r = hvf_get_supported_cpuid(wi->cpuid.eax, 6072 wi->cpuid.ecx, 6073 wi->cpuid.reg); 6074 } else if (tcg_enabled()) { 6075 r = wi->tcg_features; 6076 } else { 6077 return ~0; 6078 } 6079 6080 switch (w) { 6081 #ifndef TARGET_X86_64 6082 case FEAT_8000_0001_EDX: 6083 /* 6084 * 32-bit TCG can emulate 64-bit compatibility mode. If there is no 6085 * way for userspace to get out of its 32-bit jail, we can leave 6086 * the LM bit set. 6087 */ 6088 unavail = tcg_enabled() 6089 ? CPUID_EXT2_LM & ~CPUID_EXT2_KERNEL_FEATURES 6090 : CPUID_EXT2_LM; 6091 break; 6092 #endif 6093 6094 case FEAT_8000_0007_EBX: 6095 if (cpu && !IS_AMD_CPU(&cpu->env)) { 6096 /* Disable AMD machine check architecture for Intel CPU. */ 6097 unavail = ~0; 6098 } 6099 break; 6100 6101 case FEAT_7_0_EBX: 6102 #ifndef CONFIG_USER_ONLY 6103 if (!check_sgx_support()) { 6104 unavail = CPUID_7_0_EBX_SGX; 6105 } 6106 #endif 6107 break; 6108 case FEAT_7_0_ECX: 6109 #ifndef CONFIG_USER_ONLY 6110 if (!check_sgx_support()) { 6111 unavail = CPUID_7_0_ECX_SGX_LC; 6112 } 6113 #endif 6114 break; 6115 6116 default: 6117 break; 6118 } 6119 6120 r &= ~unavail; 6121 if (cpu && cpu->migratable) { 6122 r &= x86_cpu_get_migratable_flags(w); 6123 } 6124 return r; 6125 } 6126 6127 static void x86_cpu_get_supported_cpuid(uint32_t func, uint32_t index, 6128 uint32_t *eax, uint32_t *ebx, 6129 uint32_t *ecx, uint32_t *edx) 6130 { 6131 if (kvm_enabled()) { 6132 *eax = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EAX); 6133 *ebx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EBX); 6134 *ecx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_ECX); 6135 *edx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EDX); 6136 } else if (hvf_enabled()) { 6137 *eax = hvf_get_supported_cpuid(func, index, R_EAX); 6138 *ebx = hvf_get_supported_cpuid(func, index, R_EBX); 6139 *ecx = hvf_get_supported_cpuid(func, index, R_ECX); 6140 *edx = hvf_get_supported_cpuid(func, index, R_EDX); 6141 } else { 6142 *eax = 0; 6143 *ebx = 0; 6144 *ecx = 0; 6145 *edx = 0; 6146 } 6147 } 6148 6149 static void x86_cpu_get_cache_cpuid(uint32_t func, uint32_t index, 6150 uint32_t *eax, uint32_t *ebx, 6151 uint32_t *ecx, uint32_t *edx) 6152 { 6153 uint32_t level, unused; 6154 6155 /* Only return valid host leaves. */ 6156 switch (func) { 6157 case 2: 6158 case 4: 6159 host_cpuid(0, 0, &level, &unused, &unused, &unused); 6160 break; 6161 case 0x80000005: 6162 case 0x80000006: 6163 case 0x8000001d: 6164 host_cpuid(0x80000000, 0, &level, &unused, &unused, &unused); 6165 break; 6166 default: 6167 return; 6168 } 6169 6170 if (func > level) { 6171 *eax = 0; 6172 *ebx = 0; 6173 *ecx = 0; 6174 *edx = 0; 6175 } else { 6176 host_cpuid(func, index, eax, ebx, ecx, edx); 6177 } 6178 } 6179 6180 /* 6181 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 6182 */ 6183 void x86_cpu_apply_props(X86CPU *cpu, PropValue *props) 6184 { 6185 PropValue *pv; 6186 for (pv = props; pv->prop; pv++) { 6187 if (!pv->value) { 6188 continue; 6189 } 6190 object_property_parse(OBJECT(cpu), pv->prop, pv->value, 6191 &error_abort); 6192 } 6193 } 6194 6195 /* 6196 * Apply properties for the CPU model version specified in model. 6197 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 6198 */ 6199 6200 static void x86_cpu_apply_version_props(X86CPU *cpu, X86CPUModel *model) 6201 { 6202 const X86CPUVersionDefinition *vdef; 6203 X86CPUVersion version = x86_cpu_model_resolve_version(model); 6204 6205 if (version == CPU_VERSION_LEGACY) { 6206 return; 6207 } 6208 6209 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) { 6210 PropValue *p; 6211 6212 for (p = vdef->props; p && p->prop; p++) { 6213 object_property_parse(OBJECT(cpu), p->prop, p->value, 6214 &error_abort); 6215 } 6216 6217 if (vdef->version == version) { 6218 break; 6219 } 6220 } 6221 6222 /* 6223 * If we reached the end of the list, version number was invalid 6224 */ 6225 assert(vdef->version == version); 6226 } 6227 6228 static const CPUCaches *x86_cpu_get_versioned_cache_info(X86CPU *cpu, 6229 X86CPUModel *model) 6230 { 6231 const X86CPUVersionDefinition *vdef; 6232 X86CPUVersion version = x86_cpu_model_resolve_version(model); 6233 const CPUCaches *cache_info = model->cpudef->cache_info; 6234 6235 if (version == CPU_VERSION_LEGACY) { 6236 return cache_info; 6237 } 6238 6239 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) { 6240 if (vdef->cache_info) { 6241 cache_info = vdef->cache_info; 6242 } 6243 6244 if (vdef->version == version) { 6245 break; 6246 } 6247 } 6248 6249 assert(vdef->version == version); 6250 return cache_info; 6251 } 6252 6253 /* 6254 * Load data from X86CPUDefinition into a X86CPU object. 6255 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 6256 */ 6257 static void x86_cpu_load_model(X86CPU *cpu, X86CPUModel *model) 6258 { 6259 const X86CPUDefinition *def = model->cpudef; 6260 CPUX86State *env = &cpu->env; 6261 FeatureWord w; 6262 6263 /*NOTE: any property set by this function should be returned by 6264 * x86_cpu_static_props(), so static expansion of 6265 * query-cpu-model-expansion is always complete. 6266 */ 6267 6268 /* CPU models only set _minimum_ values for level/xlevel: */ 6269 object_property_set_uint(OBJECT(cpu), "min-level", def->level, 6270 &error_abort); 6271 object_property_set_uint(OBJECT(cpu), "min-xlevel", def->xlevel, 6272 &error_abort); 6273 6274 object_property_set_int(OBJECT(cpu), "family", def->family, &error_abort); 6275 object_property_set_int(OBJECT(cpu), "model", def->model, &error_abort); 6276 object_property_set_int(OBJECT(cpu), "stepping", def->stepping, 6277 &error_abort); 6278 object_property_set_str(OBJECT(cpu), "model-id", def->model_id, 6279 &error_abort); 6280 for (w = 0; w < FEATURE_WORDS; w++) { 6281 env->features[w] = def->features[w]; 6282 } 6283 6284 /* legacy-cache defaults to 'off' if CPU model provides cache info */ 6285 cpu->legacy_cache = !x86_cpu_get_versioned_cache_info(cpu, model); 6286 6287 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR; 6288 6289 /* sysenter isn't supported in compatibility mode on AMD, 6290 * syscall isn't supported in compatibility mode on Intel. 6291 * Normally we advertise the actual CPU vendor, but you can 6292 * override this using the 'vendor' property if you want to use 6293 * KVM's sysenter/syscall emulation in compatibility mode and 6294 * when doing cross vendor migration 6295 */ 6296 6297 /* 6298 * vendor property is set here but then overloaded with the 6299 * host cpu vendor for KVM and HVF. 6300 */ 6301 object_property_set_str(OBJECT(cpu), "vendor", def->vendor, &error_abort); 6302 6303 x86_cpu_apply_version_props(cpu, model); 6304 6305 /* 6306 * Properties in versioned CPU model are not user specified features. 6307 * We can simply clear env->user_features here since it will be filled later 6308 * in x86_cpu_expand_features() based on plus_features and minus_features. 6309 */ 6310 memset(&env->user_features, 0, sizeof(env->user_features)); 6311 } 6312 6313 static const gchar *x86_gdb_arch_name(CPUState *cs) 6314 { 6315 #ifdef TARGET_X86_64 6316 return "i386:x86-64"; 6317 #else 6318 return "i386"; 6319 #endif 6320 } 6321 6322 static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data) 6323 { 6324 X86CPUModel *model = data; 6325 X86CPUClass *xcc = X86_CPU_CLASS(oc); 6326 CPUClass *cc = CPU_CLASS(oc); 6327 6328 xcc->model = model; 6329 xcc->migration_safe = true; 6330 cc->deprecation_note = model->cpudef->deprecation_note; 6331 } 6332 6333 static void x86_register_cpu_model_type(const char *name, X86CPUModel *model) 6334 { 6335 g_autofree char *typename = x86_cpu_type_name(name); 6336 TypeInfo ti = { 6337 .name = typename, 6338 .parent = TYPE_X86_CPU, 6339 .class_init = x86_cpu_cpudef_class_init, 6340 .class_data = model, 6341 }; 6342 6343 type_register(&ti); 6344 } 6345 6346 6347 /* 6348 * register builtin_x86_defs; 6349 * "max", "base" and subclasses ("host") are not registered here. 6350 * See x86_cpu_register_types for all model registrations. 6351 */ 6352 static void x86_register_cpudef_types(const X86CPUDefinition *def) 6353 { 6354 X86CPUModel *m; 6355 const X86CPUVersionDefinition *vdef; 6356 6357 /* AMD aliases are handled at runtime based on CPUID vendor, so 6358 * they shouldn't be set on the CPU model table. 6359 */ 6360 assert(!(def->features[FEAT_8000_0001_EDX] & CPUID_EXT2_AMD_ALIASES)); 6361 /* catch mistakes instead of silently truncating model_id when too long */ 6362 assert(def->model_id && strlen(def->model_id) <= 48); 6363 6364 /* Unversioned model: */ 6365 m = g_new0(X86CPUModel, 1); 6366 m->cpudef = def; 6367 m->version = CPU_VERSION_AUTO; 6368 m->is_alias = true; 6369 x86_register_cpu_model_type(def->name, m); 6370 6371 /* Versioned models: */ 6372 6373 for (vdef = x86_cpu_def_get_versions(def); vdef->version; vdef++) { 6374 g_autofree char *name = 6375 x86_cpu_versioned_model_name(def, vdef->version); 6376 6377 m = g_new0(X86CPUModel, 1); 6378 m->cpudef = def; 6379 m->version = vdef->version; 6380 m->note = vdef->note; 6381 x86_register_cpu_model_type(name, m); 6382 6383 if (vdef->alias) { 6384 X86CPUModel *am = g_new0(X86CPUModel, 1); 6385 am->cpudef = def; 6386 am->version = vdef->version; 6387 am->is_alias = true; 6388 x86_register_cpu_model_type(vdef->alias, am); 6389 } 6390 } 6391 6392 } 6393 6394 uint32_t cpu_x86_virtual_addr_width(CPUX86State *env) 6395 { 6396 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57) { 6397 return 57; /* 57 bits virtual */ 6398 } else { 6399 return 48; /* 48 bits virtual */ 6400 } 6401 } 6402 6403 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, 6404 uint32_t *eax, uint32_t *ebx, 6405 uint32_t *ecx, uint32_t *edx) 6406 { 6407 X86CPU *cpu = env_archcpu(env); 6408 CPUState *cs = env_cpu(env); 6409 uint32_t limit; 6410 uint32_t signature[3]; 6411 X86CPUTopoInfo topo_info; 6412 uint32_t cores_per_pkg; 6413 uint32_t threads_per_pkg; 6414 6415 topo_info.dies_per_pkg = env->nr_dies; 6416 topo_info.modules_per_die = env->nr_modules; 6417 topo_info.cores_per_module = cs->nr_cores / env->nr_dies / env->nr_modules; 6418 topo_info.threads_per_core = cs->nr_threads; 6419 6420 cores_per_pkg = topo_info.cores_per_module * topo_info.modules_per_die * 6421 topo_info.dies_per_pkg; 6422 threads_per_pkg = cores_per_pkg * topo_info.threads_per_core; 6423 6424 /* Calculate & apply limits for different index ranges */ 6425 if (index >= 0xC0000000) { 6426 limit = env->cpuid_xlevel2; 6427 } else if (index >= 0x80000000) { 6428 limit = env->cpuid_xlevel; 6429 } else if (index >= 0x40000000) { 6430 limit = 0x40000001; 6431 } else { 6432 limit = env->cpuid_level; 6433 } 6434 6435 if (index > limit) { 6436 /* Intel documentation states that invalid EAX input will 6437 * return the same information as EAX=cpuid_level 6438 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID) 6439 */ 6440 index = env->cpuid_level; 6441 } 6442 6443 switch(index) { 6444 case 0: 6445 *eax = env->cpuid_level; 6446 *ebx = env->cpuid_vendor1; 6447 *edx = env->cpuid_vendor2; 6448 *ecx = env->cpuid_vendor3; 6449 break; 6450 case 1: 6451 *eax = env->cpuid_version; 6452 *ebx = (cpu->apic_id << 24) | 6453 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */ 6454 *ecx = env->features[FEAT_1_ECX]; 6455 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) { 6456 *ecx |= CPUID_EXT_OSXSAVE; 6457 } 6458 *edx = env->features[FEAT_1_EDX]; 6459 if (threads_per_pkg > 1) { 6460 *ebx |= threads_per_pkg << 16; 6461 *edx |= CPUID_HT; 6462 } 6463 if (!cpu->enable_pmu) { 6464 *ecx &= ~CPUID_EXT_PDCM; 6465 } 6466 break; 6467 case 2: 6468 /* cache info: needed for Pentium Pro compatibility */ 6469 if (cpu->cache_info_passthrough) { 6470 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 6471 break; 6472 } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { 6473 *eax = *ebx = *ecx = *edx = 0; 6474 break; 6475 } 6476 *eax = 1; /* Number of CPUID[EAX=2] calls required */ 6477 *ebx = 0; 6478 if (!cpu->enable_l3_cache) { 6479 *ecx = 0; 6480 } else { 6481 *ecx = cpuid2_cache_descriptor(env->cache_info_cpuid2.l3_cache); 6482 } 6483 *edx = (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1d_cache) << 16) | 6484 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1i_cache) << 8) | 6485 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l2_cache)); 6486 break; 6487 case 4: 6488 /* cache info: needed for Core compatibility */ 6489 if (cpu->cache_info_passthrough) { 6490 x86_cpu_get_cache_cpuid(index, count, eax, ebx, ecx, edx); 6491 /* 6492 * QEMU has its own number of cores/logical cpus, 6493 * set 24..14, 31..26 bit to configured values 6494 */ 6495 if (*eax & 31) { 6496 int host_vcpus_per_cache = 1 + ((*eax & 0x3FFC000) >> 14); 6497 6498 *eax &= ~0xFC000000; 6499 *eax |= max_core_ids_in_package(&topo_info) << 26; 6500 if (host_vcpus_per_cache > threads_per_pkg) { 6501 *eax &= ~0x3FFC000; 6502 6503 /* Share the cache at package level. */ 6504 *eax |= max_thread_ids_for_cache(&topo_info, 6505 CPU_TOPO_LEVEL_PACKAGE) << 14; 6506 } 6507 } 6508 } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { 6509 *eax = *ebx = *ecx = *edx = 0; 6510 } else { 6511 *eax = 0; 6512 6513 switch (count) { 6514 case 0: /* L1 dcache info */ 6515 encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache, 6516 &topo_info, 6517 eax, ebx, ecx, edx); 6518 if (!cpu->l1_cache_per_core) { 6519 *eax &= ~MAKE_64BIT_MASK(14, 12); 6520 } 6521 break; 6522 case 1: /* L1 icache info */ 6523 encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache, 6524 &topo_info, 6525 eax, ebx, ecx, edx); 6526 if (!cpu->l1_cache_per_core) { 6527 *eax &= ~MAKE_64BIT_MASK(14, 12); 6528 } 6529 break; 6530 case 2: /* L2 cache info */ 6531 encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache, 6532 &topo_info, 6533 eax, ebx, ecx, edx); 6534 break; 6535 case 3: /* L3 cache info */ 6536 if (cpu->enable_l3_cache) { 6537 encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache, 6538 &topo_info, 6539 eax, ebx, ecx, edx); 6540 break; 6541 } 6542 /* fall through */ 6543 default: /* end of info */ 6544 *eax = *ebx = *ecx = *edx = 0; 6545 break; 6546 } 6547 } 6548 break; 6549 case 5: 6550 /* MONITOR/MWAIT Leaf */ 6551 *eax = cpu->mwait.eax; /* Smallest monitor-line size in bytes */ 6552 *ebx = cpu->mwait.ebx; /* Largest monitor-line size in bytes */ 6553 *ecx = cpu->mwait.ecx; /* flags */ 6554 *edx = cpu->mwait.edx; /* mwait substates */ 6555 break; 6556 case 6: 6557 /* Thermal and Power Leaf */ 6558 *eax = env->features[FEAT_6_EAX]; 6559 *ebx = 0; 6560 *ecx = 0; 6561 *edx = 0; 6562 break; 6563 case 7: 6564 /* Structured Extended Feature Flags Enumeration Leaf */ 6565 if (count == 0) { 6566 /* Maximum ECX value for sub-leaves */ 6567 *eax = env->cpuid_level_func7; 6568 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */ 6569 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */ 6570 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) { 6571 *ecx |= CPUID_7_0_ECX_OSPKE; 6572 } 6573 *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */ 6574 } else if (count == 1) { 6575 *eax = env->features[FEAT_7_1_EAX]; 6576 *edx = env->features[FEAT_7_1_EDX]; 6577 *ebx = 0; 6578 *ecx = 0; 6579 } else if (count == 2) { 6580 *edx = env->features[FEAT_7_2_EDX]; 6581 *eax = 0; 6582 *ebx = 0; 6583 *ecx = 0; 6584 } else { 6585 *eax = 0; 6586 *ebx = 0; 6587 *ecx = 0; 6588 *edx = 0; 6589 } 6590 break; 6591 case 9: 6592 /* Direct Cache Access Information Leaf */ 6593 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */ 6594 *ebx = 0; 6595 *ecx = 0; 6596 *edx = 0; 6597 break; 6598 case 0xA: 6599 /* Architectural Performance Monitoring Leaf */ 6600 if (cpu->enable_pmu) { 6601 x86_cpu_get_supported_cpuid(0xA, count, eax, ebx, ecx, edx); 6602 } else { 6603 *eax = 0; 6604 *ebx = 0; 6605 *ecx = 0; 6606 *edx = 0; 6607 } 6608 break; 6609 case 0xB: 6610 /* Extended Topology Enumeration Leaf */ 6611 if (!cpu->enable_cpuid_0xb) { 6612 *eax = *ebx = *ecx = *edx = 0; 6613 break; 6614 } 6615 6616 *ecx = count & 0xff; 6617 *edx = cpu->apic_id; 6618 6619 switch (count) { 6620 case 0: 6621 *eax = apicid_core_offset(&topo_info); 6622 *ebx = topo_info.threads_per_core; 6623 *ecx |= CPUID_B_ECX_TOPO_LEVEL_SMT << 8; 6624 break; 6625 case 1: 6626 *eax = apicid_pkg_offset(&topo_info); 6627 *ebx = threads_per_pkg; 6628 *ecx |= CPUID_B_ECX_TOPO_LEVEL_CORE << 8; 6629 break; 6630 default: 6631 *eax = 0; 6632 *ebx = 0; 6633 *ecx |= CPUID_B_ECX_TOPO_LEVEL_INVALID << 8; 6634 } 6635 6636 assert(!(*eax & ~0x1f)); 6637 *ebx &= 0xffff; /* The count doesn't need to be reliable. */ 6638 break; 6639 case 0x1C: 6640 if (cpu->enable_pmu && (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) { 6641 x86_cpu_get_supported_cpuid(0x1C, 0, eax, ebx, ecx, edx); 6642 *edx = 0; 6643 } 6644 break; 6645 case 0x1F: 6646 /* V2 Extended Topology Enumeration Leaf */ 6647 if (!x86_has_extended_topo(env->avail_cpu_topo)) { 6648 *eax = *ebx = *ecx = *edx = 0; 6649 break; 6650 } 6651 6652 encode_topo_cpuid1f(env, count, &topo_info, eax, ebx, ecx, edx); 6653 break; 6654 case 0xD: { 6655 /* Processor Extended State */ 6656 *eax = 0; 6657 *ebx = 0; 6658 *ecx = 0; 6659 *edx = 0; 6660 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { 6661 break; 6662 } 6663 6664 if (count == 0) { 6665 *ecx = xsave_area_size(x86_cpu_xsave_xcr0_components(cpu), false); 6666 *eax = env->features[FEAT_XSAVE_XCR0_LO]; 6667 *edx = env->features[FEAT_XSAVE_XCR0_HI]; 6668 /* 6669 * The initial value of xcr0 and ebx == 0, On host without kvm 6670 * commit 412a3c41(e.g., CentOS 6), the ebx's value always == 0 6671 * even through guest update xcr0, this will crash some legacy guest 6672 * (e.g., CentOS 6), So set ebx == ecx to workaround it. 6673 */ 6674 *ebx = kvm_enabled() ? *ecx : xsave_area_size(env->xcr0, false); 6675 } else if (count == 1) { 6676 uint64_t xstate = x86_cpu_xsave_xcr0_components(cpu) | 6677 x86_cpu_xsave_xss_components(cpu); 6678 6679 *eax = env->features[FEAT_XSAVE]; 6680 *ebx = xsave_area_size(xstate, true); 6681 *ecx = env->features[FEAT_XSAVE_XSS_LO]; 6682 *edx = env->features[FEAT_XSAVE_XSS_HI]; 6683 if (kvm_enabled() && cpu->enable_pmu && 6684 (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR) && 6685 (*eax & CPUID_XSAVE_XSAVES)) { 6686 *ecx |= XSTATE_ARCH_LBR_MASK; 6687 } else { 6688 *ecx &= ~XSTATE_ARCH_LBR_MASK; 6689 } 6690 } else if (count == 0xf && cpu->enable_pmu 6691 && (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) { 6692 x86_cpu_get_supported_cpuid(0xD, count, eax, ebx, ecx, edx); 6693 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) { 6694 const ExtSaveArea *esa = &x86_ext_save_areas[count]; 6695 6696 if (x86_cpu_xsave_xcr0_components(cpu) & (1ULL << count)) { 6697 *eax = esa->size; 6698 *ebx = esa->offset; 6699 *ecx = esa->ecx & 6700 (ESA_FEATURE_ALIGN64_MASK | ESA_FEATURE_XFD_MASK); 6701 } else if (x86_cpu_xsave_xss_components(cpu) & (1ULL << count)) { 6702 *eax = esa->size; 6703 *ebx = 0; 6704 *ecx = 1; 6705 } 6706 } 6707 break; 6708 } 6709 case 0x12: 6710 #ifndef CONFIG_USER_ONLY 6711 if (!kvm_enabled() || 6712 !(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX)) { 6713 *eax = *ebx = *ecx = *edx = 0; 6714 break; 6715 } 6716 6717 /* 6718 * SGX sub-leafs CPUID.0x12.{0x2..N} enumerate EPC sections. Retrieve 6719 * the EPC properties, e.g. confidentiality and integrity, from the 6720 * host's first EPC section, i.e. assume there is one EPC section or 6721 * that all EPC sections have the same security properties. 6722 */ 6723 if (count > 1) { 6724 uint64_t epc_addr, epc_size; 6725 6726 if (sgx_epc_get_section(count - 2, &epc_addr, &epc_size)) { 6727 *eax = *ebx = *ecx = *edx = 0; 6728 break; 6729 } 6730 host_cpuid(index, 2, eax, ebx, ecx, edx); 6731 *eax = (uint32_t)(epc_addr & 0xfffff000) | 0x1; 6732 *ebx = (uint32_t)(epc_addr >> 32); 6733 *ecx = (uint32_t)(epc_size & 0xfffff000) | (*ecx & 0xf); 6734 *edx = (uint32_t)(epc_size >> 32); 6735 break; 6736 } 6737 6738 /* 6739 * SGX sub-leafs CPUID.0x12.{0x0,0x1} are heavily dependent on hardware 6740 * and KVM, i.e. QEMU cannot emulate features to override what KVM 6741 * supports. Features can be further restricted by userspace, but not 6742 * made more permissive. 6743 */ 6744 x86_cpu_get_supported_cpuid(0x12, count, eax, ebx, ecx, edx); 6745 6746 if (count == 0) { 6747 *eax &= env->features[FEAT_SGX_12_0_EAX]; 6748 *ebx &= env->features[FEAT_SGX_12_0_EBX]; 6749 } else { 6750 *eax &= env->features[FEAT_SGX_12_1_EAX]; 6751 *ebx &= 0; /* ebx reserve */ 6752 *ecx &= env->features[FEAT_XSAVE_XCR0_LO]; 6753 *edx &= env->features[FEAT_XSAVE_XCR0_HI]; 6754 6755 /* FP and SSE are always allowed regardless of XSAVE/XCR0. */ 6756 *ecx |= XSTATE_FP_MASK | XSTATE_SSE_MASK; 6757 6758 /* Access to PROVISIONKEY requires additional credentials. */ 6759 if ((*eax & (1U << 4)) && 6760 !kvm_enable_sgx_provisioning(cs->kvm_state)) { 6761 *eax &= ~(1U << 4); 6762 } 6763 } 6764 #endif 6765 break; 6766 case 0x14: { 6767 /* Intel Processor Trace Enumeration */ 6768 *eax = 0; 6769 *ebx = 0; 6770 *ecx = 0; 6771 *edx = 0; 6772 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) || 6773 !kvm_enabled()) { 6774 break; 6775 } 6776 6777 /* 6778 * If these are changed, they should stay in sync with 6779 * x86_cpu_filter_features(). 6780 */ 6781 if (count == 0) { 6782 *eax = INTEL_PT_MAX_SUBLEAF; 6783 *ebx = INTEL_PT_MINIMAL_EBX; 6784 *ecx = INTEL_PT_MINIMAL_ECX; 6785 if (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP) { 6786 *ecx |= CPUID_14_0_ECX_LIP; 6787 } 6788 } else if (count == 1) { 6789 *eax = INTEL_PT_MTC_BITMAP | INTEL_PT_ADDR_RANGES_NUM; 6790 *ebx = INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP; 6791 } 6792 break; 6793 } 6794 case 0x1D: { 6795 /* AMX TILE, for now hardcoded for Sapphire Rapids*/ 6796 *eax = 0; 6797 *ebx = 0; 6798 *ecx = 0; 6799 *edx = 0; 6800 if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) { 6801 break; 6802 } 6803 6804 if (count == 0) { 6805 /* Highest numbered palette subleaf */ 6806 *eax = INTEL_AMX_TILE_MAX_SUBLEAF; 6807 } else if (count == 1) { 6808 *eax = INTEL_AMX_TOTAL_TILE_BYTES | 6809 (INTEL_AMX_BYTES_PER_TILE << 16); 6810 *ebx = INTEL_AMX_BYTES_PER_ROW | (INTEL_AMX_TILE_MAX_NAMES << 16); 6811 *ecx = INTEL_AMX_TILE_MAX_ROWS; 6812 } 6813 break; 6814 } 6815 case 0x1E: { 6816 /* AMX TMUL, for now hardcoded for Sapphire Rapids */ 6817 *eax = 0; 6818 *ebx = 0; 6819 *ecx = 0; 6820 *edx = 0; 6821 if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) { 6822 break; 6823 } 6824 6825 if (count == 0) { 6826 /* Highest numbered palette subleaf */ 6827 *ebx = INTEL_AMX_TMUL_MAX_K | (INTEL_AMX_TMUL_MAX_N << 8); 6828 } 6829 break; 6830 } 6831 case 0x40000000: 6832 /* 6833 * CPUID code in kvm_arch_init_vcpu() ignores stuff 6834 * set here, but we restrict to TCG none the less. 6835 */ 6836 if (tcg_enabled() && cpu->expose_tcg) { 6837 memcpy(signature, "TCGTCGTCGTCG", 12); 6838 *eax = 0x40000001; 6839 *ebx = signature[0]; 6840 *ecx = signature[1]; 6841 *edx = signature[2]; 6842 } else { 6843 *eax = 0; 6844 *ebx = 0; 6845 *ecx = 0; 6846 *edx = 0; 6847 } 6848 break; 6849 case 0x40000001: 6850 *eax = 0; 6851 *ebx = 0; 6852 *ecx = 0; 6853 *edx = 0; 6854 break; 6855 case 0x80000000: 6856 *eax = env->cpuid_xlevel; 6857 *ebx = env->cpuid_vendor1; 6858 *edx = env->cpuid_vendor2; 6859 *ecx = env->cpuid_vendor3; 6860 break; 6861 case 0x80000001: 6862 *eax = env->cpuid_version; 6863 *ebx = 0; 6864 *ecx = env->features[FEAT_8000_0001_ECX]; 6865 *edx = env->features[FEAT_8000_0001_EDX]; 6866 6867 /* The Linux kernel checks for the CMPLegacy bit and 6868 * discards multiple thread information if it is set. 6869 * So don't set it here for Intel to make Linux guests happy. 6870 */ 6871 if (threads_per_pkg > 1) { 6872 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 || 6873 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 || 6874 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) { 6875 *ecx |= 1 << 1; /* CmpLegacy bit */ 6876 } 6877 } 6878 if (tcg_enabled() && env->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && 6879 !(env->hflags & HF_LMA_MASK)) { 6880 *edx &= ~CPUID_EXT2_SYSCALL; 6881 } 6882 break; 6883 case 0x80000002: 6884 case 0x80000003: 6885 case 0x80000004: 6886 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0]; 6887 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1]; 6888 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2]; 6889 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3]; 6890 break; 6891 case 0x80000005: 6892 /* cache info (L1 cache) */ 6893 if (cpu->cache_info_passthrough) { 6894 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 6895 break; 6896 } 6897 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | 6898 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES); 6899 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | 6900 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES); 6901 *ecx = encode_cache_cpuid80000005(env->cache_info_amd.l1d_cache); 6902 *edx = encode_cache_cpuid80000005(env->cache_info_amd.l1i_cache); 6903 break; 6904 case 0x80000006: 6905 /* cache info (L2 cache) */ 6906 if (cpu->cache_info_passthrough) { 6907 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 6908 break; 6909 } 6910 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | 6911 (L2_DTLB_2M_ENTRIES << 16) | 6912 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | 6913 (L2_ITLB_2M_ENTRIES); 6914 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | 6915 (L2_DTLB_4K_ENTRIES << 16) | 6916 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | 6917 (L2_ITLB_4K_ENTRIES); 6918 encode_cache_cpuid80000006(env->cache_info_amd.l2_cache, 6919 cpu->enable_l3_cache ? 6920 env->cache_info_amd.l3_cache : NULL, 6921 ecx, edx); 6922 break; 6923 case 0x80000007: 6924 *eax = 0; 6925 *ebx = env->features[FEAT_8000_0007_EBX]; 6926 *ecx = 0; 6927 *edx = env->features[FEAT_8000_0007_EDX]; 6928 break; 6929 case 0x80000008: 6930 /* virtual & phys address size in low 2 bytes. */ 6931 *eax = cpu->phys_bits; 6932 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 6933 /* 64 bit processor */ 6934 *eax |= (cpu_x86_virtual_addr_width(env) << 8); 6935 *eax |= (cpu->guest_phys_bits << 16); 6936 } 6937 *ebx = env->features[FEAT_8000_0008_EBX]; 6938 if (threads_per_pkg > 1) { 6939 /* 6940 * Bits 15:12 is "The number of bits in the initial 6941 * Core::X86::Apic::ApicId[ApicId] value that indicate 6942 * thread ID within a package". 6943 * Bits 7:0 is "The number of threads in the package is NC+1" 6944 */ 6945 *ecx = (apicid_pkg_offset(&topo_info) << 12) | 6946 (threads_per_pkg - 1); 6947 } else { 6948 *ecx = 0; 6949 } 6950 *edx = 0; 6951 break; 6952 case 0x8000000A: 6953 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { 6954 *eax = 0x00000001; /* SVM Revision */ 6955 *ebx = 0x00000010; /* nr of ASIDs */ 6956 *ecx = 0; 6957 *edx = env->features[FEAT_SVM]; /* optional features */ 6958 } else { 6959 *eax = 0; 6960 *ebx = 0; 6961 *ecx = 0; 6962 *edx = 0; 6963 } 6964 break; 6965 case 0x8000001D: 6966 *eax = 0; 6967 if (cpu->cache_info_passthrough) { 6968 x86_cpu_get_cache_cpuid(index, count, eax, ebx, ecx, edx); 6969 break; 6970 } 6971 switch (count) { 6972 case 0: /* L1 dcache info */ 6973 encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache, 6974 &topo_info, eax, ebx, ecx, edx); 6975 break; 6976 case 1: /* L1 icache info */ 6977 encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache, 6978 &topo_info, eax, ebx, ecx, edx); 6979 break; 6980 case 2: /* L2 cache info */ 6981 encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache, 6982 &topo_info, eax, ebx, ecx, edx); 6983 break; 6984 case 3: /* L3 cache info */ 6985 encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache, 6986 &topo_info, eax, ebx, ecx, edx); 6987 break; 6988 default: /* end of info */ 6989 *eax = *ebx = *ecx = *edx = 0; 6990 break; 6991 } 6992 if (cpu->amd_topoext_features_only) { 6993 *edx &= CACHE_NO_INVD_SHARING | CACHE_INCLUSIVE; 6994 } 6995 break; 6996 case 0x8000001E: 6997 if (cpu->core_id <= 255) { 6998 encode_topo_cpuid8000001e(cpu, &topo_info, eax, ebx, ecx, edx); 6999 } else { 7000 *eax = 0; 7001 *ebx = 0; 7002 *ecx = 0; 7003 *edx = 0; 7004 } 7005 break; 7006 case 0xC0000000: 7007 *eax = env->cpuid_xlevel2; 7008 *ebx = 0; 7009 *ecx = 0; 7010 *edx = 0; 7011 break; 7012 case 0xC0000001: 7013 /* Support for VIA CPU's CPUID instruction */ 7014 *eax = env->cpuid_version; 7015 *ebx = 0; 7016 *ecx = 0; 7017 *edx = env->features[FEAT_C000_0001_EDX]; 7018 break; 7019 case 0xC0000002: 7020 case 0xC0000003: 7021 case 0xC0000004: 7022 /* Reserved for the future, and now filled with zero */ 7023 *eax = 0; 7024 *ebx = 0; 7025 *ecx = 0; 7026 *edx = 0; 7027 break; 7028 case 0x8000001F: 7029 *eax = *ebx = *ecx = *edx = 0; 7030 if (sev_enabled()) { 7031 *eax = 0x2; 7032 *eax |= sev_es_enabled() ? 0x8 : 0; 7033 *eax |= sev_snp_enabled() ? 0x10 : 0; 7034 *ebx = sev_get_cbit_position() & 0x3f; /* EBX[5:0] */ 7035 *ebx |= (sev_get_reduced_phys_bits() & 0x3f) << 6; /* EBX[11:6] */ 7036 } 7037 break; 7038 case 0x80000021: 7039 *eax = env->features[FEAT_8000_0021_EAX]; 7040 *ebx = *ecx = *edx = 0; 7041 break; 7042 default: 7043 /* reserved values: zero */ 7044 *eax = 0; 7045 *ebx = 0; 7046 *ecx = 0; 7047 *edx = 0; 7048 break; 7049 } 7050 } 7051 7052 static void x86_cpu_set_sgxlepubkeyhash(CPUX86State *env) 7053 { 7054 #ifndef CONFIG_USER_ONLY 7055 /* Those default values are defined in Skylake HW */ 7056 env->msr_ia32_sgxlepubkeyhash[0] = 0xa6053e051270b7acULL; 7057 env->msr_ia32_sgxlepubkeyhash[1] = 0x6cfbe8ba8b3b413dULL; 7058 env->msr_ia32_sgxlepubkeyhash[2] = 0xc4916d99f2b3735dULL; 7059 env->msr_ia32_sgxlepubkeyhash[3] = 0xd4f8c05909f9bb3bULL; 7060 #endif 7061 } 7062 7063 static void x86_cpu_reset_hold(Object *obj, ResetType type) 7064 { 7065 CPUState *cs = CPU(obj); 7066 X86CPU *cpu = X86_CPU(cs); 7067 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj); 7068 CPUX86State *env = &cpu->env; 7069 target_ulong cr4; 7070 uint64_t xcr0; 7071 int i; 7072 7073 if (xcc->parent_phases.hold) { 7074 xcc->parent_phases.hold(obj, type); 7075 } 7076 7077 memset(env, 0, offsetof(CPUX86State, end_reset_fields)); 7078 7079 env->old_exception = -1; 7080 7081 /* init to reset state */ 7082 env->int_ctl = 0; 7083 env->hflags2 |= HF2_GIF_MASK; 7084 env->hflags2 |= HF2_VGIF_MASK; 7085 env->hflags &= ~HF_GUEST_MASK; 7086 7087 cpu_x86_update_cr0(env, 0x60000010); 7088 env->a20_mask = ~0x0; 7089 env->smbase = 0x30000; 7090 env->msr_smi_count = 0; 7091 7092 env->idt.limit = 0xffff; 7093 env->gdt.limit = 0xffff; 7094 env->ldt.limit = 0xffff; 7095 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT); 7096 env->tr.limit = 0xffff; 7097 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT); 7098 7099 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff, 7100 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK | 7101 DESC_R_MASK | DESC_A_MASK); 7102 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff, 7103 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7104 DESC_A_MASK); 7105 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff, 7106 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7107 DESC_A_MASK); 7108 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff, 7109 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7110 DESC_A_MASK); 7111 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff, 7112 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7113 DESC_A_MASK); 7114 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff, 7115 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7116 DESC_A_MASK); 7117 7118 env->eip = 0xfff0; 7119 env->regs[R_EDX] = env->cpuid_version; 7120 7121 env->eflags = 0x2; 7122 7123 /* FPU init */ 7124 for (i = 0; i < 8; i++) { 7125 env->fptags[i] = 1; 7126 } 7127 cpu_set_fpuc(env, 0x37f); 7128 7129 env->mxcsr = 0x1f80; 7130 /* All units are in INIT state. */ 7131 env->xstate_bv = 0; 7132 7133 env->pat = 0x0007040600070406ULL; 7134 7135 if (kvm_enabled()) { 7136 /* 7137 * KVM handles TSC = 0 specially and thinks we are hot-plugging 7138 * a new CPU, use 1 instead to force a reset. 7139 */ 7140 if (env->tsc != 0) { 7141 env->tsc = 1; 7142 } 7143 } else { 7144 env->tsc = 0; 7145 } 7146 7147 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT; 7148 if (env->features[FEAT_1_ECX] & CPUID_EXT_MONITOR) { 7149 env->msr_ia32_misc_enable |= MSR_IA32_MISC_ENABLE_MWAIT; 7150 } 7151 7152 memset(env->dr, 0, sizeof(env->dr)); 7153 env->dr[6] = DR6_FIXED_1; 7154 env->dr[7] = DR7_FIXED_1; 7155 cpu_breakpoint_remove_all(cs, BP_CPU); 7156 cpu_watchpoint_remove_all(cs, BP_CPU); 7157 7158 cr4 = 0; 7159 xcr0 = XSTATE_FP_MASK; 7160 7161 #ifdef CONFIG_USER_ONLY 7162 /* Enable all the features for user-mode. */ 7163 if (env->features[FEAT_1_EDX] & CPUID_SSE) { 7164 xcr0 |= XSTATE_SSE_MASK; 7165 } 7166 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 7167 const ExtSaveArea *esa = &x86_ext_save_areas[i]; 7168 if (!((1 << i) & CPUID_XSTATE_XCR0_MASK)) { 7169 continue; 7170 } 7171 if (env->features[esa->feature] & esa->bits) { 7172 xcr0 |= 1ull << i; 7173 } 7174 } 7175 7176 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) { 7177 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK; 7178 } 7179 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) { 7180 cr4 |= CR4_FSGSBASE_MASK; 7181 } 7182 #endif 7183 7184 env->xcr0 = xcr0; 7185 cpu_x86_update_cr4(env, cr4); 7186 7187 /* 7188 * SDM 11.11.5 requires: 7189 * - IA32_MTRR_DEF_TYPE MSR.E = 0 7190 * - IA32_MTRR_PHYSMASKn.V = 0 7191 * All other bits are undefined. For simplification, zero it all. 7192 */ 7193 env->mtrr_deftype = 0; 7194 memset(env->mtrr_var, 0, sizeof(env->mtrr_var)); 7195 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed)); 7196 7197 env->interrupt_injected = -1; 7198 env->exception_nr = -1; 7199 env->exception_pending = 0; 7200 env->exception_injected = 0; 7201 env->exception_has_payload = false; 7202 env->exception_payload = 0; 7203 env->nmi_injected = false; 7204 env->triple_fault_pending = false; 7205 #if !defined(CONFIG_USER_ONLY) 7206 /* We hard-wire the BSP to the first CPU. */ 7207 apic_designate_bsp(cpu->apic_state, cs->cpu_index == 0); 7208 7209 cs->halted = !cpu_is_bsp(cpu); 7210 7211 if (kvm_enabled()) { 7212 kvm_arch_reset_vcpu(cpu); 7213 } 7214 7215 x86_cpu_set_sgxlepubkeyhash(env); 7216 7217 env->amd_tsc_scale_msr = MSR_AMD64_TSC_RATIO_DEFAULT; 7218 7219 #endif 7220 } 7221 7222 void x86_cpu_after_reset(X86CPU *cpu) 7223 { 7224 #ifndef CONFIG_USER_ONLY 7225 if (kvm_enabled()) { 7226 kvm_arch_after_reset_vcpu(cpu); 7227 } 7228 7229 if (cpu->apic_state) { 7230 device_cold_reset(cpu->apic_state); 7231 } 7232 #endif 7233 } 7234 7235 static void mce_init(X86CPU *cpu) 7236 { 7237 CPUX86State *cenv = &cpu->env; 7238 unsigned int bank; 7239 7240 if (((cenv->cpuid_version >> 8) & 0xf) >= 6 7241 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) == 7242 (CPUID_MCE | CPUID_MCA)) { 7243 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF | 7244 (cpu->enable_lmce ? MCG_LMCE_P : 0); 7245 cenv->mcg_ctl = ~(uint64_t)0; 7246 for (bank = 0; bank < MCE_BANKS_DEF; bank++) { 7247 cenv->mce_banks[bank * 4] = ~(uint64_t)0; 7248 } 7249 } 7250 } 7251 7252 static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value) 7253 { 7254 if (*min < value) { 7255 *min = value; 7256 } 7257 } 7258 7259 /* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */ 7260 static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w) 7261 { 7262 CPUX86State *env = &cpu->env; 7263 FeatureWordInfo *fi = &feature_word_info[w]; 7264 uint32_t eax = fi->cpuid.eax; 7265 uint32_t region = eax & 0xF0000000; 7266 7267 assert(feature_word_info[w].type == CPUID_FEATURE_WORD); 7268 if (!env->features[w]) { 7269 return; 7270 } 7271 7272 switch (region) { 7273 case 0x00000000: 7274 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax); 7275 break; 7276 case 0x80000000: 7277 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax); 7278 break; 7279 case 0xC0000000: 7280 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax); 7281 break; 7282 } 7283 7284 if (eax == 7) { 7285 x86_cpu_adjust_level(cpu, &env->cpuid_min_level_func7, 7286 fi->cpuid.ecx); 7287 } 7288 } 7289 7290 /* Calculate XSAVE components based on the configured CPU feature flags */ 7291 static void x86_cpu_enable_xsave_components(X86CPU *cpu) 7292 { 7293 CPUX86State *env = &cpu->env; 7294 int i; 7295 uint64_t mask; 7296 static bool request_perm; 7297 7298 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { 7299 env->features[FEAT_XSAVE_XCR0_LO] = 0; 7300 env->features[FEAT_XSAVE_XCR0_HI] = 0; 7301 env->features[FEAT_XSAVE_XSS_LO] = 0; 7302 env->features[FEAT_XSAVE_XSS_HI] = 0; 7303 return; 7304 } 7305 7306 mask = 0; 7307 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 7308 const ExtSaveArea *esa = &x86_ext_save_areas[i]; 7309 if (env->features[esa->feature] & esa->bits) { 7310 mask |= (1ULL << i); 7311 } 7312 } 7313 7314 /* Only request permission for first vcpu */ 7315 if (kvm_enabled() && !request_perm) { 7316 kvm_request_xsave_components(cpu, mask); 7317 request_perm = true; 7318 } 7319 7320 env->features[FEAT_XSAVE_XCR0_LO] = mask & CPUID_XSTATE_XCR0_MASK; 7321 env->features[FEAT_XSAVE_XCR0_HI] = (mask & CPUID_XSTATE_XCR0_MASK) >> 32; 7322 env->features[FEAT_XSAVE_XSS_LO] = mask & CPUID_XSTATE_XSS_MASK; 7323 env->features[FEAT_XSAVE_XSS_HI] = (mask & CPUID_XSTATE_XSS_MASK) >> 32; 7324 } 7325 7326 /***** Steps involved on loading and filtering CPUID data 7327 * 7328 * When initializing and realizing a CPU object, the steps 7329 * involved in setting up CPUID data are: 7330 * 7331 * 1) Loading CPU model definition (X86CPUDefinition). This is 7332 * implemented by x86_cpu_load_model() and should be completely 7333 * transparent, as it is done automatically by instance_init. 7334 * No code should need to look at X86CPUDefinition structs 7335 * outside instance_init. 7336 * 7337 * 2) CPU expansion. This is done by realize before CPUID 7338 * filtering, and will make sure host/accelerator data is 7339 * loaded for CPU models that depend on host capabilities 7340 * (e.g. "host"). Done by x86_cpu_expand_features(). 7341 * 7342 * 3) CPUID filtering. This initializes extra data related to 7343 * CPUID, and checks if the host supports all capabilities 7344 * required by the CPU. Runnability of a CPU model is 7345 * determined at this step. Done by x86_cpu_filter_features(). 7346 * 7347 * Some operations don't require all steps to be performed. 7348 * More precisely: 7349 * 7350 * - CPU instance creation (instance_init) will run only CPU 7351 * model loading. CPU expansion can't run at instance_init-time 7352 * because host/accelerator data may be not available yet. 7353 * - CPU realization will perform both CPU model expansion and CPUID 7354 * filtering, and return an error in case one of them fails. 7355 * - query-cpu-definitions needs to run all 3 steps. It needs 7356 * to run CPUID filtering, as the 'unavailable-features' 7357 * field is set based on the filtering results. 7358 * - The query-cpu-model-expansion QMP command only needs to run 7359 * CPU model loading and CPU expansion. It should not filter 7360 * any CPUID data based on host capabilities. 7361 */ 7362 7363 /* Expand CPU configuration data, based on configured features 7364 * and host/accelerator capabilities when appropriate. 7365 */ 7366 void x86_cpu_expand_features(X86CPU *cpu, Error **errp) 7367 { 7368 CPUX86State *env = &cpu->env; 7369 FeatureWord w; 7370 int i; 7371 GList *l; 7372 7373 for (l = plus_features; l; l = l->next) { 7374 const char *prop = l->data; 7375 if (!object_property_set_bool(OBJECT(cpu), prop, true, errp)) { 7376 return; 7377 } 7378 } 7379 7380 for (l = minus_features; l; l = l->next) { 7381 const char *prop = l->data; 7382 if (!object_property_set_bool(OBJECT(cpu), prop, false, errp)) { 7383 return; 7384 } 7385 } 7386 7387 /*TODO: Now cpu->max_features doesn't overwrite features 7388 * set using QOM properties, and we can convert 7389 * plus_features & minus_features to global properties 7390 * inside x86_cpu_parse_featurestr() too. 7391 */ 7392 if (cpu->max_features) { 7393 for (w = 0; w < FEATURE_WORDS; w++) { 7394 /* Override only features that weren't set explicitly 7395 * by the user. 7396 */ 7397 env->features[w] |= 7398 x86_cpu_get_supported_feature_word(cpu, w) & 7399 ~env->user_features[w] & 7400 ~feature_word_info[w].no_autoenable_flags; 7401 } 7402 } 7403 7404 for (i = 0; i < ARRAY_SIZE(feature_dependencies); i++) { 7405 FeatureDep *d = &feature_dependencies[i]; 7406 if (!(env->features[d->from.index] & d->from.mask)) { 7407 uint64_t unavailable_features = env->features[d->to.index] & d->to.mask; 7408 7409 /* Not an error unless the dependent feature was added explicitly. */ 7410 mark_unavailable_features(cpu, d->to.index, 7411 unavailable_features & env->user_features[d->to.index], 7412 "This feature depends on other features that were not requested"); 7413 7414 env->features[d->to.index] &= ~unavailable_features; 7415 } 7416 } 7417 7418 if (!kvm_enabled() || !cpu->expose_kvm) { 7419 env->features[FEAT_KVM] = 0; 7420 } 7421 7422 x86_cpu_enable_xsave_components(cpu); 7423 7424 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */ 7425 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX); 7426 if (cpu->full_cpuid_auto_level) { 7427 x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX); 7428 x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX); 7429 x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX); 7430 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX); 7431 x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EAX); 7432 x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EDX); 7433 x86_cpu_adjust_feat_level(cpu, FEAT_7_2_EDX); 7434 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX); 7435 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX); 7436 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX); 7437 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0008_EBX); 7438 x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX); 7439 x86_cpu_adjust_feat_level(cpu, FEAT_SVM); 7440 x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE); 7441 7442 /* Intel Processor Trace requires CPUID[0x14] */ 7443 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT)) { 7444 if (cpu->intel_pt_auto_level) { 7445 x86_cpu_adjust_level(cpu, &cpu->env.cpuid_min_level, 0x14); 7446 } else if (cpu->env.cpuid_min_level < 0x14) { 7447 mark_unavailable_features(cpu, FEAT_7_0_EBX, 7448 CPUID_7_0_EBX_INTEL_PT, 7449 "Intel PT need CPUID leaf 0x14, please set by \"-cpu ...,intel-pt=on,min-level=0x14\""); 7450 } 7451 } 7452 7453 /* 7454 * Intel CPU topology with multi-dies support requires CPUID[0x1F]. 7455 * For AMD Rome/Milan, cpuid level is 0x10, and guest OS should detect 7456 * extended toplogy by leaf 0xB. Only adjust it for Intel CPU, unless 7457 * cpu->vendor_cpuid_only has been unset for compatibility with older 7458 * machine types. 7459 */ 7460 if (x86_has_extended_topo(env->avail_cpu_topo) && 7461 (IS_INTEL_CPU(env) || !cpu->vendor_cpuid_only)) { 7462 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x1F); 7463 } 7464 7465 /* SVM requires CPUID[0x8000000A] */ 7466 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { 7467 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A); 7468 } 7469 7470 /* SEV requires CPUID[0x8000001F] */ 7471 if (sev_enabled()) { 7472 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F); 7473 } 7474 7475 if (env->features[FEAT_8000_0021_EAX]) { 7476 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x80000021); 7477 } 7478 7479 /* SGX requires CPUID[0x12] for EPC enumeration */ 7480 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX) { 7481 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x12); 7482 } 7483 } 7484 7485 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */ 7486 if (env->cpuid_level_func7 == UINT32_MAX) { 7487 env->cpuid_level_func7 = env->cpuid_min_level_func7; 7488 } 7489 if (env->cpuid_level == UINT32_MAX) { 7490 env->cpuid_level = env->cpuid_min_level; 7491 } 7492 if (env->cpuid_xlevel == UINT32_MAX) { 7493 env->cpuid_xlevel = env->cpuid_min_xlevel; 7494 } 7495 if (env->cpuid_xlevel2 == UINT32_MAX) { 7496 env->cpuid_xlevel2 = env->cpuid_min_xlevel2; 7497 } 7498 7499 if (kvm_enabled() && !kvm_hyperv_expand_features(cpu, errp)) { 7500 return; 7501 } 7502 } 7503 7504 /* 7505 * Finishes initialization of CPUID data, filters CPU feature 7506 * words based on host availability of each feature. 7507 * 7508 * Returns: 0 if all flags are supported by the host, non-zero otherwise. 7509 */ 7510 static void x86_cpu_filter_features(X86CPU *cpu, bool verbose) 7511 { 7512 CPUX86State *env = &cpu->env; 7513 FeatureWord w; 7514 const char *prefix = NULL; 7515 7516 if (verbose) { 7517 prefix = accel_uses_host_cpuid() 7518 ? "host doesn't support requested feature" 7519 : "TCG doesn't support requested feature"; 7520 } 7521 7522 for (w = 0; w < FEATURE_WORDS; w++) { 7523 uint64_t host_feat = 7524 x86_cpu_get_supported_feature_word(NULL, w); 7525 uint64_t requested_features = env->features[w]; 7526 uint64_t unavailable_features = requested_features & ~host_feat; 7527 mark_unavailable_features(cpu, w, unavailable_features, prefix); 7528 } 7529 7530 /* 7531 * Check that KVM actually allows the processor tracing features that 7532 * are advertised by cpu_x86_cpuid(). Keep these two in sync. 7533 */ 7534 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) && 7535 kvm_enabled()) { 7536 uint32_t eax_0, ebx_0, ecx_0, edx_0_unused; 7537 uint32_t eax_1, ebx_1, ecx_1_unused, edx_1_unused; 7538 7539 x86_cpu_get_supported_cpuid(0x14, 0, 7540 &eax_0, &ebx_0, &ecx_0, &edx_0_unused); 7541 x86_cpu_get_supported_cpuid(0x14, 1, 7542 &eax_1, &ebx_1, &ecx_1_unused, &edx_1_unused); 7543 7544 if (!eax_0 || 7545 ((ebx_0 & INTEL_PT_MINIMAL_EBX) != INTEL_PT_MINIMAL_EBX) || 7546 ((ecx_0 & INTEL_PT_MINIMAL_ECX) != INTEL_PT_MINIMAL_ECX) || 7547 ((eax_1 & INTEL_PT_MTC_BITMAP) != INTEL_PT_MTC_BITMAP) || 7548 ((eax_1 & INTEL_PT_ADDR_RANGES_NUM_MASK) < 7549 INTEL_PT_ADDR_RANGES_NUM) || 7550 ((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) != 7551 (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) || 7552 ((ecx_0 & CPUID_14_0_ECX_LIP) != 7553 (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP))) { 7554 /* 7555 * Processor Trace capabilities aren't configurable, so if the 7556 * host can't emulate the capabilities we report on 7557 * cpu_x86_cpuid(), intel-pt can't be enabled on the current host. 7558 */ 7559 mark_unavailable_features(cpu, FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT, prefix); 7560 } 7561 } 7562 } 7563 7564 static void x86_cpu_hyperv_realize(X86CPU *cpu) 7565 { 7566 size_t len; 7567 7568 /* Hyper-V vendor id */ 7569 if (!cpu->hyperv_vendor) { 7570 object_property_set_str(OBJECT(cpu), "hv-vendor-id", "Microsoft Hv", 7571 &error_abort); 7572 } 7573 len = strlen(cpu->hyperv_vendor); 7574 if (len > 12) { 7575 warn_report("hv-vendor-id truncated to 12 characters"); 7576 len = 12; 7577 } 7578 memset(cpu->hyperv_vendor_id, 0, 12); 7579 memcpy(cpu->hyperv_vendor_id, cpu->hyperv_vendor, len); 7580 7581 /* 'Hv#1' interface identification*/ 7582 cpu->hyperv_interface_id[0] = 0x31237648; 7583 cpu->hyperv_interface_id[1] = 0; 7584 cpu->hyperv_interface_id[2] = 0; 7585 cpu->hyperv_interface_id[3] = 0; 7586 7587 /* Hypervisor implementation limits */ 7588 cpu->hyperv_limits[0] = 64; 7589 cpu->hyperv_limits[1] = 0; 7590 cpu->hyperv_limits[2] = 0; 7591 } 7592 7593 static void x86_cpu_realizefn(DeviceState *dev, Error **errp) 7594 { 7595 CPUState *cs = CPU(dev); 7596 X86CPU *cpu = X86_CPU(dev); 7597 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev); 7598 CPUX86State *env = &cpu->env; 7599 Error *local_err = NULL; 7600 unsigned requested_lbr_fmt; 7601 7602 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) 7603 /* Use pc-relative instructions in system-mode */ 7604 tcg_cflags_set(cs, CF_PCREL); 7605 #endif 7606 7607 if (cpu->apic_id == UNASSIGNED_APIC_ID) { 7608 error_setg(errp, "apic-id property was not initialized properly"); 7609 return; 7610 } 7611 7612 /* 7613 * Process Hyper-V enlightenments. 7614 * Note: this currently has to happen before the expansion of CPU features. 7615 */ 7616 x86_cpu_hyperv_realize(cpu); 7617 7618 x86_cpu_expand_features(cpu, &local_err); 7619 if (local_err) { 7620 goto out; 7621 } 7622 7623 /* 7624 * Override env->features[FEAT_PERF_CAPABILITIES].LBR_FMT 7625 * with user-provided setting. 7626 */ 7627 if (cpu->lbr_fmt != ~PERF_CAP_LBR_FMT) { 7628 if ((cpu->lbr_fmt & PERF_CAP_LBR_FMT) != cpu->lbr_fmt) { 7629 error_setg(errp, "invalid lbr-fmt"); 7630 return; 7631 } 7632 env->features[FEAT_PERF_CAPABILITIES] &= ~PERF_CAP_LBR_FMT; 7633 env->features[FEAT_PERF_CAPABILITIES] |= cpu->lbr_fmt; 7634 } 7635 7636 /* 7637 * vPMU LBR is supported when 1) KVM is enabled 2) Option pmu=on and 7638 * 3)vPMU LBR format matches that of host setting. 7639 */ 7640 requested_lbr_fmt = 7641 env->features[FEAT_PERF_CAPABILITIES] & PERF_CAP_LBR_FMT; 7642 if (requested_lbr_fmt && kvm_enabled()) { 7643 uint64_t host_perf_cap = 7644 x86_cpu_get_supported_feature_word(NULL, FEAT_PERF_CAPABILITIES); 7645 unsigned host_lbr_fmt = host_perf_cap & PERF_CAP_LBR_FMT; 7646 7647 if (!cpu->enable_pmu) { 7648 error_setg(errp, "vPMU: LBR is unsupported without pmu=on"); 7649 return; 7650 } 7651 if (requested_lbr_fmt != host_lbr_fmt) { 7652 error_setg(errp, "vPMU: the lbr-fmt value (0x%x) does not match " 7653 "the host value (0x%x).", 7654 requested_lbr_fmt, host_lbr_fmt); 7655 return; 7656 } 7657 } 7658 7659 x86_cpu_filter_features(cpu, cpu->check_cpuid || cpu->enforce_cpuid); 7660 7661 if (cpu->enforce_cpuid && x86_cpu_have_filtered_features(cpu)) { 7662 error_setg(&local_err, 7663 accel_uses_host_cpuid() ? 7664 "Host doesn't support requested features" : 7665 "TCG doesn't support requested features"); 7666 goto out; 7667 } 7668 7669 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on 7670 * CPUID[1].EDX. 7671 */ 7672 if (IS_AMD_CPU(env)) { 7673 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES; 7674 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX] 7675 & CPUID_EXT2_AMD_ALIASES); 7676 } 7677 7678 x86_cpu_set_sgxlepubkeyhash(env); 7679 7680 /* 7681 * note: the call to the framework needs to happen after feature expansion, 7682 * but before the checks/modifications to ucode_rev, mwait, phys_bits. 7683 * These may be set by the accel-specific code, 7684 * and the results are subsequently checked / assumed in this function. 7685 */ 7686 cpu_exec_realizefn(cs, &local_err); 7687 if (local_err != NULL) { 7688 error_propagate(errp, local_err); 7689 return; 7690 } 7691 7692 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) { 7693 g_autofree char *name = x86_cpu_class_get_model_name(xcc); 7694 error_setg(&local_err, "CPU model '%s' requires KVM or HVF", name); 7695 goto out; 7696 } 7697 7698 if (cpu->guest_phys_bits == -1) { 7699 /* 7700 * If it was not set by the user, or by the accelerator via 7701 * cpu_exec_realizefn, clear. 7702 */ 7703 cpu->guest_phys_bits = 0; 7704 } 7705 7706 if (cpu->ucode_rev == 0) { 7707 /* 7708 * The default is the same as KVM's. Note that this check 7709 * needs to happen after the evenual setting of ucode_rev in 7710 * accel-specific code in cpu_exec_realizefn. 7711 */ 7712 if (IS_AMD_CPU(env)) { 7713 cpu->ucode_rev = 0x01000065; 7714 } else { 7715 cpu->ucode_rev = 0x100000000ULL; 7716 } 7717 } 7718 7719 /* 7720 * mwait extended info: needed for Core compatibility 7721 * We always wake on interrupt even if host does not have the capability. 7722 * 7723 * requires the accel-specific code in cpu_exec_realizefn to 7724 * have already acquired the CPUID data into cpu->mwait. 7725 */ 7726 cpu->mwait.ecx |= CPUID_MWAIT_EMX | CPUID_MWAIT_IBE; 7727 7728 /* For 64bit systems think about the number of physical bits to present. 7729 * ideally this should be the same as the host; anything other than matching 7730 * the host can cause incorrect guest behaviour. 7731 * QEMU used to pick the magic value of 40 bits that corresponds to 7732 * consumer AMD devices but nothing else. 7733 * 7734 * Note that this code assumes features expansion has already been done 7735 * (as it checks for CPUID_EXT2_LM), and also assumes that potential 7736 * phys_bits adjustments to match the host have been already done in 7737 * accel-specific code in cpu_exec_realizefn. 7738 */ 7739 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 7740 if (cpu->phys_bits && 7741 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS || 7742 cpu->phys_bits < 32)) { 7743 error_setg(errp, "phys-bits should be between 32 and %u " 7744 " (but is %u)", 7745 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits); 7746 return; 7747 } 7748 /* 7749 * 0 means it was not explicitly set by the user (or by machine 7750 * compat_props or by the host code in host-cpu.c). 7751 * In this case, the default is the value used by TCG (40). 7752 */ 7753 if (cpu->phys_bits == 0) { 7754 cpu->phys_bits = TCG_PHYS_ADDR_BITS; 7755 } 7756 if (cpu->guest_phys_bits && 7757 (cpu->guest_phys_bits > cpu->phys_bits || 7758 cpu->guest_phys_bits < 32)) { 7759 error_setg(errp, "guest-phys-bits should be between 32 and %u " 7760 " (but is %u)", 7761 cpu->phys_bits, cpu->guest_phys_bits); 7762 return; 7763 } 7764 } else { 7765 /* For 32 bit systems don't use the user set value, but keep 7766 * phys_bits consistent with what we tell the guest. 7767 */ 7768 if (cpu->phys_bits != 0) { 7769 error_setg(errp, "phys-bits is not user-configurable in 32 bit"); 7770 return; 7771 } 7772 if (cpu->guest_phys_bits != 0) { 7773 error_setg(errp, "guest-phys-bits is not user-configurable in 32 bit"); 7774 return; 7775 } 7776 7777 if (env->features[FEAT_1_EDX] & (CPUID_PSE36 | CPUID_PAE)) { 7778 cpu->phys_bits = 36; 7779 } else { 7780 cpu->phys_bits = 32; 7781 } 7782 } 7783 7784 /* Cache information initialization */ 7785 if (!cpu->legacy_cache) { 7786 const CPUCaches *cache_info = 7787 x86_cpu_get_versioned_cache_info(cpu, xcc->model); 7788 7789 if (!xcc->model || !cache_info) { 7790 g_autofree char *name = x86_cpu_class_get_model_name(xcc); 7791 error_setg(errp, 7792 "CPU model '%s' doesn't support legacy-cache=off", name); 7793 return; 7794 } 7795 env->cache_info_cpuid2 = env->cache_info_cpuid4 = env->cache_info_amd = 7796 *cache_info; 7797 } else { 7798 /* Build legacy cache information */ 7799 env->cache_info_cpuid2.l1d_cache = &legacy_l1d_cache; 7800 env->cache_info_cpuid2.l1i_cache = &legacy_l1i_cache; 7801 env->cache_info_cpuid2.l2_cache = &legacy_l2_cache_cpuid2; 7802 env->cache_info_cpuid2.l3_cache = &legacy_l3_cache; 7803 7804 env->cache_info_cpuid4.l1d_cache = &legacy_l1d_cache; 7805 env->cache_info_cpuid4.l1i_cache = &legacy_l1i_cache; 7806 env->cache_info_cpuid4.l2_cache = &legacy_l2_cache; 7807 env->cache_info_cpuid4.l3_cache = &legacy_l3_cache; 7808 7809 env->cache_info_amd.l1d_cache = &legacy_l1d_cache_amd; 7810 env->cache_info_amd.l1i_cache = &legacy_l1i_cache_amd; 7811 env->cache_info_amd.l2_cache = &legacy_l2_cache_amd; 7812 env->cache_info_amd.l3_cache = &legacy_l3_cache; 7813 } 7814 7815 #ifndef CONFIG_USER_ONLY 7816 MachineState *ms = MACHINE(qdev_get_machine()); 7817 qemu_register_reset(x86_cpu_machine_reset_cb, cpu); 7818 7819 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || ms->smp.cpus > 1) { 7820 x86_cpu_apic_create(cpu, &local_err); 7821 if (local_err != NULL) { 7822 goto out; 7823 } 7824 } 7825 #endif 7826 7827 mce_init(cpu); 7828 7829 x86_cpu_gdb_init(cs); 7830 qemu_init_vcpu(cs); 7831 7832 /* 7833 * Most Intel and certain AMD CPUs support hyperthreading. Even though QEMU 7834 * fixes this issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX 7835 * based on inputs (sockets,cores,threads), it is still better to give 7836 * users a warning. 7837 * 7838 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise 7839 * cs->nr_threads hasn't be populated yet and the checking is incorrect. 7840 */ 7841 if (IS_AMD_CPU(env) && 7842 !(env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) && 7843 cs->nr_threads > 1) { 7844 warn_report_once("This family of AMD CPU doesn't support " 7845 "hyperthreading(%d). Please configure -smp " 7846 "options properly or try enabling topoext " 7847 "feature.", cs->nr_threads); 7848 } 7849 7850 #ifndef CONFIG_USER_ONLY 7851 x86_cpu_apic_realize(cpu, &local_err); 7852 if (local_err != NULL) { 7853 goto out; 7854 } 7855 #endif /* !CONFIG_USER_ONLY */ 7856 cpu_reset(cs); 7857 7858 xcc->parent_realize(dev, &local_err); 7859 7860 out: 7861 if (local_err != NULL) { 7862 error_propagate(errp, local_err); 7863 return; 7864 } 7865 } 7866 7867 static void x86_cpu_unrealizefn(DeviceState *dev) 7868 { 7869 X86CPU *cpu = X86_CPU(dev); 7870 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev); 7871 7872 #ifndef CONFIG_USER_ONLY 7873 cpu_remove_sync(CPU(dev)); 7874 qemu_unregister_reset(x86_cpu_machine_reset_cb, dev); 7875 #endif 7876 7877 if (cpu->apic_state) { 7878 object_unparent(OBJECT(cpu->apic_state)); 7879 cpu->apic_state = NULL; 7880 } 7881 7882 xcc->parent_unrealize(dev); 7883 } 7884 7885 typedef struct BitProperty { 7886 FeatureWord w; 7887 uint64_t mask; 7888 } BitProperty; 7889 7890 static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name, 7891 void *opaque, Error **errp) 7892 { 7893 X86CPU *cpu = X86_CPU(obj); 7894 BitProperty *fp = opaque; 7895 uint64_t f = cpu->env.features[fp->w]; 7896 bool value = (f & fp->mask) == fp->mask; 7897 visit_type_bool(v, name, &value, errp); 7898 } 7899 7900 static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name, 7901 void *opaque, Error **errp) 7902 { 7903 DeviceState *dev = DEVICE(obj); 7904 X86CPU *cpu = X86_CPU(obj); 7905 BitProperty *fp = opaque; 7906 bool value; 7907 7908 if (dev->realized) { 7909 qdev_prop_set_after_realize(dev, name, errp); 7910 return; 7911 } 7912 7913 if (!visit_type_bool(v, name, &value, errp)) { 7914 return; 7915 } 7916 7917 if (value) { 7918 cpu->env.features[fp->w] |= fp->mask; 7919 } else { 7920 cpu->env.features[fp->w] &= ~fp->mask; 7921 } 7922 cpu->env.user_features[fp->w] |= fp->mask; 7923 } 7924 7925 /* Register a boolean property to get/set a single bit in a uint32_t field. 7926 * 7927 * The same property name can be registered multiple times to make it affect 7928 * multiple bits in the same FeatureWord. In that case, the getter will return 7929 * true only if all bits are set. 7930 */ 7931 static void x86_cpu_register_bit_prop(X86CPUClass *xcc, 7932 const char *prop_name, 7933 FeatureWord w, 7934 int bitnr) 7935 { 7936 ObjectClass *oc = OBJECT_CLASS(xcc); 7937 BitProperty *fp; 7938 ObjectProperty *op; 7939 uint64_t mask = (1ULL << bitnr); 7940 7941 op = object_class_property_find(oc, prop_name); 7942 if (op) { 7943 fp = op->opaque; 7944 assert(fp->w == w); 7945 fp->mask |= mask; 7946 } else { 7947 fp = g_new0(BitProperty, 1); 7948 fp->w = w; 7949 fp->mask = mask; 7950 object_class_property_add(oc, prop_name, "bool", 7951 x86_cpu_get_bit_prop, 7952 x86_cpu_set_bit_prop, 7953 NULL, fp); 7954 } 7955 } 7956 7957 static void x86_cpu_register_feature_bit_props(X86CPUClass *xcc, 7958 FeatureWord w, 7959 int bitnr) 7960 { 7961 FeatureWordInfo *fi = &feature_word_info[w]; 7962 const char *name = fi->feat_names[bitnr]; 7963 7964 if (!name) { 7965 return; 7966 } 7967 7968 /* Property names should use "-" instead of "_". 7969 * Old names containing underscores are registered as aliases 7970 * using object_property_add_alias() 7971 */ 7972 assert(!strchr(name, '_')); 7973 /* aliases don't use "|" delimiters anymore, they are registered 7974 * manually using object_property_add_alias() */ 7975 assert(!strchr(name, '|')); 7976 x86_cpu_register_bit_prop(xcc, name, w, bitnr); 7977 } 7978 7979 static void x86_cpu_post_initfn(Object *obj) 7980 { 7981 accel_cpu_instance_init(CPU(obj)); 7982 } 7983 7984 static void x86_cpu_init_default_topo(X86CPU *cpu) 7985 { 7986 CPUX86State *env = &cpu->env; 7987 7988 env->nr_modules = 1; 7989 env->nr_dies = 1; 7990 7991 /* SMT, core and package levels are set by default. */ 7992 set_bit(CPU_TOPO_LEVEL_SMT, env->avail_cpu_topo); 7993 set_bit(CPU_TOPO_LEVEL_CORE, env->avail_cpu_topo); 7994 set_bit(CPU_TOPO_LEVEL_PACKAGE, env->avail_cpu_topo); 7995 } 7996 7997 static void x86_cpu_initfn(Object *obj) 7998 { 7999 X86CPU *cpu = X86_CPU(obj); 8000 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj); 8001 CPUX86State *env = &cpu->env; 8002 8003 x86_cpu_init_default_topo(cpu); 8004 8005 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo", 8006 x86_cpu_get_feature_words, 8007 NULL, NULL, (void *)env->features); 8008 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo", 8009 x86_cpu_get_feature_words, 8010 NULL, NULL, (void *)cpu->filtered_features); 8011 8012 object_property_add_alias(obj, "sse3", obj, "pni"); 8013 object_property_add_alias(obj, "pclmuldq", obj, "pclmulqdq"); 8014 object_property_add_alias(obj, "sse4-1", obj, "sse4.1"); 8015 object_property_add_alias(obj, "sse4-2", obj, "sse4.2"); 8016 object_property_add_alias(obj, "xd", obj, "nx"); 8017 object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt"); 8018 object_property_add_alias(obj, "i64", obj, "lm"); 8019 8020 object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl"); 8021 object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust"); 8022 object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt"); 8023 object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm"); 8024 object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy"); 8025 object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr"); 8026 object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core"); 8027 object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb"); 8028 object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay"); 8029 object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu"); 8030 object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf"); 8031 object_property_add_alias(obj, "kvm_asyncpf_int", obj, "kvm-asyncpf-int"); 8032 object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time"); 8033 object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi"); 8034 object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt"); 8035 object_property_add_alias(obj, "kvm_poll_control", obj, "kvm-poll-control"); 8036 object_property_add_alias(obj, "svm_lock", obj, "svm-lock"); 8037 object_property_add_alias(obj, "nrip_save", obj, "nrip-save"); 8038 object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale"); 8039 object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean"); 8040 object_property_add_alias(obj, "pause_filter", obj, "pause-filter"); 8041 object_property_add_alias(obj, "sse4_1", obj, "sse4.1"); 8042 object_property_add_alias(obj, "sse4_2", obj, "sse4.2"); 8043 8044 object_property_add_alias(obj, "hv-apicv", obj, "hv-avic"); 8045 cpu->lbr_fmt = ~PERF_CAP_LBR_FMT; 8046 object_property_add_alias(obj, "lbr_fmt", obj, "lbr-fmt"); 8047 8048 if (xcc->model) { 8049 x86_cpu_load_model(cpu, xcc->model); 8050 } 8051 } 8052 8053 static int64_t x86_cpu_get_arch_id(CPUState *cs) 8054 { 8055 X86CPU *cpu = X86_CPU(cs); 8056 8057 return cpu->apic_id; 8058 } 8059 8060 #if !defined(CONFIG_USER_ONLY) 8061 static bool x86_cpu_get_paging_enabled(const CPUState *cs) 8062 { 8063 X86CPU *cpu = X86_CPU(cs); 8064 8065 return cpu->env.cr[0] & CR0_PG_MASK; 8066 } 8067 #endif /* !CONFIG_USER_ONLY */ 8068 8069 static void x86_cpu_set_pc(CPUState *cs, vaddr value) 8070 { 8071 X86CPU *cpu = X86_CPU(cs); 8072 8073 cpu->env.eip = value; 8074 } 8075 8076 static vaddr x86_cpu_get_pc(CPUState *cs) 8077 { 8078 X86CPU *cpu = X86_CPU(cs); 8079 8080 /* Match cpu_get_tb_cpu_state. */ 8081 return cpu->env.eip + cpu->env.segs[R_CS].base; 8082 } 8083 8084 int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request) 8085 { 8086 X86CPU *cpu = X86_CPU(cs); 8087 CPUX86State *env = &cpu->env; 8088 8089 #if !defined(CONFIG_USER_ONLY) 8090 if (interrupt_request & CPU_INTERRUPT_POLL) { 8091 return CPU_INTERRUPT_POLL; 8092 } 8093 #endif 8094 if (interrupt_request & CPU_INTERRUPT_SIPI) { 8095 return CPU_INTERRUPT_SIPI; 8096 } 8097 8098 if (env->hflags2 & HF2_GIF_MASK) { 8099 if ((interrupt_request & CPU_INTERRUPT_SMI) && 8100 !(env->hflags & HF_SMM_MASK)) { 8101 return CPU_INTERRUPT_SMI; 8102 } else if ((interrupt_request & CPU_INTERRUPT_NMI) && 8103 !(env->hflags2 & HF2_NMI_MASK)) { 8104 return CPU_INTERRUPT_NMI; 8105 } else if (interrupt_request & CPU_INTERRUPT_MCE) { 8106 return CPU_INTERRUPT_MCE; 8107 } else if ((interrupt_request & CPU_INTERRUPT_HARD) && 8108 (((env->hflags2 & HF2_VINTR_MASK) && 8109 (env->hflags2 & HF2_HIF_MASK)) || 8110 (!(env->hflags2 & HF2_VINTR_MASK) && 8111 (env->eflags & IF_MASK && 8112 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) { 8113 return CPU_INTERRUPT_HARD; 8114 #if !defined(CONFIG_USER_ONLY) 8115 } else if (env->hflags2 & HF2_VGIF_MASK) { 8116 if((interrupt_request & CPU_INTERRUPT_VIRQ) && 8117 (env->eflags & IF_MASK) && 8118 !(env->hflags & HF_INHIBIT_IRQ_MASK)) { 8119 return CPU_INTERRUPT_VIRQ; 8120 } 8121 #endif 8122 } 8123 } 8124 8125 return 0; 8126 } 8127 8128 static bool x86_cpu_has_work(CPUState *cs) 8129 { 8130 return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0; 8131 } 8132 8133 int x86_mmu_index_pl(CPUX86State *env, unsigned pl) 8134 { 8135 int mmu_index_32 = (env->hflags & HF_CS64_MASK) ? 0 : 1; 8136 int mmu_index_base = 8137 pl == 3 ? MMU_USER64_IDX : 8138 !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP64_IDX : 8139 (env->eflags & AC_MASK) ? MMU_KNOSMAP64_IDX : MMU_KSMAP64_IDX; 8140 8141 return mmu_index_base + mmu_index_32; 8142 } 8143 8144 static int x86_cpu_mmu_index(CPUState *cs, bool ifetch) 8145 { 8146 CPUX86State *env = cpu_env(cs); 8147 return x86_mmu_index_pl(env, env->hflags & HF_CPL_MASK); 8148 } 8149 8150 static int x86_mmu_index_kernel_pl(CPUX86State *env, unsigned pl) 8151 { 8152 int mmu_index_32 = (env->hflags & HF_LMA_MASK) ? 0 : 1; 8153 int mmu_index_base = 8154 !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP64_IDX : 8155 (pl < 3 && (env->eflags & AC_MASK) 8156 ? MMU_KNOSMAP64_IDX : MMU_KSMAP64_IDX); 8157 8158 return mmu_index_base + mmu_index_32; 8159 } 8160 8161 int cpu_mmu_index_kernel(CPUX86State *env) 8162 { 8163 return x86_mmu_index_kernel_pl(env, env->hflags & HF_CPL_MASK); 8164 } 8165 8166 static void x86_disas_set_info(CPUState *cs, disassemble_info *info) 8167 { 8168 X86CPU *cpu = X86_CPU(cs); 8169 CPUX86State *env = &cpu->env; 8170 8171 info->mach = (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64 8172 : env->hflags & HF_CS32_MASK ? bfd_mach_i386_i386 8173 : bfd_mach_i386_i8086); 8174 8175 info->cap_arch = CS_ARCH_X86; 8176 info->cap_mode = (env->hflags & HF_CS64_MASK ? CS_MODE_64 8177 : env->hflags & HF_CS32_MASK ? CS_MODE_32 8178 : CS_MODE_16); 8179 info->cap_insn_unit = 1; 8180 info->cap_insn_split = 8; 8181 } 8182 8183 void x86_update_hflags(CPUX86State *env) 8184 { 8185 uint32_t hflags; 8186 #define HFLAG_COPY_MASK \ 8187 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \ 8188 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \ 8189 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \ 8190 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK) 8191 8192 hflags = env->hflags & HFLAG_COPY_MASK; 8193 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK; 8194 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT); 8195 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) & 8196 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK); 8197 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK)); 8198 8199 if (env->cr[4] & CR4_OSFXSR_MASK) { 8200 hflags |= HF_OSFXSR_MASK; 8201 } 8202 8203 if (env->efer & MSR_EFER_LMA) { 8204 hflags |= HF_LMA_MASK; 8205 } 8206 8207 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) { 8208 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; 8209 } else { 8210 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >> 8211 (DESC_B_SHIFT - HF_CS32_SHIFT); 8212 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >> 8213 (DESC_B_SHIFT - HF_SS32_SHIFT); 8214 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) || 8215 !(hflags & HF_CS32_MASK)) { 8216 hflags |= HF_ADDSEG_MASK; 8217 } else { 8218 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base | 8219 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT; 8220 } 8221 } 8222 env->hflags = hflags; 8223 } 8224 8225 static Property x86_cpu_properties[] = { 8226 #ifdef CONFIG_USER_ONLY 8227 /* apic_id = 0 by default for *-user, see commit 9886e834 */ 8228 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0), 8229 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0), 8230 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0), 8231 DEFINE_PROP_INT32("module-id", X86CPU, module_id, 0), 8232 DEFINE_PROP_INT32("die-id", X86CPU, die_id, 0), 8233 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0), 8234 #else 8235 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID), 8236 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1), 8237 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1), 8238 DEFINE_PROP_INT32("module-id", X86CPU, module_id, -1), 8239 DEFINE_PROP_INT32("die-id", X86CPU, die_id, -1), 8240 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1), 8241 #endif 8242 DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID), 8243 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false), 8244 DEFINE_PROP_UINT64_CHECKMASK("lbr-fmt", X86CPU, lbr_fmt, PERF_CAP_LBR_FMT), 8245 8246 DEFINE_PROP_UINT32("hv-spinlocks", X86CPU, hyperv_spinlock_attempts, 8247 HYPERV_SPINLOCK_NEVER_NOTIFY), 8248 DEFINE_PROP_BIT64("hv-relaxed", X86CPU, hyperv_features, 8249 HYPERV_FEAT_RELAXED, 0), 8250 DEFINE_PROP_BIT64("hv-vapic", X86CPU, hyperv_features, 8251 HYPERV_FEAT_VAPIC, 0), 8252 DEFINE_PROP_BIT64("hv-time", X86CPU, hyperv_features, 8253 HYPERV_FEAT_TIME, 0), 8254 DEFINE_PROP_BIT64("hv-crash", X86CPU, hyperv_features, 8255 HYPERV_FEAT_CRASH, 0), 8256 DEFINE_PROP_BIT64("hv-reset", X86CPU, hyperv_features, 8257 HYPERV_FEAT_RESET, 0), 8258 DEFINE_PROP_BIT64("hv-vpindex", X86CPU, hyperv_features, 8259 HYPERV_FEAT_VPINDEX, 0), 8260 DEFINE_PROP_BIT64("hv-runtime", X86CPU, hyperv_features, 8261 HYPERV_FEAT_RUNTIME, 0), 8262 DEFINE_PROP_BIT64("hv-synic", X86CPU, hyperv_features, 8263 HYPERV_FEAT_SYNIC, 0), 8264 DEFINE_PROP_BIT64("hv-stimer", X86CPU, hyperv_features, 8265 HYPERV_FEAT_STIMER, 0), 8266 DEFINE_PROP_BIT64("hv-frequencies", X86CPU, hyperv_features, 8267 HYPERV_FEAT_FREQUENCIES, 0), 8268 DEFINE_PROP_BIT64("hv-reenlightenment", X86CPU, hyperv_features, 8269 HYPERV_FEAT_REENLIGHTENMENT, 0), 8270 DEFINE_PROP_BIT64("hv-tlbflush", X86CPU, hyperv_features, 8271 HYPERV_FEAT_TLBFLUSH, 0), 8272 DEFINE_PROP_BIT64("hv-evmcs", X86CPU, hyperv_features, 8273 HYPERV_FEAT_EVMCS, 0), 8274 DEFINE_PROP_BIT64("hv-ipi", X86CPU, hyperv_features, 8275 HYPERV_FEAT_IPI, 0), 8276 DEFINE_PROP_BIT64("hv-stimer-direct", X86CPU, hyperv_features, 8277 HYPERV_FEAT_STIMER_DIRECT, 0), 8278 DEFINE_PROP_BIT64("hv-avic", X86CPU, hyperv_features, 8279 HYPERV_FEAT_AVIC, 0), 8280 DEFINE_PROP_BIT64("hv-emsr-bitmap", X86CPU, hyperv_features, 8281 HYPERV_FEAT_MSR_BITMAP, 0), 8282 DEFINE_PROP_BIT64("hv-xmm-input", X86CPU, hyperv_features, 8283 HYPERV_FEAT_XMM_INPUT, 0), 8284 DEFINE_PROP_BIT64("hv-tlbflush-ext", X86CPU, hyperv_features, 8285 HYPERV_FEAT_TLBFLUSH_EXT, 0), 8286 DEFINE_PROP_BIT64("hv-tlbflush-direct", X86CPU, hyperv_features, 8287 HYPERV_FEAT_TLBFLUSH_DIRECT, 0), 8288 DEFINE_PROP_ON_OFF_AUTO("hv-no-nonarch-coresharing", X86CPU, 8289 hyperv_no_nonarch_cs, ON_OFF_AUTO_OFF), 8290 DEFINE_PROP_BIT64("hv-syndbg", X86CPU, hyperv_features, 8291 HYPERV_FEAT_SYNDBG, 0), 8292 DEFINE_PROP_BOOL("hv-passthrough", X86CPU, hyperv_passthrough, false), 8293 DEFINE_PROP_BOOL("hv-enforce-cpuid", X86CPU, hyperv_enforce_cpuid, false), 8294 8295 /* WS2008R2 identify by default */ 8296 DEFINE_PROP_UINT32("hv-version-id-build", X86CPU, hyperv_ver_id_build, 8297 0x3839), 8298 DEFINE_PROP_UINT16("hv-version-id-major", X86CPU, hyperv_ver_id_major, 8299 0x000A), 8300 DEFINE_PROP_UINT16("hv-version-id-minor", X86CPU, hyperv_ver_id_minor, 8301 0x0000), 8302 DEFINE_PROP_UINT32("hv-version-id-spack", X86CPU, hyperv_ver_id_sp, 0), 8303 DEFINE_PROP_UINT8("hv-version-id-sbranch", X86CPU, hyperv_ver_id_sb, 0), 8304 DEFINE_PROP_UINT32("hv-version-id-snumber", X86CPU, hyperv_ver_id_sn, 0), 8305 8306 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true), 8307 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false), 8308 DEFINE_PROP_BOOL("x-force-features", X86CPU, force_features, false), 8309 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true), 8310 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0), 8311 DEFINE_PROP_UINT32("guest-phys-bits", X86CPU, guest_phys_bits, -1), 8312 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false), 8313 DEFINE_PROP_UINT8("host-phys-bits-limit", X86CPU, host_phys_bits_limit, 0), 8314 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true), 8315 DEFINE_PROP_UINT32("level-func7", X86CPU, env.cpuid_level_func7, 8316 UINT32_MAX), 8317 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX), 8318 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX), 8319 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX), 8320 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0), 8321 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0), 8322 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0), 8323 DEFINE_PROP_UINT64("ucode-rev", X86CPU, ucode_rev, 0), 8324 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true), 8325 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor), 8326 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true), 8327 DEFINE_PROP_BOOL("x-vendor-cpuid-only", X86CPU, vendor_cpuid_only, true), 8328 DEFINE_PROP_BOOL("x-amd-topoext-features-only", X86CPU, amd_topoext_features_only, true), 8329 DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false), 8330 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true), 8331 DEFINE_PROP_BOOL("kvm-pv-enforce-cpuid", X86CPU, kvm_pv_enforce_cpuid, 8332 false), 8333 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true), 8334 DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true), 8335 DEFINE_PROP_BOOL("x-migrate-smi-count", X86CPU, migrate_smi_count, 8336 true), 8337 /* 8338 * lecacy_cache defaults to true unless the CPU model provides its 8339 * own cache information (see x86_cpu_load_def()). 8340 */ 8341 DEFINE_PROP_BOOL("legacy-cache", X86CPU, legacy_cache, true), 8342 DEFINE_PROP_BOOL("legacy-multi-node", X86CPU, legacy_multi_node, false), 8343 DEFINE_PROP_BOOL("xen-vapic", X86CPU, xen_vapic, false), 8344 8345 /* 8346 * From "Requirements for Implementing the Microsoft 8347 * Hypervisor Interface": 8348 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs 8349 * 8350 * "Starting with Windows Server 2012 and Windows 8, if 8351 * CPUID.40000005.EAX contains a value of -1, Windows assumes that 8352 * the hypervisor imposes no specific limit to the number of VPs. 8353 * In this case, Windows Server 2012 guest VMs may use more than 8354 * 64 VPs, up to the maximum supported number of processors applicable 8355 * to the specific Windows version being used." 8356 */ 8357 DEFINE_PROP_INT32("x-hv-max-vps", X86CPU, hv_max_vps, -1), 8358 DEFINE_PROP_BOOL("x-hv-synic-kvm-only", X86CPU, hyperv_synic_kvm_only, 8359 false), 8360 DEFINE_PROP_BOOL("x-intel-pt-auto-level", X86CPU, intel_pt_auto_level, 8361 true), 8362 DEFINE_PROP_BOOL("x-l1-cache-per-thread", X86CPU, l1_cache_per_core, true), 8363 DEFINE_PROP_END_OF_LIST() 8364 }; 8365 8366 #ifndef CONFIG_USER_ONLY 8367 #include "hw/core/sysemu-cpu-ops.h" 8368 8369 static const struct SysemuCPUOps i386_sysemu_ops = { 8370 .get_memory_mapping = x86_cpu_get_memory_mapping, 8371 .get_paging_enabled = x86_cpu_get_paging_enabled, 8372 .get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug, 8373 .asidx_from_attrs = x86_asidx_from_attrs, 8374 .get_crash_info = x86_cpu_get_crash_info, 8375 .write_elf32_note = x86_cpu_write_elf32_note, 8376 .write_elf64_note = x86_cpu_write_elf64_note, 8377 .write_elf32_qemunote = x86_cpu_write_elf32_qemunote, 8378 .write_elf64_qemunote = x86_cpu_write_elf64_qemunote, 8379 .legacy_vmsd = &vmstate_x86_cpu, 8380 }; 8381 #endif 8382 8383 static void x86_cpu_common_class_init(ObjectClass *oc, void *data) 8384 { 8385 X86CPUClass *xcc = X86_CPU_CLASS(oc); 8386 CPUClass *cc = CPU_CLASS(oc); 8387 DeviceClass *dc = DEVICE_CLASS(oc); 8388 ResettableClass *rc = RESETTABLE_CLASS(oc); 8389 FeatureWord w; 8390 8391 device_class_set_parent_realize(dc, x86_cpu_realizefn, 8392 &xcc->parent_realize); 8393 device_class_set_parent_unrealize(dc, x86_cpu_unrealizefn, 8394 &xcc->parent_unrealize); 8395 device_class_set_props(dc, x86_cpu_properties); 8396 8397 resettable_class_set_parent_phases(rc, NULL, x86_cpu_reset_hold, NULL, 8398 &xcc->parent_phases); 8399 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP; 8400 8401 cc->class_by_name = x86_cpu_class_by_name; 8402 cc->parse_features = x86_cpu_parse_featurestr; 8403 cc->has_work = x86_cpu_has_work; 8404 cc->mmu_index = x86_cpu_mmu_index; 8405 cc->dump_state = x86_cpu_dump_state; 8406 cc->set_pc = x86_cpu_set_pc; 8407 cc->get_pc = x86_cpu_get_pc; 8408 cc->gdb_read_register = x86_cpu_gdb_read_register; 8409 cc->gdb_write_register = x86_cpu_gdb_write_register; 8410 cc->get_arch_id = x86_cpu_get_arch_id; 8411 8412 #ifndef CONFIG_USER_ONLY 8413 cc->sysemu_ops = &i386_sysemu_ops; 8414 #endif /* !CONFIG_USER_ONLY */ 8415 8416 cc->gdb_arch_name = x86_gdb_arch_name; 8417 #ifdef TARGET_X86_64 8418 cc->gdb_core_xml_file = "i386-64bit.xml"; 8419 #else 8420 cc->gdb_core_xml_file = "i386-32bit.xml"; 8421 #endif 8422 cc->disas_set_info = x86_disas_set_info; 8423 8424 dc->user_creatable = true; 8425 8426 object_class_property_add(oc, "family", "int", 8427 x86_cpuid_version_get_family, 8428 x86_cpuid_version_set_family, NULL, NULL); 8429 object_class_property_add(oc, "model", "int", 8430 x86_cpuid_version_get_model, 8431 x86_cpuid_version_set_model, NULL, NULL); 8432 object_class_property_add(oc, "stepping", "int", 8433 x86_cpuid_version_get_stepping, 8434 x86_cpuid_version_set_stepping, NULL, NULL); 8435 object_class_property_add_str(oc, "vendor", 8436 x86_cpuid_get_vendor, 8437 x86_cpuid_set_vendor); 8438 object_class_property_add_str(oc, "model-id", 8439 x86_cpuid_get_model_id, 8440 x86_cpuid_set_model_id); 8441 object_class_property_add(oc, "tsc-frequency", "int", 8442 x86_cpuid_get_tsc_freq, 8443 x86_cpuid_set_tsc_freq, NULL, NULL); 8444 /* 8445 * The "unavailable-features" property has the same semantics as 8446 * CpuDefinitionInfo.unavailable-features on the "query-cpu-definitions" 8447 * QMP command: they list the features that would have prevented the 8448 * CPU from running if the "enforce" flag was set. 8449 */ 8450 object_class_property_add(oc, "unavailable-features", "strList", 8451 x86_cpu_get_unavailable_features, 8452 NULL, NULL, NULL); 8453 8454 #if !defined(CONFIG_USER_ONLY) 8455 object_class_property_add(oc, "crash-information", "GuestPanicInformation", 8456 x86_cpu_get_crash_info_qom, NULL, NULL, NULL); 8457 #endif 8458 8459 for (w = 0; w < FEATURE_WORDS; w++) { 8460 int bitnr; 8461 for (bitnr = 0; bitnr < 64; bitnr++) { 8462 x86_cpu_register_feature_bit_props(xcc, w, bitnr); 8463 } 8464 } 8465 } 8466 8467 static const TypeInfo x86_cpu_type_info = { 8468 .name = TYPE_X86_CPU, 8469 .parent = TYPE_CPU, 8470 .instance_size = sizeof(X86CPU), 8471 .instance_align = __alignof(X86CPU), 8472 .instance_init = x86_cpu_initfn, 8473 .instance_post_init = x86_cpu_post_initfn, 8474 8475 .abstract = true, 8476 .class_size = sizeof(X86CPUClass), 8477 .class_init = x86_cpu_common_class_init, 8478 }; 8479 8480 /* "base" CPU model, used by query-cpu-model-expansion */ 8481 static void x86_cpu_base_class_init(ObjectClass *oc, void *data) 8482 { 8483 X86CPUClass *xcc = X86_CPU_CLASS(oc); 8484 8485 xcc->static_model = true; 8486 xcc->migration_safe = true; 8487 xcc->model_description = "base CPU model type with no features enabled"; 8488 xcc->ordering = 8; 8489 } 8490 8491 static const TypeInfo x86_base_cpu_type_info = { 8492 .name = X86_CPU_TYPE_NAME("base"), 8493 .parent = TYPE_X86_CPU, 8494 .class_init = x86_cpu_base_class_init, 8495 }; 8496 8497 static void x86_cpu_register_types(void) 8498 { 8499 int i; 8500 8501 type_register_static(&x86_cpu_type_info); 8502 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) { 8503 x86_register_cpudef_types(&builtin_x86_defs[i]); 8504 } 8505 type_register_static(&max_x86_cpu_type_info); 8506 type_register_static(&x86_base_cpu_type_info); 8507 } 8508 8509 type_init(x86_cpu_register_types) 8510