1 /* 2 * i386 CPUID helper functions 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/units.h" 22 #include "qemu/cutils.h" 23 #include "qemu/bitops.h" 24 #include "qemu/qemu-print.h" 25 26 #include "cpu.h" 27 #include "exec/exec-all.h" 28 #include "sysemu/kvm.h" 29 #include "sysemu/reset.h" 30 #include "sysemu/hvf.h" 31 #include "sysemu/cpus.h" 32 #include "sysemu/xen.h" 33 #include "kvm_i386.h" 34 #include "sev_i386.h" 35 36 #include "qemu/error-report.h" 37 #include "qemu/module.h" 38 #include "qemu/option.h" 39 #include "qemu/config-file.h" 40 #include "qapi/error.h" 41 #include "qapi/qapi-visit-machine.h" 42 #include "qapi/qapi-visit-run-state.h" 43 #include "qapi/qmp/qdict.h" 44 #include "qapi/qmp/qerror.h" 45 #include "qapi/visitor.h" 46 #include "qom/qom-qobject.h" 47 #include "sysemu/arch_init.h" 48 #include "qapi/qapi-commands-machine-target.h" 49 50 #include "standard-headers/asm-x86/kvm_para.h" 51 52 #include "sysemu/sysemu.h" 53 #include "sysemu/tcg.h" 54 #include "hw/qdev-properties.h" 55 #include "hw/i386/topology.h" 56 #ifndef CONFIG_USER_ONLY 57 #include "exec/address-spaces.h" 58 #include "hw/i386/apic_internal.h" 59 #include "hw/boards.h" 60 #endif 61 62 #include "disas/capstone.h" 63 64 /* Helpers for building CPUID[2] descriptors: */ 65 66 struct CPUID2CacheDescriptorInfo { 67 enum CacheType type; 68 int level; 69 int size; 70 int line_size; 71 int associativity; 72 }; 73 74 /* 75 * Known CPUID 2 cache descriptors. 76 * From Intel SDM Volume 2A, CPUID instruction 77 */ 78 struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = { 79 [0x06] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 8 * KiB, 80 .associativity = 4, .line_size = 32, }, 81 [0x08] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 16 * KiB, 82 .associativity = 4, .line_size = 32, }, 83 [0x09] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB, 84 .associativity = 4, .line_size = 64, }, 85 [0x0A] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB, 86 .associativity = 2, .line_size = 32, }, 87 [0x0C] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 88 .associativity = 4, .line_size = 32, }, 89 [0x0D] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 90 .associativity = 4, .line_size = 64, }, 91 [0x0E] = { .level = 1, .type = DATA_CACHE, .size = 24 * KiB, 92 .associativity = 6, .line_size = 64, }, 93 [0x1D] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB, 94 .associativity = 2, .line_size = 64, }, 95 [0x21] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 96 .associativity = 8, .line_size = 64, }, 97 /* lines per sector is not supported cpuid2_cache_descriptor(), 98 * so descriptors 0x22, 0x23 are not included 99 */ 100 [0x24] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 101 .associativity = 16, .line_size = 64, }, 102 /* lines per sector is not supported cpuid2_cache_descriptor(), 103 * so descriptors 0x25, 0x20 are not included 104 */ 105 [0x2C] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB, 106 .associativity = 8, .line_size = 64, }, 107 [0x30] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB, 108 .associativity = 8, .line_size = 64, }, 109 [0x41] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB, 110 .associativity = 4, .line_size = 32, }, 111 [0x42] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 112 .associativity = 4, .line_size = 32, }, 113 [0x43] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 114 .associativity = 4, .line_size = 32, }, 115 [0x44] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 116 .associativity = 4, .line_size = 32, }, 117 [0x45] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 118 .associativity = 4, .line_size = 32, }, 119 [0x46] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 120 .associativity = 4, .line_size = 64, }, 121 [0x47] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 122 .associativity = 8, .line_size = 64, }, 123 [0x48] = { .level = 2, .type = UNIFIED_CACHE, .size = 3 * MiB, 124 .associativity = 12, .line_size = 64, }, 125 /* Descriptor 0x49 depends on CPU family/model, so it is not included */ 126 [0x4A] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB, 127 .associativity = 12, .line_size = 64, }, 128 [0x4B] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 129 .associativity = 16, .line_size = 64, }, 130 [0x4C] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB, 131 .associativity = 12, .line_size = 64, }, 132 [0x4D] = { .level = 3, .type = UNIFIED_CACHE, .size = 16 * MiB, 133 .associativity = 16, .line_size = 64, }, 134 [0x4E] = { .level = 2, .type = UNIFIED_CACHE, .size = 6 * MiB, 135 .associativity = 24, .line_size = 64, }, 136 [0x60] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 137 .associativity = 8, .line_size = 64, }, 138 [0x66] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB, 139 .associativity = 4, .line_size = 64, }, 140 [0x67] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 141 .associativity = 4, .line_size = 64, }, 142 [0x68] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB, 143 .associativity = 4, .line_size = 64, }, 144 [0x78] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 145 .associativity = 4, .line_size = 64, }, 146 /* lines per sector is not supported cpuid2_cache_descriptor(), 147 * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included. 148 */ 149 [0x7D] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 150 .associativity = 8, .line_size = 64, }, 151 [0x7F] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 152 .associativity = 2, .line_size = 64, }, 153 [0x80] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 154 .associativity = 8, .line_size = 64, }, 155 [0x82] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 156 .associativity = 8, .line_size = 32, }, 157 [0x83] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 158 .associativity = 8, .line_size = 32, }, 159 [0x84] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 160 .associativity = 8, .line_size = 32, }, 161 [0x85] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 162 .associativity = 8, .line_size = 32, }, 163 [0x86] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 164 .associativity = 4, .line_size = 64, }, 165 [0x87] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 166 .associativity = 8, .line_size = 64, }, 167 [0xD0] = { .level = 3, .type = UNIFIED_CACHE, .size = 512 * KiB, 168 .associativity = 4, .line_size = 64, }, 169 [0xD1] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB, 170 .associativity = 4, .line_size = 64, }, 171 [0xD2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 172 .associativity = 4, .line_size = 64, }, 173 [0xD6] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB, 174 .associativity = 8, .line_size = 64, }, 175 [0xD7] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 176 .associativity = 8, .line_size = 64, }, 177 [0xD8] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 178 .associativity = 8, .line_size = 64, }, 179 [0xDC] = { .level = 3, .type = UNIFIED_CACHE, .size = 1.5 * MiB, 180 .associativity = 12, .line_size = 64, }, 181 [0xDD] = { .level = 3, .type = UNIFIED_CACHE, .size = 3 * MiB, 182 .associativity = 12, .line_size = 64, }, 183 [0xDE] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB, 184 .associativity = 12, .line_size = 64, }, 185 [0xE2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 186 .associativity = 16, .line_size = 64, }, 187 [0xE3] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 188 .associativity = 16, .line_size = 64, }, 189 [0xE4] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 190 .associativity = 16, .line_size = 64, }, 191 [0xEA] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB, 192 .associativity = 24, .line_size = 64, }, 193 [0xEB] = { .level = 3, .type = UNIFIED_CACHE, .size = 18 * MiB, 194 .associativity = 24, .line_size = 64, }, 195 [0xEC] = { .level = 3, .type = UNIFIED_CACHE, .size = 24 * MiB, 196 .associativity = 24, .line_size = 64, }, 197 }; 198 199 /* 200 * "CPUID leaf 2 does not report cache descriptor information, 201 * use CPUID leaf 4 to query cache parameters" 202 */ 203 #define CACHE_DESCRIPTOR_UNAVAILABLE 0xFF 204 205 /* 206 * Return a CPUID 2 cache descriptor for a given cache. 207 * If no known descriptor is found, return CACHE_DESCRIPTOR_UNAVAILABLE 208 */ 209 static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache) 210 { 211 int i; 212 213 assert(cache->size > 0); 214 assert(cache->level > 0); 215 assert(cache->line_size > 0); 216 assert(cache->associativity > 0); 217 for (i = 0; i < ARRAY_SIZE(cpuid2_cache_descriptors); i++) { 218 struct CPUID2CacheDescriptorInfo *d = &cpuid2_cache_descriptors[i]; 219 if (d->level == cache->level && d->type == cache->type && 220 d->size == cache->size && d->line_size == cache->line_size && 221 d->associativity == cache->associativity) { 222 return i; 223 } 224 } 225 226 return CACHE_DESCRIPTOR_UNAVAILABLE; 227 } 228 229 /* CPUID Leaf 4 constants: */ 230 231 /* EAX: */ 232 #define CACHE_TYPE_D 1 233 #define CACHE_TYPE_I 2 234 #define CACHE_TYPE_UNIFIED 3 235 236 #define CACHE_LEVEL(l) (l << 5) 237 238 #define CACHE_SELF_INIT_LEVEL (1 << 8) 239 240 /* EDX: */ 241 #define CACHE_NO_INVD_SHARING (1 << 0) 242 #define CACHE_INCLUSIVE (1 << 1) 243 #define CACHE_COMPLEX_IDX (1 << 2) 244 245 /* Encode CacheType for CPUID[4].EAX */ 246 #define CACHE_TYPE(t) (((t) == DATA_CACHE) ? CACHE_TYPE_D : \ 247 ((t) == INSTRUCTION_CACHE) ? CACHE_TYPE_I : \ 248 ((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \ 249 0 /* Invalid value */) 250 251 252 /* Encode cache info for CPUID[4] */ 253 static void encode_cache_cpuid4(CPUCacheInfo *cache, 254 int num_apic_ids, int num_cores, 255 uint32_t *eax, uint32_t *ebx, 256 uint32_t *ecx, uint32_t *edx) 257 { 258 assert(cache->size == cache->line_size * cache->associativity * 259 cache->partitions * cache->sets); 260 261 assert(num_apic_ids > 0); 262 *eax = CACHE_TYPE(cache->type) | 263 CACHE_LEVEL(cache->level) | 264 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) | 265 ((num_cores - 1) << 26) | 266 ((num_apic_ids - 1) << 14); 267 268 assert(cache->line_size > 0); 269 assert(cache->partitions > 0); 270 assert(cache->associativity > 0); 271 /* We don't implement fully-associative caches */ 272 assert(cache->associativity < cache->sets); 273 *ebx = (cache->line_size - 1) | 274 ((cache->partitions - 1) << 12) | 275 ((cache->associativity - 1) << 22); 276 277 assert(cache->sets > 0); 278 *ecx = cache->sets - 1; 279 280 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) | 281 (cache->inclusive ? CACHE_INCLUSIVE : 0) | 282 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); 283 } 284 285 /* Encode cache info for CPUID[0x80000005].ECX or CPUID[0x80000005].EDX */ 286 static uint32_t encode_cache_cpuid80000005(CPUCacheInfo *cache) 287 { 288 assert(cache->size % 1024 == 0); 289 assert(cache->lines_per_tag > 0); 290 assert(cache->associativity > 0); 291 assert(cache->line_size > 0); 292 return ((cache->size / 1024) << 24) | (cache->associativity << 16) | 293 (cache->lines_per_tag << 8) | (cache->line_size); 294 } 295 296 #define ASSOC_FULL 0xFF 297 298 /* AMD associativity encoding used on CPUID Leaf 0x80000006: */ 299 #define AMD_ENC_ASSOC(a) (a <= 1 ? a : \ 300 a == 2 ? 0x2 : \ 301 a == 4 ? 0x4 : \ 302 a == 8 ? 0x6 : \ 303 a == 16 ? 0x8 : \ 304 a == 32 ? 0xA : \ 305 a == 48 ? 0xB : \ 306 a == 64 ? 0xC : \ 307 a == 96 ? 0xD : \ 308 a == 128 ? 0xE : \ 309 a == ASSOC_FULL ? 0xF : \ 310 0 /* invalid value */) 311 312 /* 313 * Encode cache info for CPUID[0x80000006].ECX and CPUID[0x80000006].EDX 314 * @l3 can be NULL. 315 */ 316 static void encode_cache_cpuid80000006(CPUCacheInfo *l2, 317 CPUCacheInfo *l3, 318 uint32_t *ecx, uint32_t *edx) 319 { 320 assert(l2->size % 1024 == 0); 321 assert(l2->associativity > 0); 322 assert(l2->lines_per_tag > 0); 323 assert(l2->line_size > 0); 324 *ecx = ((l2->size / 1024) << 16) | 325 (AMD_ENC_ASSOC(l2->associativity) << 12) | 326 (l2->lines_per_tag << 8) | (l2->line_size); 327 328 if (l3) { 329 assert(l3->size % (512 * 1024) == 0); 330 assert(l3->associativity > 0); 331 assert(l3->lines_per_tag > 0); 332 assert(l3->line_size > 0); 333 *edx = ((l3->size / (512 * 1024)) << 18) | 334 (AMD_ENC_ASSOC(l3->associativity) << 12) | 335 (l3->lines_per_tag << 8) | (l3->line_size); 336 } else { 337 *edx = 0; 338 } 339 } 340 341 /* Encode cache info for CPUID[8000001D] */ 342 static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, 343 X86CPUTopoInfo *topo_info, 344 uint32_t *eax, uint32_t *ebx, 345 uint32_t *ecx, uint32_t *edx) 346 { 347 uint32_t l3_threads; 348 assert(cache->size == cache->line_size * cache->associativity * 349 cache->partitions * cache->sets); 350 351 *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) | 352 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0); 353 354 /* L3 is shared among multiple cores */ 355 if (cache->level == 3) { 356 l3_threads = topo_info->cores_per_die * topo_info->threads_per_core; 357 *eax |= (l3_threads - 1) << 14; 358 } else { 359 *eax |= ((topo_info->threads_per_core - 1) << 14); 360 } 361 362 assert(cache->line_size > 0); 363 assert(cache->partitions > 0); 364 assert(cache->associativity > 0); 365 /* We don't implement fully-associative caches */ 366 assert(cache->associativity < cache->sets); 367 *ebx = (cache->line_size - 1) | 368 ((cache->partitions - 1) << 12) | 369 ((cache->associativity - 1) << 22); 370 371 assert(cache->sets > 0); 372 *ecx = cache->sets - 1; 373 374 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) | 375 (cache->inclusive ? CACHE_INCLUSIVE : 0) | 376 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); 377 } 378 379 /* Encode cache info for CPUID[8000001E] */ 380 static void encode_topo_cpuid8000001e(X86CPU *cpu, X86CPUTopoInfo *topo_info, 381 uint32_t *eax, uint32_t *ebx, 382 uint32_t *ecx, uint32_t *edx) 383 { 384 X86CPUTopoIDs topo_ids; 385 386 x86_topo_ids_from_apicid(cpu->apic_id, topo_info, &topo_ids); 387 388 *eax = cpu->apic_id; 389 390 /* 391 * CPUID_Fn8000001E_EBX [Core Identifiers] (CoreId) 392 * Read-only. Reset: 0000_XXXXh. 393 * See Core::X86::Cpuid::ExtApicId. 394 * Core::X86::Cpuid::CoreId_lthree[1:0]_core[3:0]_thread[1:0]; 395 * Bits Description 396 * 31:16 Reserved. 397 * 15:8 ThreadsPerCore: threads per core. Read-only. Reset: XXh. 398 * The number of threads per core is ThreadsPerCore+1. 399 * 7:0 CoreId: core ID. Read-only. Reset: XXh. 400 * 401 * NOTE: CoreId is already part of apic_id. Just use it. We can 402 * use all the 8 bits to represent the core_id here. 403 */ 404 *ebx = ((topo_info->threads_per_core - 1) << 8) | (topo_ids.core_id & 0xFF); 405 406 /* 407 * CPUID_Fn8000001E_ECX [Node Identifiers] (NodeId) 408 * Read-only. Reset: 0000_0XXXh. 409 * Core::X86::Cpuid::NodeId_lthree[1:0]_core[3:0]_thread[1:0]; 410 * Bits Description 411 * 31:11 Reserved. 412 * 10:8 NodesPerProcessor: Node per processor. Read-only. Reset: XXXb. 413 * ValidValues: 414 * Value Description 415 * 000b 1 node per processor. 416 * 001b 2 nodes per processor. 417 * 010b Reserved. 418 * 011b 4 nodes per processor. 419 * 111b-100b Reserved. 420 * 7:0 NodeId: Node ID. Read-only. Reset: XXh. 421 * 422 * NOTE: Hardware reserves 3 bits for number of nodes per processor. 423 * But users can create more nodes than the actual hardware can 424 * support. To genaralize we can use all the upper 8 bits for nodes. 425 * NodeId is combination of node and socket_id which is already decoded 426 * in apic_id. Just use it by shifting. 427 */ 428 *ecx = ((topo_info->dies_per_pkg - 1) << 8) | 429 ((cpu->apic_id >> apicid_die_offset(topo_info)) & 0xFF); 430 431 *edx = 0; 432 } 433 434 /* 435 * Definitions of the hardcoded cache entries we expose: 436 * These are legacy cache values. If there is a need to change any 437 * of these values please use builtin_x86_defs 438 */ 439 440 /* L1 data cache: */ 441 static CPUCacheInfo legacy_l1d_cache = { 442 .type = DATA_CACHE, 443 .level = 1, 444 .size = 32 * KiB, 445 .self_init = 1, 446 .line_size = 64, 447 .associativity = 8, 448 .sets = 64, 449 .partitions = 1, 450 .no_invd_sharing = true, 451 }; 452 453 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ 454 static CPUCacheInfo legacy_l1d_cache_amd = { 455 .type = DATA_CACHE, 456 .level = 1, 457 .size = 64 * KiB, 458 .self_init = 1, 459 .line_size = 64, 460 .associativity = 2, 461 .sets = 512, 462 .partitions = 1, 463 .lines_per_tag = 1, 464 .no_invd_sharing = true, 465 }; 466 467 /* L1 instruction cache: */ 468 static CPUCacheInfo legacy_l1i_cache = { 469 .type = INSTRUCTION_CACHE, 470 .level = 1, 471 .size = 32 * KiB, 472 .self_init = 1, 473 .line_size = 64, 474 .associativity = 8, 475 .sets = 64, 476 .partitions = 1, 477 .no_invd_sharing = true, 478 }; 479 480 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ 481 static CPUCacheInfo legacy_l1i_cache_amd = { 482 .type = INSTRUCTION_CACHE, 483 .level = 1, 484 .size = 64 * KiB, 485 .self_init = 1, 486 .line_size = 64, 487 .associativity = 2, 488 .sets = 512, 489 .partitions = 1, 490 .lines_per_tag = 1, 491 .no_invd_sharing = true, 492 }; 493 494 /* Level 2 unified cache: */ 495 static CPUCacheInfo legacy_l2_cache = { 496 .type = UNIFIED_CACHE, 497 .level = 2, 498 .size = 4 * MiB, 499 .self_init = 1, 500 .line_size = 64, 501 .associativity = 16, 502 .sets = 4096, 503 .partitions = 1, 504 .no_invd_sharing = true, 505 }; 506 507 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */ 508 static CPUCacheInfo legacy_l2_cache_cpuid2 = { 509 .type = UNIFIED_CACHE, 510 .level = 2, 511 .size = 2 * MiB, 512 .line_size = 64, 513 .associativity = 8, 514 }; 515 516 517 /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */ 518 static CPUCacheInfo legacy_l2_cache_amd = { 519 .type = UNIFIED_CACHE, 520 .level = 2, 521 .size = 512 * KiB, 522 .line_size = 64, 523 .lines_per_tag = 1, 524 .associativity = 16, 525 .sets = 512, 526 .partitions = 1, 527 }; 528 529 /* Level 3 unified cache: */ 530 static CPUCacheInfo legacy_l3_cache = { 531 .type = UNIFIED_CACHE, 532 .level = 3, 533 .size = 16 * MiB, 534 .line_size = 64, 535 .associativity = 16, 536 .sets = 16384, 537 .partitions = 1, 538 .lines_per_tag = 1, 539 .self_init = true, 540 .inclusive = true, 541 .complex_indexing = true, 542 }; 543 544 /* TLB definitions: */ 545 546 #define L1_DTLB_2M_ASSOC 1 547 #define L1_DTLB_2M_ENTRIES 255 548 #define L1_DTLB_4K_ASSOC 1 549 #define L1_DTLB_4K_ENTRIES 255 550 551 #define L1_ITLB_2M_ASSOC 1 552 #define L1_ITLB_2M_ENTRIES 255 553 #define L1_ITLB_4K_ASSOC 1 554 #define L1_ITLB_4K_ENTRIES 255 555 556 #define L2_DTLB_2M_ASSOC 0 /* disabled */ 557 #define L2_DTLB_2M_ENTRIES 0 /* disabled */ 558 #define L2_DTLB_4K_ASSOC 4 559 #define L2_DTLB_4K_ENTRIES 512 560 561 #define L2_ITLB_2M_ASSOC 0 /* disabled */ 562 #define L2_ITLB_2M_ENTRIES 0 /* disabled */ 563 #define L2_ITLB_4K_ASSOC 4 564 #define L2_ITLB_4K_ENTRIES 512 565 566 /* CPUID Leaf 0x14 constants: */ 567 #define INTEL_PT_MAX_SUBLEAF 0x1 568 /* 569 * bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MATCH 570 * MSR can be accessed; 571 * bit[01]: Support Configurable PSB and Cycle-Accurate Mode; 572 * bit[02]: Support IP Filtering, TraceStop filtering, and preservation 573 * of Intel PT MSRs across warm reset; 574 * bit[03]: Support MTC timing packet and suppression of COFI-based packets; 575 */ 576 #define INTEL_PT_MINIMAL_EBX 0xf 577 /* 578 * bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 and 579 * IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be 580 * accessed; 581 * bit[01]: ToPA tables can hold any number of output entries, up to the 582 * maximum allowed by the MaskOrTableOffset field of 583 * IA32_RTIT_OUTPUT_MASK_PTRS; 584 * bit[02]: Support Single-Range Output scheme; 585 */ 586 #define INTEL_PT_MINIMAL_ECX 0x7 587 /* generated packets which contain IP payloads have LIP values */ 588 #define INTEL_PT_IP_LIP (1 << 31) 589 #define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */ 590 #define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3 591 #define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */ 592 #define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */ 593 #define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */ 594 595 static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1, 596 uint32_t vendor2, uint32_t vendor3) 597 { 598 int i; 599 for (i = 0; i < 4; i++) { 600 dst[i] = vendor1 >> (8 * i); 601 dst[i + 4] = vendor2 >> (8 * i); 602 dst[i + 8] = vendor3 >> (8 * i); 603 } 604 dst[CPUID_VENDOR_SZ] = '\0'; 605 } 606 607 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE) 608 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \ 609 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC) 610 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \ 611 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ 612 CPUID_PSE36 | CPUID_FXSR) 613 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE) 614 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \ 615 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \ 616 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \ 617 CPUID_PAE | CPUID_SEP | CPUID_APIC) 618 619 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \ 620 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \ 621 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ 622 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \ 623 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE) 624 /* partly implemented: 625 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */ 626 /* missing: 627 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */ 628 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \ 629 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \ 630 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \ 631 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \ 632 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR | \ 633 CPUID_EXT_RDRAND) 634 /* missing: 635 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX, 636 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA, 637 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA, 638 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_AVX, 639 CPUID_EXT_F16C */ 640 641 #ifdef TARGET_X86_64 642 #define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM) 643 #else 644 #define TCG_EXT2_X86_64_FEATURES 0 645 #endif 646 647 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \ 648 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \ 649 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \ 650 TCG_EXT2_X86_64_FEATURES) 651 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \ 652 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A) 653 #define TCG_EXT4_FEATURES 0 654 #define TCG_SVM_FEATURES CPUID_SVM_NPT 655 #define TCG_KVM_FEATURES 0 656 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \ 657 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \ 658 CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \ 659 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \ 660 CPUID_7_0_EBX_ERMS) 661 /* missing: 662 CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2, 663 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM, 664 CPUID_7_0_EBX_RDSEED */ 665 #define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_PKU | \ 666 /* CPUID_7_0_ECX_OSPKE is dynamic */ \ 667 CPUID_7_0_ECX_LA57) 668 #define TCG_7_0_EDX_FEATURES 0 669 #define TCG_7_1_EAX_FEATURES 0 670 #define TCG_APM_FEATURES 0 671 #define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT 672 #define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1) 673 /* missing: 674 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */ 675 676 typedef enum FeatureWordType { 677 CPUID_FEATURE_WORD, 678 MSR_FEATURE_WORD, 679 } FeatureWordType; 680 681 typedef struct FeatureWordInfo { 682 FeatureWordType type; 683 /* feature flags names are taken from "Intel Processor Identification and 684 * the CPUID Instruction" and AMD's "CPUID Specification". 685 * In cases of disagreement between feature naming conventions, 686 * aliases may be added. 687 */ 688 const char *feat_names[64]; 689 union { 690 /* If type==CPUID_FEATURE_WORD */ 691 struct { 692 uint32_t eax; /* Input EAX for CPUID */ 693 bool needs_ecx; /* CPUID instruction uses ECX as input */ 694 uint32_t ecx; /* Input ECX value for CPUID */ 695 int reg; /* output register (R_* constant) */ 696 } cpuid; 697 /* If type==MSR_FEATURE_WORD */ 698 struct { 699 uint32_t index; 700 } msr; 701 }; 702 uint64_t tcg_features; /* Feature flags supported by TCG */ 703 uint64_t unmigratable_flags; /* Feature flags known to be unmigratable */ 704 uint64_t migratable_flags; /* Feature flags known to be migratable */ 705 /* Features that shouldn't be auto-enabled by "-cpu host" */ 706 uint64_t no_autoenable_flags; 707 } FeatureWordInfo; 708 709 static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { 710 [FEAT_1_EDX] = { 711 .type = CPUID_FEATURE_WORD, 712 .feat_names = { 713 "fpu", "vme", "de", "pse", 714 "tsc", "msr", "pae", "mce", 715 "cx8", "apic", NULL, "sep", 716 "mtrr", "pge", "mca", "cmov", 717 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */, 718 NULL, "ds" /* Intel dts */, "acpi", "mmx", 719 "fxsr", "sse", "sse2", "ss", 720 "ht" /* Intel htt */, "tm", "ia64", "pbe", 721 }, 722 .cpuid = {.eax = 1, .reg = R_EDX, }, 723 .tcg_features = TCG_FEATURES, 724 }, 725 [FEAT_1_ECX] = { 726 .type = CPUID_FEATURE_WORD, 727 .feat_names = { 728 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor", 729 "ds-cpl", "vmx", "smx", "est", 730 "tm2", "ssse3", "cid", NULL, 731 "fma", "cx16", "xtpr", "pdcm", 732 NULL, "pcid", "dca", "sse4.1", 733 "sse4.2", "x2apic", "movbe", "popcnt", 734 "tsc-deadline", "aes", "xsave", NULL /* osxsave */, 735 "avx", "f16c", "rdrand", "hypervisor", 736 }, 737 .cpuid = { .eax = 1, .reg = R_ECX, }, 738 .tcg_features = TCG_EXT_FEATURES, 739 }, 740 /* Feature names that are already defined on feature_name[] but 741 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their 742 * names on feat_names below. They are copied automatically 743 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD. 744 */ 745 [FEAT_8000_0001_EDX] = { 746 .type = CPUID_FEATURE_WORD, 747 .feat_names = { 748 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */, 749 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */, 750 NULL /* cx8 */, NULL /* apic */, NULL, "syscall", 751 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */, 752 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */, 753 "nx", NULL, "mmxext", NULL /* mmx */, 754 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp", 755 NULL, "lm", "3dnowext", "3dnow", 756 }, 757 .cpuid = { .eax = 0x80000001, .reg = R_EDX, }, 758 .tcg_features = TCG_EXT2_FEATURES, 759 }, 760 [FEAT_8000_0001_ECX] = { 761 .type = CPUID_FEATURE_WORD, 762 .feat_names = { 763 "lahf-lm", "cmp-legacy", "svm", "extapic", 764 "cr8legacy", "abm", "sse4a", "misalignsse", 765 "3dnowprefetch", "osvw", "ibs", "xop", 766 "skinit", "wdt", NULL, "lwp", 767 "fma4", "tce", NULL, "nodeid-msr", 768 NULL, "tbm", "topoext", "perfctr-core", 769 "perfctr-nb", NULL, NULL, NULL, 770 NULL, NULL, NULL, NULL, 771 }, 772 .cpuid = { .eax = 0x80000001, .reg = R_ECX, }, 773 .tcg_features = TCG_EXT3_FEATURES, 774 /* 775 * TOPOEXT is always allowed but can't be enabled blindly by 776 * "-cpu host", as it requires consistent cache topology info 777 * to be provided so it doesn't confuse guests. 778 */ 779 .no_autoenable_flags = CPUID_EXT3_TOPOEXT, 780 }, 781 [FEAT_C000_0001_EDX] = { 782 .type = CPUID_FEATURE_WORD, 783 .feat_names = { 784 NULL, NULL, "xstore", "xstore-en", 785 NULL, NULL, "xcrypt", "xcrypt-en", 786 "ace2", "ace2-en", "phe", "phe-en", 787 "pmm", "pmm-en", NULL, NULL, 788 NULL, NULL, NULL, NULL, 789 NULL, NULL, NULL, NULL, 790 NULL, NULL, NULL, NULL, 791 NULL, NULL, NULL, NULL, 792 }, 793 .cpuid = { .eax = 0xC0000001, .reg = R_EDX, }, 794 .tcg_features = TCG_EXT4_FEATURES, 795 }, 796 [FEAT_KVM] = { 797 .type = CPUID_FEATURE_WORD, 798 .feat_names = { 799 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock", 800 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt", 801 NULL, "kvm-pv-tlb-flush", NULL, "kvm-pv-ipi", 802 "kvm-poll-control", "kvm-pv-sched-yield", "kvm-asyncpf-int", NULL, 803 NULL, NULL, NULL, NULL, 804 NULL, NULL, NULL, NULL, 805 "kvmclock-stable-bit", NULL, NULL, NULL, 806 NULL, NULL, NULL, NULL, 807 }, 808 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EAX, }, 809 .tcg_features = TCG_KVM_FEATURES, 810 }, 811 [FEAT_KVM_HINTS] = { 812 .type = CPUID_FEATURE_WORD, 813 .feat_names = { 814 "kvm-hint-dedicated", NULL, NULL, NULL, 815 NULL, NULL, NULL, NULL, 816 NULL, NULL, NULL, NULL, 817 NULL, NULL, NULL, NULL, 818 NULL, NULL, NULL, NULL, 819 NULL, NULL, NULL, NULL, 820 NULL, NULL, NULL, NULL, 821 NULL, NULL, NULL, NULL, 822 }, 823 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EDX, }, 824 .tcg_features = TCG_KVM_FEATURES, 825 /* 826 * KVM hints aren't auto-enabled by -cpu host, they need to be 827 * explicitly enabled in the command-line. 828 */ 829 .no_autoenable_flags = ~0U, 830 }, 831 /* 832 * .feat_names are commented out for Hyper-V enlightenments because we 833 * don't want to have two different ways for enabling them on QEMU command 834 * line. Some features (e.g. "hyperv_time", "hyperv_vapic", ...) require 835 * enabling several feature bits simultaneously, exposing these bits 836 * individually may just confuse guests. 837 */ 838 [FEAT_HYPERV_EAX] = { 839 .type = CPUID_FEATURE_WORD, 840 .feat_names = { 841 NULL /* hv_msr_vp_runtime_access */, NULL /* hv_msr_time_refcount_access */, 842 NULL /* hv_msr_synic_access */, NULL /* hv_msr_stimer_access */, 843 NULL /* hv_msr_apic_access */, NULL /* hv_msr_hypercall_access */, 844 NULL /* hv_vpindex_access */, NULL /* hv_msr_reset_access */, 845 NULL /* hv_msr_stats_access */, NULL /* hv_reftsc_access */, 846 NULL /* hv_msr_idle_access */, NULL /* hv_msr_frequency_access */, 847 NULL /* hv_msr_debug_access */, NULL /* hv_msr_reenlightenment_access */, 848 NULL, NULL, 849 NULL, NULL, NULL, NULL, 850 NULL, NULL, NULL, NULL, 851 NULL, NULL, NULL, NULL, 852 NULL, NULL, NULL, NULL, 853 }, 854 .cpuid = { .eax = 0x40000003, .reg = R_EAX, }, 855 }, 856 [FEAT_HYPERV_EBX] = { 857 .type = CPUID_FEATURE_WORD, 858 .feat_names = { 859 NULL /* hv_create_partitions */, NULL /* hv_access_partition_id */, 860 NULL /* hv_access_memory_pool */, NULL /* hv_adjust_message_buffers */, 861 NULL /* hv_post_messages */, NULL /* hv_signal_events */, 862 NULL /* hv_create_port */, NULL /* hv_connect_port */, 863 NULL /* hv_access_stats */, NULL, NULL, NULL /* hv_debugging */, 864 NULL /* hv_cpu_power_management */, NULL /* hv_configure_profiler */, 865 NULL, NULL, 866 NULL, NULL, NULL, NULL, 867 NULL, NULL, NULL, NULL, 868 NULL, NULL, NULL, NULL, 869 NULL, NULL, NULL, NULL, 870 }, 871 .cpuid = { .eax = 0x40000003, .reg = R_EBX, }, 872 }, 873 [FEAT_HYPERV_EDX] = { 874 .type = CPUID_FEATURE_WORD, 875 .feat_names = { 876 NULL /* hv_mwait */, NULL /* hv_guest_debugging */, 877 NULL /* hv_perf_monitor */, NULL /* hv_cpu_dynamic_part */, 878 NULL /* hv_hypercall_params_xmm */, NULL /* hv_guest_idle_state */, 879 NULL, NULL, 880 NULL, NULL, NULL /* hv_guest_crash_msr */, NULL, 881 NULL, NULL, NULL, NULL, 882 NULL, NULL, NULL, NULL, 883 NULL, NULL, NULL, NULL, 884 NULL, NULL, NULL, NULL, 885 NULL, NULL, NULL, NULL, 886 }, 887 .cpuid = { .eax = 0x40000003, .reg = R_EDX, }, 888 }, 889 [FEAT_HV_RECOMM_EAX] = { 890 .type = CPUID_FEATURE_WORD, 891 .feat_names = { 892 NULL /* hv_recommend_pv_as_switch */, 893 NULL /* hv_recommend_pv_tlbflush_local */, 894 NULL /* hv_recommend_pv_tlbflush_remote */, 895 NULL /* hv_recommend_msr_apic_access */, 896 NULL /* hv_recommend_msr_reset */, 897 NULL /* hv_recommend_relaxed_timing */, 898 NULL /* hv_recommend_dma_remapping */, 899 NULL /* hv_recommend_int_remapping */, 900 NULL /* hv_recommend_x2apic_msrs */, 901 NULL /* hv_recommend_autoeoi_deprecation */, 902 NULL /* hv_recommend_pv_ipi */, 903 NULL /* hv_recommend_ex_hypercalls */, 904 NULL /* hv_hypervisor_is_nested */, 905 NULL /* hv_recommend_int_mbec */, 906 NULL /* hv_recommend_evmcs */, 907 NULL, 908 NULL, NULL, NULL, NULL, 909 NULL, NULL, NULL, NULL, 910 NULL, NULL, NULL, NULL, 911 NULL, NULL, NULL, NULL, 912 }, 913 .cpuid = { .eax = 0x40000004, .reg = R_EAX, }, 914 }, 915 [FEAT_HV_NESTED_EAX] = { 916 .type = CPUID_FEATURE_WORD, 917 .cpuid = { .eax = 0x4000000A, .reg = R_EAX, }, 918 }, 919 [FEAT_SVM] = { 920 .type = CPUID_FEATURE_WORD, 921 .feat_names = { 922 "npt", "lbrv", "svm-lock", "nrip-save", 923 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists", 924 NULL, NULL, "pause-filter", NULL, 925 "pfthreshold", NULL, NULL, NULL, 926 NULL, NULL, NULL, NULL, 927 NULL, NULL, NULL, NULL, 928 NULL, NULL, NULL, NULL, 929 NULL, NULL, NULL, NULL, 930 }, 931 .cpuid = { .eax = 0x8000000A, .reg = R_EDX, }, 932 .tcg_features = TCG_SVM_FEATURES, 933 }, 934 [FEAT_7_0_EBX] = { 935 .type = CPUID_FEATURE_WORD, 936 .feat_names = { 937 "fsgsbase", "tsc-adjust", NULL, "bmi1", 938 "hle", "avx2", NULL, "smep", 939 "bmi2", "erms", "invpcid", "rtm", 940 NULL, NULL, "mpx", NULL, 941 "avx512f", "avx512dq", "rdseed", "adx", 942 "smap", "avx512ifma", "pcommit", "clflushopt", 943 "clwb", "intel-pt", "avx512pf", "avx512er", 944 "avx512cd", "sha-ni", "avx512bw", "avx512vl", 945 }, 946 .cpuid = { 947 .eax = 7, 948 .needs_ecx = true, .ecx = 0, 949 .reg = R_EBX, 950 }, 951 .tcg_features = TCG_7_0_EBX_FEATURES, 952 }, 953 [FEAT_7_0_ECX] = { 954 .type = CPUID_FEATURE_WORD, 955 .feat_names = { 956 NULL, "avx512vbmi", "umip", "pku", 957 NULL /* ospke */, "waitpkg", "avx512vbmi2", NULL, 958 "gfni", "vaes", "vpclmulqdq", "avx512vnni", 959 "avx512bitalg", NULL, "avx512-vpopcntdq", NULL, 960 "la57", NULL, NULL, NULL, 961 NULL, NULL, "rdpid", NULL, 962 NULL, "cldemote", NULL, "movdiri", 963 "movdir64b", NULL, NULL, NULL, 964 }, 965 .cpuid = { 966 .eax = 7, 967 .needs_ecx = true, .ecx = 0, 968 .reg = R_ECX, 969 }, 970 .tcg_features = TCG_7_0_ECX_FEATURES, 971 }, 972 [FEAT_7_0_EDX] = { 973 .type = CPUID_FEATURE_WORD, 974 .feat_names = { 975 NULL, NULL, "avx512-4vnniw", "avx512-4fmaps", 976 "fsrm", NULL, NULL, NULL, 977 "avx512-vp2intersect", NULL, "md-clear", NULL, 978 NULL, NULL, "serialize", NULL, 979 "tsx-ldtrk", NULL, NULL /* pconfig */, NULL, 980 NULL, NULL, NULL, NULL, 981 NULL, NULL, "spec-ctrl", "stibp", 982 NULL, "arch-capabilities", "core-capability", "ssbd", 983 }, 984 .cpuid = { 985 .eax = 7, 986 .needs_ecx = true, .ecx = 0, 987 .reg = R_EDX, 988 }, 989 .tcg_features = TCG_7_0_EDX_FEATURES, 990 }, 991 [FEAT_7_1_EAX] = { 992 .type = CPUID_FEATURE_WORD, 993 .feat_names = { 994 NULL, NULL, NULL, NULL, 995 NULL, "avx512-bf16", NULL, NULL, 996 NULL, NULL, NULL, NULL, 997 NULL, NULL, NULL, NULL, 998 NULL, NULL, NULL, NULL, 999 NULL, NULL, NULL, NULL, 1000 NULL, NULL, NULL, NULL, 1001 NULL, NULL, NULL, NULL, 1002 }, 1003 .cpuid = { 1004 .eax = 7, 1005 .needs_ecx = true, .ecx = 1, 1006 .reg = R_EAX, 1007 }, 1008 .tcg_features = TCG_7_1_EAX_FEATURES, 1009 }, 1010 [FEAT_8000_0007_EDX] = { 1011 .type = CPUID_FEATURE_WORD, 1012 .feat_names = { 1013 NULL, NULL, NULL, NULL, 1014 NULL, NULL, NULL, NULL, 1015 "invtsc", NULL, NULL, NULL, 1016 NULL, NULL, NULL, NULL, 1017 NULL, NULL, NULL, NULL, 1018 NULL, NULL, NULL, NULL, 1019 NULL, NULL, NULL, NULL, 1020 NULL, NULL, NULL, NULL, 1021 }, 1022 .cpuid = { .eax = 0x80000007, .reg = R_EDX, }, 1023 .tcg_features = TCG_APM_FEATURES, 1024 .unmigratable_flags = CPUID_APM_INVTSC, 1025 }, 1026 [FEAT_8000_0008_EBX] = { 1027 .type = CPUID_FEATURE_WORD, 1028 .feat_names = { 1029 "clzero", NULL, "xsaveerptr", NULL, 1030 NULL, NULL, NULL, NULL, 1031 NULL, "wbnoinvd", NULL, NULL, 1032 "ibpb", NULL, NULL, "amd-stibp", 1033 NULL, NULL, NULL, NULL, 1034 NULL, NULL, NULL, NULL, 1035 "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL, 1036 NULL, NULL, NULL, NULL, 1037 }, 1038 .cpuid = { .eax = 0x80000008, .reg = R_EBX, }, 1039 .tcg_features = 0, 1040 .unmigratable_flags = 0, 1041 }, 1042 [FEAT_XSAVE] = { 1043 .type = CPUID_FEATURE_WORD, 1044 .feat_names = { 1045 "xsaveopt", "xsavec", "xgetbv1", "xsaves", 1046 NULL, NULL, NULL, NULL, 1047 NULL, NULL, NULL, NULL, 1048 NULL, NULL, NULL, NULL, 1049 NULL, NULL, NULL, NULL, 1050 NULL, NULL, NULL, NULL, 1051 NULL, NULL, NULL, NULL, 1052 NULL, NULL, NULL, NULL, 1053 }, 1054 .cpuid = { 1055 .eax = 0xd, 1056 .needs_ecx = true, .ecx = 1, 1057 .reg = R_EAX, 1058 }, 1059 .tcg_features = TCG_XSAVE_FEATURES, 1060 }, 1061 [FEAT_6_EAX] = { 1062 .type = CPUID_FEATURE_WORD, 1063 .feat_names = { 1064 NULL, NULL, "arat", NULL, 1065 NULL, NULL, NULL, NULL, 1066 NULL, NULL, NULL, NULL, 1067 NULL, NULL, NULL, NULL, 1068 NULL, NULL, NULL, NULL, 1069 NULL, NULL, NULL, NULL, 1070 NULL, NULL, NULL, NULL, 1071 NULL, NULL, NULL, NULL, 1072 }, 1073 .cpuid = { .eax = 6, .reg = R_EAX, }, 1074 .tcg_features = TCG_6_EAX_FEATURES, 1075 }, 1076 [FEAT_XSAVE_COMP_LO] = { 1077 .type = CPUID_FEATURE_WORD, 1078 .cpuid = { 1079 .eax = 0xD, 1080 .needs_ecx = true, .ecx = 0, 1081 .reg = R_EAX, 1082 }, 1083 .tcg_features = ~0U, 1084 .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK | 1085 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK | 1086 XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK | 1087 XSTATE_PKRU_MASK, 1088 }, 1089 [FEAT_XSAVE_COMP_HI] = { 1090 .type = CPUID_FEATURE_WORD, 1091 .cpuid = { 1092 .eax = 0xD, 1093 .needs_ecx = true, .ecx = 0, 1094 .reg = R_EDX, 1095 }, 1096 .tcg_features = ~0U, 1097 }, 1098 /*Below are MSR exposed features*/ 1099 [FEAT_ARCH_CAPABILITIES] = { 1100 .type = MSR_FEATURE_WORD, 1101 .feat_names = { 1102 "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry", 1103 "ssb-no", "mds-no", "pschange-mc-no", "tsx-ctrl", 1104 "taa-no", NULL, NULL, NULL, 1105 NULL, NULL, NULL, NULL, 1106 NULL, NULL, NULL, NULL, 1107 NULL, NULL, NULL, NULL, 1108 NULL, NULL, NULL, NULL, 1109 NULL, NULL, NULL, NULL, 1110 }, 1111 .msr = { 1112 .index = MSR_IA32_ARCH_CAPABILITIES, 1113 }, 1114 }, 1115 [FEAT_CORE_CAPABILITY] = { 1116 .type = MSR_FEATURE_WORD, 1117 .feat_names = { 1118 NULL, NULL, NULL, NULL, 1119 NULL, "split-lock-detect", NULL, NULL, 1120 NULL, NULL, NULL, NULL, 1121 NULL, NULL, NULL, NULL, 1122 NULL, NULL, NULL, NULL, 1123 NULL, NULL, NULL, NULL, 1124 NULL, NULL, NULL, NULL, 1125 NULL, NULL, NULL, NULL, 1126 }, 1127 .msr = { 1128 .index = MSR_IA32_CORE_CAPABILITY, 1129 }, 1130 }, 1131 [FEAT_PERF_CAPABILITIES] = { 1132 .type = MSR_FEATURE_WORD, 1133 .feat_names = { 1134 NULL, NULL, NULL, NULL, 1135 NULL, NULL, NULL, NULL, 1136 NULL, NULL, NULL, NULL, 1137 NULL, "full-width-write", NULL, NULL, 1138 NULL, NULL, NULL, NULL, 1139 NULL, NULL, NULL, NULL, 1140 NULL, NULL, NULL, NULL, 1141 NULL, NULL, NULL, NULL, 1142 }, 1143 .msr = { 1144 .index = MSR_IA32_PERF_CAPABILITIES, 1145 }, 1146 }, 1147 1148 [FEAT_VMX_PROCBASED_CTLS] = { 1149 .type = MSR_FEATURE_WORD, 1150 .feat_names = { 1151 NULL, NULL, "vmx-vintr-pending", "vmx-tsc-offset", 1152 NULL, NULL, NULL, "vmx-hlt-exit", 1153 NULL, "vmx-invlpg-exit", "vmx-mwait-exit", "vmx-rdpmc-exit", 1154 "vmx-rdtsc-exit", NULL, NULL, "vmx-cr3-load-noexit", 1155 "vmx-cr3-store-noexit", NULL, NULL, "vmx-cr8-load-exit", 1156 "vmx-cr8-store-exit", "vmx-flexpriority", "vmx-vnmi-pending", "vmx-movdr-exit", 1157 "vmx-io-exit", "vmx-io-bitmap", NULL, "vmx-mtf", 1158 "vmx-msr-bitmap", "vmx-monitor-exit", "vmx-pause-exit", "vmx-secondary-ctls", 1159 }, 1160 .msr = { 1161 .index = MSR_IA32_VMX_TRUE_PROCBASED_CTLS, 1162 } 1163 }, 1164 1165 [FEAT_VMX_SECONDARY_CTLS] = { 1166 .type = MSR_FEATURE_WORD, 1167 .feat_names = { 1168 "vmx-apicv-xapic", "vmx-ept", "vmx-desc-exit", "vmx-rdtscp-exit", 1169 "vmx-apicv-x2apic", "vmx-vpid", "vmx-wbinvd-exit", "vmx-unrestricted-guest", 1170 "vmx-apicv-register", "vmx-apicv-vid", "vmx-ple", "vmx-rdrand-exit", 1171 "vmx-invpcid-exit", "vmx-vmfunc", "vmx-shadow-vmcs", "vmx-encls-exit", 1172 "vmx-rdseed-exit", "vmx-pml", NULL, NULL, 1173 "vmx-xsaves", NULL, NULL, NULL, 1174 NULL, NULL, NULL, NULL, 1175 NULL, NULL, NULL, NULL, 1176 }, 1177 .msr = { 1178 .index = MSR_IA32_VMX_PROCBASED_CTLS2, 1179 } 1180 }, 1181 1182 [FEAT_VMX_PINBASED_CTLS] = { 1183 .type = MSR_FEATURE_WORD, 1184 .feat_names = { 1185 "vmx-intr-exit", NULL, NULL, "vmx-nmi-exit", 1186 NULL, "vmx-vnmi", "vmx-preemption-timer", "vmx-posted-intr", 1187 NULL, NULL, NULL, NULL, 1188 NULL, NULL, NULL, NULL, 1189 NULL, NULL, NULL, NULL, 1190 NULL, NULL, NULL, NULL, 1191 NULL, NULL, NULL, NULL, 1192 NULL, NULL, NULL, NULL, 1193 }, 1194 .msr = { 1195 .index = MSR_IA32_VMX_TRUE_PINBASED_CTLS, 1196 } 1197 }, 1198 1199 [FEAT_VMX_EXIT_CTLS] = { 1200 .type = MSR_FEATURE_WORD, 1201 /* 1202 * VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE is copied from 1203 * the LM CPUID bit. 1204 */ 1205 .feat_names = { 1206 NULL, NULL, "vmx-exit-nosave-debugctl", NULL, 1207 NULL, NULL, NULL, NULL, 1208 NULL, NULL /* vmx-exit-host-addr-space-size */, NULL, NULL, 1209 "vmx-exit-load-perf-global-ctrl", NULL, NULL, "vmx-exit-ack-intr", 1210 NULL, NULL, "vmx-exit-save-pat", "vmx-exit-load-pat", 1211 "vmx-exit-save-efer", "vmx-exit-load-efer", 1212 "vmx-exit-save-preemption-timer", "vmx-exit-clear-bndcfgs", 1213 NULL, "vmx-exit-clear-rtit-ctl", NULL, NULL, 1214 NULL, NULL, NULL, NULL, 1215 }, 1216 .msr = { 1217 .index = MSR_IA32_VMX_TRUE_EXIT_CTLS, 1218 } 1219 }, 1220 1221 [FEAT_VMX_ENTRY_CTLS] = { 1222 .type = MSR_FEATURE_WORD, 1223 .feat_names = { 1224 NULL, NULL, "vmx-entry-noload-debugctl", NULL, 1225 NULL, NULL, NULL, NULL, 1226 NULL, "vmx-entry-ia32e-mode", NULL, NULL, 1227 NULL, "vmx-entry-load-perf-global-ctrl", "vmx-entry-load-pat", "vmx-entry-load-efer", 1228 "vmx-entry-load-bndcfgs", NULL, "vmx-entry-load-rtit-ctl", NULL, 1229 NULL, NULL, NULL, NULL, 1230 NULL, NULL, NULL, NULL, 1231 NULL, NULL, NULL, NULL, 1232 }, 1233 .msr = { 1234 .index = MSR_IA32_VMX_TRUE_ENTRY_CTLS, 1235 } 1236 }, 1237 1238 [FEAT_VMX_MISC] = { 1239 .type = MSR_FEATURE_WORD, 1240 .feat_names = { 1241 NULL, NULL, NULL, NULL, 1242 NULL, "vmx-store-lma", "vmx-activity-hlt", "vmx-activity-shutdown", 1243 "vmx-activity-wait-sipi", NULL, NULL, NULL, 1244 NULL, NULL, NULL, NULL, 1245 NULL, NULL, NULL, NULL, 1246 NULL, NULL, NULL, NULL, 1247 NULL, NULL, NULL, NULL, 1248 NULL, "vmx-vmwrite-vmexit-fields", "vmx-zero-len-inject", NULL, 1249 }, 1250 .msr = { 1251 .index = MSR_IA32_VMX_MISC, 1252 } 1253 }, 1254 1255 [FEAT_VMX_EPT_VPID_CAPS] = { 1256 .type = MSR_FEATURE_WORD, 1257 .feat_names = { 1258 "vmx-ept-execonly", NULL, NULL, NULL, 1259 NULL, NULL, "vmx-page-walk-4", "vmx-page-walk-5", 1260 NULL, NULL, NULL, NULL, 1261 NULL, NULL, NULL, NULL, 1262 "vmx-ept-2mb", "vmx-ept-1gb", NULL, NULL, 1263 "vmx-invept", "vmx-eptad", "vmx-ept-advanced-exitinfo", NULL, 1264 NULL, "vmx-invept-single-context", "vmx-invept-all-context", NULL, 1265 NULL, NULL, NULL, NULL, 1266 "vmx-invvpid", NULL, NULL, NULL, 1267 NULL, NULL, NULL, NULL, 1268 "vmx-invvpid-single-addr", "vmx-invept-single-context", 1269 "vmx-invvpid-all-context", "vmx-invept-single-context-noglobals", 1270 NULL, NULL, NULL, NULL, 1271 NULL, NULL, NULL, NULL, 1272 NULL, NULL, NULL, NULL, 1273 NULL, NULL, NULL, NULL, 1274 NULL, NULL, NULL, NULL, 1275 }, 1276 .msr = { 1277 .index = MSR_IA32_VMX_EPT_VPID_CAP, 1278 } 1279 }, 1280 1281 [FEAT_VMX_BASIC] = { 1282 .type = MSR_FEATURE_WORD, 1283 .feat_names = { 1284 [54] = "vmx-ins-outs", 1285 [55] = "vmx-true-ctls", 1286 }, 1287 .msr = { 1288 .index = MSR_IA32_VMX_BASIC, 1289 }, 1290 /* Just to be safe - we don't support setting the MSEG version field. */ 1291 .no_autoenable_flags = MSR_VMX_BASIC_DUAL_MONITOR, 1292 }, 1293 1294 [FEAT_VMX_VMFUNC] = { 1295 .type = MSR_FEATURE_WORD, 1296 .feat_names = { 1297 [0] = "vmx-eptp-switching", 1298 }, 1299 .msr = { 1300 .index = MSR_IA32_VMX_VMFUNC, 1301 } 1302 }, 1303 1304 }; 1305 1306 typedef struct FeatureMask { 1307 FeatureWord index; 1308 uint64_t mask; 1309 } FeatureMask; 1310 1311 typedef struct FeatureDep { 1312 FeatureMask from, to; 1313 } FeatureDep; 1314 1315 static FeatureDep feature_dependencies[] = { 1316 { 1317 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_ARCH_CAPABILITIES }, 1318 .to = { FEAT_ARCH_CAPABILITIES, ~0ull }, 1319 }, 1320 { 1321 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_CORE_CAPABILITY }, 1322 .to = { FEAT_CORE_CAPABILITY, ~0ull }, 1323 }, 1324 { 1325 .from = { FEAT_1_ECX, CPUID_EXT_PDCM }, 1326 .to = { FEAT_PERF_CAPABILITIES, ~0ull }, 1327 }, 1328 { 1329 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1330 .to = { FEAT_VMX_PROCBASED_CTLS, ~0ull }, 1331 }, 1332 { 1333 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1334 .to = { FEAT_VMX_PINBASED_CTLS, ~0ull }, 1335 }, 1336 { 1337 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1338 .to = { FEAT_VMX_EXIT_CTLS, ~0ull }, 1339 }, 1340 { 1341 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1342 .to = { FEAT_VMX_ENTRY_CTLS, ~0ull }, 1343 }, 1344 { 1345 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1346 .to = { FEAT_VMX_MISC, ~0ull }, 1347 }, 1348 { 1349 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1350 .to = { FEAT_VMX_BASIC, ~0ull }, 1351 }, 1352 { 1353 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_LM }, 1354 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_IA32E_MODE }, 1355 }, 1356 { 1357 .from = { FEAT_VMX_PROCBASED_CTLS, VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS }, 1358 .to = { FEAT_VMX_SECONDARY_CTLS, ~0ull }, 1359 }, 1360 { 1361 .from = { FEAT_XSAVE, CPUID_XSAVE_XSAVES }, 1362 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_XSAVES }, 1363 }, 1364 { 1365 .from = { FEAT_1_ECX, CPUID_EXT_RDRAND }, 1366 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDRAND_EXITING }, 1367 }, 1368 { 1369 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INVPCID }, 1370 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_INVPCID }, 1371 }, 1372 { 1373 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_RDSEED }, 1374 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDSEED_EXITING }, 1375 }, 1376 { 1377 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_RDTSCP }, 1378 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDTSCP }, 1379 }, 1380 { 1381 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT }, 1382 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull }, 1383 }, 1384 { 1385 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT }, 1386 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST }, 1387 }, 1388 { 1389 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VPID }, 1390 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull << 32 }, 1391 }, 1392 { 1393 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VMFUNC }, 1394 .to = { FEAT_VMX_VMFUNC, ~0ull }, 1395 }, 1396 { 1397 .from = { FEAT_8000_0001_ECX, CPUID_EXT3_SVM }, 1398 .to = { FEAT_SVM, ~0ull }, 1399 }, 1400 }; 1401 1402 typedef struct X86RegisterInfo32 { 1403 /* Name of register */ 1404 const char *name; 1405 /* QAPI enum value register */ 1406 X86CPURegister32 qapi_enum; 1407 } X86RegisterInfo32; 1408 1409 #define REGISTER(reg) \ 1410 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg } 1411 static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = { 1412 REGISTER(EAX), 1413 REGISTER(ECX), 1414 REGISTER(EDX), 1415 REGISTER(EBX), 1416 REGISTER(ESP), 1417 REGISTER(EBP), 1418 REGISTER(ESI), 1419 REGISTER(EDI), 1420 }; 1421 #undef REGISTER 1422 1423 typedef struct ExtSaveArea { 1424 uint32_t feature, bits; 1425 uint32_t offset, size; 1426 } ExtSaveArea; 1427 1428 static const ExtSaveArea x86_ext_save_areas[] = { 1429 [XSTATE_FP_BIT] = { 1430 /* x87 FP state component is always enabled if XSAVE is supported */ 1431 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE, 1432 /* x87 state is in the legacy region of the XSAVE area */ 1433 .offset = 0, 1434 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader), 1435 }, 1436 [XSTATE_SSE_BIT] = { 1437 /* SSE state component is always enabled if XSAVE is supported */ 1438 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE, 1439 /* SSE state is in the legacy region of the XSAVE area */ 1440 .offset = 0, 1441 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader), 1442 }, 1443 [XSTATE_YMM_BIT] = 1444 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX, 1445 .offset = offsetof(X86XSaveArea, avx_state), 1446 .size = sizeof(XSaveAVX) }, 1447 [XSTATE_BNDREGS_BIT] = 1448 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX, 1449 .offset = offsetof(X86XSaveArea, bndreg_state), 1450 .size = sizeof(XSaveBNDREG) }, 1451 [XSTATE_BNDCSR_BIT] = 1452 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX, 1453 .offset = offsetof(X86XSaveArea, bndcsr_state), 1454 .size = sizeof(XSaveBNDCSR) }, 1455 [XSTATE_OPMASK_BIT] = 1456 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1457 .offset = offsetof(X86XSaveArea, opmask_state), 1458 .size = sizeof(XSaveOpmask) }, 1459 [XSTATE_ZMM_Hi256_BIT] = 1460 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1461 .offset = offsetof(X86XSaveArea, zmm_hi256_state), 1462 .size = sizeof(XSaveZMM_Hi256) }, 1463 [XSTATE_Hi16_ZMM_BIT] = 1464 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1465 .offset = offsetof(X86XSaveArea, hi16_zmm_state), 1466 .size = sizeof(XSaveHi16_ZMM) }, 1467 [XSTATE_PKRU_BIT] = 1468 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU, 1469 .offset = offsetof(X86XSaveArea, pkru_state), 1470 .size = sizeof(XSavePKRU) }, 1471 }; 1472 1473 static uint32_t xsave_area_size(uint64_t mask) 1474 { 1475 int i; 1476 uint64_t ret = 0; 1477 1478 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 1479 const ExtSaveArea *esa = &x86_ext_save_areas[i]; 1480 if ((mask >> i) & 1) { 1481 ret = MAX(ret, esa->offset + esa->size); 1482 } 1483 } 1484 return ret; 1485 } 1486 1487 static inline bool accel_uses_host_cpuid(void) 1488 { 1489 return kvm_enabled() || hvf_enabled(); 1490 } 1491 1492 static inline uint64_t x86_cpu_xsave_components(X86CPU *cpu) 1493 { 1494 return ((uint64_t)cpu->env.features[FEAT_XSAVE_COMP_HI]) << 32 | 1495 cpu->env.features[FEAT_XSAVE_COMP_LO]; 1496 } 1497 1498 const char *get_register_name_32(unsigned int reg) 1499 { 1500 if (reg >= CPU_NB_REGS32) { 1501 return NULL; 1502 } 1503 return x86_reg_info_32[reg].name; 1504 } 1505 1506 /* 1507 * Returns the set of feature flags that are supported and migratable by 1508 * QEMU, for a given FeatureWord. 1509 */ 1510 static uint64_t x86_cpu_get_migratable_flags(FeatureWord w) 1511 { 1512 FeatureWordInfo *wi = &feature_word_info[w]; 1513 uint64_t r = 0; 1514 int i; 1515 1516 for (i = 0; i < 64; i++) { 1517 uint64_t f = 1ULL << i; 1518 1519 /* If the feature name is known, it is implicitly considered migratable, 1520 * unless it is explicitly set in unmigratable_flags */ 1521 if ((wi->migratable_flags & f) || 1522 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) { 1523 r |= f; 1524 } 1525 } 1526 return r; 1527 } 1528 1529 void host_cpuid(uint32_t function, uint32_t count, 1530 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) 1531 { 1532 uint32_t vec[4]; 1533 1534 #ifdef __x86_64__ 1535 asm volatile("cpuid" 1536 : "=a"(vec[0]), "=b"(vec[1]), 1537 "=c"(vec[2]), "=d"(vec[3]) 1538 : "0"(function), "c"(count) : "cc"); 1539 #elif defined(__i386__) 1540 asm volatile("pusha \n\t" 1541 "cpuid \n\t" 1542 "mov %%eax, 0(%2) \n\t" 1543 "mov %%ebx, 4(%2) \n\t" 1544 "mov %%ecx, 8(%2) \n\t" 1545 "mov %%edx, 12(%2) \n\t" 1546 "popa" 1547 : : "a"(function), "c"(count), "S"(vec) 1548 : "memory", "cc"); 1549 #else 1550 abort(); 1551 #endif 1552 1553 if (eax) 1554 *eax = vec[0]; 1555 if (ebx) 1556 *ebx = vec[1]; 1557 if (ecx) 1558 *ecx = vec[2]; 1559 if (edx) 1560 *edx = vec[3]; 1561 } 1562 1563 void host_vendor_fms(char *vendor, int *family, int *model, int *stepping) 1564 { 1565 uint32_t eax, ebx, ecx, edx; 1566 1567 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx); 1568 x86_cpu_vendor_words2str(vendor, ebx, edx, ecx); 1569 1570 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx); 1571 if (family) { 1572 *family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF); 1573 } 1574 if (model) { 1575 *model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12); 1576 } 1577 if (stepping) { 1578 *stepping = eax & 0x0F; 1579 } 1580 } 1581 1582 /* CPU class name definitions: */ 1583 1584 /* Return type name for a given CPU model name 1585 * Caller is responsible for freeing the returned string. 1586 */ 1587 static char *x86_cpu_type_name(const char *model_name) 1588 { 1589 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name); 1590 } 1591 1592 static ObjectClass *x86_cpu_class_by_name(const char *cpu_model) 1593 { 1594 g_autofree char *typename = x86_cpu_type_name(cpu_model); 1595 return object_class_by_name(typename); 1596 } 1597 1598 static char *x86_cpu_class_get_model_name(X86CPUClass *cc) 1599 { 1600 const char *class_name = object_class_get_name(OBJECT_CLASS(cc)); 1601 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX)); 1602 return g_strndup(class_name, 1603 strlen(class_name) - strlen(X86_CPU_TYPE_SUFFIX)); 1604 } 1605 1606 typedef struct PropValue { 1607 const char *prop, *value; 1608 } PropValue; 1609 1610 typedef struct X86CPUVersionDefinition { 1611 X86CPUVersion version; 1612 const char *alias; 1613 const char *note; 1614 PropValue *props; 1615 } X86CPUVersionDefinition; 1616 1617 /* Base definition for a CPU model */ 1618 typedef struct X86CPUDefinition { 1619 const char *name; 1620 uint32_t level; 1621 uint32_t xlevel; 1622 /* vendor is zero-terminated, 12 character ASCII string */ 1623 char vendor[CPUID_VENDOR_SZ + 1]; 1624 int family; 1625 int model; 1626 int stepping; 1627 FeatureWordArray features; 1628 const char *model_id; 1629 CPUCaches *cache_info; 1630 /* 1631 * Definitions for alternative versions of CPU model. 1632 * List is terminated by item with version == 0. 1633 * If NULL, version 1 will be registered automatically. 1634 */ 1635 const X86CPUVersionDefinition *versions; 1636 const char *deprecation_note; 1637 } X86CPUDefinition; 1638 1639 /* Reference to a specific CPU model version */ 1640 struct X86CPUModel { 1641 /* Base CPU definition */ 1642 X86CPUDefinition *cpudef; 1643 /* CPU model version */ 1644 X86CPUVersion version; 1645 const char *note; 1646 /* 1647 * If true, this is an alias CPU model. 1648 * This matters only for "-cpu help" and query-cpu-definitions 1649 */ 1650 bool is_alias; 1651 }; 1652 1653 /* Get full model name for CPU version */ 1654 static char *x86_cpu_versioned_model_name(X86CPUDefinition *cpudef, 1655 X86CPUVersion version) 1656 { 1657 assert(version > 0); 1658 return g_strdup_printf("%s-v%d", cpudef->name, (int)version); 1659 } 1660 1661 static const X86CPUVersionDefinition *x86_cpu_def_get_versions(X86CPUDefinition *def) 1662 { 1663 /* When X86CPUDefinition::versions is NULL, we register only v1 */ 1664 static const X86CPUVersionDefinition default_version_list[] = { 1665 { 1 }, 1666 { /* end of list */ } 1667 }; 1668 1669 return def->versions ?: default_version_list; 1670 } 1671 1672 static CPUCaches epyc_cache_info = { 1673 .l1d_cache = &(CPUCacheInfo) { 1674 .type = DATA_CACHE, 1675 .level = 1, 1676 .size = 32 * KiB, 1677 .line_size = 64, 1678 .associativity = 8, 1679 .partitions = 1, 1680 .sets = 64, 1681 .lines_per_tag = 1, 1682 .self_init = 1, 1683 .no_invd_sharing = true, 1684 }, 1685 .l1i_cache = &(CPUCacheInfo) { 1686 .type = INSTRUCTION_CACHE, 1687 .level = 1, 1688 .size = 64 * KiB, 1689 .line_size = 64, 1690 .associativity = 4, 1691 .partitions = 1, 1692 .sets = 256, 1693 .lines_per_tag = 1, 1694 .self_init = 1, 1695 .no_invd_sharing = true, 1696 }, 1697 .l2_cache = &(CPUCacheInfo) { 1698 .type = UNIFIED_CACHE, 1699 .level = 2, 1700 .size = 512 * KiB, 1701 .line_size = 64, 1702 .associativity = 8, 1703 .partitions = 1, 1704 .sets = 1024, 1705 .lines_per_tag = 1, 1706 }, 1707 .l3_cache = &(CPUCacheInfo) { 1708 .type = UNIFIED_CACHE, 1709 .level = 3, 1710 .size = 8 * MiB, 1711 .line_size = 64, 1712 .associativity = 16, 1713 .partitions = 1, 1714 .sets = 8192, 1715 .lines_per_tag = 1, 1716 .self_init = true, 1717 .inclusive = true, 1718 .complex_indexing = true, 1719 }, 1720 }; 1721 1722 static CPUCaches epyc_rome_cache_info = { 1723 .l1d_cache = &(CPUCacheInfo) { 1724 .type = DATA_CACHE, 1725 .level = 1, 1726 .size = 32 * KiB, 1727 .line_size = 64, 1728 .associativity = 8, 1729 .partitions = 1, 1730 .sets = 64, 1731 .lines_per_tag = 1, 1732 .self_init = 1, 1733 .no_invd_sharing = true, 1734 }, 1735 .l1i_cache = &(CPUCacheInfo) { 1736 .type = INSTRUCTION_CACHE, 1737 .level = 1, 1738 .size = 32 * KiB, 1739 .line_size = 64, 1740 .associativity = 8, 1741 .partitions = 1, 1742 .sets = 64, 1743 .lines_per_tag = 1, 1744 .self_init = 1, 1745 .no_invd_sharing = true, 1746 }, 1747 .l2_cache = &(CPUCacheInfo) { 1748 .type = UNIFIED_CACHE, 1749 .level = 2, 1750 .size = 512 * KiB, 1751 .line_size = 64, 1752 .associativity = 8, 1753 .partitions = 1, 1754 .sets = 1024, 1755 .lines_per_tag = 1, 1756 }, 1757 .l3_cache = &(CPUCacheInfo) { 1758 .type = UNIFIED_CACHE, 1759 .level = 3, 1760 .size = 16 * MiB, 1761 .line_size = 64, 1762 .associativity = 16, 1763 .partitions = 1, 1764 .sets = 16384, 1765 .lines_per_tag = 1, 1766 .self_init = true, 1767 .inclusive = true, 1768 .complex_indexing = true, 1769 }, 1770 }; 1771 1772 /* The following VMX features are not supported by KVM and are left out in the 1773 * CPU definitions: 1774 * 1775 * Dual-monitor support (all processors) 1776 * Entry to SMM 1777 * Deactivate dual-monitor treatment 1778 * Number of CR3-target values 1779 * Shutdown activity state 1780 * Wait-for-SIPI activity state 1781 * PAUSE-loop exiting (Westmere and newer) 1782 * EPT-violation #VE (Broadwell and newer) 1783 * Inject event with insn length=0 (Skylake and newer) 1784 * Conceal non-root operation from PT 1785 * Conceal VM exits from PT 1786 * Conceal VM entries from PT 1787 * Enable ENCLS exiting 1788 * Mode-based execute control (XS/XU) 1789 s TSC scaling (Skylake Server and newer) 1790 * GPA translation for PT (IceLake and newer) 1791 * User wait and pause 1792 * ENCLV exiting 1793 * Load IA32_RTIT_CTL 1794 * Clear IA32_RTIT_CTL 1795 * Advanced VM-exit information for EPT violations 1796 * Sub-page write permissions 1797 * PT in VMX operation 1798 */ 1799 1800 static X86CPUDefinition builtin_x86_defs[] = { 1801 { 1802 .name = "qemu64", 1803 .level = 0xd, 1804 .vendor = CPUID_VENDOR_AMD, 1805 .family = 6, 1806 .model = 6, 1807 .stepping = 3, 1808 .features[FEAT_1_EDX] = 1809 PPRO_FEATURES | 1810 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 1811 CPUID_PSE36, 1812 .features[FEAT_1_ECX] = 1813 CPUID_EXT_SSE3 | CPUID_EXT_CX16, 1814 .features[FEAT_8000_0001_EDX] = 1815 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 1816 .features[FEAT_8000_0001_ECX] = 1817 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM, 1818 .xlevel = 0x8000000A, 1819 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 1820 }, 1821 { 1822 .name = "phenom", 1823 .level = 5, 1824 .vendor = CPUID_VENDOR_AMD, 1825 .family = 16, 1826 .model = 2, 1827 .stepping = 3, 1828 /* Missing: CPUID_HT */ 1829 .features[FEAT_1_EDX] = 1830 PPRO_FEATURES | 1831 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 1832 CPUID_PSE36 | CPUID_VME, 1833 .features[FEAT_1_ECX] = 1834 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 | 1835 CPUID_EXT_POPCNT, 1836 .features[FEAT_8000_0001_EDX] = 1837 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | 1838 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT | 1839 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP, 1840 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, 1841 CPUID_EXT3_CR8LEG, 1842 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, 1843 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */ 1844 .features[FEAT_8000_0001_ECX] = 1845 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | 1846 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A, 1847 /* Missing: CPUID_SVM_LBRV */ 1848 .features[FEAT_SVM] = 1849 CPUID_SVM_NPT, 1850 .xlevel = 0x8000001A, 1851 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor" 1852 }, 1853 { 1854 .name = "core2duo", 1855 .level = 10, 1856 .vendor = CPUID_VENDOR_INTEL, 1857 .family = 6, 1858 .model = 15, 1859 .stepping = 11, 1860 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 1861 .features[FEAT_1_EDX] = 1862 PPRO_FEATURES | 1863 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 1864 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS, 1865 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST, 1866 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */ 1867 .features[FEAT_1_ECX] = 1868 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | 1869 CPUID_EXT_CX16, 1870 .features[FEAT_8000_0001_EDX] = 1871 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 1872 .features[FEAT_8000_0001_ECX] = 1873 CPUID_EXT3_LAHF_LM, 1874 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 1875 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 1876 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 1877 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 1878 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 1879 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 1880 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 1881 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 1882 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 1883 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 1884 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 1885 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 1886 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 1887 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 1888 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 1889 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 1890 .features[FEAT_VMX_SECONDARY_CTLS] = 1891 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES, 1892 .xlevel = 0x80000008, 1893 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz", 1894 }, 1895 { 1896 .name = "kvm64", 1897 .level = 0xd, 1898 .vendor = CPUID_VENDOR_INTEL, 1899 .family = 15, 1900 .model = 6, 1901 .stepping = 1, 1902 /* Missing: CPUID_HT */ 1903 .features[FEAT_1_EDX] = 1904 PPRO_FEATURES | CPUID_VME | 1905 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 1906 CPUID_PSE36, 1907 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */ 1908 .features[FEAT_1_ECX] = 1909 CPUID_EXT_SSE3 | CPUID_EXT_CX16, 1910 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */ 1911 .features[FEAT_8000_0001_EDX] = 1912 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 1913 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, 1914 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A, 1915 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, 1916 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */ 1917 .features[FEAT_8000_0001_ECX] = 1918 0, 1919 /* VMX features from Cedar Mill/Prescott */ 1920 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 1921 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 1922 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 1923 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 1924 VMX_PIN_BASED_NMI_EXITING, 1925 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 1926 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 1927 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 1928 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 1929 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 1930 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 1931 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 1932 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING, 1933 .xlevel = 0x80000008, 1934 .model_id = "Common KVM processor" 1935 }, 1936 { 1937 .name = "qemu32", 1938 .level = 4, 1939 .vendor = CPUID_VENDOR_INTEL, 1940 .family = 6, 1941 .model = 6, 1942 .stepping = 3, 1943 .features[FEAT_1_EDX] = 1944 PPRO_FEATURES, 1945 .features[FEAT_1_ECX] = 1946 CPUID_EXT_SSE3, 1947 .xlevel = 0x80000004, 1948 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 1949 }, 1950 { 1951 .name = "kvm32", 1952 .level = 5, 1953 .vendor = CPUID_VENDOR_INTEL, 1954 .family = 15, 1955 .model = 6, 1956 .stepping = 1, 1957 .features[FEAT_1_EDX] = 1958 PPRO_FEATURES | CPUID_VME | 1959 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36, 1960 .features[FEAT_1_ECX] = 1961 CPUID_EXT_SSE3, 1962 .features[FEAT_8000_0001_ECX] = 1963 0, 1964 /* VMX features from Yonah */ 1965 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 1966 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 1967 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 1968 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 1969 VMX_PIN_BASED_NMI_EXITING, 1970 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 1971 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 1972 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 1973 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 1974 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 1975 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 1976 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS, 1977 .xlevel = 0x80000008, 1978 .model_id = "Common 32-bit KVM processor" 1979 }, 1980 { 1981 .name = "coreduo", 1982 .level = 10, 1983 .vendor = CPUID_VENDOR_INTEL, 1984 .family = 6, 1985 .model = 14, 1986 .stepping = 8, 1987 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 1988 .features[FEAT_1_EDX] = 1989 PPRO_FEATURES | CPUID_VME | 1990 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI | 1991 CPUID_SS, 1992 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR, 1993 * CPUID_EXT_PDCM, CPUID_EXT_VMX */ 1994 .features[FEAT_1_ECX] = 1995 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR, 1996 .features[FEAT_8000_0001_EDX] = 1997 CPUID_EXT2_NX, 1998 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 1999 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2000 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2001 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2002 VMX_PIN_BASED_NMI_EXITING, 2003 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2004 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2005 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2006 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2007 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 2008 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 2009 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS, 2010 .xlevel = 0x80000008, 2011 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz", 2012 }, 2013 { 2014 .name = "486", 2015 .level = 1, 2016 .vendor = CPUID_VENDOR_INTEL, 2017 .family = 4, 2018 .model = 8, 2019 .stepping = 0, 2020 .features[FEAT_1_EDX] = 2021 I486_FEATURES, 2022 .xlevel = 0, 2023 .model_id = "", 2024 }, 2025 { 2026 .name = "pentium", 2027 .level = 1, 2028 .vendor = CPUID_VENDOR_INTEL, 2029 .family = 5, 2030 .model = 4, 2031 .stepping = 3, 2032 .features[FEAT_1_EDX] = 2033 PENTIUM_FEATURES, 2034 .xlevel = 0, 2035 .model_id = "", 2036 }, 2037 { 2038 .name = "pentium2", 2039 .level = 2, 2040 .vendor = CPUID_VENDOR_INTEL, 2041 .family = 6, 2042 .model = 5, 2043 .stepping = 2, 2044 .features[FEAT_1_EDX] = 2045 PENTIUM2_FEATURES, 2046 .xlevel = 0, 2047 .model_id = "", 2048 }, 2049 { 2050 .name = "pentium3", 2051 .level = 3, 2052 .vendor = CPUID_VENDOR_INTEL, 2053 .family = 6, 2054 .model = 7, 2055 .stepping = 3, 2056 .features[FEAT_1_EDX] = 2057 PENTIUM3_FEATURES, 2058 .xlevel = 0, 2059 .model_id = "", 2060 }, 2061 { 2062 .name = "athlon", 2063 .level = 2, 2064 .vendor = CPUID_VENDOR_AMD, 2065 .family = 6, 2066 .model = 2, 2067 .stepping = 3, 2068 .features[FEAT_1_EDX] = 2069 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR | 2070 CPUID_MCA, 2071 .features[FEAT_8000_0001_EDX] = 2072 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT, 2073 .xlevel = 0x80000008, 2074 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 2075 }, 2076 { 2077 .name = "n270", 2078 .level = 10, 2079 .vendor = CPUID_VENDOR_INTEL, 2080 .family = 6, 2081 .model = 28, 2082 .stepping = 2, 2083 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2084 .features[FEAT_1_EDX] = 2085 PPRO_FEATURES | 2086 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | 2087 CPUID_ACPI | CPUID_SS, 2088 /* Some CPUs got no CPUID_SEP */ 2089 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2, 2090 * CPUID_EXT_XTPR */ 2091 .features[FEAT_1_ECX] = 2092 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | 2093 CPUID_EXT_MOVBE, 2094 .features[FEAT_8000_0001_EDX] = 2095 CPUID_EXT2_NX, 2096 .features[FEAT_8000_0001_ECX] = 2097 CPUID_EXT3_LAHF_LM, 2098 .xlevel = 0x80000008, 2099 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz", 2100 }, 2101 { 2102 .name = "Conroe", 2103 .level = 10, 2104 .vendor = CPUID_VENDOR_INTEL, 2105 .family = 6, 2106 .model = 15, 2107 .stepping = 3, 2108 .features[FEAT_1_EDX] = 2109 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2110 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2111 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2112 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2113 CPUID_DE | CPUID_FP87, 2114 .features[FEAT_1_ECX] = 2115 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, 2116 .features[FEAT_8000_0001_EDX] = 2117 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 2118 .features[FEAT_8000_0001_ECX] = 2119 CPUID_EXT3_LAHF_LM, 2120 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2121 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2122 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2123 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2124 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2125 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2126 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2127 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2128 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2129 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2130 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2131 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2132 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2133 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2134 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2135 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2136 .features[FEAT_VMX_SECONDARY_CTLS] = 2137 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES, 2138 .xlevel = 0x80000008, 2139 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)", 2140 }, 2141 { 2142 .name = "Penryn", 2143 .level = 10, 2144 .vendor = CPUID_VENDOR_INTEL, 2145 .family = 6, 2146 .model = 23, 2147 .stepping = 3, 2148 .features[FEAT_1_EDX] = 2149 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2150 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2151 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2152 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2153 CPUID_DE | CPUID_FP87, 2154 .features[FEAT_1_ECX] = 2155 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2156 CPUID_EXT_SSE3, 2157 .features[FEAT_8000_0001_EDX] = 2158 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 2159 .features[FEAT_8000_0001_ECX] = 2160 CPUID_EXT3_LAHF_LM, 2161 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2162 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2163 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, 2164 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT | 2165 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL, 2166 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2167 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2168 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2169 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2170 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2171 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2172 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2173 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2174 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2175 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2176 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2177 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2178 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2179 .features[FEAT_VMX_SECONDARY_CTLS] = 2180 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2181 VMX_SECONDARY_EXEC_WBINVD_EXITING, 2182 .xlevel = 0x80000008, 2183 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)", 2184 }, 2185 { 2186 .name = "Nehalem", 2187 .level = 11, 2188 .vendor = CPUID_VENDOR_INTEL, 2189 .family = 6, 2190 .model = 26, 2191 .stepping = 3, 2192 .features[FEAT_1_EDX] = 2193 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2194 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2195 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2196 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2197 CPUID_DE | CPUID_FP87, 2198 .features[FEAT_1_ECX] = 2199 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 2200 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, 2201 .features[FEAT_8000_0001_EDX] = 2202 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2203 .features[FEAT_8000_0001_ECX] = 2204 CPUID_EXT3_LAHF_LM, 2205 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2206 MSR_VMX_BASIC_TRUE_CTLS, 2207 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2208 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2209 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2210 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2211 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2212 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2213 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2214 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2215 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2216 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2217 .features[FEAT_VMX_EXIT_CTLS] = 2218 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2219 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2220 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2221 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2222 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2223 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2224 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2225 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2226 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2227 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2228 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2229 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2230 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2231 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2232 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2233 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2234 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2235 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2236 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2237 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2238 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2239 .features[FEAT_VMX_SECONDARY_CTLS] = 2240 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2241 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2242 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2243 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2244 VMX_SECONDARY_EXEC_ENABLE_VPID, 2245 .xlevel = 0x80000008, 2246 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)", 2247 .versions = (X86CPUVersionDefinition[]) { 2248 { .version = 1 }, 2249 { 2250 .version = 2, 2251 .alias = "Nehalem-IBRS", 2252 .props = (PropValue[]) { 2253 { "spec-ctrl", "on" }, 2254 { "model-id", 2255 "Intel Core i7 9xx (Nehalem Core i7, IBRS update)" }, 2256 { /* end of list */ } 2257 } 2258 }, 2259 { /* end of list */ } 2260 } 2261 }, 2262 { 2263 .name = "Westmere", 2264 .level = 11, 2265 .vendor = CPUID_VENDOR_INTEL, 2266 .family = 6, 2267 .model = 44, 2268 .stepping = 1, 2269 .features[FEAT_1_EDX] = 2270 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2271 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2272 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2273 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2274 CPUID_DE | CPUID_FP87, 2275 .features[FEAT_1_ECX] = 2276 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | 2277 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2278 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 2279 .features[FEAT_8000_0001_EDX] = 2280 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2281 .features[FEAT_8000_0001_ECX] = 2282 CPUID_EXT3_LAHF_LM, 2283 .features[FEAT_6_EAX] = 2284 CPUID_6_EAX_ARAT, 2285 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2286 MSR_VMX_BASIC_TRUE_CTLS, 2287 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2288 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2289 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2290 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2291 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2292 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2293 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2294 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2295 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2296 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2297 .features[FEAT_VMX_EXIT_CTLS] = 2298 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2299 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2300 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2301 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2302 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2303 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2304 MSR_VMX_MISC_STORE_LMA, 2305 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2306 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2307 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2308 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2309 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2310 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2311 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2312 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2313 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2314 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2315 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2316 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2317 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2318 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2319 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2320 .features[FEAT_VMX_SECONDARY_CTLS] = 2321 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2322 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2323 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2324 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2325 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST, 2326 .xlevel = 0x80000008, 2327 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)", 2328 .versions = (X86CPUVersionDefinition[]) { 2329 { .version = 1 }, 2330 { 2331 .version = 2, 2332 .alias = "Westmere-IBRS", 2333 .props = (PropValue[]) { 2334 { "spec-ctrl", "on" }, 2335 { "model-id", 2336 "Westmere E56xx/L56xx/X56xx (IBRS update)" }, 2337 { /* end of list */ } 2338 } 2339 }, 2340 { /* end of list */ } 2341 } 2342 }, 2343 { 2344 .name = "SandyBridge", 2345 .level = 0xd, 2346 .vendor = CPUID_VENDOR_INTEL, 2347 .family = 6, 2348 .model = 42, 2349 .stepping = 1, 2350 .features[FEAT_1_EDX] = 2351 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2352 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2353 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2354 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2355 CPUID_DE | CPUID_FP87, 2356 .features[FEAT_1_ECX] = 2357 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2358 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | 2359 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 2360 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 2361 CPUID_EXT_SSE3, 2362 .features[FEAT_8000_0001_EDX] = 2363 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 2364 CPUID_EXT2_SYSCALL, 2365 .features[FEAT_8000_0001_ECX] = 2366 CPUID_EXT3_LAHF_LM, 2367 .features[FEAT_XSAVE] = 2368 CPUID_XSAVE_XSAVEOPT, 2369 .features[FEAT_6_EAX] = 2370 CPUID_6_EAX_ARAT, 2371 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2372 MSR_VMX_BASIC_TRUE_CTLS, 2373 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2374 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2375 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2376 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2377 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2378 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2379 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2380 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2381 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2382 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2383 .features[FEAT_VMX_EXIT_CTLS] = 2384 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2385 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2386 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2387 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2388 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2389 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2390 MSR_VMX_MISC_STORE_LMA, 2391 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2392 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2393 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2394 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2395 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2396 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2397 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2398 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2399 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2400 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2401 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2402 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2403 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2404 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2405 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2406 .features[FEAT_VMX_SECONDARY_CTLS] = 2407 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2408 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2409 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2410 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2411 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST, 2412 .xlevel = 0x80000008, 2413 .model_id = "Intel Xeon E312xx (Sandy Bridge)", 2414 .versions = (X86CPUVersionDefinition[]) { 2415 { .version = 1 }, 2416 { 2417 .version = 2, 2418 .alias = "SandyBridge-IBRS", 2419 .props = (PropValue[]) { 2420 { "spec-ctrl", "on" }, 2421 { "model-id", 2422 "Intel Xeon E312xx (Sandy Bridge, IBRS update)" }, 2423 { /* end of list */ } 2424 } 2425 }, 2426 { /* end of list */ } 2427 } 2428 }, 2429 { 2430 .name = "IvyBridge", 2431 .level = 0xd, 2432 .vendor = CPUID_VENDOR_INTEL, 2433 .family = 6, 2434 .model = 58, 2435 .stepping = 9, 2436 .features[FEAT_1_EDX] = 2437 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2438 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2439 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2440 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2441 CPUID_DE | CPUID_FP87, 2442 .features[FEAT_1_ECX] = 2443 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2444 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | 2445 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 2446 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 2447 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 2448 .features[FEAT_7_0_EBX] = 2449 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | 2450 CPUID_7_0_EBX_ERMS, 2451 .features[FEAT_8000_0001_EDX] = 2452 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 2453 CPUID_EXT2_SYSCALL, 2454 .features[FEAT_8000_0001_ECX] = 2455 CPUID_EXT3_LAHF_LM, 2456 .features[FEAT_XSAVE] = 2457 CPUID_XSAVE_XSAVEOPT, 2458 .features[FEAT_6_EAX] = 2459 CPUID_6_EAX_ARAT, 2460 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2461 MSR_VMX_BASIC_TRUE_CTLS, 2462 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2463 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2464 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2465 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2466 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2467 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2468 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2469 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2470 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2471 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2472 .features[FEAT_VMX_EXIT_CTLS] = 2473 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2474 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2475 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2476 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2477 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2478 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2479 MSR_VMX_MISC_STORE_LMA, 2480 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2481 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2482 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 2483 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2484 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2485 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2486 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2487 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2488 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2489 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2490 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2491 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2492 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2493 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2494 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2495 .features[FEAT_VMX_SECONDARY_CTLS] = 2496 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2497 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2498 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2499 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2500 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 2501 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 2502 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 2503 VMX_SECONDARY_EXEC_RDRAND_EXITING, 2504 .xlevel = 0x80000008, 2505 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)", 2506 .versions = (X86CPUVersionDefinition[]) { 2507 { .version = 1 }, 2508 { 2509 .version = 2, 2510 .alias = "IvyBridge-IBRS", 2511 .props = (PropValue[]) { 2512 { "spec-ctrl", "on" }, 2513 { "model-id", 2514 "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)" }, 2515 { /* end of list */ } 2516 } 2517 }, 2518 { /* end of list */ } 2519 } 2520 }, 2521 { 2522 .name = "Haswell", 2523 .level = 0xd, 2524 .vendor = CPUID_VENDOR_INTEL, 2525 .family = 6, 2526 .model = 60, 2527 .stepping = 4, 2528 .features[FEAT_1_EDX] = 2529 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2530 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2531 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2532 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2533 CPUID_DE | CPUID_FP87, 2534 .features[FEAT_1_ECX] = 2535 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2536 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 2537 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2538 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 2539 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 2540 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 2541 .features[FEAT_8000_0001_EDX] = 2542 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 2543 CPUID_EXT2_SYSCALL, 2544 .features[FEAT_8000_0001_ECX] = 2545 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM, 2546 .features[FEAT_7_0_EBX] = 2547 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 2548 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 2549 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 2550 CPUID_7_0_EBX_RTM, 2551 .features[FEAT_XSAVE] = 2552 CPUID_XSAVE_XSAVEOPT, 2553 .features[FEAT_6_EAX] = 2554 CPUID_6_EAX_ARAT, 2555 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2556 MSR_VMX_BASIC_TRUE_CTLS, 2557 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2558 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2559 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2560 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2561 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2562 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2563 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2564 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2565 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2566 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 2567 .features[FEAT_VMX_EXIT_CTLS] = 2568 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2569 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2570 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2571 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2572 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2573 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2574 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 2575 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2576 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2577 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 2578 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2579 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2580 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2581 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2582 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2583 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2584 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2585 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2586 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2587 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2588 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2589 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2590 .features[FEAT_VMX_SECONDARY_CTLS] = 2591 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2592 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2593 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2594 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2595 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 2596 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 2597 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 2598 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 2599 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS, 2600 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 2601 .xlevel = 0x80000008, 2602 .model_id = "Intel Core Processor (Haswell)", 2603 .versions = (X86CPUVersionDefinition[]) { 2604 { .version = 1 }, 2605 { 2606 .version = 2, 2607 .alias = "Haswell-noTSX", 2608 .props = (PropValue[]) { 2609 { "hle", "off" }, 2610 { "rtm", "off" }, 2611 { "stepping", "1" }, 2612 { "model-id", "Intel Core Processor (Haswell, no TSX)", }, 2613 { /* end of list */ } 2614 }, 2615 }, 2616 { 2617 .version = 3, 2618 .alias = "Haswell-IBRS", 2619 .props = (PropValue[]) { 2620 /* Restore TSX features removed by -v2 above */ 2621 { "hle", "on" }, 2622 { "rtm", "on" }, 2623 /* 2624 * Haswell and Haswell-IBRS had stepping=4 in 2625 * QEMU 4.0 and older 2626 */ 2627 { "stepping", "4" }, 2628 { "spec-ctrl", "on" }, 2629 { "model-id", 2630 "Intel Core Processor (Haswell, IBRS)" }, 2631 { /* end of list */ } 2632 } 2633 }, 2634 { 2635 .version = 4, 2636 .alias = "Haswell-noTSX-IBRS", 2637 .props = (PropValue[]) { 2638 { "hle", "off" }, 2639 { "rtm", "off" }, 2640 /* spec-ctrl was already enabled by -v3 above */ 2641 { "stepping", "1" }, 2642 { "model-id", 2643 "Intel Core Processor (Haswell, no TSX, IBRS)" }, 2644 { /* end of list */ } 2645 } 2646 }, 2647 { /* end of list */ } 2648 } 2649 }, 2650 { 2651 .name = "Broadwell", 2652 .level = 0xd, 2653 .vendor = CPUID_VENDOR_INTEL, 2654 .family = 6, 2655 .model = 61, 2656 .stepping = 2, 2657 .features[FEAT_1_EDX] = 2658 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2659 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2660 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2661 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2662 CPUID_DE | CPUID_FP87, 2663 .features[FEAT_1_ECX] = 2664 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2665 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 2666 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2667 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 2668 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 2669 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 2670 .features[FEAT_8000_0001_EDX] = 2671 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 2672 CPUID_EXT2_SYSCALL, 2673 .features[FEAT_8000_0001_ECX] = 2674 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 2675 .features[FEAT_7_0_EBX] = 2676 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 2677 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 2678 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 2679 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 2680 CPUID_7_0_EBX_SMAP, 2681 .features[FEAT_XSAVE] = 2682 CPUID_XSAVE_XSAVEOPT, 2683 .features[FEAT_6_EAX] = 2684 CPUID_6_EAX_ARAT, 2685 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2686 MSR_VMX_BASIC_TRUE_CTLS, 2687 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2688 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2689 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2690 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2691 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2692 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2693 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2694 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2695 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2696 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 2697 .features[FEAT_VMX_EXIT_CTLS] = 2698 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2699 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2700 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2701 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2702 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2703 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2704 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 2705 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2706 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2707 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 2708 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2709 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2710 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2711 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2712 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2713 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2714 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2715 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2716 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2717 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2718 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2719 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2720 .features[FEAT_VMX_SECONDARY_CTLS] = 2721 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2722 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2723 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2724 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2725 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 2726 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 2727 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 2728 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 2729 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 2730 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 2731 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 2732 .xlevel = 0x80000008, 2733 .model_id = "Intel Core Processor (Broadwell)", 2734 .versions = (X86CPUVersionDefinition[]) { 2735 { .version = 1 }, 2736 { 2737 .version = 2, 2738 .alias = "Broadwell-noTSX", 2739 .props = (PropValue[]) { 2740 { "hle", "off" }, 2741 { "rtm", "off" }, 2742 { "model-id", "Intel Core Processor (Broadwell, no TSX)", }, 2743 { /* end of list */ } 2744 }, 2745 }, 2746 { 2747 .version = 3, 2748 .alias = "Broadwell-IBRS", 2749 .props = (PropValue[]) { 2750 /* Restore TSX features removed by -v2 above */ 2751 { "hle", "on" }, 2752 { "rtm", "on" }, 2753 { "spec-ctrl", "on" }, 2754 { "model-id", 2755 "Intel Core Processor (Broadwell, IBRS)" }, 2756 { /* end of list */ } 2757 } 2758 }, 2759 { 2760 .version = 4, 2761 .alias = "Broadwell-noTSX-IBRS", 2762 .props = (PropValue[]) { 2763 { "hle", "off" }, 2764 { "rtm", "off" }, 2765 /* spec-ctrl was already enabled by -v3 above */ 2766 { "model-id", 2767 "Intel Core Processor (Broadwell, no TSX, IBRS)" }, 2768 { /* end of list */ } 2769 } 2770 }, 2771 { /* end of list */ } 2772 } 2773 }, 2774 { 2775 .name = "Skylake-Client", 2776 .level = 0xd, 2777 .vendor = CPUID_VENDOR_INTEL, 2778 .family = 6, 2779 .model = 94, 2780 .stepping = 3, 2781 .features[FEAT_1_EDX] = 2782 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2783 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2784 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2785 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2786 CPUID_DE | CPUID_FP87, 2787 .features[FEAT_1_ECX] = 2788 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2789 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 2790 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2791 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 2792 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 2793 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 2794 .features[FEAT_8000_0001_EDX] = 2795 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 2796 CPUID_EXT2_SYSCALL, 2797 .features[FEAT_8000_0001_ECX] = 2798 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 2799 .features[FEAT_7_0_EBX] = 2800 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 2801 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 2802 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 2803 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 2804 CPUID_7_0_EBX_SMAP, 2805 /* Missing: XSAVES (not supported by some Linux versions, 2806 * including v4.1 to v4.12). 2807 * KVM doesn't yet expose any XSAVES state save component, 2808 * and the only one defined in Skylake (processor tracing) 2809 * probably will block migration anyway. 2810 */ 2811 .features[FEAT_XSAVE] = 2812 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 2813 CPUID_XSAVE_XGETBV1, 2814 .features[FEAT_6_EAX] = 2815 CPUID_6_EAX_ARAT, 2816 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 2817 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2818 MSR_VMX_BASIC_TRUE_CTLS, 2819 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2820 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2821 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2822 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2823 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2824 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2825 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2826 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2827 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2828 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 2829 .features[FEAT_VMX_EXIT_CTLS] = 2830 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2831 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2832 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2833 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2834 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2835 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2836 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 2837 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2838 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2839 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2840 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2841 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2842 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2843 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2844 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2845 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2846 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2847 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2848 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2849 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2850 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2851 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2852 .features[FEAT_VMX_SECONDARY_CTLS] = 2853 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2854 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2855 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2856 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 2857 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 2858 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 2859 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 2860 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 2861 .xlevel = 0x80000008, 2862 .model_id = "Intel Core Processor (Skylake)", 2863 .versions = (X86CPUVersionDefinition[]) { 2864 { .version = 1 }, 2865 { 2866 .version = 2, 2867 .alias = "Skylake-Client-IBRS", 2868 .props = (PropValue[]) { 2869 { "spec-ctrl", "on" }, 2870 { "model-id", 2871 "Intel Core Processor (Skylake, IBRS)" }, 2872 { /* end of list */ } 2873 } 2874 }, 2875 { 2876 .version = 3, 2877 .alias = "Skylake-Client-noTSX-IBRS", 2878 .props = (PropValue[]) { 2879 { "hle", "off" }, 2880 { "rtm", "off" }, 2881 { "model-id", 2882 "Intel Core Processor (Skylake, IBRS, no TSX)" }, 2883 { /* end of list */ } 2884 } 2885 }, 2886 { /* end of list */ } 2887 } 2888 }, 2889 { 2890 .name = "Skylake-Server", 2891 .level = 0xd, 2892 .vendor = CPUID_VENDOR_INTEL, 2893 .family = 6, 2894 .model = 85, 2895 .stepping = 4, 2896 .features[FEAT_1_EDX] = 2897 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2898 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2899 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2900 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2901 CPUID_DE | CPUID_FP87, 2902 .features[FEAT_1_ECX] = 2903 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2904 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 2905 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2906 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 2907 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 2908 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 2909 .features[FEAT_8000_0001_EDX] = 2910 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 2911 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 2912 .features[FEAT_8000_0001_ECX] = 2913 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 2914 .features[FEAT_7_0_EBX] = 2915 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 2916 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 2917 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 2918 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 2919 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 2920 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 2921 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 2922 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 2923 .features[FEAT_7_0_ECX] = 2924 CPUID_7_0_ECX_PKU, 2925 /* Missing: XSAVES (not supported by some Linux versions, 2926 * including v4.1 to v4.12). 2927 * KVM doesn't yet expose any XSAVES state save component, 2928 * and the only one defined in Skylake (processor tracing) 2929 * probably will block migration anyway. 2930 */ 2931 .features[FEAT_XSAVE] = 2932 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 2933 CPUID_XSAVE_XGETBV1, 2934 .features[FEAT_6_EAX] = 2935 CPUID_6_EAX_ARAT, 2936 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 2937 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2938 MSR_VMX_BASIC_TRUE_CTLS, 2939 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2940 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2941 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2942 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2943 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2944 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2945 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2946 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2947 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2948 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 2949 .features[FEAT_VMX_EXIT_CTLS] = 2950 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2951 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2952 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2953 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2954 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2955 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2956 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 2957 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2958 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2959 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 2960 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2961 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2962 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2963 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2964 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2965 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2966 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2967 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2968 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2969 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2970 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2971 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2972 .features[FEAT_VMX_SECONDARY_CTLS] = 2973 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2974 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2975 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2976 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2977 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 2978 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 2979 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 2980 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 2981 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 2982 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 2983 .xlevel = 0x80000008, 2984 .model_id = "Intel Xeon Processor (Skylake)", 2985 .versions = (X86CPUVersionDefinition[]) { 2986 { .version = 1 }, 2987 { 2988 .version = 2, 2989 .alias = "Skylake-Server-IBRS", 2990 .props = (PropValue[]) { 2991 /* clflushopt was not added to Skylake-Server-IBRS */ 2992 /* TODO: add -v3 including clflushopt */ 2993 { "clflushopt", "off" }, 2994 { "spec-ctrl", "on" }, 2995 { "model-id", 2996 "Intel Xeon Processor (Skylake, IBRS)" }, 2997 { /* end of list */ } 2998 } 2999 }, 3000 { 3001 .version = 3, 3002 .alias = "Skylake-Server-noTSX-IBRS", 3003 .props = (PropValue[]) { 3004 { "hle", "off" }, 3005 { "rtm", "off" }, 3006 { "model-id", 3007 "Intel Xeon Processor (Skylake, IBRS, no TSX)" }, 3008 { /* end of list */ } 3009 } 3010 }, 3011 { 3012 .version = 4, 3013 .props = (PropValue[]) { 3014 { "vmx-eptp-switching", "on" }, 3015 { /* end of list */ } 3016 } 3017 }, 3018 { /* end of list */ } 3019 } 3020 }, 3021 { 3022 .name = "Cascadelake-Server", 3023 .level = 0xd, 3024 .vendor = CPUID_VENDOR_INTEL, 3025 .family = 6, 3026 .model = 85, 3027 .stepping = 6, 3028 .features[FEAT_1_EDX] = 3029 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3030 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3031 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3032 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3033 CPUID_DE | CPUID_FP87, 3034 .features[FEAT_1_ECX] = 3035 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3036 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3037 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3038 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3039 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3040 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3041 .features[FEAT_8000_0001_EDX] = 3042 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3043 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3044 .features[FEAT_8000_0001_ECX] = 3045 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3046 .features[FEAT_7_0_EBX] = 3047 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3048 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3049 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3050 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3051 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3052 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3053 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3054 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3055 .features[FEAT_7_0_ECX] = 3056 CPUID_7_0_ECX_PKU | 3057 CPUID_7_0_ECX_AVX512VNNI, 3058 .features[FEAT_7_0_EDX] = 3059 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 3060 /* Missing: XSAVES (not supported by some Linux versions, 3061 * including v4.1 to v4.12). 3062 * KVM doesn't yet expose any XSAVES state save component, 3063 * and the only one defined in Skylake (processor tracing) 3064 * probably will block migration anyway. 3065 */ 3066 .features[FEAT_XSAVE] = 3067 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3068 CPUID_XSAVE_XGETBV1, 3069 .features[FEAT_6_EAX] = 3070 CPUID_6_EAX_ARAT, 3071 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3072 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3073 MSR_VMX_BASIC_TRUE_CTLS, 3074 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3075 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3076 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3077 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3078 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3079 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3080 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3081 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3082 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3083 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3084 .features[FEAT_VMX_EXIT_CTLS] = 3085 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3086 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3087 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3088 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3089 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3090 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3091 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3092 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3093 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3094 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3095 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3096 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3097 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3098 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3099 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3100 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3101 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3102 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3103 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3104 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3105 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3106 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3107 .features[FEAT_VMX_SECONDARY_CTLS] = 3108 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3109 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3110 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3111 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3112 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3113 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3114 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3115 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3116 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3117 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3118 .xlevel = 0x80000008, 3119 .model_id = "Intel Xeon Processor (Cascadelake)", 3120 .versions = (X86CPUVersionDefinition[]) { 3121 { .version = 1 }, 3122 { .version = 2, 3123 .note = "ARCH_CAPABILITIES", 3124 .props = (PropValue[]) { 3125 { "arch-capabilities", "on" }, 3126 { "rdctl-no", "on" }, 3127 { "ibrs-all", "on" }, 3128 { "skip-l1dfl-vmentry", "on" }, 3129 { "mds-no", "on" }, 3130 { /* end of list */ } 3131 }, 3132 }, 3133 { .version = 3, 3134 .alias = "Cascadelake-Server-noTSX", 3135 .note = "ARCH_CAPABILITIES, no TSX", 3136 .props = (PropValue[]) { 3137 { "hle", "off" }, 3138 { "rtm", "off" }, 3139 { /* end of list */ } 3140 }, 3141 }, 3142 { .version = 4, 3143 .note = "ARCH_CAPABILITIES, no TSX", 3144 .props = (PropValue[]) { 3145 { "vmx-eptp-switching", "on" }, 3146 { /* end of list */ } 3147 }, 3148 }, 3149 { /* end of list */ } 3150 } 3151 }, 3152 { 3153 .name = "Cooperlake", 3154 .level = 0xd, 3155 .vendor = CPUID_VENDOR_INTEL, 3156 .family = 6, 3157 .model = 85, 3158 .stepping = 10, 3159 .features[FEAT_1_EDX] = 3160 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3161 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3162 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3163 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3164 CPUID_DE | CPUID_FP87, 3165 .features[FEAT_1_ECX] = 3166 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3167 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3168 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3169 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3170 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3171 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3172 .features[FEAT_8000_0001_EDX] = 3173 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3174 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3175 .features[FEAT_8000_0001_ECX] = 3176 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3177 .features[FEAT_7_0_EBX] = 3178 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3179 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3180 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3181 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3182 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3183 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3184 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3185 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3186 .features[FEAT_7_0_ECX] = 3187 CPUID_7_0_ECX_PKU | 3188 CPUID_7_0_ECX_AVX512VNNI, 3189 .features[FEAT_7_0_EDX] = 3190 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_STIBP | 3191 CPUID_7_0_EDX_SPEC_CTRL_SSBD | CPUID_7_0_EDX_ARCH_CAPABILITIES, 3192 .features[FEAT_ARCH_CAPABILITIES] = 3193 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 3194 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 3195 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO, 3196 .features[FEAT_7_1_EAX] = 3197 CPUID_7_1_EAX_AVX512_BF16, 3198 /* 3199 * Missing: XSAVES (not supported by some Linux versions, 3200 * including v4.1 to v4.12). 3201 * KVM doesn't yet expose any XSAVES state save component, 3202 * and the only one defined in Skylake (processor tracing) 3203 * probably will block migration anyway. 3204 */ 3205 .features[FEAT_XSAVE] = 3206 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3207 CPUID_XSAVE_XGETBV1, 3208 .features[FEAT_6_EAX] = 3209 CPUID_6_EAX_ARAT, 3210 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3211 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3212 MSR_VMX_BASIC_TRUE_CTLS, 3213 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3214 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3215 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3216 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3217 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3218 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3219 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3220 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3221 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3222 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3223 .features[FEAT_VMX_EXIT_CTLS] = 3224 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3225 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3226 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3227 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3228 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3229 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3230 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3231 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3232 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3233 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3234 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3235 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3236 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3237 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3238 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3239 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3240 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3241 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3242 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3243 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3244 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3245 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3246 .features[FEAT_VMX_SECONDARY_CTLS] = 3247 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3248 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3249 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3250 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3251 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3252 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3253 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3254 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3255 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3256 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3257 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3258 .xlevel = 0x80000008, 3259 .model_id = "Intel Xeon Processor (Cooperlake)", 3260 }, 3261 { 3262 .name = "Icelake-Client", 3263 .level = 0xd, 3264 .vendor = CPUID_VENDOR_INTEL, 3265 .family = 6, 3266 .model = 126, 3267 .stepping = 0, 3268 .features[FEAT_1_EDX] = 3269 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3270 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3271 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3272 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3273 CPUID_DE | CPUID_FP87, 3274 .features[FEAT_1_ECX] = 3275 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3276 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3277 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3278 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3279 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3280 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3281 .features[FEAT_8000_0001_EDX] = 3282 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3283 CPUID_EXT2_SYSCALL, 3284 .features[FEAT_8000_0001_ECX] = 3285 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3286 .features[FEAT_8000_0008_EBX] = 3287 CPUID_8000_0008_EBX_WBNOINVD, 3288 .features[FEAT_7_0_EBX] = 3289 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3290 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3291 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3292 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3293 CPUID_7_0_EBX_SMAP, 3294 .features[FEAT_7_0_ECX] = 3295 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 3296 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 3297 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 3298 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 3299 CPUID_7_0_ECX_AVX512_VPOPCNTDQ, 3300 .features[FEAT_7_0_EDX] = 3301 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 3302 /* Missing: XSAVES (not supported by some Linux versions, 3303 * including v4.1 to v4.12). 3304 * KVM doesn't yet expose any XSAVES state save component, 3305 * and the only one defined in Skylake (processor tracing) 3306 * probably will block migration anyway. 3307 */ 3308 .features[FEAT_XSAVE] = 3309 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3310 CPUID_XSAVE_XGETBV1, 3311 .features[FEAT_6_EAX] = 3312 CPUID_6_EAX_ARAT, 3313 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3314 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3315 MSR_VMX_BASIC_TRUE_CTLS, 3316 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3317 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3318 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3319 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3320 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3321 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3322 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3323 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3324 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3325 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3326 .features[FEAT_VMX_EXIT_CTLS] = 3327 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3328 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3329 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3330 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3331 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3332 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3333 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3334 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3335 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3336 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 3337 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3338 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3339 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3340 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3341 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3342 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3343 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3344 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3345 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3346 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3347 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3348 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3349 .features[FEAT_VMX_SECONDARY_CTLS] = 3350 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3351 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3352 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3353 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3354 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3355 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3356 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3357 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3358 .xlevel = 0x80000008, 3359 .model_id = "Intel Core Processor (Icelake)", 3360 .versions = (X86CPUVersionDefinition[]) { 3361 { .version = 1 }, 3362 { 3363 .version = 2, 3364 .note = "no TSX", 3365 .alias = "Icelake-Client-noTSX", 3366 .props = (PropValue[]) { 3367 { "hle", "off" }, 3368 { "rtm", "off" }, 3369 { /* end of list */ } 3370 }, 3371 }, 3372 { /* end of list */ } 3373 } 3374 }, 3375 { 3376 .name = "Icelake-Server", 3377 .level = 0xd, 3378 .vendor = CPUID_VENDOR_INTEL, 3379 .family = 6, 3380 .model = 134, 3381 .stepping = 0, 3382 .features[FEAT_1_EDX] = 3383 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3384 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3385 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3386 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3387 CPUID_DE | CPUID_FP87, 3388 .features[FEAT_1_ECX] = 3389 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3390 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3391 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3392 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3393 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3394 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3395 .features[FEAT_8000_0001_EDX] = 3396 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3397 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3398 .features[FEAT_8000_0001_ECX] = 3399 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3400 .features[FEAT_8000_0008_EBX] = 3401 CPUID_8000_0008_EBX_WBNOINVD, 3402 .features[FEAT_7_0_EBX] = 3403 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3404 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3405 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3406 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3407 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3408 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3409 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3410 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3411 .features[FEAT_7_0_ECX] = 3412 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 3413 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 3414 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 3415 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 3416 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57, 3417 .features[FEAT_7_0_EDX] = 3418 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 3419 /* Missing: XSAVES (not supported by some Linux versions, 3420 * including v4.1 to v4.12). 3421 * KVM doesn't yet expose any XSAVES state save component, 3422 * and the only one defined in Skylake (processor tracing) 3423 * probably will block migration anyway. 3424 */ 3425 .features[FEAT_XSAVE] = 3426 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3427 CPUID_XSAVE_XGETBV1, 3428 .features[FEAT_6_EAX] = 3429 CPUID_6_EAX_ARAT, 3430 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3431 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3432 MSR_VMX_BASIC_TRUE_CTLS, 3433 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3434 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3435 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3436 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3437 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3438 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3439 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3440 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3441 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3442 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3443 .features[FEAT_VMX_EXIT_CTLS] = 3444 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3445 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3446 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3447 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3448 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3449 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3450 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3451 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3452 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3453 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3454 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3455 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3456 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3457 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3458 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3459 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3460 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3461 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3462 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3463 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3464 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3465 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3466 .features[FEAT_VMX_SECONDARY_CTLS] = 3467 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3468 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3469 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3470 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3471 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3472 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3473 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3474 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3475 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS, 3476 .xlevel = 0x80000008, 3477 .model_id = "Intel Xeon Processor (Icelake)", 3478 .versions = (X86CPUVersionDefinition[]) { 3479 { .version = 1 }, 3480 { 3481 .version = 2, 3482 .note = "no TSX", 3483 .alias = "Icelake-Server-noTSX", 3484 .props = (PropValue[]) { 3485 { "hle", "off" }, 3486 { "rtm", "off" }, 3487 { /* end of list */ } 3488 }, 3489 }, 3490 { 3491 .version = 3, 3492 .props = (PropValue[]) { 3493 { "arch-capabilities", "on" }, 3494 { "rdctl-no", "on" }, 3495 { "ibrs-all", "on" }, 3496 { "skip-l1dfl-vmentry", "on" }, 3497 { "mds-no", "on" }, 3498 { "pschange-mc-no", "on" }, 3499 { "taa-no", "on" }, 3500 { /* end of list */ } 3501 }, 3502 }, 3503 { 3504 .version = 4, 3505 .props = (PropValue[]) { 3506 { "sha-ni", "on" }, 3507 { "avx512ifma", "on" }, 3508 { "rdpid", "on" }, 3509 { "fsrm", "on" }, 3510 { "vmx-rdseed-exit", "on" }, 3511 { "vmx-pml", "on" }, 3512 { "vmx-eptp-switching", "on" }, 3513 { "model", "106" }, 3514 { /* end of list */ } 3515 }, 3516 }, 3517 { /* end of list */ } 3518 } 3519 }, 3520 { 3521 .name = "Denverton", 3522 .level = 21, 3523 .vendor = CPUID_VENDOR_INTEL, 3524 .family = 6, 3525 .model = 95, 3526 .stepping = 1, 3527 .features[FEAT_1_EDX] = 3528 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 3529 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 3530 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 3531 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 3532 CPUID_SSE | CPUID_SSE2, 3533 .features[FEAT_1_ECX] = 3534 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR | 3535 CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_SSE41 | 3536 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 3537 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | 3538 CPUID_EXT_AES | CPUID_EXT_XSAVE | CPUID_EXT_RDRAND, 3539 .features[FEAT_8000_0001_EDX] = 3540 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 3541 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 3542 .features[FEAT_8000_0001_ECX] = 3543 CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3544 .features[FEAT_7_0_EBX] = 3545 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_ERMS | 3546 CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_SMAP | 3547 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_SHA_NI, 3548 .features[FEAT_7_0_EDX] = 3549 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES | 3550 CPUID_7_0_EDX_SPEC_CTRL_SSBD, 3551 /* 3552 * Missing: XSAVES (not supported by some Linux versions, 3553 * including v4.1 to v4.12). 3554 * KVM doesn't yet expose any XSAVES state save component, 3555 * and the only one defined in Skylake (processor tracing) 3556 * probably will block migration anyway. 3557 */ 3558 .features[FEAT_XSAVE] = 3559 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | CPUID_XSAVE_XGETBV1, 3560 .features[FEAT_6_EAX] = 3561 CPUID_6_EAX_ARAT, 3562 .features[FEAT_ARCH_CAPABILITIES] = 3563 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY, 3564 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3565 MSR_VMX_BASIC_TRUE_CTLS, 3566 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3567 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3568 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3569 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3570 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3571 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3572 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3573 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3574 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3575 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3576 .features[FEAT_VMX_EXIT_CTLS] = 3577 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3578 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3579 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3580 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3581 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3582 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3583 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3584 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3585 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3586 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3587 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3588 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3589 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3590 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3591 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3592 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3593 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3594 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3595 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3596 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3597 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3598 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3599 .features[FEAT_VMX_SECONDARY_CTLS] = 3600 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3601 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3602 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3603 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3604 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3605 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3606 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3607 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3608 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3609 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3610 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3611 .xlevel = 0x80000008, 3612 .model_id = "Intel Atom Processor (Denverton)", 3613 .versions = (X86CPUVersionDefinition[]) { 3614 { .version = 1 }, 3615 { 3616 .version = 2, 3617 .note = "no MPX, no MONITOR", 3618 .props = (PropValue[]) { 3619 { "monitor", "off" }, 3620 { "mpx", "off" }, 3621 { /* end of list */ }, 3622 }, 3623 }, 3624 { /* end of list */ }, 3625 }, 3626 }, 3627 { 3628 .name = "Snowridge", 3629 .level = 27, 3630 .vendor = CPUID_VENDOR_INTEL, 3631 .family = 6, 3632 .model = 134, 3633 .stepping = 1, 3634 .features[FEAT_1_EDX] = 3635 /* missing: CPUID_PN CPUID_IA64 */ 3636 /* missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 3637 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | 3638 CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_MCE | 3639 CPUID_CX8 | CPUID_APIC | CPUID_SEP | 3640 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 3641 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | 3642 CPUID_MMX | 3643 CPUID_FXSR | CPUID_SSE | CPUID_SSE2, 3644 .features[FEAT_1_ECX] = 3645 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR | 3646 CPUID_EXT_SSSE3 | 3647 CPUID_EXT_CX16 | 3648 CPUID_EXT_SSE41 | 3649 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 3650 CPUID_EXT_POPCNT | 3651 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | CPUID_EXT_XSAVE | 3652 CPUID_EXT_RDRAND, 3653 .features[FEAT_8000_0001_EDX] = 3654 CPUID_EXT2_SYSCALL | 3655 CPUID_EXT2_NX | 3656 CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3657 CPUID_EXT2_LM, 3658 .features[FEAT_8000_0001_ECX] = 3659 CPUID_EXT3_LAHF_LM | 3660 CPUID_EXT3_3DNOWPREFETCH, 3661 .features[FEAT_7_0_EBX] = 3662 CPUID_7_0_EBX_FSGSBASE | 3663 CPUID_7_0_EBX_SMEP | 3664 CPUID_7_0_EBX_ERMS | 3665 CPUID_7_0_EBX_MPX | /* missing bits 13, 15 */ 3666 CPUID_7_0_EBX_RDSEED | 3667 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 3668 CPUID_7_0_EBX_CLWB | 3669 CPUID_7_0_EBX_SHA_NI, 3670 .features[FEAT_7_0_ECX] = 3671 CPUID_7_0_ECX_UMIP | 3672 /* missing bit 5 */ 3673 CPUID_7_0_ECX_GFNI | 3674 CPUID_7_0_ECX_MOVDIRI | CPUID_7_0_ECX_CLDEMOTE | 3675 CPUID_7_0_ECX_MOVDIR64B, 3676 .features[FEAT_7_0_EDX] = 3677 CPUID_7_0_EDX_SPEC_CTRL | 3678 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD | 3679 CPUID_7_0_EDX_CORE_CAPABILITY, 3680 .features[FEAT_CORE_CAPABILITY] = 3681 MSR_CORE_CAP_SPLIT_LOCK_DETECT, 3682 /* 3683 * Missing: XSAVES (not supported by some Linux versions, 3684 * including v4.1 to v4.12). 3685 * KVM doesn't yet expose any XSAVES state save component, 3686 * and the only one defined in Skylake (processor tracing) 3687 * probably will block migration anyway. 3688 */ 3689 .features[FEAT_XSAVE] = 3690 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3691 CPUID_XSAVE_XGETBV1, 3692 .features[FEAT_6_EAX] = 3693 CPUID_6_EAX_ARAT, 3694 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3695 MSR_VMX_BASIC_TRUE_CTLS, 3696 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3697 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3698 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3699 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3700 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3701 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3702 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3703 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3704 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3705 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3706 .features[FEAT_VMX_EXIT_CTLS] = 3707 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3708 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3709 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3710 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3711 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3712 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3713 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3714 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3715 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3716 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3717 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3718 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3719 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3720 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3721 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3722 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3723 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3724 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3725 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3726 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3727 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3728 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3729 .features[FEAT_VMX_SECONDARY_CTLS] = 3730 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3731 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3732 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3733 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3734 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3735 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3736 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3737 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3738 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3739 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3740 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3741 .xlevel = 0x80000008, 3742 .model_id = "Intel Atom Processor (SnowRidge)", 3743 .versions = (X86CPUVersionDefinition[]) { 3744 { .version = 1 }, 3745 { 3746 .version = 2, 3747 .props = (PropValue[]) { 3748 { "mpx", "off" }, 3749 { "model-id", "Intel Atom Processor (Snowridge, no MPX)" }, 3750 { /* end of list */ }, 3751 }, 3752 }, 3753 { /* end of list */ }, 3754 }, 3755 }, 3756 { 3757 .name = "KnightsMill", 3758 .level = 0xd, 3759 .vendor = CPUID_VENDOR_INTEL, 3760 .family = 6, 3761 .model = 133, 3762 .stepping = 0, 3763 .features[FEAT_1_EDX] = 3764 CPUID_VME | CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | 3765 CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | 3766 CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | 3767 CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | 3768 CPUID_PSE | CPUID_DE | CPUID_FP87, 3769 .features[FEAT_1_ECX] = 3770 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3771 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3772 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3773 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3774 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3775 CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3776 .features[FEAT_8000_0001_EDX] = 3777 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3778 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3779 .features[FEAT_8000_0001_ECX] = 3780 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3781 .features[FEAT_7_0_EBX] = 3782 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 3783 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 3784 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_AVX512F | 3785 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_AVX512PF | 3786 CPUID_7_0_EBX_AVX512ER, 3787 .features[FEAT_7_0_ECX] = 3788 CPUID_7_0_ECX_AVX512_VPOPCNTDQ, 3789 .features[FEAT_7_0_EDX] = 3790 CPUID_7_0_EDX_AVX512_4VNNIW | CPUID_7_0_EDX_AVX512_4FMAPS, 3791 .features[FEAT_XSAVE] = 3792 CPUID_XSAVE_XSAVEOPT, 3793 .features[FEAT_6_EAX] = 3794 CPUID_6_EAX_ARAT, 3795 .xlevel = 0x80000008, 3796 .model_id = "Intel Xeon Phi Processor (Knights Mill)", 3797 }, 3798 { 3799 .name = "Opteron_G1", 3800 .level = 5, 3801 .vendor = CPUID_VENDOR_AMD, 3802 .family = 15, 3803 .model = 6, 3804 .stepping = 1, 3805 .features[FEAT_1_EDX] = 3806 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3807 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3808 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3809 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3810 CPUID_DE | CPUID_FP87, 3811 .features[FEAT_1_ECX] = 3812 CPUID_EXT_SSE3, 3813 .features[FEAT_8000_0001_EDX] = 3814 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3815 .xlevel = 0x80000008, 3816 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)", 3817 }, 3818 { 3819 .name = "Opteron_G2", 3820 .level = 5, 3821 .vendor = CPUID_VENDOR_AMD, 3822 .family = 15, 3823 .model = 6, 3824 .stepping = 1, 3825 .features[FEAT_1_EDX] = 3826 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3827 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3828 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3829 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3830 CPUID_DE | CPUID_FP87, 3831 .features[FEAT_1_ECX] = 3832 CPUID_EXT_CX16 | CPUID_EXT_SSE3, 3833 .features[FEAT_8000_0001_EDX] = 3834 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3835 .features[FEAT_8000_0001_ECX] = 3836 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, 3837 .xlevel = 0x80000008, 3838 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)", 3839 }, 3840 { 3841 .name = "Opteron_G3", 3842 .level = 5, 3843 .vendor = CPUID_VENDOR_AMD, 3844 .family = 16, 3845 .model = 2, 3846 .stepping = 3, 3847 .features[FEAT_1_EDX] = 3848 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3849 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3850 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3851 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3852 CPUID_DE | CPUID_FP87, 3853 .features[FEAT_1_ECX] = 3854 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR | 3855 CPUID_EXT_SSE3, 3856 .features[FEAT_8000_0001_EDX] = 3857 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL | 3858 CPUID_EXT2_RDTSCP, 3859 .features[FEAT_8000_0001_ECX] = 3860 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | 3861 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, 3862 .xlevel = 0x80000008, 3863 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)", 3864 }, 3865 { 3866 .name = "Opteron_G4", 3867 .level = 0xd, 3868 .vendor = CPUID_VENDOR_AMD, 3869 .family = 21, 3870 .model = 1, 3871 .stepping = 2, 3872 .features[FEAT_1_EDX] = 3873 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3874 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3875 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3876 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3877 CPUID_DE | CPUID_FP87, 3878 .features[FEAT_1_ECX] = 3879 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3880 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 3881 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 3882 CPUID_EXT_SSE3, 3883 .features[FEAT_8000_0001_EDX] = 3884 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX | 3885 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP, 3886 .features[FEAT_8000_0001_ECX] = 3887 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP | 3888 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | 3889 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | 3890 CPUID_EXT3_LAHF_LM, 3891 .features[FEAT_SVM] = 3892 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 3893 /* no xsaveopt! */ 3894 .xlevel = 0x8000001A, 3895 .model_id = "AMD Opteron 62xx class CPU", 3896 }, 3897 { 3898 .name = "Opteron_G5", 3899 .level = 0xd, 3900 .vendor = CPUID_VENDOR_AMD, 3901 .family = 21, 3902 .model = 2, 3903 .stepping = 0, 3904 .features[FEAT_1_EDX] = 3905 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3906 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3907 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3908 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3909 CPUID_DE | CPUID_FP87, 3910 .features[FEAT_1_ECX] = 3911 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE | 3912 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | 3913 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA | 3914 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 3915 .features[FEAT_8000_0001_EDX] = 3916 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX | 3917 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP, 3918 .features[FEAT_8000_0001_ECX] = 3919 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP | 3920 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | 3921 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | 3922 CPUID_EXT3_LAHF_LM, 3923 .features[FEAT_SVM] = 3924 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 3925 /* no xsaveopt! */ 3926 .xlevel = 0x8000001A, 3927 .model_id = "AMD Opteron 63xx class CPU", 3928 }, 3929 { 3930 .name = "EPYC", 3931 .level = 0xd, 3932 .vendor = CPUID_VENDOR_AMD, 3933 .family = 23, 3934 .model = 1, 3935 .stepping = 2, 3936 .features[FEAT_1_EDX] = 3937 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 3938 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 3939 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 3940 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 3941 CPUID_VME | CPUID_FP87, 3942 .features[FEAT_1_ECX] = 3943 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 3944 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 3945 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 3946 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 3947 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 3948 .features[FEAT_8000_0001_EDX] = 3949 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 3950 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 3951 CPUID_EXT2_SYSCALL, 3952 .features[FEAT_8000_0001_ECX] = 3953 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 3954 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 3955 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 3956 CPUID_EXT3_TOPOEXT, 3957 .features[FEAT_7_0_EBX] = 3958 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 3959 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 3960 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 3961 CPUID_7_0_EBX_SHA_NI, 3962 .features[FEAT_XSAVE] = 3963 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3964 CPUID_XSAVE_XGETBV1, 3965 .features[FEAT_6_EAX] = 3966 CPUID_6_EAX_ARAT, 3967 .features[FEAT_SVM] = 3968 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 3969 .xlevel = 0x8000001E, 3970 .model_id = "AMD EPYC Processor", 3971 .cache_info = &epyc_cache_info, 3972 .versions = (X86CPUVersionDefinition[]) { 3973 { .version = 1 }, 3974 { 3975 .version = 2, 3976 .alias = "EPYC-IBPB", 3977 .props = (PropValue[]) { 3978 { "ibpb", "on" }, 3979 { "model-id", 3980 "AMD EPYC Processor (with IBPB)" }, 3981 { /* end of list */ } 3982 } 3983 }, 3984 { 3985 .version = 3, 3986 .props = (PropValue[]) { 3987 { "ibpb", "on" }, 3988 { "perfctr-core", "on" }, 3989 { "clzero", "on" }, 3990 { "xsaveerptr", "on" }, 3991 { "xsaves", "on" }, 3992 { "model-id", 3993 "AMD EPYC Processor" }, 3994 { /* end of list */ } 3995 } 3996 }, 3997 { /* end of list */ } 3998 } 3999 }, 4000 { 4001 .name = "Dhyana", 4002 .level = 0xd, 4003 .vendor = CPUID_VENDOR_HYGON, 4004 .family = 24, 4005 .model = 0, 4006 .stepping = 1, 4007 .features[FEAT_1_EDX] = 4008 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 4009 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 4010 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 4011 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 4012 CPUID_VME | CPUID_FP87, 4013 .features[FEAT_1_ECX] = 4014 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 4015 CPUID_EXT_XSAVE | CPUID_EXT_POPCNT | 4016 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 4017 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 4018 CPUID_EXT_MONITOR | CPUID_EXT_SSE3, 4019 .features[FEAT_8000_0001_EDX] = 4020 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 4021 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 4022 CPUID_EXT2_SYSCALL, 4023 .features[FEAT_8000_0001_ECX] = 4024 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 4025 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 4026 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 4027 CPUID_EXT3_TOPOEXT, 4028 .features[FEAT_8000_0008_EBX] = 4029 CPUID_8000_0008_EBX_IBPB, 4030 .features[FEAT_7_0_EBX] = 4031 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4032 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 4033 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT, 4034 /* 4035 * Missing: XSAVES (not supported by some Linux versions, 4036 * including v4.1 to v4.12). 4037 * KVM doesn't yet expose any XSAVES state save component. 4038 */ 4039 .features[FEAT_XSAVE] = 4040 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4041 CPUID_XSAVE_XGETBV1, 4042 .features[FEAT_6_EAX] = 4043 CPUID_6_EAX_ARAT, 4044 .features[FEAT_SVM] = 4045 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 4046 .xlevel = 0x8000001E, 4047 .model_id = "Hygon Dhyana Processor", 4048 .cache_info = &epyc_cache_info, 4049 }, 4050 { 4051 .name = "EPYC-Rome", 4052 .level = 0xd, 4053 .vendor = CPUID_VENDOR_AMD, 4054 .family = 23, 4055 .model = 49, 4056 .stepping = 0, 4057 .features[FEAT_1_EDX] = 4058 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 4059 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 4060 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 4061 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 4062 CPUID_VME | CPUID_FP87, 4063 .features[FEAT_1_ECX] = 4064 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 4065 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 4066 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 4067 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 4068 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 4069 .features[FEAT_8000_0001_EDX] = 4070 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 4071 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 4072 CPUID_EXT2_SYSCALL, 4073 .features[FEAT_8000_0001_ECX] = 4074 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 4075 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 4076 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 4077 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 4078 .features[FEAT_8000_0008_EBX] = 4079 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 4080 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 4081 CPUID_8000_0008_EBX_STIBP, 4082 .features[FEAT_7_0_EBX] = 4083 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4084 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 4085 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 4086 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB, 4087 .features[FEAT_7_0_ECX] = 4088 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID, 4089 .features[FEAT_XSAVE] = 4090 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4091 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 4092 .features[FEAT_6_EAX] = 4093 CPUID_6_EAX_ARAT, 4094 .features[FEAT_SVM] = 4095 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 4096 .xlevel = 0x8000001E, 4097 .model_id = "AMD EPYC-Rome Processor", 4098 .cache_info = &epyc_rome_cache_info, 4099 }, 4100 }; 4101 4102 /* KVM-specific features that are automatically added/removed 4103 * from all CPU models when KVM is enabled. 4104 */ 4105 static PropValue kvm_default_props[] = { 4106 { "kvmclock", "on" }, 4107 { "kvm-nopiodelay", "on" }, 4108 { "kvm-asyncpf", "on" }, 4109 { "kvm-steal-time", "on" }, 4110 { "kvm-pv-eoi", "on" }, 4111 { "kvmclock-stable-bit", "on" }, 4112 { "x2apic", "on" }, 4113 { "acpi", "off" }, 4114 { "monitor", "off" }, 4115 { "svm", "off" }, 4116 { NULL, NULL }, 4117 }; 4118 4119 /* TCG-specific defaults that override all CPU models when using TCG 4120 */ 4121 static PropValue tcg_default_props[] = { 4122 { "vme", "off" }, 4123 { NULL, NULL }, 4124 }; 4125 4126 4127 /* 4128 * We resolve CPU model aliases using -v1 when using "-machine 4129 * none", but this is just for compatibility while libvirt isn't 4130 * adapted to resolve CPU model versions before creating VMs. 4131 * See "Runnability guarantee of CPU models" at 4132 * docs/system/deprecated.rst. 4133 */ 4134 X86CPUVersion default_cpu_version = 1; 4135 4136 void x86_cpu_set_default_version(X86CPUVersion version) 4137 { 4138 /* Translating CPU_VERSION_AUTO to CPU_VERSION_AUTO doesn't make sense */ 4139 assert(version != CPU_VERSION_AUTO); 4140 default_cpu_version = version; 4141 } 4142 4143 static X86CPUVersion x86_cpu_model_last_version(const X86CPUModel *model) 4144 { 4145 int v = 0; 4146 const X86CPUVersionDefinition *vdef = 4147 x86_cpu_def_get_versions(model->cpudef); 4148 while (vdef->version) { 4149 v = vdef->version; 4150 vdef++; 4151 } 4152 return v; 4153 } 4154 4155 /* Return the actual version being used for a specific CPU model */ 4156 static X86CPUVersion x86_cpu_model_resolve_version(const X86CPUModel *model) 4157 { 4158 X86CPUVersion v = model->version; 4159 if (v == CPU_VERSION_AUTO) { 4160 v = default_cpu_version; 4161 } 4162 if (v == CPU_VERSION_LATEST) { 4163 return x86_cpu_model_last_version(model); 4164 } 4165 return v; 4166 } 4167 4168 void x86_cpu_change_kvm_default(const char *prop, const char *value) 4169 { 4170 PropValue *pv; 4171 for (pv = kvm_default_props; pv->prop; pv++) { 4172 if (!strcmp(pv->prop, prop)) { 4173 pv->value = value; 4174 break; 4175 } 4176 } 4177 4178 /* It is valid to call this function only for properties that 4179 * are already present in the kvm_default_props table. 4180 */ 4181 assert(pv->prop); 4182 } 4183 4184 static bool lmce_supported(void) 4185 { 4186 uint64_t mce_cap = 0; 4187 4188 #ifdef CONFIG_KVM 4189 if (kvm_ioctl(kvm_state, KVM_X86_GET_MCE_CAP_SUPPORTED, &mce_cap) < 0) { 4190 return false; 4191 } 4192 #endif 4193 4194 return !!(mce_cap & MCG_LMCE_P); 4195 } 4196 4197 #define CPUID_MODEL_ID_SZ 48 4198 4199 /** 4200 * cpu_x86_fill_model_id: 4201 * Get CPUID model ID string from host CPU. 4202 * 4203 * @str should have at least CPUID_MODEL_ID_SZ bytes 4204 * 4205 * The function does NOT add a null terminator to the string 4206 * automatically. 4207 */ 4208 static int cpu_x86_fill_model_id(char *str) 4209 { 4210 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0; 4211 int i; 4212 4213 for (i = 0; i < 3; i++) { 4214 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx); 4215 memcpy(str + i * 16 + 0, &eax, 4); 4216 memcpy(str + i * 16 + 4, &ebx, 4); 4217 memcpy(str + i * 16 + 8, &ecx, 4); 4218 memcpy(str + i * 16 + 12, &edx, 4); 4219 } 4220 return 0; 4221 } 4222 4223 static Property max_x86_cpu_properties[] = { 4224 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true), 4225 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false), 4226 DEFINE_PROP_END_OF_LIST() 4227 }; 4228 4229 static void max_x86_cpu_class_init(ObjectClass *oc, void *data) 4230 { 4231 DeviceClass *dc = DEVICE_CLASS(oc); 4232 X86CPUClass *xcc = X86_CPU_CLASS(oc); 4233 4234 xcc->ordering = 9; 4235 4236 xcc->model_description = 4237 "Enables all features supported by the accelerator in the current host"; 4238 4239 device_class_set_props(dc, max_x86_cpu_properties); 4240 } 4241 4242 static void max_x86_cpu_initfn(Object *obj) 4243 { 4244 X86CPU *cpu = X86_CPU(obj); 4245 CPUX86State *env = &cpu->env; 4246 KVMState *s = kvm_state; 4247 4248 /* We can't fill the features array here because we don't know yet if 4249 * "migratable" is true or false. 4250 */ 4251 cpu->max_features = true; 4252 4253 if (accel_uses_host_cpuid()) { 4254 char vendor[CPUID_VENDOR_SZ + 1] = { 0 }; 4255 char model_id[CPUID_MODEL_ID_SZ + 1] = { 0 }; 4256 int family, model, stepping; 4257 4258 host_vendor_fms(vendor, &family, &model, &stepping); 4259 cpu_x86_fill_model_id(model_id); 4260 4261 object_property_set_str(OBJECT(cpu), "vendor", vendor, &error_abort); 4262 object_property_set_int(OBJECT(cpu), "family", family, &error_abort); 4263 object_property_set_int(OBJECT(cpu), "model", model, &error_abort); 4264 object_property_set_int(OBJECT(cpu), "stepping", stepping, 4265 &error_abort); 4266 object_property_set_str(OBJECT(cpu), "model-id", model_id, 4267 &error_abort); 4268 4269 if (kvm_enabled()) { 4270 env->cpuid_min_level = 4271 kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX); 4272 env->cpuid_min_xlevel = 4273 kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX); 4274 env->cpuid_min_xlevel2 = 4275 kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX); 4276 } else { 4277 env->cpuid_min_level = 4278 hvf_get_supported_cpuid(0x0, 0, R_EAX); 4279 env->cpuid_min_xlevel = 4280 hvf_get_supported_cpuid(0x80000000, 0, R_EAX); 4281 env->cpuid_min_xlevel2 = 4282 hvf_get_supported_cpuid(0xC0000000, 0, R_EAX); 4283 } 4284 4285 if (lmce_supported()) { 4286 object_property_set_bool(OBJECT(cpu), "lmce", true, &error_abort); 4287 } 4288 } else { 4289 object_property_set_str(OBJECT(cpu), "vendor", CPUID_VENDOR_AMD, 4290 &error_abort); 4291 object_property_set_int(OBJECT(cpu), "family", 6, &error_abort); 4292 object_property_set_int(OBJECT(cpu), "model", 6, &error_abort); 4293 object_property_set_int(OBJECT(cpu), "stepping", 3, &error_abort); 4294 object_property_set_str(OBJECT(cpu), "model-id", 4295 "QEMU TCG CPU version " QEMU_HW_VERSION, 4296 &error_abort); 4297 } 4298 4299 object_property_set_bool(OBJECT(cpu), "pmu", true, &error_abort); 4300 } 4301 4302 static const TypeInfo max_x86_cpu_type_info = { 4303 .name = X86_CPU_TYPE_NAME("max"), 4304 .parent = TYPE_X86_CPU, 4305 .instance_init = max_x86_cpu_initfn, 4306 .class_init = max_x86_cpu_class_init, 4307 }; 4308 4309 #if defined(CONFIG_KVM) || defined(CONFIG_HVF) 4310 static void host_x86_cpu_class_init(ObjectClass *oc, void *data) 4311 { 4312 X86CPUClass *xcc = X86_CPU_CLASS(oc); 4313 4314 xcc->host_cpuid_required = true; 4315 xcc->ordering = 8; 4316 4317 #if defined(CONFIG_KVM) 4318 xcc->model_description = 4319 "KVM processor with all supported host features "; 4320 #elif defined(CONFIG_HVF) 4321 xcc->model_description = 4322 "HVF processor with all supported host features "; 4323 #endif 4324 } 4325 4326 static const TypeInfo host_x86_cpu_type_info = { 4327 .name = X86_CPU_TYPE_NAME("host"), 4328 .parent = X86_CPU_TYPE_NAME("max"), 4329 .class_init = host_x86_cpu_class_init, 4330 }; 4331 4332 #endif 4333 4334 static char *feature_word_description(FeatureWordInfo *f, uint32_t bit) 4335 { 4336 assert(f->type == CPUID_FEATURE_WORD || f->type == MSR_FEATURE_WORD); 4337 4338 switch (f->type) { 4339 case CPUID_FEATURE_WORD: 4340 { 4341 const char *reg = get_register_name_32(f->cpuid.reg); 4342 assert(reg); 4343 return g_strdup_printf("CPUID.%02XH:%s", 4344 f->cpuid.eax, reg); 4345 } 4346 case MSR_FEATURE_WORD: 4347 return g_strdup_printf("MSR(%02XH)", 4348 f->msr.index); 4349 } 4350 4351 return NULL; 4352 } 4353 4354 static bool x86_cpu_have_filtered_features(X86CPU *cpu) 4355 { 4356 FeatureWord w; 4357 4358 for (w = 0; w < FEATURE_WORDS; w++) { 4359 if (cpu->filtered_features[w]) { 4360 return true; 4361 } 4362 } 4363 4364 return false; 4365 } 4366 4367 static void mark_unavailable_features(X86CPU *cpu, FeatureWord w, uint64_t mask, 4368 const char *verbose_prefix) 4369 { 4370 CPUX86State *env = &cpu->env; 4371 FeatureWordInfo *f = &feature_word_info[w]; 4372 int i; 4373 4374 if (!cpu->force_features) { 4375 env->features[w] &= ~mask; 4376 } 4377 cpu->filtered_features[w] |= mask; 4378 4379 if (!verbose_prefix) { 4380 return; 4381 } 4382 4383 for (i = 0; i < 64; ++i) { 4384 if ((1ULL << i) & mask) { 4385 g_autofree char *feat_word_str = feature_word_description(f, i); 4386 warn_report("%s: %s%s%s [bit %d]", 4387 verbose_prefix, 4388 feat_word_str, 4389 f->feat_names[i] ? "." : "", 4390 f->feat_names[i] ? f->feat_names[i] : "", i); 4391 } 4392 } 4393 } 4394 4395 static void x86_cpuid_version_get_family(Object *obj, Visitor *v, 4396 const char *name, void *opaque, 4397 Error **errp) 4398 { 4399 X86CPU *cpu = X86_CPU(obj); 4400 CPUX86State *env = &cpu->env; 4401 int64_t value; 4402 4403 value = (env->cpuid_version >> 8) & 0xf; 4404 if (value == 0xf) { 4405 value += (env->cpuid_version >> 20) & 0xff; 4406 } 4407 visit_type_int(v, name, &value, errp); 4408 } 4409 4410 static void x86_cpuid_version_set_family(Object *obj, Visitor *v, 4411 const char *name, void *opaque, 4412 Error **errp) 4413 { 4414 X86CPU *cpu = X86_CPU(obj); 4415 CPUX86State *env = &cpu->env; 4416 const int64_t min = 0; 4417 const int64_t max = 0xff + 0xf; 4418 int64_t value; 4419 4420 if (!visit_type_int(v, name, &value, errp)) { 4421 return; 4422 } 4423 if (value < min || value > max) { 4424 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", 4425 name ? name : "null", value, min, max); 4426 return; 4427 } 4428 4429 env->cpuid_version &= ~0xff00f00; 4430 if (value > 0x0f) { 4431 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20); 4432 } else { 4433 env->cpuid_version |= value << 8; 4434 } 4435 } 4436 4437 static void x86_cpuid_version_get_model(Object *obj, Visitor *v, 4438 const char *name, void *opaque, 4439 Error **errp) 4440 { 4441 X86CPU *cpu = X86_CPU(obj); 4442 CPUX86State *env = &cpu->env; 4443 int64_t value; 4444 4445 value = (env->cpuid_version >> 4) & 0xf; 4446 value |= ((env->cpuid_version >> 16) & 0xf) << 4; 4447 visit_type_int(v, name, &value, errp); 4448 } 4449 4450 static void x86_cpuid_version_set_model(Object *obj, Visitor *v, 4451 const char *name, void *opaque, 4452 Error **errp) 4453 { 4454 X86CPU *cpu = X86_CPU(obj); 4455 CPUX86State *env = &cpu->env; 4456 const int64_t min = 0; 4457 const int64_t max = 0xff; 4458 int64_t value; 4459 4460 if (!visit_type_int(v, name, &value, errp)) { 4461 return; 4462 } 4463 if (value < min || value > max) { 4464 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", 4465 name ? name : "null", value, min, max); 4466 return; 4467 } 4468 4469 env->cpuid_version &= ~0xf00f0; 4470 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16); 4471 } 4472 4473 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v, 4474 const char *name, void *opaque, 4475 Error **errp) 4476 { 4477 X86CPU *cpu = X86_CPU(obj); 4478 CPUX86State *env = &cpu->env; 4479 int64_t value; 4480 4481 value = env->cpuid_version & 0xf; 4482 visit_type_int(v, name, &value, errp); 4483 } 4484 4485 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v, 4486 const char *name, void *opaque, 4487 Error **errp) 4488 { 4489 X86CPU *cpu = X86_CPU(obj); 4490 CPUX86State *env = &cpu->env; 4491 const int64_t min = 0; 4492 const int64_t max = 0xf; 4493 int64_t value; 4494 4495 if (!visit_type_int(v, name, &value, errp)) { 4496 return; 4497 } 4498 if (value < min || value > max) { 4499 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", 4500 name ? name : "null", value, min, max); 4501 return; 4502 } 4503 4504 env->cpuid_version &= ~0xf; 4505 env->cpuid_version |= value & 0xf; 4506 } 4507 4508 static char *x86_cpuid_get_vendor(Object *obj, Error **errp) 4509 { 4510 X86CPU *cpu = X86_CPU(obj); 4511 CPUX86State *env = &cpu->env; 4512 char *value; 4513 4514 value = g_malloc(CPUID_VENDOR_SZ + 1); 4515 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2, 4516 env->cpuid_vendor3); 4517 return value; 4518 } 4519 4520 static void x86_cpuid_set_vendor(Object *obj, const char *value, 4521 Error **errp) 4522 { 4523 X86CPU *cpu = X86_CPU(obj); 4524 CPUX86State *env = &cpu->env; 4525 int i; 4526 4527 if (strlen(value) != CPUID_VENDOR_SZ) { 4528 error_setg(errp, QERR_PROPERTY_VALUE_BAD, "", "vendor", value); 4529 return; 4530 } 4531 4532 env->cpuid_vendor1 = 0; 4533 env->cpuid_vendor2 = 0; 4534 env->cpuid_vendor3 = 0; 4535 for (i = 0; i < 4; i++) { 4536 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i); 4537 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i); 4538 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i); 4539 } 4540 } 4541 4542 static char *x86_cpuid_get_model_id(Object *obj, Error **errp) 4543 { 4544 X86CPU *cpu = X86_CPU(obj); 4545 CPUX86State *env = &cpu->env; 4546 char *value; 4547 int i; 4548 4549 value = g_malloc(48 + 1); 4550 for (i = 0; i < 48; i++) { 4551 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3)); 4552 } 4553 value[48] = '\0'; 4554 return value; 4555 } 4556 4557 static void x86_cpuid_set_model_id(Object *obj, const char *model_id, 4558 Error **errp) 4559 { 4560 X86CPU *cpu = X86_CPU(obj); 4561 CPUX86State *env = &cpu->env; 4562 int c, len, i; 4563 4564 if (model_id == NULL) { 4565 model_id = ""; 4566 } 4567 len = strlen(model_id); 4568 memset(env->cpuid_model, 0, 48); 4569 for (i = 0; i < 48; i++) { 4570 if (i >= len) { 4571 c = '\0'; 4572 } else { 4573 c = (uint8_t)model_id[i]; 4574 } 4575 env->cpuid_model[i >> 2] |= c << (8 * (i & 3)); 4576 } 4577 } 4578 4579 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name, 4580 void *opaque, Error **errp) 4581 { 4582 X86CPU *cpu = X86_CPU(obj); 4583 int64_t value; 4584 4585 value = cpu->env.tsc_khz * 1000; 4586 visit_type_int(v, name, &value, errp); 4587 } 4588 4589 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name, 4590 void *opaque, Error **errp) 4591 { 4592 X86CPU *cpu = X86_CPU(obj); 4593 const int64_t min = 0; 4594 const int64_t max = INT64_MAX; 4595 int64_t value; 4596 4597 if (!visit_type_int(v, name, &value, errp)) { 4598 return; 4599 } 4600 if (value < min || value > max) { 4601 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", 4602 name ? name : "null", value, min, max); 4603 return; 4604 } 4605 4606 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000; 4607 } 4608 4609 /* Generic getter for "feature-words" and "filtered-features" properties */ 4610 static void x86_cpu_get_feature_words(Object *obj, Visitor *v, 4611 const char *name, void *opaque, 4612 Error **errp) 4613 { 4614 uint64_t *array = (uint64_t *)opaque; 4615 FeatureWord w; 4616 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { }; 4617 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { }; 4618 X86CPUFeatureWordInfoList *list = NULL; 4619 4620 for (w = 0; w < FEATURE_WORDS; w++) { 4621 FeatureWordInfo *wi = &feature_word_info[w]; 4622 /* 4623 * We didn't have MSR features when "feature-words" was 4624 * introduced. Therefore skipped other type entries. 4625 */ 4626 if (wi->type != CPUID_FEATURE_WORD) { 4627 continue; 4628 } 4629 X86CPUFeatureWordInfo *qwi = &word_infos[w]; 4630 qwi->cpuid_input_eax = wi->cpuid.eax; 4631 qwi->has_cpuid_input_ecx = wi->cpuid.needs_ecx; 4632 qwi->cpuid_input_ecx = wi->cpuid.ecx; 4633 qwi->cpuid_register = x86_reg_info_32[wi->cpuid.reg].qapi_enum; 4634 qwi->features = array[w]; 4635 4636 /* List will be in reverse order, but order shouldn't matter */ 4637 list_entries[w].next = list; 4638 list_entries[w].value = &word_infos[w]; 4639 list = &list_entries[w]; 4640 } 4641 4642 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp); 4643 } 4644 4645 /* Convert all '_' in a feature string option name to '-', to make feature 4646 * name conform to QOM property naming rule, which uses '-' instead of '_'. 4647 */ 4648 static inline void feat2prop(char *s) 4649 { 4650 while ((s = strchr(s, '_'))) { 4651 *s = '-'; 4652 } 4653 } 4654 4655 /* Return the feature property name for a feature flag bit */ 4656 static const char *x86_cpu_feature_name(FeatureWord w, int bitnr) 4657 { 4658 const char *name; 4659 /* XSAVE components are automatically enabled by other features, 4660 * so return the original feature name instead 4661 */ 4662 if (w == FEAT_XSAVE_COMP_LO || w == FEAT_XSAVE_COMP_HI) { 4663 int comp = (w == FEAT_XSAVE_COMP_HI) ? bitnr + 32 : bitnr; 4664 4665 if (comp < ARRAY_SIZE(x86_ext_save_areas) && 4666 x86_ext_save_areas[comp].bits) { 4667 w = x86_ext_save_areas[comp].feature; 4668 bitnr = ctz32(x86_ext_save_areas[comp].bits); 4669 } 4670 } 4671 4672 assert(bitnr < 64); 4673 assert(w < FEATURE_WORDS); 4674 name = feature_word_info[w].feat_names[bitnr]; 4675 assert(bitnr < 32 || !(name && feature_word_info[w].type == CPUID_FEATURE_WORD)); 4676 return name; 4677 } 4678 4679 /* Compatibily hack to maintain legacy +-feat semantic, 4680 * where +-feat overwrites any feature set by 4681 * feat=on|feat even if the later is parsed after +-feat 4682 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled) 4683 */ 4684 static GList *plus_features, *minus_features; 4685 4686 static gint compare_string(gconstpointer a, gconstpointer b) 4687 { 4688 return g_strcmp0(a, b); 4689 } 4690 4691 /* Parse "+feature,-feature,feature=foo" CPU feature string 4692 */ 4693 static void x86_cpu_parse_featurestr(const char *typename, char *features, 4694 Error **errp) 4695 { 4696 char *featurestr; /* Single 'key=value" string being parsed */ 4697 static bool cpu_globals_initialized; 4698 bool ambiguous = false; 4699 4700 if (cpu_globals_initialized) { 4701 return; 4702 } 4703 cpu_globals_initialized = true; 4704 4705 if (!features) { 4706 return; 4707 } 4708 4709 for (featurestr = strtok(features, ","); 4710 featurestr; 4711 featurestr = strtok(NULL, ",")) { 4712 const char *name; 4713 const char *val = NULL; 4714 char *eq = NULL; 4715 char num[32]; 4716 GlobalProperty *prop; 4717 4718 /* Compatibility syntax: */ 4719 if (featurestr[0] == '+') { 4720 plus_features = g_list_append(plus_features, 4721 g_strdup(featurestr + 1)); 4722 continue; 4723 } else if (featurestr[0] == '-') { 4724 minus_features = g_list_append(minus_features, 4725 g_strdup(featurestr + 1)); 4726 continue; 4727 } 4728 4729 eq = strchr(featurestr, '='); 4730 if (eq) { 4731 *eq++ = 0; 4732 val = eq; 4733 } else { 4734 val = "on"; 4735 } 4736 4737 feat2prop(featurestr); 4738 name = featurestr; 4739 4740 if (g_list_find_custom(plus_features, name, compare_string)) { 4741 warn_report("Ambiguous CPU model string. " 4742 "Don't mix both \"+%s\" and \"%s=%s\"", 4743 name, name, val); 4744 ambiguous = true; 4745 } 4746 if (g_list_find_custom(minus_features, name, compare_string)) { 4747 warn_report("Ambiguous CPU model string. " 4748 "Don't mix both \"-%s\" and \"%s=%s\"", 4749 name, name, val); 4750 ambiguous = true; 4751 } 4752 4753 /* Special case: */ 4754 if (!strcmp(name, "tsc-freq")) { 4755 int ret; 4756 uint64_t tsc_freq; 4757 4758 ret = qemu_strtosz_metric(val, NULL, &tsc_freq); 4759 if (ret < 0 || tsc_freq > INT64_MAX) { 4760 error_setg(errp, "bad numerical value %s", val); 4761 return; 4762 } 4763 snprintf(num, sizeof(num), "%" PRId64, tsc_freq); 4764 val = num; 4765 name = "tsc-frequency"; 4766 } 4767 4768 prop = g_new0(typeof(*prop), 1); 4769 prop->driver = typename; 4770 prop->property = g_strdup(name); 4771 prop->value = g_strdup(val); 4772 qdev_prop_register_global(prop); 4773 } 4774 4775 if (ambiguous) { 4776 warn_report("Compatibility of ambiguous CPU model " 4777 "strings won't be kept on future QEMU versions"); 4778 } 4779 } 4780 4781 static void x86_cpu_expand_features(X86CPU *cpu, Error **errp); 4782 static void x86_cpu_filter_features(X86CPU *cpu, bool verbose); 4783 4784 /* Build a list with the name of all features on a feature word array */ 4785 static void x86_cpu_list_feature_names(FeatureWordArray features, 4786 strList **feat_names) 4787 { 4788 FeatureWord w; 4789 strList **next = feat_names; 4790 4791 for (w = 0; w < FEATURE_WORDS; w++) { 4792 uint64_t filtered = features[w]; 4793 int i; 4794 for (i = 0; i < 64; i++) { 4795 if (filtered & (1ULL << i)) { 4796 strList *new = g_new0(strList, 1); 4797 new->value = g_strdup(x86_cpu_feature_name(w, i)); 4798 *next = new; 4799 next = &new->next; 4800 } 4801 } 4802 } 4803 } 4804 4805 static void x86_cpu_get_unavailable_features(Object *obj, Visitor *v, 4806 const char *name, void *opaque, 4807 Error **errp) 4808 { 4809 X86CPU *xc = X86_CPU(obj); 4810 strList *result = NULL; 4811 4812 x86_cpu_list_feature_names(xc->filtered_features, &result); 4813 visit_type_strList(v, "unavailable-features", &result, errp); 4814 } 4815 4816 /* Check for missing features that may prevent the CPU class from 4817 * running using the current machine and accelerator. 4818 */ 4819 static void x86_cpu_class_check_missing_features(X86CPUClass *xcc, 4820 strList **missing_feats) 4821 { 4822 X86CPU *xc; 4823 Error *err = NULL; 4824 strList **next = missing_feats; 4825 4826 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) { 4827 strList *new = g_new0(strList, 1); 4828 new->value = g_strdup("kvm"); 4829 *missing_feats = new; 4830 return; 4831 } 4832 4833 xc = X86_CPU(object_new_with_class(OBJECT_CLASS(xcc))); 4834 4835 x86_cpu_expand_features(xc, &err); 4836 if (err) { 4837 /* Errors at x86_cpu_expand_features should never happen, 4838 * but in case it does, just report the model as not 4839 * runnable at all using the "type" property. 4840 */ 4841 strList *new = g_new0(strList, 1); 4842 new->value = g_strdup("type"); 4843 *next = new; 4844 next = &new->next; 4845 error_free(err); 4846 } 4847 4848 x86_cpu_filter_features(xc, false); 4849 4850 x86_cpu_list_feature_names(xc->filtered_features, next); 4851 4852 object_unref(OBJECT(xc)); 4853 } 4854 4855 /* Print all cpuid feature names in featureset 4856 */ 4857 static void listflags(GList *features) 4858 { 4859 size_t len = 0; 4860 GList *tmp; 4861 4862 for (tmp = features; tmp; tmp = tmp->next) { 4863 const char *name = tmp->data; 4864 if ((len + strlen(name) + 1) >= 75) { 4865 qemu_printf("\n"); 4866 len = 0; 4867 } 4868 qemu_printf("%s%s", len == 0 ? " " : " ", name); 4869 len += strlen(name) + 1; 4870 } 4871 qemu_printf("\n"); 4872 } 4873 4874 /* Sort alphabetically by type name, respecting X86CPUClass::ordering. */ 4875 static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b) 4876 { 4877 ObjectClass *class_a = (ObjectClass *)a; 4878 ObjectClass *class_b = (ObjectClass *)b; 4879 X86CPUClass *cc_a = X86_CPU_CLASS(class_a); 4880 X86CPUClass *cc_b = X86_CPU_CLASS(class_b); 4881 int ret; 4882 4883 if (cc_a->ordering != cc_b->ordering) { 4884 ret = cc_a->ordering - cc_b->ordering; 4885 } else { 4886 g_autofree char *name_a = x86_cpu_class_get_model_name(cc_a); 4887 g_autofree char *name_b = x86_cpu_class_get_model_name(cc_b); 4888 ret = strcmp(name_a, name_b); 4889 } 4890 return ret; 4891 } 4892 4893 static GSList *get_sorted_cpu_model_list(void) 4894 { 4895 GSList *list = object_class_get_list(TYPE_X86_CPU, false); 4896 list = g_slist_sort(list, x86_cpu_list_compare); 4897 return list; 4898 } 4899 4900 static char *x86_cpu_class_get_model_id(X86CPUClass *xc) 4901 { 4902 Object *obj = object_new_with_class(OBJECT_CLASS(xc)); 4903 char *r = object_property_get_str(obj, "model-id", &error_abort); 4904 object_unref(obj); 4905 return r; 4906 } 4907 4908 static char *x86_cpu_class_get_alias_of(X86CPUClass *cc) 4909 { 4910 X86CPUVersion version; 4911 4912 if (!cc->model || !cc->model->is_alias) { 4913 return NULL; 4914 } 4915 version = x86_cpu_model_resolve_version(cc->model); 4916 if (version <= 0) { 4917 return NULL; 4918 } 4919 return x86_cpu_versioned_model_name(cc->model->cpudef, version); 4920 } 4921 4922 static void x86_cpu_list_entry(gpointer data, gpointer user_data) 4923 { 4924 ObjectClass *oc = data; 4925 X86CPUClass *cc = X86_CPU_CLASS(oc); 4926 g_autofree char *name = x86_cpu_class_get_model_name(cc); 4927 g_autofree char *desc = g_strdup(cc->model_description); 4928 g_autofree char *alias_of = x86_cpu_class_get_alias_of(cc); 4929 g_autofree char *model_id = x86_cpu_class_get_model_id(cc); 4930 4931 if (!desc && alias_of) { 4932 if (cc->model && cc->model->version == CPU_VERSION_AUTO) { 4933 desc = g_strdup("(alias configured by machine type)"); 4934 } else { 4935 desc = g_strdup_printf("(alias of %s)", alias_of); 4936 } 4937 } 4938 if (!desc && cc->model && cc->model->note) { 4939 desc = g_strdup_printf("%s [%s]", model_id, cc->model->note); 4940 } 4941 if (!desc) { 4942 desc = g_strdup_printf("%s", model_id); 4943 } 4944 4945 qemu_printf("x86 %-20s %-58s\n", name, desc); 4946 } 4947 4948 /* list available CPU models and flags */ 4949 void x86_cpu_list(void) 4950 { 4951 int i, j; 4952 GSList *list; 4953 GList *names = NULL; 4954 4955 qemu_printf("Available CPUs:\n"); 4956 list = get_sorted_cpu_model_list(); 4957 g_slist_foreach(list, x86_cpu_list_entry, NULL); 4958 g_slist_free(list); 4959 4960 names = NULL; 4961 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) { 4962 FeatureWordInfo *fw = &feature_word_info[i]; 4963 for (j = 0; j < 64; j++) { 4964 if (fw->feat_names[j]) { 4965 names = g_list_append(names, (gpointer)fw->feat_names[j]); 4966 } 4967 } 4968 } 4969 4970 names = g_list_sort(names, (GCompareFunc)strcmp); 4971 4972 qemu_printf("\nRecognized CPUID flags:\n"); 4973 listflags(names); 4974 qemu_printf("\n"); 4975 g_list_free(names); 4976 } 4977 4978 static void x86_cpu_definition_entry(gpointer data, gpointer user_data) 4979 { 4980 ObjectClass *oc = data; 4981 X86CPUClass *cc = X86_CPU_CLASS(oc); 4982 CpuDefinitionInfoList **cpu_list = user_data; 4983 CpuDefinitionInfoList *entry; 4984 CpuDefinitionInfo *info; 4985 4986 info = g_malloc0(sizeof(*info)); 4987 info->name = x86_cpu_class_get_model_name(cc); 4988 x86_cpu_class_check_missing_features(cc, &info->unavailable_features); 4989 info->has_unavailable_features = true; 4990 info->q_typename = g_strdup(object_class_get_name(oc)); 4991 info->migration_safe = cc->migration_safe; 4992 info->has_migration_safe = true; 4993 info->q_static = cc->static_model; 4994 if (cc->model && cc->model->cpudef->deprecation_note) { 4995 info->deprecated = true; 4996 } else { 4997 info->deprecated = false; 4998 } 4999 /* 5000 * Old machine types won't report aliases, so that alias translation 5001 * doesn't break compatibility with previous QEMU versions. 5002 */ 5003 if (default_cpu_version != CPU_VERSION_LEGACY) { 5004 info->alias_of = x86_cpu_class_get_alias_of(cc); 5005 info->has_alias_of = !!info->alias_of; 5006 } 5007 5008 entry = g_malloc0(sizeof(*entry)); 5009 entry->value = info; 5010 entry->next = *cpu_list; 5011 *cpu_list = entry; 5012 } 5013 5014 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) 5015 { 5016 CpuDefinitionInfoList *cpu_list = NULL; 5017 GSList *list = get_sorted_cpu_model_list(); 5018 g_slist_foreach(list, x86_cpu_definition_entry, &cpu_list); 5019 g_slist_free(list); 5020 return cpu_list; 5021 } 5022 5023 static uint64_t x86_cpu_get_supported_feature_word(FeatureWord w, 5024 bool migratable_only) 5025 { 5026 FeatureWordInfo *wi = &feature_word_info[w]; 5027 uint64_t r = 0; 5028 5029 if (kvm_enabled()) { 5030 switch (wi->type) { 5031 case CPUID_FEATURE_WORD: 5032 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid.eax, 5033 wi->cpuid.ecx, 5034 wi->cpuid.reg); 5035 break; 5036 case MSR_FEATURE_WORD: 5037 r = kvm_arch_get_supported_msr_feature(kvm_state, 5038 wi->msr.index); 5039 break; 5040 } 5041 } else if (hvf_enabled()) { 5042 if (wi->type != CPUID_FEATURE_WORD) { 5043 return 0; 5044 } 5045 r = hvf_get_supported_cpuid(wi->cpuid.eax, 5046 wi->cpuid.ecx, 5047 wi->cpuid.reg); 5048 } else if (tcg_enabled()) { 5049 r = wi->tcg_features; 5050 } else { 5051 return ~0; 5052 } 5053 if (migratable_only) { 5054 r &= x86_cpu_get_migratable_flags(w); 5055 } 5056 return r; 5057 } 5058 5059 static void x86_cpu_apply_props(X86CPU *cpu, PropValue *props) 5060 { 5061 PropValue *pv; 5062 for (pv = props; pv->prop; pv++) { 5063 if (!pv->value) { 5064 continue; 5065 } 5066 object_property_parse(OBJECT(cpu), pv->prop, pv->value, 5067 &error_abort); 5068 } 5069 } 5070 5071 /* Apply properties for the CPU model version specified in model */ 5072 static void x86_cpu_apply_version_props(X86CPU *cpu, X86CPUModel *model) 5073 { 5074 const X86CPUVersionDefinition *vdef; 5075 X86CPUVersion version = x86_cpu_model_resolve_version(model); 5076 5077 if (version == CPU_VERSION_LEGACY) { 5078 return; 5079 } 5080 5081 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) { 5082 PropValue *p; 5083 5084 for (p = vdef->props; p && p->prop; p++) { 5085 object_property_parse(OBJECT(cpu), p->prop, p->value, 5086 &error_abort); 5087 } 5088 5089 if (vdef->version == version) { 5090 break; 5091 } 5092 } 5093 5094 /* 5095 * If we reached the end of the list, version number was invalid 5096 */ 5097 assert(vdef->version == version); 5098 } 5099 5100 /* Load data from X86CPUDefinition into a X86CPU object 5101 */ 5102 static void x86_cpu_load_model(X86CPU *cpu, X86CPUModel *model) 5103 { 5104 X86CPUDefinition *def = model->cpudef; 5105 CPUX86State *env = &cpu->env; 5106 const char *vendor; 5107 char host_vendor[CPUID_VENDOR_SZ + 1]; 5108 FeatureWord w; 5109 5110 /*NOTE: any property set by this function should be returned by 5111 * x86_cpu_static_props(), so static expansion of 5112 * query-cpu-model-expansion is always complete. 5113 */ 5114 5115 /* CPU models only set _minimum_ values for level/xlevel: */ 5116 object_property_set_uint(OBJECT(cpu), "min-level", def->level, 5117 &error_abort); 5118 object_property_set_uint(OBJECT(cpu), "min-xlevel", def->xlevel, 5119 &error_abort); 5120 5121 object_property_set_int(OBJECT(cpu), "family", def->family, &error_abort); 5122 object_property_set_int(OBJECT(cpu), "model", def->model, &error_abort); 5123 object_property_set_int(OBJECT(cpu), "stepping", def->stepping, 5124 &error_abort); 5125 object_property_set_str(OBJECT(cpu), "model-id", def->model_id, 5126 &error_abort); 5127 for (w = 0; w < FEATURE_WORDS; w++) { 5128 env->features[w] = def->features[w]; 5129 } 5130 5131 /* legacy-cache defaults to 'off' if CPU model provides cache info */ 5132 cpu->legacy_cache = !def->cache_info; 5133 5134 /* Special cases not set in the X86CPUDefinition structs: */ 5135 /* TODO: in-kernel irqchip for hvf */ 5136 if (kvm_enabled()) { 5137 if (!kvm_irqchip_in_kernel()) { 5138 x86_cpu_change_kvm_default("x2apic", "off"); 5139 } 5140 5141 x86_cpu_apply_props(cpu, kvm_default_props); 5142 } else if (tcg_enabled()) { 5143 x86_cpu_apply_props(cpu, tcg_default_props); 5144 } 5145 5146 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR; 5147 5148 /* sysenter isn't supported in compatibility mode on AMD, 5149 * syscall isn't supported in compatibility mode on Intel. 5150 * Normally we advertise the actual CPU vendor, but you can 5151 * override this using the 'vendor' property if you want to use 5152 * KVM's sysenter/syscall emulation in compatibility mode and 5153 * when doing cross vendor migration 5154 */ 5155 vendor = def->vendor; 5156 if (accel_uses_host_cpuid()) { 5157 uint32_t ebx = 0, ecx = 0, edx = 0; 5158 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx); 5159 x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx); 5160 vendor = host_vendor; 5161 } 5162 5163 object_property_set_str(OBJECT(cpu), "vendor", vendor, &error_abort); 5164 5165 x86_cpu_apply_version_props(cpu, model); 5166 5167 /* 5168 * Properties in versioned CPU model are not user specified features. 5169 * We can simply clear env->user_features here since it will be filled later 5170 * in x86_cpu_expand_features() based on plus_features and minus_features. 5171 */ 5172 memset(&env->user_features, 0, sizeof(env->user_features)); 5173 } 5174 5175 #ifndef CONFIG_USER_ONLY 5176 /* Return a QDict containing keys for all properties that can be included 5177 * in static expansion of CPU models. All properties set by x86_cpu_load_model() 5178 * must be included in the dictionary. 5179 */ 5180 static QDict *x86_cpu_static_props(void) 5181 { 5182 FeatureWord w; 5183 int i; 5184 static const char *props[] = { 5185 "min-level", 5186 "min-xlevel", 5187 "family", 5188 "model", 5189 "stepping", 5190 "model-id", 5191 "vendor", 5192 "lmce", 5193 NULL, 5194 }; 5195 static QDict *d; 5196 5197 if (d) { 5198 return d; 5199 } 5200 5201 d = qdict_new(); 5202 for (i = 0; props[i]; i++) { 5203 qdict_put_null(d, props[i]); 5204 } 5205 5206 for (w = 0; w < FEATURE_WORDS; w++) { 5207 FeatureWordInfo *fi = &feature_word_info[w]; 5208 int bit; 5209 for (bit = 0; bit < 64; bit++) { 5210 if (!fi->feat_names[bit]) { 5211 continue; 5212 } 5213 qdict_put_null(d, fi->feat_names[bit]); 5214 } 5215 } 5216 5217 return d; 5218 } 5219 5220 /* Add an entry to @props dict, with the value for property. */ 5221 static void x86_cpu_expand_prop(X86CPU *cpu, QDict *props, const char *prop) 5222 { 5223 QObject *value = object_property_get_qobject(OBJECT(cpu), prop, 5224 &error_abort); 5225 5226 qdict_put_obj(props, prop, value); 5227 } 5228 5229 /* Convert CPU model data from X86CPU object to a property dictionary 5230 * that can recreate exactly the same CPU model. 5231 */ 5232 static void x86_cpu_to_dict(X86CPU *cpu, QDict *props) 5233 { 5234 QDict *sprops = x86_cpu_static_props(); 5235 const QDictEntry *e; 5236 5237 for (e = qdict_first(sprops); e; e = qdict_next(sprops, e)) { 5238 const char *prop = qdict_entry_key(e); 5239 x86_cpu_expand_prop(cpu, props, prop); 5240 } 5241 } 5242 5243 /* Convert CPU model data from X86CPU object to a property dictionary 5244 * that can recreate exactly the same CPU model, including every 5245 * writeable QOM property. 5246 */ 5247 static void x86_cpu_to_dict_full(X86CPU *cpu, QDict *props) 5248 { 5249 ObjectPropertyIterator iter; 5250 ObjectProperty *prop; 5251 5252 object_property_iter_init(&iter, OBJECT(cpu)); 5253 while ((prop = object_property_iter_next(&iter))) { 5254 /* skip read-only or write-only properties */ 5255 if (!prop->get || !prop->set) { 5256 continue; 5257 } 5258 5259 /* "hotplugged" is the only property that is configurable 5260 * on the command-line but will be set differently on CPUs 5261 * created using "-cpu ... -smp ..." and by CPUs created 5262 * on the fly by x86_cpu_from_model() for querying. Skip it. 5263 */ 5264 if (!strcmp(prop->name, "hotplugged")) { 5265 continue; 5266 } 5267 x86_cpu_expand_prop(cpu, props, prop->name); 5268 } 5269 } 5270 5271 static void object_apply_props(Object *obj, QDict *props, Error **errp) 5272 { 5273 const QDictEntry *prop; 5274 5275 for (prop = qdict_first(props); prop; prop = qdict_next(props, prop)) { 5276 if (!object_property_set_qobject(obj, qdict_entry_key(prop), 5277 qdict_entry_value(prop), errp)) { 5278 break; 5279 } 5280 } 5281 } 5282 5283 /* Create X86CPU object according to model+props specification */ 5284 static X86CPU *x86_cpu_from_model(const char *model, QDict *props, Error **errp) 5285 { 5286 X86CPU *xc = NULL; 5287 X86CPUClass *xcc; 5288 Error *err = NULL; 5289 5290 xcc = X86_CPU_CLASS(cpu_class_by_name(TYPE_X86_CPU, model)); 5291 if (xcc == NULL) { 5292 error_setg(&err, "CPU model '%s' not found", model); 5293 goto out; 5294 } 5295 5296 xc = X86_CPU(object_new_with_class(OBJECT_CLASS(xcc))); 5297 if (props) { 5298 object_apply_props(OBJECT(xc), props, &err); 5299 if (err) { 5300 goto out; 5301 } 5302 } 5303 5304 x86_cpu_expand_features(xc, &err); 5305 if (err) { 5306 goto out; 5307 } 5308 5309 out: 5310 if (err) { 5311 error_propagate(errp, err); 5312 object_unref(OBJECT(xc)); 5313 xc = NULL; 5314 } 5315 return xc; 5316 } 5317 5318 CpuModelExpansionInfo * 5319 qmp_query_cpu_model_expansion(CpuModelExpansionType type, 5320 CpuModelInfo *model, 5321 Error **errp) 5322 { 5323 X86CPU *xc = NULL; 5324 Error *err = NULL; 5325 CpuModelExpansionInfo *ret = g_new0(CpuModelExpansionInfo, 1); 5326 QDict *props = NULL; 5327 const char *base_name; 5328 5329 xc = x86_cpu_from_model(model->name, 5330 model->has_props ? 5331 qobject_to(QDict, model->props) : 5332 NULL, &err); 5333 if (err) { 5334 goto out; 5335 } 5336 5337 props = qdict_new(); 5338 ret->model = g_new0(CpuModelInfo, 1); 5339 ret->model->props = QOBJECT(props); 5340 ret->model->has_props = true; 5341 5342 switch (type) { 5343 case CPU_MODEL_EXPANSION_TYPE_STATIC: 5344 /* Static expansion will be based on "base" only */ 5345 base_name = "base"; 5346 x86_cpu_to_dict(xc, props); 5347 break; 5348 case CPU_MODEL_EXPANSION_TYPE_FULL: 5349 /* As we don't return every single property, full expansion needs 5350 * to keep the original model name+props, and add extra 5351 * properties on top of that. 5352 */ 5353 base_name = model->name; 5354 x86_cpu_to_dict_full(xc, props); 5355 break; 5356 default: 5357 error_setg(&err, "Unsupported expansion type"); 5358 goto out; 5359 } 5360 5361 x86_cpu_to_dict(xc, props); 5362 5363 ret->model->name = g_strdup(base_name); 5364 5365 out: 5366 object_unref(OBJECT(xc)); 5367 if (err) { 5368 error_propagate(errp, err); 5369 qapi_free_CpuModelExpansionInfo(ret); 5370 ret = NULL; 5371 } 5372 return ret; 5373 } 5374 #endif /* !CONFIG_USER_ONLY */ 5375 5376 static gchar *x86_gdb_arch_name(CPUState *cs) 5377 { 5378 #ifdef TARGET_X86_64 5379 return g_strdup("i386:x86-64"); 5380 #else 5381 return g_strdup("i386"); 5382 #endif 5383 } 5384 5385 static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data) 5386 { 5387 X86CPUModel *model = data; 5388 X86CPUClass *xcc = X86_CPU_CLASS(oc); 5389 CPUClass *cc = CPU_CLASS(oc); 5390 5391 xcc->model = model; 5392 xcc->migration_safe = true; 5393 cc->deprecation_note = model->cpudef->deprecation_note; 5394 } 5395 5396 static void x86_register_cpu_model_type(const char *name, X86CPUModel *model) 5397 { 5398 g_autofree char *typename = x86_cpu_type_name(name); 5399 TypeInfo ti = { 5400 .name = typename, 5401 .parent = TYPE_X86_CPU, 5402 .class_init = x86_cpu_cpudef_class_init, 5403 .class_data = model, 5404 }; 5405 5406 type_register(&ti); 5407 } 5408 5409 static void x86_register_cpudef_types(X86CPUDefinition *def) 5410 { 5411 X86CPUModel *m; 5412 const X86CPUVersionDefinition *vdef; 5413 5414 /* AMD aliases are handled at runtime based on CPUID vendor, so 5415 * they shouldn't be set on the CPU model table. 5416 */ 5417 assert(!(def->features[FEAT_8000_0001_EDX] & CPUID_EXT2_AMD_ALIASES)); 5418 /* catch mistakes instead of silently truncating model_id when too long */ 5419 assert(def->model_id && strlen(def->model_id) <= 48); 5420 5421 /* Unversioned model: */ 5422 m = g_new0(X86CPUModel, 1); 5423 m->cpudef = def; 5424 m->version = CPU_VERSION_AUTO; 5425 m->is_alias = true; 5426 x86_register_cpu_model_type(def->name, m); 5427 5428 /* Versioned models: */ 5429 5430 for (vdef = x86_cpu_def_get_versions(def); vdef->version; vdef++) { 5431 X86CPUModel *m = g_new0(X86CPUModel, 1); 5432 g_autofree char *name = 5433 x86_cpu_versioned_model_name(def, vdef->version); 5434 m->cpudef = def; 5435 m->version = vdef->version; 5436 m->note = vdef->note; 5437 x86_register_cpu_model_type(name, m); 5438 5439 if (vdef->alias) { 5440 X86CPUModel *am = g_new0(X86CPUModel, 1); 5441 am->cpudef = def; 5442 am->version = vdef->version; 5443 am->is_alias = true; 5444 x86_register_cpu_model_type(vdef->alias, am); 5445 } 5446 } 5447 5448 } 5449 5450 #if !defined(CONFIG_USER_ONLY) 5451 5452 void cpu_clear_apic_feature(CPUX86State *env) 5453 { 5454 env->features[FEAT_1_EDX] &= ~CPUID_APIC; 5455 } 5456 5457 #endif /* !CONFIG_USER_ONLY */ 5458 5459 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, 5460 uint32_t *eax, uint32_t *ebx, 5461 uint32_t *ecx, uint32_t *edx) 5462 { 5463 X86CPU *cpu = env_archcpu(env); 5464 CPUState *cs = env_cpu(env); 5465 uint32_t die_offset; 5466 uint32_t limit; 5467 uint32_t signature[3]; 5468 X86CPUTopoInfo topo_info; 5469 5470 topo_info.dies_per_pkg = env->nr_dies; 5471 topo_info.cores_per_die = cs->nr_cores; 5472 topo_info.threads_per_core = cs->nr_threads; 5473 5474 /* Calculate & apply limits for different index ranges */ 5475 if (index >= 0xC0000000) { 5476 limit = env->cpuid_xlevel2; 5477 } else if (index >= 0x80000000) { 5478 limit = env->cpuid_xlevel; 5479 } else if (index >= 0x40000000) { 5480 limit = 0x40000001; 5481 } else { 5482 limit = env->cpuid_level; 5483 } 5484 5485 if (index > limit) { 5486 /* Intel documentation states that invalid EAX input will 5487 * return the same information as EAX=cpuid_level 5488 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID) 5489 */ 5490 index = env->cpuid_level; 5491 } 5492 5493 switch(index) { 5494 case 0: 5495 *eax = env->cpuid_level; 5496 *ebx = env->cpuid_vendor1; 5497 *edx = env->cpuid_vendor2; 5498 *ecx = env->cpuid_vendor3; 5499 break; 5500 case 1: 5501 *eax = env->cpuid_version; 5502 *ebx = (cpu->apic_id << 24) | 5503 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */ 5504 *ecx = env->features[FEAT_1_ECX]; 5505 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) { 5506 *ecx |= CPUID_EXT_OSXSAVE; 5507 } 5508 *edx = env->features[FEAT_1_EDX]; 5509 if (cs->nr_cores * cs->nr_threads > 1) { 5510 *ebx |= (cs->nr_cores * cs->nr_threads) << 16; 5511 *edx |= CPUID_HT; 5512 } 5513 if (!cpu->enable_pmu) { 5514 *ecx &= ~CPUID_EXT_PDCM; 5515 } 5516 break; 5517 case 2: 5518 /* cache info: needed for Pentium Pro compatibility */ 5519 if (cpu->cache_info_passthrough) { 5520 host_cpuid(index, 0, eax, ebx, ecx, edx); 5521 break; 5522 } 5523 *eax = 1; /* Number of CPUID[EAX=2] calls required */ 5524 *ebx = 0; 5525 if (!cpu->enable_l3_cache) { 5526 *ecx = 0; 5527 } else { 5528 *ecx = cpuid2_cache_descriptor(env->cache_info_cpuid2.l3_cache); 5529 } 5530 *edx = (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1d_cache) << 16) | 5531 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1i_cache) << 8) | 5532 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l2_cache)); 5533 break; 5534 case 4: 5535 /* cache info: needed for Core compatibility */ 5536 if (cpu->cache_info_passthrough) { 5537 host_cpuid(index, count, eax, ebx, ecx, edx); 5538 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */ 5539 *eax &= ~0xFC000000; 5540 if ((*eax & 31) && cs->nr_cores > 1) { 5541 *eax |= (cs->nr_cores - 1) << 26; 5542 } 5543 } else { 5544 *eax = 0; 5545 switch (count) { 5546 case 0: /* L1 dcache info */ 5547 encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache, 5548 1, cs->nr_cores, 5549 eax, ebx, ecx, edx); 5550 break; 5551 case 1: /* L1 icache info */ 5552 encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache, 5553 1, cs->nr_cores, 5554 eax, ebx, ecx, edx); 5555 break; 5556 case 2: /* L2 cache info */ 5557 encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache, 5558 cs->nr_threads, cs->nr_cores, 5559 eax, ebx, ecx, edx); 5560 break; 5561 case 3: /* L3 cache info */ 5562 die_offset = apicid_die_offset(&topo_info); 5563 if (cpu->enable_l3_cache) { 5564 encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache, 5565 (1 << die_offset), cs->nr_cores, 5566 eax, ebx, ecx, edx); 5567 break; 5568 } 5569 /* fall through */ 5570 default: /* end of info */ 5571 *eax = *ebx = *ecx = *edx = 0; 5572 break; 5573 } 5574 } 5575 break; 5576 case 5: 5577 /* MONITOR/MWAIT Leaf */ 5578 *eax = cpu->mwait.eax; /* Smallest monitor-line size in bytes */ 5579 *ebx = cpu->mwait.ebx; /* Largest monitor-line size in bytes */ 5580 *ecx = cpu->mwait.ecx; /* flags */ 5581 *edx = cpu->mwait.edx; /* mwait substates */ 5582 break; 5583 case 6: 5584 /* Thermal and Power Leaf */ 5585 *eax = env->features[FEAT_6_EAX]; 5586 *ebx = 0; 5587 *ecx = 0; 5588 *edx = 0; 5589 break; 5590 case 7: 5591 /* Structured Extended Feature Flags Enumeration Leaf */ 5592 if (count == 0) { 5593 /* Maximum ECX value for sub-leaves */ 5594 *eax = env->cpuid_level_func7; 5595 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */ 5596 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */ 5597 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) { 5598 *ecx |= CPUID_7_0_ECX_OSPKE; 5599 } 5600 *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */ 5601 } else if (count == 1) { 5602 *eax = env->features[FEAT_7_1_EAX]; 5603 *ebx = 0; 5604 *ecx = 0; 5605 *edx = 0; 5606 } else { 5607 *eax = 0; 5608 *ebx = 0; 5609 *ecx = 0; 5610 *edx = 0; 5611 } 5612 break; 5613 case 9: 5614 /* Direct Cache Access Information Leaf */ 5615 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */ 5616 *ebx = 0; 5617 *ecx = 0; 5618 *edx = 0; 5619 break; 5620 case 0xA: 5621 /* Architectural Performance Monitoring Leaf */ 5622 if (kvm_enabled() && cpu->enable_pmu) { 5623 KVMState *s = cs->kvm_state; 5624 5625 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX); 5626 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX); 5627 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX); 5628 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX); 5629 } else if (hvf_enabled() && cpu->enable_pmu) { 5630 *eax = hvf_get_supported_cpuid(0xA, count, R_EAX); 5631 *ebx = hvf_get_supported_cpuid(0xA, count, R_EBX); 5632 *ecx = hvf_get_supported_cpuid(0xA, count, R_ECX); 5633 *edx = hvf_get_supported_cpuid(0xA, count, R_EDX); 5634 } else { 5635 *eax = 0; 5636 *ebx = 0; 5637 *ecx = 0; 5638 *edx = 0; 5639 } 5640 break; 5641 case 0xB: 5642 /* Extended Topology Enumeration Leaf */ 5643 if (!cpu->enable_cpuid_0xb) { 5644 *eax = *ebx = *ecx = *edx = 0; 5645 break; 5646 } 5647 5648 *ecx = count & 0xff; 5649 *edx = cpu->apic_id; 5650 5651 switch (count) { 5652 case 0: 5653 *eax = apicid_core_offset(&topo_info); 5654 *ebx = cs->nr_threads; 5655 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT; 5656 break; 5657 case 1: 5658 *eax = apicid_pkg_offset(&topo_info); 5659 *ebx = cs->nr_cores * cs->nr_threads; 5660 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE; 5661 break; 5662 default: 5663 *eax = 0; 5664 *ebx = 0; 5665 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID; 5666 } 5667 5668 assert(!(*eax & ~0x1f)); 5669 *ebx &= 0xffff; /* The count doesn't need to be reliable. */ 5670 break; 5671 case 0x1F: 5672 /* V2 Extended Topology Enumeration Leaf */ 5673 if (env->nr_dies < 2) { 5674 *eax = *ebx = *ecx = *edx = 0; 5675 break; 5676 } 5677 5678 *ecx = count & 0xff; 5679 *edx = cpu->apic_id; 5680 switch (count) { 5681 case 0: 5682 *eax = apicid_core_offset(&topo_info); 5683 *ebx = cs->nr_threads; 5684 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT; 5685 break; 5686 case 1: 5687 *eax = apicid_die_offset(&topo_info); 5688 *ebx = cs->nr_cores * cs->nr_threads; 5689 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE; 5690 break; 5691 case 2: 5692 *eax = apicid_pkg_offset(&topo_info); 5693 *ebx = env->nr_dies * cs->nr_cores * cs->nr_threads; 5694 *ecx |= CPUID_TOPOLOGY_LEVEL_DIE; 5695 break; 5696 default: 5697 *eax = 0; 5698 *ebx = 0; 5699 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID; 5700 } 5701 assert(!(*eax & ~0x1f)); 5702 *ebx &= 0xffff; /* The count doesn't need to be reliable. */ 5703 break; 5704 case 0xD: { 5705 /* Processor Extended State */ 5706 *eax = 0; 5707 *ebx = 0; 5708 *ecx = 0; 5709 *edx = 0; 5710 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { 5711 break; 5712 } 5713 5714 if (count == 0) { 5715 *ecx = xsave_area_size(x86_cpu_xsave_components(cpu)); 5716 *eax = env->features[FEAT_XSAVE_COMP_LO]; 5717 *edx = env->features[FEAT_XSAVE_COMP_HI]; 5718 /* 5719 * The initial value of xcr0 and ebx == 0, On host without kvm 5720 * commit 412a3c41(e.g., CentOS 6), the ebx's value always == 0 5721 * even through guest update xcr0, this will crash some legacy guest 5722 * (e.g., CentOS 6), So set ebx == ecx to workaroud it. 5723 */ 5724 *ebx = kvm_enabled() ? *ecx : xsave_area_size(env->xcr0); 5725 } else if (count == 1) { 5726 *eax = env->features[FEAT_XSAVE]; 5727 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) { 5728 if ((x86_cpu_xsave_components(cpu) >> count) & 1) { 5729 const ExtSaveArea *esa = &x86_ext_save_areas[count]; 5730 *eax = esa->size; 5731 *ebx = esa->offset; 5732 } 5733 } 5734 break; 5735 } 5736 case 0x14: { 5737 /* Intel Processor Trace Enumeration */ 5738 *eax = 0; 5739 *ebx = 0; 5740 *ecx = 0; 5741 *edx = 0; 5742 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) || 5743 !kvm_enabled()) { 5744 break; 5745 } 5746 5747 if (count == 0) { 5748 *eax = INTEL_PT_MAX_SUBLEAF; 5749 *ebx = INTEL_PT_MINIMAL_EBX; 5750 *ecx = INTEL_PT_MINIMAL_ECX; 5751 } else if (count == 1) { 5752 *eax = INTEL_PT_MTC_BITMAP | INTEL_PT_ADDR_RANGES_NUM; 5753 *ebx = INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP; 5754 } 5755 break; 5756 } 5757 case 0x40000000: 5758 /* 5759 * CPUID code in kvm_arch_init_vcpu() ignores stuff 5760 * set here, but we restrict to TCG none the less. 5761 */ 5762 if (tcg_enabled() && cpu->expose_tcg) { 5763 memcpy(signature, "TCGTCGTCGTCG", 12); 5764 *eax = 0x40000001; 5765 *ebx = signature[0]; 5766 *ecx = signature[1]; 5767 *edx = signature[2]; 5768 } else { 5769 *eax = 0; 5770 *ebx = 0; 5771 *ecx = 0; 5772 *edx = 0; 5773 } 5774 break; 5775 case 0x40000001: 5776 *eax = 0; 5777 *ebx = 0; 5778 *ecx = 0; 5779 *edx = 0; 5780 break; 5781 case 0x80000000: 5782 *eax = env->cpuid_xlevel; 5783 *ebx = env->cpuid_vendor1; 5784 *edx = env->cpuid_vendor2; 5785 *ecx = env->cpuid_vendor3; 5786 break; 5787 case 0x80000001: 5788 *eax = env->cpuid_version; 5789 *ebx = 0; 5790 *ecx = env->features[FEAT_8000_0001_ECX]; 5791 *edx = env->features[FEAT_8000_0001_EDX]; 5792 5793 /* The Linux kernel checks for the CMPLegacy bit and 5794 * discards multiple thread information if it is set. 5795 * So don't set it here for Intel to make Linux guests happy. 5796 */ 5797 if (cs->nr_cores * cs->nr_threads > 1) { 5798 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 || 5799 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 || 5800 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) { 5801 *ecx |= 1 << 1; /* CmpLegacy bit */ 5802 } 5803 } 5804 break; 5805 case 0x80000002: 5806 case 0x80000003: 5807 case 0x80000004: 5808 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0]; 5809 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1]; 5810 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2]; 5811 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3]; 5812 break; 5813 case 0x80000005: 5814 /* cache info (L1 cache) */ 5815 if (cpu->cache_info_passthrough) { 5816 host_cpuid(index, 0, eax, ebx, ecx, edx); 5817 break; 5818 } 5819 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | 5820 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES); 5821 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | 5822 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES); 5823 *ecx = encode_cache_cpuid80000005(env->cache_info_amd.l1d_cache); 5824 *edx = encode_cache_cpuid80000005(env->cache_info_amd.l1i_cache); 5825 break; 5826 case 0x80000006: 5827 /* cache info (L2 cache) */ 5828 if (cpu->cache_info_passthrough) { 5829 host_cpuid(index, 0, eax, ebx, ecx, edx); 5830 break; 5831 } 5832 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | 5833 (L2_DTLB_2M_ENTRIES << 16) | 5834 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | 5835 (L2_ITLB_2M_ENTRIES); 5836 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | 5837 (L2_DTLB_4K_ENTRIES << 16) | 5838 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | 5839 (L2_ITLB_4K_ENTRIES); 5840 encode_cache_cpuid80000006(env->cache_info_amd.l2_cache, 5841 cpu->enable_l3_cache ? 5842 env->cache_info_amd.l3_cache : NULL, 5843 ecx, edx); 5844 break; 5845 case 0x80000007: 5846 *eax = 0; 5847 *ebx = 0; 5848 *ecx = 0; 5849 *edx = env->features[FEAT_8000_0007_EDX]; 5850 break; 5851 case 0x80000008: 5852 /* virtual & phys address size in low 2 bytes. */ 5853 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 5854 /* 64 bit processor */ 5855 *eax = cpu->phys_bits; /* configurable physical bits */ 5856 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57) { 5857 *eax |= 0x00003900; /* 57 bits virtual */ 5858 } else { 5859 *eax |= 0x00003000; /* 48 bits virtual */ 5860 } 5861 } else { 5862 *eax = cpu->phys_bits; 5863 } 5864 *ebx = env->features[FEAT_8000_0008_EBX]; 5865 if (cs->nr_cores * cs->nr_threads > 1) { 5866 /* 5867 * Bits 15:12 is "The number of bits in the initial 5868 * Core::X86::Apic::ApicId[ApicId] value that indicate 5869 * thread ID within a package". 5870 * Bits 7:0 is "The number of threads in the package is NC+1" 5871 */ 5872 *ecx = (apicid_pkg_offset(&topo_info) << 12) | 5873 ((cs->nr_cores * cs->nr_threads) - 1); 5874 } else { 5875 *ecx = 0; 5876 } 5877 *edx = 0; 5878 break; 5879 case 0x8000000A: 5880 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { 5881 *eax = 0x00000001; /* SVM Revision */ 5882 *ebx = 0x00000010; /* nr of ASIDs */ 5883 *ecx = 0; 5884 *edx = env->features[FEAT_SVM]; /* optional features */ 5885 } else { 5886 *eax = 0; 5887 *ebx = 0; 5888 *ecx = 0; 5889 *edx = 0; 5890 } 5891 break; 5892 case 0x8000001D: 5893 *eax = 0; 5894 if (cpu->cache_info_passthrough) { 5895 host_cpuid(index, count, eax, ebx, ecx, edx); 5896 break; 5897 } 5898 switch (count) { 5899 case 0: /* L1 dcache info */ 5900 encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache, 5901 &topo_info, eax, ebx, ecx, edx); 5902 break; 5903 case 1: /* L1 icache info */ 5904 encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache, 5905 &topo_info, eax, ebx, ecx, edx); 5906 break; 5907 case 2: /* L2 cache info */ 5908 encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache, 5909 &topo_info, eax, ebx, ecx, edx); 5910 break; 5911 case 3: /* L3 cache info */ 5912 encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache, 5913 &topo_info, eax, ebx, ecx, edx); 5914 break; 5915 default: /* end of info */ 5916 *eax = *ebx = *ecx = *edx = 0; 5917 break; 5918 } 5919 break; 5920 case 0x8000001E: 5921 if (cpu->core_id <= 255) { 5922 encode_topo_cpuid8000001e(cpu, &topo_info, eax, ebx, ecx, edx); 5923 } else { 5924 *eax = 0; 5925 *ebx = 0; 5926 *ecx = 0; 5927 *edx = 0; 5928 } 5929 break; 5930 case 0xC0000000: 5931 *eax = env->cpuid_xlevel2; 5932 *ebx = 0; 5933 *ecx = 0; 5934 *edx = 0; 5935 break; 5936 case 0xC0000001: 5937 /* Support for VIA CPU's CPUID instruction */ 5938 *eax = env->cpuid_version; 5939 *ebx = 0; 5940 *ecx = 0; 5941 *edx = env->features[FEAT_C000_0001_EDX]; 5942 break; 5943 case 0xC0000002: 5944 case 0xC0000003: 5945 case 0xC0000004: 5946 /* Reserved for the future, and now filled with zero */ 5947 *eax = 0; 5948 *ebx = 0; 5949 *ecx = 0; 5950 *edx = 0; 5951 break; 5952 case 0x8000001F: 5953 *eax = sev_enabled() ? 0x2 : 0; 5954 *ebx = sev_get_cbit_position(); 5955 *ebx |= sev_get_reduced_phys_bits() << 6; 5956 *ecx = 0; 5957 *edx = 0; 5958 break; 5959 default: 5960 /* reserved values: zero */ 5961 *eax = 0; 5962 *ebx = 0; 5963 *ecx = 0; 5964 *edx = 0; 5965 break; 5966 } 5967 } 5968 5969 static void x86_cpu_reset(DeviceState *dev) 5970 { 5971 CPUState *s = CPU(dev); 5972 X86CPU *cpu = X86_CPU(s); 5973 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu); 5974 CPUX86State *env = &cpu->env; 5975 target_ulong cr4; 5976 uint64_t xcr0; 5977 int i; 5978 5979 xcc->parent_reset(dev); 5980 5981 memset(env, 0, offsetof(CPUX86State, end_reset_fields)); 5982 5983 env->old_exception = -1; 5984 5985 /* init to reset state */ 5986 5987 env->hflags2 |= HF2_GIF_MASK; 5988 env->hflags &= ~HF_GUEST_MASK; 5989 5990 cpu_x86_update_cr0(env, 0x60000010); 5991 env->a20_mask = ~0x0; 5992 env->smbase = 0x30000; 5993 env->msr_smi_count = 0; 5994 5995 env->idt.limit = 0xffff; 5996 env->gdt.limit = 0xffff; 5997 env->ldt.limit = 0xffff; 5998 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT); 5999 env->tr.limit = 0xffff; 6000 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT); 6001 6002 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff, 6003 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK | 6004 DESC_R_MASK | DESC_A_MASK); 6005 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff, 6006 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 6007 DESC_A_MASK); 6008 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff, 6009 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 6010 DESC_A_MASK); 6011 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff, 6012 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 6013 DESC_A_MASK); 6014 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff, 6015 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 6016 DESC_A_MASK); 6017 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff, 6018 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 6019 DESC_A_MASK); 6020 6021 env->eip = 0xfff0; 6022 env->regs[R_EDX] = env->cpuid_version; 6023 6024 env->eflags = 0x2; 6025 6026 /* FPU init */ 6027 for (i = 0; i < 8; i++) { 6028 env->fptags[i] = 1; 6029 } 6030 cpu_set_fpuc(env, 0x37f); 6031 6032 env->mxcsr = 0x1f80; 6033 /* All units are in INIT state. */ 6034 env->xstate_bv = 0; 6035 6036 env->pat = 0x0007040600070406ULL; 6037 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT; 6038 if (env->features[FEAT_1_ECX] & CPUID_EXT_MONITOR) { 6039 env->msr_ia32_misc_enable |= MSR_IA32_MISC_ENABLE_MWAIT; 6040 } 6041 6042 memset(env->dr, 0, sizeof(env->dr)); 6043 env->dr[6] = DR6_FIXED_1; 6044 env->dr[7] = DR7_FIXED_1; 6045 cpu_breakpoint_remove_all(s, BP_CPU); 6046 cpu_watchpoint_remove_all(s, BP_CPU); 6047 6048 cr4 = 0; 6049 xcr0 = XSTATE_FP_MASK; 6050 6051 #ifdef CONFIG_USER_ONLY 6052 /* Enable all the features for user-mode. */ 6053 if (env->features[FEAT_1_EDX] & CPUID_SSE) { 6054 xcr0 |= XSTATE_SSE_MASK; 6055 } 6056 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 6057 const ExtSaveArea *esa = &x86_ext_save_areas[i]; 6058 if (env->features[esa->feature] & esa->bits) { 6059 xcr0 |= 1ull << i; 6060 } 6061 } 6062 6063 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) { 6064 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK; 6065 } 6066 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) { 6067 cr4 |= CR4_FSGSBASE_MASK; 6068 } 6069 #endif 6070 6071 env->xcr0 = xcr0; 6072 cpu_x86_update_cr4(env, cr4); 6073 6074 /* 6075 * SDM 11.11.5 requires: 6076 * - IA32_MTRR_DEF_TYPE MSR.E = 0 6077 * - IA32_MTRR_PHYSMASKn.V = 0 6078 * All other bits are undefined. For simplification, zero it all. 6079 */ 6080 env->mtrr_deftype = 0; 6081 memset(env->mtrr_var, 0, sizeof(env->mtrr_var)); 6082 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed)); 6083 6084 env->interrupt_injected = -1; 6085 env->exception_nr = -1; 6086 env->exception_pending = 0; 6087 env->exception_injected = 0; 6088 env->exception_has_payload = false; 6089 env->exception_payload = 0; 6090 env->nmi_injected = false; 6091 #if !defined(CONFIG_USER_ONLY) 6092 /* We hard-wire the BSP to the first CPU. */ 6093 apic_designate_bsp(cpu->apic_state, s->cpu_index == 0); 6094 6095 s->halted = !cpu_is_bsp(cpu); 6096 6097 if (kvm_enabled()) { 6098 kvm_arch_reset_vcpu(cpu); 6099 } 6100 #endif 6101 } 6102 6103 #ifndef CONFIG_USER_ONLY 6104 bool cpu_is_bsp(X86CPU *cpu) 6105 { 6106 return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP; 6107 } 6108 6109 /* TODO: remove me, when reset over QOM tree is implemented */ 6110 static void x86_cpu_machine_reset_cb(void *opaque) 6111 { 6112 X86CPU *cpu = opaque; 6113 cpu_reset(CPU(cpu)); 6114 } 6115 #endif 6116 6117 static void mce_init(X86CPU *cpu) 6118 { 6119 CPUX86State *cenv = &cpu->env; 6120 unsigned int bank; 6121 6122 if (((cenv->cpuid_version >> 8) & 0xf) >= 6 6123 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) == 6124 (CPUID_MCE | CPUID_MCA)) { 6125 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF | 6126 (cpu->enable_lmce ? MCG_LMCE_P : 0); 6127 cenv->mcg_ctl = ~(uint64_t)0; 6128 for (bank = 0; bank < MCE_BANKS_DEF; bank++) { 6129 cenv->mce_banks[bank * 4] = ~(uint64_t)0; 6130 } 6131 } 6132 } 6133 6134 #ifndef CONFIG_USER_ONLY 6135 APICCommonClass *apic_get_class(void) 6136 { 6137 const char *apic_type = "apic"; 6138 6139 /* TODO: in-kernel irqchip for hvf */ 6140 if (kvm_apic_in_kernel()) { 6141 apic_type = "kvm-apic"; 6142 } else if (xen_enabled()) { 6143 apic_type = "xen-apic"; 6144 } 6145 6146 return APIC_COMMON_CLASS(object_class_by_name(apic_type)); 6147 } 6148 6149 static void x86_cpu_apic_create(X86CPU *cpu, Error **errp) 6150 { 6151 APICCommonState *apic; 6152 ObjectClass *apic_class = OBJECT_CLASS(apic_get_class()); 6153 6154 cpu->apic_state = DEVICE(object_new_with_class(apic_class)); 6155 6156 object_property_add_child(OBJECT(cpu), "lapic", 6157 OBJECT(cpu->apic_state)); 6158 object_unref(OBJECT(cpu->apic_state)); 6159 6160 qdev_prop_set_uint32(cpu->apic_state, "id", cpu->apic_id); 6161 /* TODO: convert to link<> */ 6162 apic = APIC_COMMON(cpu->apic_state); 6163 apic->cpu = cpu; 6164 apic->apicbase = APIC_DEFAULT_ADDRESS | MSR_IA32_APICBASE_ENABLE; 6165 } 6166 6167 static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp) 6168 { 6169 APICCommonState *apic; 6170 static bool apic_mmio_map_once; 6171 6172 if (cpu->apic_state == NULL) { 6173 return; 6174 } 6175 qdev_realize(DEVICE(cpu->apic_state), NULL, errp); 6176 6177 /* Map APIC MMIO area */ 6178 apic = APIC_COMMON(cpu->apic_state); 6179 if (!apic_mmio_map_once) { 6180 memory_region_add_subregion_overlap(get_system_memory(), 6181 apic->apicbase & 6182 MSR_IA32_APICBASE_BASE, 6183 &apic->io_memory, 6184 0x1000); 6185 apic_mmio_map_once = true; 6186 } 6187 } 6188 6189 static void x86_cpu_machine_done(Notifier *n, void *unused) 6190 { 6191 X86CPU *cpu = container_of(n, X86CPU, machine_done); 6192 MemoryRegion *smram = 6193 (MemoryRegion *) object_resolve_path("/machine/smram", NULL); 6194 6195 if (smram) { 6196 cpu->smram = g_new(MemoryRegion, 1); 6197 memory_region_init_alias(cpu->smram, OBJECT(cpu), "smram", 6198 smram, 0, 4 * GiB); 6199 memory_region_set_enabled(cpu->smram, true); 6200 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->smram, 1); 6201 } 6202 } 6203 #else 6204 static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp) 6205 { 6206 } 6207 #endif 6208 6209 /* Note: Only safe for use on x86(-64) hosts */ 6210 static uint32_t x86_host_phys_bits(void) 6211 { 6212 uint32_t eax; 6213 uint32_t host_phys_bits; 6214 6215 host_cpuid(0x80000000, 0, &eax, NULL, NULL, NULL); 6216 if (eax >= 0x80000008) { 6217 host_cpuid(0x80000008, 0, &eax, NULL, NULL, NULL); 6218 /* Note: According to AMD doc 25481 rev 2.34 they have a field 6219 * at 23:16 that can specify a maximum physical address bits for 6220 * the guest that can override this value; but I've not seen 6221 * anything with that set. 6222 */ 6223 host_phys_bits = eax & 0xff; 6224 } else { 6225 /* It's an odd 64 bit machine that doesn't have the leaf for 6226 * physical address bits; fall back to 36 that's most older 6227 * Intel. 6228 */ 6229 host_phys_bits = 36; 6230 } 6231 6232 return host_phys_bits; 6233 } 6234 6235 static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value) 6236 { 6237 if (*min < value) { 6238 *min = value; 6239 } 6240 } 6241 6242 /* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */ 6243 static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w) 6244 { 6245 CPUX86State *env = &cpu->env; 6246 FeatureWordInfo *fi = &feature_word_info[w]; 6247 uint32_t eax = fi->cpuid.eax; 6248 uint32_t region = eax & 0xF0000000; 6249 6250 assert(feature_word_info[w].type == CPUID_FEATURE_WORD); 6251 if (!env->features[w]) { 6252 return; 6253 } 6254 6255 switch (region) { 6256 case 0x00000000: 6257 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax); 6258 break; 6259 case 0x80000000: 6260 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax); 6261 break; 6262 case 0xC0000000: 6263 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax); 6264 break; 6265 } 6266 6267 if (eax == 7) { 6268 x86_cpu_adjust_level(cpu, &env->cpuid_min_level_func7, 6269 fi->cpuid.ecx); 6270 } 6271 } 6272 6273 /* Calculate XSAVE components based on the configured CPU feature flags */ 6274 static void x86_cpu_enable_xsave_components(X86CPU *cpu) 6275 { 6276 CPUX86State *env = &cpu->env; 6277 int i; 6278 uint64_t mask; 6279 6280 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { 6281 env->features[FEAT_XSAVE_COMP_LO] = 0; 6282 env->features[FEAT_XSAVE_COMP_HI] = 0; 6283 return; 6284 } 6285 6286 mask = 0; 6287 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 6288 const ExtSaveArea *esa = &x86_ext_save_areas[i]; 6289 if (env->features[esa->feature] & esa->bits) { 6290 mask |= (1ULL << i); 6291 } 6292 } 6293 6294 env->features[FEAT_XSAVE_COMP_LO] = mask; 6295 env->features[FEAT_XSAVE_COMP_HI] = mask >> 32; 6296 } 6297 6298 /***** Steps involved on loading and filtering CPUID data 6299 * 6300 * When initializing and realizing a CPU object, the steps 6301 * involved in setting up CPUID data are: 6302 * 6303 * 1) Loading CPU model definition (X86CPUDefinition). This is 6304 * implemented by x86_cpu_load_model() and should be completely 6305 * transparent, as it is done automatically by instance_init. 6306 * No code should need to look at X86CPUDefinition structs 6307 * outside instance_init. 6308 * 6309 * 2) CPU expansion. This is done by realize before CPUID 6310 * filtering, and will make sure host/accelerator data is 6311 * loaded for CPU models that depend on host capabilities 6312 * (e.g. "host"). Done by x86_cpu_expand_features(). 6313 * 6314 * 3) CPUID filtering. This initializes extra data related to 6315 * CPUID, and checks if the host supports all capabilities 6316 * required by the CPU. Runnability of a CPU model is 6317 * determined at this step. Done by x86_cpu_filter_features(). 6318 * 6319 * Some operations don't require all steps to be performed. 6320 * More precisely: 6321 * 6322 * - CPU instance creation (instance_init) will run only CPU 6323 * model loading. CPU expansion can't run at instance_init-time 6324 * because host/accelerator data may be not available yet. 6325 * - CPU realization will perform both CPU model expansion and CPUID 6326 * filtering, and return an error in case one of them fails. 6327 * - query-cpu-definitions needs to run all 3 steps. It needs 6328 * to run CPUID filtering, as the 'unavailable-features' 6329 * field is set based on the filtering results. 6330 * - The query-cpu-model-expansion QMP command only needs to run 6331 * CPU model loading and CPU expansion. It should not filter 6332 * any CPUID data based on host capabilities. 6333 */ 6334 6335 /* Expand CPU configuration data, based on configured features 6336 * and host/accelerator capabilities when appropriate. 6337 */ 6338 static void x86_cpu_expand_features(X86CPU *cpu, Error **errp) 6339 { 6340 CPUX86State *env = &cpu->env; 6341 FeatureWord w; 6342 int i; 6343 GList *l; 6344 6345 for (l = plus_features; l; l = l->next) { 6346 const char *prop = l->data; 6347 if (!object_property_set_bool(OBJECT(cpu), prop, true, errp)) { 6348 return; 6349 } 6350 } 6351 6352 for (l = minus_features; l; l = l->next) { 6353 const char *prop = l->data; 6354 if (!object_property_set_bool(OBJECT(cpu), prop, false, errp)) { 6355 return; 6356 } 6357 } 6358 6359 /*TODO: Now cpu->max_features doesn't overwrite features 6360 * set using QOM properties, and we can convert 6361 * plus_features & minus_features to global properties 6362 * inside x86_cpu_parse_featurestr() too. 6363 */ 6364 if (cpu->max_features) { 6365 for (w = 0; w < FEATURE_WORDS; w++) { 6366 /* Override only features that weren't set explicitly 6367 * by the user. 6368 */ 6369 env->features[w] |= 6370 x86_cpu_get_supported_feature_word(w, cpu->migratable) & 6371 ~env->user_features[w] & 6372 ~feature_word_info[w].no_autoenable_flags; 6373 } 6374 } 6375 6376 for (i = 0; i < ARRAY_SIZE(feature_dependencies); i++) { 6377 FeatureDep *d = &feature_dependencies[i]; 6378 if (!(env->features[d->from.index] & d->from.mask)) { 6379 uint64_t unavailable_features = env->features[d->to.index] & d->to.mask; 6380 6381 /* Not an error unless the dependent feature was added explicitly. */ 6382 mark_unavailable_features(cpu, d->to.index, 6383 unavailable_features & env->user_features[d->to.index], 6384 "This feature depends on other features that were not requested"); 6385 6386 env->features[d->to.index] &= ~unavailable_features; 6387 } 6388 } 6389 6390 if (!kvm_enabled() || !cpu->expose_kvm) { 6391 env->features[FEAT_KVM] = 0; 6392 } 6393 6394 x86_cpu_enable_xsave_components(cpu); 6395 6396 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */ 6397 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX); 6398 if (cpu->full_cpuid_auto_level) { 6399 x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX); 6400 x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX); 6401 x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX); 6402 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX); 6403 x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EAX); 6404 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX); 6405 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX); 6406 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX); 6407 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0008_EBX); 6408 x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX); 6409 x86_cpu_adjust_feat_level(cpu, FEAT_SVM); 6410 x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE); 6411 6412 /* Intel Processor Trace requires CPUID[0x14] */ 6413 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT)) { 6414 if (cpu->intel_pt_auto_level) { 6415 x86_cpu_adjust_level(cpu, &cpu->env.cpuid_min_level, 0x14); 6416 } else if (cpu->env.cpuid_min_level < 0x14) { 6417 mark_unavailable_features(cpu, FEAT_7_0_EBX, 6418 CPUID_7_0_EBX_INTEL_PT, 6419 "Intel PT need CPUID leaf 0x14, please set by \"-cpu ...,+intel-pt,min-level=0x14\""); 6420 } 6421 } 6422 6423 /* CPU topology with multi-dies support requires CPUID[0x1F] */ 6424 if (env->nr_dies > 1) { 6425 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x1F); 6426 } 6427 6428 /* SVM requires CPUID[0x8000000A] */ 6429 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { 6430 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A); 6431 } 6432 6433 /* SEV requires CPUID[0x8000001F] */ 6434 if (sev_enabled()) { 6435 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F); 6436 } 6437 } 6438 6439 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */ 6440 if (env->cpuid_level_func7 == UINT32_MAX) { 6441 env->cpuid_level_func7 = env->cpuid_min_level_func7; 6442 } 6443 if (env->cpuid_level == UINT32_MAX) { 6444 env->cpuid_level = env->cpuid_min_level; 6445 } 6446 if (env->cpuid_xlevel == UINT32_MAX) { 6447 env->cpuid_xlevel = env->cpuid_min_xlevel; 6448 } 6449 if (env->cpuid_xlevel2 == UINT32_MAX) { 6450 env->cpuid_xlevel2 = env->cpuid_min_xlevel2; 6451 } 6452 } 6453 6454 /* 6455 * Finishes initialization of CPUID data, filters CPU feature 6456 * words based on host availability of each feature. 6457 * 6458 * Returns: 0 if all flags are supported by the host, non-zero otherwise. 6459 */ 6460 static void x86_cpu_filter_features(X86CPU *cpu, bool verbose) 6461 { 6462 CPUX86State *env = &cpu->env; 6463 FeatureWord w; 6464 const char *prefix = NULL; 6465 6466 if (verbose) { 6467 prefix = accel_uses_host_cpuid() 6468 ? "host doesn't support requested feature" 6469 : "TCG doesn't support requested feature"; 6470 } 6471 6472 for (w = 0; w < FEATURE_WORDS; w++) { 6473 uint64_t host_feat = 6474 x86_cpu_get_supported_feature_word(w, false); 6475 uint64_t requested_features = env->features[w]; 6476 uint64_t unavailable_features = requested_features & ~host_feat; 6477 mark_unavailable_features(cpu, w, unavailable_features, prefix); 6478 } 6479 6480 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) && 6481 kvm_enabled()) { 6482 KVMState *s = CPU(cpu)->kvm_state; 6483 uint32_t eax_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EAX); 6484 uint32_t ebx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EBX); 6485 uint32_t ecx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_ECX); 6486 uint32_t eax_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EAX); 6487 uint32_t ebx_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EBX); 6488 6489 if (!eax_0 || 6490 ((ebx_0 & INTEL_PT_MINIMAL_EBX) != INTEL_PT_MINIMAL_EBX) || 6491 ((ecx_0 & INTEL_PT_MINIMAL_ECX) != INTEL_PT_MINIMAL_ECX) || 6492 ((eax_1 & INTEL_PT_MTC_BITMAP) != INTEL_PT_MTC_BITMAP) || 6493 ((eax_1 & INTEL_PT_ADDR_RANGES_NUM_MASK) < 6494 INTEL_PT_ADDR_RANGES_NUM) || 6495 ((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) != 6496 (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) || 6497 (ecx_0 & INTEL_PT_IP_LIP)) { 6498 /* 6499 * Processor Trace capabilities aren't configurable, so if the 6500 * host can't emulate the capabilities we report on 6501 * cpu_x86_cpuid(), intel-pt can't be enabled on the current host. 6502 */ 6503 mark_unavailable_features(cpu, FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT, prefix); 6504 } 6505 } 6506 } 6507 6508 static void x86_cpu_realizefn(DeviceState *dev, Error **errp) 6509 { 6510 CPUState *cs = CPU(dev); 6511 X86CPU *cpu = X86_CPU(dev); 6512 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev); 6513 CPUX86State *env = &cpu->env; 6514 Error *local_err = NULL; 6515 static bool ht_warned; 6516 6517 if (xcc->host_cpuid_required) { 6518 if (!accel_uses_host_cpuid()) { 6519 g_autofree char *name = x86_cpu_class_get_model_name(xcc); 6520 error_setg(&local_err, "CPU model '%s' requires KVM", name); 6521 goto out; 6522 } 6523 } 6524 6525 if (cpu->max_features && accel_uses_host_cpuid()) { 6526 if (enable_cpu_pm) { 6527 host_cpuid(5, 0, &cpu->mwait.eax, &cpu->mwait.ebx, 6528 &cpu->mwait.ecx, &cpu->mwait.edx); 6529 env->features[FEAT_1_ECX] |= CPUID_EXT_MONITOR; 6530 if (kvm_enabled() && kvm_has_waitpkg()) { 6531 env->features[FEAT_7_0_ECX] |= CPUID_7_0_ECX_WAITPKG; 6532 } 6533 } 6534 if (kvm_enabled() && cpu->ucode_rev == 0) { 6535 cpu->ucode_rev = kvm_arch_get_supported_msr_feature(kvm_state, 6536 MSR_IA32_UCODE_REV); 6537 } 6538 } 6539 6540 if (cpu->ucode_rev == 0) { 6541 /* The default is the same as KVM's. */ 6542 if (IS_AMD_CPU(env)) { 6543 cpu->ucode_rev = 0x01000065; 6544 } else { 6545 cpu->ucode_rev = 0x100000000ULL; 6546 } 6547 } 6548 6549 /* mwait extended info: needed for Core compatibility */ 6550 /* We always wake on interrupt even if host does not have the capability */ 6551 cpu->mwait.ecx |= CPUID_MWAIT_EMX | CPUID_MWAIT_IBE; 6552 6553 if (cpu->apic_id == UNASSIGNED_APIC_ID) { 6554 error_setg(errp, "apic-id property was not initialized properly"); 6555 return; 6556 } 6557 6558 x86_cpu_expand_features(cpu, &local_err); 6559 if (local_err) { 6560 goto out; 6561 } 6562 6563 x86_cpu_filter_features(cpu, cpu->check_cpuid || cpu->enforce_cpuid); 6564 6565 if (cpu->enforce_cpuid && x86_cpu_have_filtered_features(cpu)) { 6566 error_setg(&local_err, 6567 accel_uses_host_cpuid() ? 6568 "Host doesn't support requested features" : 6569 "TCG doesn't support requested features"); 6570 goto out; 6571 } 6572 6573 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on 6574 * CPUID[1].EDX. 6575 */ 6576 if (IS_AMD_CPU(env)) { 6577 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES; 6578 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX] 6579 & CPUID_EXT2_AMD_ALIASES); 6580 } 6581 6582 /* For 64bit systems think about the number of physical bits to present. 6583 * ideally this should be the same as the host; anything other than matching 6584 * the host can cause incorrect guest behaviour. 6585 * QEMU used to pick the magic value of 40 bits that corresponds to 6586 * consumer AMD devices but nothing else. 6587 */ 6588 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 6589 if (accel_uses_host_cpuid()) { 6590 uint32_t host_phys_bits = x86_host_phys_bits(); 6591 static bool warned; 6592 6593 /* Print a warning if the user set it to a value that's not the 6594 * host value. 6595 */ 6596 if (cpu->phys_bits != host_phys_bits && cpu->phys_bits != 0 && 6597 !warned) { 6598 warn_report("Host physical bits (%u)" 6599 " does not match phys-bits property (%u)", 6600 host_phys_bits, cpu->phys_bits); 6601 warned = true; 6602 } 6603 6604 if (cpu->host_phys_bits) { 6605 /* The user asked for us to use the host physical bits */ 6606 cpu->phys_bits = host_phys_bits; 6607 if (cpu->host_phys_bits_limit && 6608 cpu->phys_bits > cpu->host_phys_bits_limit) { 6609 cpu->phys_bits = cpu->host_phys_bits_limit; 6610 } 6611 } 6612 6613 if (cpu->phys_bits && 6614 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS || 6615 cpu->phys_bits < 32)) { 6616 error_setg(errp, "phys-bits should be between 32 and %u " 6617 " (but is %u)", 6618 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits); 6619 return; 6620 } 6621 } else { 6622 if (cpu->phys_bits && cpu->phys_bits != TCG_PHYS_ADDR_BITS) { 6623 error_setg(errp, "TCG only supports phys-bits=%u", 6624 TCG_PHYS_ADDR_BITS); 6625 return; 6626 } 6627 } 6628 /* 0 means it was not explicitly set by the user (or by machine 6629 * compat_props or by the host code above). In this case, the default 6630 * is the value used by TCG (40). 6631 */ 6632 if (cpu->phys_bits == 0) { 6633 cpu->phys_bits = TCG_PHYS_ADDR_BITS; 6634 } 6635 } else { 6636 /* For 32 bit systems don't use the user set value, but keep 6637 * phys_bits consistent with what we tell the guest. 6638 */ 6639 if (cpu->phys_bits != 0) { 6640 error_setg(errp, "phys-bits is not user-configurable in 32 bit"); 6641 return; 6642 } 6643 6644 if (env->features[FEAT_1_EDX] & CPUID_PSE36) { 6645 cpu->phys_bits = 36; 6646 } else { 6647 cpu->phys_bits = 32; 6648 } 6649 } 6650 6651 /* Cache information initialization */ 6652 if (!cpu->legacy_cache) { 6653 if (!xcc->model || !xcc->model->cpudef->cache_info) { 6654 g_autofree char *name = x86_cpu_class_get_model_name(xcc); 6655 error_setg(errp, 6656 "CPU model '%s' doesn't support legacy-cache=off", name); 6657 return; 6658 } 6659 env->cache_info_cpuid2 = env->cache_info_cpuid4 = env->cache_info_amd = 6660 *xcc->model->cpudef->cache_info; 6661 } else { 6662 /* Build legacy cache information */ 6663 env->cache_info_cpuid2.l1d_cache = &legacy_l1d_cache; 6664 env->cache_info_cpuid2.l1i_cache = &legacy_l1i_cache; 6665 env->cache_info_cpuid2.l2_cache = &legacy_l2_cache_cpuid2; 6666 env->cache_info_cpuid2.l3_cache = &legacy_l3_cache; 6667 6668 env->cache_info_cpuid4.l1d_cache = &legacy_l1d_cache; 6669 env->cache_info_cpuid4.l1i_cache = &legacy_l1i_cache; 6670 env->cache_info_cpuid4.l2_cache = &legacy_l2_cache; 6671 env->cache_info_cpuid4.l3_cache = &legacy_l3_cache; 6672 6673 env->cache_info_amd.l1d_cache = &legacy_l1d_cache_amd; 6674 env->cache_info_amd.l1i_cache = &legacy_l1i_cache_amd; 6675 env->cache_info_amd.l2_cache = &legacy_l2_cache_amd; 6676 env->cache_info_amd.l3_cache = &legacy_l3_cache; 6677 } 6678 6679 6680 cpu_exec_realizefn(cs, &local_err); 6681 if (local_err != NULL) { 6682 error_propagate(errp, local_err); 6683 return; 6684 } 6685 6686 #ifndef CONFIG_USER_ONLY 6687 MachineState *ms = MACHINE(qdev_get_machine()); 6688 qemu_register_reset(x86_cpu_machine_reset_cb, cpu); 6689 6690 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || ms->smp.cpus > 1) { 6691 x86_cpu_apic_create(cpu, &local_err); 6692 if (local_err != NULL) { 6693 goto out; 6694 } 6695 } 6696 #endif 6697 6698 mce_init(cpu); 6699 6700 #ifndef CONFIG_USER_ONLY 6701 if (tcg_enabled()) { 6702 cpu->cpu_as_mem = g_new(MemoryRegion, 1); 6703 cpu->cpu_as_root = g_new(MemoryRegion, 1); 6704 6705 /* Outer container... */ 6706 memory_region_init(cpu->cpu_as_root, OBJECT(cpu), "memory", ~0ull); 6707 memory_region_set_enabled(cpu->cpu_as_root, true); 6708 6709 /* ... with two regions inside: normal system memory with low 6710 * priority, and... 6711 */ 6712 memory_region_init_alias(cpu->cpu_as_mem, OBJECT(cpu), "memory", 6713 get_system_memory(), 0, ~0ull); 6714 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->cpu_as_mem, 0); 6715 memory_region_set_enabled(cpu->cpu_as_mem, true); 6716 6717 cs->num_ases = 2; 6718 cpu_address_space_init(cs, 0, "cpu-memory", cs->memory); 6719 cpu_address_space_init(cs, 1, "cpu-smm", cpu->cpu_as_root); 6720 6721 /* ... SMRAM with higher priority, linked from /machine/smram. */ 6722 cpu->machine_done.notify = x86_cpu_machine_done; 6723 qemu_add_machine_init_done_notifier(&cpu->machine_done); 6724 } 6725 #endif 6726 6727 qemu_init_vcpu(cs); 6728 6729 /* 6730 * Most Intel and certain AMD CPUs support hyperthreading. Even though QEMU 6731 * fixes this issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX 6732 * based on inputs (sockets,cores,threads), it is still better to give 6733 * users a warning. 6734 * 6735 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise 6736 * cs->nr_threads hasn't be populated yet and the checking is incorrect. 6737 */ 6738 if (IS_AMD_CPU(env) && 6739 !(env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) && 6740 cs->nr_threads > 1 && !ht_warned) { 6741 warn_report("This family of AMD CPU doesn't support " 6742 "hyperthreading(%d)", 6743 cs->nr_threads); 6744 error_printf("Please configure -smp options properly" 6745 " or try enabling topoext feature.\n"); 6746 ht_warned = true; 6747 } 6748 6749 x86_cpu_apic_realize(cpu, &local_err); 6750 if (local_err != NULL) { 6751 goto out; 6752 } 6753 cpu_reset(cs); 6754 6755 xcc->parent_realize(dev, &local_err); 6756 6757 out: 6758 if (local_err != NULL) { 6759 error_propagate(errp, local_err); 6760 return; 6761 } 6762 } 6763 6764 static void x86_cpu_unrealizefn(DeviceState *dev) 6765 { 6766 X86CPU *cpu = X86_CPU(dev); 6767 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev); 6768 6769 #ifndef CONFIG_USER_ONLY 6770 cpu_remove_sync(CPU(dev)); 6771 qemu_unregister_reset(x86_cpu_machine_reset_cb, dev); 6772 #endif 6773 6774 if (cpu->apic_state) { 6775 object_unparent(OBJECT(cpu->apic_state)); 6776 cpu->apic_state = NULL; 6777 } 6778 6779 xcc->parent_unrealize(dev); 6780 } 6781 6782 typedef struct BitProperty { 6783 FeatureWord w; 6784 uint64_t mask; 6785 } BitProperty; 6786 6787 static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name, 6788 void *opaque, Error **errp) 6789 { 6790 X86CPU *cpu = X86_CPU(obj); 6791 BitProperty *fp = opaque; 6792 uint64_t f = cpu->env.features[fp->w]; 6793 bool value = (f & fp->mask) == fp->mask; 6794 visit_type_bool(v, name, &value, errp); 6795 } 6796 6797 static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name, 6798 void *opaque, Error **errp) 6799 { 6800 DeviceState *dev = DEVICE(obj); 6801 X86CPU *cpu = X86_CPU(obj); 6802 BitProperty *fp = opaque; 6803 bool value; 6804 6805 if (dev->realized) { 6806 qdev_prop_set_after_realize(dev, name, errp); 6807 return; 6808 } 6809 6810 if (!visit_type_bool(v, name, &value, errp)) { 6811 return; 6812 } 6813 6814 if (value) { 6815 cpu->env.features[fp->w] |= fp->mask; 6816 } else { 6817 cpu->env.features[fp->w] &= ~fp->mask; 6818 } 6819 cpu->env.user_features[fp->w] |= fp->mask; 6820 } 6821 6822 static void x86_cpu_release_bit_prop(Object *obj, const char *name, 6823 void *opaque) 6824 { 6825 BitProperty *prop = opaque; 6826 g_free(prop); 6827 } 6828 6829 /* Register a boolean property to get/set a single bit in a uint32_t field. 6830 * 6831 * The same property name can be registered multiple times to make it affect 6832 * multiple bits in the same FeatureWord. In that case, the getter will return 6833 * true only if all bits are set. 6834 */ 6835 static void x86_cpu_register_bit_prop(X86CPU *cpu, 6836 const char *prop_name, 6837 FeatureWord w, 6838 int bitnr) 6839 { 6840 BitProperty *fp; 6841 ObjectProperty *op; 6842 uint64_t mask = (1ULL << bitnr); 6843 6844 op = object_property_find(OBJECT(cpu), prop_name); 6845 if (op) { 6846 fp = op->opaque; 6847 assert(fp->w == w); 6848 fp->mask |= mask; 6849 } else { 6850 fp = g_new0(BitProperty, 1); 6851 fp->w = w; 6852 fp->mask = mask; 6853 object_property_add(OBJECT(cpu), prop_name, "bool", 6854 x86_cpu_get_bit_prop, 6855 x86_cpu_set_bit_prop, 6856 x86_cpu_release_bit_prop, fp); 6857 } 6858 } 6859 6860 static void x86_cpu_register_feature_bit_props(X86CPU *cpu, 6861 FeatureWord w, 6862 int bitnr) 6863 { 6864 FeatureWordInfo *fi = &feature_word_info[w]; 6865 const char *name = fi->feat_names[bitnr]; 6866 6867 if (!name) { 6868 return; 6869 } 6870 6871 /* Property names should use "-" instead of "_". 6872 * Old names containing underscores are registered as aliases 6873 * using object_property_add_alias() 6874 */ 6875 assert(!strchr(name, '_')); 6876 /* aliases don't use "|" delimiters anymore, they are registered 6877 * manually using object_property_add_alias() */ 6878 assert(!strchr(name, '|')); 6879 x86_cpu_register_bit_prop(cpu, name, w, bitnr); 6880 } 6881 6882 #if !defined(CONFIG_USER_ONLY) 6883 static GuestPanicInformation *x86_cpu_get_crash_info(CPUState *cs) 6884 { 6885 X86CPU *cpu = X86_CPU(cs); 6886 CPUX86State *env = &cpu->env; 6887 GuestPanicInformation *panic_info = NULL; 6888 6889 if (env->features[FEAT_HYPERV_EDX] & HV_GUEST_CRASH_MSR_AVAILABLE) { 6890 panic_info = g_malloc0(sizeof(GuestPanicInformation)); 6891 6892 panic_info->type = GUEST_PANIC_INFORMATION_TYPE_HYPER_V; 6893 6894 assert(HV_CRASH_PARAMS >= 5); 6895 panic_info->u.hyper_v.arg1 = env->msr_hv_crash_params[0]; 6896 panic_info->u.hyper_v.arg2 = env->msr_hv_crash_params[1]; 6897 panic_info->u.hyper_v.arg3 = env->msr_hv_crash_params[2]; 6898 panic_info->u.hyper_v.arg4 = env->msr_hv_crash_params[3]; 6899 panic_info->u.hyper_v.arg5 = env->msr_hv_crash_params[4]; 6900 } 6901 6902 return panic_info; 6903 } 6904 static void x86_cpu_get_crash_info_qom(Object *obj, Visitor *v, 6905 const char *name, void *opaque, 6906 Error **errp) 6907 { 6908 CPUState *cs = CPU(obj); 6909 GuestPanicInformation *panic_info; 6910 6911 if (!cs->crash_occurred) { 6912 error_setg(errp, "No crash occured"); 6913 return; 6914 } 6915 6916 panic_info = x86_cpu_get_crash_info(cs); 6917 if (panic_info == NULL) { 6918 error_setg(errp, "No crash information"); 6919 return; 6920 } 6921 6922 visit_type_GuestPanicInformation(v, "crash-information", &panic_info, 6923 errp); 6924 qapi_free_GuestPanicInformation(panic_info); 6925 } 6926 #endif /* !CONFIG_USER_ONLY */ 6927 6928 static void x86_cpu_initfn(Object *obj) 6929 { 6930 X86CPU *cpu = X86_CPU(obj); 6931 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj); 6932 CPUX86State *env = &cpu->env; 6933 FeatureWord w; 6934 6935 env->nr_dies = 1; 6936 cpu_set_cpustate_pointers(cpu); 6937 6938 object_property_add(obj, "family", "int", 6939 x86_cpuid_version_get_family, 6940 x86_cpuid_version_set_family, NULL, NULL); 6941 object_property_add(obj, "model", "int", 6942 x86_cpuid_version_get_model, 6943 x86_cpuid_version_set_model, NULL, NULL); 6944 object_property_add(obj, "stepping", "int", 6945 x86_cpuid_version_get_stepping, 6946 x86_cpuid_version_set_stepping, NULL, NULL); 6947 object_property_add_str(obj, "vendor", 6948 x86_cpuid_get_vendor, 6949 x86_cpuid_set_vendor); 6950 object_property_add_str(obj, "model-id", 6951 x86_cpuid_get_model_id, 6952 x86_cpuid_set_model_id); 6953 object_property_add(obj, "tsc-frequency", "int", 6954 x86_cpuid_get_tsc_freq, 6955 x86_cpuid_set_tsc_freq, NULL, NULL); 6956 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo", 6957 x86_cpu_get_feature_words, 6958 NULL, NULL, (void *)env->features); 6959 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo", 6960 x86_cpu_get_feature_words, 6961 NULL, NULL, (void *)cpu->filtered_features); 6962 /* 6963 * The "unavailable-features" property has the same semantics as 6964 * CpuDefinitionInfo.unavailable-features on the "query-cpu-definitions" 6965 * QMP command: they list the features that would have prevented the 6966 * CPU from running if the "enforce" flag was set. 6967 */ 6968 object_property_add(obj, "unavailable-features", "strList", 6969 x86_cpu_get_unavailable_features, 6970 NULL, NULL, NULL); 6971 6972 #if !defined(CONFIG_USER_ONLY) 6973 object_property_add(obj, "crash-information", "GuestPanicInformation", 6974 x86_cpu_get_crash_info_qom, NULL, NULL, NULL); 6975 #endif 6976 6977 for (w = 0; w < FEATURE_WORDS; w++) { 6978 int bitnr; 6979 6980 for (bitnr = 0; bitnr < 64; bitnr++) { 6981 x86_cpu_register_feature_bit_props(cpu, w, bitnr); 6982 } 6983 } 6984 6985 object_property_add_alias(obj, "sse3", obj, "pni"); 6986 object_property_add_alias(obj, "pclmuldq", obj, "pclmulqdq"); 6987 object_property_add_alias(obj, "sse4-1", obj, "sse4.1"); 6988 object_property_add_alias(obj, "sse4-2", obj, "sse4.2"); 6989 object_property_add_alias(obj, "xd", obj, "nx"); 6990 object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt"); 6991 object_property_add_alias(obj, "i64", obj, "lm"); 6992 6993 object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl"); 6994 object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust"); 6995 object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt"); 6996 object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm"); 6997 object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy"); 6998 object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr"); 6999 object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core"); 7000 object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb"); 7001 object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay"); 7002 object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu"); 7003 object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf"); 7004 object_property_add_alias(obj, "kvm_asyncpf_int", obj, "kvm-asyncpf-int"); 7005 object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time"); 7006 object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi"); 7007 object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt"); 7008 object_property_add_alias(obj, "kvm_poll_control", obj, "kvm-poll-control"); 7009 object_property_add_alias(obj, "svm_lock", obj, "svm-lock"); 7010 object_property_add_alias(obj, "nrip_save", obj, "nrip-save"); 7011 object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale"); 7012 object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean"); 7013 object_property_add_alias(obj, "pause_filter", obj, "pause-filter"); 7014 object_property_add_alias(obj, "sse4_1", obj, "sse4.1"); 7015 object_property_add_alias(obj, "sse4_2", obj, "sse4.2"); 7016 7017 if (xcc->model) { 7018 x86_cpu_load_model(cpu, xcc->model); 7019 } 7020 } 7021 7022 static int64_t x86_cpu_get_arch_id(CPUState *cs) 7023 { 7024 X86CPU *cpu = X86_CPU(cs); 7025 7026 return cpu->apic_id; 7027 } 7028 7029 static bool x86_cpu_get_paging_enabled(const CPUState *cs) 7030 { 7031 X86CPU *cpu = X86_CPU(cs); 7032 7033 return cpu->env.cr[0] & CR0_PG_MASK; 7034 } 7035 7036 static void x86_cpu_set_pc(CPUState *cs, vaddr value) 7037 { 7038 X86CPU *cpu = X86_CPU(cs); 7039 7040 cpu->env.eip = value; 7041 } 7042 7043 static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) 7044 { 7045 X86CPU *cpu = X86_CPU(cs); 7046 7047 cpu->env.eip = tb->pc - tb->cs_base; 7048 } 7049 7050 int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request) 7051 { 7052 X86CPU *cpu = X86_CPU(cs); 7053 CPUX86State *env = &cpu->env; 7054 7055 #if !defined(CONFIG_USER_ONLY) 7056 if (interrupt_request & CPU_INTERRUPT_POLL) { 7057 return CPU_INTERRUPT_POLL; 7058 } 7059 #endif 7060 if (interrupt_request & CPU_INTERRUPT_SIPI) { 7061 return CPU_INTERRUPT_SIPI; 7062 } 7063 7064 if (env->hflags2 & HF2_GIF_MASK) { 7065 if ((interrupt_request & CPU_INTERRUPT_SMI) && 7066 !(env->hflags & HF_SMM_MASK)) { 7067 return CPU_INTERRUPT_SMI; 7068 } else if ((interrupt_request & CPU_INTERRUPT_NMI) && 7069 !(env->hflags2 & HF2_NMI_MASK)) { 7070 return CPU_INTERRUPT_NMI; 7071 } else if (interrupt_request & CPU_INTERRUPT_MCE) { 7072 return CPU_INTERRUPT_MCE; 7073 } else if ((interrupt_request & CPU_INTERRUPT_HARD) && 7074 (((env->hflags2 & HF2_VINTR_MASK) && 7075 (env->hflags2 & HF2_HIF_MASK)) || 7076 (!(env->hflags2 & HF2_VINTR_MASK) && 7077 (env->eflags & IF_MASK && 7078 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) { 7079 return CPU_INTERRUPT_HARD; 7080 #if !defined(CONFIG_USER_ONLY) 7081 } else if ((interrupt_request & CPU_INTERRUPT_VIRQ) && 7082 (env->eflags & IF_MASK) && 7083 !(env->hflags & HF_INHIBIT_IRQ_MASK)) { 7084 return CPU_INTERRUPT_VIRQ; 7085 #endif 7086 } 7087 } 7088 7089 return 0; 7090 } 7091 7092 static bool x86_cpu_has_work(CPUState *cs) 7093 { 7094 return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0; 7095 } 7096 7097 static void x86_disas_set_info(CPUState *cs, disassemble_info *info) 7098 { 7099 X86CPU *cpu = X86_CPU(cs); 7100 CPUX86State *env = &cpu->env; 7101 7102 info->mach = (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64 7103 : env->hflags & HF_CS32_MASK ? bfd_mach_i386_i386 7104 : bfd_mach_i386_i8086); 7105 info->print_insn = print_insn_i386; 7106 7107 info->cap_arch = CS_ARCH_X86; 7108 info->cap_mode = (env->hflags & HF_CS64_MASK ? CS_MODE_64 7109 : env->hflags & HF_CS32_MASK ? CS_MODE_32 7110 : CS_MODE_16); 7111 info->cap_insn_unit = 1; 7112 info->cap_insn_split = 8; 7113 } 7114 7115 void x86_update_hflags(CPUX86State *env) 7116 { 7117 uint32_t hflags; 7118 #define HFLAG_COPY_MASK \ 7119 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \ 7120 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \ 7121 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \ 7122 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK) 7123 7124 hflags = env->hflags & HFLAG_COPY_MASK; 7125 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK; 7126 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT); 7127 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) & 7128 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK); 7129 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK)); 7130 7131 if (env->cr[4] & CR4_OSFXSR_MASK) { 7132 hflags |= HF_OSFXSR_MASK; 7133 } 7134 7135 if (env->efer & MSR_EFER_LMA) { 7136 hflags |= HF_LMA_MASK; 7137 } 7138 7139 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) { 7140 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; 7141 } else { 7142 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >> 7143 (DESC_B_SHIFT - HF_CS32_SHIFT); 7144 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >> 7145 (DESC_B_SHIFT - HF_SS32_SHIFT); 7146 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) || 7147 !(hflags & HF_CS32_MASK)) { 7148 hflags |= HF_ADDSEG_MASK; 7149 } else { 7150 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base | 7151 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT; 7152 } 7153 } 7154 env->hflags = hflags; 7155 } 7156 7157 static Property x86_cpu_properties[] = { 7158 #ifdef CONFIG_USER_ONLY 7159 /* apic_id = 0 by default for *-user, see commit 9886e834 */ 7160 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0), 7161 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0), 7162 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0), 7163 DEFINE_PROP_INT32("die-id", X86CPU, die_id, 0), 7164 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0), 7165 #else 7166 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID), 7167 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1), 7168 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1), 7169 DEFINE_PROP_INT32("die-id", X86CPU, die_id, -1), 7170 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1), 7171 #endif 7172 DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID), 7173 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false), 7174 7175 DEFINE_PROP_UINT32("hv-spinlocks", X86CPU, hyperv_spinlock_attempts, 7176 HYPERV_SPINLOCK_NEVER_NOTIFY), 7177 DEFINE_PROP_BIT64("hv-relaxed", X86CPU, hyperv_features, 7178 HYPERV_FEAT_RELAXED, 0), 7179 DEFINE_PROP_BIT64("hv-vapic", X86CPU, hyperv_features, 7180 HYPERV_FEAT_VAPIC, 0), 7181 DEFINE_PROP_BIT64("hv-time", X86CPU, hyperv_features, 7182 HYPERV_FEAT_TIME, 0), 7183 DEFINE_PROP_BIT64("hv-crash", X86CPU, hyperv_features, 7184 HYPERV_FEAT_CRASH, 0), 7185 DEFINE_PROP_BIT64("hv-reset", X86CPU, hyperv_features, 7186 HYPERV_FEAT_RESET, 0), 7187 DEFINE_PROP_BIT64("hv-vpindex", X86CPU, hyperv_features, 7188 HYPERV_FEAT_VPINDEX, 0), 7189 DEFINE_PROP_BIT64("hv-runtime", X86CPU, hyperv_features, 7190 HYPERV_FEAT_RUNTIME, 0), 7191 DEFINE_PROP_BIT64("hv-synic", X86CPU, hyperv_features, 7192 HYPERV_FEAT_SYNIC, 0), 7193 DEFINE_PROP_BIT64("hv-stimer", X86CPU, hyperv_features, 7194 HYPERV_FEAT_STIMER, 0), 7195 DEFINE_PROP_BIT64("hv-frequencies", X86CPU, hyperv_features, 7196 HYPERV_FEAT_FREQUENCIES, 0), 7197 DEFINE_PROP_BIT64("hv-reenlightenment", X86CPU, hyperv_features, 7198 HYPERV_FEAT_REENLIGHTENMENT, 0), 7199 DEFINE_PROP_BIT64("hv-tlbflush", X86CPU, hyperv_features, 7200 HYPERV_FEAT_TLBFLUSH, 0), 7201 DEFINE_PROP_BIT64("hv-evmcs", X86CPU, hyperv_features, 7202 HYPERV_FEAT_EVMCS, 0), 7203 DEFINE_PROP_BIT64("hv-ipi", X86CPU, hyperv_features, 7204 HYPERV_FEAT_IPI, 0), 7205 DEFINE_PROP_BIT64("hv-stimer-direct", X86CPU, hyperv_features, 7206 HYPERV_FEAT_STIMER_DIRECT, 0), 7207 DEFINE_PROP_ON_OFF_AUTO("hv-no-nonarch-coresharing", X86CPU, 7208 hyperv_no_nonarch_cs, ON_OFF_AUTO_OFF), 7209 DEFINE_PROP_BOOL("hv-passthrough", X86CPU, hyperv_passthrough, false), 7210 7211 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true), 7212 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false), 7213 DEFINE_PROP_BOOL("x-force-features", X86CPU, force_features, false), 7214 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true), 7215 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0), 7216 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false), 7217 DEFINE_PROP_UINT8("host-phys-bits-limit", X86CPU, host_phys_bits_limit, 0), 7218 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true), 7219 DEFINE_PROP_UINT32("level-func7", X86CPU, env.cpuid_level_func7, 7220 UINT32_MAX), 7221 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX), 7222 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX), 7223 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX), 7224 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0), 7225 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0), 7226 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0), 7227 DEFINE_PROP_UINT64("ucode-rev", X86CPU, ucode_rev, 0), 7228 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true), 7229 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor_id), 7230 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true), 7231 DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false), 7232 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true), 7233 DEFINE_PROP_BOOL("kvm-no-smi-migration", X86CPU, kvm_no_smi_migration, 7234 false), 7235 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true), 7236 DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true), 7237 DEFINE_PROP_BOOL("x-migrate-smi-count", X86CPU, migrate_smi_count, 7238 true), 7239 /* 7240 * lecacy_cache defaults to true unless the CPU model provides its 7241 * own cache information (see x86_cpu_load_def()). 7242 */ 7243 DEFINE_PROP_BOOL("legacy-cache", X86CPU, legacy_cache, true), 7244 7245 /* 7246 * From "Requirements for Implementing the Microsoft 7247 * Hypervisor Interface": 7248 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs 7249 * 7250 * "Starting with Windows Server 2012 and Windows 8, if 7251 * CPUID.40000005.EAX contains a value of -1, Windows assumes that 7252 * the hypervisor imposes no specific limit to the number of VPs. 7253 * In this case, Windows Server 2012 guest VMs may use more than 7254 * 64 VPs, up to the maximum supported number of processors applicable 7255 * to the specific Windows version being used." 7256 */ 7257 DEFINE_PROP_INT32("x-hv-max-vps", X86CPU, hv_max_vps, -1), 7258 DEFINE_PROP_BOOL("x-hv-synic-kvm-only", X86CPU, hyperv_synic_kvm_only, 7259 false), 7260 DEFINE_PROP_BOOL("x-intel-pt-auto-level", X86CPU, intel_pt_auto_level, 7261 true), 7262 DEFINE_PROP_END_OF_LIST() 7263 }; 7264 7265 static void x86_cpu_common_class_init(ObjectClass *oc, void *data) 7266 { 7267 X86CPUClass *xcc = X86_CPU_CLASS(oc); 7268 CPUClass *cc = CPU_CLASS(oc); 7269 DeviceClass *dc = DEVICE_CLASS(oc); 7270 7271 device_class_set_parent_realize(dc, x86_cpu_realizefn, 7272 &xcc->parent_realize); 7273 device_class_set_parent_unrealize(dc, x86_cpu_unrealizefn, 7274 &xcc->parent_unrealize); 7275 device_class_set_props(dc, x86_cpu_properties); 7276 7277 device_class_set_parent_reset(dc, x86_cpu_reset, &xcc->parent_reset); 7278 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP; 7279 7280 cc->class_by_name = x86_cpu_class_by_name; 7281 cc->parse_features = x86_cpu_parse_featurestr; 7282 cc->has_work = x86_cpu_has_work; 7283 #ifdef CONFIG_TCG 7284 cc->do_interrupt = x86_cpu_do_interrupt; 7285 cc->cpu_exec_interrupt = x86_cpu_exec_interrupt; 7286 #endif 7287 cc->dump_state = x86_cpu_dump_state; 7288 cc->set_pc = x86_cpu_set_pc; 7289 cc->synchronize_from_tb = x86_cpu_synchronize_from_tb; 7290 cc->gdb_read_register = x86_cpu_gdb_read_register; 7291 cc->gdb_write_register = x86_cpu_gdb_write_register; 7292 cc->get_arch_id = x86_cpu_get_arch_id; 7293 cc->get_paging_enabled = x86_cpu_get_paging_enabled; 7294 #ifndef CONFIG_USER_ONLY 7295 cc->asidx_from_attrs = x86_asidx_from_attrs; 7296 cc->get_memory_mapping = x86_cpu_get_memory_mapping; 7297 cc->get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug; 7298 cc->get_crash_info = x86_cpu_get_crash_info; 7299 cc->write_elf64_note = x86_cpu_write_elf64_note; 7300 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote; 7301 cc->write_elf32_note = x86_cpu_write_elf32_note; 7302 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote; 7303 cc->vmsd = &vmstate_x86_cpu; 7304 #endif 7305 cc->gdb_arch_name = x86_gdb_arch_name; 7306 #ifdef TARGET_X86_64 7307 cc->gdb_core_xml_file = "i386-64bit.xml"; 7308 cc->gdb_num_core_regs = 66; 7309 #else 7310 cc->gdb_core_xml_file = "i386-32bit.xml"; 7311 cc->gdb_num_core_regs = 50; 7312 #endif 7313 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) 7314 cc->debug_excp_handler = breakpoint_handler; 7315 #endif 7316 cc->cpu_exec_enter = x86_cpu_exec_enter; 7317 cc->cpu_exec_exit = x86_cpu_exec_exit; 7318 #ifdef CONFIG_TCG 7319 cc->tcg_initialize = tcg_x86_init; 7320 cc->tlb_fill = x86_cpu_tlb_fill; 7321 #endif 7322 cc->disas_set_info = x86_disas_set_info; 7323 7324 dc->user_creatable = true; 7325 } 7326 7327 static const TypeInfo x86_cpu_type_info = { 7328 .name = TYPE_X86_CPU, 7329 .parent = TYPE_CPU, 7330 .instance_size = sizeof(X86CPU), 7331 .instance_init = x86_cpu_initfn, 7332 .abstract = true, 7333 .class_size = sizeof(X86CPUClass), 7334 .class_init = x86_cpu_common_class_init, 7335 }; 7336 7337 7338 /* "base" CPU model, used by query-cpu-model-expansion */ 7339 static void x86_cpu_base_class_init(ObjectClass *oc, void *data) 7340 { 7341 X86CPUClass *xcc = X86_CPU_CLASS(oc); 7342 7343 xcc->static_model = true; 7344 xcc->migration_safe = true; 7345 xcc->model_description = "base CPU model type with no features enabled"; 7346 xcc->ordering = 8; 7347 } 7348 7349 static const TypeInfo x86_base_cpu_type_info = { 7350 .name = X86_CPU_TYPE_NAME("base"), 7351 .parent = TYPE_X86_CPU, 7352 .class_init = x86_cpu_base_class_init, 7353 }; 7354 7355 static void x86_cpu_register_types(void) 7356 { 7357 int i; 7358 7359 type_register_static(&x86_cpu_type_info); 7360 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) { 7361 x86_register_cpudef_types(&builtin_x86_defs[i]); 7362 } 7363 type_register_static(&max_x86_cpu_type_info); 7364 type_register_static(&x86_base_cpu_type_info); 7365 #if defined(CONFIG_KVM) || defined(CONFIG_HVF) 7366 type_register_static(&host_x86_cpu_type_info); 7367 #endif 7368 } 7369 7370 type_init(x86_cpu_register_types) 7371