1 /* 2 * i386 CPUID helper functions 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/units.h" 22 #include "qemu/cutils.h" 23 #include "qemu/bitops.h" 24 #include "qemu/qemu-print.h" 25 26 #include "cpu.h" 27 #include "exec/exec-all.h" 28 #include "sysemu/kvm.h" 29 #include "sysemu/reset.h" 30 #include "sysemu/hvf.h" 31 #include "sysemu/cpus.h" 32 #include "sysemu/xen.h" 33 #include "sysemu/whpx.h" 34 #include "kvm_i386.h" 35 #include "sev_i386.h" 36 37 #include "qemu/error-report.h" 38 #include "qemu/module.h" 39 #include "qemu/option.h" 40 #include "qemu/config-file.h" 41 #include "qapi/error.h" 42 #include "qapi/qapi-visit-machine.h" 43 #include "qapi/qapi-visit-run-state.h" 44 #include "qapi/qmp/qdict.h" 45 #include "qapi/qmp/qerror.h" 46 #include "qapi/visitor.h" 47 #include "qom/qom-qobject.h" 48 #include "sysemu/arch_init.h" 49 #include "qapi/qapi-commands-machine-target.h" 50 51 #include "standard-headers/asm-x86/kvm_para.h" 52 53 #include "sysemu/sysemu.h" 54 #include "sysemu/tcg.h" 55 #include "hw/qdev-properties.h" 56 #include "hw/i386/topology.h" 57 #ifndef CONFIG_USER_ONLY 58 #include "exec/address-spaces.h" 59 #include "hw/i386/apic_internal.h" 60 #include "hw/boards.h" 61 #endif 62 63 #include "disas/capstone.h" 64 65 /* Helpers for building CPUID[2] descriptors: */ 66 67 struct CPUID2CacheDescriptorInfo { 68 enum CacheType type; 69 int level; 70 int size; 71 int line_size; 72 int associativity; 73 }; 74 75 /* 76 * Known CPUID 2 cache descriptors. 77 * From Intel SDM Volume 2A, CPUID instruction 78 */ 79 struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = { 80 [0x06] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 8 * KiB, 81 .associativity = 4, .line_size = 32, }, 82 [0x08] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 16 * KiB, 83 .associativity = 4, .line_size = 32, }, 84 [0x09] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB, 85 .associativity = 4, .line_size = 64, }, 86 [0x0A] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB, 87 .associativity = 2, .line_size = 32, }, 88 [0x0C] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 89 .associativity = 4, .line_size = 32, }, 90 [0x0D] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 91 .associativity = 4, .line_size = 64, }, 92 [0x0E] = { .level = 1, .type = DATA_CACHE, .size = 24 * KiB, 93 .associativity = 6, .line_size = 64, }, 94 [0x1D] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB, 95 .associativity = 2, .line_size = 64, }, 96 [0x21] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 97 .associativity = 8, .line_size = 64, }, 98 /* lines per sector is not supported cpuid2_cache_descriptor(), 99 * so descriptors 0x22, 0x23 are not included 100 */ 101 [0x24] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 102 .associativity = 16, .line_size = 64, }, 103 /* lines per sector is not supported cpuid2_cache_descriptor(), 104 * so descriptors 0x25, 0x20 are not included 105 */ 106 [0x2C] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB, 107 .associativity = 8, .line_size = 64, }, 108 [0x30] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB, 109 .associativity = 8, .line_size = 64, }, 110 [0x41] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB, 111 .associativity = 4, .line_size = 32, }, 112 [0x42] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 113 .associativity = 4, .line_size = 32, }, 114 [0x43] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 115 .associativity = 4, .line_size = 32, }, 116 [0x44] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 117 .associativity = 4, .line_size = 32, }, 118 [0x45] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 119 .associativity = 4, .line_size = 32, }, 120 [0x46] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 121 .associativity = 4, .line_size = 64, }, 122 [0x47] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 123 .associativity = 8, .line_size = 64, }, 124 [0x48] = { .level = 2, .type = UNIFIED_CACHE, .size = 3 * MiB, 125 .associativity = 12, .line_size = 64, }, 126 /* Descriptor 0x49 depends on CPU family/model, so it is not included */ 127 [0x4A] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB, 128 .associativity = 12, .line_size = 64, }, 129 [0x4B] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 130 .associativity = 16, .line_size = 64, }, 131 [0x4C] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB, 132 .associativity = 12, .line_size = 64, }, 133 [0x4D] = { .level = 3, .type = UNIFIED_CACHE, .size = 16 * MiB, 134 .associativity = 16, .line_size = 64, }, 135 [0x4E] = { .level = 2, .type = UNIFIED_CACHE, .size = 6 * MiB, 136 .associativity = 24, .line_size = 64, }, 137 [0x60] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 138 .associativity = 8, .line_size = 64, }, 139 [0x66] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB, 140 .associativity = 4, .line_size = 64, }, 141 [0x67] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 142 .associativity = 4, .line_size = 64, }, 143 [0x68] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB, 144 .associativity = 4, .line_size = 64, }, 145 [0x78] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 146 .associativity = 4, .line_size = 64, }, 147 /* lines per sector is not supported cpuid2_cache_descriptor(), 148 * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included. 149 */ 150 [0x7D] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 151 .associativity = 8, .line_size = 64, }, 152 [0x7F] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 153 .associativity = 2, .line_size = 64, }, 154 [0x80] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 155 .associativity = 8, .line_size = 64, }, 156 [0x82] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 157 .associativity = 8, .line_size = 32, }, 158 [0x83] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 159 .associativity = 8, .line_size = 32, }, 160 [0x84] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 161 .associativity = 8, .line_size = 32, }, 162 [0x85] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 163 .associativity = 8, .line_size = 32, }, 164 [0x86] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 165 .associativity = 4, .line_size = 64, }, 166 [0x87] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 167 .associativity = 8, .line_size = 64, }, 168 [0xD0] = { .level = 3, .type = UNIFIED_CACHE, .size = 512 * KiB, 169 .associativity = 4, .line_size = 64, }, 170 [0xD1] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB, 171 .associativity = 4, .line_size = 64, }, 172 [0xD2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 173 .associativity = 4, .line_size = 64, }, 174 [0xD6] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB, 175 .associativity = 8, .line_size = 64, }, 176 [0xD7] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 177 .associativity = 8, .line_size = 64, }, 178 [0xD8] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 179 .associativity = 8, .line_size = 64, }, 180 [0xDC] = { .level = 3, .type = UNIFIED_CACHE, .size = 1.5 * MiB, 181 .associativity = 12, .line_size = 64, }, 182 [0xDD] = { .level = 3, .type = UNIFIED_CACHE, .size = 3 * MiB, 183 .associativity = 12, .line_size = 64, }, 184 [0xDE] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB, 185 .associativity = 12, .line_size = 64, }, 186 [0xE2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 187 .associativity = 16, .line_size = 64, }, 188 [0xE3] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 189 .associativity = 16, .line_size = 64, }, 190 [0xE4] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 191 .associativity = 16, .line_size = 64, }, 192 [0xEA] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB, 193 .associativity = 24, .line_size = 64, }, 194 [0xEB] = { .level = 3, .type = UNIFIED_CACHE, .size = 18 * MiB, 195 .associativity = 24, .line_size = 64, }, 196 [0xEC] = { .level = 3, .type = UNIFIED_CACHE, .size = 24 * MiB, 197 .associativity = 24, .line_size = 64, }, 198 }; 199 200 /* 201 * "CPUID leaf 2 does not report cache descriptor information, 202 * use CPUID leaf 4 to query cache parameters" 203 */ 204 #define CACHE_DESCRIPTOR_UNAVAILABLE 0xFF 205 206 /* 207 * Return a CPUID 2 cache descriptor for a given cache. 208 * If no known descriptor is found, return CACHE_DESCRIPTOR_UNAVAILABLE 209 */ 210 static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache) 211 { 212 int i; 213 214 assert(cache->size > 0); 215 assert(cache->level > 0); 216 assert(cache->line_size > 0); 217 assert(cache->associativity > 0); 218 for (i = 0; i < ARRAY_SIZE(cpuid2_cache_descriptors); i++) { 219 struct CPUID2CacheDescriptorInfo *d = &cpuid2_cache_descriptors[i]; 220 if (d->level == cache->level && d->type == cache->type && 221 d->size == cache->size && d->line_size == cache->line_size && 222 d->associativity == cache->associativity) { 223 return i; 224 } 225 } 226 227 return CACHE_DESCRIPTOR_UNAVAILABLE; 228 } 229 230 /* CPUID Leaf 4 constants: */ 231 232 /* EAX: */ 233 #define CACHE_TYPE_D 1 234 #define CACHE_TYPE_I 2 235 #define CACHE_TYPE_UNIFIED 3 236 237 #define CACHE_LEVEL(l) (l << 5) 238 239 #define CACHE_SELF_INIT_LEVEL (1 << 8) 240 241 /* EDX: */ 242 #define CACHE_NO_INVD_SHARING (1 << 0) 243 #define CACHE_INCLUSIVE (1 << 1) 244 #define CACHE_COMPLEX_IDX (1 << 2) 245 246 /* Encode CacheType for CPUID[4].EAX */ 247 #define CACHE_TYPE(t) (((t) == DATA_CACHE) ? CACHE_TYPE_D : \ 248 ((t) == INSTRUCTION_CACHE) ? CACHE_TYPE_I : \ 249 ((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \ 250 0 /* Invalid value */) 251 252 253 /* Encode cache info for CPUID[4] */ 254 static void encode_cache_cpuid4(CPUCacheInfo *cache, 255 int num_apic_ids, int num_cores, 256 uint32_t *eax, uint32_t *ebx, 257 uint32_t *ecx, uint32_t *edx) 258 { 259 assert(cache->size == cache->line_size * cache->associativity * 260 cache->partitions * cache->sets); 261 262 assert(num_apic_ids > 0); 263 *eax = CACHE_TYPE(cache->type) | 264 CACHE_LEVEL(cache->level) | 265 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) | 266 ((num_cores - 1) << 26) | 267 ((num_apic_ids - 1) << 14); 268 269 assert(cache->line_size > 0); 270 assert(cache->partitions > 0); 271 assert(cache->associativity > 0); 272 /* We don't implement fully-associative caches */ 273 assert(cache->associativity < cache->sets); 274 *ebx = (cache->line_size - 1) | 275 ((cache->partitions - 1) << 12) | 276 ((cache->associativity - 1) << 22); 277 278 assert(cache->sets > 0); 279 *ecx = cache->sets - 1; 280 281 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) | 282 (cache->inclusive ? CACHE_INCLUSIVE : 0) | 283 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); 284 } 285 286 /* Encode cache info for CPUID[0x80000005].ECX or CPUID[0x80000005].EDX */ 287 static uint32_t encode_cache_cpuid80000005(CPUCacheInfo *cache) 288 { 289 assert(cache->size % 1024 == 0); 290 assert(cache->lines_per_tag > 0); 291 assert(cache->associativity > 0); 292 assert(cache->line_size > 0); 293 return ((cache->size / 1024) << 24) | (cache->associativity << 16) | 294 (cache->lines_per_tag << 8) | (cache->line_size); 295 } 296 297 #define ASSOC_FULL 0xFF 298 299 /* AMD associativity encoding used on CPUID Leaf 0x80000006: */ 300 #define AMD_ENC_ASSOC(a) (a <= 1 ? a : \ 301 a == 2 ? 0x2 : \ 302 a == 4 ? 0x4 : \ 303 a == 8 ? 0x6 : \ 304 a == 16 ? 0x8 : \ 305 a == 32 ? 0xA : \ 306 a == 48 ? 0xB : \ 307 a == 64 ? 0xC : \ 308 a == 96 ? 0xD : \ 309 a == 128 ? 0xE : \ 310 a == ASSOC_FULL ? 0xF : \ 311 0 /* invalid value */) 312 313 /* 314 * Encode cache info for CPUID[0x80000006].ECX and CPUID[0x80000006].EDX 315 * @l3 can be NULL. 316 */ 317 static void encode_cache_cpuid80000006(CPUCacheInfo *l2, 318 CPUCacheInfo *l3, 319 uint32_t *ecx, uint32_t *edx) 320 { 321 assert(l2->size % 1024 == 0); 322 assert(l2->associativity > 0); 323 assert(l2->lines_per_tag > 0); 324 assert(l2->line_size > 0); 325 *ecx = ((l2->size / 1024) << 16) | 326 (AMD_ENC_ASSOC(l2->associativity) << 12) | 327 (l2->lines_per_tag << 8) | (l2->line_size); 328 329 if (l3) { 330 assert(l3->size % (512 * 1024) == 0); 331 assert(l3->associativity > 0); 332 assert(l3->lines_per_tag > 0); 333 assert(l3->line_size > 0); 334 *edx = ((l3->size / (512 * 1024)) << 18) | 335 (AMD_ENC_ASSOC(l3->associativity) << 12) | 336 (l3->lines_per_tag << 8) | (l3->line_size); 337 } else { 338 *edx = 0; 339 } 340 } 341 342 /* Encode cache info for CPUID[8000001D] */ 343 static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, 344 X86CPUTopoInfo *topo_info, 345 uint32_t *eax, uint32_t *ebx, 346 uint32_t *ecx, uint32_t *edx) 347 { 348 uint32_t l3_threads; 349 assert(cache->size == cache->line_size * cache->associativity * 350 cache->partitions * cache->sets); 351 352 *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) | 353 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0); 354 355 /* L3 is shared among multiple cores */ 356 if (cache->level == 3) { 357 l3_threads = topo_info->cores_per_die * topo_info->threads_per_core; 358 *eax |= (l3_threads - 1) << 14; 359 } else { 360 *eax |= ((topo_info->threads_per_core - 1) << 14); 361 } 362 363 assert(cache->line_size > 0); 364 assert(cache->partitions > 0); 365 assert(cache->associativity > 0); 366 /* We don't implement fully-associative caches */ 367 assert(cache->associativity < cache->sets); 368 *ebx = (cache->line_size - 1) | 369 ((cache->partitions - 1) << 12) | 370 ((cache->associativity - 1) << 22); 371 372 assert(cache->sets > 0); 373 *ecx = cache->sets - 1; 374 375 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) | 376 (cache->inclusive ? CACHE_INCLUSIVE : 0) | 377 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); 378 } 379 380 /* Encode cache info for CPUID[8000001E] */ 381 static void encode_topo_cpuid8000001e(X86CPU *cpu, X86CPUTopoInfo *topo_info, 382 uint32_t *eax, uint32_t *ebx, 383 uint32_t *ecx, uint32_t *edx) 384 { 385 X86CPUTopoIDs topo_ids; 386 387 x86_topo_ids_from_apicid(cpu->apic_id, topo_info, &topo_ids); 388 389 *eax = cpu->apic_id; 390 391 /* 392 * CPUID_Fn8000001E_EBX [Core Identifiers] (CoreId) 393 * Read-only. Reset: 0000_XXXXh. 394 * See Core::X86::Cpuid::ExtApicId. 395 * Core::X86::Cpuid::CoreId_lthree[1:0]_core[3:0]_thread[1:0]; 396 * Bits Description 397 * 31:16 Reserved. 398 * 15:8 ThreadsPerCore: threads per core. Read-only. Reset: XXh. 399 * The number of threads per core is ThreadsPerCore+1. 400 * 7:0 CoreId: core ID. Read-only. Reset: XXh. 401 * 402 * NOTE: CoreId is already part of apic_id. Just use it. We can 403 * use all the 8 bits to represent the core_id here. 404 */ 405 *ebx = ((topo_info->threads_per_core - 1) << 8) | (topo_ids.core_id & 0xFF); 406 407 /* 408 * CPUID_Fn8000001E_ECX [Node Identifiers] (NodeId) 409 * Read-only. Reset: 0000_0XXXh. 410 * Core::X86::Cpuid::NodeId_lthree[1:0]_core[3:0]_thread[1:0]; 411 * Bits Description 412 * 31:11 Reserved. 413 * 10:8 NodesPerProcessor: Node per processor. Read-only. Reset: XXXb. 414 * ValidValues: 415 * Value Description 416 * 000b 1 node per processor. 417 * 001b 2 nodes per processor. 418 * 010b Reserved. 419 * 011b 4 nodes per processor. 420 * 111b-100b Reserved. 421 * 7:0 NodeId: Node ID. Read-only. Reset: XXh. 422 * 423 * NOTE: Hardware reserves 3 bits for number of nodes per processor. 424 * But users can create more nodes than the actual hardware can 425 * support. To genaralize we can use all the upper 8 bits for nodes. 426 * NodeId is combination of node and socket_id which is already decoded 427 * in apic_id. Just use it by shifting. 428 */ 429 *ecx = ((topo_info->dies_per_pkg - 1) << 8) | 430 ((cpu->apic_id >> apicid_die_offset(topo_info)) & 0xFF); 431 432 *edx = 0; 433 } 434 435 /* 436 * Definitions of the hardcoded cache entries we expose: 437 * These are legacy cache values. If there is a need to change any 438 * of these values please use builtin_x86_defs 439 */ 440 441 /* L1 data cache: */ 442 static CPUCacheInfo legacy_l1d_cache = { 443 .type = DATA_CACHE, 444 .level = 1, 445 .size = 32 * KiB, 446 .self_init = 1, 447 .line_size = 64, 448 .associativity = 8, 449 .sets = 64, 450 .partitions = 1, 451 .no_invd_sharing = true, 452 }; 453 454 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ 455 static CPUCacheInfo legacy_l1d_cache_amd = { 456 .type = DATA_CACHE, 457 .level = 1, 458 .size = 64 * KiB, 459 .self_init = 1, 460 .line_size = 64, 461 .associativity = 2, 462 .sets = 512, 463 .partitions = 1, 464 .lines_per_tag = 1, 465 .no_invd_sharing = true, 466 }; 467 468 /* L1 instruction cache: */ 469 static CPUCacheInfo legacy_l1i_cache = { 470 .type = INSTRUCTION_CACHE, 471 .level = 1, 472 .size = 32 * KiB, 473 .self_init = 1, 474 .line_size = 64, 475 .associativity = 8, 476 .sets = 64, 477 .partitions = 1, 478 .no_invd_sharing = true, 479 }; 480 481 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ 482 static CPUCacheInfo legacy_l1i_cache_amd = { 483 .type = INSTRUCTION_CACHE, 484 .level = 1, 485 .size = 64 * KiB, 486 .self_init = 1, 487 .line_size = 64, 488 .associativity = 2, 489 .sets = 512, 490 .partitions = 1, 491 .lines_per_tag = 1, 492 .no_invd_sharing = true, 493 }; 494 495 /* Level 2 unified cache: */ 496 static CPUCacheInfo legacy_l2_cache = { 497 .type = UNIFIED_CACHE, 498 .level = 2, 499 .size = 4 * MiB, 500 .self_init = 1, 501 .line_size = 64, 502 .associativity = 16, 503 .sets = 4096, 504 .partitions = 1, 505 .no_invd_sharing = true, 506 }; 507 508 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */ 509 static CPUCacheInfo legacy_l2_cache_cpuid2 = { 510 .type = UNIFIED_CACHE, 511 .level = 2, 512 .size = 2 * MiB, 513 .line_size = 64, 514 .associativity = 8, 515 }; 516 517 518 /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */ 519 static CPUCacheInfo legacy_l2_cache_amd = { 520 .type = UNIFIED_CACHE, 521 .level = 2, 522 .size = 512 * KiB, 523 .line_size = 64, 524 .lines_per_tag = 1, 525 .associativity = 16, 526 .sets = 512, 527 .partitions = 1, 528 }; 529 530 /* Level 3 unified cache: */ 531 static CPUCacheInfo legacy_l3_cache = { 532 .type = UNIFIED_CACHE, 533 .level = 3, 534 .size = 16 * MiB, 535 .line_size = 64, 536 .associativity = 16, 537 .sets = 16384, 538 .partitions = 1, 539 .lines_per_tag = 1, 540 .self_init = true, 541 .inclusive = true, 542 .complex_indexing = true, 543 }; 544 545 /* TLB definitions: */ 546 547 #define L1_DTLB_2M_ASSOC 1 548 #define L1_DTLB_2M_ENTRIES 255 549 #define L1_DTLB_4K_ASSOC 1 550 #define L1_DTLB_4K_ENTRIES 255 551 552 #define L1_ITLB_2M_ASSOC 1 553 #define L1_ITLB_2M_ENTRIES 255 554 #define L1_ITLB_4K_ASSOC 1 555 #define L1_ITLB_4K_ENTRIES 255 556 557 #define L2_DTLB_2M_ASSOC 0 /* disabled */ 558 #define L2_DTLB_2M_ENTRIES 0 /* disabled */ 559 #define L2_DTLB_4K_ASSOC 4 560 #define L2_DTLB_4K_ENTRIES 512 561 562 #define L2_ITLB_2M_ASSOC 0 /* disabled */ 563 #define L2_ITLB_2M_ENTRIES 0 /* disabled */ 564 #define L2_ITLB_4K_ASSOC 4 565 #define L2_ITLB_4K_ENTRIES 512 566 567 /* CPUID Leaf 0x14 constants: */ 568 #define INTEL_PT_MAX_SUBLEAF 0x1 569 /* 570 * bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MATCH 571 * MSR can be accessed; 572 * bit[01]: Support Configurable PSB and Cycle-Accurate Mode; 573 * bit[02]: Support IP Filtering, TraceStop filtering, and preservation 574 * of Intel PT MSRs across warm reset; 575 * bit[03]: Support MTC timing packet and suppression of COFI-based packets; 576 */ 577 #define INTEL_PT_MINIMAL_EBX 0xf 578 /* 579 * bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 and 580 * IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be 581 * accessed; 582 * bit[01]: ToPA tables can hold any number of output entries, up to the 583 * maximum allowed by the MaskOrTableOffset field of 584 * IA32_RTIT_OUTPUT_MASK_PTRS; 585 * bit[02]: Support Single-Range Output scheme; 586 */ 587 #define INTEL_PT_MINIMAL_ECX 0x7 588 /* generated packets which contain IP payloads have LIP values */ 589 #define INTEL_PT_IP_LIP (1 << 31) 590 #define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */ 591 #define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3 592 #define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */ 593 #define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */ 594 #define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */ 595 596 static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1, 597 uint32_t vendor2, uint32_t vendor3) 598 { 599 int i; 600 for (i = 0; i < 4; i++) { 601 dst[i] = vendor1 >> (8 * i); 602 dst[i + 4] = vendor2 >> (8 * i); 603 dst[i + 8] = vendor3 >> (8 * i); 604 } 605 dst[CPUID_VENDOR_SZ] = '\0'; 606 } 607 608 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE) 609 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \ 610 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC) 611 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \ 612 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ 613 CPUID_PSE36 | CPUID_FXSR) 614 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE) 615 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \ 616 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \ 617 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \ 618 CPUID_PAE | CPUID_SEP | CPUID_APIC) 619 620 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \ 621 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \ 622 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ 623 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \ 624 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE) 625 /* partly implemented: 626 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */ 627 /* missing: 628 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */ 629 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \ 630 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \ 631 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \ 632 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \ 633 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR | \ 634 CPUID_EXT_RDRAND) 635 /* missing: 636 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX, 637 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA, 638 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA, 639 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_AVX, 640 CPUID_EXT_F16C */ 641 642 #ifdef TARGET_X86_64 643 #define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM) 644 #else 645 #define TCG_EXT2_X86_64_FEATURES 0 646 #endif 647 648 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \ 649 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \ 650 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \ 651 TCG_EXT2_X86_64_FEATURES) 652 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \ 653 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A) 654 #define TCG_EXT4_FEATURES 0 655 #define TCG_SVM_FEATURES CPUID_SVM_NPT 656 #define TCG_KVM_FEATURES 0 657 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \ 658 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \ 659 CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \ 660 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \ 661 CPUID_7_0_EBX_ERMS) 662 /* missing: 663 CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2, 664 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM, 665 CPUID_7_0_EBX_RDSEED */ 666 #define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_PKU | \ 667 /* CPUID_7_0_ECX_OSPKE is dynamic */ \ 668 CPUID_7_0_ECX_LA57) 669 #define TCG_7_0_EDX_FEATURES 0 670 #define TCG_7_1_EAX_FEATURES 0 671 #define TCG_APM_FEATURES 0 672 #define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT 673 #define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1) 674 /* missing: 675 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */ 676 677 typedef enum FeatureWordType { 678 CPUID_FEATURE_WORD, 679 MSR_FEATURE_WORD, 680 } FeatureWordType; 681 682 typedef struct FeatureWordInfo { 683 FeatureWordType type; 684 /* feature flags names are taken from "Intel Processor Identification and 685 * the CPUID Instruction" and AMD's "CPUID Specification". 686 * In cases of disagreement between feature naming conventions, 687 * aliases may be added. 688 */ 689 const char *feat_names[64]; 690 union { 691 /* If type==CPUID_FEATURE_WORD */ 692 struct { 693 uint32_t eax; /* Input EAX for CPUID */ 694 bool needs_ecx; /* CPUID instruction uses ECX as input */ 695 uint32_t ecx; /* Input ECX value for CPUID */ 696 int reg; /* output register (R_* constant) */ 697 } cpuid; 698 /* If type==MSR_FEATURE_WORD */ 699 struct { 700 uint32_t index; 701 } msr; 702 }; 703 uint64_t tcg_features; /* Feature flags supported by TCG */ 704 uint64_t unmigratable_flags; /* Feature flags known to be unmigratable */ 705 uint64_t migratable_flags; /* Feature flags known to be migratable */ 706 /* Features that shouldn't be auto-enabled by "-cpu host" */ 707 uint64_t no_autoenable_flags; 708 } FeatureWordInfo; 709 710 static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { 711 [FEAT_1_EDX] = { 712 .type = CPUID_FEATURE_WORD, 713 .feat_names = { 714 "fpu", "vme", "de", "pse", 715 "tsc", "msr", "pae", "mce", 716 "cx8", "apic", NULL, "sep", 717 "mtrr", "pge", "mca", "cmov", 718 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */, 719 NULL, "ds" /* Intel dts */, "acpi", "mmx", 720 "fxsr", "sse", "sse2", "ss", 721 "ht" /* Intel htt */, "tm", "ia64", "pbe", 722 }, 723 .cpuid = {.eax = 1, .reg = R_EDX, }, 724 .tcg_features = TCG_FEATURES, 725 }, 726 [FEAT_1_ECX] = { 727 .type = CPUID_FEATURE_WORD, 728 .feat_names = { 729 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor", 730 "ds-cpl", "vmx", "smx", "est", 731 "tm2", "ssse3", "cid", NULL, 732 "fma", "cx16", "xtpr", "pdcm", 733 NULL, "pcid", "dca", "sse4.1", 734 "sse4.2", "x2apic", "movbe", "popcnt", 735 "tsc-deadline", "aes", "xsave", NULL /* osxsave */, 736 "avx", "f16c", "rdrand", "hypervisor", 737 }, 738 .cpuid = { .eax = 1, .reg = R_ECX, }, 739 .tcg_features = TCG_EXT_FEATURES, 740 }, 741 /* Feature names that are already defined on feature_name[] but 742 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their 743 * names on feat_names below. They are copied automatically 744 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD. 745 */ 746 [FEAT_8000_0001_EDX] = { 747 .type = CPUID_FEATURE_WORD, 748 .feat_names = { 749 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */, 750 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */, 751 NULL /* cx8 */, NULL /* apic */, NULL, "syscall", 752 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */, 753 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */, 754 "nx", NULL, "mmxext", NULL /* mmx */, 755 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp", 756 NULL, "lm", "3dnowext", "3dnow", 757 }, 758 .cpuid = { .eax = 0x80000001, .reg = R_EDX, }, 759 .tcg_features = TCG_EXT2_FEATURES, 760 }, 761 [FEAT_8000_0001_ECX] = { 762 .type = CPUID_FEATURE_WORD, 763 .feat_names = { 764 "lahf-lm", "cmp-legacy", "svm", "extapic", 765 "cr8legacy", "abm", "sse4a", "misalignsse", 766 "3dnowprefetch", "osvw", "ibs", "xop", 767 "skinit", "wdt", NULL, "lwp", 768 "fma4", "tce", NULL, "nodeid-msr", 769 NULL, "tbm", "topoext", "perfctr-core", 770 "perfctr-nb", NULL, NULL, NULL, 771 NULL, NULL, NULL, NULL, 772 }, 773 .cpuid = { .eax = 0x80000001, .reg = R_ECX, }, 774 .tcg_features = TCG_EXT3_FEATURES, 775 /* 776 * TOPOEXT is always allowed but can't be enabled blindly by 777 * "-cpu host", as it requires consistent cache topology info 778 * to be provided so it doesn't confuse guests. 779 */ 780 .no_autoenable_flags = CPUID_EXT3_TOPOEXT, 781 }, 782 [FEAT_C000_0001_EDX] = { 783 .type = CPUID_FEATURE_WORD, 784 .feat_names = { 785 NULL, NULL, "xstore", "xstore-en", 786 NULL, NULL, "xcrypt", "xcrypt-en", 787 "ace2", "ace2-en", "phe", "phe-en", 788 "pmm", "pmm-en", NULL, NULL, 789 NULL, NULL, NULL, NULL, 790 NULL, NULL, NULL, NULL, 791 NULL, NULL, NULL, NULL, 792 NULL, NULL, NULL, NULL, 793 }, 794 .cpuid = { .eax = 0xC0000001, .reg = R_EDX, }, 795 .tcg_features = TCG_EXT4_FEATURES, 796 }, 797 [FEAT_KVM] = { 798 .type = CPUID_FEATURE_WORD, 799 .feat_names = { 800 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock", 801 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt", 802 NULL, "kvm-pv-tlb-flush", NULL, "kvm-pv-ipi", 803 "kvm-poll-control", "kvm-pv-sched-yield", "kvm-asyncpf-int", "kvm-msi-ext-dest-id", 804 NULL, NULL, NULL, NULL, 805 NULL, NULL, NULL, NULL, 806 "kvmclock-stable-bit", NULL, NULL, NULL, 807 NULL, NULL, NULL, NULL, 808 }, 809 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EAX, }, 810 .tcg_features = TCG_KVM_FEATURES, 811 }, 812 [FEAT_KVM_HINTS] = { 813 .type = CPUID_FEATURE_WORD, 814 .feat_names = { 815 "kvm-hint-dedicated", NULL, NULL, NULL, 816 NULL, NULL, NULL, NULL, 817 NULL, NULL, NULL, NULL, 818 NULL, NULL, NULL, NULL, 819 NULL, NULL, NULL, NULL, 820 NULL, NULL, NULL, NULL, 821 NULL, NULL, NULL, NULL, 822 NULL, NULL, NULL, NULL, 823 }, 824 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EDX, }, 825 .tcg_features = TCG_KVM_FEATURES, 826 /* 827 * KVM hints aren't auto-enabled by -cpu host, they need to be 828 * explicitly enabled in the command-line. 829 */ 830 .no_autoenable_flags = ~0U, 831 }, 832 /* 833 * .feat_names are commented out for Hyper-V enlightenments because we 834 * don't want to have two different ways for enabling them on QEMU command 835 * line. Some features (e.g. "hyperv_time", "hyperv_vapic", ...) require 836 * enabling several feature bits simultaneously, exposing these bits 837 * individually may just confuse guests. 838 */ 839 [FEAT_HYPERV_EAX] = { 840 .type = CPUID_FEATURE_WORD, 841 .feat_names = { 842 NULL /* hv_msr_vp_runtime_access */, NULL /* hv_msr_time_refcount_access */, 843 NULL /* hv_msr_synic_access */, NULL /* hv_msr_stimer_access */, 844 NULL /* hv_msr_apic_access */, NULL /* hv_msr_hypercall_access */, 845 NULL /* hv_vpindex_access */, NULL /* hv_msr_reset_access */, 846 NULL /* hv_msr_stats_access */, NULL /* hv_reftsc_access */, 847 NULL /* hv_msr_idle_access */, NULL /* hv_msr_frequency_access */, 848 NULL /* hv_msr_debug_access */, NULL /* hv_msr_reenlightenment_access */, 849 NULL, NULL, 850 NULL, NULL, NULL, NULL, 851 NULL, NULL, NULL, NULL, 852 NULL, NULL, NULL, NULL, 853 NULL, NULL, NULL, NULL, 854 }, 855 .cpuid = { .eax = 0x40000003, .reg = R_EAX, }, 856 }, 857 [FEAT_HYPERV_EBX] = { 858 .type = CPUID_FEATURE_WORD, 859 .feat_names = { 860 NULL /* hv_create_partitions */, NULL /* hv_access_partition_id */, 861 NULL /* hv_access_memory_pool */, NULL /* hv_adjust_message_buffers */, 862 NULL /* hv_post_messages */, NULL /* hv_signal_events */, 863 NULL /* hv_create_port */, NULL /* hv_connect_port */, 864 NULL /* hv_access_stats */, NULL, NULL, NULL /* hv_debugging */, 865 NULL /* hv_cpu_power_management */, NULL /* hv_configure_profiler */, 866 NULL, NULL, 867 NULL, NULL, NULL, NULL, 868 NULL, NULL, NULL, NULL, 869 NULL, NULL, NULL, NULL, 870 NULL, NULL, NULL, NULL, 871 }, 872 .cpuid = { .eax = 0x40000003, .reg = R_EBX, }, 873 }, 874 [FEAT_HYPERV_EDX] = { 875 .type = CPUID_FEATURE_WORD, 876 .feat_names = { 877 NULL /* hv_mwait */, NULL /* hv_guest_debugging */, 878 NULL /* hv_perf_monitor */, NULL /* hv_cpu_dynamic_part */, 879 NULL /* hv_hypercall_params_xmm */, NULL /* hv_guest_idle_state */, 880 NULL, NULL, 881 NULL, NULL, NULL /* hv_guest_crash_msr */, NULL, 882 NULL, NULL, NULL, NULL, 883 NULL, NULL, NULL, NULL, 884 NULL, NULL, NULL, NULL, 885 NULL, NULL, NULL, NULL, 886 NULL, NULL, NULL, NULL, 887 }, 888 .cpuid = { .eax = 0x40000003, .reg = R_EDX, }, 889 }, 890 [FEAT_HV_RECOMM_EAX] = { 891 .type = CPUID_FEATURE_WORD, 892 .feat_names = { 893 NULL /* hv_recommend_pv_as_switch */, 894 NULL /* hv_recommend_pv_tlbflush_local */, 895 NULL /* hv_recommend_pv_tlbflush_remote */, 896 NULL /* hv_recommend_msr_apic_access */, 897 NULL /* hv_recommend_msr_reset */, 898 NULL /* hv_recommend_relaxed_timing */, 899 NULL /* hv_recommend_dma_remapping */, 900 NULL /* hv_recommend_int_remapping */, 901 NULL /* hv_recommend_x2apic_msrs */, 902 NULL /* hv_recommend_autoeoi_deprecation */, 903 NULL /* hv_recommend_pv_ipi */, 904 NULL /* hv_recommend_ex_hypercalls */, 905 NULL /* hv_hypervisor_is_nested */, 906 NULL /* hv_recommend_int_mbec */, 907 NULL /* hv_recommend_evmcs */, 908 NULL, 909 NULL, NULL, NULL, NULL, 910 NULL, NULL, NULL, NULL, 911 NULL, NULL, NULL, NULL, 912 NULL, NULL, NULL, NULL, 913 }, 914 .cpuid = { .eax = 0x40000004, .reg = R_EAX, }, 915 }, 916 [FEAT_HV_NESTED_EAX] = { 917 .type = CPUID_FEATURE_WORD, 918 .cpuid = { .eax = 0x4000000A, .reg = R_EAX, }, 919 }, 920 [FEAT_SVM] = { 921 .type = CPUID_FEATURE_WORD, 922 .feat_names = { 923 "npt", "lbrv", "svm-lock", "nrip-save", 924 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists", 925 NULL, NULL, "pause-filter", NULL, 926 "pfthreshold", NULL, NULL, NULL, 927 NULL, NULL, NULL, NULL, 928 NULL, NULL, NULL, NULL, 929 NULL, NULL, NULL, NULL, 930 NULL, NULL, NULL, NULL, 931 }, 932 .cpuid = { .eax = 0x8000000A, .reg = R_EDX, }, 933 .tcg_features = TCG_SVM_FEATURES, 934 }, 935 [FEAT_7_0_EBX] = { 936 .type = CPUID_FEATURE_WORD, 937 .feat_names = { 938 "fsgsbase", "tsc-adjust", NULL, "bmi1", 939 "hle", "avx2", NULL, "smep", 940 "bmi2", "erms", "invpcid", "rtm", 941 NULL, NULL, "mpx", NULL, 942 "avx512f", "avx512dq", "rdseed", "adx", 943 "smap", "avx512ifma", "pcommit", "clflushopt", 944 "clwb", "intel-pt", "avx512pf", "avx512er", 945 "avx512cd", "sha-ni", "avx512bw", "avx512vl", 946 }, 947 .cpuid = { 948 .eax = 7, 949 .needs_ecx = true, .ecx = 0, 950 .reg = R_EBX, 951 }, 952 .tcg_features = TCG_7_0_EBX_FEATURES, 953 }, 954 [FEAT_7_0_ECX] = { 955 .type = CPUID_FEATURE_WORD, 956 .feat_names = { 957 NULL, "avx512vbmi", "umip", "pku", 958 NULL /* ospke */, "waitpkg", "avx512vbmi2", NULL, 959 "gfni", "vaes", "vpclmulqdq", "avx512vnni", 960 "avx512bitalg", NULL, "avx512-vpopcntdq", NULL, 961 "la57", NULL, NULL, NULL, 962 NULL, NULL, "rdpid", NULL, 963 NULL, "cldemote", NULL, "movdiri", 964 "movdir64b", NULL, NULL, NULL, 965 }, 966 .cpuid = { 967 .eax = 7, 968 .needs_ecx = true, .ecx = 0, 969 .reg = R_ECX, 970 }, 971 .tcg_features = TCG_7_0_ECX_FEATURES, 972 }, 973 [FEAT_7_0_EDX] = { 974 .type = CPUID_FEATURE_WORD, 975 .feat_names = { 976 NULL, NULL, "avx512-4vnniw", "avx512-4fmaps", 977 "fsrm", NULL, NULL, NULL, 978 "avx512-vp2intersect", NULL, "md-clear", NULL, 979 NULL, NULL, "serialize", NULL, 980 "tsx-ldtrk", NULL, NULL /* pconfig */, NULL, 981 NULL, NULL, NULL, NULL, 982 NULL, NULL, "spec-ctrl", "stibp", 983 NULL, "arch-capabilities", "core-capability", "ssbd", 984 }, 985 .cpuid = { 986 .eax = 7, 987 .needs_ecx = true, .ecx = 0, 988 .reg = R_EDX, 989 }, 990 .tcg_features = TCG_7_0_EDX_FEATURES, 991 }, 992 [FEAT_7_1_EAX] = { 993 .type = CPUID_FEATURE_WORD, 994 .feat_names = { 995 NULL, NULL, NULL, NULL, 996 NULL, "avx512-bf16", NULL, NULL, 997 NULL, NULL, NULL, NULL, 998 NULL, NULL, NULL, NULL, 999 NULL, NULL, NULL, NULL, 1000 NULL, NULL, NULL, NULL, 1001 NULL, NULL, NULL, NULL, 1002 NULL, NULL, NULL, NULL, 1003 }, 1004 .cpuid = { 1005 .eax = 7, 1006 .needs_ecx = true, .ecx = 1, 1007 .reg = R_EAX, 1008 }, 1009 .tcg_features = TCG_7_1_EAX_FEATURES, 1010 }, 1011 [FEAT_8000_0007_EDX] = { 1012 .type = CPUID_FEATURE_WORD, 1013 .feat_names = { 1014 NULL, NULL, NULL, NULL, 1015 NULL, NULL, NULL, NULL, 1016 "invtsc", NULL, NULL, NULL, 1017 NULL, NULL, NULL, NULL, 1018 NULL, NULL, NULL, NULL, 1019 NULL, NULL, NULL, NULL, 1020 NULL, NULL, NULL, NULL, 1021 NULL, NULL, NULL, NULL, 1022 }, 1023 .cpuid = { .eax = 0x80000007, .reg = R_EDX, }, 1024 .tcg_features = TCG_APM_FEATURES, 1025 .unmigratable_flags = CPUID_APM_INVTSC, 1026 }, 1027 [FEAT_8000_0008_EBX] = { 1028 .type = CPUID_FEATURE_WORD, 1029 .feat_names = { 1030 "clzero", NULL, "xsaveerptr", NULL, 1031 NULL, NULL, NULL, NULL, 1032 NULL, "wbnoinvd", NULL, NULL, 1033 "ibpb", NULL, NULL, "amd-stibp", 1034 NULL, NULL, NULL, NULL, 1035 NULL, NULL, NULL, NULL, 1036 "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL, 1037 NULL, NULL, NULL, NULL, 1038 }, 1039 .cpuid = { .eax = 0x80000008, .reg = R_EBX, }, 1040 .tcg_features = 0, 1041 .unmigratable_flags = 0, 1042 }, 1043 [FEAT_XSAVE] = { 1044 .type = CPUID_FEATURE_WORD, 1045 .feat_names = { 1046 "xsaveopt", "xsavec", "xgetbv1", "xsaves", 1047 NULL, NULL, NULL, NULL, 1048 NULL, NULL, NULL, NULL, 1049 NULL, NULL, NULL, NULL, 1050 NULL, NULL, NULL, NULL, 1051 NULL, NULL, NULL, NULL, 1052 NULL, NULL, NULL, NULL, 1053 NULL, NULL, NULL, NULL, 1054 }, 1055 .cpuid = { 1056 .eax = 0xd, 1057 .needs_ecx = true, .ecx = 1, 1058 .reg = R_EAX, 1059 }, 1060 .tcg_features = TCG_XSAVE_FEATURES, 1061 }, 1062 [FEAT_6_EAX] = { 1063 .type = CPUID_FEATURE_WORD, 1064 .feat_names = { 1065 NULL, NULL, "arat", NULL, 1066 NULL, NULL, NULL, NULL, 1067 NULL, NULL, NULL, NULL, 1068 NULL, NULL, NULL, NULL, 1069 NULL, NULL, NULL, NULL, 1070 NULL, NULL, NULL, NULL, 1071 NULL, NULL, NULL, NULL, 1072 NULL, NULL, NULL, NULL, 1073 }, 1074 .cpuid = { .eax = 6, .reg = R_EAX, }, 1075 .tcg_features = TCG_6_EAX_FEATURES, 1076 }, 1077 [FEAT_XSAVE_COMP_LO] = { 1078 .type = CPUID_FEATURE_WORD, 1079 .cpuid = { 1080 .eax = 0xD, 1081 .needs_ecx = true, .ecx = 0, 1082 .reg = R_EAX, 1083 }, 1084 .tcg_features = ~0U, 1085 .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK | 1086 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK | 1087 XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK | 1088 XSTATE_PKRU_MASK, 1089 }, 1090 [FEAT_XSAVE_COMP_HI] = { 1091 .type = CPUID_FEATURE_WORD, 1092 .cpuid = { 1093 .eax = 0xD, 1094 .needs_ecx = true, .ecx = 0, 1095 .reg = R_EDX, 1096 }, 1097 .tcg_features = ~0U, 1098 }, 1099 /*Below are MSR exposed features*/ 1100 [FEAT_ARCH_CAPABILITIES] = { 1101 .type = MSR_FEATURE_WORD, 1102 .feat_names = { 1103 "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry", 1104 "ssb-no", "mds-no", "pschange-mc-no", "tsx-ctrl", 1105 "taa-no", NULL, NULL, NULL, 1106 NULL, NULL, NULL, NULL, 1107 NULL, NULL, NULL, NULL, 1108 NULL, NULL, NULL, NULL, 1109 NULL, NULL, NULL, NULL, 1110 NULL, NULL, NULL, NULL, 1111 }, 1112 .msr = { 1113 .index = MSR_IA32_ARCH_CAPABILITIES, 1114 }, 1115 }, 1116 [FEAT_CORE_CAPABILITY] = { 1117 .type = MSR_FEATURE_WORD, 1118 .feat_names = { 1119 NULL, NULL, NULL, NULL, 1120 NULL, "split-lock-detect", NULL, NULL, 1121 NULL, NULL, NULL, NULL, 1122 NULL, NULL, NULL, NULL, 1123 NULL, NULL, NULL, NULL, 1124 NULL, NULL, NULL, NULL, 1125 NULL, NULL, NULL, NULL, 1126 NULL, NULL, NULL, NULL, 1127 }, 1128 .msr = { 1129 .index = MSR_IA32_CORE_CAPABILITY, 1130 }, 1131 }, 1132 [FEAT_PERF_CAPABILITIES] = { 1133 .type = MSR_FEATURE_WORD, 1134 .feat_names = { 1135 NULL, NULL, NULL, NULL, 1136 NULL, NULL, NULL, NULL, 1137 NULL, NULL, NULL, NULL, 1138 NULL, "full-width-write", NULL, NULL, 1139 NULL, NULL, NULL, NULL, 1140 NULL, NULL, NULL, NULL, 1141 NULL, NULL, NULL, NULL, 1142 NULL, NULL, NULL, NULL, 1143 }, 1144 .msr = { 1145 .index = MSR_IA32_PERF_CAPABILITIES, 1146 }, 1147 }, 1148 1149 [FEAT_VMX_PROCBASED_CTLS] = { 1150 .type = MSR_FEATURE_WORD, 1151 .feat_names = { 1152 NULL, NULL, "vmx-vintr-pending", "vmx-tsc-offset", 1153 NULL, NULL, NULL, "vmx-hlt-exit", 1154 NULL, "vmx-invlpg-exit", "vmx-mwait-exit", "vmx-rdpmc-exit", 1155 "vmx-rdtsc-exit", NULL, NULL, "vmx-cr3-load-noexit", 1156 "vmx-cr3-store-noexit", NULL, NULL, "vmx-cr8-load-exit", 1157 "vmx-cr8-store-exit", "vmx-flexpriority", "vmx-vnmi-pending", "vmx-movdr-exit", 1158 "vmx-io-exit", "vmx-io-bitmap", NULL, "vmx-mtf", 1159 "vmx-msr-bitmap", "vmx-monitor-exit", "vmx-pause-exit", "vmx-secondary-ctls", 1160 }, 1161 .msr = { 1162 .index = MSR_IA32_VMX_TRUE_PROCBASED_CTLS, 1163 } 1164 }, 1165 1166 [FEAT_VMX_SECONDARY_CTLS] = { 1167 .type = MSR_FEATURE_WORD, 1168 .feat_names = { 1169 "vmx-apicv-xapic", "vmx-ept", "vmx-desc-exit", "vmx-rdtscp-exit", 1170 "vmx-apicv-x2apic", "vmx-vpid", "vmx-wbinvd-exit", "vmx-unrestricted-guest", 1171 "vmx-apicv-register", "vmx-apicv-vid", "vmx-ple", "vmx-rdrand-exit", 1172 "vmx-invpcid-exit", "vmx-vmfunc", "vmx-shadow-vmcs", "vmx-encls-exit", 1173 "vmx-rdseed-exit", "vmx-pml", NULL, NULL, 1174 "vmx-xsaves", NULL, NULL, NULL, 1175 NULL, NULL, NULL, NULL, 1176 NULL, NULL, NULL, NULL, 1177 }, 1178 .msr = { 1179 .index = MSR_IA32_VMX_PROCBASED_CTLS2, 1180 } 1181 }, 1182 1183 [FEAT_VMX_PINBASED_CTLS] = { 1184 .type = MSR_FEATURE_WORD, 1185 .feat_names = { 1186 "vmx-intr-exit", NULL, NULL, "vmx-nmi-exit", 1187 NULL, "vmx-vnmi", "vmx-preemption-timer", "vmx-posted-intr", 1188 NULL, NULL, NULL, NULL, 1189 NULL, NULL, NULL, NULL, 1190 NULL, NULL, NULL, NULL, 1191 NULL, NULL, NULL, NULL, 1192 NULL, NULL, NULL, NULL, 1193 NULL, NULL, NULL, NULL, 1194 }, 1195 .msr = { 1196 .index = MSR_IA32_VMX_TRUE_PINBASED_CTLS, 1197 } 1198 }, 1199 1200 [FEAT_VMX_EXIT_CTLS] = { 1201 .type = MSR_FEATURE_WORD, 1202 /* 1203 * VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE is copied from 1204 * the LM CPUID bit. 1205 */ 1206 .feat_names = { 1207 NULL, NULL, "vmx-exit-nosave-debugctl", NULL, 1208 NULL, NULL, NULL, NULL, 1209 NULL, NULL /* vmx-exit-host-addr-space-size */, NULL, NULL, 1210 "vmx-exit-load-perf-global-ctrl", NULL, NULL, "vmx-exit-ack-intr", 1211 NULL, NULL, "vmx-exit-save-pat", "vmx-exit-load-pat", 1212 "vmx-exit-save-efer", "vmx-exit-load-efer", 1213 "vmx-exit-save-preemption-timer", "vmx-exit-clear-bndcfgs", 1214 NULL, "vmx-exit-clear-rtit-ctl", NULL, NULL, 1215 NULL, NULL, NULL, NULL, 1216 }, 1217 .msr = { 1218 .index = MSR_IA32_VMX_TRUE_EXIT_CTLS, 1219 } 1220 }, 1221 1222 [FEAT_VMX_ENTRY_CTLS] = { 1223 .type = MSR_FEATURE_WORD, 1224 .feat_names = { 1225 NULL, NULL, "vmx-entry-noload-debugctl", NULL, 1226 NULL, NULL, NULL, NULL, 1227 NULL, "vmx-entry-ia32e-mode", NULL, NULL, 1228 NULL, "vmx-entry-load-perf-global-ctrl", "vmx-entry-load-pat", "vmx-entry-load-efer", 1229 "vmx-entry-load-bndcfgs", NULL, "vmx-entry-load-rtit-ctl", NULL, 1230 NULL, NULL, NULL, NULL, 1231 NULL, NULL, NULL, NULL, 1232 NULL, NULL, NULL, NULL, 1233 }, 1234 .msr = { 1235 .index = MSR_IA32_VMX_TRUE_ENTRY_CTLS, 1236 } 1237 }, 1238 1239 [FEAT_VMX_MISC] = { 1240 .type = MSR_FEATURE_WORD, 1241 .feat_names = { 1242 NULL, NULL, NULL, NULL, 1243 NULL, "vmx-store-lma", "vmx-activity-hlt", "vmx-activity-shutdown", 1244 "vmx-activity-wait-sipi", NULL, NULL, NULL, 1245 NULL, NULL, NULL, NULL, 1246 NULL, NULL, NULL, NULL, 1247 NULL, NULL, NULL, NULL, 1248 NULL, NULL, NULL, NULL, 1249 NULL, "vmx-vmwrite-vmexit-fields", "vmx-zero-len-inject", NULL, 1250 }, 1251 .msr = { 1252 .index = MSR_IA32_VMX_MISC, 1253 } 1254 }, 1255 1256 [FEAT_VMX_EPT_VPID_CAPS] = { 1257 .type = MSR_FEATURE_WORD, 1258 .feat_names = { 1259 "vmx-ept-execonly", NULL, NULL, NULL, 1260 NULL, NULL, "vmx-page-walk-4", "vmx-page-walk-5", 1261 NULL, NULL, NULL, NULL, 1262 NULL, NULL, NULL, NULL, 1263 "vmx-ept-2mb", "vmx-ept-1gb", NULL, NULL, 1264 "vmx-invept", "vmx-eptad", "vmx-ept-advanced-exitinfo", NULL, 1265 NULL, "vmx-invept-single-context", "vmx-invept-all-context", NULL, 1266 NULL, NULL, NULL, NULL, 1267 "vmx-invvpid", NULL, NULL, NULL, 1268 NULL, NULL, NULL, NULL, 1269 "vmx-invvpid-single-addr", "vmx-invept-single-context", 1270 "vmx-invvpid-all-context", "vmx-invept-single-context-noglobals", 1271 NULL, NULL, NULL, NULL, 1272 NULL, NULL, NULL, NULL, 1273 NULL, NULL, NULL, NULL, 1274 NULL, NULL, NULL, NULL, 1275 NULL, NULL, NULL, NULL, 1276 }, 1277 .msr = { 1278 .index = MSR_IA32_VMX_EPT_VPID_CAP, 1279 } 1280 }, 1281 1282 [FEAT_VMX_BASIC] = { 1283 .type = MSR_FEATURE_WORD, 1284 .feat_names = { 1285 [54] = "vmx-ins-outs", 1286 [55] = "vmx-true-ctls", 1287 }, 1288 .msr = { 1289 .index = MSR_IA32_VMX_BASIC, 1290 }, 1291 /* Just to be safe - we don't support setting the MSEG version field. */ 1292 .no_autoenable_flags = MSR_VMX_BASIC_DUAL_MONITOR, 1293 }, 1294 1295 [FEAT_VMX_VMFUNC] = { 1296 .type = MSR_FEATURE_WORD, 1297 .feat_names = { 1298 [0] = "vmx-eptp-switching", 1299 }, 1300 .msr = { 1301 .index = MSR_IA32_VMX_VMFUNC, 1302 } 1303 }, 1304 1305 }; 1306 1307 typedef struct FeatureMask { 1308 FeatureWord index; 1309 uint64_t mask; 1310 } FeatureMask; 1311 1312 typedef struct FeatureDep { 1313 FeatureMask from, to; 1314 } FeatureDep; 1315 1316 static FeatureDep feature_dependencies[] = { 1317 { 1318 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_ARCH_CAPABILITIES }, 1319 .to = { FEAT_ARCH_CAPABILITIES, ~0ull }, 1320 }, 1321 { 1322 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_CORE_CAPABILITY }, 1323 .to = { FEAT_CORE_CAPABILITY, ~0ull }, 1324 }, 1325 { 1326 .from = { FEAT_1_ECX, CPUID_EXT_PDCM }, 1327 .to = { FEAT_PERF_CAPABILITIES, ~0ull }, 1328 }, 1329 { 1330 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1331 .to = { FEAT_VMX_PROCBASED_CTLS, ~0ull }, 1332 }, 1333 { 1334 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1335 .to = { FEAT_VMX_PINBASED_CTLS, ~0ull }, 1336 }, 1337 { 1338 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1339 .to = { FEAT_VMX_EXIT_CTLS, ~0ull }, 1340 }, 1341 { 1342 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1343 .to = { FEAT_VMX_ENTRY_CTLS, ~0ull }, 1344 }, 1345 { 1346 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1347 .to = { FEAT_VMX_MISC, ~0ull }, 1348 }, 1349 { 1350 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1351 .to = { FEAT_VMX_BASIC, ~0ull }, 1352 }, 1353 { 1354 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_LM }, 1355 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_IA32E_MODE }, 1356 }, 1357 { 1358 .from = { FEAT_VMX_PROCBASED_CTLS, VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS }, 1359 .to = { FEAT_VMX_SECONDARY_CTLS, ~0ull }, 1360 }, 1361 { 1362 .from = { FEAT_XSAVE, CPUID_XSAVE_XSAVES }, 1363 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_XSAVES }, 1364 }, 1365 { 1366 .from = { FEAT_1_ECX, CPUID_EXT_RDRAND }, 1367 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDRAND_EXITING }, 1368 }, 1369 { 1370 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INVPCID }, 1371 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_INVPCID }, 1372 }, 1373 { 1374 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_RDSEED }, 1375 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDSEED_EXITING }, 1376 }, 1377 { 1378 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_RDTSCP }, 1379 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDTSCP }, 1380 }, 1381 { 1382 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT }, 1383 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull }, 1384 }, 1385 { 1386 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT }, 1387 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST }, 1388 }, 1389 { 1390 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VPID }, 1391 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull << 32 }, 1392 }, 1393 { 1394 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VMFUNC }, 1395 .to = { FEAT_VMX_VMFUNC, ~0ull }, 1396 }, 1397 { 1398 .from = { FEAT_8000_0001_ECX, CPUID_EXT3_SVM }, 1399 .to = { FEAT_SVM, ~0ull }, 1400 }, 1401 }; 1402 1403 typedef struct X86RegisterInfo32 { 1404 /* Name of register */ 1405 const char *name; 1406 /* QAPI enum value register */ 1407 X86CPURegister32 qapi_enum; 1408 } X86RegisterInfo32; 1409 1410 #define REGISTER(reg) \ 1411 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg } 1412 static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = { 1413 REGISTER(EAX), 1414 REGISTER(ECX), 1415 REGISTER(EDX), 1416 REGISTER(EBX), 1417 REGISTER(ESP), 1418 REGISTER(EBP), 1419 REGISTER(ESI), 1420 REGISTER(EDI), 1421 }; 1422 #undef REGISTER 1423 1424 typedef struct ExtSaveArea { 1425 uint32_t feature, bits; 1426 uint32_t offset, size; 1427 } ExtSaveArea; 1428 1429 static const ExtSaveArea x86_ext_save_areas[] = { 1430 [XSTATE_FP_BIT] = { 1431 /* x87 FP state component is always enabled if XSAVE is supported */ 1432 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE, 1433 /* x87 state is in the legacy region of the XSAVE area */ 1434 .offset = 0, 1435 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader), 1436 }, 1437 [XSTATE_SSE_BIT] = { 1438 /* SSE state component is always enabled if XSAVE is supported */ 1439 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE, 1440 /* SSE state is in the legacy region of the XSAVE area */ 1441 .offset = 0, 1442 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader), 1443 }, 1444 [XSTATE_YMM_BIT] = 1445 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX, 1446 .offset = offsetof(X86XSaveArea, avx_state), 1447 .size = sizeof(XSaveAVX) }, 1448 [XSTATE_BNDREGS_BIT] = 1449 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX, 1450 .offset = offsetof(X86XSaveArea, bndreg_state), 1451 .size = sizeof(XSaveBNDREG) }, 1452 [XSTATE_BNDCSR_BIT] = 1453 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX, 1454 .offset = offsetof(X86XSaveArea, bndcsr_state), 1455 .size = sizeof(XSaveBNDCSR) }, 1456 [XSTATE_OPMASK_BIT] = 1457 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1458 .offset = offsetof(X86XSaveArea, opmask_state), 1459 .size = sizeof(XSaveOpmask) }, 1460 [XSTATE_ZMM_Hi256_BIT] = 1461 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1462 .offset = offsetof(X86XSaveArea, zmm_hi256_state), 1463 .size = sizeof(XSaveZMM_Hi256) }, 1464 [XSTATE_Hi16_ZMM_BIT] = 1465 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1466 .offset = offsetof(X86XSaveArea, hi16_zmm_state), 1467 .size = sizeof(XSaveHi16_ZMM) }, 1468 [XSTATE_PKRU_BIT] = 1469 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU, 1470 .offset = offsetof(X86XSaveArea, pkru_state), 1471 .size = sizeof(XSavePKRU) }, 1472 }; 1473 1474 static uint32_t xsave_area_size(uint64_t mask) 1475 { 1476 int i; 1477 uint64_t ret = 0; 1478 1479 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 1480 const ExtSaveArea *esa = &x86_ext_save_areas[i]; 1481 if ((mask >> i) & 1) { 1482 ret = MAX(ret, esa->offset + esa->size); 1483 } 1484 } 1485 return ret; 1486 } 1487 1488 static inline bool accel_uses_host_cpuid(void) 1489 { 1490 return kvm_enabled() || hvf_enabled(); 1491 } 1492 1493 static inline uint64_t x86_cpu_xsave_components(X86CPU *cpu) 1494 { 1495 return ((uint64_t)cpu->env.features[FEAT_XSAVE_COMP_HI]) << 32 | 1496 cpu->env.features[FEAT_XSAVE_COMP_LO]; 1497 } 1498 1499 const char *get_register_name_32(unsigned int reg) 1500 { 1501 if (reg >= CPU_NB_REGS32) { 1502 return NULL; 1503 } 1504 return x86_reg_info_32[reg].name; 1505 } 1506 1507 /* 1508 * Returns the set of feature flags that are supported and migratable by 1509 * QEMU, for a given FeatureWord. 1510 */ 1511 static uint64_t x86_cpu_get_migratable_flags(FeatureWord w) 1512 { 1513 FeatureWordInfo *wi = &feature_word_info[w]; 1514 uint64_t r = 0; 1515 int i; 1516 1517 for (i = 0; i < 64; i++) { 1518 uint64_t f = 1ULL << i; 1519 1520 /* If the feature name is known, it is implicitly considered migratable, 1521 * unless it is explicitly set in unmigratable_flags */ 1522 if ((wi->migratable_flags & f) || 1523 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) { 1524 r |= f; 1525 } 1526 } 1527 return r; 1528 } 1529 1530 void host_cpuid(uint32_t function, uint32_t count, 1531 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) 1532 { 1533 uint32_t vec[4]; 1534 1535 #ifdef __x86_64__ 1536 asm volatile("cpuid" 1537 : "=a"(vec[0]), "=b"(vec[1]), 1538 "=c"(vec[2]), "=d"(vec[3]) 1539 : "0"(function), "c"(count) : "cc"); 1540 #elif defined(__i386__) 1541 asm volatile("pusha \n\t" 1542 "cpuid \n\t" 1543 "mov %%eax, 0(%2) \n\t" 1544 "mov %%ebx, 4(%2) \n\t" 1545 "mov %%ecx, 8(%2) \n\t" 1546 "mov %%edx, 12(%2) \n\t" 1547 "popa" 1548 : : "a"(function), "c"(count), "S"(vec) 1549 : "memory", "cc"); 1550 #else 1551 abort(); 1552 #endif 1553 1554 if (eax) 1555 *eax = vec[0]; 1556 if (ebx) 1557 *ebx = vec[1]; 1558 if (ecx) 1559 *ecx = vec[2]; 1560 if (edx) 1561 *edx = vec[3]; 1562 } 1563 1564 void host_vendor_fms(char *vendor, int *family, int *model, int *stepping) 1565 { 1566 uint32_t eax, ebx, ecx, edx; 1567 1568 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx); 1569 x86_cpu_vendor_words2str(vendor, ebx, edx, ecx); 1570 1571 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx); 1572 if (family) { 1573 *family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF); 1574 } 1575 if (model) { 1576 *model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12); 1577 } 1578 if (stepping) { 1579 *stepping = eax & 0x0F; 1580 } 1581 } 1582 1583 /* CPU class name definitions: */ 1584 1585 /* Return type name for a given CPU model name 1586 * Caller is responsible for freeing the returned string. 1587 */ 1588 static char *x86_cpu_type_name(const char *model_name) 1589 { 1590 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name); 1591 } 1592 1593 static ObjectClass *x86_cpu_class_by_name(const char *cpu_model) 1594 { 1595 g_autofree char *typename = x86_cpu_type_name(cpu_model); 1596 return object_class_by_name(typename); 1597 } 1598 1599 static char *x86_cpu_class_get_model_name(X86CPUClass *cc) 1600 { 1601 const char *class_name = object_class_get_name(OBJECT_CLASS(cc)); 1602 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX)); 1603 return g_strndup(class_name, 1604 strlen(class_name) - strlen(X86_CPU_TYPE_SUFFIX)); 1605 } 1606 1607 typedef struct PropValue { 1608 const char *prop, *value; 1609 } PropValue; 1610 1611 typedef struct X86CPUVersionDefinition { 1612 X86CPUVersion version; 1613 const char *alias; 1614 const char *note; 1615 PropValue *props; 1616 } X86CPUVersionDefinition; 1617 1618 /* Base definition for a CPU model */ 1619 typedef struct X86CPUDefinition { 1620 const char *name; 1621 uint32_t level; 1622 uint32_t xlevel; 1623 /* vendor is zero-terminated, 12 character ASCII string */ 1624 char vendor[CPUID_VENDOR_SZ + 1]; 1625 int family; 1626 int model; 1627 int stepping; 1628 FeatureWordArray features; 1629 const char *model_id; 1630 CPUCaches *cache_info; 1631 /* 1632 * Definitions for alternative versions of CPU model. 1633 * List is terminated by item with version == 0. 1634 * If NULL, version 1 will be registered automatically. 1635 */ 1636 const X86CPUVersionDefinition *versions; 1637 const char *deprecation_note; 1638 } X86CPUDefinition; 1639 1640 /* Reference to a specific CPU model version */ 1641 struct X86CPUModel { 1642 /* Base CPU definition */ 1643 X86CPUDefinition *cpudef; 1644 /* CPU model version */ 1645 X86CPUVersion version; 1646 const char *note; 1647 /* 1648 * If true, this is an alias CPU model. 1649 * This matters only for "-cpu help" and query-cpu-definitions 1650 */ 1651 bool is_alias; 1652 }; 1653 1654 /* Get full model name for CPU version */ 1655 static char *x86_cpu_versioned_model_name(X86CPUDefinition *cpudef, 1656 X86CPUVersion version) 1657 { 1658 assert(version > 0); 1659 return g_strdup_printf("%s-v%d", cpudef->name, (int)version); 1660 } 1661 1662 static const X86CPUVersionDefinition *x86_cpu_def_get_versions(X86CPUDefinition *def) 1663 { 1664 /* When X86CPUDefinition::versions is NULL, we register only v1 */ 1665 static const X86CPUVersionDefinition default_version_list[] = { 1666 { 1 }, 1667 { /* end of list */ } 1668 }; 1669 1670 return def->versions ?: default_version_list; 1671 } 1672 1673 static CPUCaches epyc_cache_info = { 1674 .l1d_cache = &(CPUCacheInfo) { 1675 .type = DATA_CACHE, 1676 .level = 1, 1677 .size = 32 * KiB, 1678 .line_size = 64, 1679 .associativity = 8, 1680 .partitions = 1, 1681 .sets = 64, 1682 .lines_per_tag = 1, 1683 .self_init = 1, 1684 .no_invd_sharing = true, 1685 }, 1686 .l1i_cache = &(CPUCacheInfo) { 1687 .type = INSTRUCTION_CACHE, 1688 .level = 1, 1689 .size = 64 * KiB, 1690 .line_size = 64, 1691 .associativity = 4, 1692 .partitions = 1, 1693 .sets = 256, 1694 .lines_per_tag = 1, 1695 .self_init = 1, 1696 .no_invd_sharing = true, 1697 }, 1698 .l2_cache = &(CPUCacheInfo) { 1699 .type = UNIFIED_CACHE, 1700 .level = 2, 1701 .size = 512 * KiB, 1702 .line_size = 64, 1703 .associativity = 8, 1704 .partitions = 1, 1705 .sets = 1024, 1706 .lines_per_tag = 1, 1707 }, 1708 .l3_cache = &(CPUCacheInfo) { 1709 .type = UNIFIED_CACHE, 1710 .level = 3, 1711 .size = 8 * MiB, 1712 .line_size = 64, 1713 .associativity = 16, 1714 .partitions = 1, 1715 .sets = 8192, 1716 .lines_per_tag = 1, 1717 .self_init = true, 1718 .inclusive = true, 1719 .complex_indexing = true, 1720 }, 1721 }; 1722 1723 static CPUCaches epyc_rome_cache_info = { 1724 .l1d_cache = &(CPUCacheInfo) { 1725 .type = DATA_CACHE, 1726 .level = 1, 1727 .size = 32 * KiB, 1728 .line_size = 64, 1729 .associativity = 8, 1730 .partitions = 1, 1731 .sets = 64, 1732 .lines_per_tag = 1, 1733 .self_init = 1, 1734 .no_invd_sharing = true, 1735 }, 1736 .l1i_cache = &(CPUCacheInfo) { 1737 .type = INSTRUCTION_CACHE, 1738 .level = 1, 1739 .size = 32 * KiB, 1740 .line_size = 64, 1741 .associativity = 8, 1742 .partitions = 1, 1743 .sets = 64, 1744 .lines_per_tag = 1, 1745 .self_init = 1, 1746 .no_invd_sharing = true, 1747 }, 1748 .l2_cache = &(CPUCacheInfo) { 1749 .type = UNIFIED_CACHE, 1750 .level = 2, 1751 .size = 512 * KiB, 1752 .line_size = 64, 1753 .associativity = 8, 1754 .partitions = 1, 1755 .sets = 1024, 1756 .lines_per_tag = 1, 1757 }, 1758 .l3_cache = &(CPUCacheInfo) { 1759 .type = UNIFIED_CACHE, 1760 .level = 3, 1761 .size = 16 * MiB, 1762 .line_size = 64, 1763 .associativity = 16, 1764 .partitions = 1, 1765 .sets = 16384, 1766 .lines_per_tag = 1, 1767 .self_init = true, 1768 .inclusive = true, 1769 .complex_indexing = true, 1770 }, 1771 }; 1772 1773 /* The following VMX features are not supported by KVM and are left out in the 1774 * CPU definitions: 1775 * 1776 * Dual-monitor support (all processors) 1777 * Entry to SMM 1778 * Deactivate dual-monitor treatment 1779 * Number of CR3-target values 1780 * Shutdown activity state 1781 * Wait-for-SIPI activity state 1782 * PAUSE-loop exiting (Westmere and newer) 1783 * EPT-violation #VE (Broadwell and newer) 1784 * Inject event with insn length=0 (Skylake and newer) 1785 * Conceal non-root operation from PT 1786 * Conceal VM exits from PT 1787 * Conceal VM entries from PT 1788 * Enable ENCLS exiting 1789 * Mode-based execute control (XS/XU) 1790 s TSC scaling (Skylake Server and newer) 1791 * GPA translation for PT (IceLake and newer) 1792 * User wait and pause 1793 * ENCLV exiting 1794 * Load IA32_RTIT_CTL 1795 * Clear IA32_RTIT_CTL 1796 * Advanced VM-exit information for EPT violations 1797 * Sub-page write permissions 1798 * PT in VMX operation 1799 */ 1800 1801 static X86CPUDefinition builtin_x86_defs[] = { 1802 { 1803 .name = "qemu64", 1804 .level = 0xd, 1805 .vendor = CPUID_VENDOR_AMD, 1806 .family = 6, 1807 .model = 6, 1808 .stepping = 3, 1809 .features[FEAT_1_EDX] = 1810 PPRO_FEATURES | 1811 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 1812 CPUID_PSE36, 1813 .features[FEAT_1_ECX] = 1814 CPUID_EXT_SSE3 | CPUID_EXT_CX16, 1815 .features[FEAT_8000_0001_EDX] = 1816 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 1817 .features[FEAT_8000_0001_ECX] = 1818 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM, 1819 .xlevel = 0x8000000A, 1820 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 1821 }, 1822 { 1823 .name = "phenom", 1824 .level = 5, 1825 .vendor = CPUID_VENDOR_AMD, 1826 .family = 16, 1827 .model = 2, 1828 .stepping = 3, 1829 /* Missing: CPUID_HT */ 1830 .features[FEAT_1_EDX] = 1831 PPRO_FEATURES | 1832 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 1833 CPUID_PSE36 | CPUID_VME, 1834 .features[FEAT_1_ECX] = 1835 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 | 1836 CPUID_EXT_POPCNT, 1837 .features[FEAT_8000_0001_EDX] = 1838 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | 1839 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT | 1840 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP, 1841 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, 1842 CPUID_EXT3_CR8LEG, 1843 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, 1844 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */ 1845 .features[FEAT_8000_0001_ECX] = 1846 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | 1847 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A, 1848 /* Missing: CPUID_SVM_LBRV */ 1849 .features[FEAT_SVM] = 1850 CPUID_SVM_NPT, 1851 .xlevel = 0x8000001A, 1852 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor" 1853 }, 1854 { 1855 .name = "core2duo", 1856 .level = 10, 1857 .vendor = CPUID_VENDOR_INTEL, 1858 .family = 6, 1859 .model = 15, 1860 .stepping = 11, 1861 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 1862 .features[FEAT_1_EDX] = 1863 PPRO_FEATURES | 1864 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 1865 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS, 1866 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST, 1867 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */ 1868 .features[FEAT_1_ECX] = 1869 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | 1870 CPUID_EXT_CX16, 1871 .features[FEAT_8000_0001_EDX] = 1872 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 1873 .features[FEAT_8000_0001_ECX] = 1874 CPUID_EXT3_LAHF_LM, 1875 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 1876 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 1877 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 1878 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 1879 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 1880 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 1881 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 1882 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 1883 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 1884 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 1885 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 1886 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 1887 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 1888 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 1889 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 1890 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 1891 .features[FEAT_VMX_SECONDARY_CTLS] = 1892 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES, 1893 .xlevel = 0x80000008, 1894 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz", 1895 }, 1896 { 1897 .name = "kvm64", 1898 .level = 0xd, 1899 .vendor = CPUID_VENDOR_INTEL, 1900 .family = 15, 1901 .model = 6, 1902 .stepping = 1, 1903 /* Missing: CPUID_HT */ 1904 .features[FEAT_1_EDX] = 1905 PPRO_FEATURES | CPUID_VME | 1906 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 1907 CPUID_PSE36, 1908 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */ 1909 .features[FEAT_1_ECX] = 1910 CPUID_EXT_SSE3 | CPUID_EXT_CX16, 1911 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */ 1912 .features[FEAT_8000_0001_EDX] = 1913 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 1914 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, 1915 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A, 1916 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, 1917 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */ 1918 .features[FEAT_8000_0001_ECX] = 1919 0, 1920 /* VMX features from Cedar Mill/Prescott */ 1921 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 1922 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 1923 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 1924 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 1925 VMX_PIN_BASED_NMI_EXITING, 1926 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 1927 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 1928 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 1929 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 1930 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 1931 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 1932 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 1933 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING, 1934 .xlevel = 0x80000008, 1935 .model_id = "Common KVM processor" 1936 }, 1937 { 1938 .name = "qemu32", 1939 .level = 4, 1940 .vendor = CPUID_VENDOR_INTEL, 1941 .family = 6, 1942 .model = 6, 1943 .stepping = 3, 1944 .features[FEAT_1_EDX] = 1945 PPRO_FEATURES, 1946 .features[FEAT_1_ECX] = 1947 CPUID_EXT_SSE3, 1948 .xlevel = 0x80000004, 1949 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 1950 }, 1951 { 1952 .name = "kvm32", 1953 .level = 5, 1954 .vendor = CPUID_VENDOR_INTEL, 1955 .family = 15, 1956 .model = 6, 1957 .stepping = 1, 1958 .features[FEAT_1_EDX] = 1959 PPRO_FEATURES | CPUID_VME | 1960 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36, 1961 .features[FEAT_1_ECX] = 1962 CPUID_EXT_SSE3, 1963 .features[FEAT_8000_0001_ECX] = 1964 0, 1965 /* VMX features from Yonah */ 1966 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 1967 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 1968 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 1969 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 1970 VMX_PIN_BASED_NMI_EXITING, 1971 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 1972 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 1973 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 1974 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 1975 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 1976 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 1977 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS, 1978 .xlevel = 0x80000008, 1979 .model_id = "Common 32-bit KVM processor" 1980 }, 1981 { 1982 .name = "coreduo", 1983 .level = 10, 1984 .vendor = CPUID_VENDOR_INTEL, 1985 .family = 6, 1986 .model = 14, 1987 .stepping = 8, 1988 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 1989 .features[FEAT_1_EDX] = 1990 PPRO_FEATURES | CPUID_VME | 1991 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI | 1992 CPUID_SS, 1993 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR, 1994 * CPUID_EXT_PDCM, CPUID_EXT_VMX */ 1995 .features[FEAT_1_ECX] = 1996 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR, 1997 .features[FEAT_8000_0001_EDX] = 1998 CPUID_EXT2_NX, 1999 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2000 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2001 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2002 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2003 VMX_PIN_BASED_NMI_EXITING, 2004 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2005 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2006 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2007 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2008 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 2009 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 2010 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS, 2011 .xlevel = 0x80000008, 2012 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz", 2013 }, 2014 { 2015 .name = "486", 2016 .level = 1, 2017 .vendor = CPUID_VENDOR_INTEL, 2018 .family = 4, 2019 .model = 8, 2020 .stepping = 0, 2021 .features[FEAT_1_EDX] = 2022 I486_FEATURES, 2023 .xlevel = 0, 2024 .model_id = "", 2025 }, 2026 { 2027 .name = "pentium", 2028 .level = 1, 2029 .vendor = CPUID_VENDOR_INTEL, 2030 .family = 5, 2031 .model = 4, 2032 .stepping = 3, 2033 .features[FEAT_1_EDX] = 2034 PENTIUM_FEATURES, 2035 .xlevel = 0, 2036 .model_id = "", 2037 }, 2038 { 2039 .name = "pentium2", 2040 .level = 2, 2041 .vendor = CPUID_VENDOR_INTEL, 2042 .family = 6, 2043 .model = 5, 2044 .stepping = 2, 2045 .features[FEAT_1_EDX] = 2046 PENTIUM2_FEATURES, 2047 .xlevel = 0, 2048 .model_id = "", 2049 }, 2050 { 2051 .name = "pentium3", 2052 .level = 3, 2053 .vendor = CPUID_VENDOR_INTEL, 2054 .family = 6, 2055 .model = 7, 2056 .stepping = 3, 2057 .features[FEAT_1_EDX] = 2058 PENTIUM3_FEATURES, 2059 .xlevel = 0, 2060 .model_id = "", 2061 }, 2062 { 2063 .name = "athlon", 2064 .level = 2, 2065 .vendor = CPUID_VENDOR_AMD, 2066 .family = 6, 2067 .model = 2, 2068 .stepping = 3, 2069 .features[FEAT_1_EDX] = 2070 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR | 2071 CPUID_MCA, 2072 .features[FEAT_8000_0001_EDX] = 2073 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT, 2074 .xlevel = 0x80000008, 2075 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 2076 }, 2077 { 2078 .name = "n270", 2079 .level = 10, 2080 .vendor = CPUID_VENDOR_INTEL, 2081 .family = 6, 2082 .model = 28, 2083 .stepping = 2, 2084 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2085 .features[FEAT_1_EDX] = 2086 PPRO_FEATURES | 2087 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | 2088 CPUID_ACPI | CPUID_SS, 2089 /* Some CPUs got no CPUID_SEP */ 2090 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2, 2091 * CPUID_EXT_XTPR */ 2092 .features[FEAT_1_ECX] = 2093 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | 2094 CPUID_EXT_MOVBE, 2095 .features[FEAT_8000_0001_EDX] = 2096 CPUID_EXT2_NX, 2097 .features[FEAT_8000_0001_ECX] = 2098 CPUID_EXT3_LAHF_LM, 2099 .xlevel = 0x80000008, 2100 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz", 2101 }, 2102 { 2103 .name = "Conroe", 2104 .level = 10, 2105 .vendor = CPUID_VENDOR_INTEL, 2106 .family = 6, 2107 .model = 15, 2108 .stepping = 3, 2109 .features[FEAT_1_EDX] = 2110 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2111 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2112 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2113 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2114 CPUID_DE | CPUID_FP87, 2115 .features[FEAT_1_ECX] = 2116 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, 2117 .features[FEAT_8000_0001_EDX] = 2118 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 2119 .features[FEAT_8000_0001_ECX] = 2120 CPUID_EXT3_LAHF_LM, 2121 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2122 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2123 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2124 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2125 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2126 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2127 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2128 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2129 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2130 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2131 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2132 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2133 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2134 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2135 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2136 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2137 .features[FEAT_VMX_SECONDARY_CTLS] = 2138 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES, 2139 .xlevel = 0x80000008, 2140 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)", 2141 }, 2142 { 2143 .name = "Penryn", 2144 .level = 10, 2145 .vendor = CPUID_VENDOR_INTEL, 2146 .family = 6, 2147 .model = 23, 2148 .stepping = 3, 2149 .features[FEAT_1_EDX] = 2150 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2151 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2152 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2153 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2154 CPUID_DE | CPUID_FP87, 2155 .features[FEAT_1_ECX] = 2156 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2157 CPUID_EXT_SSE3, 2158 .features[FEAT_8000_0001_EDX] = 2159 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 2160 .features[FEAT_8000_0001_ECX] = 2161 CPUID_EXT3_LAHF_LM, 2162 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2163 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2164 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, 2165 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT | 2166 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL, 2167 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2168 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2169 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2170 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2171 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2172 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2173 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2174 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2175 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2176 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2177 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2178 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2179 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2180 .features[FEAT_VMX_SECONDARY_CTLS] = 2181 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2182 VMX_SECONDARY_EXEC_WBINVD_EXITING, 2183 .xlevel = 0x80000008, 2184 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)", 2185 }, 2186 { 2187 .name = "Nehalem", 2188 .level = 11, 2189 .vendor = CPUID_VENDOR_INTEL, 2190 .family = 6, 2191 .model = 26, 2192 .stepping = 3, 2193 .features[FEAT_1_EDX] = 2194 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2195 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2196 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2197 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2198 CPUID_DE | CPUID_FP87, 2199 .features[FEAT_1_ECX] = 2200 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 2201 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, 2202 .features[FEAT_8000_0001_EDX] = 2203 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2204 .features[FEAT_8000_0001_ECX] = 2205 CPUID_EXT3_LAHF_LM, 2206 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2207 MSR_VMX_BASIC_TRUE_CTLS, 2208 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2209 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2210 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2211 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2212 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2213 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2214 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2215 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2216 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2217 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2218 .features[FEAT_VMX_EXIT_CTLS] = 2219 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2220 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2221 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2222 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2223 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2224 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2225 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2226 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2227 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2228 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2229 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2230 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2231 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2232 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2233 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2234 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2235 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2236 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2237 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2238 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2239 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2240 .features[FEAT_VMX_SECONDARY_CTLS] = 2241 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2242 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2243 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2244 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2245 VMX_SECONDARY_EXEC_ENABLE_VPID, 2246 .xlevel = 0x80000008, 2247 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)", 2248 .versions = (X86CPUVersionDefinition[]) { 2249 { .version = 1 }, 2250 { 2251 .version = 2, 2252 .alias = "Nehalem-IBRS", 2253 .props = (PropValue[]) { 2254 { "spec-ctrl", "on" }, 2255 { "model-id", 2256 "Intel Core i7 9xx (Nehalem Core i7, IBRS update)" }, 2257 { /* end of list */ } 2258 } 2259 }, 2260 { /* end of list */ } 2261 } 2262 }, 2263 { 2264 .name = "Westmere", 2265 .level = 11, 2266 .vendor = CPUID_VENDOR_INTEL, 2267 .family = 6, 2268 .model = 44, 2269 .stepping = 1, 2270 .features[FEAT_1_EDX] = 2271 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2272 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2273 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2274 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2275 CPUID_DE | CPUID_FP87, 2276 .features[FEAT_1_ECX] = 2277 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | 2278 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2279 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 2280 .features[FEAT_8000_0001_EDX] = 2281 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2282 .features[FEAT_8000_0001_ECX] = 2283 CPUID_EXT3_LAHF_LM, 2284 .features[FEAT_6_EAX] = 2285 CPUID_6_EAX_ARAT, 2286 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2287 MSR_VMX_BASIC_TRUE_CTLS, 2288 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2289 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2290 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2291 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2292 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2293 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2294 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2295 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2296 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2297 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2298 .features[FEAT_VMX_EXIT_CTLS] = 2299 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2300 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2301 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2302 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2303 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2304 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2305 MSR_VMX_MISC_STORE_LMA, 2306 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2307 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2308 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2309 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2310 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2311 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2312 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2313 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2314 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2315 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2316 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2317 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2318 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2319 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2320 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2321 .features[FEAT_VMX_SECONDARY_CTLS] = 2322 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2323 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2324 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2325 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2326 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST, 2327 .xlevel = 0x80000008, 2328 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)", 2329 .versions = (X86CPUVersionDefinition[]) { 2330 { .version = 1 }, 2331 { 2332 .version = 2, 2333 .alias = "Westmere-IBRS", 2334 .props = (PropValue[]) { 2335 { "spec-ctrl", "on" }, 2336 { "model-id", 2337 "Westmere E56xx/L56xx/X56xx (IBRS update)" }, 2338 { /* end of list */ } 2339 } 2340 }, 2341 { /* end of list */ } 2342 } 2343 }, 2344 { 2345 .name = "SandyBridge", 2346 .level = 0xd, 2347 .vendor = CPUID_VENDOR_INTEL, 2348 .family = 6, 2349 .model = 42, 2350 .stepping = 1, 2351 .features[FEAT_1_EDX] = 2352 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2353 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2354 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2355 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2356 CPUID_DE | CPUID_FP87, 2357 .features[FEAT_1_ECX] = 2358 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2359 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | 2360 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 2361 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 2362 CPUID_EXT_SSE3, 2363 .features[FEAT_8000_0001_EDX] = 2364 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 2365 CPUID_EXT2_SYSCALL, 2366 .features[FEAT_8000_0001_ECX] = 2367 CPUID_EXT3_LAHF_LM, 2368 .features[FEAT_XSAVE] = 2369 CPUID_XSAVE_XSAVEOPT, 2370 .features[FEAT_6_EAX] = 2371 CPUID_6_EAX_ARAT, 2372 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2373 MSR_VMX_BASIC_TRUE_CTLS, 2374 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2375 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2376 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2377 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2378 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2379 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2380 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2381 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2382 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2383 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2384 .features[FEAT_VMX_EXIT_CTLS] = 2385 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2386 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2387 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2388 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2389 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2390 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2391 MSR_VMX_MISC_STORE_LMA, 2392 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2393 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2394 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2395 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2396 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2397 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2398 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2399 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2400 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2401 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2402 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2403 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2404 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2405 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2406 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2407 .features[FEAT_VMX_SECONDARY_CTLS] = 2408 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2409 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2410 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2411 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2412 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST, 2413 .xlevel = 0x80000008, 2414 .model_id = "Intel Xeon E312xx (Sandy Bridge)", 2415 .versions = (X86CPUVersionDefinition[]) { 2416 { .version = 1 }, 2417 { 2418 .version = 2, 2419 .alias = "SandyBridge-IBRS", 2420 .props = (PropValue[]) { 2421 { "spec-ctrl", "on" }, 2422 { "model-id", 2423 "Intel Xeon E312xx (Sandy Bridge, IBRS update)" }, 2424 { /* end of list */ } 2425 } 2426 }, 2427 { /* end of list */ } 2428 } 2429 }, 2430 { 2431 .name = "IvyBridge", 2432 .level = 0xd, 2433 .vendor = CPUID_VENDOR_INTEL, 2434 .family = 6, 2435 .model = 58, 2436 .stepping = 9, 2437 .features[FEAT_1_EDX] = 2438 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2439 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2440 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2441 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2442 CPUID_DE | CPUID_FP87, 2443 .features[FEAT_1_ECX] = 2444 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2445 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | 2446 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 2447 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 2448 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 2449 .features[FEAT_7_0_EBX] = 2450 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | 2451 CPUID_7_0_EBX_ERMS, 2452 .features[FEAT_8000_0001_EDX] = 2453 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 2454 CPUID_EXT2_SYSCALL, 2455 .features[FEAT_8000_0001_ECX] = 2456 CPUID_EXT3_LAHF_LM, 2457 .features[FEAT_XSAVE] = 2458 CPUID_XSAVE_XSAVEOPT, 2459 .features[FEAT_6_EAX] = 2460 CPUID_6_EAX_ARAT, 2461 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2462 MSR_VMX_BASIC_TRUE_CTLS, 2463 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2464 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2465 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2466 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2467 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2468 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2469 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2470 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2471 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2472 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2473 .features[FEAT_VMX_EXIT_CTLS] = 2474 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2475 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2476 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2477 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2478 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2479 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2480 MSR_VMX_MISC_STORE_LMA, 2481 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2482 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2483 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 2484 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2485 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2486 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2487 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2488 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2489 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2490 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2491 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2492 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2493 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2494 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2495 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2496 .features[FEAT_VMX_SECONDARY_CTLS] = 2497 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2498 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2499 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2500 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2501 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 2502 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 2503 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 2504 VMX_SECONDARY_EXEC_RDRAND_EXITING, 2505 .xlevel = 0x80000008, 2506 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)", 2507 .versions = (X86CPUVersionDefinition[]) { 2508 { .version = 1 }, 2509 { 2510 .version = 2, 2511 .alias = "IvyBridge-IBRS", 2512 .props = (PropValue[]) { 2513 { "spec-ctrl", "on" }, 2514 { "model-id", 2515 "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)" }, 2516 { /* end of list */ } 2517 } 2518 }, 2519 { /* end of list */ } 2520 } 2521 }, 2522 { 2523 .name = "Haswell", 2524 .level = 0xd, 2525 .vendor = CPUID_VENDOR_INTEL, 2526 .family = 6, 2527 .model = 60, 2528 .stepping = 4, 2529 .features[FEAT_1_EDX] = 2530 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2531 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2532 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2533 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2534 CPUID_DE | CPUID_FP87, 2535 .features[FEAT_1_ECX] = 2536 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2537 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 2538 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2539 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 2540 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 2541 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 2542 .features[FEAT_8000_0001_EDX] = 2543 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 2544 CPUID_EXT2_SYSCALL, 2545 .features[FEAT_8000_0001_ECX] = 2546 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM, 2547 .features[FEAT_7_0_EBX] = 2548 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 2549 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 2550 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 2551 CPUID_7_0_EBX_RTM, 2552 .features[FEAT_XSAVE] = 2553 CPUID_XSAVE_XSAVEOPT, 2554 .features[FEAT_6_EAX] = 2555 CPUID_6_EAX_ARAT, 2556 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2557 MSR_VMX_BASIC_TRUE_CTLS, 2558 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2559 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2560 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2561 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2562 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2563 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2564 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2565 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2566 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2567 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 2568 .features[FEAT_VMX_EXIT_CTLS] = 2569 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2570 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2571 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2572 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2573 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2574 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2575 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 2576 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2577 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2578 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 2579 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2580 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2581 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2582 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2583 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2584 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2585 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2586 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2587 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2588 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2589 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2590 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2591 .features[FEAT_VMX_SECONDARY_CTLS] = 2592 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2593 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2594 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2595 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2596 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 2597 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 2598 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 2599 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 2600 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS, 2601 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 2602 .xlevel = 0x80000008, 2603 .model_id = "Intel Core Processor (Haswell)", 2604 .versions = (X86CPUVersionDefinition[]) { 2605 { .version = 1 }, 2606 { 2607 .version = 2, 2608 .alias = "Haswell-noTSX", 2609 .props = (PropValue[]) { 2610 { "hle", "off" }, 2611 { "rtm", "off" }, 2612 { "stepping", "1" }, 2613 { "model-id", "Intel Core Processor (Haswell, no TSX)", }, 2614 { /* end of list */ } 2615 }, 2616 }, 2617 { 2618 .version = 3, 2619 .alias = "Haswell-IBRS", 2620 .props = (PropValue[]) { 2621 /* Restore TSX features removed by -v2 above */ 2622 { "hle", "on" }, 2623 { "rtm", "on" }, 2624 /* 2625 * Haswell and Haswell-IBRS had stepping=4 in 2626 * QEMU 4.0 and older 2627 */ 2628 { "stepping", "4" }, 2629 { "spec-ctrl", "on" }, 2630 { "model-id", 2631 "Intel Core Processor (Haswell, IBRS)" }, 2632 { /* end of list */ } 2633 } 2634 }, 2635 { 2636 .version = 4, 2637 .alias = "Haswell-noTSX-IBRS", 2638 .props = (PropValue[]) { 2639 { "hle", "off" }, 2640 { "rtm", "off" }, 2641 /* spec-ctrl was already enabled by -v3 above */ 2642 { "stepping", "1" }, 2643 { "model-id", 2644 "Intel Core Processor (Haswell, no TSX, IBRS)" }, 2645 { /* end of list */ } 2646 } 2647 }, 2648 { /* end of list */ } 2649 } 2650 }, 2651 { 2652 .name = "Broadwell", 2653 .level = 0xd, 2654 .vendor = CPUID_VENDOR_INTEL, 2655 .family = 6, 2656 .model = 61, 2657 .stepping = 2, 2658 .features[FEAT_1_EDX] = 2659 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2660 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2661 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2662 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2663 CPUID_DE | CPUID_FP87, 2664 .features[FEAT_1_ECX] = 2665 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2666 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 2667 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2668 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 2669 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 2670 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 2671 .features[FEAT_8000_0001_EDX] = 2672 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 2673 CPUID_EXT2_SYSCALL, 2674 .features[FEAT_8000_0001_ECX] = 2675 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 2676 .features[FEAT_7_0_EBX] = 2677 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 2678 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 2679 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 2680 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 2681 CPUID_7_0_EBX_SMAP, 2682 .features[FEAT_XSAVE] = 2683 CPUID_XSAVE_XSAVEOPT, 2684 .features[FEAT_6_EAX] = 2685 CPUID_6_EAX_ARAT, 2686 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2687 MSR_VMX_BASIC_TRUE_CTLS, 2688 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2689 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2690 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2691 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2692 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2693 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2694 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2695 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2696 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2697 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 2698 .features[FEAT_VMX_EXIT_CTLS] = 2699 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2700 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2701 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2702 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2703 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2704 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2705 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 2706 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2707 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2708 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 2709 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2710 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2711 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2712 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2713 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2714 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2715 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2716 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2717 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2718 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2719 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2720 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2721 .features[FEAT_VMX_SECONDARY_CTLS] = 2722 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2723 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2724 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2725 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2726 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 2727 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 2728 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 2729 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 2730 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 2731 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 2732 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 2733 .xlevel = 0x80000008, 2734 .model_id = "Intel Core Processor (Broadwell)", 2735 .versions = (X86CPUVersionDefinition[]) { 2736 { .version = 1 }, 2737 { 2738 .version = 2, 2739 .alias = "Broadwell-noTSX", 2740 .props = (PropValue[]) { 2741 { "hle", "off" }, 2742 { "rtm", "off" }, 2743 { "model-id", "Intel Core Processor (Broadwell, no TSX)", }, 2744 { /* end of list */ } 2745 }, 2746 }, 2747 { 2748 .version = 3, 2749 .alias = "Broadwell-IBRS", 2750 .props = (PropValue[]) { 2751 /* Restore TSX features removed by -v2 above */ 2752 { "hle", "on" }, 2753 { "rtm", "on" }, 2754 { "spec-ctrl", "on" }, 2755 { "model-id", 2756 "Intel Core Processor (Broadwell, IBRS)" }, 2757 { /* end of list */ } 2758 } 2759 }, 2760 { 2761 .version = 4, 2762 .alias = "Broadwell-noTSX-IBRS", 2763 .props = (PropValue[]) { 2764 { "hle", "off" }, 2765 { "rtm", "off" }, 2766 /* spec-ctrl was already enabled by -v3 above */ 2767 { "model-id", 2768 "Intel Core Processor (Broadwell, no TSX, IBRS)" }, 2769 { /* end of list */ } 2770 } 2771 }, 2772 { /* end of list */ } 2773 } 2774 }, 2775 { 2776 .name = "Skylake-Client", 2777 .level = 0xd, 2778 .vendor = CPUID_VENDOR_INTEL, 2779 .family = 6, 2780 .model = 94, 2781 .stepping = 3, 2782 .features[FEAT_1_EDX] = 2783 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2784 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2785 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2786 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2787 CPUID_DE | CPUID_FP87, 2788 .features[FEAT_1_ECX] = 2789 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2790 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 2791 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2792 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 2793 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 2794 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 2795 .features[FEAT_8000_0001_EDX] = 2796 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 2797 CPUID_EXT2_SYSCALL, 2798 .features[FEAT_8000_0001_ECX] = 2799 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 2800 .features[FEAT_7_0_EBX] = 2801 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 2802 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 2803 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 2804 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 2805 CPUID_7_0_EBX_SMAP, 2806 /* Missing: XSAVES (not supported by some Linux versions, 2807 * including v4.1 to v4.12). 2808 * KVM doesn't yet expose any XSAVES state save component, 2809 * and the only one defined in Skylake (processor tracing) 2810 * probably will block migration anyway. 2811 */ 2812 .features[FEAT_XSAVE] = 2813 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 2814 CPUID_XSAVE_XGETBV1, 2815 .features[FEAT_6_EAX] = 2816 CPUID_6_EAX_ARAT, 2817 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 2818 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2819 MSR_VMX_BASIC_TRUE_CTLS, 2820 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2821 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2822 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2823 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2824 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2825 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2826 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2827 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2828 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2829 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 2830 .features[FEAT_VMX_EXIT_CTLS] = 2831 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2832 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2833 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2834 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2835 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2836 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2837 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 2838 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2839 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2840 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2841 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2842 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2843 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2844 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2845 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2846 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2847 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2848 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2849 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2850 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2851 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2852 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2853 .features[FEAT_VMX_SECONDARY_CTLS] = 2854 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2855 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2856 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2857 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 2858 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 2859 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 2860 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 2861 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 2862 .xlevel = 0x80000008, 2863 .model_id = "Intel Core Processor (Skylake)", 2864 .versions = (X86CPUVersionDefinition[]) { 2865 { .version = 1 }, 2866 { 2867 .version = 2, 2868 .alias = "Skylake-Client-IBRS", 2869 .props = (PropValue[]) { 2870 { "spec-ctrl", "on" }, 2871 { "model-id", 2872 "Intel Core Processor (Skylake, IBRS)" }, 2873 { /* end of list */ } 2874 } 2875 }, 2876 { 2877 .version = 3, 2878 .alias = "Skylake-Client-noTSX-IBRS", 2879 .props = (PropValue[]) { 2880 { "hle", "off" }, 2881 { "rtm", "off" }, 2882 { "model-id", 2883 "Intel Core Processor (Skylake, IBRS, no TSX)" }, 2884 { /* end of list */ } 2885 } 2886 }, 2887 { /* end of list */ } 2888 } 2889 }, 2890 { 2891 .name = "Skylake-Server", 2892 .level = 0xd, 2893 .vendor = CPUID_VENDOR_INTEL, 2894 .family = 6, 2895 .model = 85, 2896 .stepping = 4, 2897 .features[FEAT_1_EDX] = 2898 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2899 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2900 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2901 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2902 CPUID_DE | CPUID_FP87, 2903 .features[FEAT_1_ECX] = 2904 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2905 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 2906 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2907 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 2908 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 2909 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 2910 .features[FEAT_8000_0001_EDX] = 2911 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 2912 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 2913 .features[FEAT_8000_0001_ECX] = 2914 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 2915 .features[FEAT_7_0_EBX] = 2916 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 2917 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 2918 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 2919 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 2920 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 2921 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 2922 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 2923 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 2924 .features[FEAT_7_0_ECX] = 2925 CPUID_7_0_ECX_PKU, 2926 /* Missing: XSAVES (not supported by some Linux versions, 2927 * including v4.1 to v4.12). 2928 * KVM doesn't yet expose any XSAVES state save component, 2929 * and the only one defined in Skylake (processor tracing) 2930 * probably will block migration anyway. 2931 */ 2932 .features[FEAT_XSAVE] = 2933 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 2934 CPUID_XSAVE_XGETBV1, 2935 .features[FEAT_6_EAX] = 2936 CPUID_6_EAX_ARAT, 2937 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 2938 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2939 MSR_VMX_BASIC_TRUE_CTLS, 2940 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2941 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2942 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2943 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2944 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2945 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2946 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2947 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2948 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2949 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 2950 .features[FEAT_VMX_EXIT_CTLS] = 2951 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2952 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2953 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2954 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2955 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2956 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2957 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 2958 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2959 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2960 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 2961 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2962 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2963 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2964 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2965 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2966 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2967 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2968 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2969 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2970 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2971 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2972 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2973 .features[FEAT_VMX_SECONDARY_CTLS] = 2974 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2975 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2976 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2977 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2978 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 2979 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 2980 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 2981 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 2982 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 2983 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 2984 .xlevel = 0x80000008, 2985 .model_id = "Intel Xeon Processor (Skylake)", 2986 .versions = (X86CPUVersionDefinition[]) { 2987 { .version = 1 }, 2988 { 2989 .version = 2, 2990 .alias = "Skylake-Server-IBRS", 2991 .props = (PropValue[]) { 2992 /* clflushopt was not added to Skylake-Server-IBRS */ 2993 /* TODO: add -v3 including clflushopt */ 2994 { "clflushopt", "off" }, 2995 { "spec-ctrl", "on" }, 2996 { "model-id", 2997 "Intel Xeon Processor (Skylake, IBRS)" }, 2998 { /* end of list */ } 2999 } 3000 }, 3001 { 3002 .version = 3, 3003 .alias = "Skylake-Server-noTSX-IBRS", 3004 .props = (PropValue[]) { 3005 { "hle", "off" }, 3006 { "rtm", "off" }, 3007 { "model-id", 3008 "Intel Xeon Processor (Skylake, IBRS, no TSX)" }, 3009 { /* end of list */ } 3010 } 3011 }, 3012 { 3013 .version = 4, 3014 .props = (PropValue[]) { 3015 { "vmx-eptp-switching", "on" }, 3016 { /* end of list */ } 3017 } 3018 }, 3019 { /* end of list */ } 3020 } 3021 }, 3022 { 3023 .name = "Cascadelake-Server", 3024 .level = 0xd, 3025 .vendor = CPUID_VENDOR_INTEL, 3026 .family = 6, 3027 .model = 85, 3028 .stepping = 6, 3029 .features[FEAT_1_EDX] = 3030 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3031 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3032 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3033 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3034 CPUID_DE | CPUID_FP87, 3035 .features[FEAT_1_ECX] = 3036 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3037 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3038 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3039 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3040 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3041 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3042 .features[FEAT_8000_0001_EDX] = 3043 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3044 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3045 .features[FEAT_8000_0001_ECX] = 3046 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3047 .features[FEAT_7_0_EBX] = 3048 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3049 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3050 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3051 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3052 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3053 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3054 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3055 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3056 .features[FEAT_7_0_ECX] = 3057 CPUID_7_0_ECX_PKU | 3058 CPUID_7_0_ECX_AVX512VNNI, 3059 .features[FEAT_7_0_EDX] = 3060 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 3061 /* Missing: XSAVES (not supported by some Linux versions, 3062 * including v4.1 to v4.12). 3063 * KVM doesn't yet expose any XSAVES state save component, 3064 * and the only one defined in Skylake (processor tracing) 3065 * probably will block migration anyway. 3066 */ 3067 .features[FEAT_XSAVE] = 3068 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3069 CPUID_XSAVE_XGETBV1, 3070 .features[FEAT_6_EAX] = 3071 CPUID_6_EAX_ARAT, 3072 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3073 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3074 MSR_VMX_BASIC_TRUE_CTLS, 3075 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3076 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3077 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3078 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3079 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3080 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3081 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3082 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3083 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3084 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3085 .features[FEAT_VMX_EXIT_CTLS] = 3086 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3087 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3088 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3089 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3090 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3091 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3092 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3093 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3094 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3095 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3096 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3097 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3098 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3099 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3100 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3101 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3102 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3103 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3104 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3105 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3106 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3107 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3108 .features[FEAT_VMX_SECONDARY_CTLS] = 3109 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3110 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3111 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3112 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3113 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3114 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3115 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3116 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3117 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3118 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3119 .xlevel = 0x80000008, 3120 .model_id = "Intel Xeon Processor (Cascadelake)", 3121 .versions = (X86CPUVersionDefinition[]) { 3122 { .version = 1 }, 3123 { .version = 2, 3124 .note = "ARCH_CAPABILITIES", 3125 .props = (PropValue[]) { 3126 { "arch-capabilities", "on" }, 3127 { "rdctl-no", "on" }, 3128 { "ibrs-all", "on" }, 3129 { "skip-l1dfl-vmentry", "on" }, 3130 { "mds-no", "on" }, 3131 { /* end of list */ } 3132 }, 3133 }, 3134 { .version = 3, 3135 .alias = "Cascadelake-Server-noTSX", 3136 .note = "ARCH_CAPABILITIES, no TSX", 3137 .props = (PropValue[]) { 3138 { "hle", "off" }, 3139 { "rtm", "off" }, 3140 { /* end of list */ } 3141 }, 3142 }, 3143 { .version = 4, 3144 .note = "ARCH_CAPABILITIES, no TSX", 3145 .props = (PropValue[]) { 3146 { "vmx-eptp-switching", "on" }, 3147 { /* end of list */ } 3148 }, 3149 }, 3150 { /* end of list */ } 3151 } 3152 }, 3153 { 3154 .name = "Cooperlake", 3155 .level = 0xd, 3156 .vendor = CPUID_VENDOR_INTEL, 3157 .family = 6, 3158 .model = 85, 3159 .stepping = 10, 3160 .features[FEAT_1_EDX] = 3161 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3162 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3163 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3164 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3165 CPUID_DE | CPUID_FP87, 3166 .features[FEAT_1_ECX] = 3167 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3168 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3169 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3170 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3171 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3172 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3173 .features[FEAT_8000_0001_EDX] = 3174 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3175 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3176 .features[FEAT_8000_0001_ECX] = 3177 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3178 .features[FEAT_7_0_EBX] = 3179 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3180 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3181 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3182 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3183 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3184 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3185 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3186 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3187 .features[FEAT_7_0_ECX] = 3188 CPUID_7_0_ECX_PKU | 3189 CPUID_7_0_ECX_AVX512VNNI, 3190 .features[FEAT_7_0_EDX] = 3191 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_STIBP | 3192 CPUID_7_0_EDX_SPEC_CTRL_SSBD | CPUID_7_0_EDX_ARCH_CAPABILITIES, 3193 .features[FEAT_ARCH_CAPABILITIES] = 3194 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 3195 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 3196 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO, 3197 .features[FEAT_7_1_EAX] = 3198 CPUID_7_1_EAX_AVX512_BF16, 3199 /* 3200 * Missing: XSAVES (not supported by some Linux versions, 3201 * including v4.1 to v4.12). 3202 * KVM doesn't yet expose any XSAVES state save component, 3203 * and the only one defined in Skylake (processor tracing) 3204 * probably will block migration anyway. 3205 */ 3206 .features[FEAT_XSAVE] = 3207 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3208 CPUID_XSAVE_XGETBV1, 3209 .features[FEAT_6_EAX] = 3210 CPUID_6_EAX_ARAT, 3211 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3212 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3213 MSR_VMX_BASIC_TRUE_CTLS, 3214 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3215 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3216 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3217 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3218 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3219 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3220 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3221 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3222 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3223 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3224 .features[FEAT_VMX_EXIT_CTLS] = 3225 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3226 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3227 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3228 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3229 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3230 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3231 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3232 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3233 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3234 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3235 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3236 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3237 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3238 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3239 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3240 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3241 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3242 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3243 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3244 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3245 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3246 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3247 .features[FEAT_VMX_SECONDARY_CTLS] = 3248 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3249 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3250 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3251 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3252 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3253 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3254 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3255 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3256 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3257 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3258 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3259 .xlevel = 0x80000008, 3260 .model_id = "Intel Xeon Processor (Cooperlake)", 3261 }, 3262 { 3263 .name = "Icelake-Client", 3264 .level = 0xd, 3265 .vendor = CPUID_VENDOR_INTEL, 3266 .family = 6, 3267 .model = 126, 3268 .stepping = 0, 3269 .features[FEAT_1_EDX] = 3270 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3271 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3272 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3273 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3274 CPUID_DE | CPUID_FP87, 3275 .features[FEAT_1_ECX] = 3276 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3277 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3278 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3279 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3280 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3281 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3282 .features[FEAT_8000_0001_EDX] = 3283 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3284 CPUID_EXT2_SYSCALL, 3285 .features[FEAT_8000_0001_ECX] = 3286 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3287 .features[FEAT_8000_0008_EBX] = 3288 CPUID_8000_0008_EBX_WBNOINVD, 3289 .features[FEAT_7_0_EBX] = 3290 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3291 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3292 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3293 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3294 CPUID_7_0_EBX_SMAP, 3295 .features[FEAT_7_0_ECX] = 3296 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 3297 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 3298 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 3299 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 3300 CPUID_7_0_ECX_AVX512_VPOPCNTDQ, 3301 .features[FEAT_7_0_EDX] = 3302 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 3303 /* Missing: XSAVES (not supported by some Linux versions, 3304 * including v4.1 to v4.12). 3305 * KVM doesn't yet expose any XSAVES state save component, 3306 * and the only one defined in Skylake (processor tracing) 3307 * probably will block migration anyway. 3308 */ 3309 .features[FEAT_XSAVE] = 3310 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3311 CPUID_XSAVE_XGETBV1, 3312 .features[FEAT_6_EAX] = 3313 CPUID_6_EAX_ARAT, 3314 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3315 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3316 MSR_VMX_BASIC_TRUE_CTLS, 3317 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3318 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3319 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3320 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3321 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3322 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3323 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3324 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3325 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3326 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3327 .features[FEAT_VMX_EXIT_CTLS] = 3328 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3329 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3330 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3331 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3332 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3333 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3334 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3335 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3336 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3337 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 3338 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3339 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3340 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3341 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3342 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3343 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3344 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3345 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3346 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3347 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3348 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3349 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3350 .features[FEAT_VMX_SECONDARY_CTLS] = 3351 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3352 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3353 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3354 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3355 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3356 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3357 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3358 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3359 .xlevel = 0x80000008, 3360 .model_id = "Intel Core Processor (Icelake)", 3361 .versions = (X86CPUVersionDefinition[]) { 3362 { 3363 .version = 1, 3364 .note = "deprecated" 3365 }, 3366 { 3367 .version = 2, 3368 .note = "no TSX, deprecated", 3369 .alias = "Icelake-Client-noTSX", 3370 .props = (PropValue[]) { 3371 { "hle", "off" }, 3372 { "rtm", "off" }, 3373 { /* end of list */ } 3374 }, 3375 }, 3376 { /* end of list */ } 3377 }, 3378 .deprecation_note = "use Icelake-Server instead" 3379 }, 3380 { 3381 .name = "Icelake-Server", 3382 .level = 0xd, 3383 .vendor = CPUID_VENDOR_INTEL, 3384 .family = 6, 3385 .model = 134, 3386 .stepping = 0, 3387 .features[FEAT_1_EDX] = 3388 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3389 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3390 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3391 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3392 CPUID_DE | CPUID_FP87, 3393 .features[FEAT_1_ECX] = 3394 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3395 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3396 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3397 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3398 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3399 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3400 .features[FEAT_8000_0001_EDX] = 3401 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3402 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3403 .features[FEAT_8000_0001_ECX] = 3404 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3405 .features[FEAT_8000_0008_EBX] = 3406 CPUID_8000_0008_EBX_WBNOINVD, 3407 .features[FEAT_7_0_EBX] = 3408 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3409 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3410 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3411 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3412 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3413 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3414 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3415 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3416 .features[FEAT_7_0_ECX] = 3417 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 3418 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 3419 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 3420 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 3421 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57, 3422 .features[FEAT_7_0_EDX] = 3423 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 3424 /* Missing: XSAVES (not supported by some Linux versions, 3425 * including v4.1 to v4.12). 3426 * KVM doesn't yet expose any XSAVES state save component, 3427 * and the only one defined in Skylake (processor tracing) 3428 * probably will block migration anyway. 3429 */ 3430 .features[FEAT_XSAVE] = 3431 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3432 CPUID_XSAVE_XGETBV1, 3433 .features[FEAT_6_EAX] = 3434 CPUID_6_EAX_ARAT, 3435 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3436 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3437 MSR_VMX_BASIC_TRUE_CTLS, 3438 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3439 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3440 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3441 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3442 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3443 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3444 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3445 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3446 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3447 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3448 .features[FEAT_VMX_EXIT_CTLS] = 3449 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3450 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3451 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3452 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3453 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3454 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3455 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3456 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3457 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3458 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3459 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3460 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3461 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3462 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3463 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3464 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3465 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3466 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3467 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3468 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3469 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3470 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3471 .features[FEAT_VMX_SECONDARY_CTLS] = 3472 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3473 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3474 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3475 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3476 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3477 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3478 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3479 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3480 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS, 3481 .xlevel = 0x80000008, 3482 .model_id = "Intel Xeon Processor (Icelake)", 3483 .versions = (X86CPUVersionDefinition[]) { 3484 { .version = 1 }, 3485 { 3486 .version = 2, 3487 .note = "no TSX", 3488 .alias = "Icelake-Server-noTSX", 3489 .props = (PropValue[]) { 3490 { "hle", "off" }, 3491 { "rtm", "off" }, 3492 { /* end of list */ } 3493 }, 3494 }, 3495 { 3496 .version = 3, 3497 .props = (PropValue[]) { 3498 { "arch-capabilities", "on" }, 3499 { "rdctl-no", "on" }, 3500 { "ibrs-all", "on" }, 3501 { "skip-l1dfl-vmentry", "on" }, 3502 { "mds-no", "on" }, 3503 { "pschange-mc-no", "on" }, 3504 { "taa-no", "on" }, 3505 { /* end of list */ } 3506 }, 3507 }, 3508 { 3509 .version = 4, 3510 .props = (PropValue[]) { 3511 { "sha-ni", "on" }, 3512 { "avx512ifma", "on" }, 3513 { "rdpid", "on" }, 3514 { "fsrm", "on" }, 3515 { "vmx-rdseed-exit", "on" }, 3516 { "vmx-pml", "on" }, 3517 { "vmx-eptp-switching", "on" }, 3518 { "model", "106" }, 3519 { /* end of list */ } 3520 }, 3521 }, 3522 { /* end of list */ } 3523 } 3524 }, 3525 { 3526 .name = "Denverton", 3527 .level = 21, 3528 .vendor = CPUID_VENDOR_INTEL, 3529 .family = 6, 3530 .model = 95, 3531 .stepping = 1, 3532 .features[FEAT_1_EDX] = 3533 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 3534 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 3535 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 3536 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 3537 CPUID_SSE | CPUID_SSE2, 3538 .features[FEAT_1_ECX] = 3539 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR | 3540 CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_SSE41 | 3541 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 3542 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | 3543 CPUID_EXT_AES | CPUID_EXT_XSAVE | CPUID_EXT_RDRAND, 3544 .features[FEAT_8000_0001_EDX] = 3545 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 3546 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 3547 .features[FEAT_8000_0001_ECX] = 3548 CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3549 .features[FEAT_7_0_EBX] = 3550 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_ERMS | 3551 CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_SMAP | 3552 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_SHA_NI, 3553 .features[FEAT_7_0_EDX] = 3554 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES | 3555 CPUID_7_0_EDX_SPEC_CTRL_SSBD, 3556 /* 3557 * Missing: XSAVES (not supported by some Linux versions, 3558 * including v4.1 to v4.12). 3559 * KVM doesn't yet expose any XSAVES state save component, 3560 * and the only one defined in Skylake (processor tracing) 3561 * probably will block migration anyway. 3562 */ 3563 .features[FEAT_XSAVE] = 3564 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | CPUID_XSAVE_XGETBV1, 3565 .features[FEAT_6_EAX] = 3566 CPUID_6_EAX_ARAT, 3567 .features[FEAT_ARCH_CAPABILITIES] = 3568 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY, 3569 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3570 MSR_VMX_BASIC_TRUE_CTLS, 3571 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3572 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3573 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3574 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3575 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3576 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3577 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3578 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3579 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3580 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3581 .features[FEAT_VMX_EXIT_CTLS] = 3582 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3583 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3584 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3585 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3586 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3587 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3588 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3589 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3590 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3591 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3592 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3593 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3594 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3595 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3596 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3597 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3598 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3599 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3600 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3601 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3602 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3603 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3604 .features[FEAT_VMX_SECONDARY_CTLS] = 3605 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3606 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3607 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3608 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3609 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3610 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3611 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3612 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3613 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3614 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3615 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3616 .xlevel = 0x80000008, 3617 .model_id = "Intel Atom Processor (Denverton)", 3618 .versions = (X86CPUVersionDefinition[]) { 3619 { .version = 1 }, 3620 { 3621 .version = 2, 3622 .note = "no MPX, no MONITOR", 3623 .props = (PropValue[]) { 3624 { "monitor", "off" }, 3625 { "mpx", "off" }, 3626 { /* end of list */ }, 3627 }, 3628 }, 3629 { /* end of list */ }, 3630 }, 3631 }, 3632 { 3633 .name = "Snowridge", 3634 .level = 27, 3635 .vendor = CPUID_VENDOR_INTEL, 3636 .family = 6, 3637 .model = 134, 3638 .stepping = 1, 3639 .features[FEAT_1_EDX] = 3640 /* missing: CPUID_PN CPUID_IA64 */ 3641 /* missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 3642 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | 3643 CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_MCE | 3644 CPUID_CX8 | CPUID_APIC | CPUID_SEP | 3645 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 3646 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | 3647 CPUID_MMX | 3648 CPUID_FXSR | CPUID_SSE | CPUID_SSE2, 3649 .features[FEAT_1_ECX] = 3650 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR | 3651 CPUID_EXT_SSSE3 | 3652 CPUID_EXT_CX16 | 3653 CPUID_EXT_SSE41 | 3654 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 3655 CPUID_EXT_POPCNT | 3656 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | CPUID_EXT_XSAVE | 3657 CPUID_EXT_RDRAND, 3658 .features[FEAT_8000_0001_EDX] = 3659 CPUID_EXT2_SYSCALL | 3660 CPUID_EXT2_NX | 3661 CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3662 CPUID_EXT2_LM, 3663 .features[FEAT_8000_0001_ECX] = 3664 CPUID_EXT3_LAHF_LM | 3665 CPUID_EXT3_3DNOWPREFETCH, 3666 .features[FEAT_7_0_EBX] = 3667 CPUID_7_0_EBX_FSGSBASE | 3668 CPUID_7_0_EBX_SMEP | 3669 CPUID_7_0_EBX_ERMS | 3670 CPUID_7_0_EBX_MPX | /* missing bits 13, 15 */ 3671 CPUID_7_0_EBX_RDSEED | 3672 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 3673 CPUID_7_0_EBX_CLWB | 3674 CPUID_7_0_EBX_SHA_NI, 3675 .features[FEAT_7_0_ECX] = 3676 CPUID_7_0_ECX_UMIP | 3677 /* missing bit 5 */ 3678 CPUID_7_0_ECX_GFNI | 3679 CPUID_7_0_ECX_MOVDIRI | CPUID_7_0_ECX_CLDEMOTE | 3680 CPUID_7_0_ECX_MOVDIR64B, 3681 .features[FEAT_7_0_EDX] = 3682 CPUID_7_0_EDX_SPEC_CTRL | 3683 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD | 3684 CPUID_7_0_EDX_CORE_CAPABILITY, 3685 .features[FEAT_CORE_CAPABILITY] = 3686 MSR_CORE_CAP_SPLIT_LOCK_DETECT, 3687 /* 3688 * Missing: XSAVES (not supported by some Linux versions, 3689 * including v4.1 to v4.12). 3690 * KVM doesn't yet expose any XSAVES state save component, 3691 * and the only one defined in Skylake (processor tracing) 3692 * probably will block migration anyway. 3693 */ 3694 .features[FEAT_XSAVE] = 3695 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3696 CPUID_XSAVE_XGETBV1, 3697 .features[FEAT_6_EAX] = 3698 CPUID_6_EAX_ARAT, 3699 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3700 MSR_VMX_BASIC_TRUE_CTLS, 3701 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3702 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3703 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3704 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3705 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3706 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3707 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3708 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3709 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3710 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3711 .features[FEAT_VMX_EXIT_CTLS] = 3712 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3713 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3714 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3715 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3716 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3717 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3718 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3719 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3720 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3721 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3722 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3723 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3724 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3725 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3726 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3727 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3728 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3729 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3730 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3731 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3732 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3733 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3734 .features[FEAT_VMX_SECONDARY_CTLS] = 3735 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3736 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3737 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3738 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3739 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3740 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3741 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3742 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3743 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3744 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3745 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3746 .xlevel = 0x80000008, 3747 .model_id = "Intel Atom Processor (SnowRidge)", 3748 .versions = (X86CPUVersionDefinition[]) { 3749 { .version = 1 }, 3750 { 3751 .version = 2, 3752 .props = (PropValue[]) { 3753 { "mpx", "off" }, 3754 { "model-id", "Intel Atom Processor (Snowridge, no MPX)" }, 3755 { /* end of list */ }, 3756 }, 3757 }, 3758 { /* end of list */ }, 3759 }, 3760 }, 3761 { 3762 .name = "KnightsMill", 3763 .level = 0xd, 3764 .vendor = CPUID_VENDOR_INTEL, 3765 .family = 6, 3766 .model = 133, 3767 .stepping = 0, 3768 .features[FEAT_1_EDX] = 3769 CPUID_VME | CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | 3770 CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | 3771 CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | 3772 CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | 3773 CPUID_PSE | CPUID_DE | CPUID_FP87, 3774 .features[FEAT_1_ECX] = 3775 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3776 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3777 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3778 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3779 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3780 CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3781 .features[FEAT_8000_0001_EDX] = 3782 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3783 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3784 .features[FEAT_8000_0001_ECX] = 3785 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3786 .features[FEAT_7_0_EBX] = 3787 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 3788 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 3789 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_AVX512F | 3790 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_AVX512PF | 3791 CPUID_7_0_EBX_AVX512ER, 3792 .features[FEAT_7_0_ECX] = 3793 CPUID_7_0_ECX_AVX512_VPOPCNTDQ, 3794 .features[FEAT_7_0_EDX] = 3795 CPUID_7_0_EDX_AVX512_4VNNIW | CPUID_7_0_EDX_AVX512_4FMAPS, 3796 .features[FEAT_XSAVE] = 3797 CPUID_XSAVE_XSAVEOPT, 3798 .features[FEAT_6_EAX] = 3799 CPUID_6_EAX_ARAT, 3800 .xlevel = 0x80000008, 3801 .model_id = "Intel Xeon Phi Processor (Knights Mill)", 3802 }, 3803 { 3804 .name = "Opteron_G1", 3805 .level = 5, 3806 .vendor = CPUID_VENDOR_AMD, 3807 .family = 15, 3808 .model = 6, 3809 .stepping = 1, 3810 .features[FEAT_1_EDX] = 3811 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3812 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3813 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3814 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3815 CPUID_DE | CPUID_FP87, 3816 .features[FEAT_1_ECX] = 3817 CPUID_EXT_SSE3, 3818 .features[FEAT_8000_0001_EDX] = 3819 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3820 .xlevel = 0x80000008, 3821 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)", 3822 }, 3823 { 3824 .name = "Opteron_G2", 3825 .level = 5, 3826 .vendor = CPUID_VENDOR_AMD, 3827 .family = 15, 3828 .model = 6, 3829 .stepping = 1, 3830 .features[FEAT_1_EDX] = 3831 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3832 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3833 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3834 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3835 CPUID_DE | CPUID_FP87, 3836 .features[FEAT_1_ECX] = 3837 CPUID_EXT_CX16 | CPUID_EXT_SSE3, 3838 .features[FEAT_8000_0001_EDX] = 3839 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3840 .features[FEAT_8000_0001_ECX] = 3841 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, 3842 .xlevel = 0x80000008, 3843 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)", 3844 }, 3845 { 3846 .name = "Opteron_G3", 3847 .level = 5, 3848 .vendor = CPUID_VENDOR_AMD, 3849 .family = 16, 3850 .model = 2, 3851 .stepping = 3, 3852 .features[FEAT_1_EDX] = 3853 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3854 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3855 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3856 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3857 CPUID_DE | CPUID_FP87, 3858 .features[FEAT_1_ECX] = 3859 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR | 3860 CPUID_EXT_SSE3, 3861 .features[FEAT_8000_0001_EDX] = 3862 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL | 3863 CPUID_EXT2_RDTSCP, 3864 .features[FEAT_8000_0001_ECX] = 3865 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | 3866 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, 3867 .xlevel = 0x80000008, 3868 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)", 3869 }, 3870 { 3871 .name = "Opteron_G4", 3872 .level = 0xd, 3873 .vendor = CPUID_VENDOR_AMD, 3874 .family = 21, 3875 .model = 1, 3876 .stepping = 2, 3877 .features[FEAT_1_EDX] = 3878 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3879 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3880 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3881 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3882 CPUID_DE | CPUID_FP87, 3883 .features[FEAT_1_ECX] = 3884 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3885 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 3886 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 3887 CPUID_EXT_SSE3, 3888 .features[FEAT_8000_0001_EDX] = 3889 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX | 3890 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP, 3891 .features[FEAT_8000_0001_ECX] = 3892 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP | 3893 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | 3894 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | 3895 CPUID_EXT3_LAHF_LM, 3896 .features[FEAT_SVM] = 3897 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 3898 /* no xsaveopt! */ 3899 .xlevel = 0x8000001A, 3900 .model_id = "AMD Opteron 62xx class CPU", 3901 }, 3902 { 3903 .name = "Opteron_G5", 3904 .level = 0xd, 3905 .vendor = CPUID_VENDOR_AMD, 3906 .family = 21, 3907 .model = 2, 3908 .stepping = 0, 3909 .features[FEAT_1_EDX] = 3910 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3911 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3912 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3913 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3914 CPUID_DE | CPUID_FP87, 3915 .features[FEAT_1_ECX] = 3916 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE | 3917 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | 3918 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA | 3919 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 3920 .features[FEAT_8000_0001_EDX] = 3921 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX | 3922 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP, 3923 .features[FEAT_8000_0001_ECX] = 3924 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP | 3925 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | 3926 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | 3927 CPUID_EXT3_LAHF_LM, 3928 .features[FEAT_SVM] = 3929 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 3930 /* no xsaveopt! */ 3931 .xlevel = 0x8000001A, 3932 .model_id = "AMD Opteron 63xx class CPU", 3933 }, 3934 { 3935 .name = "EPYC", 3936 .level = 0xd, 3937 .vendor = CPUID_VENDOR_AMD, 3938 .family = 23, 3939 .model = 1, 3940 .stepping = 2, 3941 .features[FEAT_1_EDX] = 3942 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 3943 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 3944 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 3945 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 3946 CPUID_VME | CPUID_FP87, 3947 .features[FEAT_1_ECX] = 3948 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 3949 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 3950 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 3951 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 3952 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 3953 .features[FEAT_8000_0001_EDX] = 3954 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 3955 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 3956 CPUID_EXT2_SYSCALL, 3957 .features[FEAT_8000_0001_ECX] = 3958 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 3959 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 3960 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 3961 CPUID_EXT3_TOPOEXT, 3962 .features[FEAT_7_0_EBX] = 3963 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 3964 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 3965 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 3966 CPUID_7_0_EBX_SHA_NI, 3967 .features[FEAT_XSAVE] = 3968 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3969 CPUID_XSAVE_XGETBV1, 3970 .features[FEAT_6_EAX] = 3971 CPUID_6_EAX_ARAT, 3972 .features[FEAT_SVM] = 3973 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 3974 .xlevel = 0x8000001E, 3975 .model_id = "AMD EPYC Processor", 3976 .cache_info = &epyc_cache_info, 3977 .versions = (X86CPUVersionDefinition[]) { 3978 { .version = 1 }, 3979 { 3980 .version = 2, 3981 .alias = "EPYC-IBPB", 3982 .props = (PropValue[]) { 3983 { "ibpb", "on" }, 3984 { "model-id", 3985 "AMD EPYC Processor (with IBPB)" }, 3986 { /* end of list */ } 3987 } 3988 }, 3989 { 3990 .version = 3, 3991 .props = (PropValue[]) { 3992 { "ibpb", "on" }, 3993 { "perfctr-core", "on" }, 3994 { "clzero", "on" }, 3995 { "xsaveerptr", "on" }, 3996 { "xsaves", "on" }, 3997 { "model-id", 3998 "AMD EPYC Processor" }, 3999 { /* end of list */ } 4000 } 4001 }, 4002 { /* end of list */ } 4003 } 4004 }, 4005 { 4006 .name = "Dhyana", 4007 .level = 0xd, 4008 .vendor = CPUID_VENDOR_HYGON, 4009 .family = 24, 4010 .model = 0, 4011 .stepping = 1, 4012 .features[FEAT_1_EDX] = 4013 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 4014 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 4015 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 4016 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 4017 CPUID_VME | CPUID_FP87, 4018 .features[FEAT_1_ECX] = 4019 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 4020 CPUID_EXT_XSAVE | CPUID_EXT_POPCNT | 4021 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 4022 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 4023 CPUID_EXT_MONITOR | CPUID_EXT_SSE3, 4024 .features[FEAT_8000_0001_EDX] = 4025 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 4026 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 4027 CPUID_EXT2_SYSCALL, 4028 .features[FEAT_8000_0001_ECX] = 4029 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 4030 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 4031 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 4032 CPUID_EXT3_TOPOEXT, 4033 .features[FEAT_8000_0008_EBX] = 4034 CPUID_8000_0008_EBX_IBPB, 4035 .features[FEAT_7_0_EBX] = 4036 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4037 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 4038 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT, 4039 /* 4040 * Missing: XSAVES (not supported by some Linux versions, 4041 * including v4.1 to v4.12). 4042 * KVM doesn't yet expose any XSAVES state save component. 4043 */ 4044 .features[FEAT_XSAVE] = 4045 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4046 CPUID_XSAVE_XGETBV1, 4047 .features[FEAT_6_EAX] = 4048 CPUID_6_EAX_ARAT, 4049 .features[FEAT_SVM] = 4050 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 4051 .xlevel = 0x8000001E, 4052 .model_id = "Hygon Dhyana Processor", 4053 .cache_info = &epyc_cache_info, 4054 }, 4055 { 4056 .name = "EPYC-Rome", 4057 .level = 0xd, 4058 .vendor = CPUID_VENDOR_AMD, 4059 .family = 23, 4060 .model = 49, 4061 .stepping = 0, 4062 .features[FEAT_1_EDX] = 4063 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 4064 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 4065 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 4066 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 4067 CPUID_VME | CPUID_FP87, 4068 .features[FEAT_1_ECX] = 4069 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 4070 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 4071 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 4072 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 4073 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 4074 .features[FEAT_8000_0001_EDX] = 4075 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 4076 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 4077 CPUID_EXT2_SYSCALL, 4078 .features[FEAT_8000_0001_ECX] = 4079 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 4080 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 4081 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 4082 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 4083 .features[FEAT_8000_0008_EBX] = 4084 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 4085 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 4086 CPUID_8000_0008_EBX_STIBP, 4087 .features[FEAT_7_0_EBX] = 4088 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4089 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 4090 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 4091 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB, 4092 .features[FEAT_7_0_ECX] = 4093 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID, 4094 .features[FEAT_XSAVE] = 4095 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4096 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 4097 .features[FEAT_6_EAX] = 4098 CPUID_6_EAX_ARAT, 4099 .features[FEAT_SVM] = 4100 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 4101 .xlevel = 0x8000001E, 4102 .model_id = "AMD EPYC-Rome Processor", 4103 .cache_info = &epyc_rome_cache_info, 4104 }, 4105 }; 4106 4107 /* KVM-specific features that are automatically added/removed 4108 * from all CPU models when KVM is enabled. 4109 */ 4110 static PropValue kvm_default_props[] = { 4111 { "kvmclock", "on" }, 4112 { "kvm-nopiodelay", "on" }, 4113 { "kvm-asyncpf", "on" }, 4114 { "kvm-steal-time", "on" }, 4115 { "kvm-pv-eoi", "on" }, 4116 { "kvmclock-stable-bit", "on" }, 4117 { "x2apic", "on" }, 4118 { "kvm-msi-ext-dest-id", "off" }, 4119 { "acpi", "off" }, 4120 { "monitor", "off" }, 4121 { "svm", "off" }, 4122 { NULL, NULL }, 4123 }; 4124 4125 /* TCG-specific defaults that override all CPU models when using TCG 4126 */ 4127 static PropValue tcg_default_props[] = { 4128 { "vme", "off" }, 4129 { NULL, NULL }, 4130 }; 4131 4132 4133 /* 4134 * We resolve CPU model aliases using -v1 when using "-machine 4135 * none", but this is just for compatibility while libvirt isn't 4136 * adapted to resolve CPU model versions before creating VMs. 4137 * See "Runnability guarantee of CPU models" at 4138 * docs/system/deprecated.rst. 4139 */ 4140 X86CPUVersion default_cpu_version = 1; 4141 4142 void x86_cpu_set_default_version(X86CPUVersion version) 4143 { 4144 /* Translating CPU_VERSION_AUTO to CPU_VERSION_AUTO doesn't make sense */ 4145 assert(version != CPU_VERSION_AUTO); 4146 default_cpu_version = version; 4147 } 4148 4149 static X86CPUVersion x86_cpu_model_last_version(const X86CPUModel *model) 4150 { 4151 int v = 0; 4152 const X86CPUVersionDefinition *vdef = 4153 x86_cpu_def_get_versions(model->cpudef); 4154 while (vdef->version) { 4155 v = vdef->version; 4156 vdef++; 4157 } 4158 return v; 4159 } 4160 4161 /* Return the actual version being used for a specific CPU model */ 4162 static X86CPUVersion x86_cpu_model_resolve_version(const X86CPUModel *model) 4163 { 4164 X86CPUVersion v = model->version; 4165 if (v == CPU_VERSION_AUTO) { 4166 v = default_cpu_version; 4167 } 4168 if (v == CPU_VERSION_LATEST) { 4169 return x86_cpu_model_last_version(model); 4170 } 4171 return v; 4172 } 4173 4174 void x86_cpu_change_kvm_default(const char *prop, const char *value) 4175 { 4176 PropValue *pv; 4177 for (pv = kvm_default_props; pv->prop; pv++) { 4178 if (!strcmp(pv->prop, prop)) { 4179 pv->value = value; 4180 break; 4181 } 4182 } 4183 4184 /* It is valid to call this function only for properties that 4185 * are already present in the kvm_default_props table. 4186 */ 4187 assert(pv->prop); 4188 } 4189 4190 static bool lmce_supported(void) 4191 { 4192 uint64_t mce_cap = 0; 4193 4194 #ifdef CONFIG_KVM 4195 if (kvm_ioctl(kvm_state, KVM_X86_GET_MCE_CAP_SUPPORTED, &mce_cap) < 0) { 4196 return false; 4197 } 4198 #endif 4199 4200 return !!(mce_cap & MCG_LMCE_P); 4201 } 4202 4203 #define CPUID_MODEL_ID_SZ 48 4204 4205 /** 4206 * cpu_x86_fill_model_id: 4207 * Get CPUID model ID string from host CPU. 4208 * 4209 * @str should have at least CPUID_MODEL_ID_SZ bytes 4210 * 4211 * The function does NOT add a null terminator to the string 4212 * automatically. 4213 */ 4214 static int cpu_x86_fill_model_id(char *str) 4215 { 4216 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0; 4217 int i; 4218 4219 for (i = 0; i < 3; i++) { 4220 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx); 4221 memcpy(str + i * 16 + 0, &eax, 4); 4222 memcpy(str + i * 16 + 4, &ebx, 4); 4223 memcpy(str + i * 16 + 8, &ecx, 4); 4224 memcpy(str + i * 16 + 12, &edx, 4); 4225 } 4226 return 0; 4227 } 4228 4229 static Property max_x86_cpu_properties[] = { 4230 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true), 4231 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false), 4232 DEFINE_PROP_END_OF_LIST() 4233 }; 4234 4235 static void max_x86_cpu_class_init(ObjectClass *oc, void *data) 4236 { 4237 DeviceClass *dc = DEVICE_CLASS(oc); 4238 X86CPUClass *xcc = X86_CPU_CLASS(oc); 4239 4240 xcc->ordering = 9; 4241 4242 xcc->model_description = 4243 "Enables all features supported by the accelerator in the current host"; 4244 4245 device_class_set_props(dc, max_x86_cpu_properties); 4246 } 4247 4248 static void max_x86_cpu_initfn(Object *obj) 4249 { 4250 X86CPU *cpu = X86_CPU(obj); 4251 CPUX86State *env = &cpu->env; 4252 KVMState *s = kvm_state; 4253 4254 /* We can't fill the features array here because we don't know yet if 4255 * "migratable" is true or false. 4256 */ 4257 cpu->max_features = true; 4258 4259 if (accel_uses_host_cpuid()) { 4260 char vendor[CPUID_VENDOR_SZ + 1] = { 0 }; 4261 char model_id[CPUID_MODEL_ID_SZ + 1] = { 0 }; 4262 int family, model, stepping; 4263 4264 host_vendor_fms(vendor, &family, &model, &stepping); 4265 cpu_x86_fill_model_id(model_id); 4266 4267 object_property_set_str(OBJECT(cpu), "vendor", vendor, &error_abort); 4268 object_property_set_int(OBJECT(cpu), "family", family, &error_abort); 4269 object_property_set_int(OBJECT(cpu), "model", model, &error_abort); 4270 object_property_set_int(OBJECT(cpu), "stepping", stepping, 4271 &error_abort); 4272 object_property_set_str(OBJECT(cpu), "model-id", model_id, 4273 &error_abort); 4274 4275 if (kvm_enabled()) { 4276 env->cpuid_min_level = 4277 kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX); 4278 env->cpuid_min_xlevel = 4279 kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX); 4280 env->cpuid_min_xlevel2 = 4281 kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX); 4282 } else { 4283 env->cpuid_min_level = 4284 hvf_get_supported_cpuid(0x0, 0, R_EAX); 4285 env->cpuid_min_xlevel = 4286 hvf_get_supported_cpuid(0x80000000, 0, R_EAX); 4287 env->cpuid_min_xlevel2 = 4288 hvf_get_supported_cpuid(0xC0000000, 0, R_EAX); 4289 } 4290 4291 if (lmce_supported()) { 4292 object_property_set_bool(OBJECT(cpu), "lmce", true, &error_abort); 4293 } 4294 } else { 4295 object_property_set_str(OBJECT(cpu), "vendor", CPUID_VENDOR_AMD, 4296 &error_abort); 4297 object_property_set_int(OBJECT(cpu), "family", 6, &error_abort); 4298 object_property_set_int(OBJECT(cpu), "model", 6, &error_abort); 4299 object_property_set_int(OBJECT(cpu), "stepping", 3, &error_abort); 4300 object_property_set_str(OBJECT(cpu), "model-id", 4301 "QEMU TCG CPU version " QEMU_HW_VERSION, 4302 &error_abort); 4303 } 4304 4305 object_property_set_bool(OBJECT(cpu), "pmu", true, &error_abort); 4306 } 4307 4308 static const TypeInfo max_x86_cpu_type_info = { 4309 .name = X86_CPU_TYPE_NAME("max"), 4310 .parent = TYPE_X86_CPU, 4311 .instance_init = max_x86_cpu_initfn, 4312 .class_init = max_x86_cpu_class_init, 4313 }; 4314 4315 #if defined(CONFIG_KVM) || defined(CONFIG_HVF) 4316 static void host_x86_cpu_class_init(ObjectClass *oc, void *data) 4317 { 4318 X86CPUClass *xcc = X86_CPU_CLASS(oc); 4319 4320 xcc->host_cpuid_required = true; 4321 xcc->ordering = 8; 4322 4323 #if defined(CONFIG_KVM) 4324 xcc->model_description = 4325 "KVM processor with all supported host features "; 4326 #elif defined(CONFIG_HVF) 4327 xcc->model_description = 4328 "HVF processor with all supported host features "; 4329 #endif 4330 } 4331 4332 static const TypeInfo host_x86_cpu_type_info = { 4333 .name = X86_CPU_TYPE_NAME("host"), 4334 .parent = X86_CPU_TYPE_NAME("max"), 4335 .class_init = host_x86_cpu_class_init, 4336 }; 4337 4338 #endif 4339 4340 static char *feature_word_description(FeatureWordInfo *f, uint32_t bit) 4341 { 4342 assert(f->type == CPUID_FEATURE_WORD || f->type == MSR_FEATURE_WORD); 4343 4344 switch (f->type) { 4345 case CPUID_FEATURE_WORD: 4346 { 4347 const char *reg = get_register_name_32(f->cpuid.reg); 4348 assert(reg); 4349 return g_strdup_printf("CPUID.%02XH:%s", 4350 f->cpuid.eax, reg); 4351 } 4352 case MSR_FEATURE_WORD: 4353 return g_strdup_printf("MSR(%02XH)", 4354 f->msr.index); 4355 } 4356 4357 return NULL; 4358 } 4359 4360 static bool x86_cpu_have_filtered_features(X86CPU *cpu) 4361 { 4362 FeatureWord w; 4363 4364 for (w = 0; w < FEATURE_WORDS; w++) { 4365 if (cpu->filtered_features[w]) { 4366 return true; 4367 } 4368 } 4369 4370 return false; 4371 } 4372 4373 static void mark_unavailable_features(X86CPU *cpu, FeatureWord w, uint64_t mask, 4374 const char *verbose_prefix) 4375 { 4376 CPUX86State *env = &cpu->env; 4377 FeatureWordInfo *f = &feature_word_info[w]; 4378 int i; 4379 4380 if (!cpu->force_features) { 4381 env->features[w] &= ~mask; 4382 } 4383 cpu->filtered_features[w] |= mask; 4384 4385 if (!verbose_prefix) { 4386 return; 4387 } 4388 4389 for (i = 0; i < 64; ++i) { 4390 if ((1ULL << i) & mask) { 4391 g_autofree char *feat_word_str = feature_word_description(f, i); 4392 warn_report("%s: %s%s%s [bit %d]", 4393 verbose_prefix, 4394 feat_word_str, 4395 f->feat_names[i] ? "." : "", 4396 f->feat_names[i] ? f->feat_names[i] : "", i); 4397 } 4398 } 4399 } 4400 4401 static void x86_cpuid_version_get_family(Object *obj, Visitor *v, 4402 const char *name, void *opaque, 4403 Error **errp) 4404 { 4405 X86CPU *cpu = X86_CPU(obj); 4406 CPUX86State *env = &cpu->env; 4407 int64_t value; 4408 4409 value = (env->cpuid_version >> 8) & 0xf; 4410 if (value == 0xf) { 4411 value += (env->cpuid_version >> 20) & 0xff; 4412 } 4413 visit_type_int(v, name, &value, errp); 4414 } 4415 4416 static void x86_cpuid_version_set_family(Object *obj, Visitor *v, 4417 const char *name, void *opaque, 4418 Error **errp) 4419 { 4420 X86CPU *cpu = X86_CPU(obj); 4421 CPUX86State *env = &cpu->env; 4422 const int64_t min = 0; 4423 const int64_t max = 0xff + 0xf; 4424 int64_t value; 4425 4426 if (!visit_type_int(v, name, &value, errp)) { 4427 return; 4428 } 4429 if (value < min || value > max) { 4430 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", 4431 name ? name : "null", value, min, max); 4432 return; 4433 } 4434 4435 env->cpuid_version &= ~0xff00f00; 4436 if (value > 0x0f) { 4437 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20); 4438 } else { 4439 env->cpuid_version |= value << 8; 4440 } 4441 } 4442 4443 static void x86_cpuid_version_get_model(Object *obj, Visitor *v, 4444 const char *name, void *opaque, 4445 Error **errp) 4446 { 4447 X86CPU *cpu = X86_CPU(obj); 4448 CPUX86State *env = &cpu->env; 4449 int64_t value; 4450 4451 value = (env->cpuid_version >> 4) & 0xf; 4452 value |= ((env->cpuid_version >> 16) & 0xf) << 4; 4453 visit_type_int(v, name, &value, errp); 4454 } 4455 4456 static void x86_cpuid_version_set_model(Object *obj, Visitor *v, 4457 const char *name, void *opaque, 4458 Error **errp) 4459 { 4460 X86CPU *cpu = X86_CPU(obj); 4461 CPUX86State *env = &cpu->env; 4462 const int64_t min = 0; 4463 const int64_t max = 0xff; 4464 int64_t value; 4465 4466 if (!visit_type_int(v, name, &value, errp)) { 4467 return; 4468 } 4469 if (value < min || value > max) { 4470 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", 4471 name ? name : "null", value, min, max); 4472 return; 4473 } 4474 4475 env->cpuid_version &= ~0xf00f0; 4476 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16); 4477 } 4478 4479 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v, 4480 const char *name, void *opaque, 4481 Error **errp) 4482 { 4483 X86CPU *cpu = X86_CPU(obj); 4484 CPUX86State *env = &cpu->env; 4485 int64_t value; 4486 4487 value = env->cpuid_version & 0xf; 4488 visit_type_int(v, name, &value, errp); 4489 } 4490 4491 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v, 4492 const char *name, void *opaque, 4493 Error **errp) 4494 { 4495 X86CPU *cpu = X86_CPU(obj); 4496 CPUX86State *env = &cpu->env; 4497 const int64_t min = 0; 4498 const int64_t max = 0xf; 4499 int64_t value; 4500 4501 if (!visit_type_int(v, name, &value, errp)) { 4502 return; 4503 } 4504 if (value < min || value > max) { 4505 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", 4506 name ? name : "null", value, min, max); 4507 return; 4508 } 4509 4510 env->cpuid_version &= ~0xf; 4511 env->cpuid_version |= value & 0xf; 4512 } 4513 4514 static char *x86_cpuid_get_vendor(Object *obj, Error **errp) 4515 { 4516 X86CPU *cpu = X86_CPU(obj); 4517 CPUX86State *env = &cpu->env; 4518 char *value; 4519 4520 value = g_malloc(CPUID_VENDOR_SZ + 1); 4521 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2, 4522 env->cpuid_vendor3); 4523 return value; 4524 } 4525 4526 static void x86_cpuid_set_vendor(Object *obj, const char *value, 4527 Error **errp) 4528 { 4529 X86CPU *cpu = X86_CPU(obj); 4530 CPUX86State *env = &cpu->env; 4531 int i; 4532 4533 if (strlen(value) != CPUID_VENDOR_SZ) { 4534 error_setg(errp, QERR_PROPERTY_VALUE_BAD, "", "vendor", value); 4535 return; 4536 } 4537 4538 env->cpuid_vendor1 = 0; 4539 env->cpuid_vendor2 = 0; 4540 env->cpuid_vendor3 = 0; 4541 for (i = 0; i < 4; i++) { 4542 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i); 4543 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i); 4544 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i); 4545 } 4546 } 4547 4548 static char *x86_cpuid_get_model_id(Object *obj, Error **errp) 4549 { 4550 X86CPU *cpu = X86_CPU(obj); 4551 CPUX86State *env = &cpu->env; 4552 char *value; 4553 int i; 4554 4555 value = g_malloc(48 + 1); 4556 for (i = 0; i < 48; i++) { 4557 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3)); 4558 } 4559 value[48] = '\0'; 4560 return value; 4561 } 4562 4563 static void x86_cpuid_set_model_id(Object *obj, const char *model_id, 4564 Error **errp) 4565 { 4566 X86CPU *cpu = X86_CPU(obj); 4567 CPUX86State *env = &cpu->env; 4568 int c, len, i; 4569 4570 if (model_id == NULL) { 4571 model_id = ""; 4572 } 4573 len = strlen(model_id); 4574 memset(env->cpuid_model, 0, 48); 4575 for (i = 0; i < 48; i++) { 4576 if (i >= len) { 4577 c = '\0'; 4578 } else { 4579 c = (uint8_t)model_id[i]; 4580 } 4581 env->cpuid_model[i >> 2] |= c << (8 * (i & 3)); 4582 } 4583 } 4584 4585 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name, 4586 void *opaque, Error **errp) 4587 { 4588 X86CPU *cpu = X86_CPU(obj); 4589 int64_t value; 4590 4591 value = cpu->env.tsc_khz * 1000; 4592 visit_type_int(v, name, &value, errp); 4593 } 4594 4595 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name, 4596 void *opaque, Error **errp) 4597 { 4598 X86CPU *cpu = X86_CPU(obj); 4599 const int64_t min = 0; 4600 const int64_t max = INT64_MAX; 4601 int64_t value; 4602 4603 if (!visit_type_int(v, name, &value, errp)) { 4604 return; 4605 } 4606 if (value < min || value > max) { 4607 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", 4608 name ? name : "null", value, min, max); 4609 return; 4610 } 4611 4612 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000; 4613 } 4614 4615 /* Generic getter for "feature-words" and "filtered-features" properties */ 4616 static void x86_cpu_get_feature_words(Object *obj, Visitor *v, 4617 const char *name, void *opaque, 4618 Error **errp) 4619 { 4620 uint64_t *array = (uint64_t *)opaque; 4621 FeatureWord w; 4622 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { }; 4623 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { }; 4624 X86CPUFeatureWordInfoList *list = NULL; 4625 4626 for (w = 0; w < FEATURE_WORDS; w++) { 4627 FeatureWordInfo *wi = &feature_word_info[w]; 4628 /* 4629 * We didn't have MSR features when "feature-words" was 4630 * introduced. Therefore skipped other type entries. 4631 */ 4632 if (wi->type != CPUID_FEATURE_WORD) { 4633 continue; 4634 } 4635 X86CPUFeatureWordInfo *qwi = &word_infos[w]; 4636 qwi->cpuid_input_eax = wi->cpuid.eax; 4637 qwi->has_cpuid_input_ecx = wi->cpuid.needs_ecx; 4638 qwi->cpuid_input_ecx = wi->cpuid.ecx; 4639 qwi->cpuid_register = x86_reg_info_32[wi->cpuid.reg].qapi_enum; 4640 qwi->features = array[w]; 4641 4642 /* List will be in reverse order, but order shouldn't matter */ 4643 list_entries[w].next = list; 4644 list_entries[w].value = &word_infos[w]; 4645 list = &list_entries[w]; 4646 } 4647 4648 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp); 4649 } 4650 4651 /* Convert all '_' in a feature string option name to '-', to make feature 4652 * name conform to QOM property naming rule, which uses '-' instead of '_'. 4653 */ 4654 static inline void feat2prop(char *s) 4655 { 4656 while ((s = strchr(s, '_'))) { 4657 *s = '-'; 4658 } 4659 } 4660 4661 /* Return the feature property name for a feature flag bit */ 4662 static const char *x86_cpu_feature_name(FeatureWord w, int bitnr) 4663 { 4664 const char *name; 4665 /* XSAVE components are automatically enabled by other features, 4666 * so return the original feature name instead 4667 */ 4668 if (w == FEAT_XSAVE_COMP_LO || w == FEAT_XSAVE_COMP_HI) { 4669 int comp = (w == FEAT_XSAVE_COMP_HI) ? bitnr + 32 : bitnr; 4670 4671 if (comp < ARRAY_SIZE(x86_ext_save_areas) && 4672 x86_ext_save_areas[comp].bits) { 4673 w = x86_ext_save_areas[comp].feature; 4674 bitnr = ctz32(x86_ext_save_areas[comp].bits); 4675 } 4676 } 4677 4678 assert(bitnr < 64); 4679 assert(w < FEATURE_WORDS); 4680 name = feature_word_info[w].feat_names[bitnr]; 4681 assert(bitnr < 32 || !(name && feature_word_info[w].type == CPUID_FEATURE_WORD)); 4682 return name; 4683 } 4684 4685 /* Compatibily hack to maintain legacy +-feat semantic, 4686 * where +-feat overwrites any feature set by 4687 * feat=on|feat even if the later is parsed after +-feat 4688 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled) 4689 */ 4690 static GList *plus_features, *minus_features; 4691 4692 static gint compare_string(gconstpointer a, gconstpointer b) 4693 { 4694 return g_strcmp0(a, b); 4695 } 4696 4697 /* Parse "+feature,-feature,feature=foo" CPU feature string 4698 */ 4699 static void x86_cpu_parse_featurestr(const char *typename, char *features, 4700 Error **errp) 4701 { 4702 char *featurestr; /* Single 'key=value" string being parsed */ 4703 static bool cpu_globals_initialized; 4704 bool ambiguous = false; 4705 4706 if (cpu_globals_initialized) { 4707 return; 4708 } 4709 cpu_globals_initialized = true; 4710 4711 if (!features) { 4712 return; 4713 } 4714 4715 for (featurestr = strtok(features, ","); 4716 featurestr; 4717 featurestr = strtok(NULL, ",")) { 4718 const char *name; 4719 const char *val = NULL; 4720 char *eq = NULL; 4721 char num[32]; 4722 GlobalProperty *prop; 4723 4724 /* Compatibility syntax: */ 4725 if (featurestr[0] == '+') { 4726 plus_features = g_list_append(plus_features, 4727 g_strdup(featurestr + 1)); 4728 continue; 4729 } else if (featurestr[0] == '-') { 4730 minus_features = g_list_append(minus_features, 4731 g_strdup(featurestr + 1)); 4732 continue; 4733 } 4734 4735 eq = strchr(featurestr, '='); 4736 if (eq) { 4737 *eq++ = 0; 4738 val = eq; 4739 } else { 4740 val = "on"; 4741 } 4742 4743 feat2prop(featurestr); 4744 name = featurestr; 4745 4746 if (g_list_find_custom(plus_features, name, compare_string)) { 4747 warn_report("Ambiguous CPU model string. " 4748 "Don't mix both \"+%s\" and \"%s=%s\"", 4749 name, name, val); 4750 ambiguous = true; 4751 } 4752 if (g_list_find_custom(minus_features, name, compare_string)) { 4753 warn_report("Ambiguous CPU model string. " 4754 "Don't mix both \"-%s\" and \"%s=%s\"", 4755 name, name, val); 4756 ambiguous = true; 4757 } 4758 4759 /* Special case: */ 4760 if (!strcmp(name, "tsc-freq")) { 4761 int ret; 4762 uint64_t tsc_freq; 4763 4764 ret = qemu_strtosz_metric(val, NULL, &tsc_freq); 4765 if (ret < 0 || tsc_freq > INT64_MAX) { 4766 error_setg(errp, "bad numerical value %s", val); 4767 return; 4768 } 4769 snprintf(num, sizeof(num), "%" PRId64, tsc_freq); 4770 val = num; 4771 name = "tsc-frequency"; 4772 } 4773 4774 prop = g_new0(typeof(*prop), 1); 4775 prop->driver = typename; 4776 prop->property = g_strdup(name); 4777 prop->value = g_strdup(val); 4778 qdev_prop_register_global(prop); 4779 } 4780 4781 if (ambiguous) { 4782 warn_report("Compatibility of ambiguous CPU model " 4783 "strings won't be kept on future QEMU versions"); 4784 } 4785 } 4786 4787 static void x86_cpu_expand_features(X86CPU *cpu, Error **errp); 4788 static void x86_cpu_filter_features(X86CPU *cpu, bool verbose); 4789 4790 /* Build a list with the name of all features on a feature word array */ 4791 static void x86_cpu_list_feature_names(FeatureWordArray features, 4792 strList **feat_names) 4793 { 4794 FeatureWord w; 4795 strList **next = feat_names; 4796 4797 for (w = 0; w < FEATURE_WORDS; w++) { 4798 uint64_t filtered = features[w]; 4799 int i; 4800 for (i = 0; i < 64; i++) { 4801 if (filtered & (1ULL << i)) { 4802 strList *new = g_new0(strList, 1); 4803 new->value = g_strdup(x86_cpu_feature_name(w, i)); 4804 *next = new; 4805 next = &new->next; 4806 } 4807 } 4808 } 4809 } 4810 4811 static void x86_cpu_get_unavailable_features(Object *obj, Visitor *v, 4812 const char *name, void *opaque, 4813 Error **errp) 4814 { 4815 X86CPU *xc = X86_CPU(obj); 4816 strList *result = NULL; 4817 4818 x86_cpu_list_feature_names(xc->filtered_features, &result); 4819 visit_type_strList(v, "unavailable-features", &result, errp); 4820 } 4821 4822 /* Check for missing features that may prevent the CPU class from 4823 * running using the current machine and accelerator. 4824 */ 4825 static void x86_cpu_class_check_missing_features(X86CPUClass *xcc, 4826 strList **missing_feats) 4827 { 4828 X86CPU *xc; 4829 Error *err = NULL; 4830 strList **next = missing_feats; 4831 4832 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) { 4833 strList *new = g_new0(strList, 1); 4834 new->value = g_strdup("kvm"); 4835 *missing_feats = new; 4836 return; 4837 } 4838 4839 xc = X86_CPU(object_new_with_class(OBJECT_CLASS(xcc))); 4840 4841 x86_cpu_expand_features(xc, &err); 4842 if (err) { 4843 /* Errors at x86_cpu_expand_features should never happen, 4844 * but in case it does, just report the model as not 4845 * runnable at all using the "type" property. 4846 */ 4847 strList *new = g_new0(strList, 1); 4848 new->value = g_strdup("type"); 4849 *next = new; 4850 next = &new->next; 4851 error_free(err); 4852 } 4853 4854 x86_cpu_filter_features(xc, false); 4855 4856 x86_cpu_list_feature_names(xc->filtered_features, next); 4857 4858 object_unref(OBJECT(xc)); 4859 } 4860 4861 /* Print all cpuid feature names in featureset 4862 */ 4863 static void listflags(GList *features) 4864 { 4865 size_t len = 0; 4866 GList *tmp; 4867 4868 for (tmp = features; tmp; tmp = tmp->next) { 4869 const char *name = tmp->data; 4870 if ((len + strlen(name) + 1) >= 75) { 4871 qemu_printf("\n"); 4872 len = 0; 4873 } 4874 qemu_printf("%s%s", len == 0 ? " " : " ", name); 4875 len += strlen(name) + 1; 4876 } 4877 qemu_printf("\n"); 4878 } 4879 4880 /* Sort alphabetically by type name, respecting X86CPUClass::ordering. */ 4881 static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b) 4882 { 4883 ObjectClass *class_a = (ObjectClass *)a; 4884 ObjectClass *class_b = (ObjectClass *)b; 4885 X86CPUClass *cc_a = X86_CPU_CLASS(class_a); 4886 X86CPUClass *cc_b = X86_CPU_CLASS(class_b); 4887 int ret; 4888 4889 if (cc_a->ordering != cc_b->ordering) { 4890 ret = cc_a->ordering - cc_b->ordering; 4891 } else { 4892 g_autofree char *name_a = x86_cpu_class_get_model_name(cc_a); 4893 g_autofree char *name_b = x86_cpu_class_get_model_name(cc_b); 4894 ret = strcmp(name_a, name_b); 4895 } 4896 return ret; 4897 } 4898 4899 static GSList *get_sorted_cpu_model_list(void) 4900 { 4901 GSList *list = object_class_get_list(TYPE_X86_CPU, false); 4902 list = g_slist_sort(list, x86_cpu_list_compare); 4903 return list; 4904 } 4905 4906 static char *x86_cpu_class_get_model_id(X86CPUClass *xc) 4907 { 4908 Object *obj = object_new_with_class(OBJECT_CLASS(xc)); 4909 char *r = object_property_get_str(obj, "model-id", &error_abort); 4910 object_unref(obj); 4911 return r; 4912 } 4913 4914 static char *x86_cpu_class_get_alias_of(X86CPUClass *cc) 4915 { 4916 X86CPUVersion version; 4917 4918 if (!cc->model || !cc->model->is_alias) { 4919 return NULL; 4920 } 4921 version = x86_cpu_model_resolve_version(cc->model); 4922 if (version <= 0) { 4923 return NULL; 4924 } 4925 return x86_cpu_versioned_model_name(cc->model->cpudef, version); 4926 } 4927 4928 static void x86_cpu_list_entry(gpointer data, gpointer user_data) 4929 { 4930 ObjectClass *oc = data; 4931 X86CPUClass *cc = X86_CPU_CLASS(oc); 4932 g_autofree char *name = x86_cpu_class_get_model_name(cc); 4933 g_autofree char *desc = g_strdup(cc->model_description); 4934 g_autofree char *alias_of = x86_cpu_class_get_alias_of(cc); 4935 g_autofree char *model_id = x86_cpu_class_get_model_id(cc); 4936 4937 if (!desc && alias_of) { 4938 if (cc->model && cc->model->version == CPU_VERSION_AUTO) { 4939 desc = g_strdup("(alias configured by machine type)"); 4940 } else { 4941 desc = g_strdup_printf("(alias of %s)", alias_of); 4942 } 4943 } 4944 if (!desc && cc->model && cc->model->note) { 4945 desc = g_strdup_printf("%s [%s]", model_id, cc->model->note); 4946 } 4947 if (!desc) { 4948 desc = g_strdup_printf("%s", model_id); 4949 } 4950 4951 qemu_printf("x86 %-20s %-58s\n", name, desc); 4952 } 4953 4954 /* list available CPU models and flags */ 4955 void x86_cpu_list(void) 4956 { 4957 int i, j; 4958 GSList *list; 4959 GList *names = NULL; 4960 4961 qemu_printf("Available CPUs:\n"); 4962 list = get_sorted_cpu_model_list(); 4963 g_slist_foreach(list, x86_cpu_list_entry, NULL); 4964 g_slist_free(list); 4965 4966 names = NULL; 4967 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) { 4968 FeatureWordInfo *fw = &feature_word_info[i]; 4969 for (j = 0; j < 64; j++) { 4970 if (fw->feat_names[j]) { 4971 names = g_list_append(names, (gpointer)fw->feat_names[j]); 4972 } 4973 } 4974 } 4975 4976 names = g_list_sort(names, (GCompareFunc)strcmp); 4977 4978 qemu_printf("\nRecognized CPUID flags:\n"); 4979 listflags(names); 4980 qemu_printf("\n"); 4981 g_list_free(names); 4982 } 4983 4984 static void x86_cpu_definition_entry(gpointer data, gpointer user_data) 4985 { 4986 ObjectClass *oc = data; 4987 X86CPUClass *cc = X86_CPU_CLASS(oc); 4988 CpuDefinitionInfoList **cpu_list = user_data; 4989 CpuDefinitionInfoList *entry; 4990 CpuDefinitionInfo *info; 4991 4992 info = g_malloc0(sizeof(*info)); 4993 info->name = x86_cpu_class_get_model_name(cc); 4994 x86_cpu_class_check_missing_features(cc, &info->unavailable_features); 4995 info->has_unavailable_features = true; 4996 info->q_typename = g_strdup(object_class_get_name(oc)); 4997 info->migration_safe = cc->migration_safe; 4998 info->has_migration_safe = true; 4999 info->q_static = cc->static_model; 5000 if (cc->model && cc->model->cpudef->deprecation_note) { 5001 info->deprecated = true; 5002 } else { 5003 info->deprecated = false; 5004 } 5005 /* 5006 * Old machine types won't report aliases, so that alias translation 5007 * doesn't break compatibility with previous QEMU versions. 5008 */ 5009 if (default_cpu_version != CPU_VERSION_LEGACY) { 5010 info->alias_of = x86_cpu_class_get_alias_of(cc); 5011 info->has_alias_of = !!info->alias_of; 5012 } 5013 5014 entry = g_malloc0(sizeof(*entry)); 5015 entry->value = info; 5016 entry->next = *cpu_list; 5017 *cpu_list = entry; 5018 } 5019 5020 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) 5021 { 5022 CpuDefinitionInfoList *cpu_list = NULL; 5023 GSList *list = get_sorted_cpu_model_list(); 5024 g_slist_foreach(list, x86_cpu_definition_entry, &cpu_list); 5025 g_slist_free(list); 5026 return cpu_list; 5027 } 5028 5029 static uint64_t x86_cpu_get_supported_feature_word(FeatureWord w, 5030 bool migratable_only) 5031 { 5032 FeatureWordInfo *wi = &feature_word_info[w]; 5033 uint64_t r = 0; 5034 5035 if (kvm_enabled()) { 5036 switch (wi->type) { 5037 case CPUID_FEATURE_WORD: 5038 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid.eax, 5039 wi->cpuid.ecx, 5040 wi->cpuid.reg); 5041 break; 5042 case MSR_FEATURE_WORD: 5043 r = kvm_arch_get_supported_msr_feature(kvm_state, 5044 wi->msr.index); 5045 break; 5046 } 5047 } else if (hvf_enabled()) { 5048 if (wi->type != CPUID_FEATURE_WORD) { 5049 return 0; 5050 } 5051 r = hvf_get_supported_cpuid(wi->cpuid.eax, 5052 wi->cpuid.ecx, 5053 wi->cpuid.reg); 5054 } else if (tcg_enabled()) { 5055 r = wi->tcg_features; 5056 } else { 5057 return ~0; 5058 } 5059 if (migratable_only) { 5060 r &= x86_cpu_get_migratable_flags(w); 5061 } 5062 return r; 5063 } 5064 5065 static void x86_cpu_apply_props(X86CPU *cpu, PropValue *props) 5066 { 5067 PropValue *pv; 5068 for (pv = props; pv->prop; pv++) { 5069 if (!pv->value) { 5070 continue; 5071 } 5072 object_property_parse(OBJECT(cpu), pv->prop, pv->value, 5073 &error_abort); 5074 } 5075 } 5076 5077 /* Apply properties for the CPU model version specified in model */ 5078 static void x86_cpu_apply_version_props(X86CPU *cpu, X86CPUModel *model) 5079 { 5080 const X86CPUVersionDefinition *vdef; 5081 X86CPUVersion version = x86_cpu_model_resolve_version(model); 5082 5083 if (version == CPU_VERSION_LEGACY) { 5084 return; 5085 } 5086 5087 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) { 5088 PropValue *p; 5089 5090 for (p = vdef->props; p && p->prop; p++) { 5091 object_property_parse(OBJECT(cpu), p->prop, p->value, 5092 &error_abort); 5093 } 5094 5095 if (vdef->version == version) { 5096 break; 5097 } 5098 } 5099 5100 /* 5101 * If we reached the end of the list, version number was invalid 5102 */ 5103 assert(vdef->version == version); 5104 } 5105 5106 /* Load data from X86CPUDefinition into a X86CPU object 5107 */ 5108 static void x86_cpu_load_model(X86CPU *cpu, X86CPUModel *model) 5109 { 5110 X86CPUDefinition *def = model->cpudef; 5111 CPUX86State *env = &cpu->env; 5112 const char *vendor; 5113 char host_vendor[CPUID_VENDOR_SZ + 1]; 5114 FeatureWord w; 5115 5116 /*NOTE: any property set by this function should be returned by 5117 * x86_cpu_static_props(), so static expansion of 5118 * query-cpu-model-expansion is always complete. 5119 */ 5120 5121 /* CPU models only set _minimum_ values for level/xlevel: */ 5122 object_property_set_uint(OBJECT(cpu), "min-level", def->level, 5123 &error_abort); 5124 object_property_set_uint(OBJECT(cpu), "min-xlevel", def->xlevel, 5125 &error_abort); 5126 5127 object_property_set_int(OBJECT(cpu), "family", def->family, &error_abort); 5128 object_property_set_int(OBJECT(cpu), "model", def->model, &error_abort); 5129 object_property_set_int(OBJECT(cpu), "stepping", def->stepping, 5130 &error_abort); 5131 object_property_set_str(OBJECT(cpu), "model-id", def->model_id, 5132 &error_abort); 5133 for (w = 0; w < FEATURE_WORDS; w++) { 5134 env->features[w] = def->features[w]; 5135 } 5136 5137 /* legacy-cache defaults to 'off' if CPU model provides cache info */ 5138 cpu->legacy_cache = !def->cache_info; 5139 5140 /* Special cases not set in the X86CPUDefinition structs: */ 5141 /* TODO: in-kernel irqchip for hvf */ 5142 if (kvm_enabled()) { 5143 if (!kvm_irqchip_in_kernel()) { 5144 x86_cpu_change_kvm_default("x2apic", "off"); 5145 } else if (kvm_irqchip_is_split() && kvm_enable_x2apic()) { 5146 x86_cpu_change_kvm_default("kvm-msi-ext-dest-id", "on"); 5147 } 5148 5149 x86_cpu_apply_props(cpu, kvm_default_props); 5150 } else if (tcg_enabled()) { 5151 x86_cpu_apply_props(cpu, tcg_default_props); 5152 } 5153 5154 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR; 5155 5156 /* sysenter isn't supported in compatibility mode on AMD, 5157 * syscall isn't supported in compatibility mode on Intel. 5158 * Normally we advertise the actual CPU vendor, but you can 5159 * override this using the 'vendor' property if you want to use 5160 * KVM's sysenter/syscall emulation in compatibility mode and 5161 * when doing cross vendor migration 5162 */ 5163 vendor = def->vendor; 5164 if (accel_uses_host_cpuid()) { 5165 uint32_t ebx = 0, ecx = 0, edx = 0; 5166 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx); 5167 x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx); 5168 vendor = host_vendor; 5169 } 5170 5171 object_property_set_str(OBJECT(cpu), "vendor", vendor, &error_abort); 5172 5173 x86_cpu_apply_version_props(cpu, model); 5174 5175 /* 5176 * Properties in versioned CPU model are not user specified features. 5177 * We can simply clear env->user_features here since it will be filled later 5178 * in x86_cpu_expand_features() based on plus_features and minus_features. 5179 */ 5180 memset(&env->user_features, 0, sizeof(env->user_features)); 5181 } 5182 5183 #ifndef CONFIG_USER_ONLY 5184 /* Return a QDict containing keys for all properties that can be included 5185 * in static expansion of CPU models. All properties set by x86_cpu_load_model() 5186 * must be included in the dictionary. 5187 */ 5188 static QDict *x86_cpu_static_props(void) 5189 { 5190 FeatureWord w; 5191 int i; 5192 static const char *props[] = { 5193 "min-level", 5194 "min-xlevel", 5195 "family", 5196 "model", 5197 "stepping", 5198 "model-id", 5199 "vendor", 5200 "lmce", 5201 NULL, 5202 }; 5203 static QDict *d; 5204 5205 if (d) { 5206 return d; 5207 } 5208 5209 d = qdict_new(); 5210 for (i = 0; props[i]; i++) { 5211 qdict_put_null(d, props[i]); 5212 } 5213 5214 for (w = 0; w < FEATURE_WORDS; w++) { 5215 FeatureWordInfo *fi = &feature_word_info[w]; 5216 int bit; 5217 for (bit = 0; bit < 64; bit++) { 5218 if (!fi->feat_names[bit]) { 5219 continue; 5220 } 5221 qdict_put_null(d, fi->feat_names[bit]); 5222 } 5223 } 5224 5225 return d; 5226 } 5227 5228 /* Add an entry to @props dict, with the value for property. */ 5229 static void x86_cpu_expand_prop(X86CPU *cpu, QDict *props, const char *prop) 5230 { 5231 QObject *value = object_property_get_qobject(OBJECT(cpu), prop, 5232 &error_abort); 5233 5234 qdict_put_obj(props, prop, value); 5235 } 5236 5237 /* Convert CPU model data from X86CPU object to a property dictionary 5238 * that can recreate exactly the same CPU model. 5239 */ 5240 static void x86_cpu_to_dict(X86CPU *cpu, QDict *props) 5241 { 5242 QDict *sprops = x86_cpu_static_props(); 5243 const QDictEntry *e; 5244 5245 for (e = qdict_first(sprops); e; e = qdict_next(sprops, e)) { 5246 const char *prop = qdict_entry_key(e); 5247 x86_cpu_expand_prop(cpu, props, prop); 5248 } 5249 } 5250 5251 /* Convert CPU model data from X86CPU object to a property dictionary 5252 * that can recreate exactly the same CPU model, including every 5253 * writeable QOM property. 5254 */ 5255 static void x86_cpu_to_dict_full(X86CPU *cpu, QDict *props) 5256 { 5257 ObjectPropertyIterator iter; 5258 ObjectProperty *prop; 5259 5260 object_property_iter_init(&iter, OBJECT(cpu)); 5261 while ((prop = object_property_iter_next(&iter))) { 5262 /* skip read-only or write-only properties */ 5263 if (!prop->get || !prop->set) { 5264 continue; 5265 } 5266 5267 /* "hotplugged" is the only property that is configurable 5268 * on the command-line but will be set differently on CPUs 5269 * created using "-cpu ... -smp ..." and by CPUs created 5270 * on the fly by x86_cpu_from_model() for querying. Skip it. 5271 */ 5272 if (!strcmp(prop->name, "hotplugged")) { 5273 continue; 5274 } 5275 x86_cpu_expand_prop(cpu, props, prop->name); 5276 } 5277 } 5278 5279 static void object_apply_props(Object *obj, QDict *props, Error **errp) 5280 { 5281 const QDictEntry *prop; 5282 5283 for (prop = qdict_first(props); prop; prop = qdict_next(props, prop)) { 5284 if (!object_property_set_qobject(obj, qdict_entry_key(prop), 5285 qdict_entry_value(prop), errp)) { 5286 break; 5287 } 5288 } 5289 } 5290 5291 /* Create X86CPU object according to model+props specification */ 5292 static X86CPU *x86_cpu_from_model(const char *model, QDict *props, Error **errp) 5293 { 5294 X86CPU *xc = NULL; 5295 X86CPUClass *xcc; 5296 Error *err = NULL; 5297 5298 xcc = X86_CPU_CLASS(cpu_class_by_name(TYPE_X86_CPU, model)); 5299 if (xcc == NULL) { 5300 error_setg(&err, "CPU model '%s' not found", model); 5301 goto out; 5302 } 5303 5304 xc = X86_CPU(object_new_with_class(OBJECT_CLASS(xcc))); 5305 if (props) { 5306 object_apply_props(OBJECT(xc), props, &err); 5307 if (err) { 5308 goto out; 5309 } 5310 } 5311 5312 x86_cpu_expand_features(xc, &err); 5313 if (err) { 5314 goto out; 5315 } 5316 5317 out: 5318 if (err) { 5319 error_propagate(errp, err); 5320 object_unref(OBJECT(xc)); 5321 xc = NULL; 5322 } 5323 return xc; 5324 } 5325 5326 CpuModelExpansionInfo * 5327 qmp_query_cpu_model_expansion(CpuModelExpansionType type, 5328 CpuModelInfo *model, 5329 Error **errp) 5330 { 5331 X86CPU *xc = NULL; 5332 Error *err = NULL; 5333 CpuModelExpansionInfo *ret = g_new0(CpuModelExpansionInfo, 1); 5334 QDict *props = NULL; 5335 const char *base_name; 5336 5337 xc = x86_cpu_from_model(model->name, 5338 model->has_props ? 5339 qobject_to(QDict, model->props) : 5340 NULL, &err); 5341 if (err) { 5342 goto out; 5343 } 5344 5345 props = qdict_new(); 5346 ret->model = g_new0(CpuModelInfo, 1); 5347 ret->model->props = QOBJECT(props); 5348 ret->model->has_props = true; 5349 5350 switch (type) { 5351 case CPU_MODEL_EXPANSION_TYPE_STATIC: 5352 /* Static expansion will be based on "base" only */ 5353 base_name = "base"; 5354 x86_cpu_to_dict(xc, props); 5355 break; 5356 case CPU_MODEL_EXPANSION_TYPE_FULL: 5357 /* As we don't return every single property, full expansion needs 5358 * to keep the original model name+props, and add extra 5359 * properties on top of that. 5360 */ 5361 base_name = model->name; 5362 x86_cpu_to_dict_full(xc, props); 5363 break; 5364 default: 5365 error_setg(&err, "Unsupported expansion type"); 5366 goto out; 5367 } 5368 5369 x86_cpu_to_dict(xc, props); 5370 5371 ret->model->name = g_strdup(base_name); 5372 5373 out: 5374 object_unref(OBJECT(xc)); 5375 if (err) { 5376 error_propagate(errp, err); 5377 qapi_free_CpuModelExpansionInfo(ret); 5378 ret = NULL; 5379 } 5380 return ret; 5381 } 5382 #endif /* !CONFIG_USER_ONLY */ 5383 5384 static gchar *x86_gdb_arch_name(CPUState *cs) 5385 { 5386 #ifdef TARGET_X86_64 5387 return g_strdup("i386:x86-64"); 5388 #else 5389 return g_strdup("i386"); 5390 #endif 5391 } 5392 5393 static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data) 5394 { 5395 X86CPUModel *model = data; 5396 X86CPUClass *xcc = X86_CPU_CLASS(oc); 5397 CPUClass *cc = CPU_CLASS(oc); 5398 5399 xcc->model = model; 5400 xcc->migration_safe = true; 5401 cc->deprecation_note = model->cpudef->deprecation_note; 5402 } 5403 5404 static void x86_register_cpu_model_type(const char *name, X86CPUModel *model) 5405 { 5406 g_autofree char *typename = x86_cpu_type_name(name); 5407 TypeInfo ti = { 5408 .name = typename, 5409 .parent = TYPE_X86_CPU, 5410 .class_init = x86_cpu_cpudef_class_init, 5411 .class_data = model, 5412 }; 5413 5414 type_register(&ti); 5415 } 5416 5417 static void x86_register_cpudef_types(X86CPUDefinition *def) 5418 { 5419 X86CPUModel *m; 5420 const X86CPUVersionDefinition *vdef; 5421 5422 /* AMD aliases are handled at runtime based on CPUID vendor, so 5423 * they shouldn't be set on the CPU model table. 5424 */ 5425 assert(!(def->features[FEAT_8000_0001_EDX] & CPUID_EXT2_AMD_ALIASES)); 5426 /* catch mistakes instead of silently truncating model_id when too long */ 5427 assert(def->model_id && strlen(def->model_id) <= 48); 5428 5429 /* Unversioned model: */ 5430 m = g_new0(X86CPUModel, 1); 5431 m->cpudef = def; 5432 m->version = CPU_VERSION_AUTO; 5433 m->is_alias = true; 5434 x86_register_cpu_model_type(def->name, m); 5435 5436 /* Versioned models: */ 5437 5438 for (vdef = x86_cpu_def_get_versions(def); vdef->version; vdef++) { 5439 X86CPUModel *m = g_new0(X86CPUModel, 1); 5440 g_autofree char *name = 5441 x86_cpu_versioned_model_name(def, vdef->version); 5442 m->cpudef = def; 5443 m->version = vdef->version; 5444 m->note = vdef->note; 5445 x86_register_cpu_model_type(name, m); 5446 5447 if (vdef->alias) { 5448 X86CPUModel *am = g_new0(X86CPUModel, 1); 5449 am->cpudef = def; 5450 am->version = vdef->version; 5451 am->is_alias = true; 5452 x86_register_cpu_model_type(vdef->alias, am); 5453 } 5454 } 5455 5456 } 5457 5458 #if !defined(CONFIG_USER_ONLY) 5459 5460 void cpu_clear_apic_feature(CPUX86State *env) 5461 { 5462 env->features[FEAT_1_EDX] &= ~CPUID_APIC; 5463 } 5464 5465 #endif /* !CONFIG_USER_ONLY */ 5466 5467 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, 5468 uint32_t *eax, uint32_t *ebx, 5469 uint32_t *ecx, uint32_t *edx) 5470 { 5471 X86CPU *cpu = env_archcpu(env); 5472 CPUState *cs = env_cpu(env); 5473 uint32_t die_offset; 5474 uint32_t limit; 5475 uint32_t signature[3]; 5476 X86CPUTopoInfo topo_info; 5477 5478 topo_info.dies_per_pkg = env->nr_dies; 5479 topo_info.cores_per_die = cs->nr_cores; 5480 topo_info.threads_per_core = cs->nr_threads; 5481 5482 /* Calculate & apply limits for different index ranges */ 5483 if (index >= 0xC0000000) { 5484 limit = env->cpuid_xlevel2; 5485 } else if (index >= 0x80000000) { 5486 limit = env->cpuid_xlevel; 5487 } else if (index >= 0x40000000) { 5488 limit = 0x40000001; 5489 } else { 5490 limit = env->cpuid_level; 5491 } 5492 5493 if (index > limit) { 5494 /* Intel documentation states that invalid EAX input will 5495 * return the same information as EAX=cpuid_level 5496 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID) 5497 */ 5498 index = env->cpuid_level; 5499 } 5500 5501 switch(index) { 5502 case 0: 5503 *eax = env->cpuid_level; 5504 *ebx = env->cpuid_vendor1; 5505 *edx = env->cpuid_vendor2; 5506 *ecx = env->cpuid_vendor3; 5507 break; 5508 case 1: 5509 *eax = env->cpuid_version; 5510 *ebx = (cpu->apic_id << 24) | 5511 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */ 5512 *ecx = env->features[FEAT_1_ECX]; 5513 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) { 5514 *ecx |= CPUID_EXT_OSXSAVE; 5515 } 5516 *edx = env->features[FEAT_1_EDX]; 5517 if (cs->nr_cores * cs->nr_threads > 1) { 5518 *ebx |= (cs->nr_cores * cs->nr_threads) << 16; 5519 *edx |= CPUID_HT; 5520 } 5521 if (!cpu->enable_pmu) { 5522 *ecx &= ~CPUID_EXT_PDCM; 5523 } 5524 break; 5525 case 2: 5526 /* cache info: needed for Pentium Pro compatibility */ 5527 if (cpu->cache_info_passthrough) { 5528 host_cpuid(index, 0, eax, ebx, ecx, edx); 5529 break; 5530 } 5531 *eax = 1; /* Number of CPUID[EAX=2] calls required */ 5532 *ebx = 0; 5533 if (!cpu->enable_l3_cache) { 5534 *ecx = 0; 5535 } else { 5536 *ecx = cpuid2_cache_descriptor(env->cache_info_cpuid2.l3_cache); 5537 } 5538 *edx = (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1d_cache) << 16) | 5539 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1i_cache) << 8) | 5540 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l2_cache)); 5541 break; 5542 case 4: 5543 /* cache info: needed for Core compatibility */ 5544 if (cpu->cache_info_passthrough) { 5545 host_cpuid(index, count, eax, ebx, ecx, edx); 5546 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */ 5547 *eax &= ~0xFC000000; 5548 if ((*eax & 31) && cs->nr_cores > 1) { 5549 *eax |= (cs->nr_cores - 1) << 26; 5550 } 5551 } else { 5552 *eax = 0; 5553 switch (count) { 5554 case 0: /* L1 dcache info */ 5555 encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache, 5556 1, cs->nr_cores, 5557 eax, ebx, ecx, edx); 5558 break; 5559 case 1: /* L1 icache info */ 5560 encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache, 5561 1, cs->nr_cores, 5562 eax, ebx, ecx, edx); 5563 break; 5564 case 2: /* L2 cache info */ 5565 encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache, 5566 cs->nr_threads, cs->nr_cores, 5567 eax, ebx, ecx, edx); 5568 break; 5569 case 3: /* L3 cache info */ 5570 die_offset = apicid_die_offset(&topo_info); 5571 if (cpu->enable_l3_cache) { 5572 encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache, 5573 (1 << die_offset), cs->nr_cores, 5574 eax, ebx, ecx, edx); 5575 break; 5576 } 5577 /* fall through */ 5578 default: /* end of info */ 5579 *eax = *ebx = *ecx = *edx = 0; 5580 break; 5581 } 5582 } 5583 break; 5584 case 5: 5585 /* MONITOR/MWAIT Leaf */ 5586 *eax = cpu->mwait.eax; /* Smallest monitor-line size in bytes */ 5587 *ebx = cpu->mwait.ebx; /* Largest monitor-line size in bytes */ 5588 *ecx = cpu->mwait.ecx; /* flags */ 5589 *edx = cpu->mwait.edx; /* mwait substates */ 5590 break; 5591 case 6: 5592 /* Thermal and Power Leaf */ 5593 *eax = env->features[FEAT_6_EAX]; 5594 *ebx = 0; 5595 *ecx = 0; 5596 *edx = 0; 5597 break; 5598 case 7: 5599 /* Structured Extended Feature Flags Enumeration Leaf */ 5600 if (count == 0) { 5601 /* Maximum ECX value for sub-leaves */ 5602 *eax = env->cpuid_level_func7; 5603 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */ 5604 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */ 5605 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) { 5606 *ecx |= CPUID_7_0_ECX_OSPKE; 5607 } 5608 *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */ 5609 } else if (count == 1) { 5610 *eax = env->features[FEAT_7_1_EAX]; 5611 *ebx = 0; 5612 *ecx = 0; 5613 *edx = 0; 5614 } else { 5615 *eax = 0; 5616 *ebx = 0; 5617 *ecx = 0; 5618 *edx = 0; 5619 } 5620 break; 5621 case 9: 5622 /* Direct Cache Access Information Leaf */ 5623 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */ 5624 *ebx = 0; 5625 *ecx = 0; 5626 *edx = 0; 5627 break; 5628 case 0xA: 5629 /* Architectural Performance Monitoring Leaf */ 5630 if (kvm_enabled() && cpu->enable_pmu) { 5631 KVMState *s = cs->kvm_state; 5632 5633 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX); 5634 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX); 5635 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX); 5636 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX); 5637 } else if (hvf_enabled() && cpu->enable_pmu) { 5638 *eax = hvf_get_supported_cpuid(0xA, count, R_EAX); 5639 *ebx = hvf_get_supported_cpuid(0xA, count, R_EBX); 5640 *ecx = hvf_get_supported_cpuid(0xA, count, R_ECX); 5641 *edx = hvf_get_supported_cpuid(0xA, count, R_EDX); 5642 } else { 5643 *eax = 0; 5644 *ebx = 0; 5645 *ecx = 0; 5646 *edx = 0; 5647 } 5648 break; 5649 case 0xB: 5650 /* Extended Topology Enumeration Leaf */ 5651 if (!cpu->enable_cpuid_0xb) { 5652 *eax = *ebx = *ecx = *edx = 0; 5653 break; 5654 } 5655 5656 *ecx = count & 0xff; 5657 *edx = cpu->apic_id; 5658 5659 switch (count) { 5660 case 0: 5661 *eax = apicid_core_offset(&topo_info); 5662 *ebx = cs->nr_threads; 5663 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT; 5664 break; 5665 case 1: 5666 *eax = apicid_pkg_offset(&topo_info); 5667 *ebx = cs->nr_cores * cs->nr_threads; 5668 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE; 5669 break; 5670 default: 5671 *eax = 0; 5672 *ebx = 0; 5673 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID; 5674 } 5675 5676 assert(!(*eax & ~0x1f)); 5677 *ebx &= 0xffff; /* The count doesn't need to be reliable. */ 5678 break; 5679 case 0x1F: 5680 /* V2 Extended Topology Enumeration Leaf */ 5681 if (env->nr_dies < 2) { 5682 *eax = *ebx = *ecx = *edx = 0; 5683 break; 5684 } 5685 5686 *ecx = count & 0xff; 5687 *edx = cpu->apic_id; 5688 switch (count) { 5689 case 0: 5690 *eax = apicid_core_offset(&topo_info); 5691 *ebx = cs->nr_threads; 5692 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT; 5693 break; 5694 case 1: 5695 *eax = apicid_die_offset(&topo_info); 5696 *ebx = cs->nr_cores * cs->nr_threads; 5697 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE; 5698 break; 5699 case 2: 5700 *eax = apicid_pkg_offset(&topo_info); 5701 *ebx = env->nr_dies * cs->nr_cores * cs->nr_threads; 5702 *ecx |= CPUID_TOPOLOGY_LEVEL_DIE; 5703 break; 5704 default: 5705 *eax = 0; 5706 *ebx = 0; 5707 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID; 5708 } 5709 assert(!(*eax & ~0x1f)); 5710 *ebx &= 0xffff; /* The count doesn't need to be reliable. */ 5711 break; 5712 case 0xD: { 5713 /* Processor Extended State */ 5714 *eax = 0; 5715 *ebx = 0; 5716 *ecx = 0; 5717 *edx = 0; 5718 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { 5719 break; 5720 } 5721 5722 if (count == 0) { 5723 *ecx = xsave_area_size(x86_cpu_xsave_components(cpu)); 5724 *eax = env->features[FEAT_XSAVE_COMP_LO]; 5725 *edx = env->features[FEAT_XSAVE_COMP_HI]; 5726 /* 5727 * The initial value of xcr0 and ebx == 0, On host without kvm 5728 * commit 412a3c41(e.g., CentOS 6), the ebx's value always == 0 5729 * even through guest update xcr0, this will crash some legacy guest 5730 * (e.g., CentOS 6), So set ebx == ecx to workaroud it. 5731 */ 5732 *ebx = kvm_enabled() ? *ecx : xsave_area_size(env->xcr0); 5733 } else if (count == 1) { 5734 *eax = env->features[FEAT_XSAVE]; 5735 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) { 5736 if ((x86_cpu_xsave_components(cpu) >> count) & 1) { 5737 const ExtSaveArea *esa = &x86_ext_save_areas[count]; 5738 *eax = esa->size; 5739 *ebx = esa->offset; 5740 } 5741 } 5742 break; 5743 } 5744 case 0x14: { 5745 /* Intel Processor Trace Enumeration */ 5746 *eax = 0; 5747 *ebx = 0; 5748 *ecx = 0; 5749 *edx = 0; 5750 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) || 5751 !kvm_enabled()) { 5752 break; 5753 } 5754 5755 if (count == 0) { 5756 *eax = INTEL_PT_MAX_SUBLEAF; 5757 *ebx = INTEL_PT_MINIMAL_EBX; 5758 *ecx = INTEL_PT_MINIMAL_ECX; 5759 } else if (count == 1) { 5760 *eax = INTEL_PT_MTC_BITMAP | INTEL_PT_ADDR_RANGES_NUM; 5761 *ebx = INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP; 5762 } 5763 break; 5764 } 5765 case 0x40000000: 5766 /* 5767 * CPUID code in kvm_arch_init_vcpu() ignores stuff 5768 * set here, but we restrict to TCG none the less. 5769 */ 5770 if (tcg_enabled() && cpu->expose_tcg) { 5771 memcpy(signature, "TCGTCGTCGTCG", 12); 5772 *eax = 0x40000001; 5773 *ebx = signature[0]; 5774 *ecx = signature[1]; 5775 *edx = signature[2]; 5776 } else { 5777 *eax = 0; 5778 *ebx = 0; 5779 *ecx = 0; 5780 *edx = 0; 5781 } 5782 break; 5783 case 0x40000001: 5784 *eax = 0; 5785 *ebx = 0; 5786 *ecx = 0; 5787 *edx = 0; 5788 break; 5789 case 0x80000000: 5790 *eax = env->cpuid_xlevel; 5791 *ebx = env->cpuid_vendor1; 5792 *edx = env->cpuid_vendor2; 5793 *ecx = env->cpuid_vendor3; 5794 break; 5795 case 0x80000001: 5796 *eax = env->cpuid_version; 5797 *ebx = 0; 5798 *ecx = env->features[FEAT_8000_0001_ECX]; 5799 *edx = env->features[FEAT_8000_0001_EDX]; 5800 5801 /* The Linux kernel checks for the CMPLegacy bit and 5802 * discards multiple thread information if it is set. 5803 * So don't set it here for Intel to make Linux guests happy. 5804 */ 5805 if (cs->nr_cores * cs->nr_threads > 1) { 5806 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 || 5807 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 || 5808 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) { 5809 *ecx |= 1 << 1; /* CmpLegacy bit */ 5810 } 5811 } 5812 break; 5813 case 0x80000002: 5814 case 0x80000003: 5815 case 0x80000004: 5816 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0]; 5817 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1]; 5818 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2]; 5819 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3]; 5820 break; 5821 case 0x80000005: 5822 /* cache info (L1 cache) */ 5823 if (cpu->cache_info_passthrough) { 5824 host_cpuid(index, 0, eax, ebx, ecx, edx); 5825 break; 5826 } 5827 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | 5828 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES); 5829 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | 5830 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES); 5831 *ecx = encode_cache_cpuid80000005(env->cache_info_amd.l1d_cache); 5832 *edx = encode_cache_cpuid80000005(env->cache_info_amd.l1i_cache); 5833 break; 5834 case 0x80000006: 5835 /* cache info (L2 cache) */ 5836 if (cpu->cache_info_passthrough) { 5837 host_cpuid(index, 0, eax, ebx, ecx, edx); 5838 break; 5839 } 5840 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | 5841 (L2_DTLB_2M_ENTRIES << 16) | 5842 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | 5843 (L2_ITLB_2M_ENTRIES); 5844 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | 5845 (L2_DTLB_4K_ENTRIES << 16) | 5846 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | 5847 (L2_ITLB_4K_ENTRIES); 5848 encode_cache_cpuid80000006(env->cache_info_amd.l2_cache, 5849 cpu->enable_l3_cache ? 5850 env->cache_info_amd.l3_cache : NULL, 5851 ecx, edx); 5852 break; 5853 case 0x80000007: 5854 *eax = 0; 5855 *ebx = 0; 5856 *ecx = 0; 5857 *edx = env->features[FEAT_8000_0007_EDX]; 5858 break; 5859 case 0x80000008: 5860 /* virtual & phys address size in low 2 bytes. */ 5861 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 5862 /* 64 bit processor */ 5863 *eax = cpu->phys_bits; /* configurable physical bits */ 5864 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57) { 5865 *eax |= 0x00003900; /* 57 bits virtual */ 5866 } else { 5867 *eax |= 0x00003000; /* 48 bits virtual */ 5868 } 5869 } else { 5870 *eax = cpu->phys_bits; 5871 } 5872 *ebx = env->features[FEAT_8000_0008_EBX]; 5873 if (cs->nr_cores * cs->nr_threads > 1) { 5874 /* 5875 * Bits 15:12 is "The number of bits in the initial 5876 * Core::X86::Apic::ApicId[ApicId] value that indicate 5877 * thread ID within a package". 5878 * Bits 7:0 is "The number of threads in the package is NC+1" 5879 */ 5880 *ecx = (apicid_pkg_offset(&topo_info) << 12) | 5881 ((cs->nr_cores * cs->nr_threads) - 1); 5882 } else { 5883 *ecx = 0; 5884 } 5885 *edx = 0; 5886 break; 5887 case 0x8000000A: 5888 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { 5889 *eax = 0x00000001; /* SVM Revision */ 5890 *ebx = 0x00000010; /* nr of ASIDs */ 5891 *ecx = 0; 5892 *edx = env->features[FEAT_SVM]; /* optional features */ 5893 } else { 5894 *eax = 0; 5895 *ebx = 0; 5896 *ecx = 0; 5897 *edx = 0; 5898 } 5899 break; 5900 case 0x8000001D: 5901 *eax = 0; 5902 if (cpu->cache_info_passthrough) { 5903 host_cpuid(index, count, eax, ebx, ecx, edx); 5904 break; 5905 } 5906 switch (count) { 5907 case 0: /* L1 dcache info */ 5908 encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache, 5909 &topo_info, eax, ebx, ecx, edx); 5910 break; 5911 case 1: /* L1 icache info */ 5912 encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache, 5913 &topo_info, eax, ebx, ecx, edx); 5914 break; 5915 case 2: /* L2 cache info */ 5916 encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache, 5917 &topo_info, eax, ebx, ecx, edx); 5918 break; 5919 case 3: /* L3 cache info */ 5920 encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache, 5921 &topo_info, eax, ebx, ecx, edx); 5922 break; 5923 default: /* end of info */ 5924 *eax = *ebx = *ecx = *edx = 0; 5925 break; 5926 } 5927 break; 5928 case 0x8000001E: 5929 if (cpu->core_id <= 255) { 5930 encode_topo_cpuid8000001e(cpu, &topo_info, eax, ebx, ecx, edx); 5931 } else { 5932 *eax = 0; 5933 *ebx = 0; 5934 *ecx = 0; 5935 *edx = 0; 5936 } 5937 break; 5938 case 0xC0000000: 5939 *eax = env->cpuid_xlevel2; 5940 *ebx = 0; 5941 *ecx = 0; 5942 *edx = 0; 5943 break; 5944 case 0xC0000001: 5945 /* Support for VIA CPU's CPUID instruction */ 5946 *eax = env->cpuid_version; 5947 *ebx = 0; 5948 *ecx = 0; 5949 *edx = env->features[FEAT_C000_0001_EDX]; 5950 break; 5951 case 0xC0000002: 5952 case 0xC0000003: 5953 case 0xC0000004: 5954 /* Reserved for the future, and now filled with zero */ 5955 *eax = 0; 5956 *ebx = 0; 5957 *ecx = 0; 5958 *edx = 0; 5959 break; 5960 case 0x8000001F: 5961 *eax = sev_enabled() ? 0x2 : 0; 5962 *ebx = sev_get_cbit_position(); 5963 *ebx |= sev_get_reduced_phys_bits() << 6; 5964 *ecx = 0; 5965 *edx = 0; 5966 break; 5967 default: 5968 /* reserved values: zero */ 5969 *eax = 0; 5970 *ebx = 0; 5971 *ecx = 0; 5972 *edx = 0; 5973 break; 5974 } 5975 } 5976 5977 static void x86_cpu_reset(DeviceState *dev) 5978 { 5979 CPUState *s = CPU(dev); 5980 X86CPU *cpu = X86_CPU(s); 5981 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu); 5982 CPUX86State *env = &cpu->env; 5983 target_ulong cr4; 5984 uint64_t xcr0; 5985 int i; 5986 5987 xcc->parent_reset(dev); 5988 5989 memset(env, 0, offsetof(CPUX86State, end_reset_fields)); 5990 5991 env->old_exception = -1; 5992 5993 /* init to reset state */ 5994 5995 env->hflags2 |= HF2_GIF_MASK; 5996 env->hflags &= ~HF_GUEST_MASK; 5997 5998 cpu_x86_update_cr0(env, 0x60000010); 5999 env->a20_mask = ~0x0; 6000 env->smbase = 0x30000; 6001 env->msr_smi_count = 0; 6002 6003 env->idt.limit = 0xffff; 6004 env->gdt.limit = 0xffff; 6005 env->ldt.limit = 0xffff; 6006 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT); 6007 env->tr.limit = 0xffff; 6008 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT); 6009 6010 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff, 6011 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK | 6012 DESC_R_MASK | DESC_A_MASK); 6013 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff, 6014 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 6015 DESC_A_MASK); 6016 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff, 6017 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 6018 DESC_A_MASK); 6019 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff, 6020 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 6021 DESC_A_MASK); 6022 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff, 6023 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 6024 DESC_A_MASK); 6025 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff, 6026 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 6027 DESC_A_MASK); 6028 6029 env->eip = 0xfff0; 6030 env->regs[R_EDX] = env->cpuid_version; 6031 6032 env->eflags = 0x2; 6033 6034 /* FPU init */ 6035 for (i = 0; i < 8; i++) { 6036 env->fptags[i] = 1; 6037 } 6038 cpu_set_fpuc(env, 0x37f); 6039 6040 env->mxcsr = 0x1f80; 6041 /* All units are in INIT state. */ 6042 env->xstate_bv = 0; 6043 6044 env->pat = 0x0007040600070406ULL; 6045 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT; 6046 if (env->features[FEAT_1_ECX] & CPUID_EXT_MONITOR) { 6047 env->msr_ia32_misc_enable |= MSR_IA32_MISC_ENABLE_MWAIT; 6048 } 6049 6050 memset(env->dr, 0, sizeof(env->dr)); 6051 env->dr[6] = DR6_FIXED_1; 6052 env->dr[7] = DR7_FIXED_1; 6053 cpu_breakpoint_remove_all(s, BP_CPU); 6054 cpu_watchpoint_remove_all(s, BP_CPU); 6055 6056 cr4 = 0; 6057 xcr0 = XSTATE_FP_MASK; 6058 6059 #ifdef CONFIG_USER_ONLY 6060 /* Enable all the features for user-mode. */ 6061 if (env->features[FEAT_1_EDX] & CPUID_SSE) { 6062 xcr0 |= XSTATE_SSE_MASK; 6063 } 6064 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 6065 const ExtSaveArea *esa = &x86_ext_save_areas[i]; 6066 if (env->features[esa->feature] & esa->bits) { 6067 xcr0 |= 1ull << i; 6068 } 6069 } 6070 6071 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) { 6072 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK; 6073 } 6074 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) { 6075 cr4 |= CR4_FSGSBASE_MASK; 6076 } 6077 #endif 6078 6079 env->xcr0 = xcr0; 6080 cpu_x86_update_cr4(env, cr4); 6081 6082 /* 6083 * SDM 11.11.5 requires: 6084 * - IA32_MTRR_DEF_TYPE MSR.E = 0 6085 * - IA32_MTRR_PHYSMASKn.V = 0 6086 * All other bits are undefined. For simplification, zero it all. 6087 */ 6088 env->mtrr_deftype = 0; 6089 memset(env->mtrr_var, 0, sizeof(env->mtrr_var)); 6090 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed)); 6091 6092 env->interrupt_injected = -1; 6093 env->exception_nr = -1; 6094 env->exception_pending = 0; 6095 env->exception_injected = 0; 6096 env->exception_has_payload = false; 6097 env->exception_payload = 0; 6098 env->nmi_injected = false; 6099 #if !defined(CONFIG_USER_ONLY) 6100 /* We hard-wire the BSP to the first CPU. */ 6101 apic_designate_bsp(cpu->apic_state, s->cpu_index == 0); 6102 6103 s->halted = !cpu_is_bsp(cpu); 6104 6105 if (kvm_enabled()) { 6106 kvm_arch_reset_vcpu(cpu); 6107 } 6108 #endif 6109 } 6110 6111 #ifndef CONFIG_USER_ONLY 6112 bool cpu_is_bsp(X86CPU *cpu) 6113 { 6114 return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP; 6115 } 6116 6117 /* TODO: remove me, when reset over QOM tree is implemented */ 6118 static void x86_cpu_machine_reset_cb(void *opaque) 6119 { 6120 X86CPU *cpu = opaque; 6121 cpu_reset(CPU(cpu)); 6122 } 6123 #endif 6124 6125 static void mce_init(X86CPU *cpu) 6126 { 6127 CPUX86State *cenv = &cpu->env; 6128 unsigned int bank; 6129 6130 if (((cenv->cpuid_version >> 8) & 0xf) >= 6 6131 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) == 6132 (CPUID_MCE | CPUID_MCA)) { 6133 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF | 6134 (cpu->enable_lmce ? MCG_LMCE_P : 0); 6135 cenv->mcg_ctl = ~(uint64_t)0; 6136 for (bank = 0; bank < MCE_BANKS_DEF; bank++) { 6137 cenv->mce_banks[bank * 4] = ~(uint64_t)0; 6138 } 6139 } 6140 } 6141 6142 #ifndef CONFIG_USER_ONLY 6143 APICCommonClass *apic_get_class(void) 6144 { 6145 const char *apic_type = "apic"; 6146 6147 /* TODO: in-kernel irqchip for hvf */ 6148 if (kvm_apic_in_kernel()) { 6149 apic_type = "kvm-apic"; 6150 } else if (xen_enabled()) { 6151 apic_type = "xen-apic"; 6152 } else if (whpx_apic_in_platform()) { 6153 apic_type = "whpx-apic"; 6154 } 6155 6156 return APIC_COMMON_CLASS(object_class_by_name(apic_type)); 6157 } 6158 6159 static void x86_cpu_apic_create(X86CPU *cpu, Error **errp) 6160 { 6161 APICCommonState *apic; 6162 ObjectClass *apic_class = OBJECT_CLASS(apic_get_class()); 6163 6164 cpu->apic_state = DEVICE(object_new_with_class(apic_class)); 6165 6166 object_property_add_child(OBJECT(cpu), "lapic", 6167 OBJECT(cpu->apic_state)); 6168 object_unref(OBJECT(cpu->apic_state)); 6169 6170 qdev_prop_set_uint32(cpu->apic_state, "id", cpu->apic_id); 6171 /* TODO: convert to link<> */ 6172 apic = APIC_COMMON(cpu->apic_state); 6173 apic->cpu = cpu; 6174 apic->apicbase = APIC_DEFAULT_ADDRESS | MSR_IA32_APICBASE_ENABLE; 6175 } 6176 6177 static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp) 6178 { 6179 APICCommonState *apic; 6180 static bool apic_mmio_map_once; 6181 6182 if (cpu->apic_state == NULL) { 6183 return; 6184 } 6185 qdev_realize(DEVICE(cpu->apic_state), NULL, errp); 6186 6187 /* Map APIC MMIO area */ 6188 apic = APIC_COMMON(cpu->apic_state); 6189 if (!apic_mmio_map_once) { 6190 memory_region_add_subregion_overlap(get_system_memory(), 6191 apic->apicbase & 6192 MSR_IA32_APICBASE_BASE, 6193 &apic->io_memory, 6194 0x1000); 6195 apic_mmio_map_once = true; 6196 } 6197 } 6198 6199 static void x86_cpu_machine_done(Notifier *n, void *unused) 6200 { 6201 X86CPU *cpu = container_of(n, X86CPU, machine_done); 6202 MemoryRegion *smram = 6203 (MemoryRegion *) object_resolve_path("/machine/smram", NULL); 6204 6205 if (smram) { 6206 cpu->smram = g_new(MemoryRegion, 1); 6207 memory_region_init_alias(cpu->smram, OBJECT(cpu), "smram", 6208 smram, 0, 4 * GiB); 6209 memory_region_set_enabled(cpu->smram, true); 6210 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->smram, 1); 6211 } 6212 } 6213 #else 6214 static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp) 6215 { 6216 } 6217 #endif 6218 6219 /* Note: Only safe for use on x86(-64) hosts */ 6220 static uint32_t x86_host_phys_bits(void) 6221 { 6222 uint32_t eax; 6223 uint32_t host_phys_bits; 6224 6225 host_cpuid(0x80000000, 0, &eax, NULL, NULL, NULL); 6226 if (eax >= 0x80000008) { 6227 host_cpuid(0x80000008, 0, &eax, NULL, NULL, NULL); 6228 /* Note: According to AMD doc 25481 rev 2.34 they have a field 6229 * at 23:16 that can specify a maximum physical address bits for 6230 * the guest that can override this value; but I've not seen 6231 * anything with that set. 6232 */ 6233 host_phys_bits = eax & 0xff; 6234 } else { 6235 /* It's an odd 64 bit machine that doesn't have the leaf for 6236 * physical address bits; fall back to 36 that's most older 6237 * Intel. 6238 */ 6239 host_phys_bits = 36; 6240 } 6241 6242 return host_phys_bits; 6243 } 6244 6245 static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value) 6246 { 6247 if (*min < value) { 6248 *min = value; 6249 } 6250 } 6251 6252 /* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */ 6253 static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w) 6254 { 6255 CPUX86State *env = &cpu->env; 6256 FeatureWordInfo *fi = &feature_word_info[w]; 6257 uint32_t eax = fi->cpuid.eax; 6258 uint32_t region = eax & 0xF0000000; 6259 6260 assert(feature_word_info[w].type == CPUID_FEATURE_WORD); 6261 if (!env->features[w]) { 6262 return; 6263 } 6264 6265 switch (region) { 6266 case 0x00000000: 6267 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax); 6268 break; 6269 case 0x80000000: 6270 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax); 6271 break; 6272 case 0xC0000000: 6273 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax); 6274 break; 6275 } 6276 6277 if (eax == 7) { 6278 x86_cpu_adjust_level(cpu, &env->cpuid_min_level_func7, 6279 fi->cpuid.ecx); 6280 } 6281 } 6282 6283 /* Calculate XSAVE components based on the configured CPU feature flags */ 6284 static void x86_cpu_enable_xsave_components(X86CPU *cpu) 6285 { 6286 CPUX86State *env = &cpu->env; 6287 int i; 6288 uint64_t mask; 6289 6290 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { 6291 env->features[FEAT_XSAVE_COMP_LO] = 0; 6292 env->features[FEAT_XSAVE_COMP_HI] = 0; 6293 return; 6294 } 6295 6296 mask = 0; 6297 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 6298 const ExtSaveArea *esa = &x86_ext_save_areas[i]; 6299 if (env->features[esa->feature] & esa->bits) { 6300 mask |= (1ULL << i); 6301 } 6302 } 6303 6304 env->features[FEAT_XSAVE_COMP_LO] = mask; 6305 env->features[FEAT_XSAVE_COMP_HI] = mask >> 32; 6306 } 6307 6308 /***** Steps involved on loading and filtering CPUID data 6309 * 6310 * When initializing and realizing a CPU object, the steps 6311 * involved in setting up CPUID data are: 6312 * 6313 * 1) Loading CPU model definition (X86CPUDefinition). This is 6314 * implemented by x86_cpu_load_model() and should be completely 6315 * transparent, as it is done automatically by instance_init. 6316 * No code should need to look at X86CPUDefinition structs 6317 * outside instance_init. 6318 * 6319 * 2) CPU expansion. This is done by realize before CPUID 6320 * filtering, and will make sure host/accelerator data is 6321 * loaded for CPU models that depend on host capabilities 6322 * (e.g. "host"). Done by x86_cpu_expand_features(). 6323 * 6324 * 3) CPUID filtering. This initializes extra data related to 6325 * CPUID, and checks if the host supports all capabilities 6326 * required by the CPU. Runnability of a CPU model is 6327 * determined at this step. Done by x86_cpu_filter_features(). 6328 * 6329 * Some operations don't require all steps to be performed. 6330 * More precisely: 6331 * 6332 * - CPU instance creation (instance_init) will run only CPU 6333 * model loading. CPU expansion can't run at instance_init-time 6334 * because host/accelerator data may be not available yet. 6335 * - CPU realization will perform both CPU model expansion and CPUID 6336 * filtering, and return an error in case one of them fails. 6337 * - query-cpu-definitions needs to run all 3 steps. It needs 6338 * to run CPUID filtering, as the 'unavailable-features' 6339 * field is set based on the filtering results. 6340 * - The query-cpu-model-expansion QMP command only needs to run 6341 * CPU model loading and CPU expansion. It should not filter 6342 * any CPUID data based on host capabilities. 6343 */ 6344 6345 /* Expand CPU configuration data, based on configured features 6346 * and host/accelerator capabilities when appropriate. 6347 */ 6348 static void x86_cpu_expand_features(X86CPU *cpu, Error **errp) 6349 { 6350 CPUX86State *env = &cpu->env; 6351 FeatureWord w; 6352 int i; 6353 GList *l; 6354 6355 for (l = plus_features; l; l = l->next) { 6356 const char *prop = l->data; 6357 if (!object_property_set_bool(OBJECT(cpu), prop, true, errp)) { 6358 return; 6359 } 6360 } 6361 6362 for (l = minus_features; l; l = l->next) { 6363 const char *prop = l->data; 6364 if (!object_property_set_bool(OBJECT(cpu), prop, false, errp)) { 6365 return; 6366 } 6367 } 6368 6369 /*TODO: Now cpu->max_features doesn't overwrite features 6370 * set using QOM properties, and we can convert 6371 * plus_features & minus_features to global properties 6372 * inside x86_cpu_parse_featurestr() too. 6373 */ 6374 if (cpu->max_features) { 6375 for (w = 0; w < FEATURE_WORDS; w++) { 6376 /* Override only features that weren't set explicitly 6377 * by the user. 6378 */ 6379 env->features[w] |= 6380 x86_cpu_get_supported_feature_word(w, cpu->migratable) & 6381 ~env->user_features[w] & 6382 ~feature_word_info[w].no_autoenable_flags; 6383 } 6384 } 6385 6386 for (i = 0; i < ARRAY_SIZE(feature_dependencies); i++) { 6387 FeatureDep *d = &feature_dependencies[i]; 6388 if (!(env->features[d->from.index] & d->from.mask)) { 6389 uint64_t unavailable_features = env->features[d->to.index] & d->to.mask; 6390 6391 /* Not an error unless the dependent feature was added explicitly. */ 6392 mark_unavailable_features(cpu, d->to.index, 6393 unavailable_features & env->user_features[d->to.index], 6394 "This feature depends on other features that were not requested"); 6395 6396 env->features[d->to.index] &= ~unavailable_features; 6397 } 6398 } 6399 6400 if (!kvm_enabled() || !cpu->expose_kvm) { 6401 env->features[FEAT_KVM] = 0; 6402 } 6403 6404 x86_cpu_enable_xsave_components(cpu); 6405 6406 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */ 6407 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX); 6408 if (cpu->full_cpuid_auto_level) { 6409 x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX); 6410 x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX); 6411 x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX); 6412 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX); 6413 x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EAX); 6414 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX); 6415 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX); 6416 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX); 6417 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0008_EBX); 6418 x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX); 6419 x86_cpu_adjust_feat_level(cpu, FEAT_SVM); 6420 x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE); 6421 6422 /* Intel Processor Trace requires CPUID[0x14] */ 6423 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT)) { 6424 if (cpu->intel_pt_auto_level) { 6425 x86_cpu_adjust_level(cpu, &cpu->env.cpuid_min_level, 0x14); 6426 } else if (cpu->env.cpuid_min_level < 0x14) { 6427 mark_unavailable_features(cpu, FEAT_7_0_EBX, 6428 CPUID_7_0_EBX_INTEL_PT, 6429 "Intel PT need CPUID leaf 0x14, please set by \"-cpu ...,+intel-pt,min-level=0x14\""); 6430 } 6431 } 6432 6433 /* CPU topology with multi-dies support requires CPUID[0x1F] */ 6434 if (env->nr_dies > 1) { 6435 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x1F); 6436 } 6437 6438 /* SVM requires CPUID[0x8000000A] */ 6439 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { 6440 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A); 6441 } 6442 6443 /* SEV requires CPUID[0x8000001F] */ 6444 if (sev_enabled()) { 6445 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F); 6446 } 6447 } 6448 6449 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */ 6450 if (env->cpuid_level_func7 == UINT32_MAX) { 6451 env->cpuid_level_func7 = env->cpuid_min_level_func7; 6452 } 6453 if (env->cpuid_level == UINT32_MAX) { 6454 env->cpuid_level = env->cpuid_min_level; 6455 } 6456 if (env->cpuid_xlevel == UINT32_MAX) { 6457 env->cpuid_xlevel = env->cpuid_min_xlevel; 6458 } 6459 if (env->cpuid_xlevel2 == UINT32_MAX) { 6460 env->cpuid_xlevel2 = env->cpuid_min_xlevel2; 6461 } 6462 } 6463 6464 /* 6465 * Finishes initialization of CPUID data, filters CPU feature 6466 * words based on host availability of each feature. 6467 * 6468 * Returns: 0 if all flags are supported by the host, non-zero otherwise. 6469 */ 6470 static void x86_cpu_filter_features(X86CPU *cpu, bool verbose) 6471 { 6472 CPUX86State *env = &cpu->env; 6473 FeatureWord w; 6474 const char *prefix = NULL; 6475 6476 if (verbose) { 6477 prefix = accel_uses_host_cpuid() 6478 ? "host doesn't support requested feature" 6479 : "TCG doesn't support requested feature"; 6480 } 6481 6482 for (w = 0; w < FEATURE_WORDS; w++) { 6483 uint64_t host_feat = 6484 x86_cpu_get_supported_feature_word(w, false); 6485 uint64_t requested_features = env->features[w]; 6486 uint64_t unavailable_features = requested_features & ~host_feat; 6487 mark_unavailable_features(cpu, w, unavailable_features, prefix); 6488 } 6489 6490 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) && 6491 kvm_enabled()) { 6492 KVMState *s = CPU(cpu)->kvm_state; 6493 uint32_t eax_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EAX); 6494 uint32_t ebx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EBX); 6495 uint32_t ecx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_ECX); 6496 uint32_t eax_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EAX); 6497 uint32_t ebx_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EBX); 6498 6499 if (!eax_0 || 6500 ((ebx_0 & INTEL_PT_MINIMAL_EBX) != INTEL_PT_MINIMAL_EBX) || 6501 ((ecx_0 & INTEL_PT_MINIMAL_ECX) != INTEL_PT_MINIMAL_ECX) || 6502 ((eax_1 & INTEL_PT_MTC_BITMAP) != INTEL_PT_MTC_BITMAP) || 6503 ((eax_1 & INTEL_PT_ADDR_RANGES_NUM_MASK) < 6504 INTEL_PT_ADDR_RANGES_NUM) || 6505 ((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) != 6506 (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) || 6507 (ecx_0 & INTEL_PT_IP_LIP)) { 6508 /* 6509 * Processor Trace capabilities aren't configurable, so if the 6510 * host can't emulate the capabilities we report on 6511 * cpu_x86_cpuid(), intel-pt can't be enabled on the current host. 6512 */ 6513 mark_unavailable_features(cpu, FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT, prefix); 6514 } 6515 } 6516 } 6517 6518 static void x86_cpu_realizefn(DeviceState *dev, Error **errp) 6519 { 6520 CPUState *cs = CPU(dev); 6521 X86CPU *cpu = X86_CPU(dev); 6522 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev); 6523 CPUX86State *env = &cpu->env; 6524 Error *local_err = NULL; 6525 static bool ht_warned; 6526 6527 if (xcc->host_cpuid_required) { 6528 if (!accel_uses_host_cpuid()) { 6529 g_autofree char *name = x86_cpu_class_get_model_name(xcc); 6530 error_setg(&local_err, "CPU model '%s' requires KVM", name); 6531 goto out; 6532 } 6533 } 6534 6535 if (cpu->max_features && accel_uses_host_cpuid()) { 6536 if (enable_cpu_pm) { 6537 host_cpuid(5, 0, &cpu->mwait.eax, &cpu->mwait.ebx, 6538 &cpu->mwait.ecx, &cpu->mwait.edx); 6539 env->features[FEAT_1_ECX] |= CPUID_EXT_MONITOR; 6540 if (kvm_enabled() && kvm_has_waitpkg()) { 6541 env->features[FEAT_7_0_ECX] |= CPUID_7_0_ECX_WAITPKG; 6542 } 6543 } 6544 if (kvm_enabled() && cpu->ucode_rev == 0) { 6545 cpu->ucode_rev = kvm_arch_get_supported_msr_feature(kvm_state, 6546 MSR_IA32_UCODE_REV); 6547 } 6548 } 6549 6550 if (cpu->ucode_rev == 0) { 6551 /* The default is the same as KVM's. */ 6552 if (IS_AMD_CPU(env)) { 6553 cpu->ucode_rev = 0x01000065; 6554 } else { 6555 cpu->ucode_rev = 0x100000000ULL; 6556 } 6557 } 6558 6559 /* mwait extended info: needed for Core compatibility */ 6560 /* We always wake on interrupt even if host does not have the capability */ 6561 cpu->mwait.ecx |= CPUID_MWAIT_EMX | CPUID_MWAIT_IBE; 6562 6563 if (cpu->apic_id == UNASSIGNED_APIC_ID) { 6564 error_setg(errp, "apic-id property was not initialized properly"); 6565 return; 6566 } 6567 6568 x86_cpu_expand_features(cpu, &local_err); 6569 if (local_err) { 6570 goto out; 6571 } 6572 6573 x86_cpu_filter_features(cpu, cpu->check_cpuid || cpu->enforce_cpuid); 6574 6575 if (cpu->enforce_cpuid && x86_cpu_have_filtered_features(cpu)) { 6576 error_setg(&local_err, 6577 accel_uses_host_cpuid() ? 6578 "Host doesn't support requested features" : 6579 "TCG doesn't support requested features"); 6580 goto out; 6581 } 6582 6583 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on 6584 * CPUID[1].EDX. 6585 */ 6586 if (IS_AMD_CPU(env)) { 6587 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES; 6588 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX] 6589 & CPUID_EXT2_AMD_ALIASES); 6590 } 6591 6592 /* For 64bit systems think about the number of physical bits to present. 6593 * ideally this should be the same as the host; anything other than matching 6594 * the host can cause incorrect guest behaviour. 6595 * QEMU used to pick the magic value of 40 bits that corresponds to 6596 * consumer AMD devices but nothing else. 6597 */ 6598 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 6599 if (accel_uses_host_cpuid()) { 6600 uint32_t host_phys_bits = x86_host_phys_bits(); 6601 static bool warned; 6602 6603 /* Print a warning if the user set it to a value that's not the 6604 * host value. 6605 */ 6606 if (cpu->phys_bits != host_phys_bits && cpu->phys_bits != 0 && 6607 !warned) { 6608 warn_report("Host physical bits (%u)" 6609 " does not match phys-bits property (%u)", 6610 host_phys_bits, cpu->phys_bits); 6611 warned = true; 6612 } 6613 6614 if (cpu->host_phys_bits) { 6615 /* The user asked for us to use the host physical bits */ 6616 cpu->phys_bits = host_phys_bits; 6617 if (cpu->host_phys_bits_limit && 6618 cpu->phys_bits > cpu->host_phys_bits_limit) { 6619 cpu->phys_bits = cpu->host_phys_bits_limit; 6620 } 6621 } 6622 6623 if (cpu->phys_bits && 6624 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS || 6625 cpu->phys_bits < 32)) { 6626 error_setg(errp, "phys-bits should be between 32 and %u " 6627 " (but is %u)", 6628 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits); 6629 return; 6630 } 6631 } else { 6632 if (cpu->phys_bits && cpu->phys_bits != TCG_PHYS_ADDR_BITS) { 6633 error_setg(errp, "TCG only supports phys-bits=%u", 6634 TCG_PHYS_ADDR_BITS); 6635 return; 6636 } 6637 } 6638 /* 0 means it was not explicitly set by the user (or by machine 6639 * compat_props or by the host code above). In this case, the default 6640 * is the value used by TCG (40). 6641 */ 6642 if (cpu->phys_bits == 0) { 6643 cpu->phys_bits = TCG_PHYS_ADDR_BITS; 6644 } 6645 } else { 6646 /* For 32 bit systems don't use the user set value, but keep 6647 * phys_bits consistent with what we tell the guest. 6648 */ 6649 if (cpu->phys_bits != 0) { 6650 error_setg(errp, "phys-bits is not user-configurable in 32 bit"); 6651 return; 6652 } 6653 6654 if (env->features[FEAT_1_EDX] & CPUID_PSE36) { 6655 cpu->phys_bits = 36; 6656 } else { 6657 cpu->phys_bits = 32; 6658 } 6659 } 6660 6661 /* Cache information initialization */ 6662 if (!cpu->legacy_cache) { 6663 if (!xcc->model || !xcc->model->cpudef->cache_info) { 6664 g_autofree char *name = x86_cpu_class_get_model_name(xcc); 6665 error_setg(errp, 6666 "CPU model '%s' doesn't support legacy-cache=off", name); 6667 return; 6668 } 6669 env->cache_info_cpuid2 = env->cache_info_cpuid4 = env->cache_info_amd = 6670 *xcc->model->cpudef->cache_info; 6671 } else { 6672 /* Build legacy cache information */ 6673 env->cache_info_cpuid2.l1d_cache = &legacy_l1d_cache; 6674 env->cache_info_cpuid2.l1i_cache = &legacy_l1i_cache; 6675 env->cache_info_cpuid2.l2_cache = &legacy_l2_cache_cpuid2; 6676 env->cache_info_cpuid2.l3_cache = &legacy_l3_cache; 6677 6678 env->cache_info_cpuid4.l1d_cache = &legacy_l1d_cache; 6679 env->cache_info_cpuid4.l1i_cache = &legacy_l1i_cache; 6680 env->cache_info_cpuid4.l2_cache = &legacy_l2_cache; 6681 env->cache_info_cpuid4.l3_cache = &legacy_l3_cache; 6682 6683 env->cache_info_amd.l1d_cache = &legacy_l1d_cache_amd; 6684 env->cache_info_amd.l1i_cache = &legacy_l1i_cache_amd; 6685 env->cache_info_amd.l2_cache = &legacy_l2_cache_amd; 6686 env->cache_info_amd.l3_cache = &legacy_l3_cache; 6687 } 6688 6689 6690 cpu_exec_realizefn(cs, &local_err); 6691 if (local_err != NULL) { 6692 error_propagate(errp, local_err); 6693 return; 6694 } 6695 6696 #ifndef CONFIG_USER_ONLY 6697 MachineState *ms = MACHINE(qdev_get_machine()); 6698 qemu_register_reset(x86_cpu_machine_reset_cb, cpu); 6699 6700 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || ms->smp.cpus > 1) { 6701 x86_cpu_apic_create(cpu, &local_err); 6702 if (local_err != NULL) { 6703 goto out; 6704 } 6705 } 6706 #endif 6707 6708 mce_init(cpu); 6709 6710 #ifndef CONFIG_USER_ONLY 6711 if (tcg_enabled()) { 6712 cpu->cpu_as_mem = g_new(MemoryRegion, 1); 6713 cpu->cpu_as_root = g_new(MemoryRegion, 1); 6714 6715 /* Outer container... */ 6716 memory_region_init(cpu->cpu_as_root, OBJECT(cpu), "memory", ~0ull); 6717 memory_region_set_enabled(cpu->cpu_as_root, true); 6718 6719 /* ... with two regions inside: normal system memory with low 6720 * priority, and... 6721 */ 6722 memory_region_init_alias(cpu->cpu_as_mem, OBJECT(cpu), "memory", 6723 get_system_memory(), 0, ~0ull); 6724 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->cpu_as_mem, 0); 6725 memory_region_set_enabled(cpu->cpu_as_mem, true); 6726 6727 cs->num_ases = 2; 6728 cpu_address_space_init(cs, 0, "cpu-memory", cs->memory); 6729 cpu_address_space_init(cs, 1, "cpu-smm", cpu->cpu_as_root); 6730 6731 /* ... SMRAM with higher priority, linked from /machine/smram. */ 6732 cpu->machine_done.notify = x86_cpu_machine_done; 6733 qemu_add_machine_init_done_notifier(&cpu->machine_done); 6734 } 6735 #endif 6736 6737 qemu_init_vcpu(cs); 6738 6739 /* 6740 * Most Intel and certain AMD CPUs support hyperthreading. Even though QEMU 6741 * fixes this issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX 6742 * based on inputs (sockets,cores,threads), it is still better to give 6743 * users a warning. 6744 * 6745 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise 6746 * cs->nr_threads hasn't be populated yet and the checking is incorrect. 6747 */ 6748 if (IS_AMD_CPU(env) && 6749 !(env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) && 6750 cs->nr_threads > 1 && !ht_warned) { 6751 warn_report("This family of AMD CPU doesn't support " 6752 "hyperthreading(%d)", 6753 cs->nr_threads); 6754 error_printf("Please configure -smp options properly" 6755 " or try enabling topoext feature.\n"); 6756 ht_warned = true; 6757 } 6758 6759 x86_cpu_apic_realize(cpu, &local_err); 6760 if (local_err != NULL) { 6761 goto out; 6762 } 6763 cpu_reset(cs); 6764 6765 xcc->parent_realize(dev, &local_err); 6766 6767 out: 6768 if (local_err != NULL) { 6769 error_propagate(errp, local_err); 6770 return; 6771 } 6772 } 6773 6774 static void x86_cpu_unrealizefn(DeviceState *dev) 6775 { 6776 X86CPU *cpu = X86_CPU(dev); 6777 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev); 6778 6779 #ifndef CONFIG_USER_ONLY 6780 cpu_remove_sync(CPU(dev)); 6781 qemu_unregister_reset(x86_cpu_machine_reset_cb, dev); 6782 #endif 6783 6784 if (cpu->apic_state) { 6785 object_unparent(OBJECT(cpu->apic_state)); 6786 cpu->apic_state = NULL; 6787 } 6788 6789 xcc->parent_unrealize(dev); 6790 } 6791 6792 typedef struct BitProperty { 6793 FeatureWord w; 6794 uint64_t mask; 6795 } BitProperty; 6796 6797 static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name, 6798 void *opaque, Error **errp) 6799 { 6800 X86CPU *cpu = X86_CPU(obj); 6801 BitProperty *fp = opaque; 6802 uint64_t f = cpu->env.features[fp->w]; 6803 bool value = (f & fp->mask) == fp->mask; 6804 visit_type_bool(v, name, &value, errp); 6805 } 6806 6807 static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name, 6808 void *opaque, Error **errp) 6809 { 6810 DeviceState *dev = DEVICE(obj); 6811 X86CPU *cpu = X86_CPU(obj); 6812 BitProperty *fp = opaque; 6813 bool value; 6814 6815 if (dev->realized) { 6816 qdev_prop_set_after_realize(dev, name, errp); 6817 return; 6818 } 6819 6820 if (!visit_type_bool(v, name, &value, errp)) { 6821 return; 6822 } 6823 6824 if (value) { 6825 cpu->env.features[fp->w] |= fp->mask; 6826 } else { 6827 cpu->env.features[fp->w] &= ~fp->mask; 6828 } 6829 cpu->env.user_features[fp->w] |= fp->mask; 6830 } 6831 6832 static void x86_cpu_release_bit_prop(Object *obj, const char *name, 6833 void *opaque) 6834 { 6835 BitProperty *prop = opaque; 6836 g_free(prop); 6837 } 6838 6839 /* Register a boolean property to get/set a single bit in a uint32_t field. 6840 * 6841 * The same property name can be registered multiple times to make it affect 6842 * multiple bits in the same FeatureWord. In that case, the getter will return 6843 * true only if all bits are set. 6844 */ 6845 static void x86_cpu_register_bit_prop(X86CPU *cpu, 6846 const char *prop_name, 6847 FeatureWord w, 6848 int bitnr) 6849 { 6850 BitProperty *fp; 6851 ObjectProperty *op; 6852 uint64_t mask = (1ULL << bitnr); 6853 6854 op = object_property_find(OBJECT(cpu), prop_name); 6855 if (op) { 6856 fp = op->opaque; 6857 assert(fp->w == w); 6858 fp->mask |= mask; 6859 } else { 6860 fp = g_new0(BitProperty, 1); 6861 fp->w = w; 6862 fp->mask = mask; 6863 object_property_add(OBJECT(cpu), prop_name, "bool", 6864 x86_cpu_get_bit_prop, 6865 x86_cpu_set_bit_prop, 6866 x86_cpu_release_bit_prop, fp); 6867 } 6868 } 6869 6870 static void x86_cpu_register_feature_bit_props(X86CPU *cpu, 6871 FeatureWord w, 6872 int bitnr) 6873 { 6874 FeatureWordInfo *fi = &feature_word_info[w]; 6875 const char *name = fi->feat_names[bitnr]; 6876 6877 if (!name) { 6878 return; 6879 } 6880 6881 /* Property names should use "-" instead of "_". 6882 * Old names containing underscores are registered as aliases 6883 * using object_property_add_alias() 6884 */ 6885 assert(!strchr(name, '_')); 6886 /* aliases don't use "|" delimiters anymore, they are registered 6887 * manually using object_property_add_alias() */ 6888 assert(!strchr(name, '|')); 6889 x86_cpu_register_bit_prop(cpu, name, w, bitnr); 6890 } 6891 6892 #if !defined(CONFIG_USER_ONLY) 6893 static GuestPanicInformation *x86_cpu_get_crash_info(CPUState *cs) 6894 { 6895 X86CPU *cpu = X86_CPU(cs); 6896 CPUX86State *env = &cpu->env; 6897 GuestPanicInformation *panic_info = NULL; 6898 6899 if (env->features[FEAT_HYPERV_EDX] & HV_GUEST_CRASH_MSR_AVAILABLE) { 6900 panic_info = g_malloc0(sizeof(GuestPanicInformation)); 6901 6902 panic_info->type = GUEST_PANIC_INFORMATION_TYPE_HYPER_V; 6903 6904 assert(HV_CRASH_PARAMS >= 5); 6905 panic_info->u.hyper_v.arg1 = env->msr_hv_crash_params[0]; 6906 panic_info->u.hyper_v.arg2 = env->msr_hv_crash_params[1]; 6907 panic_info->u.hyper_v.arg3 = env->msr_hv_crash_params[2]; 6908 panic_info->u.hyper_v.arg4 = env->msr_hv_crash_params[3]; 6909 panic_info->u.hyper_v.arg5 = env->msr_hv_crash_params[4]; 6910 } 6911 6912 return panic_info; 6913 } 6914 static void x86_cpu_get_crash_info_qom(Object *obj, Visitor *v, 6915 const char *name, void *opaque, 6916 Error **errp) 6917 { 6918 CPUState *cs = CPU(obj); 6919 GuestPanicInformation *panic_info; 6920 6921 if (!cs->crash_occurred) { 6922 error_setg(errp, "No crash occured"); 6923 return; 6924 } 6925 6926 panic_info = x86_cpu_get_crash_info(cs); 6927 if (panic_info == NULL) { 6928 error_setg(errp, "No crash information"); 6929 return; 6930 } 6931 6932 visit_type_GuestPanicInformation(v, "crash-information", &panic_info, 6933 errp); 6934 qapi_free_GuestPanicInformation(panic_info); 6935 } 6936 #endif /* !CONFIG_USER_ONLY */ 6937 6938 static void x86_cpu_initfn(Object *obj) 6939 { 6940 X86CPU *cpu = X86_CPU(obj); 6941 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj); 6942 CPUX86State *env = &cpu->env; 6943 FeatureWord w; 6944 6945 env->nr_dies = 1; 6946 cpu_set_cpustate_pointers(cpu); 6947 6948 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo", 6949 x86_cpu_get_feature_words, 6950 NULL, NULL, (void *)env->features); 6951 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo", 6952 x86_cpu_get_feature_words, 6953 NULL, NULL, (void *)cpu->filtered_features); 6954 6955 for (w = 0; w < FEATURE_WORDS; w++) { 6956 int bitnr; 6957 6958 for (bitnr = 0; bitnr < 64; bitnr++) { 6959 x86_cpu_register_feature_bit_props(cpu, w, bitnr); 6960 } 6961 } 6962 6963 object_property_add_alias(obj, "sse3", obj, "pni"); 6964 object_property_add_alias(obj, "pclmuldq", obj, "pclmulqdq"); 6965 object_property_add_alias(obj, "sse4-1", obj, "sse4.1"); 6966 object_property_add_alias(obj, "sse4-2", obj, "sse4.2"); 6967 object_property_add_alias(obj, "xd", obj, "nx"); 6968 object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt"); 6969 object_property_add_alias(obj, "i64", obj, "lm"); 6970 6971 object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl"); 6972 object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust"); 6973 object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt"); 6974 object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm"); 6975 object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy"); 6976 object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr"); 6977 object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core"); 6978 object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb"); 6979 object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay"); 6980 object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu"); 6981 object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf"); 6982 object_property_add_alias(obj, "kvm_asyncpf_int", obj, "kvm-asyncpf-int"); 6983 object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time"); 6984 object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi"); 6985 object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt"); 6986 object_property_add_alias(obj, "kvm_poll_control", obj, "kvm-poll-control"); 6987 object_property_add_alias(obj, "svm_lock", obj, "svm-lock"); 6988 object_property_add_alias(obj, "nrip_save", obj, "nrip-save"); 6989 object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale"); 6990 object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean"); 6991 object_property_add_alias(obj, "pause_filter", obj, "pause-filter"); 6992 object_property_add_alias(obj, "sse4_1", obj, "sse4.1"); 6993 object_property_add_alias(obj, "sse4_2", obj, "sse4.2"); 6994 6995 if (xcc->model) { 6996 x86_cpu_load_model(cpu, xcc->model); 6997 } 6998 } 6999 7000 static int64_t x86_cpu_get_arch_id(CPUState *cs) 7001 { 7002 X86CPU *cpu = X86_CPU(cs); 7003 7004 return cpu->apic_id; 7005 } 7006 7007 static bool x86_cpu_get_paging_enabled(const CPUState *cs) 7008 { 7009 X86CPU *cpu = X86_CPU(cs); 7010 7011 return cpu->env.cr[0] & CR0_PG_MASK; 7012 } 7013 7014 static void x86_cpu_set_pc(CPUState *cs, vaddr value) 7015 { 7016 X86CPU *cpu = X86_CPU(cs); 7017 7018 cpu->env.eip = value; 7019 } 7020 7021 static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) 7022 { 7023 X86CPU *cpu = X86_CPU(cs); 7024 7025 cpu->env.eip = tb->pc - tb->cs_base; 7026 } 7027 7028 int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request) 7029 { 7030 X86CPU *cpu = X86_CPU(cs); 7031 CPUX86State *env = &cpu->env; 7032 7033 #if !defined(CONFIG_USER_ONLY) 7034 if (interrupt_request & CPU_INTERRUPT_POLL) { 7035 return CPU_INTERRUPT_POLL; 7036 } 7037 #endif 7038 if (interrupt_request & CPU_INTERRUPT_SIPI) { 7039 return CPU_INTERRUPT_SIPI; 7040 } 7041 7042 if (env->hflags2 & HF2_GIF_MASK) { 7043 if ((interrupt_request & CPU_INTERRUPT_SMI) && 7044 !(env->hflags & HF_SMM_MASK)) { 7045 return CPU_INTERRUPT_SMI; 7046 } else if ((interrupt_request & CPU_INTERRUPT_NMI) && 7047 !(env->hflags2 & HF2_NMI_MASK)) { 7048 return CPU_INTERRUPT_NMI; 7049 } else if (interrupt_request & CPU_INTERRUPT_MCE) { 7050 return CPU_INTERRUPT_MCE; 7051 } else if ((interrupt_request & CPU_INTERRUPT_HARD) && 7052 (((env->hflags2 & HF2_VINTR_MASK) && 7053 (env->hflags2 & HF2_HIF_MASK)) || 7054 (!(env->hflags2 & HF2_VINTR_MASK) && 7055 (env->eflags & IF_MASK && 7056 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) { 7057 return CPU_INTERRUPT_HARD; 7058 #if !defined(CONFIG_USER_ONLY) 7059 } else if ((interrupt_request & CPU_INTERRUPT_VIRQ) && 7060 (env->eflags & IF_MASK) && 7061 !(env->hflags & HF_INHIBIT_IRQ_MASK)) { 7062 return CPU_INTERRUPT_VIRQ; 7063 #endif 7064 } 7065 } 7066 7067 return 0; 7068 } 7069 7070 static bool x86_cpu_has_work(CPUState *cs) 7071 { 7072 return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0; 7073 } 7074 7075 static void x86_disas_set_info(CPUState *cs, disassemble_info *info) 7076 { 7077 X86CPU *cpu = X86_CPU(cs); 7078 CPUX86State *env = &cpu->env; 7079 7080 info->mach = (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64 7081 : env->hflags & HF_CS32_MASK ? bfd_mach_i386_i386 7082 : bfd_mach_i386_i8086); 7083 info->print_insn = print_insn_i386; 7084 7085 info->cap_arch = CS_ARCH_X86; 7086 info->cap_mode = (env->hflags & HF_CS64_MASK ? CS_MODE_64 7087 : env->hflags & HF_CS32_MASK ? CS_MODE_32 7088 : CS_MODE_16); 7089 info->cap_insn_unit = 1; 7090 info->cap_insn_split = 8; 7091 } 7092 7093 void x86_update_hflags(CPUX86State *env) 7094 { 7095 uint32_t hflags; 7096 #define HFLAG_COPY_MASK \ 7097 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \ 7098 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \ 7099 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \ 7100 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK) 7101 7102 hflags = env->hflags & HFLAG_COPY_MASK; 7103 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK; 7104 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT); 7105 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) & 7106 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK); 7107 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK)); 7108 7109 if (env->cr[4] & CR4_OSFXSR_MASK) { 7110 hflags |= HF_OSFXSR_MASK; 7111 } 7112 7113 if (env->efer & MSR_EFER_LMA) { 7114 hflags |= HF_LMA_MASK; 7115 } 7116 7117 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) { 7118 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; 7119 } else { 7120 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >> 7121 (DESC_B_SHIFT - HF_CS32_SHIFT); 7122 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >> 7123 (DESC_B_SHIFT - HF_SS32_SHIFT); 7124 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) || 7125 !(hflags & HF_CS32_MASK)) { 7126 hflags |= HF_ADDSEG_MASK; 7127 } else { 7128 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base | 7129 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT; 7130 } 7131 } 7132 env->hflags = hflags; 7133 } 7134 7135 static Property x86_cpu_properties[] = { 7136 #ifdef CONFIG_USER_ONLY 7137 /* apic_id = 0 by default for *-user, see commit 9886e834 */ 7138 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0), 7139 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0), 7140 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0), 7141 DEFINE_PROP_INT32("die-id", X86CPU, die_id, 0), 7142 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0), 7143 #else 7144 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID), 7145 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1), 7146 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1), 7147 DEFINE_PROP_INT32("die-id", X86CPU, die_id, -1), 7148 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1), 7149 #endif 7150 DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID), 7151 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false), 7152 7153 DEFINE_PROP_UINT32("hv-spinlocks", X86CPU, hyperv_spinlock_attempts, 7154 HYPERV_SPINLOCK_NEVER_NOTIFY), 7155 DEFINE_PROP_BIT64("hv-relaxed", X86CPU, hyperv_features, 7156 HYPERV_FEAT_RELAXED, 0), 7157 DEFINE_PROP_BIT64("hv-vapic", X86CPU, hyperv_features, 7158 HYPERV_FEAT_VAPIC, 0), 7159 DEFINE_PROP_BIT64("hv-time", X86CPU, hyperv_features, 7160 HYPERV_FEAT_TIME, 0), 7161 DEFINE_PROP_BIT64("hv-crash", X86CPU, hyperv_features, 7162 HYPERV_FEAT_CRASH, 0), 7163 DEFINE_PROP_BIT64("hv-reset", X86CPU, hyperv_features, 7164 HYPERV_FEAT_RESET, 0), 7165 DEFINE_PROP_BIT64("hv-vpindex", X86CPU, hyperv_features, 7166 HYPERV_FEAT_VPINDEX, 0), 7167 DEFINE_PROP_BIT64("hv-runtime", X86CPU, hyperv_features, 7168 HYPERV_FEAT_RUNTIME, 0), 7169 DEFINE_PROP_BIT64("hv-synic", X86CPU, hyperv_features, 7170 HYPERV_FEAT_SYNIC, 0), 7171 DEFINE_PROP_BIT64("hv-stimer", X86CPU, hyperv_features, 7172 HYPERV_FEAT_STIMER, 0), 7173 DEFINE_PROP_BIT64("hv-frequencies", X86CPU, hyperv_features, 7174 HYPERV_FEAT_FREQUENCIES, 0), 7175 DEFINE_PROP_BIT64("hv-reenlightenment", X86CPU, hyperv_features, 7176 HYPERV_FEAT_REENLIGHTENMENT, 0), 7177 DEFINE_PROP_BIT64("hv-tlbflush", X86CPU, hyperv_features, 7178 HYPERV_FEAT_TLBFLUSH, 0), 7179 DEFINE_PROP_BIT64("hv-evmcs", X86CPU, hyperv_features, 7180 HYPERV_FEAT_EVMCS, 0), 7181 DEFINE_PROP_BIT64("hv-ipi", X86CPU, hyperv_features, 7182 HYPERV_FEAT_IPI, 0), 7183 DEFINE_PROP_BIT64("hv-stimer-direct", X86CPU, hyperv_features, 7184 HYPERV_FEAT_STIMER_DIRECT, 0), 7185 DEFINE_PROP_ON_OFF_AUTO("hv-no-nonarch-coresharing", X86CPU, 7186 hyperv_no_nonarch_cs, ON_OFF_AUTO_OFF), 7187 DEFINE_PROP_BOOL("hv-passthrough", X86CPU, hyperv_passthrough, false), 7188 7189 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true), 7190 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false), 7191 DEFINE_PROP_BOOL("x-force-features", X86CPU, force_features, false), 7192 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true), 7193 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0), 7194 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false), 7195 DEFINE_PROP_UINT8("host-phys-bits-limit", X86CPU, host_phys_bits_limit, 0), 7196 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true), 7197 DEFINE_PROP_UINT32("level-func7", X86CPU, env.cpuid_level_func7, 7198 UINT32_MAX), 7199 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX), 7200 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX), 7201 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX), 7202 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0), 7203 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0), 7204 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0), 7205 DEFINE_PROP_UINT64("ucode-rev", X86CPU, ucode_rev, 0), 7206 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true), 7207 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor_id), 7208 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true), 7209 DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false), 7210 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true), 7211 DEFINE_PROP_BOOL("kvm-no-smi-migration", X86CPU, kvm_no_smi_migration, 7212 false), 7213 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true), 7214 DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true), 7215 DEFINE_PROP_BOOL("x-migrate-smi-count", X86CPU, migrate_smi_count, 7216 true), 7217 /* 7218 * lecacy_cache defaults to true unless the CPU model provides its 7219 * own cache information (see x86_cpu_load_def()). 7220 */ 7221 DEFINE_PROP_BOOL("legacy-cache", X86CPU, legacy_cache, true), 7222 7223 /* 7224 * From "Requirements for Implementing the Microsoft 7225 * Hypervisor Interface": 7226 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs 7227 * 7228 * "Starting with Windows Server 2012 and Windows 8, if 7229 * CPUID.40000005.EAX contains a value of -1, Windows assumes that 7230 * the hypervisor imposes no specific limit to the number of VPs. 7231 * In this case, Windows Server 2012 guest VMs may use more than 7232 * 64 VPs, up to the maximum supported number of processors applicable 7233 * to the specific Windows version being used." 7234 */ 7235 DEFINE_PROP_INT32("x-hv-max-vps", X86CPU, hv_max_vps, -1), 7236 DEFINE_PROP_BOOL("x-hv-synic-kvm-only", X86CPU, hyperv_synic_kvm_only, 7237 false), 7238 DEFINE_PROP_BOOL("x-intel-pt-auto-level", X86CPU, intel_pt_auto_level, 7239 true), 7240 DEFINE_PROP_END_OF_LIST() 7241 }; 7242 7243 static void x86_cpu_common_class_init(ObjectClass *oc, void *data) 7244 { 7245 X86CPUClass *xcc = X86_CPU_CLASS(oc); 7246 CPUClass *cc = CPU_CLASS(oc); 7247 DeviceClass *dc = DEVICE_CLASS(oc); 7248 7249 device_class_set_parent_realize(dc, x86_cpu_realizefn, 7250 &xcc->parent_realize); 7251 device_class_set_parent_unrealize(dc, x86_cpu_unrealizefn, 7252 &xcc->parent_unrealize); 7253 device_class_set_props(dc, x86_cpu_properties); 7254 7255 device_class_set_parent_reset(dc, x86_cpu_reset, &xcc->parent_reset); 7256 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP; 7257 7258 cc->class_by_name = x86_cpu_class_by_name; 7259 cc->parse_features = x86_cpu_parse_featurestr; 7260 cc->has_work = x86_cpu_has_work; 7261 #ifdef CONFIG_TCG 7262 cc->do_interrupt = x86_cpu_do_interrupt; 7263 cc->cpu_exec_interrupt = x86_cpu_exec_interrupt; 7264 #endif 7265 cc->dump_state = x86_cpu_dump_state; 7266 cc->set_pc = x86_cpu_set_pc; 7267 cc->synchronize_from_tb = x86_cpu_synchronize_from_tb; 7268 cc->gdb_read_register = x86_cpu_gdb_read_register; 7269 cc->gdb_write_register = x86_cpu_gdb_write_register; 7270 cc->get_arch_id = x86_cpu_get_arch_id; 7271 cc->get_paging_enabled = x86_cpu_get_paging_enabled; 7272 #ifndef CONFIG_USER_ONLY 7273 cc->asidx_from_attrs = x86_asidx_from_attrs; 7274 cc->get_memory_mapping = x86_cpu_get_memory_mapping; 7275 cc->get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug; 7276 cc->get_crash_info = x86_cpu_get_crash_info; 7277 cc->write_elf64_note = x86_cpu_write_elf64_note; 7278 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote; 7279 cc->write_elf32_note = x86_cpu_write_elf32_note; 7280 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote; 7281 cc->vmsd = &vmstate_x86_cpu; 7282 #endif 7283 cc->gdb_arch_name = x86_gdb_arch_name; 7284 #ifdef TARGET_X86_64 7285 cc->gdb_core_xml_file = "i386-64bit.xml"; 7286 cc->gdb_num_core_regs = 66; 7287 #else 7288 cc->gdb_core_xml_file = "i386-32bit.xml"; 7289 cc->gdb_num_core_regs = 50; 7290 #endif 7291 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) 7292 cc->debug_excp_handler = breakpoint_handler; 7293 #endif 7294 cc->cpu_exec_enter = x86_cpu_exec_enter; 7295 cc->cpu_exec_exit = x86_cpu_exec_exit; 7296 #ifdef CONFIG_TCG 7297 cc->tcg_initialize = tcg_x86_init; 7298 cc->tlb_fill = x86_cpu_tlb_fill; 7299 #endif 7300 cc->disas_set_info = x86_disas_set_info; 7301 7302 dc->user_creatable = true; 7303 7304 object_class_property_add(oc, "family", "int", 7305 x86_cpuid_version_get_family, 7306 x86_cpuid_version_set_family, NULL, NULL); 7307 object_class_property_add(oc, "model", "int", 7308 x86_cpuid_version_get_model, 7309 x86_cpuid_version_set_model, NULL, NULL); 7310 object_class_property_add(oc, "stepping", "int", 7311 x86_cpuid_version_get_stepping, 7312 x86_cpuid_version_set_stepping, NULL, NULL); 7313 object_class_property_add_str(oc, "vendor", 7314 x86_cpuid_get_vendor, 7315 x86_cpuid_set_vendor); 7316 object_class_property_add_str(oc, "model-id", 7317 x86_cpuid_get_model_id, 7318 x86_cpuid_set_model_id); 7319 object_class_property_add(oc, "tsc-frequency", "int", 7320 x86_cpuid_get_tsc_freq, 7321 x86_cpuid_set_tsc_freq, NULL, NULL); 7322 /* 7323 * The "unavailable-features" property has the same semantics as 7324 * CpuDefinitionInfo.unavailable-features on the "query-cpu-definitions" 7325 * QMP command: they list the features that would have prevented the 7326 * CPU from running if the "enforce" flag was set. 7327 */ 7328 object_class_property_add(oc, "unavailable-features", "strList", 7329 x86_cpu_get_unavailable_features, 7330 NULL, NULL, NULL); 7331 7332 #if !defined(CONFIG_USER_ONLY) 7333 object_class_property_add(oc, "crash-information", "GuestPanicInformation", 7334 x86_cpu_get_crash_info_qom, NULL, NULL, NULL); 7335 #endif 7336 7337 } 7338 7339 static const TypeInfo x86_cpu_type_info = { 7340 .name = TYPE_X86_CPU, 7341 .parent = TYPE_CPU, 7342 .instance_size = sizeof(X86CPU), 7343 .instance_init = x86_cpu_initfn, 7344 .abstract = true, 7345 .class_size = sizeof(X86CPUClass), 7346 .class_init = x86_cpu_common_class_init, 7347 }; 7348 7349 7350 /* "base" CPU model, used by query-cpu-model-expansion */ 7351 static void x86_cpu_base_class_init(ObjectClass *oc, void *data) 7352 { 7353 X86CPUClass *xcc = X86_CPU_CLASS(oc); 7354 7355 xcc->static_model = true; 7356 xcc->migration_safe = true; 7357 xcc->model_description = "base CPU model type with no features enabled"; 7358 xcc->ordering = 8; 7359 } 7360 7361 static const TypeInfo x86_base_cpu_type_info = { 7362 .name = X86_CPU_TYPE_NAME("base"), 7363 .parent = TYPE_X86_CPU, 7364 .class_init = x86_cpu_base_class_init, 7365 }; 7366 7367 static void x86_cpu_register_types(void) 7368 { 7369 int i; 7370 7371 type_register_static(&x86_cpu_type_info); 7372 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) { 7373 x86_register_cpudef_types(&builtin_x86_defs[i]); 7374 } 7375 type_register_static(&max_x86_cpu_type_info); 7376 type_register_static(&x86_base_cpu_type_info); 7377 #if defined(CONFIG_KVM) || defined(CONFIG_HVF) 7378 type_register_static(&host_x86_cpu_type_info); 7379 #endif 7380 } 7381 7382 type_init(x86_cpu_register_types) 7383