1 /* 2 * i386 CPUID helper functions 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/units.h" 22 #include "qemu/cutils.h" 23 #include "qemu/bitops.h" 24 #include "qemu/qemu-print.h" 25 26 #include "cpu.h" 27 #include "exec/exec-all.h" 28 #include "sysemu/kvm.h" 29 #include "sysemu/reset.h" 30 #include "sysemu/hvf.h" 31 #include "sysemu/cpus.h" 32 #include "kvm_i386.h" 33 #include "sev_i386.h" 34 35 #include "qemu/error-report.h" 36 #include "qemu/module.h" 37 #include "qemu/option.h" 38 #include "qemu/config-file.h" 39 #include "qapi/error.h" 40 #include "qapi/qapi-visit-machine.h" 41 #include "qapi/qapi-visit-run-state.h" 42 #include "qapi/qmp/qdict.h" 43 #include "qapi/qmp/qerror.h" 44 #include "qapi/visitor.h" 45 #include "qom/qom-qobject.h" 46 #include "sysemu/arch_init.h" 47 #include "qapi/qapi-commands-machine-target.h" 48 49 #include "standard-headers/asm-x86/kvm_para.h" 50 51 #include "sysemu/sysemu.h" 52 #include "sysemu/tcg.h" 53 #include "hw/qdev-properties.h" 54 #include "hw/i386/topology.h" 55 #ifndef CONFIG_USER_ONLY 56 #include "exec/address-spaces.h" 57 #include "hw/xen/xen.h" 58 #include "hw/i386/apic_internal.h" 59 #include "hw/boards.h" 60 #endif 61 62 #include "disas/capstone.h" 63 64 /* Helpers for building CPUID[2] descriptors: */ 65 66 struct CPUID2CacheDescriptorInfo { 67 enum CacheType type; 68 int level; 69 int size; 70 int line_size; 71 int associativity; 72 }; 73 74 /* 75 * Known CPUID 2 cache descriptors. 76 * From Intel SDM Volume 2A, CPUID instruction 77 */ 78 struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = { 79 [0x06] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 8 * KiB, 80 .associativity = 4, .line_size = 32, }, 81 [0x08] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 16 * KiB, 82 .associativity = 4, .line_size = 32, }, 83 [0x09] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB, 84 .associativity = 4, .line_size = 64, }, 85 [0x0A] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB, 86 .associativity = 2, .line_size = 32, }, 87 [0x0C] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 88 .associativity = 4, .line_size = 32, }, 89 [0x0D] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 90 .associativity = 4, .line_size = 64, }, 91 [0x0E] = { .level = 1, .type = DATA_CACHE, .size = 24 * KiB, 92 .associativity = 6, .line_size = 64, }, 93 [0x1D] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB, 94 .associativity = 2, .line_size = 64, }, 95 [0x21] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 96 .associativity = 8, .line_size = 64, }, 97 /* lines per sector is not supported cpuid2_cache_descriptor(), 98 * so descriptors 0x22, 0x23 are not included 99 */ 100 [0x24] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 101 .associativity = 16, .line_size = 64, }, 102 /* lines per sector is not supported cpuid2_cache_descriptor(), 103 * so descriptors 0x25, 0x20 are not included 104 */ 105 [0x2C] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB, 106 .associativity = 8, .line_size = 64, }, 107 [0x30] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB, 108 .associativity = 8, .line_size = 64, }, 109 [0x41] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB, 110 .associativity = 4, .line_size = 32, }, 111 [0x42] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 112 .associativity = 4, .line_size = 32, }, 113 [0x43] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 114 .associativity = 4, .line_size = 32, }, 115 [0x44] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 116 .associativity = 4, .line_size = 32, }, 117 [0x45] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 118 .associativity = 4, .line_size = 32, }, 119 [0x46] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 120 .associativity = 4, .line_size = 64, }, 121 [0x47] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 122 .associativity = 8, .line_size = 64, }, 123 [0x48] = { .level = 2, .type = UNIFIED_CACHE, .size = 3 * MiB, 124 .associativity = 12, .line_size = 64, }, 125 /* Descriptor 0x49 depends on CPU family/model, so it is not included */ 126 [0x4A] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB, 127 .associativity = 12, .line_size = 64, }, 128 [0x4B] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 129 .associativity = 16, .line_size = 64, }, 130 [0x4C] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB, 131 .associativity = 12, .line_size = 64, }, 132 [0x4D] = { .level = 3, .type = UNIFIED_CACHE, .size = 16 * MiB, 133 .associativity = 16, .line_size = 64, }, 134 [0x4E] = { .level = 2, .type = UNIFIED_CACHE, .size = 6 * MiB, 135 .associativity = 24, .line_size = 64, }, 136 [0x60] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 137 .associativity = 8, .line_size = 64, }, 138 [0x66] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB, 139 .associativity = 4, .line_size = 64, }, 140 [0x67] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 141 .associativity = 4, .line_size = 64, }, 142 [0x68] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB, 143 .associativity = 4, .line_size = 64, }, 144 [0x78] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 145 .associativity = 4, .line_size = 64, }, 146 /* lines per sector is not supported cpuid2_cache_descriptor(), 147 * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included. 148 */ 149 [0x7D] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 150 .associativity = 8, .line_size = 64, }, 151 [0x7F] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 152 .associativity = 2, .line_size = 64, }, 153 [0x80] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 154 .associativity = 8, .line_size = 64, }, 155 [0x82] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 156 .associativity = 8, .line_size = 32, }, 157 [0x83] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 158 .associativity = 8, .line_size = 32, }, 159 [0x84] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 160 .associativity = 8, .line_size = 32, }, 161 [0x85] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 162 .associativity = 8, .line_size = 32, }, 163 [0x86] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 164 .associativity = 4, .line_size = 64, }, 165 [0x87] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 166 .associativity = 8, .line_size = 64, }, 167 [0xD0] = { .level = 3, .type = UNIFIED_CACHE, .size = 512 * KiB, 168 .associativity = 4, .line_size = 64, }, 169 [0xD1] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB, 170 .associativity = 4, .line_size = 64, }, 171 [0xD2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 172 .associativity = 4, .line_size = 64, }, 173 [0xD6] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB, 174 .associativity = 8, .line_size = 64, }, 175 [0xD7] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 176 .associativity = 8, .line_size = 64, }, 177 [0xD8] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 178 .associativity = 8, .line_size = 64, }, 179 [0xDC] = { .level = 3, .type = UNIFIED_CACHE, .size = 1.5 * MiB, 180 .associativity = 12, .line_size = 64, }, 181 [0xDD] = { .level = 3, .type = UNIFIED_CACHE, .size = 3 * MiB, 182 .associativity = 12, .line_size = 64, }, 183 [0xDE] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB, 184 .associativity = 12, .line_size = 64, }, 185 [0xE2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 186 .associativity = 16, .line_size = 64, }, 187 [0xE3] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 188 .associativity = 16, .line_size = 64, }, 189 [0xE4] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 190 .associativity = 16, .line_size = 64, }, 191 [0xEA] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB, 192 .associativity = 24, .line_size = 64, }, 193 [0xEB] = { .level = 3, .type = UNIFIED_CACHE, .size = 18 * MiB, 194 .associativity = 24, .line_size = 64, }, 195 [0xEC] = { .level = 3, .type = UNIFIED_CACHE, .size = 24 * MiB, 196 .associativity = 24, .line_size = 64, }, 197 }; 198 199 /* 200 * "CPUID leaf 2 does not report cache descriptor information, 201 * use CPUID leaf 4 to query cache parameters" 202 */ 203 #define CACHE_DESCRIPTOR_UNAVAILABLE 0xFF 204 205 /* 206 * Return a CPUID 2 cache descriptor for a given cache. 207 * If no known descriptor is found, return CACHE_DESCRIPTOR_UNAVAILABLE 208 */ 209 static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache) 210 { 211 int i; 212 213 assert(cache->size > 0); 214 assert(cache->level > 0); 215 assert(cache->line_size > 0); 216 assert(cache->associativity > 0); 217 for (i = 0; i < ARRAY_SIZE(cpuid2_cache_descriptors); i++) { 218 struct CPUID2CacheDescriptorInfo *d = &cpuid2_cache_descriptors[i]; 219 if (d->level == cache->level && d->type == cache->type && 220 d->size == cache->size && d->line_size == cache->line_size && 221 d->associativity == cache->associativity) { 222 return i; 223 } 224 } 225 226 return CACHE_DESCRIPTOR_UNAVAILABLE; 227 } 228 229 /* CPUID Leaf 4 constants: */ 230 231 /* EAX: */ 232 #define CACHE_TYPE_D 1 233 #define CACHE_TYPE_I 2 234 #define CACHE_TYPE_UNIFIED 3 235 236 #define CACHE_LEVEL(l) (l << 5) 237 238 #define CACHE_SELF_INIT_LEVEL (1 << 8) 239 240 /* EDX: */ 241 #define CACHE_NO_INVD_SHARING (1 << 0) 242 #define CACHE_INCLUSIVE (1 << 1) 243 #define CACHE_COMPLEX_IDX (1 << 2) 244 245 /* Encode CacheType for CPUID[4].EAX */ 246 #define CACHE_TYPE(t) (((t) == DATA_CACHE) ? CACHE_TYPE_D : \ 247 ((t) == INSTRUCTION_CACHE) ? CACHE_TYPE_I : \ 248 ((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \ 249 0 /* Invalid value */) 250 251 252 /* Encode cache info for CPUID[4] */ 253 static void encode_cache_cpuid4(CPUCacheInfo *cache, 254 int num_apic_ids, int num_cores, 255 uint32_t *eax, uint32_t *ebx, 256 uint32_t *ecx, uint32_t *edx) 257 { 258 assert(cache->size == cache->line_size * cache->associativity * 259 cache->partitions * cache->sets); 260 261 assert(num_apic_ids > 0); 262 *eax = CACHE_TYPE(cache->type) | 263 CACHE_LEVEL(cache->level) | 264 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) | 265 ((num_cores - 1) << 26) | 266 ((num_apic_ids - 1) << 14); 267 268 assert(cache->line_size > 0); 269 assert(cache->partitions > 0); 270 assert(cache->associativity > 0); 271 /* We don't implement fully-associative caches */ 272 assert(cache->associativity < cache->sets); 273 *ebx = (cache->line_size - 1) | 274 ((cache->partitions - 1) << 12) | 275 ((cache->associativity - 1) << 22); 276 277 assert(cache->sets > 0); 278 *ecx = cache->sets - 1; 279 280 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) | 281 (cache->inclusive ? CACHE_INCLUSIVE : 0) | 282 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); 283 } 284 285 /* Encode cache info for CPUID[0x80000005].ECX or CPUID[0x80000005].EDX */ 286 static uint32_t encode_cache_cpuid80000005(CPUCacheInfo *cache) 287 { 288 assert(cache->size % 1024 == 0); 289 assert(cache->lines_per_tag > 0); 290 assert(cache->associativity > 0); 291 assert(cache->line_size > 0); 292 return ((cache->size / 1024) << 24) | (cache->associativity << 16) | 293 (cache->lines_per_tag << 8) | (cache->line_size); 294 } 295 296 #define ASSOC_FULL 0xFF 297 298 /* AMD associativity encoding used on CPUID Leaf 0x80000006: */ 299 #define AMD_ENC_ASSOC(a) (a <= 1 ? a : \ 300 a == 2 ? 0x2 : \ 301 a == 4 ? 0x4 : \ 302 a == 8 ? 0x6 : \ 303 a == 16 ? 0x8 : \ 304 a == 32 ? 0xA : \ 305 a == 48 ? 0xB : \ 306 a == 64 ? 0xC : \ 307 a == 96 ? 0xD : \ 308 a == 128 ? 0xE : \ 309 a == ASSOC_FULL ? 0xF : \ 310 0 /* invalid value */) 311 312 /* 313 * Encode cache info for CPUID[0x80000006].ECX and CPUID[0x80000006].EDX 314 * @l3 can be NULL. 315 */ 316 static void encode_cache_cpuid80000006(CPUCacheInfo *l2, 317 CPUCacheInfo *l3, 318 uint32_t *ecx, uint32_t *edx) 319 { 320 assert(l2->size % 1024 == 0); 321 assert(l2->associativity > 0); 322 assert(l2->lines_per_tag > 0); 323 assert(l2->line_size > 0); 324 *ecx = ((l2->size / 1024) << 16) | 325 (AMD_ENC_ASSOC(l2->associativity) << 12) | 326 (l2->lines_per_tag << 8) | (l2->line_size); 327 328 if (l3) { 329 assert(l3->size % (512 * 1024) == 0); 330 assert(l3->associativity > 0); 331 assert(l3->lines_per_tag > 0); 332 assert(l3->line_size > 0); 333 *edx = ((l3->size / (512 * 1024)) << 18) | 334 (AMD_ENC_ASSOC(l3->associativity) << 12) | 335 (l3->lines_per_tag << 8) | (l3->line_size); 336 } else { 337 *edx = 0; 338 } 339 } 340 341 /* 342 * Definitions used for building CPUID Leaf 0x8000001D and 0x8000001E 343 * Please refer to the AMD64 Architecture Programmer’s Manual Volume 3. 344 * Define the constants to build the cpu topology. Right now, TOPOEXT 345 * feature is enabled only on EPYC. So, these constants are based on 346 * EPYC supported configurations. We may need to handle the cases if 347 * these values change in future. 348 */ 349 /* Maximum core complexes in a node */ 350 #define MAX_CCX 2 351 /* Maximum cores in a core complex */ 352 #define MAX_CORES_IN_CCX 4 353 /* Maximum cores in a node */ 354 #define MAX_CORES_IN_NODE 8 355 /* Maximum nodes in a socket */ 356 #define MAX_NODES_PER_SOCKET 4 357 358 /* 359 * Figure out the number of nodes required to build this config. 360 * Max cores in a node is 8 361 */ 362 static int nodes_in_socket(int nr_cores) 363 { 364 int nodes; 365 366 nodes = DIV_ROUND_UP(nr_cores, MAX_CORES_IN_NODE); 367 368 /* Hardware does not support config with 3 nodes, return 4 in that case */ 369 return (nodes == 3) ? 4 : nodes; 370 } 371 372 /* 373 * Decide the number of cores in a core complex with the given nr_cores using 374 * following set constants MAX_CCX, MAX_CORES_IN_CCX, MAX_CORES_IN_NODE and 375 * MAX_NODES_PER_SOCKET. Maintain symmetry as much as possible 376 * L3 cache is shared across all cores in a core complex. So, this will also 377 * tell us how many cores are sharing the L3 cache. 378 */ 379 static int cores_in_core_complex(int nr_cores) 380 { 381 int nodes; 382 383 /* Check if we can fit all the cores in one core complex */ 384 if (nr_cores <= MAX_CORES_IN_CCX) { 385 return nr_cores; 386 } 387 /* Get the number of nodes required to build this config */ 388 nodes = nodes_in_socket(nr_cores); 389 390 /* 391 * Divide the cores accros all the core complexes 392 * Return rounded up value 393 */ 394 return DIV_ROUND_UP(nr_cores, nodes * MAX_CCX); 395 } 396 397 /* Encode cache info for CPUID[8000001D] */ 398 static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, CPUState *cs, 399 uint32_t *eax, uint32_t *ebx, 400 uint32_t *ecx, uint32_t *edx) 401 { 402 uint32_t l3_cores; 403 assert(cache->size == cache->line_size * cache->associativity * 404 cache->partitions * cache->sets); 405 406 *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) | 407 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0); 408 409 /* L3 is shared among multiple cores */ 410 if (cache->level == 3) { 411 l3_cores = cores_in_core_complex(cs->nr_cores); 412 *eax |= ((l3_cores * cs->nr_threads) - 1) << 14; 413 } else { 414 *eax |= ((cs->nr_threads - 1) << 14); 415 } 416 417 assert(cache->line_size > 0); 418 assert(cache->partitions > 0); 419 assert(cache->associativity > 0); 420 /* We don't implement fully-associative caches */ 421 assert(cache->associativity < cache->sets); 422 *ebx = (cache->line_size - 1) | 423 ((cache->partitions - 1) << 12) | 424 ((cache->associativity - 1) << 22); 425 426 assert(cache->sets > 0); 427 *ecx = cache->sets - 1; 428 429 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) | 430 (cache->inclusive ? CACHE_INCLUSIVE : 0) | 431 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); 432 } 433 434 /* Data structure to hold the configuration info for a given core index */ 435 struct core_topology { 436 /* core complex id of the current core index */ 437 int ccx_id; 438 /* 439 * Adjusted core index for this core in the topology 440 * This can be 0,1,2,3 with max 4 cores in a core complex 441 */ 442 int core_id; 443 /* Node id for this core index */ 444 int node_id; 445 /* Number of nodes in this config */ 446 int num_nodes; 447 }; 448 449 /* 450 * Build the configuration closely match the EPYC hardware. Using the EPYC 451 * hardware configuration values (MAX_CCX, MAX_CORES_IN_CCX, MAX_CORES_IN_NODE) 452 * right now. This could change in future. 453 * nr_cores : Total number of cores in the config 454 * core_id : Core index of the current CPU 455 * topo : Data structure to hold all the config info for this core index 456 */ 457 static void build_core_topology(int nr_cores, int core_id, 458 struct core_topology *topo) 459 { 460 int nodes, cores_in_ccx; 461 462 /* First get the number of nodes required */ 463 nodes = nodes_in_socket(nr_cores); 464 465 cores_in_ccx = cores_in_core_complex(nr_cores); 466 467 topo->node_id = core_id / (cores_in_ccx * MAX_CCX); 468 topo->ccx_id = (core_id % (cores_in_ccx * MAX_CCX)) / cores_in_ccx; 469 topo->core_id = core_id % cores_in_ccx; 470 topo->num_nodes = nodes; 471 } 472 473 /* Encode cache info for CPUID[8000001E] */ 474 static void encode_topo_cpuid8000001e(CPUState *cs, X86CPU *cpu, 475 uint32_t *eax, uint32_t *ebx, 476 uint32_t *ecx, uint32_t *edx) 477 { 478 struct core_topology topo = {0}; 479 unsigned long nodes; 480 int shift; 481 482 build_core_topology(cs->nr_cores, cpu->core_id, &topo); 483 *eax = cpu->apic_id; 484 /* 485 * CPUID_Fn8000001E_EBX 486 * 31:16 Reserved 487 * 15:8 Threads per core (The number of threads per core is 488 * Threads per core + 1) 489 * 7:0 Core id (see bit decoding below) 490 * SMT: 491 * 4:3 node id 492 * 2 Core complex id 493 * 1:0 Core id 494 * Non SMT: 495 * 5:4 node id 496 * 3 Core complex id 497 * 1:0 Core id 498 */ 499 if (cs->nr_threads - 1) { 500 *ebx = ((cs->nr_threads - 1) << 8) | (topo.node_id << 3) | 501 (topo.ccx_id << 2) | topo.core_id; 502 } else { 503 *ebx = (topo.node_id << 4) | (topo.ccx_id << 3) | topo.core_id; 504 } 505 /* 506 * CPUID_Fn8000001E_ECX 507 * 31:11 Reserved 508 * 10:8 Nodes per processor (Nodes per processor is number of nodes + 1) 509 * 7:0 Node id (see bit decoding below) 510 * 2 Socket id 511 * 1:0 Node id 512 */ 513 if (topo.num_nodes <= 4) { 514 *ecx = ((topo.num_nodes - 1) << 8) | (cpu->socket_id << 2) | 515 topo.node_id; 516 } else { 517 /* 518 * Node id fix up. Actual hardware supports up to 4 nodes. But with 519 * more than 32 cores, we may end up with more than 4 nodes. 520 * Node id is a combination of socket id and node id. Only requirement 521 * here is that this number should be unique accross the system. 522 * Shift the socket id to accommodate more nodes. We dont expect both 523 * socket id and node id to be big number at the same time. This is not 524 * an ideal config but we need to to support it. Max nodes we can have 525 * is 32 (255/8) with 8 cores per node and 255 max cores. We only need 526 * 5 bits for nodes. Find the left most set bit to represent the total 527 * number of nodes. find_last_bit returns last set bit(0 based). Left 528 * shift(+1) the socket id to represent all the nodes. 529 */ 530 nodes = topo.num_nodes - 1; 531 shift = find_last_bit(&nodes, 8); 532 *ecx = ((topo.num_nodes - 1) << 8) | (cpu->socket_id << (shift + 1)) | 533 topo.node_id; 534 } 535 *edx = 0; 536 } 537 538 /* 539 * Definitions of the hardcoded cache entries we expose: 540 * These are legacy cache values. If there is a need to change any 541 * of these values please use builtin_x86_defs 542 */ 543 544 /* L1 data cache: */ 545 static CPUCacheInfo legacy_l1d_cache = { 546 .type = DATA_CACHE, 547 .level = 1, 548 .size = 32 * KiB, 549 .self_init = 1, 550 .line_size = 64, 551 .associativity = 8, 552 .sets = 64, 553 .partitions = 1, 554 .no_invd_sharing = true, 555 }; 556 557 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ 558 static CPUCacheInfo legacy_l1d_cache_amd = { 559 .type = DATA_CACHE, 560 .level = 1, 561 .size = 64 * KiB, 562 .self_init = 1, 563 .line_size = 64, 564 .associativity = 2, 565 .sets = 512, 566 .partitions = 1, 567 .lines_per_tag = 1, 568 .no_invd_sharing = true, 569 }; 570 571 /* L1 instruction cache: */ 572 static CPUCacheInfo legacy_l1i_cache = { 573 .type = INSTRUCTION_CACHE, 574 .level = 1, 575 .size = 32 * KiB, 576 .self_init = 1, 577 .line_size = 64, 578 .associativity = 8, 579 .sets = 64, 580 .partitions = 1, 581 .no_invd_sharing = true, 582 }; 583 584 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ 585 static CPUCacheInfo legacy_l1i_cache_amd = { 586 .type = INSTRUCTION_CACHE, 587 .level = 1, 588 .size = 64 * KiB, 589 .self_init = 1, 590 .line_size = 64, 591 .associativity = 2, 592 .sets = 512, 593 .partitions = 1, 594 .lines_per_tag = 1, 595 .no_invd_sharing = true, 596 }; 597 598 /* Level 2 unified cache: */ 599 static CPUCacheInfo legacy_l2_cache = { 600 .type = UNIFIED_CACHE, 601 .level = 2, 602 .size = 4 * MiB, 603 .self_init = 1, 604 .line_size = 64, 605 .associativity = 16, 606 .sets = 4096, 607 .partitions = 1, 608 .no_invd_sharing = true, 609 }; 610 611 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */ 612 static CPUCacheInfo legacy_l2_cache_cpuid2 = { 613 .type = UNIFIED_CACHE, 614 .level = 2, 615 .size = 2 * MiB, 616 .line_size = 64, 617 .associativity = 8, 618 }; 619 620 621 /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */ 622 static CPUCacheInfo legacy_l2_cache_amd = { 623 .type = UNIFIED_CACHE, 624 .level = 2, 625 .size = 512 * KiB, 626 .line_size = 64, 627 .lines_per_tag = 1, 628 .associativity = 16, 629 .sets = 512, 630 .partitions = 1, 631 }; 632 633 /* Level 3 unified cache: */ 634 static CPUCacheInfo legacy_l3_cache = { 635 .type = UNIFIED_CACHE, 636 .level = 3, 637 .size = 16 * MiB, 638 .line_size = 64, 639 .associativity = 16, 640 .sets = 16384, 641 .partitions = 1, 642 .lines_per_tag = 1, 643 .self_init = true, 644 .inclusive = true, 645 .complex_indexing = true, 646 }; 647 648 /* TLB definitions: */ 649 650 #define L1_DTLB_2M_ASSOC 1 651 #define L1_DTLB_2M_ENTRIES 255 652 #define L1_DTLB_4K_ASSOC 1 653 #define L1_DTLB_4K_ENTRIES 255 654 655 #define L1_ITLB_2M_ASSOC 1 656 #define L1_ITLB_2M_ENTRIES 255 657 #define L1_ITLB_4K_ASSOC 1 658 #define L1_ITLB_4K_ENTRIES 255 659 660 #define L2_DTLB_2M_ASSOC 0 /* disabled */ 661 #define L2_DTLB_2M_ENTRIES 0 /* disabled */ 662 #define L2_DTLB_4K_ASSOC 4 663 #define L2_DTLB_4K_ENTRIES 512 664 665 #define L2_ITLB_2M_ASSOC 0 /* disabled */ 666 #define L2_ITLB_2M_ENTRIES 0 /* disabled */ 667 #define L2_ITLB_4K_ASSOC 4 668 #define L2_ITLB_4K_ENTRIES 512 669 670 /* CPUID Leaf 0x14 constants: */ 671 #define INTEL_PT_MAX_SUBLEAF 0x1 672 /* 673 * bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MATCH 674 * MSR can be accessed; 675 * bit[01]: Support Configurable PSB and Cycle-Accurate Mode; 676 * bit[02]: Support IP Filtering, TraceStop filtering, and preservation 677 * of Intel PT MSRs across warm reset; 678 * bit[03]: Support MTC timing packet and suppression of COFI-based packets; 679 */ 680 #define INTEL_PT_MINIMAL_EBX 0xf 681 /* 682 * bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 and 683 * IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be 684 * accessed; 685 * bit[01]: ToPA tables can hold any number of output entries, up to the 686 * maximum allowed by the MaskOrTableOffset field of 687 * IA32_RTIT_OUTPUT_MASK_PTRS; 688 * bit[02]: Support Single-Range Output scheme; 689 */ 690 #define INTEL_PT_MINIMAL_ECX 0x7 691 /* generated packets which contain IP payloads have LIP values */ 692 #define INTEL_PT_IP_LIP (1 << 31) 693 #define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */ 694 #define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3 695 #define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */ 696 #define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */ 697 #define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */ 698 699 static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1, 700 uint32_t vendor2, uint32_t vendor3) 701 { 702 int i; 703 for (i = 0; i < 4; i++) { 704 dst[i] = vendor1 >> (8 * i); 705 dst[i + 4] = vendor2 >> (8 * i); 706 dst[i + 8] = vendor3 >> (8 * i); 707 } 708 dst[CPUID_VENDOR_SZ] = '\0'; 709 } 710 711 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE) 712 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \ 713 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC) 714 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \ 715 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ 716 CPUID_PSE36 | CPUID_FXSR) 717 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE) 718 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \ 719 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \ 720 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \ 721 CPUID_PAE | CPUID_SEP | CPUID_APIC) 722 723 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \ 724 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \ 725 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ 726 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \ 727 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE) 728 /* partly implemented: 729 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */ 730 /* missing: 731 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */ 732 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \ 733 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \ 734 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \ 735 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \ 736 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR | \ 737 CPUID_EXT_RDRAND) 738 /* missing: 739 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX, 740 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA, 741 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA, 742 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_AVX, 743 CPUID_EXT_F16C */ 744 745 #ifdef TARGET_X86_64 746 #define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM) 747 #else 748 #define TCG_EXT2_X86_64_FEATURES 0 749 #endif 750 751 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \ 752 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \ 753 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \ 754 TCG_EXT2_X86_64_FEATURES) 755 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \ 756 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A) 757 #define TCG_EXT4_FEATURES 0 758 #define TCG_SVM_FEATURES CPUID_SVM_NPT 759 #define TCG_KVM_FEATURES 0 760 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \ 761 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \ 762 CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \ 763 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \ 764 CPUID_7_0_EBX_ERMS) 765 /* missing: 766 CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2, 767 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM, 768 CPUID_7_0_EBX_RDSEED */ 769 #define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_PKU | \ 770 /* CPUID_7_0_ECX_OSPKE is dynamic */ \ 771 CPUID_7_0_ECX_LA57) 772 #define TCG_7_0_EDX_FEATURES 0 773 #define TCG_7_1_EAX_FEATURES 0 774 #define TCG_APM_FEATURES 0 775 #define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT 776 #define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1) 777 /* missing: 778 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */ 779 780 typedef enum FeatureWordType { 781 CPUID_FEATURE_WORD, 782 MSR_FEATURE_WORD, 783 } FeatureWordType; 784 785 typedef struct FeatureWordInfo { 786 FeatureWordType type; 787 /* feature flags names are taken from "Intel Processor Identification and 788 * the CPUID Instruction" and AMD's "CPUID Specification". 789 * In cases of disagreement between feature naming conventions, 790 * aliases may be added. 791 */ 792 const char *feat_names[64]; 793 union { 794 /* If type==CPUID_FEATURE_WORD */ 795 struct { 796 uint32_t eax; /* Input EAX for CPUID */ 797 bool needs_ecx; /* CPUID instruction uses ECX as input */ 798 uint32_t ecx; /* Input ECX value for CPUID */ 799 int reg; /* output register (R_* constant) */ 800 } cpuid; 801 /* If type==MSR_FEATURE_WORD */ 802 struct { 803 uint32_t index; 804 } msr; 805 }; 806 uint64_t tcg_features; /* Feature flags supported by TCG */ 807 uint64_t unmigratable_flags; /* Feature flags known to be unmigratable */ 808 uint64_t migratable_flags; /* Feature flags known to be migratable */ 809 /* Features that shouldn't be auto-enabled by "-cpu host" */ 810 uint64_t no_autoenable_flags; 811 } FeatureWordInfo; 812 813 static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { 814 [FEAT_1_EDX] = { 815 .type = CPUID_FEATURE_WORD, 816 .feat_names = { 817 "fpu", "vme", "de", "pse", 818 "tsc", "msr", "pae", "mce", 819 "cx8", "apic", NULL, "sep", 820 "mtrr", "pge", "mca", "cmov", 821 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */, 822 NULL, "ds" /* Intel dts */, "acpi", "mmx", 823 "fxsr", "sse", "sse2", "ss", 824 "ht" /* Intel htt */, "tm", "ia64", "pbe", 825 }, 826 .cpuid = {.eax = 1, .reg = R_EDX, }, 827 .tcg_features = TCG_FEATURES, 828 }, 829 [FEAT_1_ECX] = { 830 .type = CPUID_FEATURE_WORD, 831 .feat_names = { 832 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor", 833 "ds-cpl", "vmx", "smx", "est", 834 "tm2", "ssse3", "cid", NULL, 835 "fma", "cx16", "xtpr", "pdcm", 836 NULL, "pcid", "dca", "sse4.1", 837 "sse4.2", "x2apic", "movbe", "popcnt", 838 "tsc-deadline", "aes", "xsave", NULL /* osxsave */, 839 "avx", "f16c", "rdrand", "hypervisor", 840 }, 841 .cpuid = { .eax = 1, .reg = R_ECX, }, 842 .tcg_features = TCG_EXT_FEATURES, 843 }, 844 /* Feature names that are already defined on feature_name[] but 845 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their 846 * names on feat_names below. They are copied automatically 847 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD. 848 */ 849 [FEAT_8000_0001_EDX] = { 850 .type = CPUID_FEATURE_WORD, 851 .feat_names = { 852 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */, 853 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */, 854 NULL /* cx8 */, NULL /* apic */, NULL, "syscall", 855 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */, 856 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */, 857 "nx", NULL, "mmxext", NULL /* mmx */, 858 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp", 859 NULL, "lm", "3dnowext", "3dnow", 860 }, 861 .cpuid = { .eax = 0x80000001, .reg = R_EDX, }, 862 .tcg_features = TCG_EXT2_FEATURES, 863 }, 864 [FEAT_8000_0001_ECX] = { 865 .type = CPUID_FEATURE_WORD, 866 .feat_names = { 867 "lahf-lm", "cmp-legacy", "svm", "extapic", 868 "cr8legacy", "abm", "sse4a", "misalignsse", 869 "3dnowprefetch", "osvw", "ibs", "xop", 870 "skinit", "wdt", NULL, "lwp", 871 "fma4", "tce", NULL, "nodeid-msr", 872 NULL, "tbm", "topoext", "perfctr-core", 873 "perfctr-nb", NULL, NULL, NULL, 874 NULL, NULL, NULL, NULL, 875 }, 876 .cpuid = { .eax = 0x80000001, .reg = R_ECX, }, 877 .tcg_features = TCG_EXT3_FEATURES, 878 /* 879 * TOPOEXT is always allowed but can't be enabled blindly by 880 * "-cpu host", as it requires consistent cache topology info 881 * to be provided so it doesn't confuse guests. 882 */ 883 .no_autoenable_flags = CPUID_EXT3_TOPOEXT, 884 }, 885 [FEAT_C000_0001_EDX] = { 886 .type = CPUID_FEATURE_WORD, 887 .feat_names = { 888 NULL, NULL, "xstore", "xstore-en", 889 NULL, NULL, "xcrypt", "xcrypt-en", 890 "ace2", "ace2-en", "phe", "phe-en", 891 "pmm", "pmm-en", NULL, NULL, 892 NULL, NULL, NULL, NULL, 893 NULL, NULL, NULL, NULL, 894 NULL, NULL, NULL, NULL, 895 NULL, NULL, NULL, NULL, 896 }, 897 .cpuid = { .eax = 0xC0000001, .reg = R_EDX, }, 898 .tcg_features = TCG_EXT4_FEATURES, 899 }, 900 [FEAT_KVM] = { 901 .type = CPUID_FEATURE_WORD, 902 .feat_names = { 903 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock", 904 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt", 905 NULL, "kvm-pv-tlb-flush", NULL, "kvm-pv-ipi", 906 "kvm-poll-control", "kvm-pv-sched-yield", NULL, NULL, 907 NULL, NULL, NULL, NULL, 908 NULL, NULL, NULL, NULL, 909 "kvmclock-stable-bit", NULL, NULL, NULL, 910 NULL, NULL, NULL, NULL, 911 }, 912 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EAX, }, 913 .tcg_features = TCG_KVM_FEATURES, 914 }, 915 [FEAT_KVM_HINTS] = { 916 .type = CPUID_FEATURE_WORD, 917 .feat_names = { 918 "kvm-hint-dedicated", NULL, NULL, NULL, 919 NULL, NULL, NULL, NULL, 920 NULL, NULL, NULL, NULL, 921 NULL, NULL, NULL, NULL, 922 NULL, NULL, NULL, NULL, 923 NULL, NULL, NULL, NULL, 924 NULL, NULL, NULL, NULL, 925 NULL, NULL, NULL, NULL, 926 }, 927 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EDX, }, 928 .tcg_features = TCG_KVM_FEATURES, 929 /* 930 * KVM hints aren't auto-enabled by -cpu host, they need to be 931 * explicitly enabled in the command-line. 932 */ 933 .no_autoenable_flags = ~0U, 934 }, 935 /* 936 * .feat_names are commented out for Hyper-V enlightenments because we 937 * don't want to have two different ways for enabling them on QEMU command 938 * line. Some features (e.g. "hyperv_time", "hyperv_vapic", ...) require 939 * enabling several feature bits simultaneously, exposing these bits 940 * individually may just confuse guests. 941 */ 942 [FEAT_HYPERV_EAX] = { 943 .type = CPUID_FEATURE_WORD, 944 .feat_names = { 945 NULL /* hv_msr_vp_runtime_access */, NULL /* hv_msr_time_refcount_access */, 946 NULL /* hv_msr_synic_access */, NULL /* hv_msr_stimer_access */, 947 NULL /* hv_msr_apic_access */, NULL /* hv_msr_hypercall_access */, 948 NULL /* hv_vpindex_access */, NULL /* hv_msr_reset_access */, 949 NULL /* hv_msr_stats_access */, NULL /* hv_reftsc_access */, 950 NULL /* hv_msr_idle_access */, NULL /* hv_msr_frequency_access */, 951 NULL /* hv_msr_debug_access */, NULL /* hv_msr_reenlightenment_access */, 952 NULL, NULL, 953 NULL, NULL, NULL, NULL, 954 NULL, NULL, NULL, NULL, 955 NULL, NULL, NULL, NULL, 956 NULL, NULL, NULL, NULL, 957 }, 958 .cpuid = { .eax = 0x40000003, .reg = R_EAX, }, 959 }, 960 [FEAT_HYPERV_EBX] = { 961 .type = CPUID_FEATURE_WORD, 962 .feat_names = { 963 NULL /* hv_create_partitions */, NULL /* hv_access_partition_id */, 964 NULL /* hv_access_memory_pool */, NULL /* hv_adjust_message_buffers */, 965 NULL /* hv_post_messages */, NULL /* hv_signal_events */, 966 NULL /* hv_create_port */, NULL /* hv_connect_port */, 967 NULL /* hv_access_stats */, NULL, NULL, NULL /* hv_debugging */, 968 NULL /* hv_cpu_power_management */, NULL /* hv_configure_profiler */, 969 NULL, NULL, 970 NULL, NULL, NULL, NULL, 971 NULL, NULL, NULL, NULL, 972 NULL, NULL, NULL, NULL, 973 NULL, NULL, NULL, NULL, 974 }, 975 .cpuid = { .eax = 0x40000003, .reg = R_EBX, }, 976 }, 977 [FEAT_HYPERV_EDX] = { 978 .type = CPUID_FEATURE_WORD, 979 .feat_names = { 980 NULL /* hv_mwait */, NULL /* hv_guest_debugging */, 981 NULL /* hv_perf_monitor */, NULL /* hv_cpu_dynamic_part */, 982 NULL /* hv_hypercall_params_xmm */, NULL /* hv_guest_idle_state */, 983 NULL, NULL, 984 NULL, NULL, NULL /* hv_guest_crash_msr */, NULL, 985 NULL, NULL, NULL, NULL, 986 NULL, NULL, NULL, NULL, 987 NULL, NULL, NULL, NULL, 988 NULL, NULL, NULL, NULL, 989 NULL, NULL, NULL, NULL, 990 }, 991 .cpuid = { .eax = 0x40000003, .reg = R_EDX, }, 992 }, 993 [FEAT_HV_RECOMM_EAX] = { 994 .type = CPUID_FEATURE_WORD, 995 .feat_names = { 996 NULL /* hv_recommend_pv_as_switch */, 997 NULL /* hv_recommend_pv_tlbflush_local */, 998 NULL /* hv_recommend_pv_tlbflush_remote */, 999 NULL /* hv_recommend_msr_apic_access */, 1000 NULL /* hv_recommend_msr_reset */, 1001 NULL /* hv_recommend_relaxed_timing */, 1002 NULL /* hv_recommend_dma_remapping */, 1003 NULL /* hv_recommend_int_remapping */, 1004 NULL /* hv_recommend_x2apic_msrs */, 1005 NULL /* hv_recommend_autoeoi_deprecation */, 1006 NULL /* hv_recommend_pv_ipi */, 1007 NULL /* hv_recommend_ex_hypercalls */, 1008 NULL /* hv_hypervisor_is_nested */, 1009 NULL /* hv_recommend_int_mbec */, 1010 NULL /* hv_recommend_evmcs */, 1011 NULL, 1012 NULL, NULL, NULL, NULL, 1013 NULL, NULL, NULL, NULL, 1014 NULL, NULL, NULL, NULL, 1015 NULL, NULL, NULL, NULL, 1016 }, 1017 .cpuid = { .eax = 0x40000004, .reg = R_EAX, }, 1018 }, 1019 [FEAT_HV_NESTED_EAX] = { 1020 .type = CPUID_FEATURE_WORD, 1021 .cpuid = { .eax = 0x4000000A, .reg = R_EAX, }, 1022 }, 1023 [FEAT_SVM] = { 1024 .type = CPUID_FEATURE_WORD, 1025 .feat_names = { 1026 "npt", "lbrv", "svm-lock", "nrip-save", 1027 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists", 1028 NULL, NULL, "pause-filter", NULL, 1029 "pfthreshold", NULL, NULL, NULL, 1030 NULL, NULL, NULL, NULL, 1031 NULL, NULL, NULL, NULL, 1032 NULL, NULL, NULL, NULL, 1033 NULL, NULL, NULL, NULL, 1034 }, 1035 .cpuid = { .eax = 0x8000000A, .reg = R_EDX, }, 1036 .tcg_features = TCG_SVM_FEATURES, 1037 }, 1038 [FEAT_7_0_EBX] = { 1039 .type = CPUID_FEATURE_WORD, 1040 .feat_names = { 1041 "fsgsbase", "tsc-adjust", NULL, "bmi1", 1042 "hle", "avx2", NULL, "smep", 1043 "bmi2", "erms", "invpcid", "rtm", 1044 NULL, NULL, "mpx", NULL, 1045 "avx512f", "avx512dq", "rdseed", "adx", 1046 "smap", "avx512ifma", "pcommit", "clflushopt", 1047 "clwb", "intel-pt", "avx512pf", "avx512er", 1048 "avx512cd", "sha-ni", "avx512bw", "avx512vl", 1049 }, 1050 .cpuid = { 1051 .eax = 7, 1052 .needs_ecx = true, .ecx = 0, 1053 .reg = R_EBX, 1054 }, 1055 .tcg_features = TCG_7_0_EBX_FEATURES, 1056 }, 1057 [FEAT_7_0_ECX] = { 1058 .type = CPUID_FEATURE_WORD, 1059 .feat_names = { 1060 NULL, "avx512vbmi", "umip", "pku", 1061 NULL /* ospke */, NULL, "avx512vbmi2", NULL, 1062 "gfni", "vaes", "vpclmulqdq", "avx512vnni", 1063 "avx512bitalg", NULL, "avx512-vpopcntdq", NULL, 1064 "la57", NULL, NULL, NULL, 1065 NULL, NULL, "rdpid", NULL, 1066 NULL, "cldemote", NULL, "movdiri", 1067 "movdir64b", NULL, NULL, NULL, 1068 }, 1069 .cpuid = { 1070 .eax = 7, 1071 .needs_ecx = true, .ecx = 0, 1072 .reg = R_ECX, 1073 }, 1074 .tcg_features = TCG_7_0_ECX_FEATURES, 1075 }, 1076 [FEAT_7_0_EDX] = { 1077 .type = CPUID_FEATURE_WORD, 1078 .feat_names = { 1079 NULL, NULL, "avx512-4vnniw", "avx512-4fmaps", 1080 NULL, NULL, NULL, NULL, 1081 NULL, NULL, "md-clear", NULL, 1082 NULL, NULL, NULL, NULL, 1083 NULL, NULL, NULL /* pconfig */, NULL, 1084 NULL, NULL, NULL, NULL, 1085 NULL, NULL, "spec-ctrl", "stibp", 1086 NULL, "arch-capabilities", "core-capability", "ssbd", 1087 }, 1088 .cpuid = { 1089 .eax = 7, 1090 .needs_ecx = true, .ecx = 0, 1091 .reg = R_EDX, 1092 }, 1093 .tcg_features = TCG_7_0_EDX_FEATURES, 1094 }, 1095 [FEAT_7_1_EAX] = { 1096 .type = CPUID_FEATURE_WORD, 1097 .feat_names = { 1098 NULL, NULL, NULL, NULL, 1099 NULL, "avx512-bf16", NULL, NULL, 1100 NULL, NULL, NULL, NULL, 1101 NULL, NULL, NULL, NULL, 1102 NULL, NULL, NULL, NULL, 1103 NULL, NULL, NULL, NULL, 1104 NULL, NULL, NULL, NULL, 1105 NULL, NULL, NULL, NULL, 1106 }, 1107 .cpuid = { 1108 .eax = 7, 1109 .needs_ecx = true, .ecx = 1, 1110 .reg = R_EAX, 1111 }, 1112 .tcg_features = TCG_7_1_EAX_FEATURES, 1113 }, 1114 [FEAT_8000_0007_EDX] = { 1115 .type = CPUID_FEATURE_WORD, 1116 .feat_names = { 1117 NULL, NULL, NULL, NULL, 1118 NULL, NULL, NULL, NULL, 1119 "invtsc", NULL, NULL, NULL, 1120 NULL, NULL, NULL, NULL, 1121 NULL, NULL, NULL, NULL, 1122 NULL, NULL, NULL, NULL, 1123 NULL, NULL, NULL, NULL, 1124 NULL, NULL, NULL, NULL, 1125 }, 1126 .cpuid = { .eax = 0x80000007, .reg = R_EDX, }, 1127 .tcg_features = TCG_APM_FEATURES, 1128 .unmigratable_flags = CPUID_APM_INVTSC, 1129 }, 1130 [FEAT_8000_0008_EBX] = { 1131 .type = CPUID_FEATURE_WORD, 1132 .feat_names = { 1133 "clzero", NULL, "xsaveerptr", NULL, 1134 NULL, NULL, NULL, NULL, 1135 NULL, "wbnoinvd", NULL, NULL, 1136 "ibpb", NULL, NULL, NULL, 1137 NULL, NULL, NULL, NULL, 1138 NULL, NULL, NULL, NULL, 1139 "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL, 1140 NULL, NULL, NULL, NULL, 1141 }, 1142 .cpuid = { .eax = 0x80000008, .reg = R_EBX, }, 1143 .tcg_features = 0, 1144 .unmigratable_flags = 0, 1145 }, 1146 [FEAT_XSAVE] = { 1147 .type = CPUID_FEATURE_WORD, 1148 .feat_names = { 1149 "xsaveopt", "xsavec", "xgetbv1", "xsaves", 1150 NULL, NULL, NULL, NULL, 1151 NULL, NULL, NULL, NULL, 1152 NULL, NULL, NULL, NULL, 1153 NULL, NULL, NULL, NULL, 1154 NULL, NULL, NULL, NULL, 1155 NULL, NULL, NULL, NULL, 1156 NULL, NULL, NULL, NULL, 1157 }, 1158 .cpuid = { 1159 .eax = 0xd, 1160 .needs_ecx = true, .ecx = 1, 1161 .reg = R_EAX, 1162 }, 1163 .tcg_features = TCG_XSAVE_FEATURES, 1164 }, 1165 [FEAT_6_EAX] = { 1166 .type = CPUID_FEATURE_WORD, 1167 .feat_names = { 1168 NULL, NULL, "arat", NULL, 1169 NULL, NULL, NULL, NULL, 1170 NULL, NULL, NULL, NULL, 1171 NULL, NULL, NULL, NULL, 1172 NULL, NULL, NULL, NULL, 1173 NULL, NULL, NULL, NULL, 1174 NULL, NULL, NULL, NULL, 1175 NULL, NULL, NULL, NULL, 1176 }, 1177 .cpuid = { .eax = 6, .reg = R_EAX, }, 1178 .tcg_features = TCG_6_EAX_FEATURES, 1179 }, 1180 [FEAT_XSAVE_COMP_LO] = { 1181 .type = CPUID_FEATURE_WORD, 1182 .cpuid = { 1183 .eax = 0xD, 1184 .needs_ecx = true, .ecx = 0, 1185 .reg = R_EAX, 1186 }, 1187 .tcg_features = ~0U, 1188 .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK | 1189 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK | 1190 XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK | 1191 XSTATE_PKRU_MASK, 1192 }, 1193 [FEAT_XSAVE_COMP_HI] = { 1194 .type = CPUID_FEATURE_WORD, 1195 .cpuid = { 1196 .eax = 0xD, 1197 .needs_ecx = true, .ecx = 0, 1198 .reg = R_EDX, 1199 }, 1200 .tcg_features = ~0U, 1201 }, 1202 /*Below are MSR exposed features*/ 1203 [FEAT_ARCH_CAPABILITIES] = { 1204 .type = MSR_FEATURE_WORD, 1205 .feat_names = { 1206 "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry", 1207 "ssb-no", "mds-no", NULL, NULL, 1208 NULL, NULL, NULL, NULL, 1209 NULL, NULL, NULL, NULL, 1210 NULL, NULL, NULL, NULL, 1211 NULL, NULL, NULL, NULL, 1212 NULL, NULL, NULL, NULL, 1213 NULL, NULL, NULL, NULL, 1214 }, 1215 .msr = { 1216 .index = MSR_IA32_ARCH_CAPABILITIES, 1217 }, 1218 }, 1219 [FEAT_CORE_CAPABILITY] = { 1220 .type = MSR_FEATURE_WORD, 1221 .feat_names = { 1222 NULL, NULL, NULL, NULL, 1223 NULL, "split-lock-detect", NULL, NULL, 1224 NULL, NULL, NULL, NULL, 1225 NULL, NULL, NULL, NULL, 1226 NULL, NULL, NULL, NULL, 1227 NULL, NULL, NULL, NULL, 1228 NULL, NULL, NULL, NULL, 1229 NULL, NULL, NULL, NULL, 1230 }, 1231 .msr = { 1232 .index = MSR_IA32_CORE_CAPABILITY, 1233 }, 1234 }, 1235 }; 1236 1237 typedef struct FeatureMask { 1238 FeatureWord index; 1239 uint64_t mask; 1240 } FeatureMask; 1241 1242 typedef struct FeatureDep { 1243 FeatureMask from, to; 1244 } FeatureDep; 1245 1246 static FeatureDep feature_dependencies[] = { 1247 { 1248 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_ARCH_CAPABILITIES }, 1249 .to = { FEAT_ARCH_CAPABILITIES, ~0ull }, 1250 }, 1251 { 1252 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_CORE_CAPABILITY }, 1253 .to = { FEAT_CORE_CAPABILITY, ~0ull }, 1254 }, 1255 }; 1256 1257 typedef struct X86RegisterInfo32 { 1258 /* Name of register */ 1259 const char *name; 1260 /* QAPI enum value register */ 1261 X86CPURegister32 qapi_enum; 1262 } X86RegisterInfo32; 1263 1264 #define REGISTER(reg) \ 1265 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg } 1266 static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = { 1267 REGISTER(EAX), 1268 REGISTER(ECX), 1269 REGISTER(EDX), 1270 REGISTER(EBX), 1271 REGISTER(ESP), 1272 REGISTER(EBP), 1273 REGISTER(ESI), 1274 REGISTER(EDI), 1275 }; 1276 #undef REGISTER 1277 1278 typedef struct ExtSaveArea { 1279 uint32_t feature, bits; 1280 uint32_t offset, size; 1281 } ExtSaveArea; 1282 1283 static const ExtSaveArea x86_ext_save_areas[] = { 1284 [XSTATE_FP_BIT] = { 1285 /* x87 FP state component is always enabled if XSAVE is supported */ 1286 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE, 1287 /* x87 state is in the legacy region of the XSAVE area */ 1288 .offset = 0, 1289 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader), 1290 }, 1291 [XSTATE_SSE_BIT] = { 1292 /* SSE state component is always enabled if XSAVE is supported */ 1293 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE, 1294 /* SSE state is in the legacy region of the XSAVE area */ 1295 .offset = 0, 1296 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader), 1297 }, 1298 [XSTATE_YMM_BIT] = 1299 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX, 1300 .offset = offsetof(X86XSaveArea, avx_state), 1301 .size = sizeof(XSaveAVX) }, 1302 [XSTATE_BNDREGS_BIT] = 1303 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX, 1304 .offset = offsetof(X86XSaveArea, bndreg_state), 1305 .size = sizeof(XSaveBNDREG) }, 1306 [XSTATE_BNDCSR_BIT] = 1307 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX, 1308 .offset = offsetof(X86XSaveArea, bndcsr_state), 1309 .size = sizeof(XSaveBNDCSR) }, 1310 [XSTATE_OPMASK_BIT] = 1311 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1312 .offset = offsetof(X86XSaveArea, opmask_state), 1313 .size = sizeof(XSaveOpmask) }, 1314 [XSTATE_ZMM_Hi256_BIT] = 1315 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1316 .offset = offsetof(X86XSaveArea, zmm_hi256_state), 1317 .size = sizeof(XSaveZMM_Hi256) }, 1318 [XSTATE_Hi16_ZMM_BIT] = 1319 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1320 .offset = offsetof(X86XSaveArea, hi16_zmm_state), 1321 .size = sizeof(XSaveHi16_ZMM) }, 1322 [XSTATE_PKRU_BIT] = 1323 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU, 1324 .offset = offsetof(X86XSaveArea, pkru_state), 1325 .size = sizeof(XSavePKRU) }, 1326 }; 1327 1328 static uint32_t xsave_area_size(uint64_t mask) 1329 { 1330 int i; 1331 uint64_t ret = 0; 1332 1333 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 1334 const ExtSaveArea *esa = &x86_ext_save_areas[i]; 1335 if ((mask >> i) & 1) { 1336 ret = MAX(ret, esa->offset + esa->size); 1337 } 1338 } 1339 return ret; 1340 } 1341 1342 static inline bool accel_uses_host_cpuid(void) 1343 { 1344 return kvm_enabled() || hvf_enabled(); 1345 } 1346 1347 static inline uint64_t x86_cpu_xsave_components(X86CPU *cpu) 1348 { 1349 return ((uint64_t)cpu->env.features[FEAT_XSAVE_COMP_HI]) << 32 | 1350 cpu->env.features[FEAT_XSAVE_COMP_LO]; 1351 } 1352 1353 const char *get_register_name_32(unsigned int reg) 1354 { 1355 if (reg >= CPU_NB_REGS32) { 1356 return NULL; 1357 } 1358 return x86_reg_info_32[reg].name; 1359 } 1360 1361 /* 1362 * Returns the set of feature flags that are supported and migratable by 1363 * QEMU, for a given FeatureWord. 1364 */ 1365 static uint64_t x86_cpu_get_migratable_flags(FeatureWord w) 1366 { 1367 FeatureWordInfo *wi = &feature_word_info[w]; 1368 uint64_t r = 0; 1369 int i; 1370 1371 for (i = 0; i < 64; i++) { 1372 uint64_t f = 1ULL << i; 1373 1374 /* If the feature name is known, it is implicitly considered migratable, 1375 * unless it is explicitly set in unmigratable_flags */ 1376 if ((wi->migratable_flags & f) || 1377 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) { 1378 r |= f; 1379 } 1380 } 1381 return r; 1382 } 1383 1384 void host_cpuid(uint32_t function, uint32_t count, 1385 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) 1386 { 1387 uint32_t vec[4]; 1388 1389 #ifdef __x86_64__ 1390 asm volatile("cpuid" 1391 : "=a"(vec[0]), "=b"(vec[1]), 1392 "=c"(vec[2]), "=d"(vec[3]) 1393 : "0"(function), "c"(count) : "cc"); 1394 #elif defined(__i386__) 1395 asm volatile("pusha \n\t" 1396 "cpuid \n\t" 1397 "mov %%eax, 0(%2) \n\t" 1398 "mov %%ebx, 4(%2) \n\t" 1399 "mov %%ecx, 8(%2) \n\t" 1400 "mov %%edx, 12(%2) \n\t" 1401 "popa" 1402 : : "a"(function), "c"(count), "S"(vec) 1403 : "memory", "cc"); 1404 #else 1405 abort(); 1406 #endif 1407 1408 if (eax) 1409 *eax = vec[0]; 1410 if (ebx) 1411 *ebx = vec[1]; 1412 if (ecx) 1413 *ecx = vec[2]; 1414 if (edx) 1415 *edx = vec[3]; 1416 } 1417 1418 void host_vendor_fms(char *vendor, int *family, int *model, int *stepping) 1419 { 1420 uint32_t eax, ebx, ecx, edx; 1421 1422 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx); 1423 x86_cpu_vendor_words2str(vendor, ebx, edx, ecx); 1424 1425 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx); 1426 if (family) { 1427 *family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF); 1428 } 1429 if (model) { 1430 *model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12); 1431 } 1432 if (stepping) { 1433 *stepping = eax & 0x0F; 1434 } 1435 } 1436 1437 /* CPU class name definitions: */ 1438 1439 /* Return type name for a given CPU model name 1440 * Caller is responsible for freeing the returned string. 1441 */ 1442 static char *x86_cpu_type_name(const char *model_name) 1443 { 1444 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name); 1445 } 1446 1447 static ObjectClass *x86_cpu_class_by_name(const char *cpu_model) 1448 { 1449 ObjectClass *oc; 1450 char *typename = x86_cpu_type_name(cpu_model); 1451 oc = object_class_by_name(typename); 1452 g_free(typename); 1453 return oc; 1454 } 1455 1456 static char *x86_cpu_class_get_model_name(X86CPUClass *cc) 1457 { 1458 const char *class_name = object_class_get_name(OBJECT_CLASS(cc)); 1459 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX)); 1460 return g_strndup(class_name, 1461 strlen(class_name) - strlen(X86_CPU_TYPE_SUFFIX)); 1462 } 1463 1464 typedef struct PropValue { 1465 const char *prop, *value; 1466 } PropValue; 1467 1468 typedef struct X86CPUVersionDefinition { 1469 X86CPUVersion version; 1470 const char *alias; 1471 PropValue *props; 1472 } X86CPUVersionDefinition; 1473 1474 /* Base definition for a CPU model */ 1475 typedef struct X86CPUDefinition { 1476 const char *name; 1477 uint32_t level; 1478 uint32_t xlevel; 1479 /* vendor is zero-terminated, 12 character ASCII string */ 1480 char vendor[CPUID_VENDOR_SZ + 1]; 1481 int family; 1482 int model; 1483 int stepping; 1484 FeatureWordArray features; 1485 const char *model_id; 1486 CPUCaches *cache_info; 1487 /* 1488 * Definitions for alternative versions of CPU model. 1489 * List is terminated by item with version == 0. 1490 * If NULL, version 1 will be registered automatically. 1491 */ 1492 const X86CPUVersionDefinition *versions; 1493 } X86CPUDefinition; 1494 1495 /* Reference to a specific CPU model version */ 1496 struct X86CPUModel { 1497 /* Base CPU definition */ 1498 X86CPUDefinition *cpudef; 1499 /* CPU model version */ 1500 X86CPUVersion version; 1501 /* 1502 * If true, this is an alias CPU model. 1503 * This matters only for "-cpu help" and query-cpu-definitions 1504 */ 1505 bool is_alias; 1506 }; 1507 1508 /* Get full model name for CPU version */ 1509 static char *x86_cpu_versioned_model_name(X86CPUDefinition *cpudef, 1510 X86CPUVersion version) 1511 { 1512 assert(version > 0); 1513 return g_strdup_printf("%s-v%d", cpudef->name, (int)version); 1514 } 1515 1516 static const X86CPUVersionDefinition *x86_cpu_def_get_versions(X86CPUDefinition *def) 1517 { 1518 /* When X86CPUDefinition::versions is NULL, we register only v1 */ 1519 static const X86CPUVersionDefinition default_version_list[] = { 1520 { 1 }, 1521 { /* end of list */ } 1522 }; 1523 1524 return def->versions ?: default_version_list; 1525 } 1526 1527 static CPUCaches epyc_cache_info = { 1528 .l1d_cache = &(CPUCacheInfo) { 1529 .type = DATA_CACHE, 1530 .level = 1, 1531 .size = 32 * KiB, 1532 .line_size = 64, 1533 .associativity = 8, 1534 .partitions = 1, 1535 .sets = 64, 1536 .lines_per_tag = 1, 1537 .self_init = 1, 1538 .no_invd_sharing = true, 1539 }, 1540 .l1i_cache = &(CPUCacheInfo) { 1541 .type = INSTRUCTION_CACHE, 1542 .level = 1, 1543 .size = 64 * KiB, 1544 .line_size = 64, 1545 .associativity = 4, 1546 .partitions = 1, 1547 .sets = 256, 1548 .lines_per_tag = 1, 1549 .self_init = 1, 1550 .no_invd_sharing = true, 1551 }, 1552 .l2_cache = &(CPUCacheInfo) { 1553 .type = UNIFIED_CACHE, 1554 .level = 2, 1555 .size = 512 * KiB, 1556 .line_size = 64, 1557 .associativity = 8, 1558 .partitions = 1, 1559 .sets = 1024, 1560 .lines_per_tag = 1, 1561 }, 1562 .l3_cache = &(CPUCacheInfo) { 1563 .type = UNIFIED_CACHE, 1564 .level = 3, 1565 .size = 8 * MiB, 1566 .line_size = 64, 1567 .associativity = 16, 1568 .partitions = 1, 1569 .sets = 8192, 1570 .lines_per_tag = 1, 1571 .self_init = true, 1572 .inclusive = true, 1573 .complex_indexing = true, 1574 }, 1575 }; 1576 1577 static X86CPUDefinition builtin_x86_defs[] = { 1578 { 1579 .name = "qemu64", 1580 .level = 0xd, 1581 .vendor = CPUID_VENDOR_AMD, 1582 .family = 6, 1583 .model = 6, 1584 .stepping = 3, 1585 .features[FEAT_1_EDX] = 1586 PPRO_FEATURES | 1587 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 1588 CPUID_PSE36, 1589 .features[FEAT_1_ECX] = 1590 CPUID_EXT_SSE3 | CPUID_EXT_CX16, 1591 .features[FEAT_8000_0001_EDX] = 1592 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 1593 .features[FEAT_8000_0001_ECX] = 1594 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM, 1595 .xlevel = 0x8000000A, 1596 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 1597 }, 1598 { 1599 .name = "phenom", 1600 .level = 5, 1601 .vendor = CPUID_VENDOR_AMD, 1602 .family = 16, 1603 .model = 2, 1604 .stepping = 3, 1605 /* Missing: CPUID_HT */ 1606 .features[FEAT_1_EDX] = 1607 PPRO_FEATURES | 1608 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 1609 CPUID_PSE36 | CPUID_VME, 1610 .features[FEAT_1_ECX] = 1611 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 | 1612 CPUID_EXT_POPCNT, 1613 .features[FEAT_8000_0001_EDX] = 1614 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | 1615 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT | 1616 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP, 1617 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, 1618 CPUID_EXT3_CR8LEG, 1619 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, 1620 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */ 1621 .features[FEAT_8000_0001_ECX] = 1622 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | 1623 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A, 1624 /* Missing: CPUID_SVM_LBRV */ 1625 .features[FEAT_SVM] = 1626 CPUID_SVM_NPT, 1627 .xlevel = 0x8000001A, 1628 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor" 1629 }, 1630 { 1631 .name = "core2duo", 1632 .level = 10, 1633 .vendor = CPUID_VENDOR_INTEL, 1634 .family = 6, 1635 .model = 15, 1636 .stepping = 11, 1637 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 1638 .features[FEAT_1_EDX] = 1639 PPRO_FEATURES | 1640 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 1641 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS, 1642 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST, 1643 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */ 1644 .features[FEAT_1_ECX] = 1645 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | 1646 CPUID_EXT_CX16, 1647 .features[FEAT_8000_0001_EDX] = 1648 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 1649 .features[FEAT_8000_0001_ECX] = 1650 CPUID_EXT3_LAHF_LM, 1651 .xlevel = 0x80000008, 1652 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz", 1653 }, 1654 { 1655 .name = "kvm64", 1656 .level = 0xd, 1657 .vendor = CPUID_VENDOR_INTEL, 1658 .family = 15, 1659 .model = 6, 1660 .stepping = 1, 1661 /* Missing: CPUID_HT */ 1662 .features[FEAT_1_EDX] = 1663 PPRO_FEATURES | CPUID_VME | 1664 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 1665 CPUID_PSE36, 1666 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */ 1667 .features[FEAT_1_ECX] = 1668 CPUID_EXT_SSE3 | CPUID_EXT_CX16, 1669 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */ 1670 .features[FEAT_8000_0001_EDX] = 1671 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 1672 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, 1673 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A, 1674 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, 1675 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */ 1676 .features[FEAT_8000_0001_ECX] = 1677 0, 1678 .xlevel = 0x80000008, 1679 .model_id = "Common KVM processor" 1680 }, 1681 { 1682 .name = "qemu32", 1683 .level = 4, 1684 .vendor = CPUID_VENDOR_INTEL, 1685 .family = 6, 1686 .model = 6, 1687 .stepping = 3, 1688 .features[FEAT_1_EDX] = 1689 PPRO_FEATURES, 1690 .features[FEAT_1_ECX] = 1691 CPUID_EXT_SSE3, 1692 .xlevel = 0x80000004, 1693 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 1694 }, 1695 { 1696 .name = "kvm32", 1697 .level = 5, 1698 .vendor = CPUID_VENDOR_INTEL, 1699 .family = 15, 1700 .model = 6, 1701 .stepping = 1, 1702 .features[FEAT_1_EDX] = 1703 PPRO_FEATURES | CPUID_VME | 1704 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36, 1705 .features[FEAT_1_ECX] = 1706 CPUID_EXT_SSE3, 1707 .features[FEAT_8000_0001_ECX] = 1708 0, 1709 .xlevel = 0x80000008, 1710 .model_id = "Common 32-bit KVM processor" 1711 }, 1712 { 1713 .name = "coreduo", 1714 .level = 10, 1715 .vendor = CPUID_VENDOR_INTEL, 1716 .family = 6, 1717 .model = 14, 1718 .stepping = 8, 1719 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 1720 .features[FEAT_1_EDX] = 1721 PPRO_FEATURES | CPUID_VME | 1722 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI | 1723 CPUID_SS, 1724 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR, 1725 * CPUID_EXT_PDCM, CPUID_EXT_VMX */ 1726 .features[FEAT_1_ECX] = 1727 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR, 1728 .features[FEAT_8000_0001_EDX] = 1729 CPUID_EXT2_NX, 1730 .xlevel = 0x80000008, 1731 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz", 1732 }, 1733 { 1734 .name = "486", 1735 .level = 1, 1736 .vendor = CPUID_VENDOR_INTEL, 1737 .family = 4, 1738 .model = 8, 1739 .stepping = 0, 1740 .features[FEAT_1_EDX] = 1741 I486_FEATURES, 1742 .xlevel = 0, 1743 .model_id = "", 1744 }, 1745 { 1746 .name = "pentium", 1747 .level = 1, 1748 .vendor = CPUID_VENDOR_INTEL, 1749 .family = 5, 1750 .model = 4, 1751 .stepping = 3, 1752 .features[FEAT_1_EDX] = 1753 PENTIUM_FEATURES, 1754 .xlevel = 0, 1755 .model_id = "", 1756 }, 1757 { 1758 .name = "pentium2", 1759 .level = 2, 1760 .vendor = CPUID_VENDOR_INTEL, 1761 .family = 6, 1762 .model = 5, 1763 .stepping = 2, 1764 .features[FEAT_1_EDX] = 1765 PENTIUM2_FEATURES, 1766 .xlevel = 0, 1767 .model_id = "", 1768 }, 1769 { 1770 .name = "pentium3", 1771 .level = 3, 1772 .vendor = CPUID_VENDOR_INTEL, 1773 .family = 6, 1774 .model = 7, 1775 .stepping = 3, 1776 .features[FEAT_1_EDX] = 1777 PENTIUM3_FEATURES, 1778 .xlevel = 0, 1779 .model_id = "", 1780 }, 1781 { 1782 .name = "athlon", 1783 .level = 2, 1784 .vendor = CPUID_VENDOR_AMD, 1785 .family = 6, 1786 .model = 2, 1787 .stepping = 3, 1788 .features[FEAT_1_EDX] = 1789 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR | 1790 CPUID_MCA, 1791 .features[FEAT_8000_0001_EDX] = 1792 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT, 1793 .xlevel = 0x80000008, 1794 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 1795 }, 1796 { 1797 .name = "n270", 1798 .level = 10, 1799 .vendor = CPUID_VENDOR_INTEL, 1800 .family = 6, 1801 .model = 28, 1802 .stepping = 2, 1803 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 1804 .features[FEAT_1_EDX] = 1805 PPRO_FEATURES | 1806 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | 1807 CPUID_ACPI | CPUID_SS, 1808 /* Some CPUs got no CPUID_SEP */ 1809 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2, 1810 * CPUID_EXT_XTPR */ 1811 .features[FEAT_1_ECX] = 1812 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | 1813 CPUID_EXT_MOVBE, 1814 .features[FEAT_8000_0001_EDX] = 1815 CPUID_EXT2_NX, 1816 .features[FEAT_8000_0001_ECX] = 1817 CPUID_EXT3_LAHF_LM, 1818 .xlevel = 0x80000008, 1819 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz", 1820 }, 1821 { 1822 .name = "Conroe", 1823 .level = 10, 1824 .vendor = CPUID_VENDOR_INTEL, 1825 .family = 6, 1826 .model = 15, 1827 .stepping = 3, 1828 .features[FEAT_1_EDX] = 1829 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 1830 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 1831 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 1832 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 1833 CPUID_DE | CPUID_FP87, 1834 .features[FEAT_1_ECX] = 1835 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, 1836 .features[FEAT_8000_0001_EDX] = 1837 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 1838 .features[FEAT_8000_0001_ECX] = 1839 CPUID_EXT3_LAHF_LM, 1840 .xlevel = 0x80000008, 1841 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)", 1842 }, 1843 { 1844 .name = "Penryn", 1845 .level = 10, 1846 .vendor = CPUID_VENDOR_INTEL, 1847 .family = 6, 1848 .model = 23, 1849 .stepping = 3, 1850 .features[FEAT_1_EDX] = 1851 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 1852 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 1853 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 1854 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 1855 CPUID_DE | CPUID_FP87, 1856 .features[FEAT_1_ECX] = 1857 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 1858 CPUID_EXT_SSE3, 1859 .features[FEAT_8000_0001_EDX] = 1860 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 1861 .features[FEAT_8000_0001_ECX] = 1862 CPUID_EXT3_LAHF_LM, 1863 .xlevel = 0x80000008, 1864 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)", 1865 }, 1866 { 1867 .name = "Nehalem", 1868 .level = 11, 1869 .vendor = CPUID_VENDOR_INTEL, 1870 .family = 6, 1871 .model = 26, 1872 .stepping = 3, 1873 .features[FEAT_1_EDX] = 1874 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 1875 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 1876 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 1877 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 1878 CPUID_DE | CPUID_FP87, 1879 .features[FEAT_1_ECX] = 1880 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 1881 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, 1882 .features[FEAT_8000_0001_EDX] = 1883 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 1884 .features[FEAT_8000_0001_ECX] = 1885 CPUID_EXT3_LAHF_LM, 1886 .xlevel = 0x80000008, 1887 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)", 1888 .versions = (X86CPUVersionDefinition[]) { 1889 { .version = 1 }, 1890 { 1891 .version = 2, 1892 .alias = "Nehalem-IBRS", 1893 .props = (PropValue[]) { 1894 { "spec-ctrl", "on" }, 1895 { "model-id", 1896 "Intel Core i7 9xx (Nehalem Core i7, IBRS update)" }, 1897 { /* end of list */ } 1898 } 1899 }, 1900 { /* end of list */ } 1901 } 1902 }, 1903 { 1904 .name = "Westmere", 1905 .level = 11, 1906 .vendor = CPUID_VENDOR_INTEL, 1907 .family = 6, 1908 .model = 44, 1909 .stepping = 1, 1910 .features[FEAT_1_EDX] = 1911 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 1912 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 1913 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 1914 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 1915 CPUID_DE | CPUID_FP87, 1916 .features[FEAT_1_ECX] = 1917 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | 1918 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 1919 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 1920 .features[FEAT_8000_0001_EDX] = 1921 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 1922 .features[FEAT_8000_0001_ECX] = 1923 CPUID_EXT3_LAHF_LM, 1924 .features[FEAT_6_EAX] = 1925 CPUID_6_EAX_ARAT, 1926 .xlevel = 0x80000008, 1927 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)", 1928 .versions = (X86CPUVersionDefinition[]) { 1929 { .version = 1 }, 1930 { 1931 .version = 2, 1932 .alias = "Westmere-IBRS", 1933 .props = (PropValue[]) { 1934 { "spec-ctrl", "on" }, 1935 { "model-id", 1936 "Westmere E56xx/L56xx/X56xx (IBRS update)" }, 1937 { /* end of list */ } 1938 } 1939 }, 1940 { /* end of list */ } 1941 } 1942 }, 1943 { 1944 .name = "SandyBridge", 1945 .level = 0xd, 1946 .vendor = CPUID_VENDOR_INTEL, 1947 .family = 6, 1948 .model = 42, 1949 .stepping = 1, 1950 .features[FEAT_1_EDX] = 1951 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 1952 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 1953 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 1954 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 1955 CPUID_DE | CPUID_FP87, 1956 .features[FEAT_1_ECX] = 1957 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 1958 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | 1959 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 1960 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 1961 CPUID_EXT_SSE3, 1962 .features[FEAT_8000_0001_EDX] = 1963 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 1964 CPUID_EXT2_SYSCALL, 1965 .features[FEAT_8000_0001_ECX] = 1966 CPUID_EXT3_LAHF_LM, 1967 .features[FEAT_XSAVE] = 1968 CPUID_XSAVE_XSAVEOPT, 1969 .features[FEAT_6_EAX] = 1970 CPUID_6_EAX_ARAT, 1971 .xlevel = 0x80000008, 1972 .model_id = "Intel Xeon E312xx (Sandy Bridge)", 1973 .versions = (X86CPUVersionDefinition[]) { 1974 { .version = 1 }, 1975 { 1976 .version = 2, 1977 .alias = "SandyBridge-IBRS", 1978 .props = (PropValue[]) { 1979 { "spec-ctrl", "on" }, 1980 { "model-id", 1981 "Intel Xeon E312xx (Sandy Bridge, IBRS update)" }, 1982 { /* end of list */ } 1983 } 1984 }, 1985 { /* end of list */ } 1986 } 1987 }, 1988 { 1989 .name = "IvyBridge", 1990 .level = 0xd, 1991 .vendor = CPUID_VENDOR_INTEL, 1992 .family = 6, 1993 .model = 58, 1994 .stepping = 9, 1995 .features[FEAT_1_EDX] = 1996 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 1997 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 1998 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 1999 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2000 CPUID_DE | CPUID_FP87, 2001 .features[FEAT_1_ECX] = 2002 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2003 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | 2004 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 2005 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 2006 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 2007 .features[FEAT_7_0_EBX] = 2008 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | 2009 CPUID_7_0_EBX_ERMS, 2010 .features[FEAT_8000_0001_EDX] = 2011 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 2012 CPUID_EXT2_SYSCALL, 2013 .features[FEAT_8000_0001_ECX] = 2014 CPUID_EXT3_LAHF_LM, 2015 .features[FEAT_XSAVE] = 2016 CPUID_XSAVE_XSAVEOPT, 2017 .features[FEAT_6_EAX] = 2018 CPUID_6_EAX_ARAT, 2019 .xlevel = 0x80000008, 2020 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)", 2021 .versions = (X86CPUVersionDefinition[]) { 2022 { .version = 1 }, 2023 { 2024 .version = 2, 2025 .alias = "IvyBridge-IBRS", 2026 .props = (PropValue[]) { 2027 { "spec-ctrl", "on" }, 2028 { "model-id", 2029 "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)" }, 2030 { /* end of list */ } 2031 } 2032 }, 2033 { /* end of list */ } 2034 } 2035 }, 2036 { 2037 .name = "Haswell", 2038 .level = 0xd, 2039 .vendor = CPUID_VENDOR_INTEL, 2040 .family = 6, 2041 .model = 60, 2042 .stepping = 4, 2043 .features[FEAT_1_EDX] = 2044 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2045 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2046 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2047 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2048 CPUID_DE | CPUID_FP87, 2049 .features[FEAT_1_ECX] = 2050 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2051 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 2052 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2053 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 2054 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 2055 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 2056 .features[FEAT_8000_0001_EDX] = 2057 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 2058 CPUID_EXT2_SYSCALL, 2059 .features[FEAT_8000_0001_ECX] = 2060 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM, 2061 .features[FEAT_7_0_EBX] = 2062 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 2063 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 2064 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 2065 CPUID_7_0_EBX_RTM, 2066 .features[FEAT_XSAVE] = 2067 CPUID_XSAVE_XSAVEOPT, 2068 .features[FEAT_6_EAX] = 2069 CPUID_6_EAX_ARAT, 2070 .xlevel = 0x80000008, 2071 .model_id = "Intel Core Processor (Haswell)", 2072 .versions = (X86CPUVersionDefinition[]) { 2073 { .version = 1 }, 2074 { 2075 .version = 2, 2076 .alias = "Haswell-noTSX", 2077 .props = (PropValue[]) { 2078 { "hle", "off" }, 2079 { "rtm", "off" }, 2080 { "stepping", "1" }, 2081 { "model-id", "Intel Core Processor (Haswell, no TSX)", }, 2082 { /* end of list */ } 2083 }, 2084 }, 2085 { 2086 .version = 3, 2087 .alias = "Haswell-IBRS", 2088 .props = (PropValue[]) { 2089 /* Restore TSX features removed by -v2 above */ 2090 { "hle", "on" }, 2091 { "rtm", "on" }, 2092 /* 2093 * Haswell and Haswell-IBRS had stepping=4 in 2094 * QEMU 4.0 and older 2095 */ 2096 { "stepping", "4" }, 2097 { "spec-ctrl", "on" }, 2098 { "model-id", 2099 "Intel Core Processor (Haswell, IBRS)" }, 2100 { /* end of list */ } 2101 } 2102 }, 2103 { 2104 .version = 4, 2105 .alias = "Haswell-noTSX-IBRS", 2106 .props = (PropValue[]) { 2107 { "hle", "off" }, 2108 { "rtm", "off" }, 2109 /* spec-ctrl was already enabled by -v3 above */ 2110 { "stepping", "1" }, 2111 { "model-id", 2112 "Intel Core Processor (Haswell, no TSX, IBRS)" }, 2113 { /* end of list */ } 2114 } 2115 }, 2116 { /* end of list */ } 2117 } 2118 }, 2119 { 2120 .name = "Broadwell", 2121 .level = 0xd, 2122 .vendor = CPUID_VENDOR_INTEL, 2123 .family = 6, 2124 .model = 61, 2125 .stepping = 2, 2126 .features[FEAT_1_EDX] = 2127 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2128 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2129 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2130 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2131 CPUID_DE | CPUID_FP87, 2132 .features[FEAT_1_ECX] = 2133 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2134 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 2135 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2136 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 2137 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 2138 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 2139 .features[FEAT_8000_0001_EDX] = 2140 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 2141 CPUID_EXT2_SYSCALL, 2142 .features[FEAT_8000_0001_ECX] = 2143 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 2144 .features[FEAT_7_0_EBX] = 2145 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 2146 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 2147 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 2148 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 2149 CPUID_7_0_EBX_SMAP, 2150 .features[FEAT_XSAVE] = 2151 CPUID_XSAVE_XSAVEOPT, 2152 .features[FEAT_6_EAX] = 2153 CPUID_6_EAX_ARAT, 2154 .xlevel = 0x80000008, 2155 .model_id = "Intel Core Processor (Broadwell)", 2156 .versions = (X86CPUVersionDefinition[]) { 2157 { .version = 1 }, 2158 { 2159 .version = 2, 2160 .alias = "Broadwell-noTSX", 2161 .props = (PropValue[]) { 2162 { "hle", "off" }, 2163 { "rtm", "off" }, 2164 { "model-id", "Intel Core Processor (Broadwell, no TSX)", }, 2165 { /* end of list */ } 2166 }, 2167 }, 2168 { 2169 .version = 3, 2170 .alias = "Broadwell-IBRS", 2171 .props = (PropValue[]) { 2172 /* Restore TSX features removed by -v2 above */ 2173 { "hle", "on" }, 2174 { "rtm", "on" }, 2175 { "spec-ctrl", "on" }, 2176 { "model-id", 2177 "Intel Core Processor (Broadwell, IBRS)" }, 2178 { /* end of list */ } 2179 } 2180 }, 2181 { 2182 .version = 4, 2183 .alias = "Broadwell-noTSX-IBRS", 2184 .props = (PropValue[]) { 2185 { "hle", "off" }, 2186 { "rtm", "off" }, 2187 /* spec-ctrl was already enabled by -v3 above */ 2188 { "model-id", 2189 "Intel Core Processor (Broadwell, no TSX, IBRS)" }, 2190 { /* end of list */ } 2191 } 2192 }, 2193 { /* end of list */ } 2194 } 2195 }, 2196 { 2197 .name = "Skylake-Client", 2198 .level = 0xd, 2199 .vendor = CPUID_VENDOR_INTEL, 2200 .family = 6, 2201 .model = 94, 2202 .stepping = 3, 2203 .features[FEAT_1_EDX] = 2204 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2205 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2206 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2207 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2208 CPUID_DE | CPUID_FP87, 2209 .features[FEAT_1_ECX] = 2210 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2211 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 2212 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2213 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 2214 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 2215 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 2216 .features[FEAT_8000_0001_EDX] = 2217 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 2218 CPUID_EXT2_SYSCALL, 2219 .features[FEAT_8000_0001_ECX] = 2220 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 2221 .features[FEAT_7_0_EBX] = 2222 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 2223 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 2224 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 2225 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 2226 CPUID_7_0_EBX_SMAP, 2227 /* Missing: XSAVES (not supported by some Linux versions, 2228 * including v4.1 to v4.12). 2229 * KVM doesn't yet expose any XSAVES state save component, 2230 * and the only one defined in Skylake (processor tracing) 2231 * probably will block migration anyway. 2232 */ 2233 .features[FEAT_XSAVE] = 2234 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 2235 CPUID_XSAVE_XGETBV1, 2236 .features[FEAT_6_EAX] = 2237 CPUID_6_EAX_ARAT, 2238 .xlevel = 0x80000008, 2239 .model_id = "Intel Core Processor (Skylake)", 2240 .versions = (X86CPUVersionDefinition[]) { 2241 { .version = 1 }, 2242 { 2243 .version = 2, 2244 .alias = "Skylake-Client-IBRS", 2245 .props = (PropValue[]) { 2246 { "spec-ctrl", "on" }, 2247 { "model-id", 2248 "Intel Core Processor (Skylake, IBRS)" }, 2249 { /* end of list */ } 2250 } 2251 }, 2252 { /* end of list */ } 2253 } 2254 }, 2255 { 2256 .name = "Skylake-Server", 2257 .level = 0xd, 2258 .vendor = CPUID_VENDOR_INTEL, 2259 .family = 6, 2260 .model = 85, 2261 .stepping = 4, 2262 .features[FEAT_1_EDX] = 2263 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2264 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2265 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2266 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2267 CPUID_DE | CPUID_FP87, 2268 .features[FEAT_1_ECX] = 2269 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2270 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 2271 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2272 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 2273 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 2274 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 2275 .features[FEAT_8000_0001_EDX] = 2276 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 2277 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 2278 .features[FEAT_8000_0001_ECX] = 2279 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 2280 .features[FEAT_7_0_EBX] = 2281 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 2282 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 2283 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 2284 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 2285 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 2286 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 2287 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 2288 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 2289 .features[FEAT_7_0_ECX] = 2290 CPUID_7_0_ECX_PKU, 2291 /* Missing: XSAVES (not supported by some Linux versions, 2292 * including v4.1 to v4.12). 2293 * KVM doesn't yet expose any XSAVES state save component, 2294 * and the only one defined in Skylake (processor tracing) 2295 * probably will block migration anyway. 2296 */ 2297 .features[FEAT_XSAVE] = 2298 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 2299 CPUID_XSAVE_XGETBV1, 2300 .features[FEAT_6_EAX] = 2301 CPUID_6_EAX_ARAT, 2302 .xlevel = 0x80000008, 2303 .model_id = "Intel Xeon Processor (Skylake)", 2304 .versions = (X86CPUVersionDefinition[]) { 2305 { .version = 1 }, 2306 { 2307 .version = 2, 2308 .alias = "Skylake-Server-IBRS", 2309 .props = (PropValue[]) { 2310 /* clflushopt was not added to Skylake-Server-IBRS */ 2311 /* TODO: add -v3 including clflushopt */ 2312 { "clflushopt", "off" }, 2313 { "spec-ctrl", "on" }, 2314 { "model-id", 2315 "Intel Xeon Processor (Skylake, IBRS)" }, 2316 { /* end of list */ } 2317 } 2318 }, 2319 { /* end of list */ } 2320 } 2321 }, 2322 { 2323 .name = "Cascadelake-Server", 2324 .level = 0xd, 2325 .vendor = CPUID_VENDOR_INTEL, 2326 .family = 6, 2327 .model = 85, 2328 .stepping = 6, 2329 .features[FEAT_1_EDX] = 2330 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2331 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2332 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2333 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2334 CPUID_DE | CPUID_FP87, 2335 .features[FEAT_1_ECX] = 2336 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2337 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 2338 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2339 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 2340 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 2341 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 2342 .features[FEAT_8000_0001_EDX] = 2343 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 2344 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 2345 .features[FEAT_8000_0001_ECX] = 2346 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 2347 .features[FEAT_7_0_EBX] = 2348 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 2349 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 2350 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 2351 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 2352 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 2353 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 2354 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 2355 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 2356 .features[FEAT_7_0_ECX] = 2357 CPUID_7_0_ECX_PKU | 2358 CPUID_7_0_ECX_AVX512VNNI, 2359 .features[FEAT_7_0_EDX] = 2360 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 2361 /* Missing: XSAVES (not supported by some Linux versions, 2362 * including v4.1 to v4.12). 2363 * KVM doesn't yet expose any XSAVES state save component, 2364 * and the only one defined in Skylake (processor tracing) 2365 * probably will block migration anyway. 2366 */ 2367 .features[FEAT_XSAVE] = 2368 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 2369 CPUID_XSAVE_XGETBV1, 2370 .features[FEAT_6_EAX] = 2371 CPUID_6_EAX_ARAT, 2372 .xlevel = 0x80000008, 2373 .model_id = "Intel Xeon Processor (Cascadelake)", 2374 .versions = (X86CPUVersionDefinition[]) { 2375 { .version = 1 }, 2376 { .version = 2, 2377 .props = (PropValue[]) { 2378 { "arch-capabilities", "on" }, 2379 { "rdctl-no", "on" }, 2380 { "ibrs-all", "on" }, 2381 { "skip-l1dfl-vmentry", "on" }, 2382 { "mds-no", "on" }, 2383 { /* end of list */ } 2384 }, 2385 }, 2386 { /* end of list */ } 2387 } 2388 }, 2389 { 2390 .name = "Icelake-Client", 2391 .level = 0xd, 2392 .vendor = CPUID_VENDOR_INTEL, 2393 .family = 6, 2394 .model = 126, 2395 .stepping = 0, 2396 .features[FEAT_1_EDX] = 2397 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2398 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2399 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2400 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2401 CPUID_DE | CPUID_FP87, 2402 .features[FEAT_1_ECX] = 2403 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2404 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 2405 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2406 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 2407 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 2408 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 2409 .features[FEAT_8000_0001_EDX] = 2410 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 2411 CPUID_EXT2_SYSCALL, 2412 .features[FEAT_8000_0001_ECX] = 2413 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 2414 .features[FEAT_8000_0008_EBX] = 2415 CPUID_8000_0008_EBX_WBNOINVD, 2416 .features[FEAT_7_0_EBX] = 2417 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 2418 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 2419 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 2420 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 2421 CPUID_7_0_EBX_SMAP, 2422 .features[FEAT_7_0_ECX] = 2423 CPUID_7_0_ECX_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 2424 CPUID_7_0_ECX_VBMI2 | CPUID_7_0_ECX_GFNI | 2425 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 2426 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 2427 CPUID_7_0_ECX_AVX512_VPOPCNTDQ, 2428 .features[FEAT_7_0_EDX] = 2429 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 2430 /* Missing: XSAVES (not supported by some Linux versions, 2431 * including v4.1 to v4.12). 2432 * KVM doesn't yet expose any XSAVES state save component, 2433 * and the only one defined in Skylake (processor tracing) 2434 * probably will block migration anyway. 2435 */ 2436 .features[FEAT_XSAVE] = 2437 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 2438 CPUID_XSAVE_XGETBV1, 2439 .features[FEAT_6_EAX] = 2440 CPUID_6_EAX_ARAT, 2441 .xlevel = 0x80000008, 2442 .model_id = "Intel Core Processor (Icelake)", 2443 }, 2444 { 2445 .name = "Icelake-Server", 2446 .level = 0xd, 2447 .vendor = CPUID_VENDOR_INTEL, 2448 .family = 6, 2449 .model = 134, 2450 .stepping = 0, 2451 .features[FEAT_1_EDX] = 2452 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2453 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2454 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2455 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2456 CPUID_DE | CPUID_FP87, 2457 .features[FEAT_1_ECX] = 2458 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2459 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 2460 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2461 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 2462 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 2463 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 2464 .features[FEAT_8000_0001_EDX] = 2465 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 2466 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 2467 .features[FEAT_8000_0001_ECX] = 2468 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 2469 .features[FEAT_8000_0008_EBX] = 2470 CPUID_8000_0008_EBX_WBNOINVD, 2471 .features[FEAT_7_0_EBX] = 2472 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 2473 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 2474 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 2475 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 2476 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 2477 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 2478 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 2479 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 2480 .features[FEAT_7_0_ECX] = 2481 CPUID_7_0_ECX_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 2482 CPUID_7_0_ECX_VBMI2 | CPUID_7_0_ECX_GFNI | 2483 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 2484 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 2485 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57, 2486 .features[FEAT_7_0_EDX] = 2487 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 2488 /* Missing: XSAVES (not supported by some Linux versions, 2489 * including v4.1 to v4.12). 2490 * KVM doesn't yet expose any XSAVES state save component, 2491 * and the only one defined in Skylake (processor tracing) 2492 * probably will block migration anyway. 2493 */ 2494 .features[FEAT_XSAVE] = 2495 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 2496 CPUID_XSAVE_XGETBV1, 2497 .features[FEAT_6_EAX] = 2498 CPUID_6_EAX_ARAT, 2499 .xlevel = 0x80000008, 2500 .model_id = "Intel Xeon Processor (Icelake)", 2501 }, 2502 { 2503 .name = "Snowridge", 2504 .level = 27, 2505 .vendor = CPUID_VENDOR_INTEL, 2506 .family = 6, 2507 .model = 134, 2508 .stepping = 1, 2509 .features[FEAT_1_EDX] = 2510 /* missing: CPUID_PN CPUID_IA64 */ 2511 /* missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2512 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | 2513 CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_MCE | 2514 CPUID_CX8 | CPUID_APIC | CPUID_SEP | 2515 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 2516 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | 2517 CPUID_MMX | 2518 CPUID_FXSR | CPUID_SSE | CPUID_SSE2, 2519 .features[FEAT_1_ECX] = 2520 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR | 2521 CPUID_EXT_SSSE3 | 2522 CPUID_EXT_CX16 | 2523 CPUID_EXT_SSE41 | 2524 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 2525 CPUID_EXT_POPCNT | 2526 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | CPUID_EXT_XSAVE | 2527 CPUID_EXT_RDRAND, 2528 .features[FEAT_8000_0001_EDX] = 2529 CPUID_EXT2_SYSCALL | 2530 CPUID_EXT2_NX | 2531 CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 2532 CPUID_EXT2_LM, 2533 .features[FEAT_8000_0001_ECX] = 2534 CPUID_EXT3_LAHF_LM | 2535 CPUID_EXT3_3DNOWPREFETCH, 2536 .features[FEAT_7_0_EBX] = 2537 CPUID_7_0_EBX_FSGSBASE | 2538 CPUID_7_0_EBX_SMEP | 2539 CPUID_7_0_EBX_ERMS | 2540 CPUID_7_0_EBX_MPX | /* missing bits 13, 15 */ 2541 CPUID_7_0_EBX_RDSEED | 2542 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 2543 CPUID_7_0_EBX_CLWB | 2544 CPUID_7_0_EBX_SHA_NI, 2545 .features[FEAT_7_0_ECX] = 2546 CPUID_7_0_ECX_UMIP | 2547 /* missing bit 5 */ 2548 CPUID_7_0_ECX_GFNI | 2549 CPUID_7_0_ECX_MOVDIRI | CPUID_7_0_ECX_CLDEMOTE | 2550 CPUID_7_0_ECX_MOVDIR64B, 2551 .features[FEAT_7_0_EDX] = 2552 CPUID_7_0_EDX_SPEC_CTRL | 2553 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD | 2554 CPUID_7_0_EDX_CORE_CAPABILITY, 2555 .features[FEAT_CORE_CAPABILITY] = 2556 MSR_CORE_CAP_SPLIT_LOCK_DETECT, 2557 /* 2558 * Missing: XSAVES (not supported by some Linux versions, 2559 * including v4.1 to v4.12). 2560 * KVM doesn't yet expose any XSAVES state save component, 2561 * and the only one defined in Skylake (processor tracing) 2562 * probably will block migration anyway. 2563 */ 2564 .features[FEAT_XSAVE] = 2565 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 2566 CPUID_XSAVE_XGETBV1, 2567 .features[FEAT_6_EAX] = 2568 CPUID_6_EAX_ARAT, 2569 .xlevel = 0x80000008, 2570 .model_id = "Intel Atom Processor (SnowRidge)", 2571 }, 2572 { 2573 .name = "KnightsMill", 2574 .level = 0xd, 2575 .vendor = CPUID_VENDOR_INTEL, 2576 .family = 6, 2577 .model = 133, 2578 .stepping = 0, 2579 .features[FEAT_1_EDX] = 2580 CPUID_VME | CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | 2581 CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | 2582 CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | 2583 CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | 2584 CPUID_PSE | CPUID_DE | CPUID_FP87, 2585 .features[FEAT_1_ECX] = 2586 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2587 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 2588 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2589 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 2590 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 2591 CPUID_EXT_F16C | CPUID_EXT_RDRAND, 2592 .features[FEAT_8000_0001_EDX] = 2593 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 2594 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 2595 .features[FEAT_8000_0001_ECX] = 2596 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 2597 .features[FEAT_7_0_EBX] = 2598 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 2599 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 2600 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_AVX512F | 2601 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_AVX512PF | 2602 CPUID_7_0_EBX_AVX512ER, 2603 .features[FEAT_7_0_ECX] = 2604 CPUID_7_0_ECX_AVX512_VPOPCNTDQ, 2605 .features[FEAT_7_0_EDX] = 2606 CPUID_7_0_EDX_AVX512_4VNNIW | CPUID_7_0_EDX_AVX512_4FMAPS, 2607 .features[FEAT_XSAVE] = 2608 CPUID_XSAVE_XSAVEOPT, 2609 .features[FEAT_6_EAX] = 2610 CPUID_6_EAX_ARAT, 2611 .xlevel = 0x80000008, 2612 .model_id = "Intel Xeon Phi Processor (Knights Mill)", 2613 }, 2614 { 2615 .name = "Opteron_G1", 2616 .level = 5, 2617 .vendor = CPUID_VENDOR_AMD, 2618 .family = 15, 2619 .model = 6, 2620 .stepping = 1, 2621 .features[FEAT_1_EDX] = 2622 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2623 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2624 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2625 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2626 CPUID_DE | CPUID_FP87, 2627 .features[FEAT_1_ECX] = 2628 CPUID_EXT_SSE3, 2629 .features[FEAT_8000_0001_EDX] = 2630 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 2631 .xlevel = 0x80000008, 2632 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)", 2633 }, 2634 { 2635 .name = "Opteron_G2", 2636 .level = 5, 2637 .vendor = CPUID_VENDOR_AMD, 2638 .family = 15, 2639 .model = 6, 2640 .stepping = 1, 2641 .features[FEAT_1_EDX] = 2642 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2643 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2644 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2645 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2646 CPUID_DE | CPUID_FP87, 2647 .features[FEAT_1_ECX] = 2648 CPUID_EXT_CX16 | CPUID_EXT_SSE3, 2649 .features[FEAT_8000_0001_EDX] = 2650 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 2651 .features[FEAT_8000_0001_ECX] = 2652 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, 2653 .xlevel = 0x80000008, 2654 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)", 2655 }, 2656 { 2657 .name = "Opteron_G3", 2658 .level = 5, 2659 .vendor = CPUID_VENDOR_AMD, 2660 .family = 16, 2661 .model = 2, 2662 .stepping = 3, 2663 .features[FEAT_1_EDX] = 2664 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2665 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2666 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2667 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2668 CPUID_DE | CPUID_FP87, 2669 .features[FEAT_1_ECX] = 2670 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR | 2671 CPUID_EXT_SSE3, 2672 .features[FEAT_8000_0001_EDX] = 2673 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL | 2674 CPUID_EXT2_RDTSCP, 2675 .features[FEAT_8000_0001_ECX] = 2676 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | 2677 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, 2678 .xlevel = 0x80000008, 2679 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)", 2680 }, 2681 { 2682 .name = "Opteron_G4", 2683 .level = 0xd, 2684 .vendor = CPUID_VENDOR_AMD, 2685 .family = 21, 2686 .model = 1, 2687 .stepping = 2, 2688 .features[FEAT_1_EDX] = 2689 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2690 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2691 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2692 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2693 CPUID_DE | CPUID_FP87, 2694 .features[FEAT_1_ECX] = 2695 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2696 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 2697 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 2698 CPUID_EXT_SSE3, 2699 .features[FEAT_8000_0001_EDX] = 2700 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX | 2701 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP, 2702 .features[FEAT_8000_0001_ECX] = 2703 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP | 2704 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | 2705 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | 2706 CPUID_EXT3_LAHF_LM, 2707 .features[FEAT_SVM] = 2708 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 2709 /* no xsaveopt! */ 2710 .xlevel = 0x8000001A, 2711 .model_id = "AMD Opteron 62xx class CPU", 2712 }, 2713 { 2714 .name = "Opteron_G5", 2715 .level = 0xd, 2716 .vendor = CPUID_VENDOR_AMD, 2717 .family = 21, 2718 .model = 2, 2719 .stepping = 0, 2720 .features[FEAT_1_EDX] = 2721 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2722 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2723 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2724 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2725 CPUID_DE | CPUID_FP87, 2726 .features[FEAT_1_ECX] = 2727 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE | 2728 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | 2729 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA | 2730 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 2731 .features[FEAT_8000_0001_EDX] = 2732 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX | 2733 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP, 2734 .features[FEAT_8000_0001_ECX] = 2735 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP | 2736 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | 2737 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | 2738 CPUID_EXT3_LAHF_LM, 2739 .features[FEAT_SVM] = 2740 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 2741 /* no xsaveopt! */ 2742 .xlevel = 0x8000001A, 2743 .model_id = "AMD Opteron 63xx class CPU", 2744 }, 2745 { 2746 .name = "EPYC", 2747 .level = 0xd, 2748 .vendor = CPUID_VENDOR_AMD, 2749 .family = 23, 2750 .model = 1, 2751 .stepping = 2, 2752 .features[FEAT_1_EDX] = 2753 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 2754 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 2755 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 2756 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 2757 CPUID_VME | CPUID_FP87, 2758 .features[FEAT_1_ECX] = 2759 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 2760 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 2761 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 2762 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 2763 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 2764 .features[FEAT_8000_0001_EDX] = 2765 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 2766 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 2767 CPUID_EXT2_SYSCALL, 2768 .features[FEAT_8000_0001_ECX] = 2769 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 2770 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 2771 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 2772 CPUID_EXT3_TOPOEXT, 2773 .features[FEAT_7_0_EBX] = 2774 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 2775 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 2776 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 2777 CPUID_7_0_EBX_SHA_NI, 2778 /* Missing: XSAVES (not supported by some Linux versions, 2779 * including v4.1 to v4.12). 2780 * KVM doesn't yet expose any XSAVES state save component. 2781 */ 2782 .features[FEAT_XSAVE] = 2783 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 2784 CPUID_XSAVE_XGETBV1, 2785 .features[FEAT_6_EAX] = 2786 CPUID_6_EAX_ARAT, 2787 .features[FEAT_SVM] = 2788 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 2789 .xlevel = 0x8000001E, 2790 .model_id = "AMD EPYC Processor", 2791 .cache_info = &epyc_cache_info, 2792 .versions = (X86CPUVersionDefinition[]) { 2793 { .version = 1 }, 2794 { 2795 .version = 2, 2796 .alias = "EPYC-IBPB", 2797 .props = (PropValue[]) { 2798 { "ibpb", "on" }, 2799 { "model-id", 2800 "AMD EPYC Processor (with IBPB)" }, 2801 { /* end of list */ } 2802 } 2803 }, 2804 { /* end of list */ } 2805 } 2806 }, 2807 { 2808 .name = "Dhyana", 2809 .level = 0xd, 2810 .vendor = CPUID_VENDOR_HYGON, 2811 .family = 24, 2812 .model = 0, 2813 .stepping = 1, 2814 .features[FEAT_1_EDX] = 2815 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 2816 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 2817 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 2818 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 2819 CPUID_VME | CPUID_FP87, 2820 .features[FEAT_1_ECX] = 2821 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 2822 CPUID_EXT_XSAVE | CPUID_EXT_POPCNT | 2823 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 2824 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 2825 CPUID_EXT_MONITOR | CPUID_EXT_SSE3, 2826 .features[FEAT_8000_0001_EDX] = 2827 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 2828 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 2829 CPUID_EXT2_SYSCALL, 2830 .features[FEAT_8000_0001_ECX] = 2831 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 2832 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 2833 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 2834 CPUID_EXT3_TOPOEXT, 2835 .features[FEAT_8000_0008_EBX] = 2836 CPUID_8000_0008_EBX_IBPB, 2837 .features[FEAT_7_0_EBX] = 2838 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 2839 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 2840 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT, 2841 /* 2842 * Missing: XSAVES (not supported by some Linux versions, 2843 * including v4.1 to v4.12). 2844 * KVM doesn't yet expose any XSAVES state save component. 2845 */ 2846 .features[FEAT_XSAVE] = 2847 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 2848 CPUID_XSAVE_XGETBV1, 2849 .features[FEAT_6_EAX] = 2850 CPUID_6_EAX_ARAT, 2851 .features[FEAT_SVM] = 2852 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 2853 .xlevel = 0x8000001E, 2854 .model_id = "Hygon Dhyana Processor", 2855 .cache_info = &epyc_cache_info, 2856 }, 2857 }; 2858 2859 /* KVM-specific features that are automatically added/removed 2860 * from all CPU models when KVM is enabled. 2861 */ 2862 static PropValue kvm_default_props[] = { 2863 { "kvmclock", "on" }, 2864 { "kvm-nopiodelay", "on" }, 2865 { "kvm-asyncpf", "on" }, 2866 { "kvm-steal-time", "on" }, 2867 { "kvm-pv-eoi", "on" }, 2868 { "kvmclock-stable-bit", "on" }, 2869 { "x2apic", "on" }, 2870 { "acpi", "off" }, 2871 { "monitor", "off" }, 2872 { "svm", "off" }, 2873 { NULL, NULL }, 2874 }; 2875 2876 /* TCG-specific defaults that override all CPU models when using TCG 2877 */ 2878 static PropValue tcg_default_props[] = { 2879 { "vme", "off" }, 2880 { NULL, NULL }, 2881 }; 2882 2883 2884 X86CPUVersion default_cpu_version = CPU_VERSION_LATEST; 2885 2886 void x86_cpu_set_default_version(X86CPUVersion version) 2887 { 2888 /* Translating CPU_VERSION_AUTO to CPU_VERSION_AUTO doesn't make sense */ 2889 assert(version != CPU_VERSION_AUTO); 2890 default_cpu_version = version; 2891 } 2892 2893 static X86CPUVersion x86_cpu_model_last_version(const X86CPUModel *model) 2894 { 2895 int v = 0; 2896 const X86CPUVersionDefinition *vdef = 2897 x86_cpu_def_get_versions(model->cpudef); 2898 while (vdef->version) { 2899 v = vdef->version; 2900 vdef++; 2901 } 2902 return v; 2903 } 2904 2905 /* Return the actual version being used for a specific CPU model */ 2906 static X86CPUVersion x86_cpu_model_resolve_version(const X86CPUModel *model) 2907 { 2908 X86CPUVersion v = model->version; 2909 if (v == CPU_VERSION_AUTO) { 2910 v = default_cpu_version; 2911 } 2912 if (v == CPU_VERSION_LATEST) { 2913 return x86_cpu_model_last_version(model); 2914 } 2915 return v; 2916 } 2917 2918 void x86_cpu_change_kvm_default(const char *prop, const char *value) 2919 { 2920 PropValue *pv; 2921 for (pv = kvm_default_props; pv->prop; pv++) { 2922 if (!strcmp(pv->prop, prop)) { 2923 pv->value = value; 2924 break; 2925 } 2926 } 2927 2928 /* It is valid to call this function only for properties that 2929 * are already present in the kvm_default_props table. 2930 */ 2931 assert(pv->prop); 2932 } 2933 2934 static uint64_t x86_cpu_get_supported_feature_word(FeatureWord w, 2935 bool migratable_only); 2936 2937 static bool lmce_supported(void) 2938 { 2939 uint64_t mce_cap = 0; 2940 2941 #ifdef CONFIG_KVM 2942 if (kvm_ioctl(kvm_state, KVM_X86_GET_MCE_CAP_SUPPORTED, &mce_cap) < 0) { 2943 return false; 2944 } 2945 #endif 2946 2947 return !!(mce_cap & MCG_LMCE_P); 2948 } 2949 2950 #define CPUID_MODEL_ID_SZ 48 2951 2952 /** 2953 * cpu_x86_fill_model_id: 2954 * Get CPUID model ID string from host CPU. 2955 * 2956 * @str should have at least CPUID_MODEL_ID_SZ bytes 2957 * 2958 * The function does NOT add a null terminator to the string 2959 * automatically. 2960 */ 2961 static int cpu_x86_fill_model_id(char *str) 2962 { 2963 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0; 2964 int i; 2965 2966 for (i = 0; i < 3; i++) { 2967 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx); 2968 memcpy(str + i * 16 + 0, &eax, 4); 2969 memcpy(str + i * 16 + 4, &ebx, 4); 2970 memcpy(str + i * 16 + 8, &ecx, 4); 2971 memcpy(str + i * 16 + 12, &edx, 4); 2972 } 2973 return 0; 2974 } 2975 2976 static Property max_x86_cpu_properties[] = { 2977 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true), 2978 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false), 2979 DEFINE_PROP_END_OF_LIST() 2980 }; 2981 2982 static void max_x86_cpu_class_init(ObjectClass *oc, void *data) 2983 { 2984 DeviceClass *dc = DEVICE_CLASS(oc); 2985 X86CPUClass *xcc = X86_CPU_CLASS(oc); 2986 2987 xcc->ordering = 9; 2988 2989 xcc->model_description = 2990 "Enables all features supported by the accelerator in the current host"; 2991 2992 dc->props = max_x86_cpu_properties; 2993 } 2994 2995 static void max_x86_cpu_initfn(Object *obj) 2996 { 2997 X86CPU *cpu = X86_CPU(obj); 2998 CPUX86State *env = &cpu->env; 2999 KVMState *s = kvm_state; 3000 3001 /* We can't fill the features array here because we don't know yet if 3002 * "migratable" is true or false. 3003 */ 3004 cpu->max_features = true; 3005 3006 if (accel_uses_host_cpuid()) { 3007 char vendor[CPUID_VENDOR_SZ + 1] = { 0 }; 3008 char model_id[CPUID_MODEL_ID_SZ + 1] = { 0 }; 3009 int family, model, stepping; 3010 3011 host_vendor_fms(vendor, &family, &model, &stepping); 3012 cpu_x86_fill_model_id(model_id); 3013 3014 object_property_set_str(OBJECT(cpu), vendor, "vendor", &error_abort); 3015 object_property_set_int(OBJECT(cpu), family, "family", &error_abort); 3016 object_property_set_int(OBJECT(cpu), model, "model", &error_abort); 3017 object_property_set_int(OBJECT(cpu), stepping, "stepping", 3018 &error_abort); 3019 object_property_set_str(OBJECT(cpu), model_id, "model-id", 3020 &error_abort); 3021 3022 if (kvm_enabled()) { 3023 env->cpuid_min_level = 3024 kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX); 3025 env->cpuid_min_xlevel = 3026 kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX); 3027 env->cpuid_min_xlevel2 = 3028 kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX); 3029 } else { 3030 env->cpuid_min_level = 3031 hvf_get_supported_cpuid(0x0, 0, R_EAX); 3032 env->cpuid_min_xlevel = 3033 hvf_get_supported_cpuid(0x80000000, 0, R_EAX); 3034 env->cpuid_min_xlevel2 = 3035 hvf_get_supported_cpuid(0xC0000000, 0, R_EAX); 3036 } 3037 3038 if (lmce_supported()) { 3039 object_property_set_bool(OBJECT(cpu), true, "lmce", &error_abort); 3040 } 3041 } else { 3042 object_property_set_str(OBJECT(cpu), CPUID_VENDOR_AMD, 3043 "vendor", &error_abort); 3044 object_property_set_int(OBJECT(cpu), 6, "family", &error_abort); 3045 object_property_set_int(OBJECT(cpu), 6, "model", &error_abort); 3046 object_property_set_int(OBJECT(cpu), 3, "stepping", &error_abort); 3047 object_property_set_str(OBJECT(cpu), 3048 "QEMU TCG CPU version " QEMU_HW_VERSION, 3049 "model-id", &error_abort); 3050 } 3051 3052 object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort); 3053 } 3054 3055 static const TypeInfo max_x86_cpu_type_info = { 3056 .name = X86_CPU_TYPE_NAME("max"), 3057 .parent = TYPE_X86_CPU, 3058 .instance_init = max_x86_cpu_initfn, 3059 .class_init = max_x86_cpu_class_init, 3060 }; 3061 3062 #if defined(CONFIG_KVM) || defined(CONFIG_HVF) 3063 static void host_x86_cpu_class_init(ObjectClass *oc, void *data) 3064 { 3065 X86CPUClass *xcc = X86_CPU_CLASS(oc); 3066 3067 xcc->host_cpuid_required = true; 3068 xcc->ordering = 8; 3069 3070 #if defined(CONFIG_KVM) 3071 xcc->model_description = 3072 "KVM processor with all supported host features "; 3073 #elif defined(CONFIG_HVF) 3074 xcc->model_description = 3075 "HVF processor with all supported host features "; 3076 #endif 3077 } 3078 3079 static const TypeInfo host_x86_cpu_type_info = { 3080 .name = X86_CPU_TYPE_NAME("host"), 3081 .parent = X86_CPU_TYPE_NAME("max"), 3082 .class_init = host_x86_cpu_class_init, 3083 }; 3084 3085 #endif 3086 3087 static char *feature_word_description(FeatureWordInfo *f, uint32_t bit) 3088 { 3089 assert(f->type == CPUID_FEATURE_WORD || f->type == MSR_FEATURE_WORD); 3090 3091 switch (f->type) { 3092 case CPUID_FEATURE_WORD: 3093 { 3094 const char *reg = get_register_name_32(f->cpuid.reg); 3095 assert(reg); 3096 return g_strdup_printf("CPUID.%02XH:%s", 3097 f->cpuid.eax, reg); 3098 } 3099 case MSR_FEATURE_WORD: 3100 return g_strdup_printf("MSR(%02XH)", 3101 f->msr.index); 3102 } 3103 3104 return NULL; 3105 } 3106 3107 static bool x86_cpu_have_filtered_features(X86CPU *cpu) 3108 { 3109 FeatureWord w; 3110 3111 for (w = 0; w < FEATURE_WORDS; w++) { 3112 if (cpu->filtered_features[w]) { 3113 return true; 3114 } 3115 } 3116 3117 return false; 3118 } 3119 3120 static void mark_unavailable_features(X86CPU *cpu, FeatureWord w, uint64_t mask, 3121 const char *verbose_prefix) 3122 { 3123 CPUX86State *env = &cpu->env; 3124 FeatureWordInfo *f = &feature_word_info[w]; 3125 int i; 3126 char *feat_word_str; 3127 3128 if (!cpu->force_features) { 3129 env->features[w] &= ~mask; 3130 } 3131 cpu->filtered_features[w] |= mask; 3132 3133 if (!verbose_prefix) { 3134 return; 3135 } 3136 3137 for (i = 0; i < 64; ++i) { 3138 if ((1ULL << i) & mask) { 3139 feat_word_str = feature_word_description(f, i); 3140 warn_report("%s: %s%s%s [bit %d]", 3141 verbose_prefix, 3142 feat_word_str, 3143 f->feat_names[i] ? "." : "", 3144 f->feat_names[i] ? f->feat_names[i] : "", i); 3145 g_free(feat_word_str); 3146 } 3147 } 3148 } 3149 3150 static void x86_cpuid_version_get_family(Object *obj, Visitor *v, 3151 const char *name, void *opaque, 3152 Error **errp) 3153 { 3154 X86CPU *cpu = X86_CPU(obj); 3155 CPUX86State *env = &cpu->env; 3156 int64_t value; 3157 3158 value = (env->cpuid_version >> 8) & 0xf; 3159 if (value == 0xf) { 3160 value += (env->cpuid_version >> 20) & 0xff; 3161 } 3162 visit_type_int(v, name, &value, errp); 3163 } 3164 3165 static void x86_cpuid_version_set_family(Object *obj, Visitor *v, 3166 const char *name, void *opaque, 3167 Error **errp) 3168 { 3169 X86CPU *cpu = X86_CPU(obj); 3170 CPUX86State *env = &cpu->env; 3171 const int64_t min = 0; 3172 const int64_t max = 0xff + 0xf; 3173 Error *local_err = NULL; 3174 int64_t value; 3175 3176 visit_type_int(v, name, &value, &local_err); 3177 if (local_err) { 3178 error_propagate(errp, local_err); 3179 return; 3180 } 3181 if (value < min || value > max) { 3182 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", 3183 name ? name : "null", value, min, max); 3184 return; 3185 } 3186 3187 env->cpuid_version &= ~0xff00f00; 3188 if (value > 0x0f) { 3189 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20); 3190 } else { 3191 env->cpuid_version |= value << 8; 3192 } 3193 } 3194 3195 static void x86_cpuid_version_get_model(Object *obj, Visitor *v, 3196 const char *name, void *opaque, 3197 Error **errp) 3198 { 3199 X86CPU *cpu = X86_CPU(obj); 3200 CPUX86State *env = &cpu->env; 3201 int64_t value; 3202 3203 value = (env->cpuid_version >> 4) & 0xf; 3204 value |= ((env->cpuid_version >> 16) & 0xf) << 4; 3205 visit_type_int(v, name, &value, errp); 3206 } 3207 3208 static void x86_cpuid_version_set_model(Object *obj, Visitor *v, 3209 const char *name, void *opaque, 3210 Error **errp) 3211 { 3212 X86CPU *cpu = X86_CPU(obj); 3213 CPUX86State *env = &cpu->env; 3214 const int64_t min = 0; 3215 const int64_t max = 0xff; 3216 Error *local_err = NULL; 3217 int64_t value; 3218 3219 visit_type_int(v, name, &value, &local_err); 3220 if (local_err) { 3221 error_propagate(errp, local_err); 3222 return; 3223 } 3224 if (value < min || value > max) { 3225 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", 3226 name ? name : "null", value, min, max); 3227 return; 3228 } 3229 3230 env->cpuid_version &= ~0xf00f0; 3231 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16); 3232 } 3233 3234 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v, 3235 const char *name, void *opaque, 3236 Error **errp) 3237 { 3238 X86CPU *cpu = X86_CPU(obj); 3239 CPUX86State *env = &cpu->env; 3240 int64_t value; 3241 3242 value = env->cpuid_version & 0xf; 3243 visit_type_int(v, name, &value, errp); 3244 } 3245 3246 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v, 3247 const char *name, void *opaque, 3248 Error **errp) 3249 { 3250 X86CPU *cpu = X86_CPU(obj); 3251 CPUX86State *env = &cpu->env; 3252 const int64_t min = 0; 3253 const int64_t max = 0xf; 3254 Error *local_err = NULL; 3255 int64_t value; 3256 3257 visit_type_int(v, name, &value, &local_err); 3258 if (local_err) { 3259 error_propagate(errp, local_err); 3260 return; 3261 } 3262 if (value < min || value > max) { 3263 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", 3264 name ? name : "null", value, min, max); 3265 return; 3266 } 3267 3268 env->cpuid_version &= ~0xf; 3269 env->cpuid_version |= value & 0xf; 3270 } 3271 3272 static char *x86_cpuid_get_vendor(Object *obj, Error **errp) 3273 { 3274 X86CPU *cpu = X86_CPU(obj); 3275 CPUX86State *env = &cpu->env; 3276 char *value; 3277 3278 value = g_malloc(CPUID_VENDOR_SZ + 1); 3279 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2, 3280 env->cpuid_vendor3); 3281 return value; 3282 } 3283 3284 static void x86_cpuid_set_vendor(Object *obj, const char *value, 3285 Error **errp) 3286 { 3287 X86CPU *cpu = X86_CPU(obj); 3288 CPUX86State *env = &cpu->env; 3289 int i; 3290 3291 if (strlen(value) != CPUID_VENDOR_SZ) { 3292 error_setg(errp, QERR_PROPERTY_VALUE_BAD, "", "vendor", value); 3293 return; 3294 } 3295 3296 env->cpuid_vendor1 = 0; 3297 env->cpuid_vendor2 = 0; 3298 env->cpuid_vendor3 = 0; 3299 for (i = 0; i < 4; i++) { 3300 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i); 3301 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i); 3302 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i); 3303 } 3304 } 3305 3306 static char *x86_cpuid_get_model_id(Object *obj, Error **errp) 3307 { 3308 X86CPU *cpu = X86_CPU(obj); 3309 CPUX86State *env = &cpu->env; 3310 char *value; 3311 int i; 3312 3313 value = g_malloc(48 + 1); 3314 for (i = 0; i < 48; i++) { 3315 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3)); 3316 } 3317 value[48] = '\0'; 3318 return value; 3319 } 3320 3321 static void x86_cpuid_set_model_id(Object *obj, const char *model_id, 3322 Error **errp) 3323 { 3324 X86CPU *cpu = X86_CPU(obj); 3325 CPUX86State *env = &cpu->env; 3326 int c, len, i; 3327 3328 if (model_id == NULL) { 3329 model_id = ""; 3330 } 3331 len = strlen(model_id); 3332 memset(env->cpuid_model, 0, 48); 3333 for (i = 0; i < 48; i++) { 3334 if (i >= len) { 3335 c = '\0'; 3336 } else { 3337 c = (uint8_t)model_id[i]; 3338 } 3339 env->cpuid_model[i >> 2] |= c << (8 * (i & 3)); 3340 } 3341 } 3342 3343 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name, 3344 void *opaque, Error **errp) 3345 { 3346 X86CPU *cpu = X86_CPU(obj); 3347 int64_t value; 3348 3349 value = cpu->env.tsc_khz * 1000; 3350 visit_type_int(v, name, &value, errp); 3351 } 3352 3353 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name, 3354 void *opaque, Error **errp) 3355 { 3356 X86CPU *cpu = X86_CPU(obj); 3357 const int64_t min = 0; 3358 const int64_t max = INT64_MAX; 3359 Error *local_err = NULL; 3360 int64_t value; 3361 3362 visit_type_int(v, name, &value, &local_err); 3363 if (local_err) { 3364 error_propagate(errp, local_err); 3365 return; 3366 } 3367 if (value < min || value > max) { 3368 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", 3369 name ? name : "null", value, min, max); 3370 return; 3371 } 3372 3373 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000; 3374 } 3375 3376 /* Generic getter for "feature-words" and "filtered-features" properties */ 3377 static void x86_cpu_get_feature_words(Object *obj, Visitor *v, 3378 const char *name, void *opaque, 3379 Error **errp) 3380 { 3381 uint64_t *array = (uint64_t *)opaque; 3382 FeatureWord w; 3383 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { }; 3384 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { }; 3385 X86CPUFeatureWordInfoList *list = NULL; 3386 3387 for (w = 0; w < FEATURE_WORDS; w++) { 3388 FeatureWordInfo *wi = &feature_word_info[w]; 3389 /* 3390 * We didn't have MSR features when "feature-words" was 3391 * introduced. Therefore skipped other type entries. 3392 */ 3393 if (wi->type != CPUID_FEATURE_WORD) { 3394 continue; 3395 } 3396 X86CPUFeatureWordInfo *qwi = &word_infos[w]; 3397 qwi->cpuid_input_eax = wi->cpuid.eax; 3398 qwi->has_cpuid_input_ecx = wi->cpuid.needs_ecx; 3399 qwi->cpuid_input_ecx = wi->cpuid.ecx; 3400 qwi->cpuid_register = x86_reg_info_32[wi->cpuid.reg].qapi_enum; 3401 qwi->features = array[w]; 3402 3403 /* List will be in reverse order, but order shouldn't matter */ 3404 list_entries[w].next = list; 3405 list_entries[w].value = &word_infos[w]; 3406 list = &list_entries[w]; 3407 } 3408 3409 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp); 3410 } 3411 3412 /* Convert all '_' in a feature string option name to '-', to make feature 3413 * name conform to QOM property naming rule, which uses '-' instead of '_'. 3414 */ 3415 static inline void feat2prop(char *s) 3416 { 3417 while ((s = strchr(s, '_'))) { 3418 *s = '-'; 3419 } 3420 } 3421 3422 /* Return the feature property name for a feature flag bit */ 3423 static const char *x86_cpu_feature_name(FeatureWord w, int bitnr) 3424 { 3425 const char *name; 3426 /* XSAVE components are automatically enabled by other features, 3427 * so return the original feature name instead 3428 */ 3429 if (w == FEAT_XSAVE_COMP_LO || w == FEAT_XSAVE_COMP_HI) { 3430 int comp = (w == FEAT_XSAVE_COMP_HI) ? bitnr + 32 : bitnr; 3431 3432 if (comp < ARRAY_SIZE(x86_ext_save_areas) && 3433 x86_ext_save_areas[comp].bits) { 3434 w = x86_ext_save_areas[comp].feature; 3435 bitnr = ctz32(x86_ext_save_areas[comp].bits); 3436 } 3437 } 3438 3439 assert(bitnr < 64); 3440 assert(w < FEATURE_WORDS); 3441 name = feature_word_info[w].feat_names[bitnr]; 3442 assert(bitnr < 32 || !(name && feature_word_info[w].type == CPUID_FEATURE_WORD)); 3443 return name; 3444 } 3445 3446 /* Compatibily hack to maintain legacy +-feat semantic, 3447 * where +-feat overwrites any feature set by 3448 * feat=on|feat even if the later is parsed after +-feat 3449 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled) 3450 */ 3451 static GList *plus_features, *minus_features; 3452 3453 static gint compare_string(gconstpointer a, gconstpointer b) 3454 { 3455 return g_strcmp0(a, b); 3456 } 3457 3458 /* Parse "+feature,-feature,feature=foo" CPU feature string 3459 */ 3460 static void x86_cpu_parse_featurestr(const char *typename, char *features, 3461 Error **errp) 3462 { 3463 char *featurestr; /* Single 'key=value" string being parsed */ 3464 static bool cpu_globals_initialized; 3465 bool ambiguous = false; 3466 3467 if (cpu_globals_initialized) { 3468 return; 3469 } 3470 cpu_globals_initialized = true; 3471 3472 if (!features) { 3473 return; 3474 } 3475 3476 for (featurestr = strtok(features, ","); 3477 featurestr; 3478 featurestr = strtok(NULL, ",")) { 3479 const char *name; 3480 const char *val = NULL; 3481 char *eq = NULL; 3482 char num[32]; 3483 GlobalProperty *prop; 3484 3485 /* Compatibility syntax: */ 3486 if (featurestr[0] == '+') { 3487 plus_features = g_list_append(plus_features, 3488 g_strdup(featurestr + 1)); 3489 continue; 3490 } else if (featurestr[0] == '-') { 3491 minus_features = g_list_append(minus_features, 3492 g_strdup(featurestr + 1)); 3493 continue; 3494 } 3495 3496 eq = strchr(featurestr, '='); 3497 if (eq) { 3498 *eq++ = 0; 3499 val = eq; 3500 } else { 3501 val = "on"; 3502 } 3503 3504 feat2prop(featurestr); 3505 name = featurestr; 3506 3507 if (g_list_find_custom(plus_features, name, compare_string)) { 3508 warn_report("Ambiguous CPU model string. " 3509 "Don't mix both \"+%s\" and \"%s=%s\"", 3510 name, name, val); 3511 ambiguous = true; 3512 } 3513 if (g_list_find_custom(minus_features, name, compare_string)) { 3514 warn_report("Ambiguous CPU model string. " 3515 "Don't mix both \"-%s\" and \"%s=%s\"", 3516 name, name, val); 3517 ambiguous = true; 3518 } 3519 3520 /* Special case: */ 3521 if (!strcmp(name, "tsc-freq")) { 3522 int ret; 3523 uint64_t tsc_freq; 3524 3525 ret = qemu_strtosz_metric(val, NULL, &tsc_freq); 3526 if (ret < 0 || tsc_freq > INT64_MAX) { 3527 error_setg(errp, "bad numerical value %s", val); 3528 return; 3529 } 3530 snprintf(num, sizeof(num), "%" PRId64, tsc_freq); 3531 val = num; 3532 name = "tsc-frequency"; 3533 } 3534 3535 prop = g_new0(typeof(*prop), 1); 3536 prop->driver = typename; 3537 prop->property = g_strdup(name); 3538 prop->value = g_strdup(val); 3539 qdev_prop_register_global(prop); 3540 } 3541 3542 if (ambiguous) { 3543 warn_report("Compatibility of ambiguous CPU model " 3544 "strings won't be kept on future QEMU versions"); 3545 } 3546 } 3547 3548 static void x86_cpu_expand_features(X86CPU *cpu, Error **errp); 3549 static void x86_cpu_filter_features(X86CPU *cpu, bool verbose); 3550 3551 /* Build a list with the name of all features on a feature word array */ 3552 static void x86_cpu_list_feature_names(FeatureWordArray features, 3553 strList **feat_names) 3554 { 3555 FeatureWord w; 3556 strList **next = feat_names; 3557 3558 for (w = 0; w < FEATURE_WORDS; w++) { 3559 uint64_t filtered = features[w]; 3560 int i; 3561 for (i = 0; i < 64; i++) { 3562 if (filtered & (1ULL << i)) { 3563 strList *new = g_new0(strList, 1); 3564 new->value = g_strdup(x86_cpu_feature_name(w, i)); 3565 *next = new; 3566 next = &new->next; 3567 } 3568 } 3569 } 3570 } 3571 3572 static void x86_cpu_get_unavailable_features(Object *obj, Visitor *v, 3573 const char *name, void *opaque, 3574 Error **errp) 3575 { 3576 X86CPU *xc = X86_CPU(obj); 3577 strList *result = NULL; 3578 3579 x86_cpu_list_feature_names(xc->filtered_features, &result); 3580 visit_type_strList(v, "unavailable-features", &result, errp); 3581 } 3582 3583 /* Check for missing features that may prevent the CPU class from 3584 * running using the current machine and accelerator. 3585 */ 3586 static void x86_cpu_class_check_missing_features(X86CPUClass *xcc, 3587 strList **missing_feats) 3588 { 3589 X86CPU *xc; 3590 Error *err = NULL; 3591 strList **next = missing_feats; 3592 3593 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) { 3594 strList *new = g_new0(strList, 1); 3595 new->value = g_strdup("kvm"); 3596 *missing_feats = new; 3597 return; 3598 } 3599 3600 xc = X86_CPU(object_new(object_class_get_name(OBJECT_CLASS(xcc)))); 3601 3602 x86_cpu_expand_features(xc, &err); 3603 if (err) { 3604 /* Errors at x86_cpu_expand_features should never happen, 3605 * but in case it does, just report the model as not 3606 * runnable at all using the "type" property. 3607 */ 3608 strList *new = g_new0(strList, 1); 3609 new->value = g_strdup("type"); 3610 *next = new; 3611 next = &new->next; 3612 } 3613 3614 x86_cpu_filter_features(xc, false); 3615 3616 x86_cpu_list_feature_names(xc->filtered_features, next); 3617 3618 object_unref(OBJECT(xc)); 3619 } 3620 3621 /* Print all cpuid feature names in featureset 3622 */ 3623 static void listflags(GList *features) 3624 { 3625 size_t len = 0; 3626 GList *tmp; 3627 3628 for (tmp = features; tmp; tmp = tmp->next) { 3629 const char *name = tmp->data; 3630 if ((len + strlen(name) + 1) >= 75) { 3631 qemu_printf("\n"); 3632 len = 0; 3633 } 3634 qemu_printf("%s%s", len == 0 ? " " : " ", name); 3635 len += strlen(name) + 1; 3636 } 3637 qemu_printf("\n"); 3638 } 3639 3640 /* Sort alphabetically by type name, respecting X86CPUClass::ordering. */ 3641 static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b) 3642 { 3643 ObjectClass *class_a = (ObjectClass *)a; 3644 ObjectClass *class_b = (ObjectClass *)b; 3645 X86CPUClass *cc_a = X86_CPU_CLASS(class_a); 3646 X86CPUClass *cc_b = X86_CPU_CLASS(class_b); 3647 char *name_a, *name_b; 3648 int ret; 3649 3650 if (cc_a->ordering != cc_b->ordering) { 3651 ret = cc_a->ordering - cc_b->ordering; 3652 } else { 3653 name_a = x86_cpu_class_get_model_name(cc_a); 3654 name_b = x86_cpu_class_get_model_name(cc_b); 3655 ret = strcmp(name_a, name_b); 3656 g_free(name_a); 3657 g_free(name_b); 3658 } 3659 return ret; 3660 } 3661 3662 static GSList *get_sorted_cpu_model_list(void) 3663 { 3664 GSList *list = object_class_get_list(TYPE_X86_CPU, false); 3665 list = g_slist_sort(list, x86_cpu_list_compare); 3666 return list; 3667 } 3668 3669 static char *x86_cpu_class_get_model_id(X86CPUClass *xc) 3670 { 3671 Object *obj = object_new(object_class_get_name(OBJECT_CLASS(xc))); 3672 char *r = object_property_get_str(obj, "model-id", &error_abort); 3673 object_unref(obj); 3674 return r; 3675 } 3676 3677 static char *x86_cpu_class_get_alias_of(X86CPUClass *cc) 3678 { 3679 X86CPUVersion version; 3680 3681 if (!cc->model || !cc->model->is_alias) { 3682 return NULL; 3683 } 3684 version = x86_cpu_model_resolve_version(cc->model); 3685 if (version <= 0) { 3686 return NULL; 3687 } 3688 return x86_cpu_versioned_model_name(cc->model->cpudef, version); 3689 } 3690 3691 static void x86_cpu_list_entry(gpointer data, gpointer user_data) 3692 { 3693 ObjectClass *oc = data; 3694 X86CPUClass *cc = X86_CPU_CLASS(oc); 3695 char *name = x86_cpu_class_get_model_name(cc); 3696 char *desc = g_strdup(cc->model_description); 3697 char *alias_of = x86_cpu_class_get_alias_of(cc); 3698 3699 if (!desc && alias_of) { 3700 if (cc->model && cc->model->version == CPU_VERSION_AUTO) { 3701 desc = g_strdup("(alias configured by machine type)"); 3702 } else { 3703 desc = g_strdup_printf("(alias of %s)", alias_of); 3704 } 3705 } 3706 if (!desc) { 3707 desc = x86_cpu_class_get_model_id(cc); 3708 } 3709 3710 qemu_printf("x86 %-20s %-48s\n", name, desc); 3711 g_free(name); 3712 g_free(desc); 3713 g_free(alias_of); 3714 } 3715 3716 /* list available CPU models and flags */ 3717 void x86_cpu_list(void) 3718 { 3719 int i, j; 3720 GSList *list; 3721 GList *names = NULL; 3722 3723 qemu_printf("Available CPUs:\n"); 3724 list = get_sorted_cpu_model_list(); 3725 g_slist_foreach(list, x86_cpu_list_entry, NULL); 3726 g_slist_free(list); 3727 3728 names = NULL; 3729 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) { 3730 FeatureWordInfo *fw = &feature_word_info[i]; 3731 for (j = 0; j < 64; j++) { 3732 if (fw->feat_names[j]) { 3733 names = g_list_append(names, (gpointer)fw->feat_names[j]); 3734 } 3735 } 3736 } 3737 3738 names = g_list_sort(names, (GCompareFunc)strcmp); 3739 3740 qemu_printf("\nRecognized CPUID flags:\n"); 3741 listflags(names); 3742 qemu_printf("\n"); 3743 g_list_free(names); 3744 } 3745 3746 static void x86_cpu_definition_entry(gpointer data, gpointer user_data) 3747 { 3748 ObjectClass *oc = data; 3749 X86CPUClass *cc = X86_CPU_CLASS(oc); 3750 CpuDefinitionInfoList **cpu_list = user_data; 3751 CpuDefinitionInfoList *entry; 3752 CpuDefinitionInfo *info; 3753 3754 info = g_malloc0(sizeof(*info)); 3755 info->name = x86_cpu_class_get_model_name(cc); 3756 x86_cpu_class_check_missing_features(cc, &info->unavailable_features); 3757 info->has_unavailable_features = true; 3758 info->q_typename = g_strdup(object_class_get_name(oc)); 3759 info->migration_safe = cc->migration_safe; 3760 info->has_migration_safe = true; 3761 info->q_static = cc->static_model; 3762 /* 3763 * Old machine types won't report aliases, so that alias translation 3764 * doesn't break compatibility with previous QEMU versions. 3765 */ 3766 if (default_cpu_version != CPU_VERSION_LEGACY) { 3767 info->alias_of = x86_cpu_class_get_alias_of(cc); 3768 info->has_alias_of = !!info->alias_of; 3769 } 3770 3771 entry = g_malloc0(sizeof(*entry)); 3772 entry->value = info; 3773 entry->next = *cpu_list; 3774 *cpu_list = entry; 3775 } 3776 3777 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) 3778 { 3779 CpuDefinitionInfoList *cpu_list = NULL; 3780 GSList *list = get_sorted_cpu_model_list(); 3781 g_slist_foreach(list, x86_cpu_definition_entry, &cpu_list); 3782 g_slist_free(list); 3783 return cpu_list; 3784 } 3785 3786 static uint64_t x86_cpu_get_supported_feature_word(FeatureWord w, 3787 bool migratable_only) 3788 { 3789 FeatureWordInfo *wi = &feature_word_info[w]; 3790 uint64_t r = 0; 3791 3792 if (kvm_enabled()) { 3793 switch (wi->type) { 3794 case CPUID_FEATURE_WORD: 3795 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid.eax, 3796 wi->cpuid.ecx, 3797 wi->cpuid.reg); 3798 break; 3799 case MSR_FEATURE_WORD: 3800 r = kvm_arch_get_supported_msr_feature(kvm_state, 3801 wi->msr.index); 3802 break; 3803 } 3804 } else if (hvf_enabled()) { 3805 if (wi->type != CPUID_FEATURE_WORD) { 3806 return 0; 3807 } 3808 r = hvf_get_supported_cpuid(wi->cpuid.eax, 3809 wi->cpuid.ecx, 3810 wi->cpuid.reg); 3811 } else if (tcg_enabled()) { 3812 r = wi->tcg_features; 3813 } else { 3814 return ~0; 3815 } 3816 if (migratable_only) { 3817 r &= x86_cpu_get_migratable_flags(w); 3818 } 3819 return r; 3820 } 3821 3822 static void x86_cpu_apply_props(X86CPU *cpu, PropValue *props) 3823 { 3824 PropValue *pv; 3825 for (pv = props; pv->prop; pv++) { 3826 if (!pv->value) { 3827 continue; 3828 } 3829 object_property_parse(OBJECT(cpu), pv->value, pv->prop, 3830 &error_abort); 3831 } 3832 } 3833 3834 /* Apply properties for the CPU model version specified in model */ 3835 static void x86_cpu_apply_version_props(X86CPU *cpu, X86CPUModel *model) 3836 { 3837 const X86CPUVersionDefinition *vdef; 3838 X86CPUVersion version = x86_cpu_model_resolve_version(model); 3839 3840 if (version == CPU_VERSION_LEGACY) { 3841 return; 3842 } 3843 3844 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) { 3845 PropValue *p; 3846 3847 for (p = vdef->props; p && p->prop; p++) { 3848 object_property_parse(OBJECT(cpu), p->value, p->prop, 3849 &error_abort); 3850 } 3851 3852 if (vdef->version == version) { 3853 break; 3854 } 3855 } 3856 3857 /* 3858 * If we reached the end of the list, version number was invalid 3859 */ 3860 assert(vdef->version == version); 3861 } 3862 3863 /* Load data from X86CPUDefinition into a X86CPU object 3864 */ 3865 static void x86_cpu_load_model(X86CPU *cpu, X86CPUModel *model, Error **errp) 3866 { 3867 X86CPUDefinition *def = model->cpudef; 3868 CPUX86State *env = &cpu->env; 3869 const char *vendor; 3870 char host_vendor[CPUID_VENDOR_SZ + 1]; 3871 FeatureWord w; 3872 3873 /*NOTE: any property set by this function should be returned by 3874 * x86_cpu_static_props(), so static expansion of 3875 * query-cpu-model-expansion is always complete. 3876 */ 3877 3878 /* CPU models only set _minimum_ values for level/xlevel: */ 3879 object_property_set_uint(OBJECT(cpu), def->level, "min-level", errp); 3880 object_property_set_uint(OBJECT(cpu), def->xlevel, "min-xlevel", errp); 3881 3882 object_property_set_int(OBJECT(cpu), def->family, "family", errp); 3883 object_property_set_int(OBJECT(cpu), def->model, "model", errp); 3884 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp); 3885 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp); 3886 for (w = 0; w < FEATURE_WORDS; w++) { 3887 env->features[w] = def->features[w]; 3888 } 3889 3890 /* legacy-cache defaults to 'off' if CPU model provides cache info */ 3891 cpu->legacy_cache = !def->cache_info; 3892 3893 /* Special cases not set in the X86CPUDefinition structs: */ 3894 /* TODO: in-kernel irqchip for hvf */ 3895 if (kvm_enabled()) { 3896 if (!kvm_irqchip_in_kernel()) { 3897 x86_cpu_change_kvm_default("x2apic", "off"); 3898 } 3899 3900 x86_cpu_apply_props(cpu, kvm_default_props); 3901 } else if (tcg_enabled()) { 3902 x86_cpu_apply_props(cpu, tcg_default_props); 3903 } 3904 3905 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR; 3906 3907 /* sysenter isn't supported in compatibility mode on AMD, 3908 * syscall isn't supported in compatibility mode on Intel. 3909 * Normally we advertise the actual CPU vendor, but you can 3910 * override this using the 'vendor' property if you want to use 3911 * KVM's sysenter/syscall emulation in compatibility mode and 3912 * when doing cross vendor migration 3913 */ 3914 vendor = def->vendor; 3915 if (accel_uses_host_cpuid()) { 3916 uint32_t ebx = 0, ecx = 0, edx = 0; 3917 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx); 3918 x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx); 3919 vendor = host_vendor; 3920 } 3921 3922 object_property_set_str(OBJECT(cpu), vendor, "vendor", errp); 3923 3924 x86_cpu_apply_version_props(cpu, model); 3925 } 3926 3927 #ifndef CONFIG_USER_ONLY 3928 /* Return a QDict containing keys for all properties that can be included 3929 * in static expansion of CPU models. All properties set by x86_cpu_load_model() 3930 * must be included in the dictionary. 3931 */ 3932 static QDict *x86_cpu_static_props(void) 3933 { 3934 FeatureWord w; 3935 int i; 3936 static const char *props[] = { 3937 "min-level", 3938 "min-xlevel", 3939 "family", 3940 "model", 3941 "stepping", 3942 "model-id", 3943 "vendor", 3944 "lmce", 3945 NULL, 3946 }; 3947 static QDict *d; 3948 3949 if (d) { 3950 return d; 3951 } 3952 3953 d = qdict_new(); 3954 for (i = 0; props[i]; i++) { 3955 qdict_put_null(d, props[i]); 3956 } 3957 3958 for (w = 0; w < FEATURE_WORDS; w++) { 3959 FeatureWordInfo *fi = &feature_word_info[w]; 3960 int bit; 3961 for (bit = 0; bit < 64; bit++) { 3962 if (!fi->feat_names[bit]) { 3963 continue; 3964 } 3965 qdict_put_null(d, fi->feat_names[bit]); 3966 } 3967 } 3968 3969 return d; 3970 } 3971 3972 /* Add an entry to @props dict, with the value for property. */ 3973 static void x86_cpu_expand_prop(X86CPU *cpu, QDict *props, const char *prop) 3974 { 3975 QObject *value = object_property_get_qobject(OBJECT(cpu), prop, 3976 &error_abort); 3977 3978 qdict_put_obj(props, prop, value); 3979 } 3980 3981 /* Convert CPU model data from X86CPU object to a property dictionary 3982 * that can recreate exactly the same CPU model. 3983 */ 3984 static void x86_cpu_to_dict(X86CPU *cpu, QDict *props) 3985 { 3986 QDict *sprops = x86_cpu_static_props(); 3987 const QDictEntry *e; 3988 3989 for (e = qdict_first(sprops); e; e = qdict_next(sprops, e)) { 3990 const char *prop = qdict_entry_key(e); 3991 x86_cpu_expand_prop(cpu, props, prop); 3992 } 3993 } 3994 3995 /* Convert CPU model data from X86CPU object to a property dictionary 3996 * that can recreate exactly the same CPU model, including every 3997 * writeable QOM property. 3998 */ 3999 static void x86_cpu_to_dict_full(X86CPU *cpu, QDict *props) 4000 { 4001 ObjectPropertyIterator iter; 4002 ObjectProperty *prop; 4003 4004 object_property_iter_init(&iter, OBJECT(cpu)); 4005 while ((prop = object_property_iter_next(&iter))) { 4006 /* skip read-only or write-only properties */ 4007 if (!prop->get || !prop->set) { 4008 continue; 4009 } 4010 4011 /* "hotplugged" is the only property that is configurable 4012 * on the command-line but will be set differently on CPUs 4013 * created using "-cpu ... -smp ..." and by CPUs created 4014 * on the fly by x86_cpu_from_model() for querying. Skip it. 4015 */ 4016 if (!strcmp(prop->name, "hotplugged")) { 4017 continue; 4018 } 4019 x86_cpu_expand_prop(cpu, props, prop->name); 4020 } 4021 } 4022 4023 static void object_apply_props(Object *obj, QDict *props, Error **errp) 4024 { 4025 const QDictEntry *prop; 4026 Error *err = NULL; 4027 4028 for (prop = qdict_first(props); prop; prop = qdict_next(props, prop)) { 4029 object_property_set_qobject(obj, qdict_entry_value(prop), 4030 qdict_entry_key(prop), &err); 4031 if (err) { 4032 break; 4033 } 4034 } 4035 4036 error_propagate(errp, err); 4037 } 4038 4039 /* Create X86CPU object according to model+props specification */ 4040 static X86CPU *x86_cpu_from_model(const char *model, QDict *props, Error **errp) 4041 { 4042 X86CPU *xc = NULL; 4043 X86CPUClass *xcc; 4044 Error *err = NULL; 4045 4046 xcc = X86_CPU_CLASS(cpu_class_by_name(TYPE_X86_CPU, model)); 4047 if (xcc == NULL) { 4048 error_setg(&err, "CPU model '%s' not found", model); 4049 goto out; 4050 } 4051 4052 xc = X86_CPU(object_new(object_class_get_name(OBJECT_CLASS(xcc)))); 4053 if (props) { 4054 object_apply_props(OBJECT(xc), props, &err); 4055 if (err) { 4056 goto out; 4057 } 4058 } 4059 4060 x86_cpu_expand_features(xc, &err); 4061 if (err) { 4062 goto out; 4063 } 4064 4065 out: 4066 if (err) { 4067 error_propagate(errp, err); 4068 object_unref(OBJECT(xc)); 4069 xc = NULL; 4070 } 4071 return xc; 4072 } 4073 4074 CpuModelExpansionInfo * 4075 qmp_query_cpu_model_expansion(CpuModelExpansionType type, 4076 CpuModelInfo *model, 4077 Error **errp) 4078 { 4079 X86CPU *xc = NULL; 4080 Error *err = NULL; 4081 CpuModelExpansionInfo *ret = g_new0(CpuModelExpansionInfo, 1); 4082 QDict *props = NULL; 4083 const char *base_name; 4084 4085 xc = x86_cpu_from_model(model->name, 4086 model->has_props ? 4087 qobject_to(QDict, model->props) : 4088 NULL, &err); 4089 if (err) { 4090 goto out; 4091 } 4092 4093 props = qdict_new(); 4094 ret->model = g_new0(CpuModelInfo, 1); 4095 ret->model->props = QOBJECT(props); 4096 ret->model->has_props = true; 4097 4098 switch (type) { 4099 case CPU_MODEL_EXPANSION_TYPE_STATIC: 4100 /* Static expansion will be based on "base" only */ 4101 base_name = "base"; 4102 x86_cpu_to_dict(xc, props); 4103 break; 4104 case CPU_MODEL_EXPANSION_TYPE_FULL: 4105 /* As we don't return every single property, full expansion needs 4106 * to keep the original model name+props, and add extra 4107 * properties on top of that. 4108 */ 4109 base_name = model->name; 4110 x86_cpu_to_dict_full(xc, props); 4111 break; 4112 default: 4113 error_setg(&err, "Unsupported expansion type"); 4114 goto out; 4115 } 4116 4117 x86_cpu_to_dict(xc, props); 4118 4119 ret->model->name = g_strdup(base_name); 4120 4121 out: 4122 object_unref(OBJECT(xc)); 4123 if (err) { 4124 error_propagate(errp, err); 4125 qapi_free_CpuModelExpansionInfo(ret); 4126 ret = NULL; 4127 } 4128 return ret; 4129 } 4130 #endif /* !CONFIG_USER_ONLY */ 4131 4132 static gchar *x86_gdb_arch_name(CPUState *cs) 4133 { 4134 #ifdef TARGET_X86_64 4135 return g_strdup("i386:x86-64"); 4136 #else 4137 return g_strdup("i386"); 4138 #endif 4139 } 4140 4141 static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data) 4142 { 4143 X86CPUModel *model = data; 4144 X86CPUClass *xcc = X86_CPU_CLASS(oc); 4145 4146 xcc->model = model; 4147 xcc->migration_safe = true; 4148 } 4149 4150 static void x86_register_cpu_model_type(const char *name, X86CPUModel *model) 4151 { 4152 char *typename = x86_cpu_type_name(name); 4153 TypeInfo ti = { 4154 .name = typename, 4155 .parent = TYPE_X86_CPU, 4156 .class_init = x86_cpu_cpudef_class_init, 4157 .class_data = model, 4158 }; 4159 4160 type_register(&ti); 4161 g_free(typename); 4162 } 4163 4164 static void x86_register_cpudef_types(X86CPUDefinition *def) 4165 { 4166 X86CPUModel *m; 4167 const X86CPUVersionDefinition *vdef; 4168 char *name; 4169 4170 /* AMD aliases are handled at runtime based on CPUID vendor, so 4171 * they shouldn't be set on the CPU model table. 4172 */ 4173 assert(!(def->features[FEAT_8000_0001_EDX] & CPUID_EXT2_AMD_ALIASES)); 4174 /* catch mistakes instead of silently truncating model_id when too long */ 4175 assert(def->model_id && strlen(def->model_id) <= 48); 4176 4177 /* Unversioned model: */ 4178 m = g_new0(X86CPUModel, 1); 4179 m->cpudef = def; 4180 m->version = CPU_VERSION_AUTO; 4181 m->is_alias = true; 4182 x86_register_cpu_model_type(def->name, m); 4183 4184 /* Versioned models: */ 4185 4186 for (vdef = x86_cpu_def_get_versions(def); vdef->version; vdef++) { 4187 X86CPUModel *m = g_new0(X86CPUModel, 1); 4188 m->cpudef = def; 4189 m->version = vdef->version; 4190 name = x86_cpu_versioned_model_name(def, vdef->version); 4191 x86_register_cpu_model_type(name, m); 4192 g_free(name); 4193 4194 if (vdef->alias) { 4195 X86CPUModel *am = g_new0(X86CPUModel, 1); 4196 am->cpudef = def; 4197 am->version = vdef->version; 4198 am->is_alias = true; 4199 x86_register_cpu_model_type(vdef->alias, am); 4200 } 4201 } 4202 4203 } 4204 4205 #if !defined(CONFIG_USER_ONLY) 4206 4207 void cpu_clear_apic_feature(CPUX86State *env) 4208 { 4209 env->features[FEAT_1_EDX] &= ~CPUID_APIC; 4210 } 4211 4212 #endif /* !CONFIG_USER_ONLY */ 4213 4214 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, 4215 uint32_t *eax, uint32_t *ebx, 4216 uint32_t *ecx, uint32_t *edx) 4217 { 4218 X86CPU *cpu = env_archcpu(env); 4219 CPUState *cs = env_cpu(env); 4220 uint32_t die_offset; 4221 uint32_t limit; 4222 uint32_t signature[3]; 4223 4224 /* Calculate & apply limits for different index ranges */ 4225 if (index >= 0xC0000000) { 4226 limit = env->cpuid_xlevel2; 4227 } else if (index >= 0x80000000) { 4228 limit = env->cpuid_xlevel; 4229 } else if (index >= 0x40000000) { 4230 limit = 0x40000001; 4231 } else { 4232 limit = env->cpuid_level; 4233 } 4234 4235 if (index > limit) { 4236 /* Intel documentation states that invalid EAX input will 4237 * return the same information as EAX=cpuid_level 4238 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID) 4239 */ 4240 index = env->cpuid_level; 4241 } 4242 4243 switch(index) { 4244 case 0: 4245 *eax = env->cpuid_level; 4246 *ebx = env->cpuid_vendor1; 4247 *edx = env->cpuid_vendor2; 4248 *ecx = env->cpuid_vendor3; 4249 break; 4250 case 1: 4251 *eax = env->cpuid_version; 4252 *ebx = (cpu->apic_id << 24) | 4253 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */ 4254 *ecx = env->features[FEAT_1_ECX]; 4255 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) { 4256 *ecx |= CPUID_EXT_OSXSAVE; 4257 } 4258 *edx = env->features[FEAT_1_EDX]; 4259 if (cs->nr_cores * cs->nr_threads > 1) { 4260 *ebx |= (cs->nr_cores * cs->nr_threads) << 16; 4261 *edx |= CPUID_HT; 4262 } 4263 break; 4264 case 2: 4265 /* cache info: needed for Pentium Pro compatibility */ 4266 if (cpu->cache_info_passthrough) { 4267 host_cpuid(index, 0, eax, ebx, ecx, edx); 4268 break; 4269 } 4270 *eax = 1; /* Number of CPUID[EAX=2] calls required */ 4271 *ebx = 0; 4272 if (!cpu->enable_l3_cache) { 4273 *ecx = 0; 4274 } else { 4275 *ecx = cpuid2_cache_descriptor(env->cache_info_cpuid2.l3_cache); 4276 } 4277 *edx = (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1d_cache) << 16) | 4278 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1i_cache) << 8) | 4279 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l2_cache)); 4280 break; 4281 case 4: 4282 /* cache info: needed for Core compatibility */ 4283 if (cpu->cache_info_passthrough) { 4284 host_cpuid(index, count, eax, ebx, ecx, edx); 4285 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */ 4286 *eax &= ~0xFC000000; 4287 if ((*eax & 31) && cs->nr_cores > 1) { 4288 *eax |= (cs->nr_cores - 1) << 26; 4289 } 4290 } else { 4291 *eax = 0; 4292 switch (count) { 4293 case 0: /* L1 dcache info */ 4294 encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache, 4295 1, cs->nr_cores, 4296 eax, ebx, ecx, edx); 4297 break; 4298 case 1: /* L1 icache info */ 4299 encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache, 4300 1, cs->nr_cores, 4301 eax, ebx, ecx, edx); 4302 break; 4303 case 2: /* L2 cache info */ 4304 encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache, 4305 cs->nr_threads, cs->nr_cores, 4306 eax, ebx, ecx, edx); 4307 break; 4308 case 3: /* L3 cache info */ 4309 die_offset = apicid_die_offset(env->nr_dies, 4310 cs->nr_cores, cs->nr_threads); 4311 if (cpu->enable_l3_cache) { 4312 encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache, 4313 (1 << die_offset), cs->nr_cores, 4314 eax, ebx, ecx, edx); 4315 break; 4316 } 4317 /* fall through */ 4318 default: /* end of info */ 4319 *eax = *ebx = *ecx = *edx = 0; 4320 break; 4321 } 4322 } 4323 break; 4324 case 5: 4325 /* MONITOR/MWAIT Leaf */ 4326 *eax = cpu->mwait.eax; /* Smallest monitor-line size in bytes */ 4327 *ebx = cpu->mwait.ebx; /* Largest monitor-line size in bytes */ 4328 *ecx = cpu->mwait.ecx; /* flags */ 4329 *edx = cpu->mwait.edx; /* mwait substates */ 4330 break; 4331 case 6: 4332 /* Thermal and Power Leaf */ 4333 *eax = env->features[FEAT_6_EAX]; 4334 *ebx = 0; 4335 *ecx = 0; 4336 *edx = 0; 4337 break; 4338 case 7: 4339 /* Structured Extended Feature Flags Enumeration Leaf */ 4340 if (count == 0) { 4341 /* Maximum ECX value for sub-leaves */ 4342 *eax = env->cpuid_level_func7; 4343 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */ 4344 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */ 4345 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) { 4346 *ecx |= CPUID_7_0_ECX_OSPKE; 4347 } 4348 *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */ 4349 } else if (count == 1) { 4350 *eax = env->features[FEAT_7_1_EAX]; 4351 *ebx = 0; 4352 *ecx = 0; 4353 *edx = 0; 4354 } else { 4355 *eax = 0; 4356 *ebx = 0; 4357 *ecx = 0; 4358 *edx = 0; 4359 } 4360 break; 4361 case 9: 4362 /* Direct Cache Access Information Leaf */ 4363 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */ 4364 *ebx = 0; 4365 *ecx = 0; 4366 *edx = 0; 4367 break; 4368 case 0xA: 4369 /* Architectural Performance Monitoring Leaf */ 4370 if (kvm_enabled() && cpu->enable_pmu) { 4371 KVMState *s = cs->kvm_state; 4372 4373 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX); 4374 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX); 4375 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX); 4376 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX); 4377 } else if (hvf_enabled() && cpu->enable_pmu) { 4378 *eax = hvf_get_supported_cpuid(0xA, count, R_EAX); 4379 *ebx = hvf_get_supported_cpuid(0xA, count, R_EBX); 4380 *ecx = hvf_get_supported_cpuid(0xA, count, R_ECX); 4381 *edx = hvf_get_supported_cpuid(0xA, count, R_EDX); 4382 } else { 4383 *eax = 0; 4384 *ebx = 0; 4385 *ecx = 0; 4386 *edx = 0; 4387 } 4388 break; 4389 case 0xB: 4390 /* Extended Topology Enumeration Leaf */ 4391 if (!cpu->enable_cpuid_0xb) { 4392 *eax = *ebx = *ecx = *edx = 0; 4393 break; 4394 } 4395 4396 *ecx = count & 0xff; 4397 *edx = cpu->apic_id; 4398 4399 switch (count) { 4400 case 0: 4401 *eax = apicid_core_offset(env->nr_dies, 4402 cs->nr_cores, cs->nr_threads); 4403 *ebx = cs->nr_threads; 4404 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT; 4405 break; 4406 case 1: 4407 *eax = apicid_pkg_offset(env->nr_dies, 4408 cs->nr_cores, cs->nr_threads); 4409 *ebx = cs->nr_cores * cs->nr_threads; 4410 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE; 4411 break; 4412 default: 4413 *eax = 0; 4414 *ebx = 0; 4415 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID; 4416 } 4417 4418 assert(!(*eax & ~0x1f)); 4419 *ebx &= 0xffff; /* The count doesn't need to be reliable. */ 4420 break; 4421 case 0x1F: 4422 /* V2 Extended Topology Enumeration Leaf */ 4423 if (env->nr_dies < 2) { 4424 *eax = *ebx = *ecx = *edx = 0; 4425 break; 4426 } 4427 4428 *ecx = count & 0xff; 4429 *edx = cpu->apic_id; 4430 switch (count) { 4431 case 0: 4432 *eax = apicid_core_offset(env->nr_dies, cs->nr_cores, 4433 cs->nr_threads); 4434 *ebx = cs->nr_threads; 4435 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT; 4436 break; 4437 case 1: 4438 *eax = apicid_die_offset(env->nr_dies, cs->nr_cores, 4439 cs->nr_threads); 4440 *ebx = cs->nr_cores * cs->nr_threads; 4441 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE; 4442 break; 4443 case 2: 4444 *eax = apicid_pkg_offset(env->nr_dies, cs->nr_cores, 4445 cs->nr_threads); 4446 *ebx = env->nr_dies * cs->nr_cores * cs->nr_threads; 4447 *ecx |= CPUID_TOPOLOGY_LEVEL_DIE; 4448 break; 4449 default: 4450 *eax = 0; 4451 *ebx = 0; 4452 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID; 4453 } 4454 assert(!(*eax & ~0x1f)); 4455 *ebx &= 0xffff; /* The count doesn't need to be reliable. */ 4456 break; 4457 case 0xD: { 4458 /* Processor Extended State */ 4459 *eax = 0; 4460 *ebx = 0; 4461 *ecx = 0; 4462 *edx = 0; 4463 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { 4464 break; 4465 } 4466 4467 if (count == 0) { 4468 *ecx = xsave_area_size(x86_cpu_xsave_components(cpu)); 4469 *eax = env->features[FEAT_XSAVE_COMP_LO]; 4470 *edx = env->features[FEAT_XSAVE_COMP_HI]; 4471 *ebx = xsave_area_size(env->xcr0); 4472 } else if (count == 1) { 4473 *eax = env->features[FEAT_XSAVE]; 4474 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) { 4475 if ((x86_cpu_xsave_components(cpu) >> count) & 1) { 4476 const ExtSaveArea *esa = &x86_ext_save_areas[count]; 4477 *eax = esa->size; 4478 *ebx = esa->offset; 4479 } 4480 } 4481 break; 4482 } 4483 case 0x14: { 4484 /* Intel Processor Trace Enumeration */ 4485 *eax = 0; 4486 *ebx = 0; 4487 *ecx = 0; 4488 *edx = 0; 4489 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) || 4490 !kvm_enabled()) { 4491 break; 4492 } 4493 4494 if (count == 0) { 4495 *eax = INTEL_PT_MAX_SUBLEAF; 4496 *ebx = INTEL_PT_MINIMAL_EBX; 4497 *ecx = INTEL_PT_MINIMAL_ECX; 4498 } else if (count == 1) { 4499 *eax = INTEL_PT_MTC_BITMAP | INTEL_PT_ADDR_RANGES_NUM; 4500 *ebx = INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP; 4501 } 4502 break; 4503 } 4504 case 0x40000000: 4505 /* 4506 * CPUID code in kvm_arch_init_vcpu() ignores stuff 4507 * set here, but we restrict to TCG none the less. 4508 */ 4509 if (tcg_enabled() && cpu->expose_tcg) { 4510 memcpy(signature, "TCGTCGTCGTCG", 12); 4511 *eax = 0x40000001; 4512 *ebx = signature[0]; 4513 *ecx = signature[1]; 4514 *edx = signature[2]; 4515 } else { 4516 *eax = 0; 4517 *ebx = 0; 4518 *ecx = 0; 4519 *edx = 0; 4520 } 4521 break; 4522 case 0x40000001: 4523 *eax = 0; 4524 *ebx = 0; 4525 *ecx = 0; 4526 *edx = 0; 4527 break; 4528 case 0x80000000: 4529 *eax = env->cpuid_xlevel; 4530 *ebx = env->cpuid_vendor1; 4531 *edx = env->cpuid_vendor2; 4532 *ecx = env->cpuid_vendor3; 4533 break; 4534 case 0x80000001: 4535 *eax = env->cpuid_version; 4536 *ebx = 0; 4537 *ecx = env->features[FEAT_8000_0001_ECX]; 4538 *edx = env->features[FEAT_8000_0001_EDX]; 4539 4540 /* The Linux kernel checks for the CMPLegacy bit and 4541 * discards multiple thread information if it is set. 4542 * So don't set it here for Intel to make Linux guests happy. 4543 */ 4544 if (cs->nr_cores * cs->nr_threads > 1) { 4545 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 || 4546 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 || 4547 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) { 4548 *ecx |= 1 << 1; /* CmpLegacy bit */ 4549 } 4550 } 4551 break; 4552 case 0x80000002: 4553 case 0x80000003: 4554 case 0x80000004: 4555 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0]; 4556 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1]; 4557 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2]; 4558 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3]; 4559 break; 4560 case 0x80000005: 4561 /* cache info (L1 cache) */ 4562 if (cpu->cache_info_passthrough) { 4563 host_cpuid(index, 0, eax, ebx, ecx, edx); 4564 break; 4565 } 4566 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \ 4567 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES); 4568 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \ 4569 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES); 4570 *ecx = encode_cache_cpuid80000005(env->cache_info_amd.l1d_cache); 4571 *edx = encode_cache_cpuid80000005(env->cache_info_amd.l1i_cache); 4572 break; 4573 case 0x80000006: 4574 /* cache info (L2 cache) */ 4575 if (cpu->cache_info_passthrough) { 4576 host_cpuid(index, 0, eax, ebx, ecx, edx); 4577 break; 4578 } 4579 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \ 4580 (L2_DTLB_2M_ENTRIES << 16) | \ 4581 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \ 4582 (L2_ITLB_2M_ENTRIES); 4583 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \ 4584 (L2_DTLB_4K_ENTRIES << 16) | \ 4585 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \ 4586 (L2_ITLB_4K_ENTRIES); 4587 encode_cache_cpuid80000006(env->cache_info_amd.l2_cache, 4588 cpu->enable_l3_cache ? 4589 env->cache_info_amd.l3_cache : NULL, 4590 ecx, edx); 4591 break; 4592 case 0x80000007: 4593 *eax = 0; 4594 *ebx = 0; 4595 *ecx = 0; 4596 *edx = env->features[FEAT_8000_0007_EDX]; 4597 break; 4598 case 0x80000008: 4599 /* virtual & phys address size in low 2 bytes. */ 4600 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 4601 /* 64 bit processor */ 4602 *eax = cpu->phys_bits; /* configurable physical bits */ 4603 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57) { 4604 *eax |= 0x00003900; /* 57 bits virtual */ 4605 } else { 4606 *eax |= 0x00003000; /* 48 bits virtual */ 4607 } 4608 } else { 4609 *eax = cpu->phys_bits; 4610 } 4611 *ebx = env->features[FEAT_8000_0008_EBX]; 4612 *ecx = 0; 4613 *edx = 0; 4614 if (cs->nr_cores * cs->nr_threads > 1) { 4615 *ecx |= (cs->nr_cores * cs->nr_threads) - 1; 4616 } 4617 break; 4618 case 0x8000000A: 4619 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { 4620 *eax = 0x00000001; /* SVM Revision */ 4621 *ebx = 0x00000010; /* nr of ASIDs */ 4622 *ecx = 0; 4623 *edx = env->features[FEAT_SVM]; /* optional features */ 4624 } else { 4625 *eax = 0; 4626 *ebx = 0; 4627 *ecx = 0; 4628 *edx = 0; 4629 } 4630 break; 4631 case 0x8000001D: 4632 *eax = 0; 4633 if (cpu->cache_info_passthrough) { 4634 host_cpuid(index, count, eax, ebx, ecx, edx); 4635 break; 4636 } 4637 switch (count) { 4638 case 0: /* L1 dcache info */ 4639 encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache, cs, 4640 eax, ebx, ecx, edx); 4641 break; 4642 case 1: /* L1 icache info */ 4643 encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache, cs, 4644 eax, ebx, ecx, edx); 4645 break; 4646 case 2: /* L2 cache info */ 4647 encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache, cs, 4648 eax, ebx, ecx, edx); 4649 break; 4650 case 3: /* L3 cache info */ 4651 encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache, cs, 4652 eax, ebx, ecx, edx); 4653 break; 4654 default: /* end of info */ 4655 *eax = *ebx = *ecx = *edx = 0; 4656 break; 4657 } 4658 break; 4659 case 0x8000001E: 4660 assert(cpu->core_id <= 255); 4661 encode_topo_cpuid8000001e(cs, cpu, 4662 eax, ebx, ecx, edx); 4663 break; 4664 case 0xC0000000: 4665 *eax = env->cpuid_xlevel2; 4666 *ebx = 0; 4667 *ecx = 0; 4668 *edx = 0; 4669 break; 4670 case 0xC0000001: 4671 /* Support for VIA CPU's CPUID instruction */ 4672 *eax = env->cpuid_version; 4673 *ebx = 0; 4674 *ecx = 0; 4675 *edx = env->features[FEAT_C000_0001_EDX]; 4676 break; 4677 case 0xC0000002: 4678 case 0xC0000003: 4679 case 0xC0000004: 4680 /* Reserved for the future, and now filled with zero */ 4681 *eax = 0; 4682 *ebx = 0; 4683 *ecx = 0; 4684 *edx = 0; 4685 break; 4686 case 0x8000001F: 4687 *eax = sev_enabled() ? 0x2 : 0; 4688 *ebx = sev_get_cbit_position(); 4689 *ebx |= sev_get_reduced_phys_bits() << 6; 4690 *ecx = 0; 4691 *edx = 0; 4692 break; 4693 default: 4694 /* reserved values: zero */ 4695 *eax = 0; 4696 *ebx = 0; 4697 *ecx = 0; 4698 *edx = 0; 4699 break; 4700 } 4701 } 4702 4703 /* CPUClass::reset() */ 4704 static void x86_cpu_reset(CPUState *s) 4705 { 4706 X86CPU *cpu = X86_CPU(s); 4707 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu); 4708 CPUX86State *env = &cpu->env; 4709 target_ulong cr4; 4710 uint64_t xcr0; 4711 int i; 4712 4713 xcc->parent_reset(s); 4714 4715 memset(env, 0, offsetof(CPUX86State, end_reset_fields)); 4716 4717 env->old_exception = -1; 4718 4719 /* init to reset state */ 4720 4721 env->hflags2 |= HF2_GIF_MASK; 4722 4723 cpu_x86_update_cr0(env, 0x60000010); 4724 env->a20_mask = ~0x0; 4725 env->smbase = 0x30000; 4726 env->msr_smi_count = 0; 4727 4728 env->idt.limit = 0xffff; 4729 env->gdt.limit = 0xffff; 4730 env->ldt.limit = 0xffff; 4731 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT); 4732 env->tr.limit = 0xffff; 4733 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT); 4734 4735 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff, 4736 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK | 4737 DESC_R_MASK | DESC_A_MASK); 4738 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff, 4739 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 4740 DESC_A_MASK); 4741 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff, 4742 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 4743 DESC_A_MASK); 4744 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff, 4745 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 4746 DESC_A_MASK); 4747 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff, 4748 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 4749 DESC_A_MASK); 4750 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff, 4751 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 4752 DESC_A_MASK); 4753 4754 env->eip = 0xfff0; 4755 env->regs[R_EDX] = env->cpuid_version; 4756 4757 env->eflags = 0x2; 4758 4759 /* FPU init */ 4760 for (i = 0; i < 8; i++) { 4761 env->fptags[i] = 1; 4762 } 4763 cpu_set_fpuc(env, 0x37f); 4764 4765 env->mxcsr = 0x1f80; 4766 /* All units are in INIT state. */ 4767 env->xstate_bv = 0; 4768 4769 env->pat = 0x0007040600070406ULL; 4770 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT; 4771 if (env->features[FEAT_1_ECX] & CPUID_EXT_MONITOR) { 4772 env->msr_ia32_misc_enable |= MSR_IA32_MISC_ENABLE_MWAIT; 4773 } 4774 4775 memset(env->dr, 0, sizeof(env->dr)); 4776 env->dr[6] = DR6_FIXED_1; 4777 env->dr[7] = DR7_FIXED_1; 4778 cpu_breakpoint_remove_all(s, BP_CPU); 4779 cpu_watchpoint_remove_all(s, BP_CPU); 4780 4781 cr4 = 0; 4782 xcr0 = XSTATE_FP_MASK; 4783 4784 #ifdef CONFIG_USER_ONLY 4785 /* Enable all the features for user-mode. */ 4786 if (env->features[FEAT_1_EDX] & CPUID_SSE) { 4787 xcr0 |= XSTATE_SSE_MASK; 4788 } 4789 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 4790 const ExtSaveArea *esa = &x86_ext_save_areas[i]; 4791 if (env->features[esa->feature] & esa->bits) { 4792 xcr0 |= 1ull << i; 4793 } 4794 } 4795 4796 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) { 4797 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK; 4798 } 4799 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) { 4800 cr4 |= CR4_FSGSBASE_MASK; 4801 } 4802 #endif 4803 4804 env->xcr0 = xcr0; 4805 cpu_x86_update_cr4(env, cr4); 4806 4807 /* 4808 * SDM 11.11.5 requires: 4809 * - IA32_MTRR_DEF_TYPE MSR.E = 0 4810 * - IA32_MTRR_PHYSMASKn.V = 0 4811 * All other bits are undefined. For simplification, zero it all. 4812 */ 4813 env->mtrr_deftype = 0; 4814 memset(env->mtrr_var, 0, sizeof(env->mtrr_var)); 4815 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed)); 4816 4817 env->interrupt_injected = -1; 4818 env->exception_nr = -1; 4819 env->exception_pending = 0; 4820 env->exception_injected = 0; 4821 env->exception_has_payload = false; 4822 env->exception_payload = 0; 4823 env->nmi_injected = false; 4824 #if !defined(CONFIG_USER_ONLY) 4825 /* We hard-wire the BSP to the first CPU. */ 4826 apic_designate_bsp(cpu->apic_state, s->cpu_index == 0); 4827 4828 s->halted = !cpu_is_bsp(cpu); 4829 4830 if (kvm_enabled()) { 4831 kvm_arch_reset_vcpu(cpu); 4832 } 4833 else if (hvf_enabled()) { 4834 hvf_reset_vcpu(s); 4835 } 4836 #endif 4837 } 4838 4839 #ifndef CONFIG_USER_ONLY 4840 bool cpu_is_bsp(X86CPU *cpu) 4841 { 4842 return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP; 4843 } 4844 4845 /* TODO: remove me, when reset over QOM tree is implemented */ 4846 static void x86_cpu_machine_reset_cb(void *opaque) 4847 { 4848 X86CPU *cpu = opaque; 4849 cpu_reset(CPU(cpu)); 4850 } 4851 #endif 4852 4853 static void mce_init(X86CPU *cpu) 4854 { 4855 CPUX86State *cenv = &cpu->env; 4856 unsigned int bank; 4857 4858 if (((cenv->cpuid_version >> 8) & 0xf) >= 6 4859 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) == 4860 (CPUID_MCE | CPUID_MCA)) { 4861 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF | 4862 (cpu->enable_lmce ? MCG_LMCE_P : 0); 4863 cenv->mcg_ctl = ~(uint64_t)0; 4864 for (bank = 0; bank < MCE_BANKS_DEF; bank++) { 4865 cenv->mce_banks[bank * 4] = ~(uint64_t)0; 4866 } 4867 } 4868 } 4869 4870 #ifndef CONFIG_USER_ONLY 4871 APICCommonClass *apic_get_class(void) 4872 { 4873 const char *apic_type = "apic"; 4874 4875 /* TODO: in-kernel irqchip for hvf */ 4876 if (kvm_apic_in_kernel()) { 4877 apic_type = "kvm-apic"; 4878 } else if (xen_enabled()) { 4879 apic_type = "xen-apic"; 4880 } 4881 4882 return APIC_COMMON_CLASS(object_class_by_name(apic_type)); 4883 } 4884 4885 static void x86_cpu_apic_create(X86CPU *cpu, Error **errp) 4886 { 4887 APICCommonState *apic; 4888 ObjectClass *apic_class = OBJECT_CLASS(apic_get_class()); 4889 4890 cpu->apic_state = DEVICE(object_new(object_class_get_name(apic_class))); 4891 4892 object_property_add_child(OBJECT(cpu), "lapic", 4893 OBJECT(cpu->apic_state), &error_abort); 4894 object_unref(OBJECT(cpu->apic_state)); 4895 4896 qdev_prop_set_uint32(cpu->apic_state, "id", cpu->apic_id); 4897 /* TODO: convert to link<> */ 4898 apic = APIC_COMMON(cpu->apic_state); 4899 apic->cpu = cpu; 4900 apic->apicbase = APIC_DEFAULT_ADDRESS | MSR_IA32_APICBASE_ENABLE; 4901 } 4902 4903 static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp) 4904 { 4905 APICCommonState *apic; 4906 static bool apic_mmio_map_once; 4907 4908 if (cpu->apic_state == NULL) { 4909 return; 4910 } 4911 object_property_set_bool(OBJECT(cpu->apic_state), true, "realized", 4912 errp); 4913 4914 /* Map APIC MMIO area */ 4915 apic = APIC_COMMON(cpu->apic_state); 4916 if (!apic_mmio_map_once) { 4917 memory_region_add_subregion_overlap(get_system_memory(), 4918 apic->apicbase & 4919 MSR_IA32_APICBASE_BASE, 4920 &apic->io_memory, 4921 0x1000); 4922 apic_mmio_map_once = true; 4923 } 4924 } 4925 4926 static void x86_cpu_machine_done(Notifier *n, void *unused) 4927 { 4928 X86CPU *cpu = container_of(n, X86CPU, machine_done); 4929 MemoryRegion *smram = 4930 (MemoryRegion *) object_resolve_path("/machine/smram", NULL); 4931 4932 if (smram) { 4933 cpu->smram = g_new(MemoryRegion, 1); 4934 memory_region_init_alias(cpu->smram, OBJECT(cpu), "smram", 4935 smram, 0, 1ull << 32); 4936 memory_region_set_enabled(cpu->smram, true); 4937 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->smram, 1); 4938 } 4939 } 4940 #else 4941 static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp) 4942 { 4943 } 4944 #endif 4945 4946 /* Note: Only safe for use on x86(-64) hosts */ 4947 static uint32_t x86_host_phys_bits(void) 4948 { 4949 uint32_t eax; 4950 uint32_t host_phys_bits; 4951 4952 host_cpuid(0x80000000, 0, &eax, NULL, NULL, NULL); 4953 if (eax >= 0x80000008) { 4954 host_cpuid(0x80000008, 0, &eax, NULL, NULL, NULL); 4955 /* Note: According to AMD doc 25481 rev 2.34 they have a field 4956 * at 23:16 that can specify a maximum physical address bits for 4957 * the guest that can override this value; but I've not seen 4958 * anything with that set. 4959 */ 4960 host_phys_bits = eax & 0xff; 4961 } else { 4962 /* It's an odd 64 bit machine that doesn't have the leaf for 4963 * physical address bits; fall back to 36 that's most older 4964 * Intel. 4965 */ 4966 host_phys_bits = 36; 4967 } 4968 4969 return host_phys_bits; 4970 } 4971 4972 static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value) 4973 { 4974 if (*min < value) { 4975 *min = value; 4976 } 4977 } 4978 4979 /* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */ 4980 static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w) 4981 { 4982 CPUX86State *env = &cpu->env; 4983 FeatureWordInfo *fi = &feature_word_info[w]; 4984 uint32_t eax = fi->cpuid.eax; 4985 uint32_t region = eax & 0xF0000000; 4986 4987 assert(feature_word_info[w].type == CPUID_FEATURE_WORD); 4988 if (!env->features[w]) { 4989 return; 4990 } 4991 4992 switch (region) { 4993 case 0x00000000: 4994 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax); 4995 break; 4996 case 0x80000000: 4997 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax); 4998 break; 4999 case 0xC0000000: 5000 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax); 5001 break; 5002 } 5003 5004 if (eax == 7) { 5005 x86_cpu_adjust_level(cpu, &env->cpuid_min_level_func7, 5006 fi->cpuid.ecx); 5007 } 5008 } 5009 5010 /* Calculate XSAVE components based on the configured CPU feature flags */ 5011 static void x86_cpu_enable_xsave_components(X86CPU *cpu) 5012 { 5013 CPUX86State *env = &cpu->env; 5014 int i; 5015 uint64_t mask; 5016 5017 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { 5018 return; 5019 } 5020 5021 mask = 0; 5022 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 5023 const ExtSaveArea *esa = &x86_ext_save_areas[i]; 5024 if (env->features[esa->feature] & esa->bits) { 5025 mask |= (1ULL << i); 5026 } 5027 } 5028 5029 env->features[FEAT_XSAVE_COMP_LO] = mask; 5030 env->features[FEAT_XSAVE_COMP_HI] = mask >> 32; 5031 } 5032 5033 /***** Steps involved on loading and filtering CPUID data 5034 * 5035 * When initializing and realizing a CPU object, the steps 5036 * involved in setting up CPUID data are: 5037 * 5038 * 1) Loading CPU model definition (X86CPUDefinition). This is 5039 * implemented by x86_cpu_load_model() and should be completely 5040 * transparent, as it is done automatically by instance_init. 5041 * No code should need to look at X86CPUDefinition structs 5042 * outside instance_init. 5043 * 5044 * 2) CPU expansion. This is done by realize before CPUID 5045 * filtering, and will make sure host/accelerator data is 5046 * loaded for CPU models that depend on host capabilities 5047 * (e.g. "host"). Done by x86_cpu_expand_features(). 5048 * 5049 * 3) CPUID filtering. This initializes extra data related to 5050 * CPUID, and checks if the host supports all capabilities 5051 * required by the CPU. Runnability of a CPU model is 5052 * determined at this step. Done by x86_cpu_filter_features(). 5053 * 5054 * Some operations don't require all steps to be performed. 5055 * More precisely: 5056 * 5057 * - CPU instance creation (instance_init) will run only CPU 5058 * model loading. CPU expansion can't run at instance_init-time 5059 * because host/accelerator data may be not available yet. 5060 * - CPU realization will perform both CPU model expansion and CPUID 5061 * filtering, and return an error in case one of them fails. 5062 * - query-cpu-definitions needs to run all 3 steps. It needs 5063 * to run CPUID filtering, as the 'unavailable-features' 5064 * field is set based on the filtering results. 5065 * - The query-cpu-model-expansion QMP command only needs to run 5066 * CPU model loading and CPU expansion. It should not filter 5067 * any CPUID data based on host capabilities. 5068 */ 5069 5070 /* Expand CPU configuration data, based on configured features 5071 * and host/accelerator capabilities when appropriate. 5072 */ 5073 static void x86_cpu_expand_features(X86CPU *cpu, Error **errp) 5074 { 5075 CPUX86State *env = &cpu->env; 5076 FeatureWord w; 5077 int i; 5078 GList *l; 5079 Error *local_err = NULL; 5080 5081 for (l = plus_features; l; l = l->next) { 5082 const char *prop = l->data; 5083 object_property_set_bool(OBJECT(cpu), true, prop, &local_err); 5084 if (local_err) { 5085 goto out; 5086 } 5087 } 5088 5089 for (l = minus_features; l; l = l->next) { 5090 const char *prop = l->data; 5091 object_property_set_bool(OBJECT(cpu), false, prop, &local_err); 5092 if (local_err) { 5093 goto out; 5094 } 5095 } 5096 5097 /*TODO: Now cpu->max_features doesn't overwrite features 5098 * set using QOM properties, and we can convert 5099 * plus_features & minus_features to global properties 5100 * inside x86_cpu_parse_featurestr() too. 5101 */ 5102 if (cpu->max_features) { 5103 for (w = 0; w < FEATURE_WORDS; w++) { 5104 /* Override only features that weren't set explicitly 5105 * by the user. 5106 */ 5107 env->features[w] |= 5108 x86_cpu_get_supported_feature_word(w, cpu->migratable) & 5109 ~env->user_features[w] & \ 5110 ~feature_word_info[w].no_autoenable_flags; 5111 } 5112 } 5113 5114 for (i = 0; i < ARRAY_SIZE(feature_dependencies); i++) { 5115 FeatureDep *d = &feature_dependencies[i]; 5116 if (!(env->features[d->from.index] & d->from.mask)) { 5117 uint64_t unavailable_features = env->features[d->to.index] & d->to.mask; 5118 5119 /* Not an error unless the dependent feature was added explicitly. */ 5120 mark_unavailable_features(cpu, d->to.index, 5121 unavailable_features & env->user_features[d->to.index], 5122 "This feature depends on other features that were not requested"); 5123 5124 env->user_features[d->to.index] |= unavailable_features; 5125 env->features[d->to.index] &= ~unavailable_features; 5126 } 5127 } 5128 5129 if (!kvm_enabled() || !cpu->expose_kvm) { 5130 env->features[FEAT_KVM] = 0; 5131 } 5132 5133 x86_cpu_enable_xsave_components(cpu); 5134 5135 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */ 5136 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX); 5137 if (cpu->full_cpuid_auto_level) { 5138 x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX); 5139 x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX); 5140 x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX); 5141 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX); 5142 x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EAX); 5143 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX); 5144 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX); 5145 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX); 5146 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0008_EBX); 5147 x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX); 5148 x86_cpu_adjust_feat_level(cpu, FEAT_SVM); 5149 x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE); 5150 5151 /* Intel Processor Trace requires CPUID[0x14] */ 5152 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) && 5153 kvm_enabled() && cpu->intel_pt_auto_level) { 5154 x86_cpu_adjust_level(cpu, &cpu->env.cpuid_min_level, 0x14); 5155 } 5156 5157 /* CPU topology with multi-dies support requires CPUID[0x1F] */ 5158 if (env->nr_dies > 1) { 5159 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x1F); 5160 } 5161 5162 /* SVM requires CPUID[0x8000000A] */ 5163 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { 5164 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A); 5165 } 5166 5167 /* SEV requires CPUID[0x8000001F] */ 5168 if (sev_enabled()) { 5169 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F); 5170 } 5171 } 5172 5173 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */ 5174 if (env->cpuid_level_func7 == UINT32_MAX) { 5175 env->cpuid_level_func7 = env->cpuid_min_level_func7; 5176 } 5177 if (env->cpuid_level == UINT32_MAX) { 5178 env->cpuid_level = env->cpuid_min_level; 5179 } 5180 if (env->cpuid_xlevel == UINT32_MAX) { 5181 env->cpuid_xlevel = env->cpuid_min_xlevel; 5182 } 5183 if (env->cpuid_xlevel2 == UINT32_MAX) { 5184 env->cpuid_xlevel2 = env->cpuid_min_xlevel2; 5185 } 5186 5187 out: 5188 if (local_err != NULL) { 5189 error_propagate(errp, local_err); 5190 } 5191 } 5192 5193 /* 5194 * Finishes initialization of CPUID data, filters CPU feature 5195 * words based on host availability of each feature. 5196 * 5197 * Returns: 0 if all flags are supported by the host, non-zero otherwise. 5198 */ 5199 static void x86_cpu_filter_features(X86CPU *cpu, bool verbose) 5200 { 5201 CPUX86State *env = &cpu->env; 5202 FeatureWord w; 5203 const char *prefix = NULL; 5204 5205 if (verbose) { 5206 prefix = accel_uses_host_cpuid() 5207 ? "host doesn't support requested feature" 5208 : "TCG doesn't support requested feature"; 5209 } 5210 5211 for (w = 0; w < FEATURE_WORDS; w++) { 5212 uint64_t host_feat = 5213 x86_cpu_get_supported_feature_word(w, false); 5214 uint64_t requested_features = env->features[w]; 5215 uint64_t unavailable_features = requested_features & ~host_feat; 5216 mark_unavailable_features(cpu, w, unavailable_features, prefix); 5217 } 5218 5219 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) && 5220 kvm_enabled()) { 5221 KVMState *s = CPU(cpu)->kvm_state; 5222 uint32_t eax_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EAX); 5223 uint32_t ebx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EBX); 5224 uint32_t ecx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_ECX); 5225 uint32_t eax_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EAX); 5226 uint32_t ebx_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EBX); 5227 5228 if (!eax_0 || 5229 ((ebx_0 & INTEL_PT_MINIMAL_EBX) != INTEL_PT_MINIMAL_EBX) || 5230 ((ecx_0 & INTEL_PT_MINIMAL_ECX) != INTEL_PT_MINIMAL_ECX) || 5231 ((eax_1 & INTEL_PT_MTC_BITMAP) != INTEL_PT_MTC_BITMAP) || 5232 ((eax_1 & INTEL_PT_ADDR_RANGES_NUM_MASK) < 5233 INTEL_PT_ADDR_RANGES_NUM) || 5234 ((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) != 5235 (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) || 5236 (ecx_0 & INTEL_PT_IP_LIP)) { 5237 /* 5238 * Processor Trace capabilities aren't configurable, so if the 5239 * host can't emulate the capabilities we report on 5240 * cpu_x86_cpuid(), intel-pt can't be enabled on the current host. 5241 */ 5242 mark_unavailable_features(cpu, FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT, prefix); 5243 } 5244 } 5245 } 5246 5247 static void x86_cpu_realizefn(DeviceState *dev, Error **errp) 5248 { 5249 CPUState *cs = CPU(dev); 5250 X86CPU *cpu = X86_CPU(dev); 5251 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev); 5252 CPUX86State *env = &cpu->env; 5253 Error *local_err = NULL; 5254 static bool ht_warned; 5255 5256 if (xcc->host_cpuid_required) { 5257 if (!accel_uses_host_cpuid()) { 5258 char *name = x86_cpu_class_get_model_name(xcc); 5259 error_setg(&local_err, "CPU model '%s' requires KVM", name); 5260 g_free(name); 5261 goto out; 5262 } 5263 5264 if (enable_cpu_pm) { 5265 host_cpuid(5, 0, &cpu->mwait.eax, &cpu->mwait.ebx, 5266 &cpu->mwait.ecx, &cpu->mwait.edx); 5267 env->features[FEAT_1_ECX] |= CPUID_EXT_MONITOR; 5268 } 5269 } 5270 5271 /* mwait extended info: needed for Core compatibility */ 5272 /* We always wake on interrupt even if host does not have the capability */ 5273 cpu->mwait.ecx |= CPUID_MWAIT_EMX | CPUID_MWAIT_IBE; 5274 5275 if (cpu->apic_id == UNASSIGNED_APIC_ID) { 5276 error_setg(errp, "apic-id property was not initialized properly"); 5277 return; 5278 } 5279 5280 x86_cpu_expand_features(cpu, &local_err); 5281 if (local_err) { 5282 goto out; 5283 } 5284 5285 x86_cpu_filter_features(cpu, cpu->check_cpuid || cpu->enforce_cpuid); 5286 5287 if (cpu->enforce_cpuid && x86_cpu_have_filtered_features(cpu)) { 5288 error_setg(&local_err, 5289 accel_uses_host_cpuid() ? 5290 "Host doesn't support requested features" : 5291 "TCG doesn't support requested features"); 5292 goto out; 5293 } 5294 5295 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on 5296 * CPUID[1].EDX. 5297 */ 5298 if (IS_AMD_CPU(env)) { 5299 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES; 5300 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX] 5301 & CPUID_EXT2_AMD_ALIASES); 5302 } 5303 5304 /* For 64bit systems think about the number of physical bits to present. 5305 * ideally this should be the same as the host; anything other than matching 5306 * the host can cause incorrect guest behaviour. 5307 * QEMU used to pick the magic value of 40 bits that corresponds to 5308 * consumer AMD devices but nothing else. 5309 */ 5310 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 5311 if (accel_uses_host_cpuid()) { 5312 uint32_t host_phys_bits = x86_host_phys_bits(); 5313 static bool warned; 5314 5315 /* Print a warning if the user set it to a value that's not the 5316 * host value. 5317 */ 5318 if (cpu->phys_bits != host_phys_bits && cpu->phys_bits != 0 && 5319 !warned) { 5320 warn_report("Host physical bits (%u)" 5321 " does not match phys-bits property (%u)", 5322 host_phys_bits, cpu->phys_bits); 5323 warned = true; 5324 } 5325 5326 if (cpu->host_phys_bits) { 5327 /* The user asked for us to use the host physical bits */ 5328 cpu->phys_bits = host_phys_bits; 5329 if (cpu->host_phys_bits_limit && 5330 cpu->phys_bits > cpu->host_phys_bits_limit) { 5331 cpu->phys_bits = cpu->host_phys_bits_limit; 5332 } 5333 } 5334 5335 if (cpu->phys_bits && 5336 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS || 5337 cpu->phys_bits < 32)) { 5338 error_setg(errp, "phys-bits should be between 32 and %u " 5339 " (but is %u)", 5340 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits); 5341 return; 5342 } 5343 } else { 5344 if (cpu->phys_bits && cpu->phys_bits != TCG_PHYS_ADDR_BITS) { 5345 error_setg(errp, "TCG only supports phys-bits=%u", 5346 TCG_PHYS_ADDR_BITS); 5347 return; 5348 } 5349 } 5350 /* 0 means it was not explicitly set by the user (or by machine 5351 * compat_props or by the host code above). In this case, the default 5352 * is the value used by TCG (40). 5353 */ 5354 if (cpu->phys_bits == 0) { 5355 cpu->phys_bits = TCG_PHYS_ADDR_BITS; 5356 } 5357 } else { 5358 /* For 32 bit systems don't use the user set value, but keep 5359 * phys_bits consistent with what we tell the guest. 5360 */ 5361 if (cpu->phys_bits != 0) { 5362 error_setg(errp, "phys-bits is not user-configurable in 32 bit"); 5363 return; 5364 } 5365 5366 if (env->features[FEAT_1_EDX] & CPUID_PSE36) { 5367 cpu->phys_bits = 36; 5368 } else { 5369 cpu->phys_bits = 32; 5370 } 5371 } 5372 5373 /* Cache information initialization */ 5374 if (!cpu->legacy_cache) { 5375 if (!xcc->model || !xcc->model->cpudef->cache_info) { 5376 char *name = x86_cpu_class_get_model_name(xcc); 5377 error_setg(errp, 5378 "CPU model '%s' doesn't support legacy-cache=off", name); 5379 g_free(name); 5380 return; 5381 } 5382 env->cache_info_cpuid2 = env->cache_info_cpuid4 = env->cache_info_amd = 5383 *xcc->model->cpudef->cache_info; 5384 } else { 5385 /* Build legacy cache information */ 5386 env->cache_info_cpuid2.l1d_cache = &legacy_l1d_cache; 5387 env->cache_info_cpuid2.l1i_cache = &legacy_l1i_cache; 5388 env->cache_info_cpuid2.l2_cache = &legacy_l2_cache_cpuid2; 5389 env->cache_info_cpuid2.l3_cache = &legacy_l3_cache; 5390 5391 env->cache_info_cpuid4.l1d_cache = &legacy_l1d_cache; 5392 env->cache_info_cpuid4.l1i_cache = &legacy_l1i_cache; 5393 env->cache_info_cpuid4.l2_cache = &legacy_l2_cache; 5394 env->cache_info_cpuid4.l3_cache = &legacy_l3_cache; 5395 5396 env->cache_info_amd.l1d_cache = &legacy_l1d_cache_amd; 5397 env->cache_info_amd.l1i_cache = &legacy_l1i_cache_amd; 5398 env->cache_info_amd.l2_cache = &legacy_l2_cache_amd; 5399 env->cache_info_amd.l3_cache = &legacy_l3_cache; 5400 } 5401 5402 5403 cpu_exec_realizefn(cs, &local_err); 5404 if (local_err != NULL) { 5405 error_propagate(errp, local_err); 5406 return; 5407 } 5408 5409 #ifndef CONFIG_USER_ONLY 5410 MachineState *ms = MACHINE(qdev_get_machine()); 5411 qemu_register_reset(x86_cpu_machine_reset_cb, cpu); 5412 5413 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || ms->smp.cpus > 1) { 5414 x86_cpu_apic_create(cpu, &local_err); 5415 if (local_err != NULL) { 5416 goto out; 5417 } 5418 } 5419 #endif 5420 5421 mce_init(cpu); 5422 5423 #ifndef CONFIG_USER_ONLY 5424 if (tcg_enabled()) { 5425 cpu->cpu_as_mem = g_new(MemoryRegion, 1); 5426 cpu->cpu_as_root = g_new(MemoryRegion, 1); 5427 5428 /* Outer container... */ 5429 memory_region_init(cpu->cpu_as_root, OBJECT(cpu), "memory", ~0ull); 5430 memory_region_set_enabled(cpu->cpu_as_root, true); 5431 5432 /* ... with two regions inside: normal system memory with low 5433 * priority, and... 5434 */ 5435 memory_region_init_alias(cpu->cpu_as_mem, OBJECT(cpu), "memory", 5436 get_system_memory(), 0, ~0ull); 5437 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->cpu_as_mem, 0); 5438 memory_region_set_enabled(cpu->cpu_as_mem, true); 5439 5440 cs->num_ases = 2; 5441 cpu_address_space_init(cs, 0, "cpu-memory", cs->memory); 5442 cpu_address_space_init(cs, 1, "cpu-smm", cpu->cpu_as_root); 5443 5444 /* ... SMRAM with higher priority, linked from /machine/smram. */ 5445 cpu->machine_done.notify = x86_cpu_machine_done; 5446 qemu_add_machine_init_done_notifier(&cpu->machine_done); 5447 } 5448 #endif 5449 5450 qemu_init_vcpu(cs); 5451 5452 /* 5453 * Most Intel and certain AMD CPUs support hyperthreading. Even though QEMU 5454 * fixes this issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX 5455 * based on inputs (sockets,cores,threads), it is still better to give 5456 * users a warning. 5457 * 5458 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise 5459 * cs->nr_threads hasn't be populated yet and the checking is incorrect. 5460 */ 5461 if (IS_AMD_CPU(env) && 5462 !(env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) && 5463 cs->nr_threads > 1 && !ht_warned) { 5464 warn_report("This family of AMD CPU doesn't support " 5465 "hyperthreading(%d)", 5466 cs->nr_threads); 5467 error_printf("Please configure -smp options properly" 5468 " or try enabling topoext feature.\n"); 5469 ht_warned = true; 5470 } 5471 5472 x86_cpu_apic_realize(cpu, &local_err); 5473 if (local_err != NULL) { 5474 goto out; 5475 } 5476 cpu_reset(cs); 5477 5478 xcc->parent_realize(dev, &local_err); 5479 5480 out: 5481 if (local_err != NULL) { 5482 error_propagate(errp, local_err); 5483 return; 5484 } 5485 } 5486 5487 static void x86_cpu_unrealizefn(DeviceState *dev, Error **errp) 5488 { 5489 X86CPU *cpu = X86_CPU(dev); 5490 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev); 5491 Error *local_err = NULL; 5492 5493 #ifndef CONFIG_USER_ONLY 5494 cpu_remove_sync(CPU(dev)); 5495 qemu_unregister_reset(x86_cpu_machine_reset_cb, dev); 5496 #endif 5497 5498 if (cpu->apic_state) { 5499 object_unparent(OBJECT(cpu->apic_state)); 5500 cpu->apic_state = NULL; 5501 } 5502 5503 xcc->parent_unrealize(dev, &local_err); 5504 if (local_err != NULL) { 5505 error_propagate(errp, local_err); 5506 return; 5507 } 5508 } 5509 5510 typedef struct BitProperty { 5511 FeatureWord w; 5512 uint64_t mask; 5513 } BitProperty; 5514 5515 static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name, 5516 void *opaque, Error **errp) 5517 { 5518 X86CPU *cpu = X86_CPU(obj); 5519 BitProperty *fp = opaque; 5520 uint64_t f = cpu->env.features[fp->w]; 5521 bool value = (f & fp->mask) == fp->mask; 5522 visit_type_bool(v, name, &value, errp); 5523 } 5524 5525 static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name, 5526 void *opaque, Error **errp) 5527 { 5528 DeviceState *dev = DEVICE(obj); 5529 X86CPU *cpu = X86_CPU(obj); 5530 BitProperty *fp = opaque; 5531 Error *local_err = NULL; 5532 bool value; 5533 5534 if (dev->realized) { 5535 qdev_prop_set_after_realize(dev, name, errp); 5536 return; 5537 } 5538 5539 visit_type_bool(v, name, &value, &local_err); 5540 if (local_err) { 5541 error_propagate(errp, local_err); 5542 return; 5543 } 5544 5545 if (value) { 5546 cpu->env.features[fp->w] |= fp->mask; 5547 } else { 5548 cpu->env.features[fp->w] &= ~fp->mask; 5549 } 5550 cpu->env.user_features[fp->w] |= fp->mask; 5551 } 5552 5553 static void x86_cpu_release_bit_prop(Object *obj, const char *name, 5554 void *opaque) 5555 { 5556 BitProperty *prop = opaque; 5557 g_free(prop); 5558 } 5559 5560 /* Register a boolean property to get/set a single bit in a uint32_t field. 5561 * 5562 * The same property name can be registered multiple times to make it affect 5563 * multiple bits in the same FeatureWord. In that case, the getter will return 5564 * true only if all bits are set. 5565 */ 5566 static void x86_cpu_register_bit_prop(X86CPU *cpu, 5567 const char *prop_name, 5568 FeatureWord w, 5569 int bitnr) 5570 { 5571 BitProperty *fp; 5572 ObjectProperty *op; 5573 uint64_t mask = (1ULL << bitnr); 5574 5575 op = object_property_find(OBJECT(cpu), prop_name, NULL); 5576 if (op) { 5577 fp = op->opaque; 5578 assert(fp->w == w); 5579 fp->mask |= mask; 5580 } else { 5581 fp = g_new0(BitProperty, 1); 5582 fp->w = w; 5583 fp->mask = mask; 5584 object_property_add(OBJECT(cpu), prop_name, "bool", 5585 x86_cpu_get_bit_prop, 5586 x86_cpu_set_bit_prop, 5587 x86_cpu_release_bit_prop, fp, &error_abort); 5588 } 5589 } 5590 5591 static void x86_cpu_register_feature_bit_props(X86CPU *cpu, 5592 FeatureWord w, 5593 int bitnr) 5594 { 5595 FeatureWordInfo *fi = &feature_word_info[w]; 5596 const char *name = fi->feat_names[bitnr]; 5597 5598 if (!name) { 5599 return; 5600 } 5601 5602 /* Property names should use "-" instead of "_". 5603 * Old names containing underscores are registered as aliases 5604 * using object_property_add_alias() 5605 */ 5606 assert(!strchr(name, '_')); 5607 /* aliases don't use "|" delimiters anymore, they are registered 5608 * manually using object_property_add_alias() */ 5609 assert(!strchr(name, '|')); 5610 x86_cpu_register_bit_prop(cpu, name, w, bitnr); 5611 } 5612 5613 static GuestPanicInformation *x86_cpu_get_crash_info(CPUState *cs) 5614 { 5615 X86CPU *cpu = X86_CPU(cs); 5616 CPUX86State *env = &cpu->env; 5617 GuestPanicInformation *panic_info = NULL; 5618 5619 if (env->features[FEAT_HYPERV_EDX] & HV_GUEST_CRASH_MSR_AVAILABLE) { 5620 panic_info = g_malloc0(sizeof(GuestPanicInformation)); 5621 5622 panic_info->type = GUEST_PANIC_INFORMATION_TYPE_HYPER_V; 5623 5624 assert(HV_CRASH_PARAMS >= 5); 5625 panic_info->u.hyper_v.arg1 = env->msr_hv_crash_params[0]; 5626 panic_info->u.hyper_v.arg2 = env->msr_hv_crash_params[1]; 5627 panic_info->u.hyper_v.arg3 = env->msr_hv_crash_params[2]; 5628 panic_info->u.hyper_v.arg4 = env->msr_hv_crash_params[3]; 5629 panic_info->u.hyper_v.arg5 = env->msr_hv_crash_params[4]; 5630 } 5631 5632 return panic_info; 5633 } 5634 static void x86_cpu_get_crash_info_qom(Object *obj, Visitor *v, 5635 const char *name, void *opaque, 5636 Error **errp) 5637 { 5638 CPUState *cs = CPU(obj); 5639 GuestPanicInformation *panic_info; 5640 5641 if (!cs->crash_occurred) { 5642 error_setg(errp, "No crash occured"); 5643 return; 5644 } 5645 5646 panic_info = x86_cpu_get_crash_info(cs); 5647 if (panic_info == NULL) { 5648 error_setg(errp, "No crash information"); 5649 return; 5650 } 5651 5652 visit_type_GuestPanicInformation(v, "crash-information", &panic_info, 5653 errp); 5654 qapi_free_GuestPanicInformation(panic_info); 5655 } 5656 5657 static void x86_cpu_initfn(Object *obj) 5658 { 5659 X86CPU *cpu = X86_CPU(obj); 5660 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj); 5661 CPUX86State *env = &cpu->env; 5662 FeatureWord w; 5663 5664 env->nr_dies = 1; 5665 cpu_set_cpustate_pointers(cpu); 5666 5667 object_property_add(obj, "family", "int", 5668 x86_cpuid_version_get_family, 5669 x86_cpuid_version_set_family, NULL, NULL, NULL); 5670 object_property_add(obj, "model", "int", 5671 x86_cpuid_version_get_model, 5672 x86_cpuid_version_set_model, NULL, NULL, NULL); 5673 object_property_add(obj, "stepping", "int", 5674 x86_cpuid_version_get_stepping, 5675 x86_cpuid_version_set_stepping, NULL, NULL, NULL); 5676 object_property_add_str(obj, "vendor", 5677 x86_cpuid_get_vendor, 5678 x86_cpuid_set_vendor, NULL); 5679 object_property_add_str(obj, "model-id", 5680 x86_cpuid_get_model_id, 5681 x86_cpuid_set_model_id, NULL); 5682 object_property_add(obj, "tsc-frequency", "int", 5683 x86_cpuid_get_tsc_freq, 5684 x86_cpuid_set_tsc_freq, NULL, NULL, NULL); 5685 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo", 5686 x86_cpu_get_feature_words, 5687 NULL, NULL, (void *)env->features, NULL); 5688 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo", 5689 x86_cpu_get_feature_words, 5690 NULL, NULL, (void *)cpu->filtered_features, NULL); 5691 /* 5692 * The "unavailable-features" property has the same semantics as 5693 * CpuDefinitionInfo.unavailable-features on the "query-cpu-definitions" 5694 * QMP command: they list the features that would have prevented the 5695 * CPU from running if the "enforce" flag was set. 5696 */ 5697 object_property_add(obj, "unavailable-features", "strList", 5698 x86_cpu_get_unavailable_features, 5699 NULL, NULL, NULL, &error_abort); 5700 5701 object_property_add(obj, "crash-information", "GuestPanicInformation", 5702 x86_cpu_get_crash_info_qom, NULL, NULL, NULL, NULL); 5703 5704 for (w = 0; w < FEATURE_WORDS; w++) { 5705 int bitnr; 5706 5707 for (bitnr = 0; bitnr < 64; bitnr++) { 5708 x86_cpu_register_feature_bit_props(cpu, w, bitnr); 5709 } 5710 } 5711 5712 object_property_add_alias(obj, "sse3", obj, "pni", &error_abort); 5713 object_property_add_alias(obj, "pclmuldq", obj, "pclmulqdq", &error_abort); 5714 object_property_add_alias(obj, "sse4-1", obj, "sse4.1", &error_abort); 5715 object_property_add_alias(obj, "sse4-2", obj, "sse4.2", &error_abort); 5716 object_property_add_alias(obj, "xd", obj, "nx", &error_abort); 5717 object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt", &error_abort); 5718 object_property_add_alias(obj, "i64", obj, "lm", &error_abort); 5719 5720 object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl", &error_abort); 5721 object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust", &error_abort); 5722 object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt", &error_abort); 5723 object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm", &error_abort); 5724 object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy", &error_abort); 5725 object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr", &error_abort); 5726 object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core", &error_abort); 5727 object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb", &error_abort); 5728 object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay", &error_abort); 5729 object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu", &error_abort); 5730 object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf", &error_abort); 5731 object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time", &error_abort); 5732 object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi", &error_abort); 5733 object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt", &error_abort); 5734 object_property_add_alias(obj, "kvm_poll_control", obj, "kvm-poll-control", 5735 &error_abort); 5736 object_property_add_alias(obj, "svm_lock", obj, "svm-lock", &error_abort); 5737 object_property_add_alias(obj, "nrip_save", obj, "nrip-save", &error_abort); 5738 object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale", &error_abort); 5739 object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean", &error_abort); 5740 object_property_add_alias(obj, "pause_filter", obj, "pause-filter", &error_abort); 5741 object_property_add_alias(obj, "sse4_1", obj, "sse4.1", &error_abort); 5742 object_property_add_alias(obj, "sse4_2", obj, "sse4.2", &error_abort); 5743 5744 if (xcc->model) { 5745 x86_cpu_load_model(cpu, xcc->model, &error_abort); 5746 } 5747 } 5748 5749 static int64_t x86_cpu_get_arch_id(CPUState *cs) 5750 { 5751 X86CPU *cpu = X86_CPU(cs); 5752 5753 return cpu->apic_id; 5754 } 5755 5756 static bool x86_cpu_get_paging_enabled(const CPUState *cs) 5757 { 5758 X86CPU *cpu = X86_CPU(cs); 5759 5760 return cpu->env.cr[0] & CR0_PG_MASK; 5761 } 5762 5763 static void x86_cpu_set_pc(CPUState *cs, vaddr value) 5764 { 5765 X86CPU *cpu = X86_CPU(cs); 5766 5767 cpu->env.eip = value; 5768 } 5769 5770 static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) 5771 { 5772 X86CPU *cpu = X86_CPU(cs); 5773 5774 cpu->env.eip = tb->pc - tb->cs_base; 5775 } 5776 5777 int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request) 5778 { 5779 X86CPU *cpu = X86_CPU(cs); 5780 CPUX86State *env = &cpu->env; 5781 5782 #if !defined(CONFIG_USER_ONLY) 5783 if (interrupt_request & CPU_INTERRUPT_POLL) { 5784 return CPU_INTERRUPT_POLL; 5785 } 5786 #endif 5787 if (interrupt_request & CPU_INTERRUPT_SIPI) { 5788 return CPU_INTERRUPT_SIPI; 5789 } 5790 5791 if (env->hflags2 & HF2_GIF_MASK) { 5792 if ((interrupt_request & CPU_INTERRUPT_SMI) && 5793 !(env->hflags & HF_SMM_MASK)) { 5794 return CPU_INTERRUPT_SMI; 5795 } else if ((interrupt_request & CPU_INTERRUPT_NMI) && 5796 !(env->hflags2 & HF2_NMI_MASK)) { 5797 return CPU_INTERRUPT_NMI; 5798 } else if (interrupt_request & CPU_INTERRUPT_MCE) { 5799 return CPU_INTERRUPT_MCE; 5800 } else if ((interrupt_request & CPU_INTERRUPT_HARD) && 5801 (((env->hflags2 & HF2_VINTR_MASK) && 5802 (env->hflags2 & HF2_HIF_MASK)) || 5803 (!(env->hflags2 & HF2_VINTR_MASK) && 5804 (env->eflags & IF_MASK && 5805 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) { 5806 return CPU_INTERRUPT_HARD; 5807 #if !defined(CONFIG_USER_ONLY) 5808 } else if ((interrupt_request & CPU_INTERRUPT_VIRQ) && 5809 (env->eflags & IF_MASK) && 5810 !(env->hflags & HF_INHIBIT_IRQ_MASK)) { 5811 return CPU_INTERRUPT_VIRQ; 5812 #endif 5813 } 5814 } 5815 5816 return 0; 5817 } 5818 5819 static bool x86_cpu_has_work(CPUState *cs) 5820 { 5821 return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0; 5822 } 5823 5824 static void x86_disas_set_info(CPUState *cs, disassemble_info *info) 5825 { 5826 X86CPU *cpu = X86_CPU(cs); 5827 CPUX86State *env = &cpu->env; 5828 5829 info->mach = (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64 5830 : env->hflags & HF_CS32_MASK ? bfd_mach_i386_i386 5831 : bfd_mach_i386_i8086); 5832 info->print_insn = print_insn_i386; 5833 5834 info->cap_arch = CS_ARCH_X86; 5835 info->cap_mode = (env->hflags & HF_CS64_MASK ? CS_MODE_64 5836 : env->hflags & HF_CS32_MASK ? CS_MODE_32 5837 : CS_MODE_16); 5838 info->cap_insn_unit = 1; 5839 info->cap_insn_split = 8; 5840 } 5841 5842 void x86_update_hflags(CPUX86State *env) 5843 { 5844 uint32_t hflags; 5845 #define HFLAG_COPY_MASK \ 5846 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \ 5847 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \ 5848 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \ 5849 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK) 5850 5851 hflags = env->hflags & HFLAG_COPY_MASK; 5852 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK; 5853 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT); 5854 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) & 5855 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK); 5856 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK)); 5857 5858 if (env->cr[4] & CR4_OSFXSR_MASK) { 5859 hflags |= HF_OSFXSR_MASK; 5860 } 5861 5862 if (env->efer & MSR_EFER_LMA) { 5863 hflags |= HF_LMA_MASK; 5864 } 5865 5866 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) { 5867 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; 5868 } else { 5869 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >> 5870 (DESC_B_SHIFT - HF_CS32_SHIFT); 5871 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >> 5872 (DESC_B_SHIFT - HF_SS32_SHIFT); 5873 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) || 5874 !(hflags & HF_CS32_MASK)) { 5875 hflags |= HF_ADDSEG_MASK; 5876 } else { 5877 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base | 5878 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT; 5879 } 5880 } 5881 env->hflags = hflags; 5882 } 5883 5884 static Property x86_cpu_properties[] = { 5885 #ifdef CONFIG_USER_ONLY 5886 /* apic_id = 0 by default for *-user, see commit 9886e834 */ 5887 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0), 5888 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0), 5889 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0), 5890 DEFINE_PROP_INT32("die-id", X86CPU, die_id, 0), 5891 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0), 5892 #else 5893 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID), 5894 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1), 5895 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1), 5896 DEFINE_PROP_INT32("die-id", X86CPU, die_id, -1), 5897 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1), 5898 #endif 5899 DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID), 5900 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false), 5901 5902 DEFINE_PROP_UINT32("hv-spinlocks", X86CPU, hyperv_spinlock_attempts, 5903 HYPERV_SPINLOCK_NEVER_RETRY), 5904 DEFINE_PROP_BIT64("hv-relaxed", X86CPU, hyperv_features, 5905 HYPERV_FEAT_RELAXED, 0), 5906 DEFINE_PROP_BIT64("hv-vapic", X86CPU, hyperv_features, 5907 HYPERV_FEAT_VAPIC, 0), 5908 DEFINE_PROP_BIT64("hv-time", X86CPU, hyperv_features, 5909 HYPERV_FEAT_TIME, 0), 5910 DEFINE_PROP_BIT64("hv-crash", X86CPU, hyperv_features, 5911 HYPERV_FEAT_CRASH, 0), 5912 DEFINE_PROP_BIT64("hv-reset", X86CPU, hyperv_features, 5913 HYPERV_FEAT_RESET, 0), 5914 DEFINE_PROP_BIT64("hv-vpindex", X86CPU, hyperv_features, 5915 HYPERV_FEAT_VPINDEX, 0), 5916 DEFINE_PROP_BIT64("hv-runtime", X86CPU, hyperv_features, 5917 HYPERV_FEAT_RUNTIME, 0), 5918 DEFINE_PROP_BIT64("hv-synic", X86CPU, hyperv_features, 5919 HYPERV_FEAT_SYNIC, 0), 5920 DEFINE_PROP_BIT64("hv-stimer", X86CPU, hyperv_features, 5921 HYPERV_FEAT_STIMER, 0), 5922 DEFINE_PROP_BIT64("hv-frequencies", X86CPU, hyperv_features, 5923 HYPERV_FEAT_FREQUENCIES, 0), 5924 DEFINE_PROP_BIT64("hv-reenlightenment", X86CPU, hyperv_features, 5925 HYPERV_FEAT_REENLIGHTENMENT, 0), 5926 DEFINE_PROP_BIT64("hv-tlbflush", X86CPU, hyperv_features, 5927 HYPERV_FEAT_TLBFLUSH, 0), 5928 DEFINE_PROP_BIT64("hv-evmcs", X86CPU, hyperv_features, 5929 HYPERV_FEAT_EVMCS, 0), 5930 DEFINE_PROP_BIT64("hv-ipi", X86CPU, hyperv_features, 5931 HYPERV_FEAT_IPI, 0), 5932 DEFINE_PROP_BIT64("hv-stimer-direct", X86CPU, hyperv_features, 5933 HYPERV_FEAT_STIMER_DIRECT, 0), 5934 DEFINE_PROP_BOOL("hv-passthrough", X86CPU, hyperv_passthrough, false), 5935 5936 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true), 5937 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false), 5938 DEFINE_PROP_BOOL("x-force-features", X86CPU, force_features, false), 5939 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true), 5940 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0), 5941 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false), 5942 DEFINE_PROP_UINT8("host-phys-bits-limit", X86CPU, host_phys_bits_limit, 0), 5943 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true), 5944 DEFINE_PROP_UINT32("level-func7", X86CPU, env.cpuid_level_func7, 5945 UINT32_MAX), 5946 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX), 5947 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX), 5948 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX), 5949 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0), 5950 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0), 5951 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0), 5952 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true), 5953 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor_id), 5954 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true), 5955 DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false), 5956 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true), 5957 DEFINE_PROP_BOOL("kvm-no-smi-migration", X86CPU, kvm_no_smi_migration, 5958 false), 5959 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true), 5960 DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true), 5961 DEFINE_PROP_BOOL("x-migrate-smi-count", X86CPU, migrate_smi_count, 5962 true), 5963 /* 5964 * lecacy_cache defaults to true unless the CPU model provides its 5965 * own cache information (see x86_cpu_load_def()). 5966 */ 5967 DEFINE_PROP_BOOL("legacy-cache", X86CPU, legacy_cache, true), 5968 5969 /* 5970 * From "Requirements for Implementing the Microsoft 5971 * Hypervisor Interface": 5972 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs 5973 * 5974 * "Starting with Windows Server 2012 and Windows 8, if 5975 * CPUID.40000005.EAX contains a value of -1, Windows assumes that 5976 * the hypervisor imposes no specific limit to the number of VPs. 5977 * In this case, Windows Server 2012 guest VMs may use more than 5978 * 64 VPs, up to the maximum supported number of processors applicable 5979 * to the specific Windows version being used." 5980 */ 5981 DEFINE_PROP_INT32("x-hv-max-vps", X86CPU, hv_max_vps, -1), 5982 DEFINE_PROP_BOOL("x-hv-synic-kvm-only", X86CPU, hyperv_synic_kvm_only, 5983 false), 5984 DEFINE_PROP_BOOL("x-intel-pt-auto-level", X86CPU, intel_pt_auto_level, 5985 true), 5986 DEFINE_PROP_END_OF_LIST() 5987 }; 5988 5989 static void x86_cpu_common_class_init(ObjectClass *oc, void *data) 5990 { 5991 X86CPUClass *xcc = X86_CPU_CLASS(oc); 5992 CPUClass *cc = CPU_CLASS(oc); 5993 DeviceClass *dc = DEVICE_CLASS(oc); 5994 5995 device_class_set_parent_realize(dc, x86_cpu_realizefn, 5996 &xcc->parent_realize); 5997 device_class_set_parent_unrealize(dc, x86_cpu_unrealizefn, 5998 &xcc->parent_unrealize); 5999 dc->props = x86_cpu_properties; 6000 6001 xcc->parent_reset = cc->reset; 6002 cc->reset = x86_cpu_reset; 6003 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP; 6004 6005 cc->class_by_name = x86_cpu_class_by_name; 6006 cc->parse_features = x86_cpu_parse_featurestr; 6007 cc->has_work = x86_cpu_has_work; 6008 #ifdef CONFIG_TCG 6009 cc->do_interrupt = x86_cpu_do_interrupt; 6010 cc->cpu_exec_interrupt = x86_cpu_exec_interrupt; 6011 #endif 6012 cc->dump_state = x86_cpu_dump_state; 6013 cc->get_crash_info = x86_cpu_get_crash_info; 6014 cc->set_pc = x86_cpu_set_pc; 6015 cc->synchronize_from_tb = x86_cpu_synchronize_from_tb; 6016 cc->gdb_read_register = x86_cpu_gdb_read_register; 6017 cc->gdb_write_register = x86_cpu_gdb_write_register; 6018 cc->get_arch_id = x86_cpu_get_arch_id; 6019 cc->get_paging_enabled = x86_cpu_get_paging_enabled; 6020 #ifndef CONFIG_USER_ONLY 6021 cc->asidx_from_attrs = x86_asidx_from_attrs; 6022 cc->get_memory_mapping = x86_cpu_get_memory_mapping; 6023 cc->get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug; 6024 cc->write_elf64_note = x86_cpu_write_elf64_note; 6025 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote; 6026 cc->write_elf32_note = x86_cpu_write_elf32_note; 6027 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote; 6028 cc->vmsd = &vmstate_x86_cpu; 6029 #endif 6030 cc->gdb_arch_name = x86_gdb_arch_name; 6031 #ifdef TARGET_X86_64 6032 cc->gdb_core_xml_file = "i386-64bit.xml"; 6033 cc->gdb_num_core_regs = 66; 6034 #else 6035 cc->gdb_core_xml_file = "i386-32bit.xml"; 6036 cc->gdb_num_core_regs = 50; 6037 #endif 6038 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) 6039 cc->debug_excp_handler = breakpoint_handler; 6040 #endif 6041 cc->cpu_exec_enter = x86_cpu_exec_enter; 6042 cc->cpu_exec_exit = x86_cpu_exec_exit; 6043 #ifdef CONFIG_TCG 6044 cc->tcg_initialize = tcg_x86_init; 6045 cc->tlb_fill = x86_cpu_tlb_fill; 6046 #endif 6047 cc->disas_set_info = x86_disas_set_info; 6048 6049 dc->user_creatable = true; 6050 } 6051 6052 static const TypeInfo x86_cpu_type_info = { 6053 .name = TYPE_X86_CPU, 6054 .parent = TYPE_CPU, 6055 .instance_size = sizeof(X86CPU), 6056 .instance_init = x86_cpu_initfn, 6057 .abstract = true, 6058 .class_size = sizeof(X86CPUClass), 6059 .class_init = x86_cpu_common_class_init, 6060 }; 6061 6062 6063 /* "base" CPU model, used by query-cpu-model-expansion */ 6064 static void x86_cpu_base_class_init(ObjectClass *oc, void *data) 6065 { 6066 X86CPUClass *xcc = X86_CPU_CLASS(oc); 6067 6068 xcc->static_model = true; 6069 xcc->migration_safe = true; 6070 xcc->model_description = "base CPU model type with no features enabled"; 6071 xcc->ordering = 8; 6072 } 6073 6074 static const TypeInfo x86_base_cpu_type_info = { 6075 .name = X86_CPU_TYPE_NAME("base"), 6076 .parent = TYPE_X86_CPU, 6077 .class_init = x86_cpu_base_class_init, 6078 }; 6079 6080 static void x86_cpu_register_types(void) 6081 { 6082 int i; 6083 6084 type_register_static(&x86_cpu_type_info); 6085 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) { 6086 x86_register_cpudef_types(&builtin_x86_defs[i]); 6087 } 6088 type_register_static(&max_x86_cpu_type_info); 6089 type_register_static(&x86_base_cpu_type_info); 6090 #if defined(CONFIG_KVM) || defined(CONFIG_HVF) 6091 type_register_static(&host_x86_cpu_type_info); 6092 #endif 6093 } 6094 6095 type_init(x86_cpu_register_types) 6096