1 /* 2 * i386 CPUID, CPU class, definitions, models 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/units.h" 22 #include "qemu/cutils.h" 23 #include "qemu/qemu-print.h" 24 #include "qemu/hw-version.h" 25 #include "cpu.h" 26 #include "tcg/helper-tcg.h" 27 #include "exec/translation-block.h" 28 #include "system/hvf.h" 29 #include "hvf/hvf-i386.h" 30 #include "kvm/kvm_i386.h" 31 #include "sev.h" 32 #include "qapi/error.h" 33 #include "qemu/error-report.h" 34 #include "qapi/qapi-visit-machine.h" 35 #include "standard-headers/asm-x86/kvm_para.h" 36 #include "hw/qdev-properties.h" 37 #include "hw/i386/topology.h" 38 #include "exec/watchpoint.h" 39 #ifndef CONFIG_USER_ONLY 40 #include "system/reset.h" 41 #include "qapi/qapi-commands-machine-target.h" 42 #include "system/address-spaces.h" 43 #include "hw/boards.h" 44 #include "hw/i386/sgx-epc.h" 45 #endif 46 #include "tcg/tcg-cpu.h" 47 48 #include "disas/capstone.h" 49 #include "cpu-internal.h" 50 51 static void x86_cpu_realizefn(DeviceState *dev, Error **errp); 52 static void x86_cpu_get_supported_cpuid(uint32_t func, uint32_t index, 53 uint32_t *eax, uint32_t *ebx, 54 uint32_t *ecx, uint32_t *edx); 55 56 /* Helpers for building CPUID[2] descriptors: */ 57 58 struct CPUID2CacheDescriptorInfo { 59 enum CacheType type; 60 int level; 61 int size; 62 int line_size; 63 int associativity; 64 }; 65 66 /* 67 * Known CPUID 2 cache descriptors. 68 * From Intel SDM Volume 2A, CPUID instruction 69 */ 70 struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = { 71 [0x06] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 8 * KiB, 72 .associativity = 4, .line_size = 32, }, 73 [0x08] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 16 * KiB, 74 .associativity = 4, .line_size = 32, }, 75 [0x09] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB, 76 .associativity = 4, .line_size = 64, }, 77 [0x0A] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB, 78 .associativity = 2, .line_size = 32, }, 79 [0x0C] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 80 .associativity = 4, .line_size = 32, }, 81 [0x0D] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 82 .associativity = 4, .line_size = 64, }, 83 [0x0E] = { .level = 1, .type = DATA_CACHE, .size = 24 * KiB, 84 .associativity = 6, .line_size = 64, }, 85 [0x1D] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB, 86 .associativity = 2, .line_size = 64, }, 87 [0x21] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 88 .associativity = 8, .line_size = 64, }, 89 /* lines per sector is not supported cpuid2_cache_descriptor(), 90 * so descriptors 0x22, 0x23 are not included 91 */ 92 [0x24] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 93 .associativity = 16, .line_size = 64, }, 94 /* lines per sector is not supported cpuid2_cache_descriptor(), 95 * so descriptors 0x25, 0x20 are not included 96 */ 97 [0x2C] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB, 98 .associativity = 8, .line_size = 64, }, 99 [0x30] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB, 100 .associativity = 8, .line_size = 64, }, 101 [0x41] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB, 102 .associativity = 4, .line_size = 32, }, 103 [0x42] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 104 .associativity = 4, .line_size = 32, }, 105 [0x43] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 106 .associativity = 4, .line_size = 32, }, 107 [0x44] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 108 .associativity = 4, .line_size = 32, }, 109 [0x45] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 110 .associativity = 4, .line_size = 32, }, 111 [0x46] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 112 .associativity = 4, .line_size = 64, }, 113 [0x47] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 114 .associativity = 8, .line_size = 64, }, 115 [0x48] = { .level = 2, .type = UNIFIED_CACHE, .size = 3 * MiB, 116 .associativity = 12, .line_size = 64, }, 117 /* Descriptor 0x49 depends on CPU family/model, so it is not included */ 118 [0x4A] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB, 119 .associativity = 12, .line_size = 64, }, 120 [0x4B] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 121 .associativity = 16, .line_size = 64, }, 122 [0x4C] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB, 123 .associativity = 12, .line_size = 64, }, 124 [0x4D] = { .level = 3, .type = UNIFIED_CACHE, .size = 16 * MiB, 125 .associativity = 16, .line_size = 64, }, 126 [0x4E] = { .level = 2, .type = UNIFIED_CACHE, .size = 6 * MiB, 127 .associativity = 24, .line_size = 64, }, 128 [0x60] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 129 .associativity = 8, .line_size = 64, }, 130 [0x66] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB, 131 .associativity = 4, .line_size = 64, }, 132 [0x67] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 133 .associativity = 4, .line_size = 64, }, 134 [0x68] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB, 135 .associativity = 4, .line_size = 64, }, 136 [0x78] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 137 .associativity = 4, .line_size = 64, }, 138 /* lines per sector is not supported cpuid2_cache_descriptor(), 139 * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included. 140 */ 141 [0x7D] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 142 .associativity = 8, .line_size = 64, }, 143 [0x7F] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 144 .associativity = 2, .line_size = 64, }, 145 [0x80] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 146 .associativity = 8, .line_size = 64, }, 147 [0x82] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 148 .associativity = 8, .line_size = 32, }, 149 [0x83] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 150 .associativity = 8, .line_size = 32, }, 151 [0x84] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 152 .associativity = 8, .line_size = 32, }, 153 [0x85] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 154 .associativity = 8, .line_size = 32, }, 155 [0x86] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 156 .associativity = 4, .line_size = 64, }, 157 [0x87] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 158 .associativity = 8, .line_size = 64, }, 159 [0xD0] = { .level = 3, .type = UNIFIED_CACHE, .size = 512 * KiB, 160 .associativity = 4, .line_size = 64, }, 161 [0xD1] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB, 162 .associativity = 4, .line_size = 64, }, 163 [0xD2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 164 .associativity = 4, .line_size = 64, }, 165 [0xD6] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB, 166 .associativity = 8, .line_size = 64, }, 167 [0xD7] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 168 .associativity = 8, .line_size = 64, }, 169 [0xD8] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 170 .associativity = 8, .line_size = 64, }, 171 [0xDC] = { .level = 3, .type = UNIFIED_CACHE, .size = 1.5 * MiB, 172 .associativity = 12, .line_size = 64, }, 173 [0xDD] = { .level = 3, .type = UNIFIED_CACHE, .size = 3 * MiB, 174 .associativity = 12, .line_size = 64, }, 175 [0xDE] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB, 176 .associativity = 12, .line_size = 64, }, 177 [0xE2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 178 .associativity = 16, .line_size = 64, }, 179 [0xE3] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 180 .associativity = 16, .line_size = 64, }, 181 [0xE4] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 182 .associativity = 16, .line_size = 64, }, 183 [0xEA] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB, 184 .associativity = 24, .line_size = 64, }, 185 [0xEB] = { .level = 3, .type = UNIFIED_CACHE, .size = 18 * MiB, 186 .associativity = 24, .line_size = 64, }, 187 [0xEC] = { .level = 3, .type = UNIFIED_CACHE, .size = 24 * MiB, 188 .associativity = 24, .line_size = 64, }, 189 }; 190 191 /* 192 * "CPUID leaf 2 does not report cache descriptor information, 193 * use CPUID leaf 4 to query cache parameters" 194 */ 195 #define CACHE_DESCRIPTOR_UNAVAILABLE 0xFF 196 197 /* 198 * Return a CPUID 2 cache descriptor for a given cache. 199 * If no known descriptor is found, return CACHE_DESCRIPTOR_UNAVAILABLE 200 */ 201 static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache) 202 { 203 int i; 204 205 assert(cache->size > 0); 206 assert(cache->level > 0); 207 assert(cache->line_size > 0); 208 assert(cache->associativity > 0); 209 for (i = 0; i < ARRAY_SIZE(cpuid2_cache_descriptors); i++) { 210 struct CPUID2CacheDescriptorInfo *d = &cpuid2_cache_descriptors[i]; 211 if (d->level == cache->level && d->type == cache->type && 212 d->size == cache->size && d->line_size == cache->line_size && 213 d->associativity == cache->associativity) { 214 return i; 215 } 216 } 217 218 return CACHE_DESCRIPTOR_UNAVAILABLE; 219 } 220 221 /* CPUID Leaf 4 constants: */ 222 223 /* EAX: */ 224 #define CACHE_TYPE_D 1 225 #define CACHE_TYPE_I 2 226 #define CACHE_TYPE_UNIFIED 3 227 228 #define CACHE_LEVEL(l) (l << 5) 229 230 #define CACHE_SELF_INIT_LEVEL (1 << 8) 231 232 /* EDX: */ 233 #define CACHE_NO_INVD_SHARING (1 << 0) 234 #define CACHE_INCLUSIVE (1 << 1) 235 #define CACHE_COMPLEX_IDX (1 << 2) 236 237 /* Encode CacheType for CPUID[4].EAX */ 238 #define CACHE_TYPE(t) (((t) == DATA_CACHE) ? CACHE_TYPE_D : \ 239 ((t) == INSTRUCTION_CACHE) ? CACHE_TYPE_I : \ 240 ((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \ 241 0 /* Invalid value */) 242 243 static uint32_t max_thread_ids_for_cache(X86CPUTopoInfo *topo_info, 244 enum CpuTopologyLevel share_level) 245 { 246 uint32_t num_ids = 0; 247 248 switch (share_level) { 249 case CPU_TOPOLOGY_LEVEL_CORE: 250 num_ids = 1 << apicid_core_offset(topo_info); 251 break; 252 case CPU_TOPOLOGY_LEVEL_MODULE: 253 num_ids = 1 << apicid_module_offset(topo_info); 254 break; 255 case CPU_TOPOLOGY_LEVEL_DIE: 256 num_ids = 1 << apicid_die_offset(topo_info); 257 break; 258 case CPU_TOPOLOGY_LEVEL_SOCKET: 259 num_ids = 1 << apicid_pkg_offset(topo_info); 260 break; 261 default: 262 /* 263 * Currently there is no use case for THREAD, so use 264 * assert directly to facilitate debugging. 265 */ 266 g_assert_not_reached(); 267 } 268 269 return num_ids - 1; 270 } 271 272 static uint32_t max_core_ids_in_package(X86CPUTopoInfo *topo_info) 273 { 274 uint32_t num_cores = 1 << (apicid_pkg_offset(topo_info) - 275 apicid_core_offset(topo_info)); 276 return num_cores - 1; 277 } 278 279 /* Encode cache info for CPUID[4] */ 280 static void encode_cache_cpuid4(CPUCacheInfo *cache, 281 X86CPUTopoInfo *topo_info, 282 uint32_t *eax, uint32_t *ebx, 283 uint32_t *ecx, uint32_t *edx) 284 { 285 assert(cache->size == cache->line_size * cache->associativity * 286 cache->partitions * cache->sets); 287 288 *eax = CACHE_TYPE(cache->type) | 289 CACHE_LEVEL(cache->level) | 290 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) | 291 (max_core_ids_in_package(topo_info) << 26) | 292 (max_thread_ids_for_cache(topo_info, cache->share_level) << 14); 293 294 assert(cache->line_size > 0); 295 assert(cache->partitions > 0); 296 assert(cache->associativity > 0); 297 /* We don't implement fully-associative caches */ 298 assert(cache->associativity < cache->sets); 299 *ebx = (cache->line_size - 1) | 300 ((cache->partitions - 1) << 12) | 301 ((cache->associativity - 1) << 22); 302 303 assert(cache->sets > 0); 304 *ecx = cache->sets - 1; 305 306 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) | 307 (cache->inclusive ? CACHE_INCLUSIVE : 0) | 308 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); 309 } 310 311 static uint32_t num_threads_by_topo_level(X86CPUTopoInfo *topo_info, 312 enum CpuTopologyLevel topo_level) 313 { 314 switch (topo_level) { 315 case CPU_TOPOLOGY_LEVEL_THREAD: 316 return 1; 317 case CPU_TOPOLOGY_LEVEL_CORE: 318 return topo_info->threads_per_core; 319 case CPU_TOPOLOGY_LEVEL_MODULE: 320 return x86_threads_per_module(topo_info); 321 case CPU_TOPOLOGY_LEVEL_DIE: 322 return x86_threads_per_die(topo_info); 323 case CPU_TOPOLOGY_LEVEL_SOCKET: 324 return x86_threads_per_pkg(topo_info); 325 default: 326 g_assert_not_reached(); 327 } 328 return 0; 329 } 330 331 static uint32_t apicid_offset_by_topo_level(X86CPUTopoInfo *topo_info, 332 enum CpuTopologyLevel topo_level) 333 { 334 switch (topo_level) { 335 case CPU_TOPOLOGY_LEVEL_THREAD: 336 return 0; 337 case CPU_TOPOLOGY_LEVEL_CORE: 338 return apicid_core_offset(topo_info); 339 case CPU_TOPOLOGY_LEVEL_MODULE: 340 return apicid_module_offset(topo_info); 341 case CPU_TOPOLOGY_LEVEL_DIE: 342 return apicid_die_offset(topo_info); 343 case CPU_TOPOLOGY_LEVEL_SOCKET: 344 return apicid_pkg_offset(topo_info); 345 default: 346 g_assert_not_reached(); 347 } 348 return 0; 349 } 350 351 static uint32_t cpuid1f_topo_type(enum CpuTopologyLevel topo_level) 352 { 353 switch (topo_level) { 354 case CPU_TOPOLOGY_LEVEL_INVALID: 355 return CPUID_1F_ECX_TOPO_LEVEL_INVALID; 356 case CPU_TOPOLOGY_LEVEL_THREAD: 357 return CPUID_1F_ECX_TOPO_LEVEL_SMT; 358 case CPU_TOPOLOGY_LEVEL_CORE: 359 return CPUID_1F_ECX_TOPO_LEVEL_CORE; 360 case CPU_TOPOLOGY_LEVEL_MODULE: 361 return CPUID_1F_ECX_TOPO_LEVEL_MODULE; 362 case CPU_TOPOLOGY_LEVEL_DIE: 363 return CPUID_1F_ECX_TOPO_LEVEL_DIE; 364 default: 365 /* Other types are not supported in QEMU. */ 366 g_assert_not_reached(); 367 } 368 return 0; 369 } 370 371 static void encode_topo_cpuid1f(CPUX86State *env, uint32_t count, 372 X86CPUTopoInfo *topo_info, 373 uint32_t *eax, uint32_t *ebx, 374 uint32_t *ecx, uint32_t *edx) 375 { 376 X86CPU *cpu = env_archcpu(env); 377 unsigned long level, base_level, next_level; 378 uint32_t num_threads_next_level, offset_next_level; 379 380 assert(count <= CPU_TOPOLOGY_LEVEL_SOCKET); 381 382 /* 383 * Find the No.(count + 1) topology level in avail_cpu_topo bitmap. 384 * The search starts from bit 0 (CPU_TOPOLOGY_LEVEL_THREAD). 385 */ 386 level = CPU_TOPOLOGY_LEVEL_THREAD; 387 base_level = level; 388 for (int i = 0; i <= count; i++) { 389 level = find_next_bit(env->avail_cpu_topo, 390 CPU_TOPOLOGY_LEVEL_SOCKET, 391 base_level); 392 393 /* 394 * CPUID[0x1f] doesn't explicitly encode the package level, 395 * and it just encodes the invalid level (all fields are 0) 396 * into the last subleaf of 0x1f. 397 */ 398 if (level == CPU_TOPOLOGY_LEVEL_SOCKET) { 399 level = CPU_TOPOLOGY_LEVEL_INVALID; 400 break; 401 } 402 /* Search the next level. */ 403 base_level = level + 1; 404 } 405 406 if (level == CPU_TOPOLOGY_LEVEL_INVALID) { 407 num_threads_next_level = 0; 408 offset_next_level = 0; 409 } else { 410 next_level = find_next_bit(env->avail_cpu_topo, 411 CPU_TOPOLOGY_LEVEL_SOCKET, 412 level + 1); 413 num_threads_next_level = num_threads_by_topo_level(topo_info, 414 next_level); 415 offset_next_level = apicid_offset_by_topo_level(topo_info, 416 next_level); 417 } 418 419 *eax = offset_next_level; 420 /* The count (bits 15-00) doesn't need to be reliable. */ 421 *ebx = num_threads_next_level & 0xffff; 422 *ecx = (count & 0xff) | (cpuid1f_topo_type(level) << 8); 423 *edx = cpu->apic_id; 424 425 assert(!(*eax & ~0x1f)); 426 } 427 428 /* Encode cache info for CPUID[0x80000005].ECX or CPUID[0x80000005].EDX */ 429 static uint32_t encode_cache_cpuid80000005(CPUCacheInfo *cache) 430 { 431 assert(cache->size % 1024 == 0); 432 assert(cache->lines_per_tag > 0); 433 assert(cache->associativity > 0); 434 assert(cache->line_size > 0); 435 return ((cache->size / 1024) << 24) | (cache->associativity << 16) | 436 (cache->lines_per_tag << 8) | (cache->line_size); 437 } 438 439 #define ASSOC_FULL 0xFF 440 441 /* AMD associativity encoding used on CPUID Leaf 0x80000006: */ 442 #define AMD_ENC_ASSOC(a) (a <= 1 ? a : \ 443 a == 2 ? 0x2 : \ 444 a == 4 ? 0x4 : \ 445 a == 8 ? 0x6 : \ 446 a == 16 ? 0x8 : \ 447 a == 32 ? 0xA : \ 448 a == 48 ? 0xB : \ 449 a == 64 ? 0xC : \ 450 a == 96 ? 0xD : \ 451 a == 128 ? 0xE : \ 452 a == ASSOC_FULL ? 0xF : \ 453 0 /* invalid value */) 454 455 /* 456 * Encode cache info for CPUID[0x80000006].ECX and CPUID[0x80000006].EDX 457 * @l3 can be NULL. 458 */ 459 static void encode_cache_cpuid80000006(CPUCacheInfo *l2, 460 CPUCacheInfo *l3, 461 uint32_t *ecx, uint32_t *edx) 462 { 463 assert(l2->size % 1024 == 0); 464 assert(l2->associativity > 0); 465 assert(l2->lines_per_tag > 0); 466 assert(l2->line_size > 0); 467 *ecx = ((l2->size / 1024) << 16) | 468 (AMD_ENC_ASSOC(l2->associativity) << 12) | 469 (l2->lines_per_tag << 8) | (l2->line_size); 470 471 if (l3) { 472 assert(l3->size % (512 * 1024) == 0); 473 assert(l3->associativity > 0); 474 assert(l3->lines_per_tag > 0); 475 assert(l3->line_size > 0); 476 *edx = ((l3->size / (512 * 1024)) << 18) | 477 (AMD_ENC_ASSOC(l3->associativity) << 12) | 478 (l3->lines_per_tag << 8) | (l3->line_size); 479 } else { 480 *edx = 0; 481 } 482 } 483 484 /* Encode cache info for CPUID[8000001D] */ 485 static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, 486 X86CPUTopoInfo *topo_info, 487 uint32_t *eax, uint32_t *ebx, 488 uint32_t *ecx, uint32_t *edx) 489 { 490 assert(cache->size == cache->line_size * cache->associativity * 491 cache->partitions * cache->sets); 492 493 *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) | 494 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0); 495 *eax |= max_thread_ids_for_cache(topo_info, cache->share_level) << 14; 496 497 assert(cache->line_size > 0); 498 assert(cache->partitions > 0); 499 assert(cache->associativity > 0); 500 /* We don't implement fully-associative caches */ 501 assert(cache->associativity < cache->sets); 502 *ebx = (cache->line_size - 1) | 503 ((cache->partitions - 1) << 12) | 504 ((cache->associativity - 1) << 22); 505 506 assert(cache->sets > 0); 507 *ecx = cache->sets - 1; 508 509 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) | 510 (cache->inclusive ? CACHE_INCLUSIVE : 0) | 511 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); 512 } 513 514 /* Encode cache info for CPUID[8000001E] */ 515 static void encode_topo_cpuid8000001e(X86CPU *cpu, X86CPUTopoInfo *topo_info, 516 uint32_t *eax, uint32_t *ebx, 517 uint32_t *ecx, uint32_t *edx) 518 { 519 X86CPUTopoIDs topo_ids; 520 521 x86_topo_ids_from_apicid(cpu->apic_id, topo_info, &topo_ids); 522 523 *eax = cpu->apic_id; 524 525 /* 526 * CPUID_Fn8000001E_EBX [Core Identifiers] (CoreId) 527 * Read-only. Reset: 0000_XXXXh. 528 * See Core::X86::Cpuid::ExtApicId. 529 * Core::X86::Cpuid::CoreId_lthree[1:0]_core[3:0]_thread[1:0]; 530 * Bits Description 531 * 31:16 Reserved. 532 * 15:8 ThreadsPerCore: threads per core. Read-only. Reset: XXh. 533 * The number of threads per core is ThreadsPerCore+1. 534 * 7:0 CoreId: core ID. Read-only. Reset: XXh. 535 * 536 * NOTE: CoreId is already part of apic_id. Just use it. We can 537 * use all the 8 bits to represent the core_id here. 538 */ 539 *ebx = ((topo_info->threads_per_core - 1) << 8) | (topo_ids.core_id & 0xFF); 540 541 /* 542 * CPUID_Fn8000001E_ECX [Node Identifiers] (NodeId) 543 * Read-only. Reset: 0000_0XXXh. 544 * Core::X86::Cpuid::NodeId_lthree[1:0]_core[3:0]_thread[1:0]; 545 * Bits Description 546 * 31:11 Reserved. 547 * 10:8 NodesPerProcessor: Node per processor. Read-only. Reset: XXXb. 548 * ValidValues: 549 * Value Description 550 * 0h 1 node per processor. 551 * 7h-1h Reserved. 552 * 7:0 NodeId: Node ID. Read-only. Reset: XXh. 553 * 554 * NOTE: Hardware reserves 3 bits for number of nodes per processor. 555 * But users can create more nodes than the actual hardware can 556 * support. To genaralize we can use all the upper 8 bits for nodes. 557 * NodeId is combination of node and socket_id which is already decoded 558 * in apic_id. Just use it by shifting. 559 */ 560 if (cpu->legacy_multi_node) { 561 *ecx = ((topo_info->dies_per_pkg - 1) << 8) | 562 ((cpu->apic_id >> apicid_die_offset(topo_info)) & 0xFF); 563 } else { 564 *ecx = (cpu->apic_id >> apicid_pkg_offset(topo_info)) & 0xFF; 565 } 566 567 *edx = 0; 568 } 569 570 /* 571 * Definitions of the hardcoded cache entries we expose: 572 * These are legacy cache values. If there is a need to change any 573 * of these values please use builtin_x86_defs 574 */ 575 576 /* L1 data cache: */ 577 static CPUCacheInfo legacy_l1d_cache = { 578 .type = DATA_CACHE, 579 .level = 1, 580 .size = 32 * KiB, 581 .self_init = 1, 582 .line_size = 64, 583 .associativity = 8, 584 .sets = 64, 585 .partitions = 1, 586 .no_invd_sharing = true, 587 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 588 }; 589 590 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ 591 static CPUCacheInfo legacy_l1d_cache_amd = { 592 .type = DATA_CACHE, 593 .level = 1, 594 .size = 64 * KiB, 595 .self_init = 1, 596 .line_size = 64, 597 .associativity = 2, 598 .sets = 512, 599 .partitions = 1, 600 .lines_per_tag = 1, 601 .no_invd_sharing = true, 602 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 603 }; 604 605 /* L1 instruction cache: */ 606 static CPUCacheInfo legacy_l1i_cache = { 607 .type = INSTRUCTION_CACHE, 608 .level = 1, 609 .size = 32 * KiB, 610 .self_init = 1, 611 .line_size = 64, 612 .associativity = 8, 613 .sets = 64, 614 .partitions = 1, 615 .no_invd_sharing = true, 616 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 617 }; 618 619 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ 620 static CPUCacheInfo legacy_l1i_cache_amd = { 621 .type = INSTRUCTION_CACHE, 622 .level = 1, 623 .size = 64 * KiB, 624 .self_init = 1, 625 .line_size = 64, 626 .associativity = 2, 627 .sets = 512, 628 .partitions = 1, 629 .lines_per_tag = 1, 630 .no_invd_sharing = true, 631 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 632 }; 633 634 /* Level 2 unified cache: */ 635 static CPUCacheInfo legacy_l2_cache = { 636 .type = UNIFIED_CACHE, 637 .level = 2, 638 .size = 4 * MiB, 639 .self_init = 1, 640 .line_size = 64, 641 .associativity = 16, 642 .sets = 4096, 643 .partitions = 1, 644 .no_invd_sharing = true, 645 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 646 }; 647 648 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */ 649 static CPUCacheInfo legacy_l2_cache_cpuid2 = { 650 .type = UNIFIED_CACHE, 651 .level = 2, 652 .size = 2 * MiB, 653 .line_size = 64, 654 .associativity = 8, 655 .share_level = CPU_TOPOLOGY_LEVEL_INVALID, 656 }; 657 658 659 /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */ 660 static CPUCacheInfo legacy_l2_cache_amd = { 661 .type = UNIFIED_CACHE, 662 .level = 2, 663 .size = 512 * KiB, 664 .line_size = 64, 665 .lines_per_tag = 1, 666 .associativity = 16, 667 .sets = 512, 668 .partitions = 1, 669 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 670 }; 671 672 /* Level 3 unified cache: */ 673 static CPUCacheInfo legacy_l3_cache = { 674 .type = UNIFIED_CACHE, 675 .level = 3, 676 .size = 16 * MiB, 677 .line_size = 64, 678 .associativity = 16, 679 .sets = 16384, 680 .partitions = 1, 681 .lines_per_tag = 1, 682 .self_init = true, 683 .inclusive = true, 684 .complex_indexing = true, 685 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 686 }; 687 688 /* TLB definitions: */ 689 690 #define L1_DTLB_2M_ASSOC 1 691 #define L1_DTLB_2M_ENTRIES 255 692 #define L1_DTLB_4K_ASSOC 1 693 #define L1_DTLB_4K_ENTRIES 255 694 695 #define L1_ITLB_2M_ASSOC 1 696 #define L1_ITLB_2M_ENTRIES 255 697 #define L1_ITLB_4K_ASSOC 1 698 #define L1_ITLB_4K_ENTRIES 255 699 700 #define L2_DTLB_2M_ASSOC 0 /* disabled */ 701 #define L2_DTLB_2M_ENTRIES 0 /* disabled */ 702 #define L2_DTLB_4K_ASSOC 4 703 #define L2_DTLB_4K_ENTRIES 512 704 705 #define L2_ITLB_2M_ASSOC 0 /* disabled */ 706 #define L2_ITLB_2M_ENTRIES 0 /* disabled */ 707 #define L2_ITLB_4K_ASSOC 4 708 #define L2_ITLB_4K_ENTRIES 512 709 710 /* CPUID Leaf 0x14 constants: */ 711 #define INTEL_PT_MAX_SUBLEAF 0x1 712 /* 713 * bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MATCH 714 * MSR can be accessed; 715 * bit[01]: Support Configurable PSB and Cycle-Accurate Mode; 716 * bit[02]: Support IP Filtering, TraceStop filtering, and preservation 717 * of Intel PT MSRs across warm reset; 718 * bit[03]: Support MTC timing packet and suppression of COFI-based packets; 719 */ 720 #define INTEL_PT_MINIMAL_EBX 0xf 721 /* 722 * bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 and 723 * IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be 724 * accessed; 725 * bit[01]: ToPA tables can hold any number of output entries, up to the 726 * maximum allowed by the MaskOrTableOffset field of 727 * IA32_RTIT_OUTPUT_MASK_PTRS; 728 * bit[02]: Support Single-Range Output scheme; 729 */ 730 #define INTEL_PT_MINIMAL_ECX 0x7 731 /* generated packets which contain IP payloads have LIP values */ 732 #define INTEL_PT_IP_LIP (1 << 31) 733 #define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */ 734 #define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3 735 #define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */ 736 #define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */ 737 #define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */ 738 739 /* CPUID Leaf 0x1D constants: */ 740 #define INTEL_AMX_TILE_MAX_SUBLEAF 0x1 741 #define INTEL_AMX_TOTAL_TILE_BYTES 0x2000 742 #define INTEL_AMX_BYTES_PER_TILE 0x400 743 #define INTEL_AMX_BYTES_PER_ROW 0x40 744 #define INTEL_AMX_TILE_MAX_NAMES 0x8 745 #define INTEL_AMX_TILE_MAX_ROWS 0x10 746 747 /* CPUID Leaf 0x1E constants: */ 748 #define INTEL_AMX_TMUL_MAX_K 0x10 749 #define INTEL_AMX_TMUL_MAX_N 0x40 750 751 void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1, 752 uint32_t vendor2, uint32_t vendor3) 753 { 754 int i; 755 for (i = 0; i < 4; i++) { 756 dst[i] = vendor1 >> (8 * i); 757 dst[i + 4] = vendor2 >> (8 * i); 758 dst[i + 8] = vendor3 >> (8 * i); 759 } 760 dst[CPUID_VENDOR_SZ] = '\0'; 761 } 762 763 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE) 764 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \ 765 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC) 766 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \ 767 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ 768 CPUID_PSE36 | CPUID_FXSR) 769 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE) 770 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \ 771 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \ 772 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \ 773 CPUID_PAE | CPUID_SEP | CPUID_APIC) 774 775 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \ 776 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \ 777 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ 778 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \ 779 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE) 780 /* partly implemented: 781 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */ 782 /* missing: 783 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */ 784 785 /* 786 * Kernel-only features that can be shown to usermode programs even if 787 * they aren't actually supported by TCG, because qemu-user only runs 788 * in CPL=3; remove them if they are ever implemented for system emulation. 789 */ 790 #if defined CONFIG_USER_ONLY 791 #define CPUID_EXT_KERNEL_FEATURES \ 792 (CPUID_EXT_PCID | CPUID_EXT_TSC_DEADLINE_TIMER) 793 #else 794 #define CPUID_EXT_KERNEL_FEATURES 0 795 #endif 796 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \ 797 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \ 798 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \ 799 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \ 800 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR | \ 801 CPUID_EXT_RDRAND | CPUID_EXT_AVX | CPUID_EXT_F16C | \ 802 CPUID_EXT_FMA | CPUID_EXT_X2APIC | CPUID_EXT_KERNEL_FEATURES) 803 /* missing: 804 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX, 805 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, 806 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA, 807 CPUID_EXT_TSC_DEADLINE_TIMER 808 */ 809 810 #ifdef TARGET_X86_64 811 #define TCG_EXT2_X86_64_FEATURES CPUID_EXT2_LM 812 #else 813 #define TCG_EXT2_X86_64_FEATURES 0 814 #endif 815 816 /* 817 * CPUID_*_KERNEL_FEATURES denotes bits and features that are not usable 818 * in usermode or by 32-bit programs. Those are added to supported 819 * TCG features unconditionally in user-mode emulation mode. This may 820 * indeed seem strange or incorrect, but it works because code running 821 * under usermode emulation cannot access them. 822 * 823 * Even for long mode, qemu-i386 is not running "a userspace program on a 824 * 32-bit CPU"; it's running "a userspace program with a 32-bit code segment" 825 * and therefore using the 32-bit ABI; the CPU itself might be 64-bit 826 * but again the difference is only visible in kernel mode. 827 */ 828 #if defined CONFIG_LINUX_USER 829 #define CPUID_EXT2_KERNEL_FEATURES (CPUID_EXT2_LM | CPUID_EXT2_FFXSR) 830 #elif defined CONFIG_USER_ONLY 831 /* FIXME: Long mode not yet supported for i386 bsd-user */ 832 #define CPUID_EXT2_KERNEL_FEATURES CPUID_EXT2_FFXSR 833 #else 834 #define CPUID_EXT2_KERNEL_FEATURES 0 835 #endif 836 837 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \ 838 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \ 839 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \ 840 CPUID_EXT2_SYSCALL | TCG_EXT2_X86_64_FEATURES | \ 841 CPUID_EXT2_KERNEL_FEATURES) 842 843 #if defined CONFIG_USER_ONLY 844 #define CPUID_EXT3_KERNEL_FEATURES CPUID_EXT3_OSVW 845 #else 846 #define CPUID_EXT3_KERNEL_FEATURES 0 847 #endif 848 849 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \ 850 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A | \ 851 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_KERNEL_FEATURES) 852 853 #define TCG_EXT4_FEATURES 0 854 855 #if defined CONFIG_USER_ONLY 856 #define CPUID_SVM_KERNEL_FEATURES (CPUID_SVM_NRIPSAVE | CPUID_SVM_VNMI) 857 #else 858 #define CPUID_SVM_KERNEL_FEATURES 0 859 #endif 860 #define TCG_SVM_FEATURES (CPUID_SVM_NPT | CPUID_SVM_VGIF | \ 861 CPUID_SVM_SVME_ADDR_CHK | CPUID_SVM_KERNEL_FEATURES) 862 863 #define TCG_KVM_FEATURES 0 864 865 #if defined CONFIG_USER_ONLY 866 #define CPUID_7_0_EBX_KERNEL_FEATURES CPUID_7_0_EBX_INVPCID 867 #else 868 #define CPUID_7_0_EBX_KERNEL_FEATURES 0 869 #endif 870 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \ 871 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \ 872 CPUID_7_0_EBX_CLFLUSHOPT | \ 873 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \ 874 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_RDSEED | \ 875 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_KERNEL_FEATURES) 876 /* missing: 877 CPUID_7_0_EBX_HLE 878 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM */ 879 880 #if !defined CONFIG_USER_ONLY || defined CONFIG_LINUX 881 #define TCG_7_0_ECX_RDPID CPUID_7_0_ECX_RDPID 882 #else 883 #define TCG_7_0_ECX_RDPID 0 884 #endif 885 #define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | \ 886 /* CPUID_7_0_ECX_OSPKE is dynamic */ \ 887 CPUID_7_0_ECX_LA57 | CPUID_7_0_ECX_PKS | CPUID_7_0_ECX_VAES | \ 888 TCG_7_0_ECX_RDPID) 889 890 #if defined CONFIG_USER_ONLY 891 #define CPUID_7_0_EDX_KERNEL_FEATURES (CPUID_7_0_EDX_SPEC_CTRL | \ 892 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD) 893 #else 894 #define CPUID_7_0_EDX_KERNEL_FEATURES 0 895 #endif 896 #define TCG_7_0_EDX_FEATURES (CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_KERNEL_FEATURES) 897 898 #define TCG_7_1_EAX_FEATURES (CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | \ 899 CPUID_7_1_EAX_FSRC | CPUID_7_1_EAX_CMPCCXADD) 900 #define TCG_7_1_EDX_FEATURES 0 901 #define TCG_7_2_EDX_FEATURES 0 902 #define TCG_APM_FEATURES 0 903 #define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT 904 #define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1) 905 /* missing: 906 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */ 907 #define TCG_14_0_ECX_FEATURES 0 908 #define TCG_SGX_12_0_EAX_FEATURES 0 909 #define TCG_SGX_12_0_EBX_FEATURES 0 910 #define TCG_SGX_12_1_EAX_FEATURES 0 911 #define TCG_24_0_EBX_FEATURES 0 912 913 #if defined CONFIG_USER_ONLY 914 #define CPUID_8000_0008_EBX_KERNEL_FEATURES (CPUID_8000_0008_EBX_IBPB | \ 915 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | \ 916 CPUID_8000_0008_EBX_STIBP_ALWAYS_ON | CPUID_8000_0008_EBX_AMD_SSBD | \ 917 CPUID_8000_0008_EBX_AMD_PSFD) 918 #else 919 #define CPUID_8000_0008_EBX_KERNEL_FEATURES 0 920 #endif 921 922 #define TCG_8000_0008_EBX (CPUID_8000_0008_EBX_XSAVEERPTR | \ 923 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_KERNEL_FEATURES) 924 925 #if defined CONFIG_USER_ONLY 926 #define CPUID_8000_0021_EAX_KERNEL_FEATURES CPUID_8000_0021_EAX_AUTO_IBRS 927 #else 928 #define CPUID_8000_0021_EAX_KERNEL_FEATURES 0 929 #endif 930 931 #define TCG_8000_0021_EAX_FEATURES ( \ 932 CPUID_8000_0021_EAX_NO_NESTED_DATA_BP | \ 933 CPUID_8000_0021_EAX_NULL_SEL_CLR_BASE | \ 934 CPUID_8000_0021_EAX_KERNEL_FEATURES) 935 936 FeatureWordInfo feature_word_info[FEATURE_WORDS] = { 937 [FEAT_1_EDX] = { 938 .type = CPUID_FEATURE_WORD, 939 .feat_names = { 940 "fpu", "vme", "de", "pse", 941 "tsc", "msr", "pae", "mce", 942 "cx8", "apic", NULL, "sep", 943 "mtrr", "pge", "mca", "cmov", 944 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */, 945 NULL, "ds" /* Intel dts */, "acpi", "mmx", 946 "fxsr", "sse", "sse2", "ss", 947 "ht" /* Intel htt */, "tm", "ia64", "pbe", 948 }, 949 .cpuid = {.eax = 1, .reg = R_EDX, }, 950 .tcg_features = TCG_FEATURES, 951 .no_autoenable_flags = CPUID_HT, 952 }, 953 [FEAT_1_ECX] = { 954 .type = CPUID_FEATURE_WORD, 955 .feat_names = { 956 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor", 957 "ds-cpl", "vmx", "smx", "est", 958 "tm2", "ssse3", "cid", NULL, 959 "fma", "cx16", "xtpr", "pdcm", 960 NULL, "pcid", "dca", "sse4.1", 961 "sse4.2", "x2apic", "movbe", "popcnt", 962 "tsc-deadline", "aes", "xsave", NULL /* osxsave */, 963 "avx", "f16c", "rdrand", "hypervisor", 964 }, 965 .cpuid = { .eax = 1, .reg = R_ECX, }, 966 .tcg_features = TCG_EXT_FEATURES, 967 }, 968 /* Feature names that are already defined on feature_name[] but 969 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their 970 * names on feat_names below. They are copied automatically 971 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD. 972 */ 973 [FEAT_8000_0001_EDX] = { 974 .type = CPUID_FEATURE_WORD, 975 .feat_names = { 976 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */, 977 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */, 978 NULL /* cx8 */, NULL /* apic */, NULL, "syscall", 979 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */, 980 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */, 981 "nx", NULL, "mmxext", NULL /* mmx */, 982 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp", 983 NULL, "lm", "3dnowext", "3dnow", 984 }, 985 .cpuid = { .eax = 0x80000001, .reg = R_EDX, }, 986 .tcg_features = TCG_EXT2_FEATURES, 987 }, 988 [FEAT_8000_0001_ECX] = { 989 .type = CPUID_FEATURE_WORD, 990 .feat_names = { 991 "lahf-lm", "cmp-legacy", "svm", "extapic", 992 "cr8legacy", "abm", "sse4a", "misalignsse", 993 "3dnowprefetch", "osvw", "ibs", "xop", 994 "skinit", "wdt", NULL, "lwp", 995 "fma4", "tce", NULL, "nodeid-msr", 996 NULL, "tbm", "topoext", "perfctr-core", 997 "perfctr-nb", NULL, NULL, NULL, 998 NULL, NULL, NULL, NULL, 999 }, 1000 .cpuid = { .eax = 0x80000001, .reg = R_ECX, }, 1001 .tcg_features = TCG_EXT3_FEATURES, 1002 /* 1003 * TOPOEXT is always allowed but can't be enabled blindly by 1004 * "-cpu host", as it requires consistent cache topology info 1005 * to be provided so it doesn't confuse guests. 1006 */ 1007 .no_autoenable_flags = CPUID_EXT3_TOPOEXT, 1008 }, 1009 [FEAT_C000_0001_EDX] = { 1010 .type = CPUID_FEATURE_WORD, 1011 .feat_names = { 1012 NULL, NULL, "xstore", "xstore-en", 1013 NULL, NULL, "xcrypt", "xcrypt-en", 1014 "ace2", "ace2-en", "phe", "phe-en", 1015 "pmm", "pmm-en", NULL, NULL, 1016 NULL, NULL, NULL, NULL, 1017 NULL, NULL, NULL, NULL, 1018 NULL, NULL, NULL, NULL, 1019 NULL, NULL, NULL, NULL, 1020 }, 1021 .cpuid = { .eax = 0xC0000001, .reg = R_EDX, }, 1022 .tcg_features = TCG_EXT4_FEATURES, 1023 }, 1024 [FEAT_KVM] = { 1025 .type = CPUID_FEATURE_WORD, 1026 .feat_names = { 1027 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock", 1028 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt", 1029 NULL, "kvm-pv-tlb-flush", "kvm-asyncpf-vmexit", "kvm-pv-ipi", 1030 "kvm-poll-control", "kvm-pv-sched-yield", "kvm-asyncpf-int", "kvm-msi-ext-dest-id", 1031 NULL, NULL, NULL, NULL, 1032 NULL, NULL, NULL, NULL, 1033 "kvmclock-stable-bit", NULL, NULL, NULL, 1034 NULL, NULL, NULL, NULL, 1035 }, 1036 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EAX, }, 1037 .tcg_features = TCG_KVM_FEATURES, 1038 }, 1039 [FEAT_KVM_HINTS] = { 1040 .type = CPUID_FEATURE_WORD, 1041 .feat_names = { 1042 "kvm-hint-dedicated", NULL, NULL, NULL, 1043 NULL, NULL, NULL, NULL, 1044 NULL, NULL, NULL, NULL, 1045 NULL, NULL, NULL, NULL, 1046 NULL, NULL, NULL, NULL, 1047 NULL, NULL, NULL, NULL, 1048 NULL, NULL, NULL, NULL, 1049 NULL, NULL, NULL, NULL, 1050 }, 1051 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EDX, }, 1052 .tcg_features = TCG_KVM_FEATURES, 1053 /* 1054 * KVM hints aren't auto-enabled by -cpu host, they need to be 1055 * explicitly enabled in the command-line. 1056 */ 1057 .no_autoenable_flags = ~0U, 1058 }, 1059 [FEAT_SVM] = { 1060 .type = CPUID_FEATURE_WORD, 1061 .feat_names = { 1062 "npt", "lbrv", "svm-lock", "nrip-save", 1063 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists", 1064 NULL, NULL, "pause-filter", NULL, 1065 "pfthreshold", "avic", NULL, "v-vmsave-vmload", 1066 "vgif", NULL, NULL, NULL, 1067 NULL, NULL, NULL, NULL, 1068 NULL, "vnmi", NULL, NULL, 1069 "svme-addr-chk", NULL, NULL, NULL, 1070 }, 1071 .cpuid = { .eax = 0x8000000A, .reg = R_EDX, }, 1072 .tcg_features = TCG_SVM_FEATURES, 1073 }, 1074 [FEAT_7_0_EBX] = { 1075 .type = CPUID_FEATURE_WORD, 1076 .feat_names = { 1077 "fsgsbase", "tsc-adjust", "sgx", "bmi1", 1078 "hle", "avx2", "fdp-excptn-only", "smep", 1079 "bmi2", "erms", "invpcid", "rtm", 1080 NULL, "zero-fcs-fds", "mpx", NULL, 1081 "avx512f", "avx512dq", "rdseed", "adx", 1082 "smap", "avx512ifma", "pcommit", "clflushopt", 1083 "clwb", "intel-pt", "avx512pf", "avx512er", 1084 "avx512cd", "sha-ni", "avx512bw", "avx512vl", 1085 }, 1086 .cpuid = { 1087 .eax = 7, 1088 .needs_ecx = true, .ecx = 0, 1089 .reg = R_EBX, 1090 }, 1091 .tcg_features = TCG_7_0_EBX_FEATURES, 1092 }, 1093 [FEAT_7_0_ECX] = { 1094 .type = CPUID_FEATURE_WORD, 1095 .feat_names = { 1096 NULL, "avx512vbmi", "umip", "pku", 1097 NULL /* ospke */, "waitpkg", "avx512vbmi2", NULL, 1098 "gfni", "vaes", "vpclmulqdq", "avx512vnni", 1099 "avx512bitalg", NULL, "avx512-vpopcntdq", NULL, 1100 "la57", NULL, NULL, NULL, 1101 NULL, NULL, "rdpid", NULL, 1102 "bus-lock-detect", "cldemote", NULL, "movdiri", 1103 "movdir64b", NULL, "sgxlc", "pks", 1104 }, 1105 .cpuid = { 1106 .eax = 7, 1107 .needs_ecx = true, .ecx = 0, 1108 .reg = R_ECX, 1109 }, 1110 .tcg_features = TCG_7_0_ECX_FEATURES, 1111 }, 1112 [FEAT_7_0_EDX] = { 1113 .type = CPUID_FEATURE_WORD, 1114 .feat_names = { 1115 NULL, NULL, "avx512-4vnniw", "avx512-4fmaps", 1116 "fsrm", NULL, NULL, NULL, 1117 "avx512-vp2intersect", NULL, "md-clear", NULL, 1118 NULL, NULL, "serialize", NULL, 1119 "tsx-ldtrk", NULL, NULL /* pconfig */, "arch-lbr", 1120 NULL, NULL, "amx-bf16", "avx512-fp16", 1121 "amx-tile", "amx-int8", "spec-ctrl", "stibp", 1122 "flush-l1d", "arch-capabilities", "core-capability", "ssbd", 1123 }, 1124 .cpuid = { 1125 .eax = 7, 1126 .needs_ecx = true, .ecx = 0, 1127 .reg = R_EDX, 1128 }, 1129 .tcg_features = TCG_7_0_EDX_FEATURES, 1130 }, 1131 [FEAT_7_1_EAX] = { 1132 .type = CPUID_FEATURE_WORD, 1133 .feat_names = { 1134 "sha512", "sm3", "sm4", NULL, 1135 "avx-vnni", "avx512-bf16", NULL, "cmpccxadd", 1136 NULL, NULL, "fzrm", "fsrs", 1137 "fsrc", NULL, NULL, NULL, 1138 NULL, "fred", "lkgs", "wrmsrns", 1139 NULL, "amx-fp16", NULL, "avx-ifma", 1140 NULL, NULL, "lam", NULL, 1141 NULL, NULL, NULL, NULL, 1142 }, 1143 .cpuid = { 1144 .eax = 7, 1145 .needs_ecx = true, .ecx = 1, 1146 .reg = R_EAX, 1147 }, 1148 .tcg_features = TCG_7_1_EAX_FEATURES, 1149 }, 1150 [FEAT_7_1_EDX] = { 1151 .type = CPUID_FEATURE_WORD, 1152 .feat_names = { 1153 NULL, NULL, NULL, NULL, 1154 "avx-vnni-int8", "avx-ne-convert", NULL, NULL, 1155 "amx-complex", NULL, "avx-vnni-int16", NULL, 1156 NULL, NULL, "prefetchiti", NULL, 1157 NULL, NULL, NULL, "avx10", 1158 NULL, NULL, NULL, NULL, 1159 NULL, NULL, NULL, NULL, 1160 NULL, NULL, NULL, NULL, 1161 }, 1162 .cpuid = { 1163 .eax = 7, 1164 .needs_ecx = true, .ecx = 1, 1165 .reg = R_EDX, 1166 }, 1167 .tcg_features = TCG_7_1_EDX_FEATURES, 1168 }, 1169 [FEAT_7_2_EDX] = { 1170 .type = CPUID_FEATURE_WORD, 1171 .feat_names = { 1172 "intel-psfd", "ipred-ctrl", "rrsba-ctrl", "ddpd-u", 1173 "bhi-ctrl", "mcdt-no", NULL, NULL, 1174 NULL, NULL, NULL, NULL, 1175 NULL, NULL, NULL, NULL, 1176 NULL, NULL, NULL, NULL, 1177 NULL, NULL, NULL, NULL, 1178 NULL, NULL, NULL, NULL, 1179 NULL, NULL, NULL, NULL, 1180 }, 1181 .cpuid = { 1182 .eax = 7, 1183 .needs_ecx = true, .ecx = 2, 1184 .reg = R_EDX, 1185 }, 1186 .tcg_features = TCG_7_2_EDX_FEATURES, 1187 }, 1188 [FEAT_24_0_EBX] = { 1189 .type = CPUID_FEATURE_WORD, 1190 .feat_names = { 1191 [16] = "avx10-128", 1192 [17] = "avx10-256", 1193 [18] = "avx10-512", 1194 }, 1195 .cpuid = { 1196 .eax = 0x24, 1197 .needs_ecx = true, .ecx = 0, 1198 .reg = R_EBX, 1199 }, 1200 .tcg_features = TCG_24_0_EBX_FEATURES, 1201 }, 1202 [FEAT_8000_0007_EDX] = { 1203 .type = CPUID_FEATURE_WORD, 1204 .feat_names = { 1205 NULL, NULL, NULL, NULL, 1206 NULL, NULL, NULL, NULL, 1207 "invtsc", NULL, NULL, NULL, 1208 NULL, NULL, NULL, NULL, 1209 NULL, NULL, NULL, NULL, 1210 NULL, NULL, NULL, NULL, 1211 NULL, NULL, NULL, NULL, 1212 NULL, NULL, NULL, NULL, 1213 }, 1214 .cpuid = { .eax = 0x80000007, .reg = R_EDX, }, 1215 .tcg_features = TCG_APM_FEATURES, 1216 .unmigratable_flags = CPUID_APM_INVTSC, 1217 }, 1218 [FEAT_8000_0007_EBX] = { 1219 .type = CPUID_FEATURE_WORD, 1220 .feat_names = { 1221 "overflow-recov", "succor", NULL, NULL, 1222 NULL, NULL, NULL, NULL, 1223 NULL, NULL, NULL, NULL, 1224 NULL, NULL, NULL, NULL, 1225 NULL, NULL, NULL, NULL, 1226 NULL, NULL, NULL, NULL, 1227 NULL, NULL, NULL, NULL, 1228 NULL, NULL, NULL, NULL, 1229 }, 1230 .cpuid = { .eax = 0x80000007, .reg = R_EBX, }, 1231 .tcg_features = 0, 1232 .unmigratable_flags = 0, 1233 }, 1234 [FEAT_8000_0008_EBX] = { 1235 .type = CPUID_FEATURE_WORD, 1236 .feat_names = { 1237 "clzero", NULL, "xsaveerptr", NULL, 1238 NULL, NULL, NULL, NULL, 1239 NULL, "wbnoinvd", NULL, NULL, 1240 "ibpb", NULL, "ibrs", "amd-stibp", 1241 NULL, "stibp-always-on", NULL, NULL, 1242 NULL, NULL, NULL, NULL, 1243 "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL, 1244 "amd-psfd", NULL, NULL, NULL, 1245 }, 1246 .cpuid = { .eax = 0x80000008, .reg = R_EBX, }, 1247 .tcg_features = TCG_8000_0008_EBX, 1248 .unmigratable_flags = 0, 1249 }, 1250 [FEAT_8000_0021_EAX] = { 1251 .type = CPUID_FEATURE_WORD, 1252 .feat_names = { 1253 "no-nested-data-bp", NULL, "lfence-always-serializing", NULL, 1254 NULL, NULL, "null-sel-clr-base", NULL, 1255 "auto-ibrs", NULL, NULL, NULL, 1256 NULL, NULL, NULL, NULL, 1257 NULL, NULL, NULL, NULL, 1258 NULL, NULL, NULL, NULL, 1259 "eraps", NULL, NULL, "sbpb", 1260 "ibpb-brtype", "srso-no", "srso-user-kernel-no", NULL, 1261 }, 1262 .cpuid = { .eax = 0x80000021, .reg = R_EAX, }, 1263 .tcg_features = TCG_8000_0021_EAX_FEATURES, 1264 .unmigratable_flags = 0, 1265 }, 1266 [FEAT_8000_0021_EBX] = { 1267 .type = CPUID_FEATURE_WORD, 1268 .cpuid = { .eax = 0x80000021, .reg = R_EBX, }, 1269 .tcg_features = 0, 1270 .unmigratable_flags = 0, 1271 }, 1272 [FEAT_8000_0022_EAX] = { 1273 .type = CPUID_FEATURE_WORD, 1274 .feat_names = { 1275 "perfmon-v2", NULL, NULL, NULL, 1276 NULL, NULL, NULL, NULL, 1277 NULL, NULL, NULL, NULL, 1278 NULL, NULL, NULL, NULL, 1279 NULL, NULL, NULL, NULL, 1280 NULL, NULL, NULL, NULL, 1281 NULL, NULL, NULL, NULL, 1282 NULL, NULL, NULL, NULL, 1283 }, 1284 .cpuid = { .eax = 0x80000022, .reg = R_EAX, }, 1285 .tcg_features = 0, 1286 .unmigratable_flags = 0, 1287 }, 1288 [FEAT_XSAVE] = { 1289 .type = CPUID_FEATURE_WORD, 1290 .feat_names = { 1291 "xsaveopt", "xsavec", "xgetbv1", "xsaves", 1292 "xfd", NULL, NULL, NULL, 1293 NULL, NULL, NULL, NULL, 1294 NULL, NULL, NULL, NULL, 1295 NULL, NULL, NULL, NULL, 1296 NULL, NULL, NULL, NULL, 1297 NULL, NULL, NULL, NULL, 1298 NULL, NULL, NULL, NULL, 1299 }, 1300 .cpuid = { 1301 .eax = 0xd, 1302 .needs_ecx = true, .ecx = 1, 1303 .reg = R_EAX, 1304 }, 1305 .tcg_features = TCG_XSAVE_FEATURES, 1306 }, 1307 [FEAT_XSAVE_XSS_LO] = { 1308 .type = CPUID_FEATURE_WORD, 1309 .feat_names = { 1310 NULL, NULL, NULL, NULL, 1311 NULL, NULL, NULL, NULL, 1312 NULL, NULL, NULL, NULL, 1313 NULL, NULL, NULL, NULL, 1314 NULL, NULL, NULL, NULL, 1315 NULL, NULL, NULL, NULL, 1316 NULL, NULL, NULL, NULL, 1317 NULL, NULL, NULL, NULL, 1318 }, 1319 .cpuid = { 1320 .eax = 0xD, 1321 .needs_ecx = true, 1322 .ecx = 1, 1323 .reg = R_ECX, 1324 }, 1325 }, 1326 [FEAT_XSAVE_XSS_HI] = { 1327 .type = CPUID_FEATURE_WORD, 1328 .cpuid = { 1329 .eax = 0xD, 1330 .needs_ecx = true, 1331 .ecx = 1, 1332 .reg = R_EDX 1333 }, 1334 }, 1335 [FEAT_6_EAX] = { 1336 .type = CPUID_FEATURE_WORD, 1337 .feat_names = { 1338 NULL, NULL, "arat", NULL, 1339 NULL, NULL, NULL, NULL, 1340 NULL, NULL, NULL, NULL, 1341 NULL, NULL, NULL, NULL, 1342 NULL, NULL, NULL, NULL, 1343 NULL, NULL, NULL, NULL, 1344 NULL, NULL, NULL, NULL, 1345 NULL, NULL, NULL, NULL, 1346 }, 1347 .cpuid = { .eax = 6, .reg = R_EAX, }, 1348 .tcg_features = TCG_6_EAX_FEATURES, 1349 }, 1350 [FEAT_XSAVE_XCR0_LO] = { 1351 .type = CPUID_FEATURE_WORD, 1352 .cpuid = { 1353 .eax = 0xD, 1354 .needs_ecx = true, .ecx = 0, 1355 .reg = R_EAX, 1356 }, 1357 .tcg_features = XSTATE_FP_MASK | XSTATE_SSE_MASK | 1358 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK | 1359 XSTATE_PKRU_MASK, 1360 .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK | 1361 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK | 1362 XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK | 1363 XSTATE_PKRU_MASK, 1364 }, 1365 [FEAT_XSAVE_XCR0_HI] = { 1366 .type = CPUID_FEATURE_WORD, 1367 .cpuid = { 1368 .eax = 0xD, 1369 .needs_ecx = true, .ecx = 0, 1370 .reg = R_EDX, 1371 }, 1372 .tcg_features = 0U, 1373 }, 1374 /*Below are MSR exposed features*/ 1375 [FEAT_ARCH_CAPABILITIES] = { 1376 .type = MSR_FEATURE_WORD, 1377 .feat_names = { 1378 "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry", 1379 "ssb-no", "mds-no", "pschange-mc-no", "tsx-ctrl", 1380 "taa-no", NULL, NULL, NULL, 1381 NULL, "sbdr-ssdp-no", "fbsdp-no", "psdp-no", 1382 NULL, "fb-clear", NULL, NULL, 1383 "bhi-no", NULL, NULL, NULL, 1384 "pbrsb-no", NULL, "gds-no", "rfds-no", 1385 "rfds-clear", NULL, NULL, NULL, 1386 }, 1387 .msr = { 1388 .index = MSR_IA32_ARCH_CAPABILITIES, 1389 }, 1390 /* 1391 * FEAT_ARCH_CAPABILITIES only affects a read-only MSR, which 1392 * cannot be read from user mode. Therefore, it has no impact 1393 > on any user-mode operation, and warnings about unsupported 1394 * features do not matter. 1395 */ 1396 .tcg_features = ~0U, 1397 }, 1398 [FEAT_CORE_CAPABILITY] = { 1399 .type = MSR_FEATURE_WORD, 1400 .feat_names = { 1401 NULL, NULL, NULL, NULL, 1402 NULL, "split-lock-detect", NULL, NULL, 1403 NULL, NULL, NULL, NULL, 1404 NULL, NULL, NULL, NULL, 1405 NULL, NULL, NULL, NULL, 1406 NULL, NULL, NULL, NULL, 1407 NULL, NULL, NULL, NULL, 1408 NULL, NULL, NULL, NULL, 1409 }, 1410 .msr = { 1411 .index = MSR_IA32_CORE_CAPABILITY, 1412 }, 1413 }, 1414 [FEAT_PERF_CAPABILITIES] = { 1415 .type = MSR_FEATURE_WORD, 1416 .feat_names = { 1417 NULL, NULL, NULL, NULL, 1418 NULL, NULL, NULL, NULL, 1419 NULL, NULL, NULL, NULL, 1420 NULL, "full-width-write", NULL, NULL, 1421 NULL, NULL, NULL, NULL, 1422 NULL, NULL, NULL, NULL, 1423 NULL, NULL, NULL, NULL, 1424 NULL, NULL, NULL, NULL, 1425 }, 1426 .msr = { 1427 .index = MSR_IA32_PERF_CAPABILITIES, 1428 }, 1429 }, 1430 1431 [FEAT_VMX_PROCBASED_CTLS] = { 1432 .type = MSR_FEATURE_WORD, 1433 .feat_names = { 1434 NULL, NULL, "vmx-vintr-pending", "vmx-tsc-offset", 1435 NULL, NULL, NULL, "vmx-hlt-exit", 1436 NULL, "vmx-invlpg-exit", "vmx-mwait-exit", "vmx-rdpmc-exit", 1437 "vmx-rdtsc-exit", NULL, NULL, "vmx-cr3-load-noexit", 1438 "vmx-cr3-store-noexit", NULL, NULL, "vmx-cr8-load-exit", 1439 "vmx-cr8-store-exit", "vmx-flexpriority", "vmx-vnmi-pending", "vmx-movdr-exit", 1440 "vmx-io-exit", "vmx-io-bitmap", NULL, "vmx-mtf", 1441 "vmx-msr-bitmap", "vmx-monitor-exit", "vmx-pause-exit", "vmx-secondary-ctls", 1442 }, 1443 .msr = { 1444 .index = MSR_IA32_VMX_TRUE_PROCBASED_CTLS, 1445 } 1446 }, 1447 1448 [FEAT_VMX_SECONDARY_CTLS] = { 1449 .type = MSR_FEATURE_WORD, 1450 .feat_names = { 1451 "vmx-apicv-xapic", "vmx-ept", "vmx-desc-exit", "vmx-rdtscp-exit", 1452 "vmx-apicv-x2apic", "vmx-vpid", "vmx-wbinvd-exit", "vmx-unrestricted-guest", 1453 "vmx-apicv-register", "vmx-apicv-vid", "vmx-ple", "vmx-rdrand-exit", 1454 "vmx-invpcid-exit", "vmx-vmfunc", "vmx-shadow-vmcs", "vmx-encls-exit", 1455 "vmx-rdseed-exit", "vmx-pml", NULL, NULL, 1456 "vmx-xsaves", NULL, NULL, NULL, 1457 NULL, "vmx-tsc-scaling", "vmx-enable-user-wait-pause", NULL, 1458 NULL, NULL, NULL, NULL, 1459 }, 1460 .msr = { 1461 .index = MSR_IA32_VMX_PROCBASED_CTLS2, 1462 } 1463 }, 1464 1465 [FEAT_VMX_PINBASED_CTLS] = { 1466 .type = MSR_FEATURE_WORD, 1467 .feat_names = { 1468 "vmx-intr-exit", NULL, NULL, "vmx-nmi-exit", 1469 NULL, "vmx-vnmi", "vmx-preemption-timer", "vmx-posted-intr", 1470 NULL, NULL, NULL, NULL, 1471 NULL, NULL, NULL, NULL, 1472 NULL, NULL, NULL, NULL, 1473 NULL, NULL, NULL, NULL, 1474 NULL, NULL, NULL, NULL, 1475 NULL, NULL, NULL, NULL, 1476 }, 1477 .msr = { 1478 .index = MSR_IA32_VMX_TRUE_PINBASED_CTLS, 1479 } 1480 }, 1481 1482 [FEAT_VMX_EXIT_CTLS] = { 1483 .type = MSR_FEATURE_WORD, 1484 /* 1485 * VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE is copied from 1486 * the LM CPUID bit. 1487 */ 1488 .feat_names = { 1489 NULL, NULL, "vmx-exit-nosave-debugctl", NULL, 1490 NULL, NULL, NULL, NULL, 1491 NULL, NULL /* vmx-exit-host-addr-space-size */, NULL, NULL, 1492 "vmx-exit-load-perf-global-ctrl", NULL, NULL, "vmx-exit-ack-intr", 1493 NULL, NULL, "vmx-exit-save-pat", "vmx-exit-load-pat", 1494 "vmx-exit-save-efer", "vmx-exit-load-efer", 1495 "vmx-exit-save-preemption-timer", "vmx-exit-clear-bndcfgs", 1496 NULL, "vmx-exit-clear-rtit-ctl", NULL, NULL, 1497 NULL, "vmx-exit-load-pkrs", NULL, "vmx-exit-secondary-ctls", 1498 }, 1499 .msr = { 1500 .index = MSR_IA32_VMX_TRUE_EXIT_CTLS, 1501 } 1502 }, 1503 1504 [FEAT_VMX_ENTRY_CTLS] = { 1505 .type = MSR_FEATURE_WORD, 1506 .feat_names = { 1507 NULL, NULL, "vmx-entry-noload-debugctl", NULL, 1508 NULL, NULL, NULL, NULL, 1509 NULL, "vmx-entry-ia32e-mode", NULL, NULL, 1510 NULL, "vmx-entry-load-perf-global-ctrl", "vmx-entry-load-pat", "vmx-entry-load-efer", 1511 "vmx-entry-load-bndcfgs", NULL, "vmx-entry-load-rtit-ctl", NULL, 1512 NULL, NULL, "vmx-entry-load-pkrs", "vmx-entry-load-fred", 1513 NULL, NULL, NULL, NULL, 1514 NULL, NULL, NULL, NULL, 1515 }, 1516 .msr = { 1517 .index = MSR_IA32_VMX_TRUE_ENTRY_CTLS, 1518 } 1519 }, 1520 1521 [FEAT_VMX_MISC] = { 1522 .type = MSR_FEATURE_WORD, 1523 .feat_names = { 1524 NULL, NULL, NULL, NULL, 1525 NULL, "vmx-store-lma", "vmx-activity-hlt", "vmx-activity-shutdown", 1526 "vmx-activity-wait-sipi", NULL, NULL, NULL, 1527 NULL, NULL, NULL, NULL, 1528 NULL, NULL, NULL, NULL, 1529 NULL, NULL, NULL, NULL, 1530 NULL, NULL, NULL, NULL, 1531 NULL, "vmx-vmwrite-vmexit-fields", "vmx-zero-len-inject", NULL, 1532 }, 1533 .msr = { 1534 .index = MSR_IA32_VMX_MISC, 1535 } 1536 }, 1537 1538 [FEAT_VMX_EPT_VPID_CAPS] = { 1539 .type = MSR_FEATURE_WORD, 1540 .feat_names = { 1541 "vmx-ept-execonly", NULL, NULL, NULL, 1542 NULL, NULL, "vmx-page-walk-4", "vmx-page-walk-5", 1543 NULL, NULL, NULL, NULL, 1544 NULL, NULL, NULL, NULL, 1545 "vmx-ept-2mb", "vmx-ept-1gb", NULL, NULL, 1546 "vmx-invept", "vmx-eptad", "vmx-ept-advanced-exitinfo", NULL, 1547 NULL, "vmx-invept-single-context", "vmx-invept-all-context", NULL, 1548 NULL, NULL, NULL, NULL, 1549 "vmx-invvpid", NULL, NULL, NULL, 1550 NULL, NULL, NULL, NULL, 1551 "vmx-invvpid-single-addr", "vmx-invept-single-context", 1552 "vmx-invvpid-all-context", "vmx-invept-single-context-noglobals", 1553 NULL, NULL, NULL, NULL, 1554 NULL, NULL, NULL, NULL, 1555 NULL, NULL, NULL, NULL, 1556 NULL, NULL, NULL, NULL, 1557 NULL, NULL, NULL, NULL, 1558 }, 1559 .msr = { 1560 .index = MSR_IA32_VMX_EPT_VPID_CAP, 1561 } 1562 }, 1563 1564 [FEAT_VMX_BASIC] = { 1565 .type = MSR_FEATURE_WORD, 1566 .feat_names = { 1567 [54] = "vmx-ins-outs", 1568 [55] = "vmx-true-ctls", 1569 [56] = "vmx-any-errcode", 1570 [58] = "vmx-nested-exception", 1571 }, 1572 .msr = { 1573 .index = MSR_IA32_VMX_BASIC, 1574 }, 1575 /* Just to be safe - we don't support setting the MSEG version field. */ 1576 .no_autoenable_flags = MSR_VMX_BASIC_DUAL_MONITOR, 1577 }, 1578 1579 [FEAT_VMX_VMFUNC] = { 1580 .type = MSR_FEATURE_WORD, 1581 .feat_names = { 1582 [0] = "vmx-eptp-switching", 1583 }, 1584 .msr = { 1585 .index = MSR_IA32_VMX_VMFUNC, 1586 } 1587 }, 1588 1589 [FEAT_14_0_ECX] = { 1590 .type = CPUID_FEATURE_WORD, 1591 .feat_names = { 1592 NULL, NULL, NULL, NULL, 1593 NULL, NULL, NULL, NULL, 1594 NULL, NULL, NULL, NULL, 1595 NULL, NULL, NULL, NULL, 1596 NULL, NULL, NULL, NULL, 1597 NULL, NULL, NULL, NULL, 1598 NULL, NULL, NULL, NULL, 1599 NULL, NULL, NULL, "intel-pt-lip", 1600 }, 1601 .cpuid = { 1602 .eax = 0x14, 1603 .needs_ecx = true, .ecx = 0, 1604 .reg = R_ECX, 1605 }, 1606 .tcg_features = TCG_14_0_ECX_FEATURES, 1607 }, 1608 1609 [FEAT_SGX_12_0_EAX] = { 1610 .type = CPUID_FEATURE_WORD, 1611 .feat_names = { 1612 "sgx1", "sgx2", NULL, NULL, 1613 NULL, NULL, NULL, NULL, 1614 NULL, NULL, NULL, "sgx-edeccssa", 1615 NULL, NULL, NULL, NULL, 1616 NULL, NULL, NULL, NULL, 1617 NULL, NULL, NULL, NULL, 1618 NULL, NULL, NULL, NULL, 1619 NULL, NULL, NULL, NULL, 1620 }, 1621 .cpuid = { 1622 .eax = 0x12, 1623 .needs_ecx = true, .ecx = 0, 1624 .reg = R_EAX, 1625 }, 1626 .tcg_features = TCG_SGX_12_0_EAX_FEATURES, 1627 }, 1628 1629 [FEAT_SGX_12_0_EBX] = { 1630 .type = CPUID_FEATURE_WORD, 1631 .feat_names = { 1632 "sgx-exinfo" , NULL, NULL, NULL, 1633 NULL, NULL, NULL, NULL, 1634 NULL, NULL, NULL, NULL, 1635 NULL, NULL, NULL, NULL, 1636 NULL, NULL, NULL, NULL, 1637 NULL, NULL, NULL, NULL, 1638 NULL, NULL, NULL, NULL, 1639 NULL, NULL, NULL, NULL, 1640 }, 1641 .cpuid = { 1642 .eax = 0x12, 1643 .needs_ecx = true, .ecx = 0, 1644 .reg = R_EBX, 1645 }, 1646 .tcg_features = TCG_SGX_12_0_EBX_FEATURES, 1647 }, 1648 1649 [FEAT_SGX_12_1_EAX] = { 1650 .type = CPUID_FEATURE_WORD, 1651 .feat_names = { 1652 NULL, "sgx-debug", "sgx-mode64", NULL, 1653 "sgx-provisionkey", "sgx-tokenkey", NULL, "sgx-kss", 1654 NULL, NULL, "sgx-aex-notify", NULL, 1655 NULL, NULL, NULL, NULL, 1656 NULL, NULL, NULL, NULL, 1657 NULL, NULL, NULL, NULL, 1658 NULL, NULL, NULL, NULL, 1659 NULL, NULL, NULL, NULL, 1660 }, 1661 .cpuid = { 1662 .eax = 0x12, 1663 .needs_ecx = true, .ecx = 1, 1664 .reg = R_EAX, 1665 }, 1666 .tcg_features = TCG_SGX_12_1_EAX_FEATURES, 1667 }, 1668 }; 1669 1670 typedef struct FeatureMask { 1671 FeatureWord index; 1672 uint64_t mask; 1673 } FeatureMask; 1674 1675 typedef struct FeatureDep { 1676 FeatureMask from, to; 1677 } FeatureDep; 1678 1679 static FeatureDep feature_dependencies[] = { 1680 { 1681 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_ARCH_CAPABILITIES }, 1682 .to = { FEAT_ARCH_CAPABILITIES, ~0ull }, 1683 }, 1684 { 1685 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_CORE_CAPABILITY }, 1686 .to = { FEAT_CORE_CAPABILITY, ~0ull }, 1687 }, 1688 { 1689 .from = { FEAT_1_ECX, CPUID_EXT_PDCM }, 1690 .to = { FEAT_PERF_CAPABILITIES, ~0ull }, 1691 }, 1692 { 1693 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1694 .to = { FEAT_VMX_PROCBASED_CTLS, ~0ull }, 1695 }, 1696 { 1697 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1698 .to = { FEAT_VMX_PINBASED_CTLS, ~0ull }, 1699 }, 1700 { 1701 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1702 .to = { FEAT_VMX_EXIT_CTLS, ~0ull }, 1703 }, 1704 { 1705 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1706 .to = { FEAT_VMX_ENTRY_CTLS, ~0ull }, 1707 }, 1708 { 1709 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1710 .to = { FEAT_VMX_MISC, ~0ull }, 1711 }, 1712 { 1713 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1714 .to = { FEAT_VMX_BASIC, ~0ull }, 1715 }, 1716 { 1717 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_LM }, 1718 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_IA32E_MODE }, 1719 }, 1720 { 1721 .from = { FEAT_VMX_PROCBASED_CTLS, VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS }, 1722 .to = { FEAT_VMX_SECONDARY_CTLS, ~0ull }, 1723 }, 1724 { 1725 .from = { FEAT_XSAVE, CPUID_XSAVE_XSAVES }, 1726 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_XSAVES }, 1727 }, 1728 { 1729 .from = { FEAT_1_ECX, CPUID_EXT_RDRAND }, 1730 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDRAND_EXITING }, 1731 }, 1732 { 1733 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INVPCID }, 1734 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_INVPCID }, 1735 }, 1736 { 1737 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_MPX }, 1738 .to = { FEAT_VMX_EXIT_CTLS, VMX_VM_EXIT_CLEAR_BNDCFGS }, 1739 }, 1740 { 1741 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_MPX }, 1742 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_LOAD_BNDCFGS }, 1743 }, 1744 { 1745 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_RDSEED }, 1746 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDSEED_EXITING }, 1747 }, 1748 { 1749 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT }, 1750 .to = { FEAT_14_0_ECX, ~0ull }, 1751 }, 1752 { 1753 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_RDTSCP }, 1754 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDTSCP }, 1755 }, 1756 { 1757 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT }, 1758 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull }, 1759 }, 1760 { 1761 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT }, 1762 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST }, 1763 }, 1764 { 1765 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VPID }, 1766 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull << 32 }, 1767 }, 1768 { 1769 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VMFUNC }, 1770 .to = { FEAT_VMX_VMFUNC, ~0ull }, 1771 }, 1772 { 1773 .from = { FEAT_8000_0001_ECX, CPUID_EXT3_SVM }, 1774 .to = { FEAT_SVM, ~0ull }, 1775 }, 1776 { 1777 .from = { FEAT_7_0_ECX, CPUID_7_0_ECX_WAITPKG }, 1778 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_USER_WAIT_PAUSE }, 1779 }, 1780 { 1781 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_LM }, 1782 .to = { FEAT_7_1_EAX, CPUID_7_1_EAX_FRED }, 1783 }, 1784 { 1785 .from = { FEAT_7_1_EAX, CPUID_7_1_EAX_LKGS }, 1786 .to = { FEAT_7_1_EAX, CPUID_7_1_EAX_FRED }, 1787 }, 1788 { 1789 .from = { FEAT_7_1_EAX, CPUID_7_1_EAX_WRMSRNS }, 1790 .to = { FEAT_7_1_EAX, CPUID_7_1_EAX_FRED }, 1791 }, 1792 { 1793 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_SGX }, 1794 .to = { FEAT_7_0_ECX, CPUID_7_0_ECX_SGX_LC }, 1795 }, 1796 { 1797 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_SGX }, 1798 .to = { FEAT_SGX_12_0_EAX, ~0ull }, 1799 }, 1800 { 1801 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_SGX }, 1802 .to = { FEAT_SGX_12_0_EBX, ~0ull }, 1803 }, 1804 { 1805 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_SGX }, 1806 .to = { FEAT_SGX_12_1_EAX, ~0ull }, 1807 }, 1808 { 1809 .from = { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_128 }, 1810 .to = { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_256 }, 1811 }, 1812 { 1813 .from = { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_256 }, 1814 .to = { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_512 }, 1815 }, 1816 { 1817 .from = { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_VL_MASK }, 1818 .to = { FEAT_7_1_EDX, CPUID_7_1_EDX_AVX10 }, 1819 }, 1820 { 1821 .from = { FEAT_7_1_EDX, CPUID_7_1_EDX_AVX10 }, 1822 .to = { FEAT_24_0_EBX, ~0ull }, 1823 }, 1824 }; 1825 1826 typedef struct X86RegisterInfo32 { 1827 /* Name of register */ 1828 const char *name; 1829 /* QAPI enum value register */ 1830 X86CPURegister32 qapi_enum; 1831 } X86RegisterInfo32; 1832 1833 #define REGISTER(reg) \ 1834 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg } 1835 static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = { 1836 REGISTER(EAX), 1837 REGISTER(ECX), 1838 REGISTER(EDX), 1839 REGISTER(EBX), 1840 REGISTER(ESP), 1841 REGISTER(EBP), 1842 REGISTER(ESI), 1843 REGISTER(EDI), 1844 }; 1845 #undef REGISTER 1846 1847 /* CPUID feature bits available in XSS */ 1848 #define CPUID_XSTATE_XSS_MASK (XSTATE_ARCH_LBR_MASK) 1849 1850 ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUNT] = { 1851 [XSTATE_FP_BIT] = { 1852 /* x87 FP state component is always enabled if XSAVE is supported */ 1853 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE, 1854 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader), 1855 }, 1856 [XSTATE_SSE_BIT] = { 1857 /* SSE state component is always enabled if XSAVE is supported */ 1858 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE, 1859 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader), 1860 }, 1861 [XSTATE_YMM_BIT] = 1862 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX, 1863 .size = sizeof(XSaveAVX) }, 1864 [XSTATE_BNDREGS_BIT] = 1865 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX, 1866 .size = sizeof(XSaveBNDREG) }, 1867 [XSTATE_BNDCSR_BIT] = 1868 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX, 1869 .size = sizeof(XSaveBNDCSR) }, 1870 [XSTATE_OPMASK_BIT] = 1871 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1872 .size = sizeof(XSaveOpmask) }, 1873 [XSTATE_ZMM_Hi256_BIT] = 1874 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1875 .size = sizeof(XSaveZMM_Hi256) }, 1876 [XSTATE_Hi16_ZMM_BIT] = 1877 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1878 .size = sizeof(XSaveHi16_ZMM) }, 1879 [XSTATE_PKRU_BIT] = 1880 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU, 1881 .size = sizeof(XSavePKRU) }, 1882 [XSTATE_ARCH_LBR_BIT] = { 1883 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_ARCH_LBR, 1884 .offset = 0 /*supervisor mode component, offset = 0 */, 1885 .size = sizeof(XSavesArchLBR) }, 1886 [XSTATE_XTILE_CFG_BIT] = { 1887 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_AMX_TILE, 1888 .size = sizeof(XSaveXTILECFG), 1889 }, 1890 [XSTATE_XTILE_DATA_BIT] = { 1891 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_AMX_TILE, 1892 .size = sizeof(XSaveXTILEDATA) 1893 }, 1894 }; 1895 1896 uint32_t xsave_area_size(uint64_t mask, bool compacted) 1897 { 1898 uint64_t ret = x86_ext_save_areas[0].size; 1899 const ExtSaveArea *esa; 1900 uint32_t offset = 0; 1901 int i; 1902 1903 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 1904 esa = &x86_ext_save_areas[i]; 1905 if ((mask >> i) & 1) { 1906 offset = compacted ? ret : esa->offset; 1907 ret = MAX(ret, offset + esa->size); 1908 } 1909 } 1910 return ret; 1911 } 1912 1913 static inline bool accel_uses_host_cpuid(void) 1914 { 1915 return kvm_enabled() || hvf_enabled(); 1916 } 1917 1918 static inline uint64_t x86_cpu_xsave_xcr0_components(X86CPU *cpu) 1919 { 1920 return ((uint64_t)cpu->env.features[FEAT_XSAVE_XCR0_HI]) << 32 | 1921 cpu->env.features[FEAT_XSAVE_XCR0_LO]; 1922 } 1923 1924 /* Return name of 32-bit register, from a R_* constant */ 1925 static const char *get_register_name_32(unsigned int reg) 1926 { 1927 if (reg >= CPU_NB_REGS32) { 1928 return NULL; 1929 } 1930 return x86_reg_info_32[reg].name; 1931 } 1932 1933 static inline uint64_t x86_cpu_xsave_xss_components(X86CPU *cpu) 1934 { 1935 return ((uint64_t)cpu->env.features[FEAT_XSAVE_XSS_HI]) << 32 | 1936 cpu->env.features[FEAT_XSAVE_XSS_LO]; 1937 } 1938 1939 /* 1940 * Returns the set of feature flags that are supported and migratable by 1941 * QEMU, for a given FeatureWord. 1942 */ 1943 static uint64_t x86_cpu_get_migratable_flags(X86CPU *cpu, FeatureWord w) 1944 { 1945 FeatureWordInfo *wi = &feature_word_info[w]; 1946 CPUX86State *env = &cpu->env; 1947 uint64_t r = 0; 1948 int i; 1949 1950 for (i = 0; i < 64; i++) { 1951 uint64_t f = 1ULL << i; 1952 1953 /* If the feature name is known, it is implicitly considered migratable, 1954 * unless it is explicitly set in unmigratable_flags */ 1955 if ((wi->migratable_flags & f) || 1956 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) { 1957 r |= f; 1958 } 1959 } 1960 1961 /* when tsc-khz is set explicitly, invtsc is migratable */ 1962 if ((w == FEAT_8000_0007_EDX) && env->user_tsc_khz) { 1963 r |= CPUID_APM_INVTSC; 1964 } 1965 1966 return r; 1967 } 1968 1969 void host_cpuid(uint32_t function, uint32_t count, 1970 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) 1971 { 1972 uint32_t vec[4]; 1973 1974 #ifdef __x86_64__ 1975 asm volatile("cpuid" 1976 : "=a"(vec[0]), "=b"(vec[1]), 1977 "=c"(vec[2]), "=d"(vec[3]) 1978 : "0"(function), "c"(count) : "cc"); 1979 #elif defined(__i386__) 1980 asm volatile("pusha \n\t" 1981 "cpuid \n\t" 1982 "mov %%eax, 0(%2) \n\t" 1983 "mov %%ebx, 4(%2) \n\t" 1984 "mov %%ecx, 8(%2) \n\t" 1985 "mov %%edx, 12(%2) \n\t" 1986 "popa" 1987 : : "a"(function), "c"(count), "S"(vec) 1988 : "memory", "cc"); 1989 #else 1990 abort(); 1991 #endif 1992 1993 if (eax) 1994 *eax = vec[0]; 1995 if (ebx) 1996 *ebx = vec[1]; 1997 if (ecx) 1998 *ecx = vec[2]; 1999 if (edx) 2000 *edx = vec[3]; 2001 } 2002 2003 /* CPU class name definitions: */ 2004 2005 /* Return type name for a given CPU model name 2006 * Caller is responsible for freeing the returned string. 2007 */ 2008 static char *x86_cpu_type_name(const char *model_name) 2009 { 2010 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name); 2011 } 2012 2013 static ObjectClass *x86_cpu_class_by_name(const char *cpu_model) 2014 { 2015 g_autofree char *typename = x86_cpu_type_name(cpu_model); 2016 return object_class_by_name(typename); 2017 } 2018 2019 static char *x86_cpu_class_get_model_name(X86CPUClass *cc) 2020 { 2021 const char *class_name = object_class_get_name(OBJECT_CLASS(cc)); 2022 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX)); 2023 return cpu_model_from_type(class_name); 2024 } 2025 2026 typedef struct X86CPUVersionDefinition { 2027 X86CPUVersion version; 2028 const char *alias; 2029 const char *note; 2030 PropValue *props; 2031 const CPUCaches *const cache_info; 2032 } X86CPUVersionDefinition; 2033 2034 /* Base definition for a CPU model */ 2035 typedef struct X86CPUDefinition { 2036 const char *name; 2037 uint32_t level; 2038 uint32_t xlevel; 2039 /* vendor is zero-terminated, 12 character ASCII string */ 2040 char vendor[CPUID_VENDOR_SZ + 1]; 2041 int family; 2042 int model; 2043 int stepping; 2044 uint8_t avx10_version; 2045 FeatureWordArray features; 2046 const char *model_id; 2047 const CPUCaches *const cache_info; 2048 /* 2049 * Definitions for alternative versions of CPU model. 2050 * List is terminated by item with version == 0. 2051 * If NULL, version 1 will be registered automatically. 2052 */ 2053 const X86CPUVersionDefinition *versions; 2054 const char *deprecation_note; 2055 } X86CPUDefinition; 2056 2057 /* Reference to a specific CPU model version */ 2058 struct X86CPUModel { 2059 /* Base CPU definition */ 2060 const X86CPUDefinition *cpudef; 2061 /* CPU model version */ 2062 X86CPUVersion version; 2063 const char *note; 2064 /* 2065 * If true, this is an alias CPU model. 2066 * This matters only for "-cpu help" and query-cpu-definitions 2067 */ 2068 bool is_alias; 2069 }; 2070 2071 /* Get full model name for CPU version */ 2072 static char *x86_cpu_versioned_model_name(const X86CPUDefinition *cpudef, 2073 X86CPUVersion version) 2074 { 2075 assert(version > 0); 2076 return g_strdup_printf("%s-v%d", cpudef->name, (int)version); 2077 } 2078 2079 static const X86CPUVersionDefinition * 2080 x86_cpu_def_get_versions(const X86CPUDefinition *def) 2081 { 2082 /* When X86CPUDefinition::versions is NULL, we register only v1 */ 2083 static const X86CPUVersionDefinition default_version_list[] = { 2084 { 1 }, 2085 { /* end of list */ } 2086 }; 2087 2088 return def->versions ?: default_version_list; 2089 } 2090 2091 static const CPUCaches epyc_cache_info = { 2092 .l1d_cache = &(CPUCacheInfo) { 2093 .type = DATA_CACHE, 2094 .level = 1, 2095 .size = 32 * KiB, 2096 .line_size = 64, 2097 .associativity = 8, 2098 .partitions = 1, 2099 .sets = 64, 2100 .lines_per_tag = 1, 2101 .self_init = 1, 2102 .no_invd_sharing = true, 2103 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2104 }, 2105 .l1i_cache = &(CPUCacheInfo) { 2106 .type = INSTRUCTION_CACHE, 2107 .level = 1, 2108 .size = 64 * KiB, 2109 .line_size = 64, 2110 .associativity = 4, 2111 .partitions = 1, 2112 .sets = 256, 2113 .lines_per_tag = 1, 2114 .self_init = 1, 2115 .no_invd_sharing = true, 2116 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2117 }, 2118 .l2_cache = &(CPUCacheInfo) { 2119 .type = UNIFIED_CACHE, 2120 .level = 2, 2121 .size = 512 * KiB, 2122 .line_size = 64, 2123 .associativity = 8, 2124 .partitions = 1, 2125 .sets = 1024, 2126 .lines_per_tag = 1, 2127 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2128 }, 2129 .l3_cache = &(CPUCacheInfo) { 2130 .type = UNIFIED_CACHE, 2131 .level = 3, 2132 .size = 8 * MiB, 2133 .line_size = 64, 2134 .associativity = 16, 2135 .partitions = 1, 2136 .sets = 8192, 2137 .lines_per_tag = 1, 2138 .self_init = true, 2139 .inclusive = true, 2140 .complex_indexing = true, 2141 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2142 }, 2143 }; 2144 2145 static CPUCaches epyc_v4_cache_info = { 2146 .l1d_cache = &(CPUCacheInfo) { 2147 .type = DATA_CACHE, 2148 .level = 1, 2149 .size = 32 * KiB, 2150 .line_size = 64, 2151 .associativity = 8, 2152 .partitions = 1, 2153 .sets = 64, 2154 .lines_per_tag = 1, 2155 .self_init = 1, 2156 .no_invd_sharing = true, 2157 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2158 }, 2159 .l1i_cache = &(CPUCacheInfo) { 2160 .type = INSTRUCTION_CACHE, 2161 .level = 1, 2162 .size = 64 * KiB, 2163 .line_size = 64, 2164 .associativity = 4, 2165 .partitions = 1, 2166 .sets = 256, 2167 .lines_per_tag = 1, 2168 .self_init = 1, 2169 .no_invd_sharing = true, 2170 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2171 }, 2172 .l2_cache = &(CPUCacheInfo) { 2173 .type = UNIFIED_CACHE, 2174 .level = 2, 2175 .size = 512 * KiB, 2176 .line_size = 64, 2177 .associativity = 8, 2178 .partitions = 1, 2179 .sets = 1024, 2180 .lines_per_tag = 1, 2181 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2182 }, 2183 .l3_cache = &(CPUCacheInfo) { 2184 .type = UNIFIED_CACHE, 2185 .level = 3, 2186 .size = 8 * MiB, 2187 .line_size = 64, 2188 .associativity = 16, 2189 .partitions = 1, 2190 .sets = 8192, 2191 .lines_per_tag = 1, 2192 .self_init = true, 2193 .inclusive = true, 2194 .complex_indexing = false, 2195 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2196 }, 2197 }; 2198 2199 static const CPUCaches epyc_rome_cache_info = { 2200 .l1d_cache = &(CPUCacheInfo) { 2201 .type = DATA_CACHE, 2202 .level = 1, 2203 .size = 32 * KiB, 2204 .line_size = 64, 2205 .associativity = 8, 2206 .partitions = 1, 2207 .sets = 64, 2208 .lines_per_tag = 1, 2209 .self_init = 1, 2210 .no_invd_sharing = true, 2211 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2212 }, 2213 .l1i_cache = &(CPUCacheInfo) { 2214 .type = INSTRUCTION_CACHE, 2215 .level = 1, 2216 .size = 32 * KiB, 2217 .line_size = 64, 2218 .associativity = 8, 2219 .partitions = 1, 2220 .sets = 64, 2221 .lines_per_tag = 1, 2222 .self_init = 1, 2223 .no_invd_sharing = true, 2224 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2225 }, 2226 .l2_cache = &(CPUCacheInfo) { 2227 .type = UNIFIED_CACHE, 2228 .level = 2, 2229 .size = 512 * KiB, 2230 .line_size = 64, 2231 .associativity = 8, 2232 .partitions = 1, 2233 .sets = 1024, 2234 .lines_per_tag = 1, 2235 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2236 }, 2237 .l3_cache = &(CPUCacheInfo) { 2238 .type = UNIFIED_CACHE, 2239 .level = 3, 2240 .size = 16 * MiB, 2241 .line_size = 64, 2242 .associativity = 16, 2243 .partitions = 1, 2244 .sets = 16384, 2245 .lines_per_tag = 1, 2246 .self_init = true, 2247 .inclusive = true, 2248 .complex_indexing = true, 2249 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2250 }, 2251 }; 2252 2253 static const CPUCaches epyc_rome_v3_cache_info = { 2254 .l1d_cache = &(CPUCacheInfo) { 2255 .type = DATA_CACHE, 2256 .level = 1, 2257 .size = 32 * KiB, 2258 .line_size = 64, 2259 .associativity = 8, 2260 .partitions = 1, 2261 .sets = 64, 2262 .lines_per_tag = 1, 2263 .self_init = 1, 2264 .no_invd_sharing = true, 2265 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2266 }, 2267 .l1i_cache = &(CPUCacheInfo) { 2268 .type = INSTRUCTION_CACHE, 2269 .level = 1, 2270 .size = 32 * KiB, 2271 .line_size = 64, 2272 .associativity = 8, 2273 .partitions = 1, 2274 .sets = 64, 2275 .lines_per_tag = 1, 2276 .self_init = 1, 2277 .no_invd_sharing = true, 2278 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2279 }, 2280 .l2_cache = &(CPUCacheInfo) { 2281 .type = UNIFIED_CACHE, 2282 .level = 2, 2283 .size = 512 * KiB, 2284 .line_size = 64, 2285 .associativity = 8, 2286 .partitions = 1, 2287 .sets = 1024, 2288 .lines_per_tag = 1, 2289 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2290 }, 2291 .l3_cache = &(CPUCacheInfo) { 2292 .type = UNIFIED_CACHE, 2293 .level = 3, 2294 .size = 16 * MiB, 2295 .line_size = 64, 2296 .associativity = 16, 2297 .partitions = 1, 2298 .sets = 16384, 2299 .lines_per_tag = 1, 2300 .self_init = true, 2301 .inclusive = true, 2302 .complex_indexing = false, 2303 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2304 }, 2305 }; 2306 2307 static const CPUCaches epyc_milan_cache_info = { 2308 .l1d_cache = &(CPUCacheInfo) { 2309 .type = DATA_CACHE, 2310 .level = 1, 2311 .size = 32 * KiB, 2312 .line_size = 64, 2313 .associativity = 8, 2314 .partitions = 1, 2315 .sets = 64, 2316 .lines_per_tag = 1, 2317 .self_init = 1, 2318 .no_invd_sharing = true, 2319 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2320 }, 2321 .l1i_cache = &(CPUCacheInfo) { 2322 .type = INSTRUCTION_CACHE, 2323 .level = 1, 2324 .size = 32 * KiB, 2325 .line_size = 64, 2326 .associativity = 8, 2327 .partitions = 1, 2328 .sets = 64, 2329 .lines_per_tag = 1, 2330 .self_init = 1, 2331 .no_invd_sharing = true, 2332 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2333 }, 2334 .l2_cache = &(CPUCacheInfo) { 2335 .type = UNIFIED_CACHE, 2336 .level = 2, 2337 .size = 512 * KiB, 2338 .line_size = 64, 2339 .associativity = 8, 2340 .partitions = 1, 2341 .sets = 1024, 2342 .lines_per_tag = 1, 2343 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2344 }, 2345 .l3_cache = &(CPUCacheInfo) { 2346 .type = UNIFIED_CACHE, 2347 .level = 3, 2348 .size = 32 * MiB, 2349 .line_size = 64, 2350 .associativity = 16, 2351 .partitions = 1, 2352 .sets = 32768, 2353 .lines_per_tag = 1, 2354 .self_init = true, 2355 .inclusive = true, 2356 .complex_indexing = true, 2357 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2358 }, 2359 }; 2360 2361 static const CPUCaches epyc_milan_v2_cache_info = { 2362 .l1d_cache = &(CPUCacheInfo) { 2363 .type = DATA_CACHE, 2364 .level = 1, 2365 .size = 32 * KiB, 2366 .line_size = 64, 2367 .associativity = 8, 2368 .partitions = 1, 2369 .sets = 64, 2370 .lines_per_tag = 1, 2371 .self_init = 1, 2372 .no_invd_sharing = true, 2373 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2374 }, 2375 .l1i_cache = &(CPUCacheInfo) { 2376 .type = INSTRUCTION_CACHE, 2377 .level = 1, 2378 .size = 32 * KiB, 2379 .line_size = 64, 2380 .associativity = 8, 2381 .partitions = 1, 2382 .sets = 64, 2383 .lines_per_tag = 1, 2384 .self_init = 1, 2385 .no_invd_sharing = true, 2386 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2387 }, 2388 .l2_cache = &(CPUCacheInfo) { 2389 .type = UNIFIED_CACHE, 2390 .level = 2, 2391 .size = 512 * KiB, 2392 .line_size = 64, 2393 .associativity = 8, 2394 .partitions = 1, 2395 .sets = 1024, 2396 .lines_per_tag = 1, 2397 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2398 }, 2399 .l3_cache = &(CPUCacheInfo) { 2400 .type = UNIFIED_CACHE, 2401 .level = 3, 2402 .size = 32 * MiB, 2403 .line_size = 64, 2404 .associativity = 16, 2405 .partitions = 1, 2406 .sets = 32768, 2407 .lines_per_tag = 1, 2408 .self_init = true, 2409 .inclusive = true, 2410 .complex_indexing = false, 2411 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2412 }, 2413 }; 2414 2415 static const CPUCaches epyc_genoa_cache_info = { 2416 .l1d_cache = &(CPUCacheInfo) { 2417 .type = DATA_CACHE, 2418 .level = 1, 2419 .size = 32 * KiB, 2420 .line_size = 64, 2421 .associativity = 8, 2422 .partitions = 1, 2423 .sets = 64, 2424 .lines_per_tag = 1, 2425 .self_init = 1, 2426 .no_invd_sharing = true, 2427 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2428 }, 2429 .l1i_cache = &(CPUCacheInfo) { 2430 .type = INSTRUCTION_CACHE, 2431 .level = 1, 2432 .size = 32 * KiB, 2433 .line_size = 64, 2434 .associativity = 8, 2435 .partitions = 1, 2436 .sets = 64, 2437 .lines_per_tag = 1, 2438 .self_init = 1, 2439 .no_invd_sharing = true, 2440 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2441 }, 2442 .l2_cache = &(CPUCacheInfo) { 2443 .type = UNIFIED_CACHE, 2444 .level = 2, 2445 .size = 1 * MiB, 2446 .line_size = 64, 2447 .associativity = 8, 2448 .partitions = 1, 2449 .sets = 2048, 2450 .lines_per_tag = 1, 2451 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2452 }, 2453 .l3_cache = &(CPUCacheInfo) { 2454 .type = UNIFIED_CACHE, 2455 .level = 3, 2456 .size = 32 * MiB, 2457 .line_size = 64, 2458 .associativity = 16, 2459 .partitions = 1, 2460 .sets = 32768, 2461 .lines_per_tag = 1, 2462 .self_init = true, 2463 .inclusive = true, 2464 .complex_indexing = false, 2465 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2466 }, 2467 }; 2468 2469 /* The following VMX features are not supported by KVM and are left out in the 2470 * CPU definitions: 2471 * 2472 * Dual-monitor support (all processors) 2473 * Entry to SMM 2474 * Deactivate dual-monitor treatment 2475 * Number of CR3-target values 2476 * Shutdown activity state 2477 * Wait-for-SIPI activity state 2478 * PAUSE-loop exiting (Westmere and newer) 2479 * EPT-violation #VE (Broadwell and newer) 2480 * Inject event with insn length=0 (Skylake and newer) 2481 * Conceal non-root operation from PT 2482 * Conceal VM exits from PT 2483 * Conceal VM entries from PT 2484 * Enable ENCLS exiting 2485 * Mode-based execute control (XS/XU) 2486 * TSC scaling (Skylake Server and newer) 2487 * GPA translation for PT (IceLake and newer) 2488 * User wait and pause 2489 * ENCLV exiting 2490 * Load IA32_RTIT_CTL 2491 * Clear IA32_RTIT_CTL 2492 * Advanced VM-exit information for EPT violations 2493 * Sub-page write permissions 2494 * PT in VMX operation 2495 */ 2496 2497 static const X86CPUDefinition builtin_x86_defs[] = { 2498 { 2499 .name = "qemu64", 2500 .level = 0xd, 2501 .vendor = CPUID_VENDOR_AMD, 2502 .family = 15, 2503 .model = 107, 2504 .stepping = 1, 2505 .features[FEAT_1_EDX] = 2506 PPRO_FEATURES | 2507 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2508 CPUID_PSE36, 2509 .features[FEAT_1_ECX] = 2510 CPUID_EXT_SSE3 | CPUID_EXT_CX16, 2511 .features[FEAT_8000_0001_EDX] = 2512 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2513 .features[FEAT_8000_0001_ECX] = 2514 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM, 2515 .xlevel = 0x8000000A, 2516 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 2517 }, 2518 { 2519 .name = "phenom", 2520 .level = 5, 2521 .vendor = CPUID_VENDOR_AMD, 2522 .family = 16, 2523 .model = 2, 2524 .stepping = 3, 2525 /* Missing: CPUID_HT */ 2526 .features[FEAT_1_EDX] = 2527 PPRO_FEATURES | 2528 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2529 CPUID_PSE36 | CPUID_VME, 2530 .features[FEAT_1_ECX] = 2531 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 | 2532 CPUID_EXT_POPCNT, 2533 .features[FEAT_8000_0001_EDX] = 2534 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | 2535 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT | 2536 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP, 2537 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, 2538 CPUID_EXT3_CR8LEG, 2539 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, 2540 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */ 2541 .features[FEAT_8000_0001_ECX] = 2542 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | 2543 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A, 2544 /* Missing: CPUID_SVM_LBRV */ 2545 .features[FEAT_SVM] = 2546 CPUID_SVM_NPT, 2547 .xlevel = 0x8000001A, 2548 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor" 2549 }, 2550 { 2551 .name = "core2duo", 2552 .level = 10, 2553 .vendor = CPUID_VENDOR_INTEL, 2554 .family = 6, 2555 .model = 15, 2556 .stepping = 11, 2557 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2558 .features[FEAT_1_EDX] = 2559 PPRO_FEATURES | 2560 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2561 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS, 2562 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST, 2563 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */ 2564 .features[FEAT_1_ECX] = 2565 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | 2566 CPUID_EXT_CX16, 2567 .features[FEAT_8000_0001_EDX] = 2568 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2569 .features[FEAT_8000_0001_ECX] = 2570 CPUID_EXT3_LAHF_LM, 2571 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2572 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2573 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2574 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2575 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2576 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2577 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2578 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2579 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2580 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2581 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2582 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2583 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2584 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2585 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2586 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2587 .features[FEAT_VMX_SECONDARY_CTLS] = 2588 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES, 2589 .xlevel = 0x80000008, 2590 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz", 2591 }, 2592 { 2593 .name = "kvm64", 2594 .level = 0xd, 2595 .vendor = CPUID_VENDOR_INTEL, 2596 .family = 15, 2597 .model = 6, 2598 .stepping = 1, 2599 /* Missing: CPUID_HT */ 2600 .features[FEAT_1_EDX] = 2601 PPRO_FEATURES | CPUID_VME | 2602 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2603 CPUID_PSE36, 2604 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */ 2605 .features[FEAT_1_ECX] = 2606 CPUID_EXT_SSE3 | CPUID_EXT_CX16, 2607 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */ 2608 .features[FEAT_8000_0001_EDX] = 2609 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2610 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, 2611 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A, 2612 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, 2613 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */ 2614 .features[FEAT_8000_0001_ECX] = 2615 0, 2616 /* VMX features from Cedar Mill/Prescott */ 2617 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2618 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2619 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2620 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2621 VMX_PIN_BASED_NMI_EXITING, 2622 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2623 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2624 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2625 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2626 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2627 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2628 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2629 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING, 2630 .xlevel = 0x80000008, 2631 .model_id = "Common KVM processor" 2632 }, 2633 { 2634 .name = "qemu32", 2635 .level = 4, 2636 .vendor = CPUID_VENDOR_INTEL, 2637 .family = 6, 2638 .model = 6, 2639 .stepping = 3, 2640 .features[FEAT_1_EDX] = 2641 PPRO_FEATURES, 2642 .features[FEAT_1_ECX] = 2643 CPUID_EXT_SSE3, 2644 .xlevel = 0x80000004, 2645 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 2646 }, 2647 { 2648 .name = "kvm32", 2649 .level = 5, 2650 .vendor = CPUID_VENDOR_INTEL, 2651 .family = 15, 2652 .model = 6, 2653 .stepping = 1, 2654 .features[FEAT_1_EDX] = 2655 PPRO_FEATURES | CPUID_VME | 2656 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36, 2657 .features[FEAT_1_ECX] = 2658 CPUID_EXT_SSE3, 2659 .features[FEAT_8000_0001_ECX] = 2660 0, 2661 /* VMX features from Yonah */ 2662 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2663 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2664 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2665 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2666 VMX_PIN_BASED_NMI_EXITING, 2667 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2668 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2669 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2670 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2671 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 2672 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 2673 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS, 2674 .xlevel = 0x80000008, 2675 .model_id = "Common 32-bit KVM processor" 2676 }, 2677 { 2678 .name = "coreduo", 2679 .level = 10, 2680 .vendor = CPUID_VENDOR_INTEL, 2681 .family = 6, 2682 .model = 14, 2683 .stepping = 8, 2684 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2685 .features[FEAT_1_EDX] = 2686 PPRO_FEATURES | CPUID_VME | 2687 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI | 2688 CPUID_SS, 2689 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR, 2690 * CPUID_EXT_PDCM, CPUID_EXT_VMX */ 2691 .features[FEAT_1_ECX] = 2692 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR, 2693 .features[FEAT_8000_0001_EDX] = 2694 CPUID_EXT2_NX, 2695 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2696 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2697 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2698 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2699 VMX_PIN_BASED_NMI_EXITING, 2700 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2701 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2702 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2703 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2704 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 2705 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 2706 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS, 2707 .xlevel = 0x80000008, 2708 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz", 2709 }, 2710 { 2711 .name = "486", 2712 .level = 1, 2713 .vendor = CPUID_VENDOR_INTEL, 2714 .family = 4, 2715 .model = 8, 2716 .stepping = 0, 2717 .features[FEAT_1_EDX] = 2718 I486_FEATURES, 2719 .xlevel = 0, 2720 .model_id = "", 2721 }, 2722 { 2723 .name = "pentium", 2724 .level = 1, 2725 .vendor = CPUID_VENDOR_INTEL, 2726 .family = 5, 2727 .model = 4, 2728 .stepping = 3, 2729 .features[FEAT_1_EDX] = 2730 PENTIUM_FEATURES, 2731 .xlevel = 0, 2732 .model_id = "", 2733 }, 2734 { 2735 .name = "pentium2", 2736 .level = 2, 2737 .vendor = CPUID_VENDOR_INTEL, 2738 .family = 6, 2739 .model = 5, 2740 .stepping = 2, 2741 .features[FEAT_1_EDX] = 2742 PENTIUM2_FEATURES, 2743 .xlevel = 0, 2744 .model_id = "", 2745 }, 2746 { 2747 .name = "pentium3", 2748 .level = 3, 2749 .vendor = CPUID_VENDOR_INTEL, 2750 .family = 6, 2751 .model = 7, 2752 .stepping = 3, 2753 .features[FEAT_1_EDX] = 2754 PENTIUM3_FEATURES, 2755 .xlevel = 0, 2756 .model_id = "", 2757 }, 2758 { 2759 .name = "athlon", 2760 .level = 2, 2761 .vendor = CPUID_VENDOR_AMD, 2762 .family = 6, 2763 .model = 2, 2764 .stepping = 3, 2765 .features[FEAT_1_EDX] = 2766 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR | 2767 CPUID_MCA, 2768 .features[FEAT_8000_0001_EDX] = 2769 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT, 2770 .xlevel = 0x80000008, 2771 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 2772 }, 2773 { 2774 .name = "n270", 2775 .level = 10, 2776 .vendor = CPUID_VENDOR_INTEL, 2777 .family = 6, 2778 .model = 28, 2779 .stepping = 2, 2780 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2781 .features[FEAT_1_EDX] = 2782 PPRO_FEATURES | 2783 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | 2784 CPUID_ACPI | CPUID_SS, 2785 /* Some CPUs got no CPUID_SEP */ 2786 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2, 2787 * CPUID_EXT_XTPR */ 2788 .features[FEAT_1_ECX] = 2789 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | 2790 CPUID_EXT_MOVBE, 2791 .features[FEAT_8000_0001_EDX] = 2792 CPUID_EXT2_NX, 2793 .features[FEAT_8000_0001_ECX] = 2794 CPUID_EXT3_LAHF_LM, 2795 .xlevel = 0x80000008, 2796 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz", 2797 }, 2798 { 2799 .name = "Conroe", 2800 .level = 10, 2801 .vendor = CPUID_VENDOR_INTEL, 2802 .family = 6, 2803 .model = 15, 2804 .stepping = 3, 2805 .features[FEAT_1_EDX] = 2806 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2807 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2808 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2809 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2810 CPUID_DE | CPUID_FP87, 2811 .features[FEAT_1_ECX] = 2812 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, 2813 .features[FEAT_8000_0001_EDX] = 2814 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 2815 .features[FEAT_8000_0001_ECX] = 2816 CPUID_EXT3_LAHF_LM, 2817 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2818 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2819 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2820 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2821 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2822 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2823 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2824 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2825 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2826 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2827 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2828 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2829 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2830 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2831 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2832 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2833 .features[FEAT_VMX_SECONDARY_CTLS] = 2834 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES, 2835 .xlevel = 0x80000008, 2836 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)", 2837 }, 2838 { 2839 .name = "Penryn", 2840 .level = 10, 2841 .vendor = CPUID_VENDOR_INTEL, 2842 .family = 6, 2843 .model = 23, 2844 .stepping = 3, 2845 .features[FEAT_1_EDX] = 2846 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2847 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2848 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2849 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2850 CPUID_DE | CPUID_FP87, 2851 .features[FEAT_1_ECX] = 2852 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2853 CPUID_EXT_SSE3, 2854 .features[FEAT_8000_0001_EDX] = 2855 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 2856 .features[FEAT_8000_0001_ECX] = 2857 CPUID_EXT3_LAHF_LM, 2858 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2859 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2860 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, 2861 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT | 2862 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL, 2863 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2864 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2865 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2866 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2867 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2868 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2869 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2870 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2871 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2872 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2873 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2874 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2875 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2876 .features[FEAT_VMX_SECONDARY_CTLS] = 2877 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2878 VMX_SECONDARY_EXEC_WBINVD_EXITING, 2879 .xlevel = 0x80000008, 2880 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)", 2881 }, 2882 { 2883 .name = "Nehalem", 2884 .level = 11, 2885 .vendor = CPUID_VENDOR_INTEL, 2886 .family = 6, 2887 .model = 26, 2888 .stepping = 3, 2889 .features[FEAT_1_EDX] = 2890 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2891 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2892 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2893 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2894 CPUID_DE | CPUID_FP87, 2895 .features[FEAT_1_ECX] = 2896 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 2897 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, 2898 .features[FEAT_8000_0001_EDX] = 2899 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2900 .features[FEAT_8000_0001_ECX] = 2901 CPUID_EXT3_LAHF_LM, 2902 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2903 MSR_VMX_BASIC_TRUE_CTLS, 2904 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2905 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2906 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2907 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2908 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2909 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2910 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2911 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2912 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2913 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2914 .features[FEAT_VMX_EXIT_CTLS] = 2915 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2916 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2917 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2918 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2919 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2920 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2921 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2922 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2923 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2924 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2925 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2926 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2927 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2928 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2929 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2930 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2931 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2932 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2933 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2934 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2935 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2936 .features[FEAT_VMX_SECONDARY_CTLS] = 2937 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2938 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2939 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2940 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2941 VMX_SECONDARY_EXEC_ENABLE_VPID, 2942 .xlevel = 0x80000008, 2943 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)", 2944 .versions = (X86CPUVersionDefinition[]) { 2945 { .version = 1 }, 2946 { 2947 .version = 2, 2948 .alias = "Nehalem-IBRS", 2949 .props = (PropValue[]) { 2950 { "spec-ctrl", "on" }, 2951 { "model-id", 2952 "Intel Core i7 9xx (Nehalem Core i7, IBRS update)" }, 2953 { /* end of list */ } 2954 } 2955 }, 2956 { /* end of list */ } 2957 } 2958 }, 2959 { 2960 .name = "Westmere", 2961 .level = 11, 2962 .vendor = CPUID_VENDOR_INTEL, 2963 .family = 6, 2964 .model = 44, 2965 .stepping = 1, 2966 .features[FEAT_1_EDX] = 2967 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2968 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2969 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2970 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2971 CPUID_DE | CPUID_FP87, 2972 .features[FEAT_1_ECX] = 2973 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | 2974 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2975 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 2976 .features[FEAT_8000_0001_EDX] = 2977 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2978 .features[FEAT_8000_0001_ECX] = 2979 CPUID_EXT3_LAHF_LM, 2980 .features[FEAT_6_EAX] = 2981 CPUID_6_EAX_ARAT, 2982 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2983 MSR_VMX_BASIC_TRUE_CTLS, 2984 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2985 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2986 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2987 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2988 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2989 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2990 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2991 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2992 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2993 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2994 .features[FEAT_VMX_EXIT_CTLS] = 2995 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2996 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2997 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2998 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2999 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3000 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3001 MSR_VMX_MISC_STORE_LMA, 3002 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3003 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3004 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 3005 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3006 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3007 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3008 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3009 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3010 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3011 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3012 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3013 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3014 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3015 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3016 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3017 .features[FEAT_VMX_SECONDARY_CTLS] = 3018 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3019 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3020 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3021 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3022 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST, 3023 .xlevel = 0x80000008, 3024 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)", 3025 .versions = (X86CPUVersionDefinition[]) { 3026 { .version = 1 }, 3027 { 3028 .version = 2, 3029 .alias = "Westmere-IBRS", 3030 .props = (PropValue[]) { 3031 { "spec-ctrl", "on" }, 3032 { "model-id", 3033 "Westmere E56xx/L56xx/X56xx (IBRS update)" }, 3034 { /* end of list */ } 3035 } 3036 }, 3037 { /* end of list */ } 3038 } 3039 }, 3040 { 3041 .name = "SandyBridge", 3042 .level = 0xd, 3043 .vendor = CPUID_VENDOR_INTEL, 3044 .family = 6, 3045 .model = 42, 3046 .stepping = 1, 3047 .features[FEAT_1_EDX] = 3048 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3049 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3050 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3051 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3052 CPUID_DE | CPUID_FP87, 3053 .features[FEAT_1_ECX] = 3054 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3055 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | 3056 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 3057 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 3058 CPUID_EXT_SSE3, 3059 .features[FEAT_8000_0001_EDX] = 3060 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3061 CPUID_EXT2_SYSCALL, 3062 .features[FEAT_8000_0001_ECX] = 3063 CPUID_EXT3_LAHF_LM, 3064 .features[FEAT_XSAVE] = 3065 CPUID_XSAVE_XSAVEOPT, 3066 .features[FEAT_6_EAX] = 3067 CPUID_6_EAX_ARAT, 3068 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3069 MSR_VMX_BASIC_TRUE_CTLS, 3070 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3071 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3072 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3073 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3074 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3075 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3076 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3077 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3078 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3079 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 3080 .features[FEAT_VMX_EXIT_CTLS] = 3081 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3082 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3083 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3084 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3085 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3086 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3087 MSR_VMX_MISC_STORE_LMA, 3088 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3089 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3090 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 3091 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3092 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3093 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3094 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3095 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3096 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3097 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3098 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3099 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3100 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3101 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3102 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3103 .features[FEAT_VMX_SECONDARY_CTLS] = 3104 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3105 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3106 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3107 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3108 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST, 3109 .xlevel = 0x80000008, 3110 .model_id = "Intel Xeon E312xx (Sandy Bridge)", 3111 .versions = (X86CPUVersionDefinition[]) { 3112 { .version = 1 }, 3113 { 3114 .version = 2, 3115 .alias = "SandyBridge-IBRS", 3116 .props = (PropValue[]) { 3117 { "spec-ctrl", "on" }, 3118 { "model-id", 3119 "Intel Xeon E312xx (Sandy Bridge, IBRS update)" }, 3120 { /* end of list */ } 3121 } 3122 }, 3123 { /* end of list */ } 3124 } 3125 }, 3126 { 3127 .name = "IvyBridge", 3128 .level = 0xd, 3129 .vendor = CPUID_VENDOR_INTEL, 3130 .family = 6, 3131 .model = 58, 3132 .stepping = 9, 3133 .features[FEAT_1_EDX] = 3134 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3135 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3136 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3137 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3138 CPUID_DE | CPUID_FP87, 3139 .features[FEAT_1_ECX] = 3140 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3141 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | 3142 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 3143 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 3144 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3145 .features[FEAT_7_0_EBX] = 3146 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | 3147 CPUID_7_0_EBX_ERMS, 3148 .features[FEAT_8000_0001_EDX] = 3149 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3150 CPUID_EXT2_SYSCALL, 3151 .features[FEAT_8000_0001_ECX] = 3152 CPUID_EXT3_LAHF_LM, 3153 .features[FEAT_XSAVE] = 3154 CPUID_XSAVE_XSAVEOPT, 3155 .features[FEAT_6_EAX] = 3156 CPUID_6_EAX_ARAT, 3157 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3158 MSR_VMX_BASIC_TRUE_CTLS, 3159 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3160 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3161 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3162 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3163 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3164 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3165 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3166 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3167 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3168 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 3169 .features[FEAT_VMX_EXIT_CTLS] = 3170 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3171 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3172 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3173 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3174 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3175 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3176 MSR_VMX_MISC_STORE_LMA, 3177 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3178 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3179 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3180 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3181 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3182 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3183 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3184 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3185 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3186 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3187 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3188 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3189 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3190 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3191 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3192 .features[FEAT_VMX_SECONDARY_CTLS] = 3193 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3194 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3195 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3196 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3197 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3198 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3199 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3200 VMX_SECONDARY_EXEC_RDRAND_EXITING, 3201 .xlevel = 0x80000008, 3202 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)", 3203 .versions = (X86CPUVersionDefinition[]) { 3204 { .version = 1 }, 3205 { 3206 .version = 2, 3207 .alias = "IvyBridge-IBRS", 3208 .props = (PropValue[]) { 3209 { "spec-ctrl", "on" }, 3210 { "model-id", 3211 "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)" }, 3212 { /* end of list */ } 3213 } 3214 }, 3215 { /* end of list */ } 3216 } 3217 }, 3218 { 3219 .name = "Haswell", 3220 .level = 0xd, 3221 .vendor = CPUID_VENDOR_INTEL, 3222 .family = 6, 3223 .model = 60, 3224 .stepping = 4, 3225 .features[FEAT_1_EDX] = 3226 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3227 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3228 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3229 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3230 CPUID_DE | CPUID_FP87, 3231 .features[FEAT_1_ECX] = 3232 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3233 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3234 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3235 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3236 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3237 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3238 .features[FEAT_8000_0001_EDX] = 3239 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3240 CPUID_EXT2_SYSCALL, 3241 .features[FEAT_8000_0001_ECX] = 3242 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM, 3243 .features[FEAT_7_0_EBX] = 3244 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3245 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3246 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3247 CPUID_7_0_EBX_RTM, 3248 .features[FEAT_XSAVE] = 3249 CPUID_XSAVE_XSAVEOPT, 3250 .features[FEAT_6_EAX] = 3251 CPUID_6_EAX_ARAT, 3252 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3253 MSR_VMX_BASIC_TRUE_CTLS, 3254 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3255 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3256 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3257 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3258 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3259 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3260 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3261 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3262 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3263 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3264 .features[FEAT_VMX_EXIT_CTLS] = 3265 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3266 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3267 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3268 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3269 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3270 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3271 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3272 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3273 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3274 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3275 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3276 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3277 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3278 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3279 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3280 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3281 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3282 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3283 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3284 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3285 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3286 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3287 .features[FEAT_VMX_SECONDARY_CTLS] = 3288 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3289 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3290 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3291 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3292 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3293 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3294 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3295 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3296 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS, 3297 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3298 .xlevel = 0x80000008, 3299 .model_id = "Intel Core Processor (Haswell)", 3300 .versions = (X86CPUVersionDefinition[]) { 3301 { .version = 1 }, 3302 { 3303 .version = 2, 3304 .alias = "Haswell-noTSX", 3305 .props = (PropValue[]) { 3306 { "hle", "off" }, 3307 { "rtm", "off" }, 3308 { "stepping", "1" }, 3309 { "model-id", "Intel Core Processor (Haswell, no TSX)", }, 3310 { /* end of list */ } 3311 }, 3312 }, 3313 { 3314 .version = 3, 3315 .alias = "Haswell-IBRS", 3316 .props = (PropValue[]) { 3317 /* Restore TSX features removed by -v2 above */ 3318 { "hle", "on" }, 3319 { "rtm", "on" }, 3320 /* 3321 * Haswell and Haswell-IBRS had stepping=4 in 3322 * QEMU 4.0 and older 3323 */ 3324 { "stepping", "4" }, 3325 { "spec-ctrl", "on" }, 3326 { "model-id", 3327 "Intel Core Processor (Haswell, IBRS)" }, 3328 { /* end of list */ } 3329 } 3330 }, 3331 { 3332 .version = 4, 3333 .alias = "Haswell-noTSX-IBRS", 3334 .props = (PropValue[]) { 3335 { "hle", "off" }, 3336 { "rtm", "off" }, 3337 /* spec-ctrl was already enabled by -v3 above */ 3338 { "stepping", "1" }, 3339 { "model-id", 3340 "Intel Core Processor (Haswell, no TSX, IBRS)" }, 3341 { /* end of list */ } 3342 } 3343 }, 3344 { /* end of list */ } 3345 } 3346 }, 3347 { 3348 .name = "Broadwell", 3349 .level = 0xd, 3350 .vendor = CPUID_VENDOR_INTEL, 3351 .family = 6, 3352 .model = 61, 3353 .stepping = 2, 3354 .features[FEAT_1_EDX] = 3355 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3356 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3357 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3358 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3359 CPUID_DE | CPUID_FP87, 3360 .features[FEAT_1_ECX] = 3361 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3362 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3363 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3364 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3365 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3366 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3367 .features[FEAT_8000_0001_EDX] = 3368 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3369 CPUID_EXT2_SYSCALL, 3370 .features[FEAT_8000_0001_ECX] = 3371 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3372 .features[FEAT_7_0_EBX] = 3373 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3374 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3375 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3376 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3377 CPUID_7_0_EBX_SMAP, 3378 .features[FEAT_XSAVE] = 3379 CPUID_XSAVE_XSAVEOPT, 3380 .features[FEAT_6_EAX] = 3381 CPUID_6_EAX_ARAT, 3382 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3383 MSR_VMX_BASIC_TRUE_CTLS, 3384 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3385 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3386 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3387 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3388 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3389 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3390 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3391 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3392 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3393 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3394 .features[FEAT_VMX_EXIT_CTLS] = 3395 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3396 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3397 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3398 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3399 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3400 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3401 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3402 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3403 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3404 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3405 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3406 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3407 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3408 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3409 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3410 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3411 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3412 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3413 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3414 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3415 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3416 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3417 .features[FEAT_VMX_SECONDARY_CTLS] = 3418 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3419 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3420 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3421 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3422 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3423 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3424 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3425 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3426 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3427 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3428 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3429 .xlevel = 0x80000008, 3430 .model_id = "Intel Core Processor (Broadwell)", 3431 .versions = (X86CPUVersionDefinition[]) { 3432 { .version = 1 }, 3433 { 3434 .version = 2, 3435 .alias = "Broadwell-noTSX", 3436 .props = (PropValue[]) { 3437 { "hle", "off" }, 3438 { "rtm", "off" }, 3439 { "model-id", "Intel Core Processor (Broadwell, no TSX)", }, 3440 { /* end of list */ } 3441 }, 3442 }, 3443 { 3444 .version = 3, 3445 .alias = "Broadwell-IBRS", 3446 .props = (PropValue[]) { 3447 /* Restore TSX features removed by -v2 above */ 3448 { "hle", "on" }, 3449 { "rtm", "on" }, 3450 { "spec-ctrl", "on" }, 3451 { "model-id", 3452 "Intel Core Processor (Broadwell, IBRS)" }, 3453 { /* end of list */ } 3454 } 3455 }, 3456 { 3457 .version = 4, 3458 .alias = "Broadwell-noTSX-IBRS", 3459 .props = (PropValue[]) { 3460 { "hle", "off" }, 3461 { "rtm", "off" }, 3462 /* spec-ctrl was already enabled by -v3 above */ 3463 { "model-id", 3464 "Intel Core Processor (Broadwell, no TSX, IBRS)" }, 3465 { /* end of list */ } 3466 } 3467 }, 3468 { /* end of list */ } 3469 } 3470 }, 3471 { 3472 .name = "Skylake-Client", 3473 .level = 0xd, 3474 .vendor = CPUID_VENDOR_INTEL, 3475 .family = 6, 3476 .model = 94, 3477 .stepping = 3, 3478 .features[FEAT_1_EDX] = 3479 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3480 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3481 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3482 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3483 CPUID_DE | CPUID_FP87, 3484 .features[FEAT_1_ECX] = 3485 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3486 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3487 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3488 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3489 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3490 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3491 .features[FEAT_8000_0001_EDX] = 3492 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3493 CPUID_EXT2_SYSCALL, 3494 .features[FEAT_8000_0001_ECX] = 3495 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3496 .features[FEAT_7_0_EBX] = 3497 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3498 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3499 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3500 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3501 CPUID_7_0_EBX_SMAP, 3502 /* XSAVES is added in version 4 */ 3503 .features[FEAT_XSAVE] = 3504 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3505 CPUID_XSAVE_XGETBV1, 3506 .features[FEAT_6_EAX] = 3507 CPUID_6_EAX_ARAT, 3508 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3509 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3510 MSR_VMX_BASIC_TRUE_CTLS, 3511 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3512 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3513 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3514 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3515 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3516 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3517 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3518 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3519 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3520 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3521 .features[FEAT_VMX_EXIT_CTLS] = 3522 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3523 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3524 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3525 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3526 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3527 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3528 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3529 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3530 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3531 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 3532 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3533 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3534 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3535 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3536 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3537 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3538 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3539 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3540 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3541 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3542 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3543 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3544 .features[FEAT_VMX_SECONDARY_CTLS] = 3545 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3546 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3547 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3548 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3549 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3550 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3551 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3552 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3553 .xlevel = 0x80000008, 3554 .model_id = "Intel Core Processor (Skylake)", 3555 .versions = (X86CPUVersionDefinition[]) { 3556 { .version = 1 }, 3557 { 3558 .version = 2, 3559 .alias = "Skylake-Client-IBRS", 3560 .props = (PropValue[]) { 3561 { "spec-ctrl", "on" }, 3562 { "model-id", 3563 "Intel Core Processor (Skylake, IBRS)" }, 3564 { /* end of list */ } 3565 } 3566 }, 3567 { 3568 .version = 3, 3569 .alias = "Skylake-Client-noTSX-IBRS", 3570 .props = (PropValue[]) { 3571 { "hle", "off" }, 3572 { "rtm", "off" }, 3573 { "model-id", 3574 "Intel Core Processor (Skylake, IBRS, no TSX)" }, 3575 { /* end of list */ } 3576 } 3577 }, 3578 { 3579 .version = 4, 3580 .note = "IBRS, XSAVES, no TSX", 3581 .props = (PropValue[]) { 3582 { "xsaves", "on" }, 3583 { "vmx-xsaves", "on" }, 3584 { /* end of list */ } 3585 } 3586 }, 3587 { /* end of list */ } 3588 } 3589 }, 3590 { 3591 .name = "Skylake-Server", 3592 .level = 0xd, 3593 .vendor = CPUID_VENDOR_INTEL, 3594 .family = 6, 3595 .model = 85, 3596 .stepping = 4, 3597 .features[FEAT_1_EDX] = 3598 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3599 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3600 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3601 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3602 CPUID_DE | CPUID_FP87, 3603 .features[FEAT_1_ECX] = 3604 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3605 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3606 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3607 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3608 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3609 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3610 .features[FEAT_8000_0001_EDX] = 3611 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3612 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3613 .features[FEAT_8000_0001_ECX] = 3614 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3615 .features[FEAT_7_0_EBX] = 3616 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3617 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3618 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3619 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3620 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3621 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3622 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3623 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3624 .features[FEAT_7_0_ECX] = 3625 CPUID_7_0_ECX_PKU, 3626 /* XSAVES is added in version 5 */ 3627 .features[FEAT_XSAVE] = 3628 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3629 CPUID_XSAVE_XGETBV1, 3630 .features[FEAT_6_EAX] = 3631 CPUID_6_EAX_ARAT, 3632 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3633 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3634 MSR_VMX_BASIC_TRUE_CTLS, 3635 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3636 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3637 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3638 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3639 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3640 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3641 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3642 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3643 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3644 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3645 .features[FEAT_VMX_EXIT_CTLS] = 3646 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3647 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3648 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3649 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3650 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3651 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3652 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3653 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3654 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3655 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3656 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3657 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3658 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3659 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3660 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3661 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3662 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3663 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3664 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3665 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3666 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3667 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3668 .features[FEAT_VMX_SECONDARY_CTLS] = 3669 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3670 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3671 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3672 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3673 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3674 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3675 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3676 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3677 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3678 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3679 .xlevel = 0x80000008, 3680 .model_id = "Intel Xeon Processor (Skylake)", 3681 .versions = (X86CPUVersionDefinition[]) { 3682 { .version = 1 }, 3683 { 3684 .version = 2, 3685 .alias = "Skylake-Server-IBRS", 3686 .props = (PropValue[]) { 3687 /* clflushopt was not added to Skylake-Server-IBRS */ 3688 /* TODO: add -v3 including clflushopt */ 3689 { "clflushopt", "off" }, 3690 { "spec-ctrl", "on" }, 3691 { "model-id", 3692 "Intel Xeon Processor (Skylake, IBRS)" }, 3693 { /* end of list */ } 3694 } 3695 }, 3696 { 3697 .version = 3, 3698 .alias = "Skylake-Server-noTSX-IBRS", 3699 .props = (PropValue[]) { 3700 { "hle", "off" }, 3701 { "rtm", "off" }, 3702 { "model-id", 3703 "Intel Xeon Processor (Skylake, IBRS, no TSX)" }, 3704 { /* end of list */ } 3705 } 3706 }, 3707 { 3708 .version = 4, 3709 .note = "IBRS, EPT switching, no TSX", 3710 .props = (PropValue[]) { 3711 { "vmx-eptp-switching", "on" }, 3712 { /* end of list */ } 3713 } 3714 }, 3715 { 3716 .version = 5, 3717 .note = "IBRS, XSAVES, EPT switching, no TSX", 3718 .props = (PropValue[]) { 3719 { "xsaves", "on" }, 3720 { "vmx-xsaves", "on" }, 3721 { /* end of list */ } 3722 } 3723 }, 3724 { /* end of list */ } 3725 } 3726 }, 3727 { 3728 .name = "Cascadelake-Server", 3729 .level = 0xd, 3730 .vendor = CPUID_VENDOR_INTEL, 3731 .family = 6, 3732 .model = 85, 3733 .stepping = 6, 3734 .features[FEAT_1_EDX] = 3735 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3736 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3737 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3738 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3739 CPUID_DE | CPUID_FP87, 3740 .features[FEAT_1_ECX] = 3741 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3742 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3743 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3744 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3745 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3746 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3747 .features[FEAT_8000_0001_EDX] = 3748 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3749 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3750 .features[FEAT_8000_0001_ECX] = 3751 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3752 .features[FEAT_7_0_EBX] = 3753 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3754 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3755 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3756 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3757 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3758 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3759 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3760 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3761 .features[FEAT_7_0_ECX] = 3762 CPUID_7_0_ECX_PKU | 3763 CPUID_7_0_ECX_AVX512VNNI, 3764 .features[FEAT_7_0_EDX] = 3765 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 3766 /* XSAVES is added in version 5 */ 3767 .features[FEAT_XSAVE] = 3768 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3769 CPUID_XSAVE_XGETBV1, 3770 .features[FEAT_6_EAX] = 3771 CPUID_6_EAX_ARAT, 3772 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3773 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3774 MSR_VMX_BASIC_TRUE_CTLS, 3775 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3776 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3777 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3778 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3779 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3780 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3781 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3782 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3783 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3784 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3785 .features[FEAT_VMX_EXIT_CTLS] = 3786 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3787 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3788 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3789 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3790 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3791 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3792 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3793 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3794 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3795 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3796 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3797 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3798 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3799 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3800 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3801 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3802 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3803 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3804 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3805 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3806 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3807 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3808 .features[FEAT_VMX_SECONDARY_CTLS] = 3809 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3810 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3811 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3812 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3813 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3814 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3815 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3816 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3817 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3818 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3819 .xlevel = 0x80000008, 3820 .model_id = "Intel Xeon Processor (Cascadelake)", 3821 .versions = (X86CPUVersionDefinition[]) { 3822 { .version = 1 }, 3823 { .version = 2, 3824 .note = "ARCH_CAPABILITIES", 3825 .props = (PropValue[]) { 3826 { "arch-capabilities", "on" }, 3827 { "rdctl-no", "on" }, 3828 { "ibrs-all", "on" }, 3829 { "skip-l1dfl-vmentry", "on" }, 3830 { "mds-no", "on" }, 3831 { /* end of list */ } 3832 }, 3833 }, 3834 { .version = 3, 3835 .alias = "Cascadelake-Server-noTSX", 3836 .note = "ARCH_CAPABILITIES, no TSX", 3837 .props = (PropValue[]) { 3838 { "hle", "off" }, 3839 { "rtm", "off" }, 3840 { /* end of list */ } 3841 }, 3842 }, 3843 { .version = 4, 3844 .note = "ARCH_CAPABILITIES, EPT switching, no TSX", 3845 .props = (PropValue[]) { 3846 { "vmx-eptp-switching", "on" }, 3847 { /* end of list */ } 3848 }, 3849 }, 3850 { .version = 5, 3851 .note = "ARCH_CAPABILITIES, EPT switching, XSAVES, no TSX", 3852 .props = (PropValue[]) { 3853 { "xsaves", "on" }, 3854 { "vmx-xsaves", "on" }, 3855 { /* end of list */ } 3856 }, 3857 }, 3858 { /* end of list */ } 3859 } 3860 }, 3861 { 3862 .name = "Cooperlake", 3863 .level = 0xd, 3864 .vendor = CPUID_VENDOR_INTEL, 3865 .family = 6, 3866 .model = 85, 3867 .stepping = 10, 3868 .features[FEAT_1_EDX] = 3869 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3870 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3871 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3872 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3873 CPUID_DE | CPUID_FP87, 3874 .features[FEAT_1_ECX] = 3875 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3876 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3877 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3878 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3879 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3880 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3881 .features[FEAT_8000_0001_EDX] = 3882 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3883 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3884 .features[FEAT_8000_0001_ECX] = 3885 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3886 .features[FEAT_7_0_EBX] = 3887 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3888 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3889 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3890 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3891 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3892 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3893 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3894 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3895 .features[FEAT_7_0_ECX] = 3896 CPUID_7_0_ECX_PKU | 3897 CPUID_7_0_ECX_AVX512VNNI, 3898 .features[FEAT_7_0_EDX] = 3899 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_STIBP | 3900 CPUID_7_0_EDX_SPEC_CTRL_SSBD | CPUID_7_0_EDX_ARCH_CAPABILITIES, 3901 .features[FEAT_ARCH_CAPABILITIES] = 3902 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 3903 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 3904 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO, 3905 .features[FEAT_7_1_EAX] = 3906 CPUID_7_1_EAX_AVX512_BF16, 3907 /* XSAVES is added in version 2 */ 3908 .features[FEAT_XSAVE] = 3909 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3910 CPUID_XSAVE_XGETBV1, 3911 .features[FEAT_6_EAX] = 3912 CPUID_6_EAX_ARAT, 3913 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3914 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3915 MSR_VMX_BASIC_TRUE_CTLS, 3916 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3917 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3918 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3919 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3920 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3921 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3922 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3923 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3924 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3925 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3926 .features[FEAT_VMX_EXIT_CTLS] = 3927 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3928 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3929 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3930 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3931 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3932 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3933 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3934 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3935 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3936 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3937 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3938 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3939 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3940 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3941 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3942 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3943 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3944 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3945 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3946 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3947 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3948 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3949 .features[FEAT_VMX_SECONDARY_CTLS] = 3950 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3951 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3952 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3953 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3954 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3955 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3956 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3957 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3958 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3959 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3960 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3961 .xlevel = 0x80000008, 3962 .model_id = "Intel Xeon Processor (Cooperlake)", 3963 .versions = (X86CPUVersionDefinition[]) { 3964 { .version = 1 }, 3965 { .version = 2, 3966 .note = "XSAVES", 3967 .props = (PropValue[]) { 3968 { "xsaves", "on" }, 3969 { "vmx-xsaves", "on" }, 3970 { /* end of list */ } 3971 }, 3972 }, 3973 { /* end of list */ } 3974 } 3975 }, 3976 { 3977 .name = "Icelake-Server", 3978 .level = 0xd, 3979 .vendor = CPUID_VENDOR_INTEL, 3980 .family = 6, 3981 .model = 134, 3982 .stepping = 0, 3983 .features[FEAT_1_EDX] = 3984 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3985 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3986 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3987 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3988 CPUID_DE | CPUID_FP87, 3989 .features[FEAT_1_ECX] = 3990 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3991 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3992 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3993 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3994 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3995 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3996 .features[FEAT_8000_0001_EDX] = 3997 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3998 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3999 .features[FEAT_8000_0001_ECX] = 4000 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 4001 .features[FEAT_8000_0008_EBX] = 4002 CPUID_8000_0008_EBX_WBNOINVD, 4003 .features[FEAT_7_0_EBX] = 4004 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 4005 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 4006 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 4007 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 4008 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 4009 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 4010 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 4011 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 4012 .features[FEAT_7_0_ECX] = 4013 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 4014 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 4015 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4016 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 4017 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57, 4018 .features[FEAT_7_0_EDX] = 4019 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4020 /* XSAVES is added in version 5 */ 4021 .features[FEAT_XSAVE] = 4022 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4023 CPUID_XSAVE_XGETBV1, 4024 .features[FEAT_6_EAX] = 4025 CPUID_6_EAX_ARAT, 4026 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 4027 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 4028 MSR_VMX_BASIC_TRUE_CTLS, 4029 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 4030 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 4031 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 4032 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 4033 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 4034 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 4035 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4036 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4037 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4038 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 4039 .features[FEAT_VMX_EXIT_CTLS] = 4040 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4041 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4042 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 4043 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4044 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4045 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 4046 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 4047 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 4048 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 4049 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 4050 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4051 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4052 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4053 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4054 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4055 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 4056 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 4057 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 4058 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 4059 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4060 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4061 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4062 .features[FEAT_VMX_SECONDARY_CTLS] = 4063 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4064 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 4065 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 4066 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4067 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4068 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4069 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4070 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4071 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS, 4072 .xlevel = 0x80000008, 4073 .model_id = "Intel Xeon Processor (Icelake)", 4074 .versions = (X86CPUVersionDefinition[]) { 4075 { .version = 1 }, 4076 { 4077 .version = 2, 4078 .note = "no TSX", 4079 .alias = "Icelake-Server-noTSX", 4080 .props = (PropValue[]) { 4081 { "hle", "off" }, 4082 { "rtm", "off" }, 4083 { /* end of list */ } 4084 }, 4085 }, 4086 { 4087 .version = 3, 4088 .props = (PropValue[]) { 4089 { "arch-capabilities", "on" }, 4090 { "rdctl-no", "on" }, 4091 { "ibrs-all", "on" }, 4092 { "skip-l1dfl-vmentry", "on" }, 4093 { "mds-no", "on" }, 4094 { "pschange-mc-no", "on" }, 4095 { "taa-no", "on" }, 4096 { /* end of list */ } 4097 }, 4098 }, 4099 { 4100 .version = 4, 4101 .props = (PropValue[]) { 4102 { "sha-ni", "on" }, 4103 { "avx512ifma", "on" }, 4104 { "rdpid", "on" }, 4105 { "fsrm", "on" }, 4106 { "vmx-rdseed-exit", "on" }, 4107 { "vmx-pml", "on" }, 4108 { "vmx-eptp-switching", "on" }, 4109 { "model", "106" }, 4110 { /* end of list */ } 4111 }, 4112 }, 4113 { 4114 .version = 5, 4115 .note = "XSAVES", 4116 .props = (PropValue[]) { 4117 { "xsaves", "on" }, 4118 { "vmx-xsaves", "on" }, 4119 { /* end of list */ } 4120 }, 4121 }, 4122 { 4123 .version = 6, 4124 .note = "5-level EPT", 4125 .props = (PropValue[]) { 4126 { "vmx-page-walk-5", "on" }, 4127 { /* end of list */ } 4128 }, 4129 }, 4130 { 4131 .version = 7, 4132 .note = "TSX, taa-no", 4133 .props = (PropValue[]) { 4134 /* Restore TSX features removed by -v2 above */ 4135 { "hle", "on" }, 4136 { "rtm", "on" }, 4137 { /* end of list */ } 4138 }, 4139 }, 4140 { /* end of list */ } 4141 } 4142 }, 4143 { 4144 .name = "SapphireRapids", 4145 .level = 0x20, 4146 .vendor = CPUID_VENDOR_INTEL, 4147 .family = 6, 4148 .model = 143, 4149 .stepping = 4, 4150 /* 4151 * please keep the ascending order so that we can have a clear view of 4152 * bit position of each feature. 4153 */ 4154 .features[FEAT_1_EDX] = 4155 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4156 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4157 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4158 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4159 CPUID_SSE | CPUID_SSE2, 4160 .features[FEAT_1_ECX] = 4161 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 4162 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 4163 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4164 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 4165 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4166 .features[FEAT_8000_0001_EDX] = 4167 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4168 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4169 .features[FEAT_8000_0001_ECX] = 4170 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 4171 .features[FEAT_8000_0008_EBX] = 4172 CPUID_8000_0008_EBX_WBNOINVD, 4173 .features[FEAT_7_0_EBX] = 4174 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_HLE | 4175 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | 4176 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RTM | 4177 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 4178 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | 4179 CPUID_7_0_EBX_AVX512IFMA | CPUID_7_0_EBX_CLFLUSHOPT | 4180 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | 4181 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, 4182 .features[FEAT_7_0_ECX] = 4183 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 4184 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 4185 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4186 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 4187 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | 4188 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT, 4189 .features[FEAT_7_0_EDX] = 4190 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 4191 CPUID_7_0_EDX_TSX_LDTRK | CPUID_7_0_EDX_AMX_BF16 | 4192 CPUID_7_0_EDX_AVX512_FP16 | CPUID_7_0_EDX_AMX_TILE | 4193 CPUID_7_0_EDX_AMX_INT8 | CPUID_7_0_EDX_SPEC_CTRL | 4194 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4195 .features[FEAT_ARCH_CAPABILITIES] = 4196 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 4197 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 4198 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO, 4199 .features[FEAT_XSAVE] = 4200 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4201 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES | CPUID_D_1_EAX_XFD, 4202 .features[FEAT_6_EAX] = 4203 CPUID_6_EAX_ARAT, 4204 .features[FEAT_7_1_EAX] = 4205 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_AVX512_BF16 | 4206 CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC, 4207 .features[FEAT_VMX_BASIC] = 4208 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 4209 .features[FEAT_VMX_ENTRY_CTLS] = 4210 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 4211 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 4212 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 4213 .features[FEAT_VMX_EPT_VPID_CAPS] = 4214 MSR_VMX_EPT_EXECONLY | 4215 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_PAGE_WALK_LENGTH_5 | 4216 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 4217 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 4218 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4219 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4220 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 4221 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4222 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 4223 .features[FEAT_VMX_EXIT_CTLS] = 4224 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4225 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4226 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 4227 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4228 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4229 .features[FEAT_VMX_MISC] = 4230 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 4231 MSR_VMX_MISC_VMWRITE_VMEXIT, 4232 .features[FEAT_VMX_PINBASED_CTLS] = 4233 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 4234 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 4235 VMX_PIN_BASED_POSTED_INTR, 4236 .features[FEAT_VMX_PROCBASED_CTLS] = 4237 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4238 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4239 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4240 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4241 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4242 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4243 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 4244 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 4245 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4246 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 4247 VMX_CPU_BASED_PAUSE_EXITING | 4248 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4249 .features[FEAT_VMX_SECONDARY_CTLS] = 4250 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4251 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 4252 VMX_SECONDARY_EXEC_RDTSCP | 4253 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4254 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 4255 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4256 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4257 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4258 VMX_SECONDARY_EXEC_RDRAND_EXITING | 4259 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4260 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4261 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 4262 VMX_SECONDARY_EXEC_XSAVES, 4263 .features[FEAT_VMX_VMFUNC] = 4264 MSR_VMX_VMFUNC_EPT_SWITCHING, 4265 .xlevel = 0x80000008, 4266 .model_id = "Intel Xeon Processor (SapphireRapids)", 4267 .versions = (X86CPUVersionDefinition[]) { 4268 { .version = 1 }, 4269 { 4270 .version = 2, 4271 .props = (PropValue[]) { 4272 { "sbdr-ssdp-no", "on" }, 4273 { "fbsdp-no", "on" }, 4274 { "psdp-no", "on" }, 4275 { /* end of list */ } 4276 } 4277 }, 4278 { 4279 .version = 3, 4280 .props = (PropValue[]) { 4281 { "ss", "on" }, 4282 { "tsc-adjust", "on" }, 4283 { "cldemote", "on" }, 4284 { "movdiri", "on" }, 4285 { "movdir64b", "on" }, 4286 { /* end of list */ } 4287 } 4288 }, 4289 { /* end of list */ } 4290 } 4291 }, 4292 { 4293 .name = "GraniteRapids", 4294 .level = 0x20, 4295 .vendor = CPUID_VENDOR_INTEL, 4296 .family = 6, 4297 .model = 173, 4298 .stepping = 0, 4299 /* 4300 * please keep the ascending order so that we can have a clear view of 4301 * bit position of each feature. 4302 */ 4303 .features[FEAT_1_EDX] = 4304 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4305 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4306 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4307 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4308 CPUID_SSE | CPUID_SSE2, 4309 .features[FEAT_1_ECX] = 4310 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 4311 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 4312 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4313 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 4314 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4315 .features[FEAT_8000_0001_EDX] = 4316 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4317 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4318 .features[FEAT_8000_0001_ECX] = 4319 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 4320 .features[FEAT_8000_0008_EBX] = 4321 CPUID_8000_0008_EBX_WBNOINVD, 4322 .features[FEAT_7_0_EBX] = 4323 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_HLE | 4324 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | 4325 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RTM | 4326 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 4327 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | 4328 CPUID_7_0_EBX_AVX512IFMA | CPUID_7_0_EBX_CLFLUSHOPT | 4329 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | 4330 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, 4331 .features[FEAT_7_0_ECX] = 4332 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 4333 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 4334 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4335 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 4336 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | 4337 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT, 4338 .features[FEAT_7_0_EDX] = 4339 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 4340 CPUID_7_0_EDX_TSX_LDTRK | CPUID_7_0_EDX_AMX_BF16 | 4341 CPUID_7_0_EDX_AVX512_FP16 | CPUID_7_0_EDX_AMX_TILE | 4342 CPUID_7_0_EDX_AMX_INT8 | CPUID_7_0_EDX_SPEC_CTRL | 4343 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4344 .features[FEAT_ARCH_CAPABILITIES] = 4345 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 4346 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 4347 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO | 4348 MSR_ARCH_CAP_SBDR_SSDP_NO | MSR_ARCH_CAP_FBSDP_NO | 4349 MSR_ARCH_CAP_PSDP_NO | MSR_ARCH_CAP_PBRSB_NO, 4350 .features[FEAT_XSAVE] = 4351 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4352 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES | CPUID_D_1_EAX_XFD, 4353 .features[FEAT_6_EAX] = 4354 CPUID_6_EAX_ARAT, 4355 .features[FEAT_7_1_EAX] = 4356 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_AVX512_BF16 | 4357 CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC | 4358 CPUID_7_1_EAX_AMX_FP16, 4359 .features[FEAT_7_1_EDX] = 4360 CPUID_7_1_EDX_PREFETCHITI, 4361 .features[FEAT_7_2_EDX] = 4362 CPUID_7_2_EDX_MCDT_NO, 4363 .features[FEAT_VMX_BASIC] = 4364 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 4365 .features[FEAT_VMX_ENTRY_CTLS] = 4366 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 4367 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 4368 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 4369 .features[FEAT_VMX_EPT_VPID_CAPS] = 4370 MSR_VMX_EPT_EXECONLY | 4371 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_PAGE_WALK_LENGTH_5 | 4372 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 4373 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 4374 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4375 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4376 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 4377 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4378 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 4379 .features[FEAT_VMX_EXIT_CTLS] = 4380 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4381 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4382 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 4383 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4384 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4385 .features[FEAT_VMX_MISC] = 4386 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 4387 MSR_VMX_MISC_VMWRITE_VMEXIT, 4388 .features[FEAT_VMX_PINBASED_CTLS] = 4389 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 4390 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 4391 VMX_PIN_BASED_POSTED_INTR, 4392 .features[FEAT_VMX_PROCBASED_CTLS] = 4393 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4394 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4395 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4396 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4397 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4398 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4399 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 4400 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 4401 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4402 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 4403 VMX_CPU_BASED_PAUSE_EXITING | 4404 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4405 .features[FEAT_VMX_SECONDARY_CTLS] = 4406 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4407 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 4408 VMX_SECONDARY_EXEC_RDTSCP | 4409 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4410 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 4411 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4412 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4413 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4414 VMX_SECONDARY_EXEC_RDRAND_EXITING | 4415 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4416 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4417 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 4418 VMX_SECONDARY_EXEC_XSAVES, 4419 .features[FEAT_VMX_VMFUNC] = 4420 MSR_VMX_VMFUNC_EPT_SWITCHING, 4421 .xlevel = 0x80000008, 4422 .model_id = "Intel Xeon Processor (GraniteRapids)", 4423 .versions = (X86CPUVersionDefinition[]) { 4424 { .version = 1 }, 4425 { 4426 .version = 2, 4427 .props = (PropValue[]) { 4428 { "ss", "on" }, 4429 { "tsc-adjust", "on" }, 4430 { "cldemote", "on" }, 4431 { "movdiri", "on" }, 4432 { "movdir64b", "on" }, 4433 { "avx10", "on" }, 4434 { "avx10-128", "on" }, 4435 { "avx10-256", "on" }, 4436 { "avx10-512", "on" }, 4437 { "avx10-version", "1" }, 4438 { "stepping", "1" }, 4439 { /* end of list */ } 4440 } 4441 }, 4442 { /* end of list */ }, 4443 }, 4444 }, 4445 { 4446 .name = "SierraForest", 4447 .level = 0x23, 4448 .vendor = CPUID_VENDOR_INTEL, 4449 .family = 6, 4450 .model = 175, 4451 .stepping = 0, 4452 /* 4453 * please keep the ascending order so that we can have a clear view of 4454 * bit position of each feature. 4455 */ 4456 .features[FEAT_1_EDX] = 4457 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4458 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4459 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4460 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4461 CPUID_SSE | CPUID_SSE2, 4462 .features[FEAT_1_ECX] = 4463 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 4464 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 4465 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4466 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 4467 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4468 .features[FEAT_8000_0001_EDX] = 4469 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4470 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4471 .features[FEAT_8000_0001_ECX] = 4472 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 4473 .features[FEAT_8000_0008_EBX] = 4474 CPUID_8000_0008_EBX_WBNOINVD, 4475 .features[FEAT_7_0_EBX] = 4476 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4477 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 4478 CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 4479 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB | 4480 CPUID_7_0_EBX_SHA_NI, 4481 .features[FEAT_7_0_ECX] = 4482 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_GFNI | 4483 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4484 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT, 4485 .features[FEAT_7_0_EDX] = 4486 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 4487 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES | 4488 CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4489 .features[FEAT_ARCH_CAPABILITIES] = 4490 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 4491 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 4492 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_SBDR_SSDP_NO | 4493 MSR_ARCH_CAP_FBSDP_NO | MSR_ARCH_CAP_PSDP_NO | 4494 MSR_ARCH_CAP_PBRSB_NO, 4495 .features[FEAT_XSAVE] = 4496 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4497 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 4498 .features[FEAT_6_EAX] = 4499 CPUID_6_EAX_ARAT, 4500 .features[FEAT_7_1_EAX] = 4501 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_CMPCCXADD | 4502 CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_AVX_IFMA, 4503 .features[FEAT_7_1_EDX] = 4504 CPUID_7_1_EDX_AVX_VNNI_INT8 | CPUID_7_1_EDX_AVX_NE_CONVERT, 4505 .features[FEAT_7_2_EDX] = 4506 CPUID_7_2_EDX_MCDT_NO, 4507 .features[FEAT_VMX_BASIC] = 4508 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 4509 .features[FEAT_VMX_ENTRY_CTLS] = 4510 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 4511 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 4512 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 4513 .features[FEAT_VMX_EPT_VPID_CAPS] = 4514 MSR_VMX_EPT_EXECONLY | MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | 4515 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 4516 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 4517 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4518 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4519 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 4520 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4521 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 4522 .features[FEAT_VMX_EXIT_CTLS] = 4523 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4524 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4525 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 4526 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4527 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4528 .features[FEAT_VMX_MISC] = 4529 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 4530 MSR_VMX_MISC_VMWRITE_VMEXIT, 4531 .features[FEAT_VMX_PINBASED_CTLS] = 4532 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 4533 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 4534 VMX_PIN_BASED_POSTED_INTR, 4535 .features[FEAT_VMX_PROCBASED_CTLS] = 4536 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4537 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4538 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4539 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4540 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4541 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4542 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 4543 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 4544 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4545 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 4546 VMX_CPU_BASED_PAUSE_EXITING | 4547 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4548 .features[FEAT_VMX_SECONDARY_CTLS] = 4549 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4550 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 4551 VMX_SECONDARY_EXEC_RDTSCP | 4552 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4553 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 4554 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4555 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4556 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4557 VMX_SECONDARY_EXEC_RDRAND_EXITING | 4558 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4559 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4560 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 4561 VMX_SECONDARY_EXEC_XSAVES, 4562 .features[FEAT_VMX_VMFUNC] = 4563 MSR_VMX_VMFUNC_EPT_SWITCHING, 4564 .xlevel = 0x80000008, 4565 .model_id = "Intel Xeon Processor (SierraForest)", 4566 .versions = (X86CPUVersionDefinition[]) { 4567 { .version = 1 }, 4568 { 4569 .version = 2, 4570 .props = (PropValue[]) { 4571 { "ss", "on" }, 4572 { "tsc-adjust", "on" }, 4573 { "cldemote", "on" }, 4574 { "movdiri", "on" }, 4575 { "movdir64b", "on" }, 4576 { "gds-no", "on" }, 4577 { "rfds-no", "on" }, 4578 { "lam", "on" }, 4579 { "intel-psfd", "on"}, 4580 { "ipred-ctrl", "on"}, 4581 { "rrsba-ctrl", "on"}, 4582 { "bhi-ctrl", "on"}, 4583 { "stepping", "3" }, 4584 { /* end of list */ } 4585 } 4586 }, 4587 { /* end of list */ }, 4588 }, 4589 }, 4590 { 4591 .name = "ClearwaterForest", 4592 .level = 0x23, 4593 .xlevel = 0x80000008, 4594 .vendor = CPUID_VENDOR_INTEL, 4595 .family = 6, 4596 .model = 221, 4597 .stepping = 0, 4598 /* 4599 * please keep the ascending order so that we can have a clear view of 4600 * bit position of each feature. 4601 */ 4602 .features[FEAT_1_EDX] = 4603 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4604 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4605 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4606 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4607 CPUID_SSE | CPUID_SSE2 | CPUID_SS, 4608 .features[FEAT_1_ECX] = 4609 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 4610 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 4611 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4612 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 4613 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4614 .features[FEAT_8000_0001_EDX] = 4615 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4616 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4617 .features[FEAT_8000_0001_ECX] = 4618 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 4619 .features[FEAT_8000_0008_EBX] = 4620 CPUID_8000_0008_EBX_WBNOINVD, 4621 .features[FEAT_7_0_EBX] = 4622 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_TSC_ADJUST | 4623 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 4624 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 4625 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | 4626 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB | 4627 CPUID_7_0_EBX_SHA_NI, 4628 .features[FEAT_7_0_ECX] = 4629 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_GFNI | 4630 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4631 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT | 4632 CPUID_7_0_ECX_CLDEMOTE | CPUID_7_0_ECX_MOVDIRI | 4633 CPUID_7_0_ECX_MOVDIR64B, 4634 .features[FEAT_7_0_EDX] = 4635 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 4636 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES | 4637 CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4638 .features[FEAT_ARCH_CAPABILITIES] = 4639 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 4640 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 4641 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_SBDR_SSDP_NO | 4642 MSR_ARCH_CAP_FBSDP_NO | MSR_ARCH_CAP_PSDP_NO | 4643 MSR_ARCH_CAP_BHI_NO | MSR_ARCH_CAP_PBRSB_NO | 4644 MSR_ARCH_CAP_GDS_NO | MSR_ARCH_CAP_RFDS_NO, 4645 .features[FEAT_XSAVE] = 4646 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4647 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 4648 .features[FEAT_6_EAX] = 4649 CPUID_6_EAX_ARAT, 4650 .features[FEAT_7_1_EAX] = 4651 CPUID_7_1_EAX_SHA512 | CPUID_7_1_EAX_SM3 | CPUID_7_1_EAX_SM4 | 4652 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_CMPCCXADD | 4653 CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_AVX_IFMA | 4654 CPUID_7_1_EAX_LAM, 4655 .features[FEAT_7_1_EDX] = 4656 CPUID_7_1_EDX_AVX_VNNI_INT8 | CPUID_7_1_EDX_AVX_NE_CONVERT | 4657 CPUID_7_1_EDX_AVX_VNNI_INT16 | CPUID_7_1_EDX_PREFETCHITI, 4658 .features[FEAT_7_2_EDX] = 4659 CPUID_7_2_EDX_PSFD | CPUID_7_2_EDX_IPRED_CTRL | 4660 CPUID_7_2_EDX_RRSBA_CTRL | CPUID_7_2_EDX_DDPD_U | 4661 CPUID_7_2_EDX_BHI_CTRL | CPUID_7_2_EDX_MCDT_NO, 4662 .features[FEAT_VMX_BASIC] = 4663 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 4664 .features[FEAT_VMX_ENTRY_CTLS] = 4665 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 4666 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 4667 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 4668 .features[FEAT_VMX_EPT_VPID_CAPS] = 4669 MSR_VMX_EPT_EXECONLY | MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | 4670 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 4671 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 4672 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4673 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4674 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 4675 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4676 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 4677 .features[FEAT_VMX_EXIT_CTLS] = 4678 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4679 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4680 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 4681 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4682 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4683 .features[FEAT_VMX_MISC] = 4684 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 4685 MSR_VMX_MISC_VMWRITE_VMEXIT, 4686 .features[FEAT_VMX_PINBASED_CTLS] = 4687 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 4688 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 4689 VMX_PIN_BASED_POSTED_INTR, 4690 .features[FEAT_VMX_PROCBASED_CTLS] = 4691 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4692 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4693 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4694 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4695 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4696 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4697 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 4698 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 4699 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4700 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 4701 VMX_CPU_BASED_PAUSE_EXITING | 4702 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4703 .features[FEAT_VMX_SECONDARY_CTLS] = 4704 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4705 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 4706 VMX_SECONDARY_EXEC_RDTSCP | 4707 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4708 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 4709 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4710 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4711 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4712 VMX_SECONDARY_EXEC_RDRAND_EXITING | 4713 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4714 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4715 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 4716 VMX_SECONDARY_EXEC_XSAVES, 4717 .features[FEAT_VMX_VMFUNC] = 4718 MSR_VMX_VMFUNC_EPT_SWITCHING, 4719 .model_id = "Intel Xeon Processor (ClearwaterForest)", 4720 .versions = (X86CPUVersionDefinition[]) { 4721 { .version = 1 }, 4722 { /* end of list */ }, 4723 }, 4724 }, 4725 { 4726 .name = "Denverton", 4727 .level = 21, 4728 .vendor = CPUID_VENDOR_INTEL, 4729 .family = 6, 4730 .model = 95, 4731 .stepping = 1, 4732 .features[FEAT_1_EDX] = 4733 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4734 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4735 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4736 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4737 CPUID_SSE | CPUID_SSE2, 4738 .features[FEAT_1_ECX] = 4739 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR | 4740 CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_SSE41 | 4741 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4742 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | 4743 CPUID_EXT_AES | CPUID_EXT_XSAVE | CPUID_EXT_RDRAND, 4744 .features[FEAT_8000_0001_EDX] = 4745 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4746 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4747 .features[FEAT_8000_0001_ECX] = 4748 CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 4749 .features[FEAT_7_0_EBX] = 4750 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_ERMS | 4751 CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_SMAP | 4752 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_SHA_NI, 4753 .features[FEAT_7_0_EDX] = 4754 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES | 4755 CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4756 /* XSAVES is added in version 3 */ 4757 .features[FEAT_XSAVE] = 4758 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | CPUID_XSAVE_XGETBV1, 4759 .features[FEAT_6_EAX] = 4760 CPUID_6_EAX_ARAT, 4761 .features[FEAT_ARCH_CAPABILITIES] = 4762 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY, 4763 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 4764 MSR_VMX_BASIC_TRUE_CTLS, 4765 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 4766 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 4767 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 4768 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 4769 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 4770 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 4771 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4772 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4773 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4774 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 4775 .features[FEAT_VMX_EXIT_CTLS] = 4776 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4777 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4778 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 4779 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4780 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4781 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 4782 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 4783 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 4784 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 4785 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 4786 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4787 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4788 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4789 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4790 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4791 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 4792 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 4793 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 4794 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 4795 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4796 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4797 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4798 .features[FEAT_VMX_SECONDARY_CTLS] = 4799 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4800 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 4801 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 4802 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4803 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4804 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4805 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4806 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4807 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4808 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 4809 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 4810 .xlevel = 0x80000008, 4811 .model_id = "Intel Atom Processor (Denverton)", 4812 .versions = (X86CPUVersionDefinition[]) { 4813 { .version = 1 }, 4814 { 4815 .version = 2, 4816 .note = "no MPX, no MONITOR", 4817 .props = (PropValue[]) { 4818 { "monitor", "off" }, 4819 { "mpx", "off" }, 4820 { /* end of list */ }, 4821 }, 4822 }, 4823 { 4824 .version = 3, 4825 .note = "XSAVES, no MPX, no MONITOR", 4826 .props = (PropValue[]) { 4827 { "xsaves", "on" }, 4828 { "vmx-xsaves", "on" }, 4829 { /* end of list */ }, 4830 }, 4831 }, 4832 { /* end of list */ }, 4833 }, 4834 }, 4835 { 4836 .name = "Snowridge", 4837 .level = 27, 4838 .vendor = CPUID_VENDOR_INTEL, 4839 .family = 6, 4840 .model = 134, 4841 .stepping = 1, 4842 .features[FEAT_1_EDX] = 4843 /* missing: CPUID_PN CPUID_IA64 */ 4844 /* missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 4845 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | 4846 CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_MCE | 4847 CPUID_CX8 | CPUID_APIC | CPUID_SEP | 4848 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4849 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | 4850 CPUID_MMX | 4851 CPUID_FXSR | CPUID_SSE | CPUID_SSE2, 4852 .features[FEAT_1_ECX] = 4853 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR | 4854 CPUID_EXT_SSSE3 | 4855 CPUID_EXT_CX16 | 4856 CPUID_EXT_SSE41 | 4857 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4858 CPUID_EXT_POPCNT | 4859 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | CPUID_EXT_XSAVE | 4860 CPUID_EXT_RDRAND, 4861 .features[FEAT_8000_0001_EDX] = 4862 CPUID_EXT2_SYSCALL | 4863 CPUID_EXT2_NX | 4864 CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 4865 CPUID_EXT2_LM, 4866 .features[FEAT_8000_0001_ECX] = 4867 CPUID_EXT3_LAHF_LM | 4868 CPUID_EXT3_3DNOWPREFETCH, 4869 .features[FEAT_7_0_EBX] = 4870 CPUID_7_0_EBX_FSGSBASE | 4871 CPUID_7_0_EBX_SMEP | 4872 CPUID_7_0_EBX_ERMS | 4873 CPUID_7_0_EBX_MPX | /* missing bits 13, 15 */ 4874 CPUID_7_0_EBX_RDSEED | 4875 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 4876 CPUID_7_0_EBX_CLWB | 4877 CPUID_7_0_EBX_SHA_NI, 4878 .features[FEAT_7_0_ECX] = 4879 CPUID_7_0_ECX_UMIP | 4880 /* missing bit 5 */ 4881 CPUID_7_0_ECX_GFNI | 4882 CPUID_7_0_ECX_MOVDIRI | CPUID_7_0_ECX_CLDEMOTE | 4883 CPUID_7_0_ECX_MOVDIR64B, 4884 .features[FEAT_7_0_EDX] = 4885 CPUID_7_0_EDX_SPEC_CTRL | 4886 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD | 4887 CPUID_7_0_EDX_CORE_CAPABILITY, 4888 .features[FEAT_CORE_CAPABILITY] = 4889 MSR_CORE_CAP_SPLIT_LOCK_DETECT, 4890 /* XSAVES is added in version 3 */ 4891 .features[FEAT_XSAVE] = 4892 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4893 CPUID_XSAVE_XGETBV1, 4894 .features[FEAT_6_EAX] = 4895 CPUID_6_EAX_ARAT, 4896 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 4897 MSR_VMX_BASIC_TRUE_CTLS, 4898 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 4899 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 4900 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 4901 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 4902 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 4903 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 4904 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4905 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4906 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4907 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 4908 .features[FEAT_VMX_EXIT_CTLS] = 4909 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4910 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4911 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 4912 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4913 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4914 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 4915 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 4916 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 4917 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 4918 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 4919 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4920 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4921 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4922 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4923 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4924 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 4925 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 4926 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 4927 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 4928 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4929 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4930 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4931 .features[FEAT_VMX_SECONDARY_CTLS] = 4932 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4933 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 4934 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 4935 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4936 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4937 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4938 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4939 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4940 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4941 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 4942 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 4943 .xlevel = 0x80000008, 4944 .model_id = "Intel Atom Processor (SnowRidge)", 4945 .versions = (X86CPUVersionDefinition[]) { 4946 { .version = 1 }, 4947 { 4948 .version = 2, 4949 .props = (PropValue[]) { 4950 { "mpx", "off" }, 4951 { "model-id", "Intel Atom Processor (Snowridge, no MPX)" }, 4952 { /* end of list */ }, 4953 }, 4954 }, 4955 { 4956 .version = 3, 4957 .note = "XSAVES, no MPX", 4958 .props = (PropValue[]) { 4959 { "xsaves", "on" }, 4960 { "vmx-xsaves", "on" }, 4961 { /* end of list */ }, 4962 }, 4963 }, 4964 { 4965 .version = 4, 4966 .note = "no split lock detect, no core-capability", 4967 .props = (PropValue[]) { 4968 { "split-lock-detect", "off" }, 4969 { "core-capability", "off" }, 4970 { /* end of list */ }, 4971 }, 4972 }, 4973 { /* end of list */ }, 4974 }, 4975 }, 4976 { 4977 .name = "KnightsMill", 4978 .level = 0xd, 4979 .vendor = CPUID_VENDOR_INTEL, 4980 .family = 6, 4981 .model = 133, 4982 .stepping = 0, 4983 .features[FEAT_1_EDX] = 4984 CPUID_VME | CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | 4985 CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | 4986 CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | 4987 CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | 4988 CPUID_PSE | CPUID_DE | CPUID_FP87, 4989 .features[FEAT_1_ECX] = 4990 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 4991 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 4992 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 4993 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 4994 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 4995 CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4996 .features[FEAT_8000_0001_EDX] = 4997 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 4998 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 4999 .features[FEAT_8000_0001_ECX] = 5000 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 5001 .features[FEAT_7_0_EBX] = 5002 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5003 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 5004 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_AVX512F | 5005 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_AVX512PF | 5006 CPUID_7_0_EBX_AVX512ER, 5007 .features[FEAT_7_0_ECX] = 5008 CPUID_7_0_ECX_AVX512_VPOPCNTDQ, 5009 .features[FEAT_7_0_EDX] = 5010 CPUID_7_0_EDX_AVX512_4VNNIW | CPUID_7_0_EDX_AVX512_4FMAPS, 5011 .features[FEAT_XSAVE] = 5012 CPUID_XSAVE_XSAVEOPT, 5013 .features[FEAT_6_EAX] = 5014 CPUID_6_EAX_ARAT, 5015 .xlevel = 0x80000008, 5016 .model_id = "Intel Xeon Phi Processor (Knights Mill)", 5017 }, 5018 { 5019 .name = "Opteron_G1", 5020 .level = 5, 5021 .vendor = CPUID_VENDOR_AMD, 5022 .family = 15, 5023 .model = 6, 5024 .stepping = 1, 5025 .features[FEAT_1_EDX] = 5026 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 5027 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 5028 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 5029 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 5030 CPUID_DE | CPUID_FP87, 5031 .features[FEAT_1_ECX] = 5032 CPUID_EXT_SSE3, 5033 .features[FEAT_8000_0001_EDX] = 5034 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 5035 .xlevel = 0x80000008, 5036 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)", 5037 }, 5038 { 5039 .name = "Opteron_G2", 5040 .level = 5, 5041 .vendor = CPUID_VENDOR_AMD, 5042 .family = 15, 5043 .model = 6, 5044 .stepping = 1, 5045 .features[FEAT_1_EDX] = 5046 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 5047 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 5048 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 5049 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 5050 CPUID_DE | CPUID_FP87, 5051 .features[FEAT_1_ECX] = 5052 CPUID_EXT_CX16 | CPUID_EXT_SSE3, 5053 .features[FEAT_8000_0001_EDX] = 5054 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 5055 .features[FEAT_8000_0001_ECX] = 5056 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, 5057 .xlevel = 0x80000008, 5058 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)", 5059 }, 5060 { 5061 .name = "Opteron_G3", 5062 .level = 5, 5063 .vendor = CPUID_VENDOR_AMD, 5064 .family = 16, 5065 .model = 2, 5066 .stepping = 3, 5067 .features[FEAT_1_EDX] = 5068 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 5069 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 5070 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 5071 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 5072 CPUID_DE | CPUID_FP87, 5073 .features[FEAT_1_ECX] = 5074 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR | 5075 CPUID_EXT_SSE3, 5076 .features[FEAT_8000_0001_EDX] = 5077 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL | 5078 CPUID_EXT2_RDTSCP, 5079 .features[FEAT_8000_0001_ECX] = 5080 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | 5081 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, 5082 .xlevel = 0x80000008, 5083 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)", 5084 }, 5085 { 5086 .name = "Opteron_G4", 5087 .level = 0xd, 5088 .vendor = CPUID_VENDOR_AMD, 5089 .family = 21, 5090 .model = 1, 5091 .stepping = 2, 5092 .features[FEAT_1_EDX] = 5093 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 5094 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 5095 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 5096 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 5097 CPUID_DE | CPUID_FP87, 5098 .features[FEAT_1_ECX] = 5099 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 5100 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5101 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 5102 CPUID_EXT_SSE3, 5103 .features[FEAT_8000_0001_EDX] = 5104 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX | 5105 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP, 5106 .features[FEAT_8000_0001_ECX] = 5107 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP | 5108 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | 5109 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | 5110 CPUID_EXT3_LAHF_LM, 5111 .features[FEAT_SVM] = 5112 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 5113 /* no xsaveopt! */ 5114 .xlevel = 0x8000001A, 5115 .model_id = "AMD Opteron 62xx class CPU", 5116 }, 5117 { 5118 .name = "Opteron_G5", 5119 .level = 0xd, 5120 .vendor = CPUID_VENDOR_AMD, 5121 .family = 21, 5122 .model = 2, 5123 .stepping = 0, 5124 .features[FEAT_1_EDX] = 5125 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 5126 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 5127 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 5128 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 5129 CPUID_DE | CPUID_FP87, 5130 .features[FEAT_1_ECX] = 5131 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE | 5132 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | 5133 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA | 5134 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 5135 .features[FEAT_8000_0001_EDX] = 5136 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX | 5137 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP, 5138 .features[FEAT_8000_0001_ECX] = 5139 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP | 5140 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | 5141 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | 5142 CPUID_EXT3_LAHF_LM, 5143 .features[FEAT_SVM] = 5144 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 5145 /* no xsaveopt! */ 5146 .xlevel = 0x8000001A, 5147 .model_id = "AMD Opteron 63xx class CPU", 5148 }, 5149 { 5150 .name = "EPYC", 5151 .level = 0xd, 5152 .vendor = CPUID_VENDOR_AMD, 5153 .family = 23, 5154 .model = 1, 5155 .stepping = 2, 5156 .features[FEAT_1_EDX] = 5157 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 5158 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 5159 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 5160 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 5161 CPUID_VME | CPUID_FP87, 5162 .features[FEAT_1_ECX] = 5163 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5164 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 5165 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5166 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 5167 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 5168 .features[FEAT_8000_0001_EDX] = 5169 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5170 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5171 CPUID_EXT2_SYSCALL, 5172 .features[FEAT_8000_0001_ECX] = 5173 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5174 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5175 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5176 CPUID_EXT3_TOPOEXT, 5177 .features[FEAT_7_0_EBX] = 5178 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5179 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 5180 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 5181 CPUID_7_0_EBX_SHA_NI, 5182 .features[FEAT_XSAVE] = 5183 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5184 CPUID_XSAVE_XGETBV1, 5185 .features[FEAT_6_EAX] = 5186 CPUID_6_EAX_ARAT, 5187 .features[FEAT_SVM] = 5188 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 5189 .xlevel = 0x8000001E, 5190 .model_id = "AMD EPYC Processor", 5191 .cache_info = &epyc_cache_info, 5192 .versions = (X86CPUVersionDefinition[]) { 5193 { .version = 1 }, 5194 { 5195 .version = 2, 5196 .alias = "EPYC-IBPB", 5197 .props = (PropValue[]) { 5198 { "ibpb", "on" }, 5199 { "model-id", 5200 "AMD EPYC Processor (with IBPB)" }, 5201 { /* end of list */ } 5202 } 5203 }, 5204 { 5205 .version = 3, 5206 .props = (PropValue[]) { 5207 { "ibpb", "on" }, 5208 { "perfctr-core", "on" }, 5209 { "clzero", "on" }, 5210 { "xsaveerptr", "on" }, 5211 { "xsaves", "on" }, 5212 { "model-id", 5213 "AMD EPYC Processor" }, 5214 { /* end of list */ } 5215 } 5216 }, 5217 { 5218 .version = 4, 5219 .props = (PropValue[]) { 5220 { "model-id", 5221 "AMD EPYC-v4 Processor" }, 5222 { /* end of list */ } 5223 }, 5224 .cache_info = &epyc_v4_cache_info 5225 }, 5226 { /* end of list */ } 5227 } 5228 }, 5229 { 5230 .name = "Dhyana", 5231 .level = 0xd, 5232 .vendor = CPUID_VENDOR_HYGON, 5233 .family = 24, 5234 .model = 0, 5235 .stepping = 1, 5236 .features[FEAT_1_EDX] = 5237 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 5238 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 5239 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 5240 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 5241 CPUID_VME | CPUID_FP87, 5242 .features[FEAT_1_ECX] = 5243 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5244 CPUID_EXT_XSAVE | CPUID_EXT_POPCNT | 5245 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5246 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 5247 CPUID_EXT_MONITOR | CPUID_EXT_SSE3, 5248 .features[FEAT_8000_0001_EDX] = 5249 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5250 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5251 CPUID_EXT2_SYSCALL, 5252 .features[FEAT_8000_0001_ECX] = 5253 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5254 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5255 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5256 CPUID_EXT3_TOPOEXT, 5257 .features[FEAT_8000_0008_EBX] = 5258 CPUID_8000_0008_EBX_IBPB, 5259 .features[FEAT_7_0_EBX] = 5260 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5261 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 5262 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT, 5263 /* XSAVES is added in version 2 */ 5264 .features[FEAT_XSAVE] = 5265 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5266 CPUID_XSAVE_XGETBV1, 5267 .features[FEAT_6_EAX] = 5268 CPUID_6_EAX_ARAT, 5269 .features[FEAT_SVM] = 5270 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 5271 .xlevel = 0x8000001E, 5272 .model_id = "Hygon Dhyana Processor", 5273 .cache_info = &epyc_cache_info, 5274 .versions = (X86CPUVersionDefinition[]) { 5275 { .version = 1 }, 5276 { .version = 2, 5277 .note = "XSAVES", 5278 .props = (PropValue[]) { 5279 { "xsaves", "on" }, 5280 { /* end of list */ } 5281 }, 5282 }, 5283 { /* end of list */ } 5284 } 5285 }, 5286 { 5287 .name = "EPYC-Rome", 5288 .level = 0xd, 5289 .vendor = CPUID_VENDOR_AMD, 5290 .family = 23, 5291 .model = 49, 5292 .stepping = 0, 5293 .features[FEAT_1_EDX] = 5294 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 5295 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 5296 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 5297 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 5298 CPUID_VME | CPUID_FP87, 5299 .features[FEAT_1_ECX] = 5300 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5301 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 5302 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5303 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 5304 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 5305 .features[FEAT_8000_0001_EDX] = 5306 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5307 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5308 CPUID_EXT2_SYSCALL, 5309 .features[FEAT_8000_0001_ECX] = 5310 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5311 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5312 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5313 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 5314 .features[FEAT_8000_0008_EBX] = 5315 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 5316 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 5317 CPUID_8000_0008_EBX_STIBP, 5318 .features[FEAT_7_0_EBX] = 5319 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5320 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 5321 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 5322 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB, 5323 .features[FEAT_7_0_ECX] = 5324 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID, 5325 .features[FEAT_XSAVE] = 5326 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5327 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 5328 .features[FEAT_6_EAX] = 5329 CPUID_6_EAX_ARAT, 5330 .features[FEAT_SVM] = 5331 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 5332 .xlevel = 0x8000001E, 5333 .model_id = "AMD EPYC-Rome Processor", 5334 .cache_info = &epyc_rome_cache_info, 5335 .versions = (X86CPUVersionDefinition[]) { 5336 { .version = 1 }, 5337 { 5338 .version = 2, 5339 .props = (PropValue[]) { 5340 { "ibrs", "on" }, 5341 { "amd-ssbd", "on" }, 5342 { /* end of list */ } 5343 } 5344 }, 5345 { 5346 .version = 3, 5347 .props = (PropValue[]) { 5348 { "model-id", 5349 "AMD EPYC-Rome-v3 Processor" }, 5350 { /* end of list */ } 5351 }, 5352 .cache_info = &epyc_rome_v3_cache_info 5353 }, 5354 { 5355 .version = 4, 5356 .props = (PropValue[]) { 5357 /* Erratum 1386 */ 5358 { "model-id", 5359 "AMD EPYC-Rome-v4 Processor (no XSAVES)" }, 5360 { "xsaves", "off" }, 5361 { /* end of list */ } 5362 }, 5363 }, 5364 { /* end of list */ } 5365 } 5366 }, 5367 { 5368 .name = "EPYC-Milan", 5369 .level = 0xd, 5370 .vendor = CPUID_VENDOR_AMD, 5371 .family = 25, 5372 .model = 1, 5373 .stepping = 1, 5374 .features[FEAT_1_EDX] = 5375 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 5376 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 5377 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 5378 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 5379 CPUID_VME | CPUID_FP87, 5380 .features[FEAT_1_ECX] = 5381 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5382 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 5383 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5384 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 5385 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 5386 CPUID_EXT_PCID, 5387 .features[FEAT_8000_0001_EDX] = 5388 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5389 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5390 CPUID_EXT2_SYSCALL, 5391 .features[FEAT_8000_0001_ECX] = 5392 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5393 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5394 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5395 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 5396 .features[FEAT_8000_0008_EBX] = 5397 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 5398 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 5399 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | 5400 CPUID_8000_0008_EBX_AMD_SSBD, 5401 .features[FEAT_7_0_EBX] = 5402 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5403 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 5404 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 5405 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_ERMS | 5406 CPUID_7_0_EBX_INVPCID, 5407 .features[FEAT_7_0_ECX] = 5408 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_PKU, 5409 .features[FEAT_7_0_EDX] = 5410 CPUID_7_0_EDX_FSRM, 5411 .features[FEAT_XSAVE] = 5412 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5413 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 5414 .features[FEAT_6_EAX] = 5415 CPUID_6_EAX_ARAT, 5416 .features[FEAT_SVM] = 5417 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE | CPUID_SVM_SVME_ADDR_CHK, 5418 .xlevel = 0x8000001E, 5419 .model_id = "AMD EPYC-Milan Processor", 5420 .cache_info = &epyc_milan_cache_info, 5421 .versions = (X86CPUVersionDefinition[]) { 5422 { .version = 1 }, 5423 { 5424 .version = 2, 5425 .props = (PropValue[]) { 5426 { "model-id", 5427 "AMD EPYC-Milan-v2 Processor" }, 5428 { "vaes", "on" }, 5429 { "vpclmulqdq", "on" }, 5430 { "stibp-always-on", "on" }, 5431 { "amd-psfd", "on" }, 5432 { "no-nested-data-bp", "on" }, 5433 { "lfence-always-serializing", "on" }, 5434 { "null-sel-clr-base", "on" }, 5435 { /* end of list */ } 5436 }, 5437 .cache_info = &epyc_milan_v2_cache_info 5438 }, 5439 { /* end of list */ } 5440 } 5441 }, 5442 { 5443 .name = "EPYC-Genoa", 5444 .level = 0xd, 5445 .vendor = CPUID_VENDOR_AMD, 5446 .family = 25, 5447 .model = 17, 5448 .stepping = 0, 5449 .features[FEAT_1_EDX] = 5450 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 5451 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 5452 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 5453 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 5454 CPUID_VME | CPUID_FP87, 5455 .features[FEAT_1_ECX] = 5456 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5457 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 5458 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5459 CPUID_EXT_PCID | CPUID_EXT_CX16 | CPUID_EXT_FMA | 5460 CPUID_EXT_SSSE3 | CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | 5461 CPUID_EXT_SSE3, 5462 .features[FEAT_8000_0001_EDX] = 5463 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5464 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5465 CPUID_EXT2_SYSCALL, 5466 .features[FEAT_8000_0001_ECX] = 5467 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5468 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5469 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5470 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 5471 .features[FEAT_8000_0008_EBX] = 5472 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 5473 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 5474 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | 5475 CPUID_8000_0008_EBX_STIBP_ALWAYS_ON | 5476 CPUID_8000_0008_EBX_AMD_SSBD | CPUID_8000_0008_EBX_AMD_PSFD, 5477 .features[FEAT_8000_0021_EAX] = 5478 CPUID_8000_0021_EAX_NO_NESTED_DATA_BP | 5479 CPUID_8000_0021_EAX_LFENCE_ALWAYS_SERIALIZING | 5480 CPUID_8000_0021_EAX_NULL_SEL_CLR_BASE | 5481 CPUID_8000_0021_EAX_AUTO_IBRS, 5482 .features[FEAT_7_0_EBX] = 5483 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5484 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 5485 CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_AVX512F | 5486 CPUID_7_0_EBX_AVX512DQ | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 5487 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_AVX512IFMA | 5488 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB | 5489 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | 5490 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, 5491 .features[FEAT_7_0_ECX] = 5492 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 5493 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 5494 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 5495 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 5496 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | 5497 CPUID_7_0_ECX_RDPID, 5498 .features[FEAT_7_0_EDX] = 5499 CPUID_7_0_EDX_FSRM, 5500 .features[FEAT_7_1_EAX] = 5501 CPUID_7_1_EAX_AVX512_BF16, 5502 .features[FEAT_XSAVE] = 5503 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5504 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 5505 .features[FEAT_6_EAX] = 5506 CPUID_6_EAX_ARAT, 5507 .features[FEAT_SVM] = 5508 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE | CPUID_SVM_VNMI | 5509 CPUID_SVM_SVME_ADDR_CHK, 5510 .xlevel = 0x80000022, 5511 .model_id = "AMD EPYC-Genoa Processor", 5512 .cache_info = &epyc_genoa_cache_info, 5513 }, 5514 { 5515 .name = "YongFeng", 5516 .level = 0x1F, 5517 .vendor = CPUID_VENDOR_ZHAOXIN1, 5518 .family = 7, 5519 .model = 11, 5520 .stepping = 3, 5521 /* missing: CPUID_HT, CPUID_TM, CPUID_PBE */ 5522 .features[FEAT_1_EDX] = 5523 CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 5524 CPUID_ACPI | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | 5525 CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | 5526 CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | 5527 CPUID_PSE | CPUID_DE | CPUID_VME | CPUID_FP87, 5528 /* 5529 * missing: CPUID_EXT_OSXSAVE, CPUID_EXT_XTPR, CPUID_EXT_TM2, 5530 * CPUID_EXT_EST, CPUID_EXT_SMX, CPUID_EXT_VMX 5531 */ 5532 .features[FEAT_1_ECX] = 5533 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5534 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_TSC_DEADLINE_TIMER | 5535 CPUID_EXT_POPCNT | CPUID_EXT_MOVBE | CPUID_EXT_X2APIC | 5536 CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | CPUID_EXT_PCID | 5537 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 5538 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 5539 .features[FEAT_7_0_EBX] = 5540 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_ADX | 5541 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_BMI2 | 5542 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_BMI1 | 5543 CPUID_7_0_EBX_FSGSBASE, 5544 /* missing: CPUID_7_0_ECX_OSPKE */ 5545 .features[FEAT_7_0_ECX] = 5546 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_UMIP, 5547 .features[FEAT_7_0_EDX] = 5548 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL, 5549 .features[FEAT_8000_0001_EDX] = 5550 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5551 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 5552 .features[FEAT_8000_0001_ECX] = 5553 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM, 5554 .features[FEAT_8000_0007_EDX] = CPUID_APM_INVTSC, 5555 /* 5556 * TODO: When the Linux kernel introduces other existing definitions 5557 * for this leaf, remember to update the definitions here. 5558 */ 5559 .features[FEAT_C000_0001_EDX] = 5560 CPUID_C000_0001_EDX_PMM_EN | CPUID_C000_0001_EDX_PMM | 5561 CPUID_C000_0001_EDX_PHE_EN | CPUID_C000_0001_EDX_PHE | 5562 CPUID_C000_0001_EDX_ACE2 | 5563 CPUID_C000_0001_EDX_XCRYPT_EN | CPUID_C000_0001_EDX_XCRYPT | 5564 CPUID_C000_0001_EDX_XSTORE_EN | CPUID_C000_0001_EDX_XSTORE, 5565 .features[FEAT_XSAVE] = 5566 CPUID_XSAVE_XSAVEOPT, 5567 .features[FEAT_ARCH_CAPABILITIES] = 5568 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | 5569 MSR_ARCH_CAP_MDS_NO | MSR_ARCH_CAP_PSCHANGE_MC_NO | 5570 MSR_ARCH_CAP_SSB_NO, 5571 .features[FEAT_VMX_PROCBASED_CTLS] = 5572 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | VMX_CPU_BASED_HLT_EXITING | 5573 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_INVLPG_EXITING | 5574 VMX_CPU_BASED_MWAIT_EXITING | VMX_CPU_BASED_RDPMC_EXITING | 5575 VMX_CPU_BASED_RDTSC_EXITING | VMX_CPU_BASED_CR3_LOAD_EXITING | 5576 VMX_CPU_BASED_CR3_STORE_EXITING | VMX_CPU_BASED_CR8_LOAD_EXITING | 5577 VMX_CPU_BASED_CR8_STORE_EXITING | VMX_CPU_BASED_TPR_SHADOW | 5578 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_MOV_DR_EXITING | 5579 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 5580 VMX_CPU_BASED_MONITOR_TRAP_FLAG | VMX_CPU_BASED_USE_MSR_BITMAPS | 5581 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 5582 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 5583 /* 5584 * missing: VMX_SECONDARY_EXEC_PAUSE_LOOP_EXITING, 5585 * VMX_SECONDARY_EXEC_TSC_SCALING 5586 */ 5587 .features[FEAT_VMX_SECONDARY_CTLS] = 5588 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 5589 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 5590 VMX_SECONDARY_EXEC_RDTSCP | VMX_SECONDARY_EXEC_ENABLE_VPID | 5591 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 5592 VMX_SECONDARY_EXEC_WBINVD_EXITING | 5593 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 5594 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 5595 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 5596 VMX_SECONDARY_EXEC_RDRAND_EXITING | 5597 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 5598 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | 5599 VMX_SECONDARY_EXEC_SHADOW_VMCS | 5600 VMX_SECONDARY_EXEC_ENABLE_PML, 5601 .features[FEAT_VMX_PINBASED_CTLS] = 5602 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 5603 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 5604 VMX_PIN_BASED_POSTED_INTR, 5605 .features[FEAT_VMX_EXIT_CTLS] = 5606 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE | 5607 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 5608 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 5609 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 5610 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 5611 /* missing: VMX_VM_ENTRY_SMM, VMX_VM_ENTRY_DEACT_DUAL_MONITOR */ 5612 .features[FEAT_VMX_ENTRY_CTLS] = 5613 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 5614 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 5615 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 5616 /* 5617 * missing: MSR_VMX_MISC_ACTIVITY_SHUTDOWN, 5618 * MSR_VMX_MISC_ACTIVITY_WAIT_SIPI 5619 */ 5620 .features[FEAT_VMX_MISC] = 5621 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 5622 MSR_VMX_MISC_VMWRITE_VMEXIT, 5623 /* missing: MSR_VMX_EPT_UC */ 5624 .features[FEAT_VMX_EPT_VPID_CAPS] = 5625 MSR_VMX_EPT_EXECONLY | MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | 5626 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 5627 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 5628 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 5629 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID | 5630 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 5631 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 5632 .features[FEAT_VMX_BASIC] = 5633 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 5634 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 5635 .xlevel = 0x80000008, 5636 .model_id = "Zhaoxin YongFeng Processor", 5637 .versions = (X86CPUVersionDefinition[]) { 5638 { .version = 1 }, 5639 { 5640 .version = 2, 5641 .note = "with the correct model number", 5642 .props = (PropValue[]) { 5643 { "model", "0x5b" }, 5644 { /* end of list */ } 5645 } 5646 }, 5647 { /* end of list */ } 5648 } 5649 }, 5650 }; 5651 5652 /* 5653 * We resolve CPU model aliases using -v1 when using "-machine 5654 * none", but this is just for compatibility while libvirt isn't 5655 * adapted to resolve CPU model versions before creating VMs. 5656 * See "Runnability guarantee of CPU models" at 5657 * docs/about/deprecated.rst. 5658 */ 5659 X86CPUVersion default_cpu_version = 1; 5660 5661 void x86_cpu_set_default_version(X86CPUVersion version) 5662 { 5663 /* Translating CPU_VERSION_AUTO to CPU_VERSION_AUTO doesn't make sense */ 5664 assert(version != CPU_VERSION_AUTO); 5665 default_cpu_version = version; 5666 } 5667 5668 static X86CPUVersion x86_cpu_model_last_version(const X86CPUModel *model) 5669 { 5670 int v = 0; 5671 const X86CPUVersionDefinition *vdef = 5672 x86_cpu_def_get_versions(model->cpudef); 5673 while (vdef->version) { 5674 v = vdef->version; 5675 vdef++; 5676 } 5677 return v; 5678 } 5679 5680 /* Return the actual version being used for a specific CPU model */ 5681 static X86CPUVersion x86_cpu_model_resolve_version(const X86CPUModel *model) 5682 { 5683 X86CPUVersion v = model->version; 5684 if (v == CPU_VERSION_AUTO) { 5685 v = default_cpu_version; 5686 } 5687 if (v == CPU_VERSION_LATEST) { 5688 return x86_cpu_model_last_version(model); 5689 } 5690 return v; 5691 } 5692 5693 static const Property max_x86_cpu_properties[] = { 5694 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true), 5695 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false), 5696 }; 5697 5698 static void max_x86_cpu_realize(DeviceState *dev, Error **errp) 5699 { 5700 Object *obj = OBJECT(dev); 5701 5702 if (!object_property_get_int(obj, "family", &error_abort)) { 5703 if (X86_CPU(obj)->env.features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 5704 object_property_set_int(obj, "family", 15, &error_abort); 5705 object_property_set_int(obj, "model", 107, &error_abort); 5706 object_property_set_int(obj, "stepping", 1, &error_abort); 5707 } else { 5708 object_property_set_int(obj, "family", 6, &error_abort); 5709 object_property_set_int(obj, "model", 6, &error_abort); 5710 object_property_set_int(obj, "stepping", 3, &error_abort); 5711 } 5712 } 5713 5714 x86_cpu_realizefn(dev, errp); 5715 } 5716 5717 static void max_x86_cpu_class_init(ObjectClass *oc, const void *data) 5718 { 5719 DeviceClass *dc = DEVICE_CLASS(oc); 5720 X86CPUClass *xcc = X86_CPU_CLASS(oc); 5721 5722 xcc->ordering = 9; 5723 5724 xcc->model_description = 5725 "Enables all features supported by the accelerator in the current host"; 5726 5727 device_class_set_props(dc, max_x86_cpu_properties); 5728 dc->realize = max_x86_cpu_realize; 5729 } 5730 5731 static void max_x86_cpu_initfn(Object *obj) 5732 { 5733 X86CPU *cpu = X86_CPU(obj); 5734 5735 /* We can't fill the features array here because we don't know yet if 5736 * "migratable" is true or false. 5737 */ 5738 cpu->max_features = true; 5739 object_property_set_bool(OBJECT(cpu), "pmu", true, &error_abort); 5740 5741 /* 5742 * these defaults are used for TCG and all other accelerators 5743 * besides KVM and HVF, which overwrite these values 5744 */ 5745 object_property_set_str(OBJECT(cpu), "vendor", CPUID_VENDOR_AMD, 5746 &error_abort); 5747 object_property_set_str(OBJECT(cpu), "model-id", 5748 "QEMU TCG CPU version " QEMU_HW_VERSION, 5749 &error_abort); 5750 } 5751 5752 static const TypeInfo max_x86_cpu_type_info = { 5753 .name = X86_CPU_TYPE_NAME("max"), 5754 .parent = TYPE_X86_CPU, 5755 .instance_init = max_x86_cpu_initfn, 5756 .class_init = max_x86_cpu_class_init, 5757 }; 5758 5759 static char *feature_word_description(FeatureWordInfo *f, uint32_t bit) 5760 { 5761 assert(f->type == CPUID_FEATURE_WORD || f->type == MSR_FEATURE_WORD); 5762 5763 switch (f->type) { 5764 case CPUID_FEATURE_WORD: 5765 { 5766 const char *reg = get_register_name_32(f->cpuid.reg); 5767 assert(reg); 5768 return g_strdup_printf("CPUID.%02XH:%s", 5769 f->cpuid.eax, reg); 5770 } 5771 case MSR_FEATURE_WORD: 5772 return g_strdup_printf("MSR(%02XH)", 5773 f->msr.index); 5774 } 5775 5776 return NULL; 5777 } 5778 5779 static bool x86_cpu_have_filtered_features(X86CPU *cpu) 5780 { 5781 FeatureWord w; 5782 5783 for (w = 0; w < FEATURE_WORDS; w++) { 5784 if (cpu->filtered_features[w]) { 5785 return true; 5786 } 5787 } 5788 5789 return false; 5790 } 5791 5792 static void mark_unavailable_features(X86CPU *cpu, FeatureWord w, uint64_t mask, 5793 const char *verbose_prefix) 5794 { 5795 CPUX86State *env = &cpu->env; 5796 FeatureWordInfo *f = &feature_word_info[w]; 5797 int i; 5798 5799 if (!cpu->force_features) { 5800 env->features[w] &= ~mask; 5801 } 5802 cpu->filtered_features[w] |= mask; 5803 5804 if (!verbose_prefix) { 5805 return; 5806 } 5807 5808 for (i = 0; i < 64; ++i) { 5809 if ((1ULL << i) & mask) { 5810 g_autofree char *feat_word_str = feature_word_description(f, i); 5811 warn_report("%s: %s%s%s [bit %d]", 5812 verbose_prefix, 5813 feat_word_str, 5814 f->feat_names[i] ? "." : "", 5815 f->feat_names[i] ? f->feat_names[i] : "", i); 5816 } 5817 } 5818 } 5819 5820 static void x86_cpuid_version_get_family(Object *obj, Visitor *v, 5821 const char *name, void *opaque, 5822 Error **errp) 5823 { 5824 X86CPU *cpu = X86_CPU(obj); 5825 CPUX86State *env = &cpu->env; 5826 uint64_t value; 5827 5828 value = (env->cpuid_version >> 8) & 0xf; 5829 if (value == 0xf) { 5830 value += (env->cpuid_version >> 20) & 0xff; 5831 } 5832 visit_type_uint64(v, name, &value, errp); 5833 } 5834 5835 static void x86_cpuid_version_set_family(Object *obj, Visitor *v, 5836 const char *name, void *opaque, 5837 Error **errp) 5838 { 5839 X86CPU *cpu = X86_CPU(obj); 5840 CPUX86State *env = &cpu->env; 5841 const uint64_t max = 0xff + 0xf; 5842 uint64_t value; 5843 5844 if (!visit_type_uint64(v, name, &value, errp)) { 5845 return; 5846 } 5847 if (value > max) { 5848 error_setg(errp, "parameter '%s' can be at most %" PRIu64, 5849 name ? name : "null", max); 5850 return; 5851 } 5852 5853 env->cpuid_version &= ~0xff00f00; 5854 if (value > 0x0f) { 5855 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20); 5856 } else { 5857 env->cpuid_version |= value << 8; 5858 } 5859 } 5860 5861 static void x86_cpuid_version_get_model(Object *obj, Visitor *v, 5862 const char *name, void *opaque, 5863 Error **errp) 5864 { 5865 X86CPU *cpu = X86_CPU(obj); 5866 CPUX86State *env = &cpu->env; 5867 uint64_t value; 5868 5869 value = (env->cpuid_version >> 4) & 0xf; 5870 value |= ((env->cpuid_version >> 16) & 0xf) << 4; 5871 visit_type_uint64(v, name, &value, errp); 5872 } 5873 5874 static void x86_cpuid_version_set_model(Object *obj, Visitor *v, 5875 const char *name, void *opaque, 5876 Error **errp) 5877 { 5878 X86CPU *cpu = X86_CPU(obj); 5879 CPUX86State *env = &cpu->env; 5880 const uint64_t max = 0xff; 5881 uint64_t value; 5882 5883 if (!visit_type_uint64(v, name, &value, errp)) { 5884 return; 5885 } 5886 if (value > max) { 5887 error_setg(errp, "parameter '%s' can be at most %" PRIu64, 5888 name ? name : "null", max); 5889 return; 5890 } 5891 5892 env->cpuid_version &= ~0xf00f0; 5893 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16); 5894 } 5895 5896 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v, 5897 const char *name, void *opaque, 5898 Error **errp) 5899 { 5900 X86CPU *cpu = X86_CPU(obj); 5901 CPUX86State *env = &cpu->env; 5902 uint64_t value; 5903 5904 value = env->cpuid_version & 0xf; 5905 visit_type_uint64(v, name, &value, errp); 5906 } 5907 5908 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v, 5909 const char *name, void *opaque, 5910 Error **errp) 5911 { 5912 X86CPU *cpu = X86_CPU(obj); 5913 CPUX86State *env = &cpu->env; 5914 const uint64_t max = 0xf; 5915 uint64_t value; 5916 5917 if (!visit_type_uint64(v, name, &value, errp)) { 5918 return; 5919 } 5920 if (value > max) { 5921 error_setg(errp, "parameter '%s' can be at most %" PRIu64, 5922 name ? name : "null", max); 5923 return; 5924 } 5925 5926 env->cpuid_version &= ~0xf; 5927 env->cpuid_version |= value & 0xf; 5928 } 5929 5930 static char *x86_cpuid_get_vendor(Object *obj, Error **errp) 5931 { 5932 X86CPU *cpu = X86_CPU(obj); 5933 CPUX86State *env = &cpu->env; 5934 char *value; 5935 5936 value = g_malloc(CPUID_VENDOR_SZ + 1); 5937 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2, 5938 env->cpuid_vendor3); 5939 return value; 5940 } 5941 5942 static void x86_cpuid_set_vendor(Object *obj, const char *value, 5943 Error **errp) 5944 { 5945 X86CPU *cpu = X86_CPU(obj); 5946 CPUX86State *env = &cpu->env; 5947 int i; 5948 5949 if (strlen(value) != CPUID_VENDOR_SZ) { 5950 error_setg(errp, "value of property 'vendor' must consist of" 5951 " exactly " stringify(CPUID_VENDOR_SZ) " characters"); 5952 return; 5953 } 5954 5955 env->cpuid_vendor1 = 0; 5956 env->cpuid_vendor2 = 0; 5957 env->cpuid_vendor3 = 0; 5958 for (i = 0; i < 4; i++) { 5959 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i); 5960 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i); 5961 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i); 5962 } 5963 } 5964 5965 static char *x86_cpuid_get_model_id(Object *obj, Error **errp) 5966 { 5967 X86CPU *cpu = X86_CPU(obj); 5968 CPUX86State *env = &cpu->env; 5969 char *value; 5970 int i; 5971 5972 value = g_malloc(48 + 1); 5973 for (i = 0; i < 48; i++) { 5974 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3)); 5975 } 5976 value[48] = '\0'; 5977 return value; 5978 } 5979 5980 static void x86_cpuid_set_model_id(Object *obj, const char *model_id, 5981 Error **errp) 5982 { 5983 X86CPU *cpu = X86_CPU(obj); 5984 CPUX86State *env = &cpu->env; 5985 int c, len, i; 5986 5987 if (model_id == NULL) { 5988 model_id = ""; 5989 } 5990 len = strlen(model_id); 5991 memset(env->cpuid_model, 0, 48); 5992 for (i = 0; i < 48; i++) { 5993 if (i >= len) { 5994 c = '\0'; 5995 } else { 5996 c = (uint8_t)model_id[i]; 5997 } 5998 env->cpuid_model[i >> 2] |= c << (8 * (i & 3)); 5999 } 6000 } 6001 6002 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name, 6003 void *opaque, Error **errp) 6004 { 6005 X86CPU *cpu = X86_CPU(obj); 6006 int64_t value; 6007 6008 value = cpu->env.tsc_khz * 1000; 6009 visit_type_int(v, name, &value, errp); 6010 } 6011 6012 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name, 6013 void *opaque, Error **errp) 6014 { 6015 X86CPU *cpu = X86_CPU(obj); 6016 const int64_t max = INT64_MAX; 6017 int64_t value; 6018 6019 if (!visit_type_int(v, name, &value, errp)) { 6020 return; 6021 } 6022 if (value < 0 || value > max) { 6023 error_setg(errp, "parameter '%s' can be at most %" PRId64, 6024 name ? name : "null", max); 6025 return; 6026 } 6027 6028 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000; 6029 } 6030 6031 /* Generic getter for "feature-words" and "filtered-features" properties */ 6032 static void x86_cpu_get_feature_words(Object *obj, Visitor *v, 6033 const char *name, void *opaque, 6034 Error **errp) 6035 { 6036 uint64_t *array = (uint64_t *)opaque; 6037 FeatureWord w; 6038 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { }; 6039 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { }; 6040 X86CPUFeatureWordInfoList *list = NULL; 6041 6042 for (w = 0; w < FEATURE_WORDS; w++) { 6043 FeatureWordInfo *wi = &feature_word_info[w]; 6044 /* 6045 * We didn't have MSR features when "feature-words" was 6046 * introduced. Therefore skipped other type entries. 6047 */ 6048 if (wi->type != CPUID_FEATURE_WORD) { 6049 continue; 6050 } 6051 X86CPUFeatureWordInfo *qwi = &word_infos[w]; 6052 qwi->cpuid_input_eax = wi->cpuid.eax; 6053 qwi->has_cpuid_input_ecx = wi->cpuid.needs_ecx; 6054 qwi->cpuid_input_ecx = wi->cpuid.ecx; 6055 qwi->cpuid_register = x86_reg_info_32[wi->cpuid.reg].qapi_enum; 6056 qwi->features = array[w]; 6057 6058 /* List will be in reverse order, but order shouldn't matter */ 6059 list_entries[w].next = list; 6060 list_entries[w].value = &word_infos[w]; 6061 list = &list_entries[w]; 6062 } 6063 6064 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp); 6065 } 6066 6067 /* Convert all '_' in a feature string option name to '-', to make feature 6068 * name conform to QOM property naming rule, which uses '-' instead of '_'. 6069 */ 6070 static inline void feat2prop(char *s) 6071 { 6072 while ((s = strchr(s, '_'))) { 6073 *s = '-'; 6074 } 6075 } 6076 6077 /* Return the feature property name for a feature flag bit */ 6078 static const char *x86_cpu_feature_name(FeatureWord w, int bitnr) 6079 { 6080 const char *name; 6081 /* XSAVE components are automatically enabled by other features, 6082 * so return the original feature name instead 6083 */ 6084 if (w == FEAT_XSAVE_XCR0_LO || w == FEAT_XSAVE_XCR0_HI) { 6085 int comp = (w == FEAT_XSAVE_XCR0_HI) ? bitnr + 32 : bitnr; 6086 6087 if (comp < ARRAY_SIZE(x86_ext_save_areas) && 6088 x86_ext_save_areas[comp].bits) { 6089 w = x86_ext_save_areas[comp].feature; 6090 bitnr = ctz32(x86_ext_save_areas[comp].bits); 6091 } 6092 } 6093 6094 assert(bitnr < 64); 6095 assert(w < FEATURE_WORDS); 6096 name = feature_word_info[w].feat_names[bitnr]; 6097 assert(bitnr < 32 || !(name && feature_word_info[w].type == CPUID_FEATURE_WORD)); 6098 return name; 6099 } 6100 6101 /* Compatibility hack to maintain legacy +-feat semantic, 6102 * where +-feat overwrites any feature set by 6103 * feat=on|feat even if the later is parsed after +-feat 6104 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled) 6105 */ 6106 static GList *plus_features, *minus_features; 6107 6108 static gint compare_string(gconstpointer a, gconstpointer b) 6109 { 6110 return g_strcmp0(a, b); 6111 } 6112 6113 /* Parse "+feature,-feature,feature=foo" CPU feature string 6114 */ 6115 static void x86_cpu_parse_featurestr(const char *typename, char *features, 6116 Error **errp) 6117 { 6118 char *featurestr; /* Single 'key=value" string being parsed */ 6119 static bool cpu_globals_initialized; 6120 bool ambiguous = false; 6121 6122 if (cpu_globals_initialized) { 6123 return; 6124 } 6125 cpu_globals_initialized = true; 6126 6127 if (!features) { 6128 return; 6129 } 6130 6131 for (featurestr = strtok(features, ","); 6132 featurestr; 6133 featurestr = strtok(NULL, ",")) { 6134 const char *name; 6135 const char *val = NULL; 6136 char *eq = NULL; 6137 char num[32]; 6138 GlobalProperty *prop; 6139 6140 /* Compatibility syntax: */ 6141 if (featurestr[0] == '+') { 6142 plus_features = g_list_append(plus_features, 6143 g_strdup(featurestr + 1)); 6144 continue; 6145 } else if (featurestr[0] == '-') { 6146 minus_features = g_list_append(minus_features, 6147 g_strdup(featurestr + 1)); 6148 continue; 6149 } 6150 6151 eq = strchr(featurestr, '='); 6152 if (eq) { 6153 *eq++ = 0; 6154 val = eq; 6155 } else { 6156 val = "on"; 6157 } 6158 6159 feat2prop(featurestr); 6160 name = featurestr; 6161 6162 if (g_list_find_custom(plus_features, name, compare_string)) { 6163 warn_report("Ambiguous CPU model string. " 6164 "Don't mix both \"+%s\" and \"%s=%s\"", 6165 name, name, val); 6166 ambiguous = true; 6167 } 6168 if (g_list_find_custom(minus_features, name, compare_string)) { 6169 warn_report("Ambiguous CPU model string. " 6170 "Don't mix both \"-%s\" and \"%s=%s\"", 6171 name, name, val); 6172 ambiguous = true; 6173 } 6174 6175 /* Special case: */ 6176 if (!strcmp(name, "tsc-freq")) { 6177 int ret; 6178 uint64_t tsc_freq; 6179 6180 ret = qemu_strtosz_metric(val, NULL, &tsc_freq); 6181 if (ret < 0 || tsc_freq > INT64_MAX) { 6182 error_setg(errp, "bad numerical value %s", val); 6183 return; 6184 } 6185 snprintf(num, sizeof(num), "%" PRId64, tsc_freq); 6186 val = num; 6187 name = "tsc-frequency"; 6188 } 6189 6190 prop = g_new0(typeof(*prop), 1); 6191 prop->driver = typename; 6192 prop->property = g_strdup(name); 6193 prop->value = g_strdup(val); 6194 qdev_prop_register_global(prop); 6195 } 6196 6197 if (ambiguous) { 6198 warn_report("Compatibility of ambiguous CPU model " 6199 "strings won't be kept on future QEMU versions"); 6200 } 6201 } 6202 6203 static bool x86_cpu_filter_features(X86CPU *cpu, bool verbose); 6204 6205 /* Build a list with the name of all features on a feature word array */ 6206 static void x86_cpu_list_feature_names(FeatureWordArray features, 6207 strList **list) 6208 { 6209 strList **tail = list; 6210 FeatureWord w; 6211 6212 for (w = 0; w < FEATURE_WORDS; w++) { 6213 uint64_t filtered = features[w]; 6214 int i; 6215 for (i = 0; i < 64; i++) { 6216 if (filtered & (1ULL << i)) { 6217 QAPI_LIST_APPEND(tail, g_strdup(x86_cpu_feature_name(w, i))); 6218 } 6219 } 6220 } 6221 } 6222 6223 static void x86_cpu_get_unavailable_features(Object *obj, Visitor *v, 6224 const char *name, void *opaque, 6225 Error **errp) 6226 { 6227 X86CPU *xc = X86_CPU(obj); 6228 strList *result = NULL; 6229 6230 x86_cpu_list_feature_names(xc->filtered_features, &result); 6231 visit_type_strList(v, "unavailable-features", &result, errp); 6232 } 6233 6234 /* Print all cpuid feature names in featureset 6235 */ 6236 static void listflags(GList *features) 6237 { 6238 size_t len = 0; 6239 GList *tmp; 6240 6241 for (tmp = features; tmp; tmp = tmp->next) { 6242 const char *name = tmp->data; 6243 if ((len + strlen(name) + 1) >= 75) { 6244 qemu_printf("\n"); 6245 len = 0; 6246 } 6247 qemu_printf("%s%s", len == 0 ? " " : " ", name); 6248 len += strlen(name) + 1; 6249 } 6250 qemu_printf("\n"); 6251 } 6252 6253 /* Sort alphabetically by type name, respecting X86CPUClass::ordering. */ 6254 static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b, gpointer d) 6255 { 6256 ObjectClass *class_a = (ObjectClass *)a; 6257 ObjectClass *class_b = (ObjectClass *)b; 6258 X86CPUClass *cc_a = X86_CPU_CLASS(class_a); 6259 X86CPUClass *cc_b = X86_CPU_CLASS(class_b); 6260 int ret; 6261 6262 if (cc_a->ordering != cc_b->ordering) { 6263 ret = cc_a->ordering - cc_b->ordering; 6264 } else { 6265 g_autofree char *name_a = x86_cpu_class_get_model_name(cc_a); 6266 g_autofree char *name_b = x86_cpu_class_get_model_name(cc_b); 6267 ret = strcmp(name_a, name_b); 6268 } 6269 return ret; 6270 } 6271 6272 static GSList *get_sorted_cpu_model_list(void) 6273 { 6274 GSList *list = object_class_get_list(TYPE_X86_CPU, false); 6275 list = g_slist_sort_with_data(list, x86_cpu_list_compare, NULL); 6276 return list; 6277 } 6278 6279 static char *x86_cpu_class_get_model_id(X86CPUClass *xc) 6280 { 6281 Object *obj = object_new_with_class(OBJECT_CLASS(xc)); 6282 char *r = object_property_get_str(obj, "model-id", &error_abort); 6283 object_unref(obj); 6284 return r; 6285 } 6286 6287 static char *x86_cpu_class_get_alias_of(X86CPUClass *cc) 6288 { 6289 X86CPUVersion version; 6290 6291 if (!cc->model || !cc->model->is_alias) { 6292 return NULL; 6293 } 6294 version = x86_cpu_model_resolve_version(cc->model); 6295 if (version <= 0) { 6296 return NULL; 6297 } 6298 return x86_cpu_versioned_model_name(cc->model->cpudef, version); 6299 } 6300 6301 static void x86_cpu_list_entry(gpointer data, gpointer user_data) 6302 { 6303 ObjectClass *oc = data; 6304 X86CPUClass *cc = X86_CPU_CLASS(oc); 6305 g_autofree char *name = x86_cpu_class_get_model_name(cc); 6306 g_autofree char *desc = g_strdup(cc->model_description); 6307 g_autofree char *alias_of = x86_cpu_class_get_alias_of(cc); 6308 g_autofree char *model_id = x86_cpu_class_get_model_id(cc); 6309 6310 if (!desc && alias_of) { 6311 if (cc->model && cc->model->version == CPU_VERSION_AUTO) { 6312 desc = g_strdup("(alias configured by machine type)"); 6313 } else { 6314 desc = g_strdup_printf("(alias of %s)", alias_of); 6315 } 6316 } 6317 if (!desc && cc->model && cc->model->note) { 6318 desc = g_strdup_printf("%s [%s]", model_id, cc->model->note); 6319 } 6320 if (!desc) { 6321 desc = g_strdup(model_id); 6322 } 6323 6324 if (cc->model && cc->model->cpudef->deprecation_note) { 6325 g_autofree char *olddesc = desc; 6326 desc = g_strdup_printf("%s (deprecated)", olddesc); 6327 } 6328 6329 qemu_printf(" %-20s %s\n", name, desc); 6330 } 6331 6332 static gint strcmp_wrap(gconstpointer a, gconstpointer b, gpointer d) 6333 { 6334 return strcmp(a, b); 6335 } 6336 6337 /* list available CPU models and flags */ 6338 static void x86_cpu_list(void) 6339 { 6340 int i, j; 6341 GSList *list; 6342 GList *names = NULL; 6343 6344 qemu_printf("Available CPUs:\n"); 6345 list = get_sorted_cpu_model_list(); 6346 g_slist_foreach(list, x86_cpu_list_entry, NULL); 6347 g_slist_free(list); 6348 6349 names = NULL; 6350 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) { 6351 FeatureWordInfo *fw = &feature_word_info[i]; 6352 for (j = 0; j < 64; j++) { 6353 if (fw->feat_names[j]) { 6354 names = g_list_append(names, (gpointer)fw->feat_names[j]); 6355 } 6356 } 6357 } 6358 6359 names = g_list_sort_with_data(names, strcmp_wrap, NULL); 6360 6361 qemu_printf("\nRecognized CPUID flags:\n"); 6362 listflags(names); 6363 qemu_printf("\n"); 6364 g_list_free(names); 6365 } 6366 6367 #ifndef CONFIG_USER_ONLY 6368 6369 /* Check for missing features that may prevent the CPU class from 6370 * running using the current machine and accelerator. 6371 */ 6372 static void x86_cpu_class_check_missing_features(X86CPUClass *xcc, 6373 strList **list) 6374 { 6375 strList **tail = list; 6376 X86CPU *xc; 6377 Error *err = NULL; 6378 6379 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) { 6380 QAPI_LIST_APPEND(tail, g_strdup("kvm")); 6381 return; 6382 } 6383 6384 xc = X86_CPU(object_new_with_class(OBJECT_CLASS(xcc))); 6385 6386 x86_cpu_expand_features(xc, &err); 6387 if (err) { 6388 /* Errors at x86_cpu_expand_features should never happen, 6389 * but in case it does, just report the model as not 6390 * runnable at all using the "type" property. 6391 */ 6392 QAPI_LIST_APPEND(tail, g_strdup("type")); 6393 error_free(err); 6394 } 6395 6396 x86_cpu_filter_features(xc, false); 6397 6398 x86_cpu_list_feature_names(xc->filtered_features, tail); 6399 6400 object_unref(OBJECT(xc)); 6401 } 6402 6403 static void x86_cpu_definition_entry(gpointer data, gpointer user_data) 6404 { 6405 ObjectClass *oc = data; 6406 X86CPUClass *cc = X86_CPU_CLASS(oc); 6407 CpuDefinitionInfoList **cpu_list = user_data; 6408 CpuDefinitionInfo *info; 6409 6410 info = g_malloc0(sizeof(*info)); 6411 info->name = x86_cpu_class_get_model_name(cc); 6412 x86_cpu_class_check_missing_features(cc, &info->unavailable_features); 6413 info->has_unavailable_features = true; 6414 info->q_typename = g_strdup(object_class_get_name(oc)); 6415 info->migration_safe = cc->migration_safe; 6416 info->has_migration_safe = true; 6417 info->q_static = cc->static_model; 6418 if (cc->model && cc->model->cpudef->deprecation_note) { 6419 info->deprecated = true; 6420 } else { 6421 info->deprecated = false; 6422 } 6423 /* 6424 * Old machine types won't report aliases, so that alias translation 6425 * doesn't break compatibility with previous QEMU versions. 6426 */ 6427 if (default_cpu_version != CPU_VERSION_LEGACY) { 6428 info->alias_of = x86_cpu_class_get_alias_of(cc); 6429 } 6430 6431 QAPI_LIST_PREPEND(*cpu_list, info); 6432 } 6433 6434 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) 6435 { 6436 CpuDefinitionInfoList *cpu_list = NULL; 6437 GSList *list = get_sorted_cpu_model_list(); 6438 g_slist_foreach(list, x86_cpu_definition_entry, &cpu_list); 6439 g_slist_free(list); 6440 return cpu_list; 6441 } 6442 6443 #endif /* !CONFIG_USER_ONLY */ 6444 6445 uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w) 6446 { 6447 FeatureWordInfo *wi = &feature_word_info[w]; 6448 uint64_t r = 0; 6449 uint64_t unavail = 0; 6450 6451 if (kvm_enabled()) { 6452 switch (wi->type) { 6453 case CPUID_FEATURE_WORD: 6454 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid.eax, 6455 wi->cpuid.ecx, 6456 wi->cpuid.reg); 6457 break; 6458 case MSR_FEATURE_WORD: 6459 r = kvm_arch_get_supported_msr_feature(kvm_state, 6460 wi->msr.index); 6461 break; 6462 } 6463 } else if (hvf_enabled()) { 6464 if (wi->type != CPUID_FEATURE_WORD) { 6465 return 0; 6466 } 6467 r = hvf_get_supported_cpuid(wi->cpuid.eax, 6468 wi->cpuid.ecx, 6469 wi->cpuid.reg); 6470 } else if (tcg_enabled()) { 6471 r = wi->tcg_features; 6472 } else { 6473 return ~0; 6474 } 6475 6476 switch (w) { 6477 #ifndef TARGET_X86_64 6478 case FEAT_8000_0001_EDX: 6479 /* 6480 * 32-bit TCG can emulate 64-bit compatibility mode. If there is no 6481 * way for userspace to get out of its 32-bit jail, we can leave 6482 * the LM bit set. 6483 */ 6484 unavail = tcg_enabled() 6485 ? CPUID_EXT2_LM & ~CPUID_EXT2_KERNEL_FEATURES 6486 : CPUID_EXT2_LM; 6487 break; 6488 #endif 6489 6490 case FEAT_8000_0007_EBX: 6491 if (cpu && !IS_AMD_CPU(&cpu->env)) { 6492 /* Disable AMD machine check architecture for Intel CPU. */ 6493 unavail = ~0; 6494 } 6495 break; 6496 6497 case FEAT_7_0_EBX: 6498 #ifndef CONFIG_USER_ONLY 6499 if (!check_sgx_support()) { 6500 unavail = CPUID_7_0_EBX_SGX; 6501 } 6502 #endif 6503 break; 6504 case FEAT_7_0_ECX: 6505 #ifndef CONFIG_USER_ONLY 6506 if (!check_sgx_support()) { 6507 unavail = CPUID_7_0_ECX_SGX_LC; 6508 } 6509 #endif 6510 break; 6511 6512 default: 6513 break; 6514 } 6515 6516 r &= ~unavail; 6517 if (cpu && cpu->migratable) { 6518 r &= x86_cpu_get_migratable_flags(cpu, w); 6519 } 6520 return r; 6521 } 6522 6523 static void x86_cpu_get_supported_cpuid(uint32_t func, uint32_t index, 6524 uint32_t *eax, uint32_t *ebx, 6525 uint32_t *ecx, uint32_t *edx) 6526 { 6527 if (kvm_enabled()) { 6528 *eax = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EAX); 6529 *ebx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EBX); 6530 *ecx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_ECX); 6531 *edx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EDX); 6532 } else if (hvf_enabled()) { 6533 *eax = hvf_get_supported_cpuid(func, index, R_EAX); 6534 *ebx = hvf_get_supported_cpuid(func, index, R_EBX); 6535 *ecx = hvf_get_supported_cpuid(func, index, R_ECX); 6536 *edx = hvf_get_supported_cpuid(func, index, R_EDX); 6537 } else { 6538 *eax = 0; 6539 *ebx = 0; 6540 *ecx = 0; 6541 *edx = 0; 6542 } 6543 } 6544 6545 static void x86_cpu_get_cache_cpuid(uint32_t func, uint32_t index, 6546 uint32_t *eax, uint32_t *ebx, 6547 uint32_t *ecx, uint32_t *edx) 6548 { 6549 uint32_t level, unused; 6550 6551 /* Only return valid host leaves. */ 6552 switch (func) { 6553 case 2: 6554 case 4: 6555 host_cpuid(0, 0, &level, &unused, &unused, &unused); 6556 break; 6557 case 0x80000005: 6558 case 0x80000006: 6559 case 0x8000001d: 6560 host_cpuid(0x80000000, 0, &level, &unused, &unused, &unused); 6561 break; 6562 default: 6563 return; 6564 } 6565 6566 if (func > level) { 6567 *eax = 0; 6568 *ebx = 0; 6569 *ecx = 0; 6570 *edx = 0; 6571 } else { 6572 host_cpuid(func, index, eax, ebx, ecx, edx); 6573 } 6574 } 6575 6576 /* 6577 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 6578 */ 6579 void x86_cpu_apply_props(X86CPU *cpu, PropValue *props) 6580 { 6581 PropValue *pv; 6582 for (pv = props; pv->prop; pv++) { 6583 if (!pv->value) { 6584 continue; 6585 } 6586 object_property_parse(OBJECT(cpu), pv->prop, pv->value, 6587 &error_abort); 6588 } 6589 } 6590 6591 /* 6592 * Apply properties for the CPU model version specified in model. 6593 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 6594 */ 6595 6596 static void x86_cpu_apply_version_props(X86CPU *cpu, const X86CPUModel *model) 6597 { 6598 const X86CPUVersionDefinition *vdef; 6599 X86CPUVersion version = x86_cpu_model_resolve_version(model); 6600 6601 if (version == CPU_VERSION_LEGACY) { 6602 return; 6603 } 6604 6605 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) { 6606 PropValue *p; 6607 6608 for (p = vdef->props; p && p->prop; p++) { 6609 object_property_parse(OBJECT(cpu), p->prop, p->value, 6610 &error_abort); 6611 } 6612 6613 if (vdef->version == version) { 6614 break; 6615 } 6616 } 6617 6618 /* 6619 * If we reached the end of the list, version number was invalid 6620 */ 6621 assert(vdef->version == version); 6622 } 6623 6624 static const CPUCaches *x86_cpu_get_versioned_cache_info(X86CPU *cpu, 6625 const X86CPUModel *model) 6626 { 6627 const X86CPUVersionDefinition *vdef; 6628 X86CPUVersion version = x86_cpu_model_resolve_version(model); 6629 const CPUCaches *cache_info = model->cpudef->cache_info; 6630 6631 if (version == CPU_VERSION_LEGACY) { 6632 return cache_info; 6633 } 6634 6635 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) { 6636 if (vdef->cache_info) { 6637 cache_info = vdef->cache_info; 6638 } 6639 6640 if (vdef->version == version) { 6641 break; 6642 } 6643 } 6644 6645 assert(vdef->version == version); 6646 return cache_info; 6647 } 6648 6649 /* 6650 * Load data from X86CPUDefinition into a X86CPU object. 6651 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 6652 */ 6653 static void x86_cpu_load_model(X86CPU *cpu, const X86CPUModel *model) 6654 { 6655 const X86CPUDefinition *def = model->cpudef; 6656 CPUX86State *env = &cpu->env; 6657 FeatureWord w; 6658 6659 /*NOTE: any property set by this function should be returned by 6660 * x86_cpu_static_props(), so static expansion of 6661 * query-cpu-model-expansion is always complete. 6662 */ 6663 6664 /* CPU models only set _minimum_ values for level/xlevel: */ 6665 object_property_set_uint(OBJECT(cpu), "min-level", def->level, 6666 &error_abort); 6667 object_property_set_uint(OBJECT(cpu), "min-xlevel", def->xlevel, 6668 &error_abort); 6669 6670 object_property_set_int(OBJECT(cpu), "family", def->family, &error_abort); 6671 object_property_set_int(OBJECT(cpu), "model", def->model, &error_abort); 6672 object_property_set_int(OBJECT(cpu), "stepping", def->stepping, 6673 &error_abort); 6674 object_property_set_str(OBJECT(cpu), "model-id", def->model_id, 6675 &error_abort); 6676 for (w = 0; w < FEATURE_WORDS; w++) { 6677 env->features[w] = def->features[w]; 6678 } 6679 6680 /* legacy-cache defaults to 'off' if CPU model provides cache info */ 6681 cpu->legacy_cache = !x86_cpu_get_versioned_cache_info(cpu, model); 6682 6683 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR; 6684 6685 /* sysenter isn't supported in compatibility mode on AMD, 6686 * syscall isn't supported in compatibility mode on Intel. 6687 * Normally we advertise the actual CPU vendor, but you can 6688 * override this using the 'vendor' property if you want to use 6689 * KVM's sysenter/syscall emulation in compatibility mode and 6690 * when doing cross vendor migration 6691 */ 6692 6693 /* 6694 * vendor property is set here but then overloaded with the 6695 * host cpu vendor for KVM and HVF. 6696 */ 6697 object_property_set_str(OBJECT(cpu), "vendor", def->vendor, &error_abort); 6698 6699 object_property_set_uint(OBJECT(cpu), "avx10-version", def->avx10_version, 6700 &error_abort); 6701 6702 x86_cpu_apply_version_props(cpu, model); 6703 6704 /* 6705 * Properties in versioned CPU model are not user specified features. 6706 * We can simply clear env->user_features here since it will be filled later 6707 * in x86_cpu_expand_features() based on plus_features and minus_features. 6708 */ 6709 memset(&env->user_features, 0, sizeof(env->user_features)); 6710 } 6711 6712 static const gchar *x86_gdb_arch_name(CPUState *cs) 6713 { 6714 #ifdef TARGET_X86_64 6715 return "i386:x86-64"; 6716 #else 6717 return "i386"; 6718 #endif 6719 } 6720 6721 static void x86_cpu_cpudef_class_init(ObjectClass *oc, const void *data) 6722 { 6723 const X86CPUModel *model = data; 6724 X86CPUClass *xcc = X86_CPU_CLASS(oc); 6725 CPUClass *cc = CPU_CLASS(oc); 6726 6727 xcc->model = model; 6728 xcc->migration_safe = true; 6729 cc->deprecation_note = model->cpudef->deprecation_note; 6730 } 6731 6732 static void x86_register_cpu_model_type(const char *name, X86CPUModel *model) 6733 { 6734 g_autofree char *typename = x86_cpu_type_name(name); 6735 TypeInfo ti = { 6736 .name = typename, 6737 .parent = TYPE_X86_CPU, 6738 .class_init = x86_cpu_cpudef_class_init, 6739 .class_data = model, 6740 }; 6741 6742 type_register_static(&ti); 6743 } 6744 6745 6746 /* 6747 * register builtin_x86_defs; 6748 * "max", "base" and subclasses ("host") are not registered here. 6749 * See x86_cpu_register_types for all model registrations. 6750 */ 6751 static void x86_register_cpudef_types(const X86CPUDefinition *def) 6752 { 6753 X86CPUModel *m; 6754 const X86CPUVersionDefinition *vdef; 6755 6756 /* AMD aliases are handled at runtime based on CPUID vendor, so 6757 * they shouldn't be set on the CPU model table. 6758 */ 6759 assert(!(def->features[FEAT_8000_0001_EDX] & CPUID_EXT2_AMD_ALIASES)); 6760 /* catch mistakes instead of silently truncating model_id when too long */ 6761 assert(def->model_id && strlen(def->model_id) <= 48); 6762 6763 /* Unversioned model: */ 6764 m = g_new0(X86CPUModel, 1); 6765 m->cpudef = def; 6766 m->version = CPU_VERSION_AUTO; 6767 m->is_alias = true; 6768 x86_register_cpu_model_type(def->name, m); 6769 6770 /* Versioned models: */ 6771 6772 for (vdef = x86_cpu_def_get_versions(def); vdef->version; vdef++) { 6773 g_autofree char *name = 6774 x86_cpu_versioned_model_name(def, vdef->version); 6775 6776 m = g_new0(X86CPUModel, 1); 6777 m->cpudef = def; 6778 m->version = vdef->version; 6779 m->note = vdef->note; 6780 x86_register_cpu_model_type(name, m); 6781 6782 if (vdef->alias) { 6783 X86CPUModel *am = g_new0(X86CPUModel, 1); 6784 am->cpudef = def; 6785 am->version = vdef->version; 6786 am->is_alias = true; 6787 x86_register_cpu_model_type(vdef->alias, am); 6788 } 6789 } 6790 6791 } 6792 6793 uint32_t cpu_x86_virtual_addr_width(CPUX86State *env) 6794 { 6795 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57) { 6796 return 57; /* 57 bits virtual */ 6797 } else { 6798 return 48; /* 48 bits virtual */ 6799 } 6800 } 6801 6802 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, 6803 uint32_t *eax, uint32_t *ebx, 6804 uint32_t *ecx, uint32_t *edx) 6805 { 6806 X86CPU *cpu = env_archcpu(env); 6807 CPUState *cs = env_cpu(env); 6808 uint32_t limit; 6809 uint32_t signature[3]; 6810 X86CPUTopoInfo *topo_info = &env->topo_info; 6811 uint32_t threads_per_pkg; 6812 6813 threads_per_pkg = x86_threads_per_pkg(topo_info); 6814 6815 /* Calculate & apply limits for different index ranges */ 6816 if (index >= 0xC0000000) { 6817 limit = env->cpuid_xlevel2; 6818 } else if (index >= 0x80000000) { 6819 limit = env->cpuid_xlevel; 6820 } else if (index >= 0x40000000) { 6821 limit = 0x40000001; 6822 } else { 6823 limit = env->cpuid_level; 6824 } 6825 6826 if (index > limit) { 6827 /* Intel documentation states that invalid EAX input will 6828 * return the same information as EAX=cpuid_level 6829 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID) 6830 */ 6831 index = env->cpuid_level; 6832 } 6833 6834 switch(index) { 6835 case 0: 6836 *eax = env->cpuid_level; 6837 *ebx = env->cpuid_vendor1; 6838 *edx = env->cpuid_vendor2; 6839 *ecx = env->cpuid_vendor3; 6840 break; 6841 case 1: 6842 *eax = env->cpuid_version; 6843 *ebx = (cpu->apic_id << 24) | 6844 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */ 6845 *ecx = env->features[FEAT_1_ECX]; 6846 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) { 6847 *ecx |= CPUID_EXT_OSXSAVE; 6848 } 6849 *edx = env->features[FEAT_1_EDX]; 6850 if (threads_per_pkg > 1) { 6851 *ebx |= threads_per_pkg << 16; 6852 } 6853 if (!cpu->enable_pmu) { 6854 *ecx &= ~CPUID_EXT_PDCM; 6855 } 6856 break; 6857 case 2: 6858 /* cache info: needed for Pentium Pro compatibility */ 6859 if (cpu->cache_info_passthrough) { 6860 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 6861 break; 6862 } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { 6863 *eax = *ebx = *ecx = *edx = 0; 6864 break; 6865 } 6866 *eax = 1; /* Number of CPUID[EAX=2] calls required */ 6867 *ebx = 0; 6868 if (!cpu->enable_l3_cache) { 6869 *ecx = 0; 6870 } else { 6871 *ecx = cpuid2_cache_descriptor(env->cache_info_cpuid2.l3_cache); 6872 } 6873 *edx = (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1d_cache) << 16) | 6874 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1i_cache) << 8) | 6875 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l2_cache)); 6876 break; 6877 case 4: 6878 /* cache info: needed for Core compatibility */ 6879 if (cpu->cache_info_passthrough) { 6880 x86_cpu_get_cache_cpuid(index, count, eax, ebx, ecx, edx); 6881 /* 6882 * QEMU has its own number of cores/logical cpus, 6883 * set 24..14, 31..26 bit to configured values 6884 */ 6885 if (*eax & 31) { 6886 int host_vcpus_per_cache = 1 + ((*eax & 0x3FFC000) >> 14); 6887 6888 *eax &= ~0xFC000000; 6889 *eax |= max_core_ids_in_package(topo_info) << 26; 6890 if (host_vcpus_per_cache > threads_per_pkg) { 6891 *eax &= ~0x3FFC000; 6892 6893 /* Share the cache at package level. */ 6894 *eax |= max_thread_ids_for_cache(topo_info, 6895 CPU_TOPOLOGY_LEVEL_SOCKET) << 14; 6896 } 6897 } 6898 } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { 6899 *eax = *ebx = *ecx = *edx = 0; 6900 } else { 6901 *eax = 0; 6902 6903 switch (count) { 6904 case 0: /* L1 dcache info */ 6905 encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache, 6906 topo_info, 6907 eax, ebx, ecx, edx); 6908 if (!cpu->l1_cache_per_core) { 6909 *eax &= ~MAKE_64BIT_MASK(14, 12); 6910 } 6911 break; 6912 case 1: /* L1 icache info */ 6913 encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache, 6914 topo_info, 6915 eax, ebx, ecx, edx); 6916 if (!cpu->l1_cache_per_core) { 6917 *eax &= ~MAKE_64BIT_MASK(14, 12); 6918 } 6919 break; 6920 case 2: /* L2 cache info */ 6921 encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache, 6922 topo_info, 6923 eax, ebx, ecx, edx); 6924 break; 6925 case 3: /* L3 cache info */ 6926 if (cpu->enable_l3_cache) { 6927 encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache, 6928 topo_info, 6929 eax, ebx, ecx, edx); 6930 break; 6931 } 6932 /* fall through */ 6933 default: /* end of info */ 6934 *eax = *ebx = *ecx = *edx = 0; 6935 break; 6936 } 6937 } 6938 break; 6939 case 5: 6940 /* MONITOR/MWAIT Leaf */ 6941 *eax = cpu->mwait.eax; /* Smallest monitor-line size in bytes */ 6942 *ebx = cpu->mwait.ebx; /* Largest monitor-line size in bytes */ 6943 *ecx = cpu->mwait.ecx; /* flags */ 6944 *edx = cpu->mwait.edx; /* mwait substates */ 6945 break; 6946 case 6: 6947 /* Thermal and Power Leaf */ 6948 *eax = env->features[FEAT_6_EAX]; 6949 *ebx = 0; 6950 *ecx = 0; 6951 *edx = 0; 6952 break; 6953 case 7: 6954 /* Structured Extended Feature Flags Enumeration Leaf */ 6955 if (count == 0) { 6956 /* Maximum ECX value for sub-leaves */ 6957 *eax = env->cpuid_level_func7; 6958 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */ 6959 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */ 6960 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) { 6961 *ecx |= CPUID_7_0_ECX_OSPKE; 6962 } 6963 *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */ 6964 } else if (count == 1) { 6965 *eax = env->features[FEAT_7_1_EAX]; 6966 *edx = env->features[FEAT_7_1_EDX]; 6967 *ebx = 0; 6968 *ecx = 0; 6969 } else if (count == 2) { 6970 *edx = env->features[FEAT_7_2_EDX]; 6971 *eax = 0; 6972 *ebx = 0; 6973 *ecx = 0; 6974 } else { 6975 *eax = 0; 6976 *ebx = 0; 6977 *ecx = 0; 6978 *edx = 0; 6979 } 6980 break; 6981 case 9: 6982 /* Direct Cache Access Information Leaf */ 6983 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */ 6984 *ebx = 0; 6985 *ecx = 0; 6986 *edx = 0; 6987 break; 6988 case 0xA: 6989 /* Architectural Performance Monitoring Leaf */ 6990 if (cpu->enable_pmu) { 6991 x86_cpu_get_supported_cpuid(0xA, count, eax, ebx, ecx, edx); 6992 } else { 6993 *eax = 0; 6994 *ebx = 0; 6995 *ecx = 0; 6996 *edx = 0; 6997 } 6998 break; 6999 case 0xB: 7000 /* Extended Topology Enumeration Leaf */ 7001 if (!cpu->enable_cpuid_0xb) { 7002 *eax = *ebx = *ecx = *edx = 0; 7003 break; 7004 } 7005 7006 *ecx = count & 0xff; 7007 *edx = cpu->apic_id; 7008 7009 switch (count) { 7010 case 0: 7011 *eax = apicid_core_offset(topo_info); 7012 *ebx = topo_info->threads_per_core; 7013 *ecx |= CPUID_B_ECX_TOPO_LEVEL_SMT << 8; 7014 break; 7015 case 1: 7016 *eax = apicid_pkg_offset(topo_info); 7017 *ebx = threads_per_pkg; 7018 *ecx |= CPUID_B_ECX_TOPO_LEVEL_CORE << 8; 7019 break; 7020 default: 7021 *eax = 0; 7022 *ebx = 0; 7023 *ecx |= CPUID_B_ECX_TOPO_LEVEL_INVALID << 8; 7024 } 7025 7026 assert(!(*eax & ~0x1f)); 7027 *ebx &= 0xffff; /* The count doesn't need to be reliable. */ 7028 break; 7029 case 0x1C: 7030 if (cpu->enable_pmu && (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) { 7031 x86_cpu_get_supported_cpuid(0x1C, 0, eax, ebx, ecx, edx); 7032 *edx = 0; 7033 } 7034 break; 7035 case 0x1F: 7036 /* V2 Extended Topology Enumeration Leaf */ 7037 if (!x86_has_extended_topo(env->avail_cpu_topo)) { 7038 *eax = *ebx = *ecx = *edx = 0; 7039 break; 7040 } 7041 7042 encode_topo_cpuid1f(env, count, topo_info, eax, ebx, ecx, edx); 7043 break; 7044 case 0xD: { 7045 /* Processor Extended State */ 7046 *eax = 0; 7047 *ebx = 0; 7048 *ecx = 0; 7049 *edx = 0; 7050 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { 7051 break; 7052 } 7053 7054 if (count == 0) { 7055 *ecx = xsave_area_size(x86_cpu_xsave_xcr0_components(cpu), false); 7056 *eax = env->features[FEAT_XSAVE_XCR0_LO]; 7057 *edx = env->features[FEAT_XSAVE_XCR0_HI]; 7058 /* 7059 * The initial value of xcr0 and ebx == 0, On host without kvm 7060 * commit 412a3c41(e.g., CentOS 6), the ebx's value always == 0 7061 * even through guest update xcr0, this will crash some legacy guest 7062 * (e.g., CentOS 6), So set ebx == ecx to workaround it. 7063 */ 7064 *ebx = kvm_enabled() ? *ecx : xsave_area_size(env->xcr0, false); 7065 } else if (count == 1) { 7066 uint64_t xstate = x86_cpu_xsave_xcr0_components(cpu) | 7067 x86_cpu_xsave_xss_components(cpu); 7068 7069 *eax = env->features[FEAT_XSAVE]; 7070 *ebx = xsave_area_size(xstate, true); 7071 *ecx = env->features[FEAT_XSAVE_XSS_LO]; 7072 *edx = env->features[FEAT_XSAVE_XSS_HI]; 7073 if (kvm_enabled() && cpu->enable_pmu && 7074 (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR) && 7075 (*eax & CPUID_XSAVE_XSAVES)) { 7076 *ecx |= XSTATE_ARCH_LBR_MASK; 7077 } else { 7078 *ecx &= ~XSTATE_ARCH_LBR_MASK; 7079 } 7080 } else if (count == 0xf && cpu->enable_pmu 7081 && (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) { 7082 x86_cpu_get_supported_cpuid(0xD, count, eax, ebx, ecx, edx); 7083 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) { 7084 const ExtSaveArea *esa = &x86_ext_save_areas[count]; 7085 7086 if (x86_cpu_xsave_xcr0_components(cpu) & (1ULL << count)) { 7087 *eax = esa->size; 7088 *ebx = esa->offset; 7089 *ecx = esa->ecx & 7090 (ESA_FEATURE_ALIGN64_MASK | ESA_FEATURE_XFD_MASK); 7091 } else if (x86_cpu_xsave_xss_components(cpu) & (1ULL << count)) { 7092 *eax = esa->size; 7093 *ebx = 0; 7094 *ecx = 1; 7095 } 7096 } 7097 break; 7098 } 7099 case 0x12: 7100 #ifndef CONFIG_USER_ONLY 7101 if (!kvm_enabled() || 7102 !(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX)) { 7103 *eax = *ebx = *ecx = *edx = 0; 7104 break; 7105 } 7106 7107 /* 7108 * SGX sub-leafs CPUID.0x12.{0x2..N} enumerate EPC sections. Retrieve 7109 * the EPC properties, e.g. confidentiality and integrity, from the 7110 * host's first EPC section, i.e. assume there is one EPC section or 7111 * that all EPC sections have the same security properties. 7112 */ 7113 if (count > 1) { 7114 uint64_t epc_addr, epc_size; 7115 7116 if (sgx_epc_get_section(count - 2, &epc_addr, &epc_size)) { 7117 *eax = *ebx = *ecx = *edx = 0; 7118 break; 7119 } 7120 host_cpuid(index, 2, eax, ebx, ecx, edx); 7121 *eax = (uint32_t)(epc_addr & 0xfffff000) | 0x1; 7122 *ebx = (uint32_t)(epc_addr >> 32); 7123 *ecx = (uint32_t)(epc_size & 0xfffff000) | (*ecx & 0xf); 7124 *edx = (uint32_t)(epc_size >> 32); 7125 break; 7126 } 7127 7128 /* 7129 * SGX sub-leafs CPUID.0x12.{0x0,0x1} are heavily dependent on hardware 7130 * and KVM, i.e. QEMU cannot emulate features to override what KVM 7131 * supports. Features can be further restricted by userspace, but not 7132 * made more permissive. 7133 */ 7134 x86_cpu_get_supported_cpuid(0x12, count, eax, ebx, ecx, edx); 7135 7136 if (count == 0) { 7137 *eax &= env->features[FEAT_SGX_12_0_EAX]; 7138 *ebx &= env->features[FEAT_SGX_12_0_EBX]; 7139 } else { 7140 *eax &= env->features[FEAT_SGX_12_1_EAX]; 7141 *ebx &= 0; /* ebx reserve */ 7142 *ecx &= env->features[FEAT_XSAVE_XCR0_LO]; 7143 *edx &= env->features[FEAT_XSAVE_XCR0_HI]; 7144 7145 /* FP and SSE are always allowed regardless of XSAVE/XCR0. */ 7146 *ecx |= XSTATE_FP_MASK | XSTATE_SSE_MASK; 7147 7148 /* Access to PROVISIONKEY requires additional credentials. */ 7149 if ((*eax & (1U << 4)) && 7150 !kvm_enable_sgx_provisioning(cs->kvm_state)) { 7151 *eax &= ~(1U << 4); 7152 } 7153 } 7154 #endif 7155 break; 7156 case 0x14: { 7157 /* Intel Processor Trace Enumeration */ 7158 *eax = 0; 7159 *ebx = 0; 7160 *ecx = 0; 7161 *edx = 0; 7162 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) || 7163 !kvm_enabled()) { 7164 break; 7165 } 7166 7167 /* 7168 * If these are changed, they should stay in sync with 7169 * x86_cpu_filter_features(). 7170 */ 7171 if (count == 0) { 7172 *eax = INTEL_PT_MAX_SUBLEAF; 7173 *ebx = INTEL_PT_MINIMAL_EBX; 7174 *ecx = INTEL_PT_MINIMAL_ECX; 7175 if (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP) { 7176 *ecx |= CPUID_14_0_ECX_LIP; 7177 } 7178 } else if (count == 1) { 7179 *eax = INTEL_PT_MTC_BITMAP | INTEL_PT_ADDR_RANGES_NUM; 7180 *ebx = INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP; 7181 } 7182 break; 7183 } 7184 case 0x1D: { 7185 /* AMX TILE, for now hardcoded for Sapphire Rapids*/ 7186 *eax = 0; 7187 *ebx = 0; 7188 *ecx = 0; 7189 *edx = 0; 7190 if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) { 7191 break; 7192 } 7193 7194 if (count == 0) { 7195 /* Highest numbered palette subleaf */ 7196 *eax = INTEL_AMX_TILE_MAX_SUBLEAF; 7197 } else if (count == 1) { 7198 *eax = INTEL_AMX_TOTAL_TILE_BYTES | 7199 (INTEL_AMX_BYTES_PER_TILE << 16); 7200 *ebx = INTEL_AMX_BYTES_PER_ROW | (INTEL_AMX_TILE_MAX_NAMES << 16); 7201 *ecx = INTEL_AMX_TILE_MAX_ROWS; 7202 } 7203 break; 7204 } 7205 case 0x1E: { 7206 /* AMX TMUL, for now hardcoded for Sapphire Rapids */ 7207 *eax = 0; 7208 *ebx = 0; 7209 *ecx = 0; 7210 *edx = 0; 7211 if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) { 7212 break; 7213 } 7214 7215 if (count == 0) { 7216 /* Highest numbered palette subleaf */ 7217 *ebx = INTEL_AMX_TMUL_MAX_K | (INTEL_AMX_TMUL_MAX_N << 8); 7218 } 7219 break; 7220 } 7221 case 0x24: { 7222 *eax = 0; 7223 *ebx = 0; 7224 *ecx = 0; 7225 *edx = 0; 7226 if ((env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) && count == 0) { 7227 *ebx = env->features[FEAT_24_0_EBX] | env->avx10_version; 7228 } 7229 break; 7230 } 7231 case 0x40000000: 7232 /* 7233 * CPUID code in kvm_arch_init_vcpu() ignores stuff 7234 * set here, but we restrict to TCG none the less. 7235 */ 7236 if (tcg_enabled() && cpu->expose_tcg) { 7237 memcpy(signature, "TCGTCGTCGTCG", 12); 7238 *eax = 0x40000001; 7239 *ebx = signature[0]; 7240 *ecx = signature[1]; 7241 *edx = signature[2]; 7242 } else { 7243 *eax = 0; 7244 *ebx = 0; 7245 *ecx = 0; 7246 *edx = 0; 7247 } 7248 break; 7249 case 0x40000001: 7250 *eax = 0; 7251 *ebx = 0; 7252 *ecx = 0; 7253 *edx = 0; 7254 break; 7255 case 0x80000000: 7256 *eax = env->cpuid_xlevel; 7257 *ebx = env->cpuid_vendor1; 7258 *edx = env->cpuid_vendor2; 7259 *ecx = env->cpuid_vendor3; 7260 break; 7261 case 0x80000001: 7262 *eax = env->cpuid_version; 7263 *ebx = 0; 7264 *ecx = env->features[FEAT_8000_0001_ECX]; 7265 *edx = env->features[FEAT_8000_0001_EDX]; 7266 7267 if (tcg_enabled() && env->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && 7268 !(env->hflags & HF_LMA_MASK)) { 7269 *edx &= ~CPUID_EXT2_SYSCALL; 7270 } 7271 break; 7272 case 0x80000002: 7273 case 0x80000003: 7274 case 0x80000004: 7275 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0]; 7276 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1]; 7277 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2]; 7278 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3]; 7279 break; 7280 case 0x80000005: 7281 /* cache info (L1 cache) */ 7282 if (cpu->cache_info_passthrough) { 7283 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 7284 break; 7285 } 7286 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | 7287 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES); 7288 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | 7289 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES); 7290 *ecx = encode_cache_cpuid80000005(env->cache_info_amd.l1d_cache); 7291 *edx = encode_cache_cpuid80000005(env->cache_info_amd.l1i_cache); 7292 break; 7293 case 0x80000006: 7294 /* cache info (L2 cache) */ 7295 if (cpu->cache_info_passthrough) { 7296 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 7297 break; 7298 } 7299 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | 7300 (L2_DTLB_2M_ENTRIES << 16) | 7301 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | 7302 (L2_ITLB_2M_ENTRIES); 7303 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | 7304 (L2_DTLB_4K_ENTRIES << 16) | 7305 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | 7306 (L2_ITLB_4K_ENTRIES); 7307 encode_cache_cpuid80000006(env->cache_info_amd.l2_cache, 7308 cpu->enable_l3_cache ? 7309 env->cache_info_amd.l3_cache : NULL, 7310 ecx, edx); 7311 break; 7312 case 0x80000007: 7313 *eax = 0; 7314 *ebx = env->features[FEAT_8000_0007_EBX]; 7315 *ecx = 0; 7316 *edx = env->features[FEAT_8000_0007_EDX]; 7317 break; 7318 case 0x80000008: 7319 /* virtual & phys address size in low 2 bytes. */ 7320 *eax = cpu->phys_bits; 7321 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 7322 /* 64 bit processor */ 7323 *eax |= (cpu_x86_virtual_addr_width(env) << 8); 7324 *eax |= (cpu->guest_phys_bits << 16); 7325 } 7326 *ebx = env->features[FEAT_8000_0008_EBX]; 7327 if (threads_per_pkg > 1) { 7328 /* 7329 * Bits 15:12 is "The number of bits in the initial 7330 * Core::X86::Apic::ApicId[ApicId] value that indicate 7331 * thread ID within a package". 7332 * Bits 7:0 is "The number of threads in the package is NC+1" 7333 */ 7334 *ecx = (apicid_pkg_offset(topo_info) << 12) | 7335 (threads_per_pkg - 1); 7336 } else { 7337 *ecx = 0; 7338 } 7339 *edx = 0; 7340 break; 7341 case 0x8000000A: 7342 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { 7343 *eax = 0x00000001; /* SVM Revision */ 7344 *ebx = 0x00000010; /* nr of ASIDs */ 7345 *ecx = 0; 7346 *edx = env->features[FEAT_SVM]; /* optional features */ 7347 } else { 7348 *eax = 0; 7349 *ebx = 0; 7350 *ecx = 0; 7351 *edx = 0; 7352 } 7353 break; 7354 case 0x8000001D: 7355 *eax = 0; 7356 if (cpu->cache_info_passthrough) { 7357 x86_cpu_get_cache_cpuid(index, count, eax, ebx, ecx, edx); 7358 break; 7359 } 7360 switch (count) { 7361 case 0: /* L1 dcache info */ 7362 encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache, 7363 topo_info, eax, ebx, ecx, edx); 7364 break; 7365 case 1: /* L1 icache info */ 7366 encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache, 7367 topo_info, eax, ebx, ecx, edx); 7368 break; 7369 case 2: /* L2 cache info */ 7370 encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache, 7371 topo_info, eax, ebx, ecx, edx); 7372 break; 7373 case 3: /* L3 cache info */ 7374 encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache, 7375 topo_info, eax, ebx, ecx, edx); 7376 break; 7377 default: /* end of info */ 7378 *eax = *ebx = *ecx = *edx = 0; 7379 break; 7380 } 7381 if (cpu->amd_topoext_features_only) { 7382 *edx &= CACHE_NO_INVD_SHARING | CACHE_INCLUSIVE; 7383 } 7384 break; 7385 case 0x8000001E: 7386 if (cpu->core_id <= 255) { 7387 encode_topo_cpuid8000001e(cpu, topo_info, eax, ebx, ecx, edx); 7388 } else { 7389 *eax = 0; 7390 *ebx = 0; 7391 *ecx = 0; 7392 *edx = 0; 7393 } 7394 break; 7395 case 0x80000022: 7396 *eax = *ebx = *ecx = *edx = 0; 7397 /* AMD Extended Performance Monitoring and Debug */ 7398 if (kvm_enabled() && cpu->enable_pmu && 7399 (env->features[FEAT_8000_0022_EAX] & CPUID_8000_0022_EAX_PERFMON_V2)) { 7400 *eax |= CPUID_8000_0022_EAX_PERFMON_V2; 7401 *ebx |= kvm_arch_get_supported_cpuid(cs->kvm_state, index, count, 7402 R_EBX) & 0xf; 7403 } 7404 break; 7405 case 0xC0000000: 7406 *eax = env->cpuid_xlevel2; 7407 *ebx = 0; 7408 *ecx = 0; 7409 *edx = 0; 7410 break; 7411 case 0xC0000001: 7412 /* Support for VIA CPU's CPUID instruction */ 7413 *eax = env->cpuid_version; 7414 *ebx = 0; 7415 *ecx = 0; 7416 *edx = env->features[FEAT_C000_0001_EDX]; 7417 break; 7418 case 0xC0000002: 7419 case 0xC0000003: 7420 case 0xC0000004: 7421 /* Reserved for the future, and now filled with zero */ 7422 *eax = 0; 7423 *ebx = 0; 7424 *ecx = 0; 7425 *edx = 0; 7426 break; 7427 case 0x8000001F: 7428 *eax = *ebx = *ecx = *edx = 0; 7429 if (sev_enabled()) { 7430 *eax = 0x2; 7431 *eax |= sev_es_enabled() ? 0x8 : 0; 7432 *eax |= sev_snp_enabled() ? 0x10 : 0; 7433 *ebx = sev_get_cbit_position() & 0x3f; /* EBX[5:0] */ 7434 *ebx |= (sev_get_reduced_phys_bits() & 0x3f) << 6; /* EBX[11:6] */ 7435 } 7436 break; 7437 case 0x80000021: 7438 *eax = *ebx = *ecx = *edx = 0; 7439 *eax = env->features[FEAT_8000_0021_EAX]; 7440 *ebx = env->features[FEAT_8000_0021_EBX]; 7441 break; 7442 default: 7443 /* reserved values: zero */ 7444 *eax = 0; 7445 *ebx = 0; 7446 *ecx = 0; 7447 *edx = 0; 7448 break; 7449 } 7450 } 7451 7452 static void x86_cpu_set_sgxlepubkeyhash(CPUX86State *env) 7453 { 7454 #ifndef CONFIG_USER_ONLY 7455 /* Those default values are defined in Skylake HW */ 7456 env->msr_ia32_sgxlepubkeyhash[0] = 0xa6053e051270b7acULL; 7457 env->msr_ia32_sgxlepubkeyhash[1] = 0x6cfbe8ba8b3b413dULL; 7458 env->msr_ia32_sgxlepubkeyhash[2] = 0xc4916d99f2b3735dULL; 7459 env->msr_ia32_sgxlepubkeyhash[3] = 0xd4f8c05909f9bb3bULL; 7460 #endif 7461 } 7462 7463 static bool cpuid_has_xsave_feature(CPUX86State *env, const ExtSaveArea *esa) 7464 { 7465 if (!esa->size) { 7466 return false; 7467 } 7468 7469 if (env->features[esa->feature] & esa->bits) { 7470 return true; 7471 } 7472 if (esa->feature == FEAT_7_0_EBX && esa->bits == CPUID_7_0_EBX_AVX512F 7473 && (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10)) { 7474 return true; 7475 } 7476 7477 return false; 7478 } 7479 7480 static void x86_cpu_reset_hold(Object *obj, ResetType type) 7481 { 7482 CPUState *cs = CPU(obj); 7483 X86CPU *cpu = X86_CPU(cs); 7484 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj); 7485 CPUX86State *env = &cpu->env; 7486 target_ulong cr4; 7487 uint64_t xcr0; 7488 int i; 7489 7490 if (xcc->parent_phases.hold) { 7491 xcc->parent_phases.hold(obj, type); 7492 } 7493 7494 memset(env, 0, offsetof(CPUX86State, end_reset_fields)); 7495 7496 if (tcg_enabled()) { 7497 cpu_init_fp_statuses(env); 7498 } 7499 7500 env->old_exception = -1; 7501 7502 /* init to reset state */ 7503 env->int_ctl = 0; 7504 env->hflags2 |= HF2_GIF_MASK; 7505 env->hflags2 |= HF2_VGIF_MASK; 7506 env->hflags &= ~HF_GUEST_MASK; 7507 7508 cpu_x86_update_cr0(env, 0x60000010); 7509 env->a20_mask = ~0x0; 7510 env->smbase = 0x30000; 7511 env->msr_smi_count = 0; 7512 7513 env->idt.limit = 0xffff; 7514 env->gdt.limit = 0xffff; 7515 env->ldt.limit = 0xffff; 7516 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT); 7517 env->tr.limit = 0xffff; 7518 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT); 7519 7520 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff, 7521 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK | 7522 DESC_R_MASK | DESC_A_MASK); 7523 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff, 7524 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7525 DESC_A_MASK); 7526 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff, 7527 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7528 DESC_A_MASK); 7529 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff, 7530 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7531 DESC_A_MASK); 7532 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff, 7533 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7534 DESC_A_MASK); 7535 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff, 7536 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7537 DESC_A_MASK); 7538 7539 env->eip = 0xfff0; 7540 env->regs[R_EDX] = env->cpuid_version; 7541 7542 env->eflags = 0x2; 7543 7544 /* FPU init */ 7545 for (i = 0; i < 8; i++) { 7546 env->fptags[i] = 1; 7547 } 7548 cpu_set_fpuc(env, 0x37f); 7549 7550 env->mxcsr = 0x1f80; 7551 /* All units are in INIT state. */ 7552 env->xstate_bv = 0; 7553 7554 env->pat = 0x0007040600070406ULL; 7555 7556 if (kvm_enabled()) { 7557 /* 7558 * KVM handles TSC = 0 specially and thinks we are hot-plugging 7559 * a new CPU, use 1 instead to force a reset. 7560 */ 7561 if (env->tsc != 0) { 7562 env->tsc = 1; 7563 } 7564 } else { 7565 env->tsc = 0; 7566 } 7567 7568 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT; 7569 if (env->features[FEAT_1_ECX] & CPUID_EXT_MONITOR) { 7570 env->msr_ia32_misc_enable |= MSR_IA32_MISC_ENABLE_MWAIT; 7571 } 7572 7573 memset(env->dr, 0, sizeof(env->dr)); 7574 env->dr[6] = DR6_FIXED_1; 7575 env->dr[7] = DR7_FIXED_1; 7576 cpu_breakpoint_remove_all(cs, BP_CPU); 7577 cpu_watchpoint_remove_all(cs, BP_CPU); 7578 7579 cr4 = 0; 7580 xcr0 = XSTATE_FP_MASK; 7581 7582 #ifdef CONFIG_USER_ONLY 7583 /* Enable all the features for user-mode. */ 7584 if (env->features[FEAT_1_EDX] & CPUID_SSE) { 7585 xcr0 |= XSTATE_SSE_MASK; 7586 } 7587 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 7588 const ExtSaveArea *esa = &x86_ext_save_areas[i]; 7589 if (!((1 << i) & CPUID_XSTATE_XCR0_MASK)) { 7590 continue; 7591 } 7592 if (cpuid_has_xsave_feature(env, esa)) { 7593 xcr0 |= 1ull << i; 7594 } 7595 } 7596 7597 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) { 7598 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK; 7599 } 7600 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) { 7601 cr4 |= CR4_FSGSBASE_MASK; 7602 } 7603 #endif 7604 7605 env->xcr0 = xcr0; 7606 cpu_x86_update_cr4(env, cr4); 7607 7608 /* 7609 * SDM 11.11.5 requires: 7610 * - IA32_MTRR_DEF_TYPE MSR.E = 0 7611 * - IA32_MTRR_PHYSMASKn.V = 0 7612 * All other bits are undefined. For simplification, zero it all. 7613 */ 7614 env->mtrr_deftype = 0; 7615 memset(env->mtrr_var, 0, sizeof(env->mtrr_var)); 7616 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed)); 7617 7618 env->interrupt_injected = -1; 7619 env->exception_nr = -1; 7620 env->exception_pending = 0; 7621 env->exception_injected = 0; 7622 env->exception_has_payload = false; 7623 env->exception_payload = 0; 7624 env->nmi_injected = false; 7625 env->triple_fault_pending = false; 7626 #if !defined(CONFIG_USER_ONLY) 7627 /* We hard-wire the BSP to the first CPU. */ 7628 apic_designate_bsp(cpu->apic_state, cs->cpu_index == 0); 7629 7630 cs->halted = !cpu_is_bsp(cpu); 7631 7632 if (kvm_enabled()) { 7633 kvm_arch_reset_vcpu(cpu); 7634 } 7635 7636 x86_cpu_set_sgxlepubkeyhash(env); 7637 7638 env->amd_tsc_scale_msr = MSR_AMD64_TSC_RATIO_DEFAULT; 7639 7640 #endif 7641 } 7642 7643 void x86_cpu_after_reset(X86CPU *cpu) 7644 { 7645 #ifndef CONFIG_USER_ONLY 7646 if (kvm_enabled()) { 7647 kvm_arch_after_reset_vcpu(cpu); 7648 } 7649 7650 if (cpu->apic_state) { 7651 device_cold_reset(cpu->apic_state); 7652 } 7653 #endif 7654 } 7655 7656 static void mce_init(X86CPU *cpu) 7657 { 7658 CPUX86State *cenv = &cpu->env; 7659 unsigned int bank; 7660 7661 if (((cenv->cpuid_version >> 8) & 0xf) >= 6 7662 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) == 7663 (CPUID_MCE | CPUID_MCA)) { 7664 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF | 7665 (cpu->enable_lmce ? MCG_LMCE_P : 0); 7666 cenv->mcg_ctl = ~(uint64_t)0; 7667 for (bank = 0; bank < MCE_BANKS_DEF; bank++) { 7668 cenv->mce_banks[bank * 4] = ~(uint64_t)0; 7669 } 7670 } 7671 } 7672 7673 static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value) 7674 { 7675 if (*min < value) { 7676 *min = value; 7677 } 7678 } 7679 7680 /* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */ 7681 static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w) 7682 { 7683 CPUX86State *env = &cpu->env; 7684 FeatureWordInfo *fi = &feature_word_info[w]; 7685 uint32_t eax = fi->cpuid.eax; 7686 uint32_t region = eax & 0xF0000000; 7687 7688 assert(feature_word_info[w].type == CPUID_FEATURE_WORD); 7689 if (!env->features[w]) { 7690 return; 7691 } 7692 7693 switch (region) { 7694 case 0x00000000: 7695 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax); 7696 break; 7697 case 0x80000000: 7698 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax); 7699 break; 7700 case 0xC0000000: 7701 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax); 7702 break; 7703 } 7704 7705 if (eax == 7) { 7706 x86_cpu_adjust_level(cpu, &env->cpuid_min_level_func7, 7707 fi->cpuid.ecx); 7708 } 7709 } 7710 7711 /* Calculate XSAVE components based on the configured CPU feature flags */ 7712 static void x86_cpu_enable_xsave_components(X86CPU *cpu) 7713 { 7714 CPUX86State *env = &cpu->env; 7715 int i; 7716 uint64_t mask; 7717 static bool request_perm; 7718 7719 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { 7720 env->features[FEAT_XSAVE_XCR0_LO] = 0; 7721 env->features[FEAT_XSAVE_XCR0_HI] = 0; 7722 env->features[FEAT_XSAVE_XSS_LO] = 0; 7723 env->features[FEAT_XSAVE_XSS_HI] = 0; 7724 return; 7725 } 7726 7727 mask = 0; 7728 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 7729 const ExtSaveArea *esa = &x86_ext_save_areas[i]; 7730 if (cpuid_has_xsave_feature(env, esa)) { 7731 mask |= (1ULL << i); 7732 } 7733 } 7734 7735 /* Only request permission for first vcpu */ 7736 if (kvm_enabled() && !request_perm) { 7737 kvm_request_xsave_components(cpu, mask); 7738 request_perm = true; 7739 } 7740 7741 env->features[FEAT_XSAVE_XCR0_LO] = mask & CPUID_XSTATE_XCR0_MASK; 7742 env->features[FEAT_XSAVE_XCR0_HI] = (mask & CPUID_XSTATE_XCR0_MASK) >> 32; 7743 env->features[FEAT_XSAVE_XSS_LO] = mask & CPUID_XSTATE_XSS_MASK; 7744 env->features[FEAT_XSAVE_XSS_HI] = (mask & CPUID_XSTATE_XSS_MASK) >> 32; 7745 } 7746 7747 /***** Steps involved on loading and filtering CPUID data 7748 * 7749 * When initializing and realizing a CPU object, the steps 7750 * involved in setting up CPUID data are: 7751 * 7752 * 1) Loading CPU model definition (X86CPUDefinition). This is 7753 * implemented by x86_cpu_load_model() and should be completely 7754 * transparent, as it is done automatically by instance_init. 7755 * No code should need to look at X86CPUDefinition structs 7756 * outside instance_init. 7757 * 7758 * 2) CPU expansion. This is done by realize before CPUID 7759 * filtering, and will make sure host/accelerator data is 7760 * loaded for CPU models that depend on host capabilities 7761 * (e.g. "host"). Done by x86_cpu_expand_features(). 7762 * 7763 * 3) CPUID filtering. This initializes extra data related to 7764 * CPUID, and checks if the host supports all capabilities 7765 * required by the CPU. Runnability of a CPU model is 7766 * determined at this step. Done by x86_cpu_filter_features(). 7767 * 7768 * Some operations don't require all steps to be performed. 7769 * More precisely: 7770 * 7771 * - CPU instance creation (instance_init) will run only CPU 7772 * model loading. CPU expansion can't run at instance_init-time 7773 * because host/accelerator data may be not available yet. 7774 * - CPU realization will perform both CPU model expansion and CPUID 7775 * filtering, and return an error in case one of them fails. 7776 * - query-cpu-definitions needs to run all 3 steps. It needs 7777 * to run CPUID filtering, as the 'unavailable-features' 7778 * field is set based on the filtering results. 7779 * - The query-cpu-model-expansion QMP command only needs to run 7780 * CPU model loading and CPU expansion. It should not filter 7781 * any CPUID data based on host capabilities. 7782 */ 7783 7784 /* Expand CPU configuration data, based on configured features 7785 * and host/accelerator capabilities when appropriate. 7786 */ 7787 void x86_cpu_expand_features(X86CPU *cpu, Error **errp) 7788 { 7789 CPUX86State *env = &cpu->env; 7790 FeatureWord w; 7791 int i; 7792 GList *l; 7793 7794 for (l = plus_features; l; l = l->next) { 7795 const char *prop = l->data; 7796 if (!object_property_set_bool(OBJECT(cpu), prop, true, errp)) { 7797 return; 7798 } 7799 } 7800 7801 for (l = minus_features; l; l = l->next) { 7802 const char *prop = l->data; 7803 if (!object_property_set_bool(OBJECT(cpu), prop, false, errp)) { 7804 return; 7805 } 7806 } 7807 7808 /*TODO: Now cpu->max_features doesn't overwrite features 7809 * set using QOM properties, and we can convert 7810 * plus_features & minus_features to global properties 7811 * inside x86_cpu_parse_featurestr() too. 7812 */ 7813 if (cpu->max_features) { 7814 for (w = 0; w < FEATURE_WORDS; w++) { 7815 /* Override only features that weren't set explicitly 7816 * by the user. 7817 */ 7818 env->features[w] |= 7819 x86_cpu_get_supported_feature_word(cpu, w) & 7820 ~env->user_features[w] & 7821 ~feature_word_info[w].no_autoenable_flags; 7822 } 7823 7824 if ((env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) && !env->avx10_version) { 7825 uint32_t eax, ebx, ecx, edx; 7826 x86_cpu_get_supported_cpuid(0x24, 0, &eax, &ebx, &ecx, &edx); 7827 env->avx10_version = ebx & 0xff; 7828 } 7829 } 7830 7831 if (x86_threads_per_pkg(&env->topo_info) > 1) { 7832 env->features[FEAT_1_EDX] |= CPUID_HT; 7833 7834 /* 7835 * The Linux kernel checks for the CMPLegacy bit and 7836 * discards multiple thread information if it is set. 7837 * So don't set it here for Intel (and other processors 7838 * following Intel's behavior) to make Linux guests happy. 7839 */ 7840 if (!IS_INTEL_CPU(env) && !IS_ZHAOXIN_CPU(env)) { 7841 env->features[FEAT_8000_0001_ECX] |= CPUID_EXT3_CMP_LEG; 7842 } 7843 } 7844 7845 for (i = 0; i < ARRAY_SIZE(feature_dependencies); i++) { 7846 FeatureDep *d = &feature_dependencies[i]; 7847 if (!(env->features[d->from.index] & d->from.mask)) { 7848 uint64_t unavailable_features = env->features[d->to.index] & d->to.mask; 7849 7850 /* Not an error unless the dependent feature was added explicitly. */ 7851 mark_unavailable_features(cpu, d->to.index, 7852 unavailable_features & env->user_features[d->to.index], 7853 "This feature depends on other features that were not requested"); 7854 7855 env->features[d->to.index] &= ~unavailable_features; 7856 } 7857 } 7858 7859 if (!kvm_enabled() || !cpu->expose_kvm) { 7860 env->features[FEAT_KVM] = 0; 7861 } 7862 7863 x86_cpu_enable_xsave_components(cpu); 7864 7865 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */ 7866 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX); 7867 if (cpu->full_cpuid_auto_level) { 7868 x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX); 7869 x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX); 7870 x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX); 7871 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX); 7872 x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EAX); 7873 x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EDX); 7874 x86_cpu_adjust_feat_level(cpu, FEAT_7_2_EDX); 7875 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX); 7876 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX); 7877 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX); 7878 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0008_EBX); 7879 x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX); 7880 x86_cpu_adjust_feat_level(cpu, FEAT_SVM); 7881 x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE); 7882 7883 /* Intel Processor Trace requires CPUID[0x14] */ 7884 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT)) { 7885 if (cpu->intel_pt_auto_level) { 7886 x86_cpu_adjust_level(cpu, &cpu->env.cpuid_min_level, 0x14); 7887 } else if (cpu->env.cpuid_min_level < 0x14) { 7888 mark_unavailable_features(cpu, FEAT_7_0_EBX, 7889 CPUID_7_0_EBX_INTEL_PT, 7890 "Intel PT need CPUID leaf 0x14, please set by \"-cpu ...,intel-pt=on,min-level=0x14\""); 7891 } 7892 } 7893 7894 /* 7895 * Intel CPU topology with multi-dies support requires CPUID[0x1F]. 7896 * For AMD Rome/Milan, cpuid level is 0x10, and guest OS should detect 7897 * extended toplogy by leaf 0xB. Only adjust it for Intel CPU, unless 7898 * cpu->vendor_cpuid_only has been unset for compatibility with older 7899 * machine types. 7900 */ 7901 if (x86_has_extended_topo(env->avail_cpu_topo) && 7902 (IS_INTEL_CPU(env) || !cpu->vendor_cpuid_only)) { 7903 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x1F); 7904 } 7905 7906 /* Advanced Vector Extensions 10 (AVX10) requires CPUID[0x24] */ 7907 if (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) { 7908 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x24); 7909 } 7910 7911 /* SVM requires CPUID[0x8000000A] */ 7912 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { 7913 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A); 7914 } 7915 7916 /* SEV requires CPUID[0x8000001F] */ 7917 if (sev_enabled()) { 7918 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F); 7919 } 7920 7921 if (env->features[FEAT_8000_0021_EAX]) { 7922 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x80000021); 7923 } 7924 7925 /* SGX requires CPUID[0x12] for EPC enumeration */ 7926 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX) { 7927 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x12); 7928 } 7929 } 7930 7931 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */ 7932 if (env->cpuid_level_func7 == UINT32_MAX) { 7933 env->cpuid_level_func7 = env->cpuid_min_level_func7; 7934 } 7935 if (env->cpuid_level == UINT32_MAX) { 7936 env->cpuid_level = env->cpuid_min_level; 7937 } 7938 if (env->cpuid_xlevel == UINT32_MAX) { 7939 env->cpuid_xlevel = env->cpuid_min_xlevel; 7940 } 7941 if (env->cpuid_xlevel2 == UINT32_MAX) { 7942 env->cpuid_xlevel2 = env->cpuid_min_xlevel2; 7943 } 7944 7945 if (kvm_enabled() && !kvm_hyperv_expand_features(cpu, errp)) { 7946 return; 7947 } 7948 } 7949 7950 /* 7951 * Finishes initialization of CPUID data, filters CPU feature 7952 * words based on host availability of each feature. 7953 * 7954 * Returns: true if any flag is not supported by the host, false otherwise. 7955 */ 7956 static bool x86_cpu_filter_features(X86CPU *cpu, bool verbose) 7957 { 7958 CPUX86State *env = &cpu->env; 7959 FeatureWord w; 7960 const char *prefix = NULL; 7961 bool have_filtered_features; 7962 7963 uint32_t eax_0, ebx_0, ecx_0, edx_0; 7964 uint32_t eax_1, ebx_1, ecx_1, edx_1; 7965 7966 if (verbose) { 7967 prefix = accel_uses_host_cpuid() 7968 ? "host doesn't support requested feature" 7969 : "TCG doesn't support requested feature"; 7970 } 7971 7972 for (w = 0; w < FEATURE_WORDS; w++) { 7973 uint64_t host_feat = 7974 x86_cpu_get_supported_feature_word(NULL, w); 7975 uint64_t requested_features = env->features[w]; 7976 uint64_t unavailable_features = requested_features & ~host_feat; 7977 mark_unavailable_features(cpu, w, unavailable_features, prefix); 7978 } 7979 7980 /* 7981 * Check that KVM actually allows the processor tracing features that 7982 * are advertised by cpu_x86_cpuid(). Keep these two in sync. 7983 */ 7984 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) && 7985 kvm_enabled()) { 7986 x86_cpu_get_supported_cpuid(0x14, 0, 7987 &eax_0, &ebx_0, &ecx_0, &edx_0); 7988 x86_cpu_get_supported_cpuid(0x14, 1, 7989 &eax_1, &ebx_1, &ecx_1, &edx_1); 7990 7991 if (!eax_0 || 7992 ((ebx_0 & INTEL_PT_MINIMAL_EBX) != INTEL_PT_MINIMAL_EBX) || 7993 ((ecx_0 & INTEL_PT_MINIMAL_ECX) != INTEL_PT_MINIMAL_ECX) || 7994 ((eax_1 & INTEL_PT_MTC_BITMAP) != INTEL_PT_MTC_BITMAP) || 7995 ((eax_1 & INTEL_PT_ADDR_RANGES_NUM_MASK) < 7996 INTEL_PT_ADDR_RANGES_NUM) || 7997 ((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) != 7998 (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) || 7999 ((ecx_0 & CPUID_14_0_ECX_LIP) != 8000 (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP))) { 8001 /* 8002 * Processor Trace capabilities aren't configurable, so if the 8003 * host can't emulate the capabilities we report on 8004 * cpu_x86_cpuid(), intel-pt can't be enabled on the current host. 8005 */ 8006 mark_unavailable_features(cpu, FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT, prefix); 8007 } 8008 } 8009 8010 have_filtered_features = x86_cpu_have_filtered_features(cpu); 8011 8012 if (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) { 8013 x86_cpu_get_supported_cpuid(0x24, 0, 8014 &eax_0, &ebx_0, &ecx_0, &edx_0); 8015 uint8_t version = ebx_0 & 0xff; 8016 8017 if (version < env->avx10_version) { 8018 if (prefix) { 8019 warn_report("%s: avx10.%d. Adjust to avx10.%d", 8020 prefix, env->avx10_version, version); 8021 } 8022 env->avx10_version = version; 8023 have_filtered_features = true; 8024 } 8025 } else if (env->avx10_version) { 8026 if (prefix) { 8027 warn_report("%s: avx10.%d.", prefix, env->avx10_version); 8028 } 8029 have_filtered_features = true; 8030 } 8031 8032 return have_filtered_features; 8033 } 8034 8035 static void x86_cpu_hyperv_realize(X86CPU *cpu) 8036 { 8037 size_t len; 8038 8039 /* Hyper-V vendor id */ 8040 if (!cpu->hyperv_vendor) { 8041 object_property_set_str(OBJECT(cpu), "hv-vendor-id", "Microsoft Hv", 8042 &error_abort); 8043 } 8044 len = strlen(cpu->hyperv_vendor); 8045 if (len > 12) { 8046 warn_report("hv-vendor-id truncated to 12 characters"); 8047 len = 12; 8048 } 8049 memset(cpu->hyperv_vendor_id, 0, 12); 8050 memcpy(cpu->hyperv_vendor_id, cpu->hyperv_vendor, len); 8051 8052 /* 'Hv#1' interface identification*/ 8053 cpu->hyperv_interface_id[0] = 0x31237648; 8054 cpu->hyperv_interface_id[1] = 0; 8055 cpu->hyperv_interface_id[2] = 0; 8056 cpu->hyperv_interface_id[3] = 0; 8057 8058 /* Hypervisor implementation limits */ 8059 cpu->hyperv_limits[0] = 64; 8060 cpu->hyperv_limits[1] = 0; 8061 cpu->hyperv_limits[2] = 0; 8062 } 8063 8064 #ifndef CONFIG_USER_ONLY 8065 static bool x86_cpu_update_smp_cache_topo(MachineState *ms, X86CPU *cpu, 8066 Error **errp) 8067 { 8068 CPUX86State *env = &cpu->env; 8069 CpuTopologyLevel level; 8070 8071 level = machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1D); 8072 if (level != CPU_TOPOLOGY_LEVEL_DEFAULT) { 8073 env->cache_info_cpuid4.l1d_cache->share_level = level; 8074 env->cache_info_amd.l1d_cache->share_level = level; 8075 } else { 8076 machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1D, 8077 env->cache_info_cpuid4.l1d_cache->share_level); 8078 machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1D, 8079 env->cache_info_amd.l1d_cache->share_level); 8080 } 8081 8082 level = machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1I); 8083 if (level != CPU_TOPOLOGY_LEVEL_DEFAULT) { 8084 env->cache_info_cpuid4.l1i_cache->share_level = level; 8085 env->cache_info_amd.l1i_cache->share_level = level; 8086 } else { 8087 machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1I, 8088 env->cache_info_cpuid4.l1i_cache->share_level); 8089 machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1I, 8090 env->cache_info_amd.l1i_cache->share_level); 8091 } 8092 8093 level = machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L2); 8094 if (level != CPU_TOPOLOGY_LEVEL_DEFAULT) { 8095 env->cache_info_cpuid4.l2_cache->share_level = level; 8096 env->cache_info_amd.l2_cache->share_level = level; 8097 } else { 8098 machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L2, 8099 env->cache_info_cpuid4.l2_cache->share_level); 8100 machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L2, 8101 env->cache_info_amd.l2_cache->share_level); 8102 } 8103 8104 level = machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L3); 8105 if (level != CPU_TOPOLOGY_LEVEL_DEFAULT) { 8106 env->cache_info_cpuid4.l3_cache->share_level = level; 8107 env->cache_info_amd.l3_cache->share_level = level; 8108 } else { 8109 machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L3, 8110 env->cache_info_cpuid4.l3_cache->share_level); 8111 machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L3, 8112 env->cache_info_amd.l3_cache->share_level); 8113 } 8114 8115 if (!machine_check_smp_cache(ms, errp)) { 8116 return false; 8117 } 8118 return true; 8119 } 8120 #endif 8121 8122 static void x86_cpu_realizefn(DeviceState *dev, Error **errp) 8123 { 8124 CPUState *cs = CPU(dev); 8125 X86CPU *cpu = X86_CPU(dev); 8126 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev); 8127 CPUX86State *env = &cpu->env; 8128 Error *local_err = NULL; 8129 unsigned requested_lbr_fmt; 8130 8131 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) 8132 /* Use pc-relative instructions in system-mode */ 8133 tcg_cflags_set(cs, CF_PCREL); 8134 #endif 8135 8136 if (cpu->apic_id == UNASSIGNED_APIC_ID) { 8137 error_setg(errp, "apic-id property was not initialized properly"); 8138 return; 8139 } 8140 8141 /* 8142 * Process Hyper-V enlightenments. 8143 * Note: this currently has to happen before the expansion of CPU features. 8144 */ 8145 x86_cpu_hyperv_realize(cpu); 8146 8147 x86_cpu_expand_features(cpu, &local_err); 8148 if (local_err) { 8149 goto out; 8150 } 8151 8152 /* 8153 * Override env->features[FEAT_PERF_CAPABILITIES].LBR_FMT 8154 * with user-provided setting. 8155 */ 8156 if (cpu->lbr_fmt != ~PERF_CAP_LBR_FMT) { 8157 if ((cpu->lbr_fmt & PERF_CAP_LBR_FMT) != cpu->lbr_fmt) { 8158 error_setg(errp, "invalid lbr-fmt"); 8159 return; 8160 } 8161 env->features[FEAT_PERF_CAPABILITIES] &= ~PERF_CAP_LBR_FMT; 8162 env->features[FEAT_PERF_CAPABILITIES] |= cpu->lbr_fmt; 8163 } 8164 8165 /* 8166 * vPMU LBR is supported when 1) KVM is enabled 2) Option pmu=on and 8167 * 3)vPMU LBR format matches that of host setting. 8168 */ 8169 requested_lbr_fmt = 8170 env->features[FEAT_PERF_CAPABILITIES] & PERF_CAP_LBR_FMT; 8171 if (requested_lbr_fmt && kvm_enabled()) { 8172 uint64_t host_perf_cap = 8173 x86_cpu_get_supported_feature_word(NULL, FEAT_PERF_CAPABILITIES); 8174 unsigned host_lbr_fmt = host_perf_cap & PERF_CAP_LBR_FMT; 8175 8176 if (!cpu->enable_pmu) { 8177 error_setg(errp, "vPMU: LBR is unsupported without pmu=on"); 8178 return; 8179 } 8180 if (requested_lbr_fmt != host_lbr_fmt) { 8181 error_setg(errp, "vPMU: the lbr-fmt value (0x%x) does not match " 8182 "the host value (0x%x).", 8183 requested_lbr_fmt, host_lbr_fmt); 8184 return; 8185 } 8186 } 8187 8188 if (x86_cpu_filter_features(cpu, cpu->check_cpuid || cpu->enforce_cpuid)) { 8189 if (cpu->enforce_cpuid) { 8190 error_setg(&local_err, 8191 accel_uses_host_cpuid() ? 8192 "Host doesn't support requested features" : 8193 "TCG doesn't support requested features"); 8194 goto out; 8195 } 8196 } 8197 8198 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on 8199 * CPUID[1].EDX. 8200 */ 8201 if (IS_AMD_CPU(env)) { 8202 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES; 8203 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX] 8204 & CPUID_EXT2_AMD_ALIASES); 8205 } 8206 8207 x86_cpu_set_sgxlepubkeyhash(env); 8208 8209 /* 8210 * note: the call to the framework needs to happen after feature expansion, 8211 * but before the checks/modifications to ucode_rev, mwait, phys_bits. 8212 * These may be set by the accel-specific code, 8213 * and the results are subsequently checked / assumed in this function. 8214 */ 8215 cpu_exec_realizefn(cs, &local_err); 8216 if (local_err != NULL) { 8217 error_propagate(errp, local_err); 8218 return; 8219 } 8220 8221 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) { 8222 g_autofree char *name = x86_cpu_class_get_model_name(xcc); 8223 error_setg(&local_err, "CPU model '%s' requires KVM or HVF", name); 8224 goto out; 8225 } 8226 8227 if (cpu->guest_phys_bits == -1) { 8228 /* 8229 * If it was not set by the user, or by the accelerator via 8230 * cpu_exec_realizefn, clear. 8231 */ 8232 cpu->guest_phys_bits = 0; 8233 } 8234 8235 if (cpu->ucode_rev == 0) { 8236 /* 8237 * The default is the same as KVM's. Note that this check 8238 * needs to happen after the evenual setting of ucode_rev in 8239 * accel-specific code in cpu_exec_realizefn. 8240 */ 8241 if (IS_AMD_CPU(env)) { 8242 cpu->ucode_rev = 0x01000065; 8243 } else { 8244 cpu->ucode_rev = 0x100000000ULL; 8245 } 8246 } 8247 8248 /* 8249 * mwait extended info: needed for Core compatibility 8250 * We always wake on interrupt even if host does not have the capability. 8251 * 8252 * requires the accel-specific code in cpu_exec_realizefn to 8253 * have already acquired the CPUID data into cpu->mwait. 8254 */ 8255 cpu->mwait.ecx |= CPUID_MWAIT_EMX | CPUID_MWAIT_IBE; 8256 8257 /* 8258 * Most Intel and certain AMD CPUs support hyperthreading. Even though QEMU 8259 * fixes this issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX 8260 * based on inputs (sockets,cores,threads), it is still better to give 8261 * users a warning. 8262 */ 8263 if (IS_AMD_CPU(env) && 8264 !(env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) && 8265 env->topo_info.threads_per_core > 1) { 8266 warn_report_once("This family of AMD CPU doesn't support " 8267 "hyperthreading(%d). Please configure -smp " 8268 "options properly or try enabling topoext " 8269 "feature.", env->topo_info.threads_per_core); 8270 } 8271 8272 /* For 64bit systems think about the number of physical bits to present. 8273 * ideally this should be the same as the host; anything other than matching 8274 * the host can cause incorrect guest behaviour. 8275 * QEMU used to pick the magic value of 40 bits that corresponds to 8276 * consumer AMD devices but nothing else. 8277 * 8278 * Note that this code assumes features expansion has already been done 8279 * (as it checks for CPUID_EXT2_LM), and also assumes that potential 8280 * phys_bits adjustments to match the host have been already done in 8281 * accel-specific code in cpu_exec_realizefn. 8282 */ 8283 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 8284 if (cpu->phys_bits && 8285 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS || 8286 cpu->phys_bits < 32)) { 8287 error_setg(errp, "phys-bits should be between 32 and %u " 8288 " (but is %u)", 8289 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits); 8290 return; 8291 } 8292 /* 8293 * 0 means it was not explicitly set by the user (or by machine 8294 * compat_props or by the host code in host-cpu.c). 8295 * In this case, the default is the value used by TCG (40). 8296 */ 8297 if (cpu->phys_bits == 0) { 8298 cpu->phys_bits = TCG_PHYS_ADDR_BITS; 8299 } 8300 if (cpu->guest_phys_bits && 8301 (cpu->guest_phys_bits > cpu->phys_bits || 8302 cpu->guest_phys_bits < 32)) { 8303 error_setg(errp, "guest-phys-bits should be between 32 and %u " 8304 " (but is %u)", 8305 cpu->phys_bits, cpu->guest_phys_bits); 8306 return; 8307 } 8308 } else { 8309 /* For 32 bit systems don't use the user set value, but keep 8310 * phys_bits consistent with what we tell the guest. 8311 */ 8312 if (cpu->phys_bits != 0) { 8313 error_setg(errp, "phys-bits is not user-configurable in 32 bit"); 8314 return; 8315 } 8316 if (cpu->guest_phys_bits != 0) { 8317 error_setg(errp, "guest-phys-bits is not user-configurable in 32 bit"); 8318 return; 8319 } 8320 8321 if (env->features[FEAT_1_EDX] & (CPUID_PSE36 | CPUID_PAE)) { 8322 cpu->phys_bits = 36; 8323 } else { 8324 cpu->phys_bits = 32; 8325 } 8326 } 8327 8328 /* Cache information initialization */ 8329 if (!cpu->legacy_cache) { 8330 const CPUCaches *cache_info = 8331 x86_cpu_get_versioned_cache_info(cpu, xcc->model); 8332 8333 if (!xcc->model || !cache_info) { 8334 g_autofree char *name = x86_cpu_class_get_model_name(xcc); 8335 error_setg(errp, 8336 "CPU model '%s' doesn't support legacy-cache=off", name); 8337 return; 8338 } 8339 env->cache_info_cpuid2 = env->cache_info_cpuid4 = env->cache_info_amd = 8340 *cache_info; 8341 } else { 8342 /* Build legacy cache information */ 8343 env->cache_info_cpuid2.l1d_cache = &legacy_l1d_cache; 8344 env->cache_info_cpuid2.l1i_cache = &legacy_l1i_cache; 8345 env->cache_info_cpuid2.l2_cache = &legacy_l2_cache_cpuid2; 8346 env->cache_info_cpuid2.l3_cache = &legacy_l3_cache; 8347 8348 env->cache_info_cpuid4.l1d_cache = &legacy_l1d_cache; 8349 env->cache_info_cpuid4.l1i_cache = &legacy_l1i_cache; 8350 env->cache_info_cpuid4.l2_cache = &legacy_l2_cache; 8351 env->cache_info_cpuid4.l3_cache = &legacy_l3_cache; 8352 8353 env->cache_info_amd.l1d_cache = &legacy_l1d_cache_amd; 8354 env->cache_info_amd.l1i_cache = &legacy_l1i_cache_amd; 8355 env->cache_info_amd.l2_cache = &legacy_l2_cache_amd; 8356 env->cache_info_amd.l3_cache = &legacy_l3_cache; 8357 } 8358 8359 #ifndef CONFIG_USER_ONLY 8360 MachineState *ms = MACHINE(qdev_get_machine()); 8361 MachineClass *mc = MACHINE_GET_CLASS(ms); 8362 8363 if (mc->smp_props.has_caches) { 8364 if (!x86_cpu_update_smp_cache_topo(ms, cpu, errp)) { 8365 return; 8366 } 8367 } 8368 8369 qemu_register_reset(x86_cpu_machine_reset_cb, cpu); 8370 8371 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || ms->smp.cpus > 1) { 8372 x86_cpu_apic_create(cpu, &local_err); 8373 if (local_err != NULL) { 8374 goto out; 8375 } 8376 } 8377 #endif 8378 8379 mce_init(cpu); 8380 8381 x86_cpu_gdb_init(cs); 8382 qemu_init_vcpu(cs); 8383 8384 #ifndef CONFIG_USER_ONLY 8385 x86_cpu_apic_realize(cpu, &local_err); 8386 if (local_err != NULL) { 8387 goto out; 8388 } 8389 #endif /* !CONFIG_USER_ONLY */ 8390 cpu_reset(cs); 8391 8392 xcc->parent_realize(dev, &local_err); 8393 8394 out: 8395 if (local_err != NULL) { 8396 error_propagate(errp, local_err); 8397 return; 8398 } 8399 } 8400 8401 static void x86_cpu_unrealizefn(DeviceState *dev) 8402 { 8403 X86CPU *cpu = X86_CPU(dev); 8404 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev); 8405 8406 #ifndef CONFIG_USER_ONLY 8407 cpu_remove_sync(CPU(dev)); 8408 qemu_unregister_reset(x86_cpu_machine_reset_cb, dev); 8409 #endif 8410 8411 if (cpu->apic_state) { 8412 object_unparent(OBJECT(cpu->apic_state)); 8413 cpu->apic_state = NULL; 8414 } 8415 8416 xcc->parent_unrealize(dev); 8417 } 8418 8419 typedef struct BitProperty { 8420 FeatureWord w; 8421 uint64_t mask; 8422 } BitProperty; 8423 8424 static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name, 8425 void *opaque, Error **errp) 8426 { 8427 X86CPU *cpu = X86_CPU(obj); 8428 BitProperty *fp = opaque; 8429 uint64_t f = cpu->env.features[fp->w]; 8430 bool value = (f & fp->mask) == fp->mask; 8431 visit_type_bool(v, name, &value, errp); 8432 } 8433 8434 static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name, 8435 void *opaque, Error **errp) 8436 { 8437 DeviceState *dev = DEVICE(obj); 8438 X86CPU *cpu = X86_CPU(obj); 8439 BitProperty *fp = opaque; 8440 bool value; 8441 8442 if (dev->realized) { 8443 qdev_prop_set_after_realize(dev, name, errp); 8444 return; 8445 } 8446 8447 if (!visit_type_bool(v, name, &value, errp)) { 8448 return; 8449 } 8450 8451 if (value) { 8452 cpu->env.features[fp->w] |= fp->mask; 8453 } else { 8454 cpu->env.features[fp->w] &= ~fp->mask; 8455 } 8456 cpu->env.user_features[fp->w] |= fp->mask; 8457 } 8458 8459 /* Register a boolean property to get/set a single bit in a uint32_t field. 8460 * 8461 * The same property name can be registered multiple times to make it affect 8462 * multiple bits in the same FeatureWord. In that case, the getter will return 8463 * true only if all bits are set. 8464 */ 8465 static void x86_cpu_register_bit_prop(X86CPUClass *xcc, 8466 const char *prop_name, 8467 FeatureWord w, 8468 int bitnr) 8469 { 8470 ObjectClass *oc = OBJECT_CLASS(xcc); 8471 BitProperty *fp; 8472 ObjectProperty *op; 8473 uint64_t mask = (1ULL << bitnr); 8474 8475 op = object_class_property_find(oc, prop_name); 8476 if (op) { 8477 fp = op->opaque; 8478 assert(fp->w == w); 8479 fp->mask |= mask; 8480 } else { 8481 fp = g_new0(BitProperty, 1); 8482 fp->w = w; 8483 fp->mask = mask; 8484 object_class_property_add(oc, prop_name, "bool", 8485 x86_cpu_get_bit_prop, 8486 x86_cpu_set_bit_prop, 8487 NULL, fp); 8488 } 8489 } 8490 8491 static void x86_cpu_register_feature_bit_props(X86CPUClass *xcc, 8492 FeatureWord w, 8493 int bitnr) 8494 { 8495 FeatureWordInfo *fi = &feature_word_info[w]; 8496 const char *name = fi->feat_names[bitnr]; 8497 8498 if (!name) { 8499 return; 8500 } 8501 8502 /* Property names should use "-" instead of "_". 8503 * Old names containing underscores are registered as aliases 8504 * using object_property_add_alias() 8505 */ 8506 assert(!strchr(name, '_')); 8507 /* aliases don't use "|" delimiters anymore, they are registered 8508 * manually using object_property_add_alias() */ 8509 assert(!strchr(name, '|')); 8510 x86_cpu_register_bit_prop(xcc, name, w, bitnr); 8511 } 8512 8513 static void x86_cpu_post_initfn(Object *obj) 8514 { 8515 static bool first = true; 8516 uint64_t supported_xcr0; 8517 int i; 8518 8519 if (first) { 8520 first = false; 8521 8522 supported_xcr0 = 8523 ((uint64_t) x86_cpu_get_supported_feature_word(NULL, FEAT_XSAVE_XCR0_HI) << 32) | 8524 x86_cpu_get_supported_feature_word(NULL, FEAT_XSAVE_XCR0_LO); 8525 8526 for (i = XSTATE_SSE_BIT + 1; i < XSAVE_STATE_AREA_COUNT; i++) { 8527 ExtSaveArea *esa = &x86_ext_save_areas[i]; 8528 8529 if (!(supported_xcr0 & (1 << i))) { 8530 esa->size = 0; 8531 } 8532 } 8533 } 8534 8535 accel_cpu_instance_init(CPU(obj)); 8536 } 8537 8538 static void x86_cpu_init_default_topo(X86CPU *cpu) 8539 { 8540 CPUX86State *env = &cpu->env; 8541 8542 env->topo_info = (X86CPUTopoInfo) {1, 1, 1, 1}; 8543 8544 /* thread, core and socket levels are set by default. */ 8545 set_bit(CPU_TOPOLOGY_LEVEL_THREAD, env->avail_cpu_topo); 8546 set_bit(CPU_TOPOLOGY_LEVEL_CORE, env->avail_cpu_topo); 8547 set_bit(CPU_TOPOLOGY_LEVEL_SOCKET, env->avail_cpu_topo); 8548 } 8549 8550 static void x86_cpu_initfn(Object *obj) 8551 { 8552 X86CPU *cpu = X86_CPU(obj); 8553 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj); 8554 CPUX86State *env = &cpu->env; 8555 8556 x86_cpu_init_default_topo(cpu); 8557 8558 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo", 8559 x86_cpu_get_feature_words, 8560 NULL, NULL, (void *)env->features); 8561 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo", 8562 x86_cpu_get_feature_words, 8563 NULL, NULL, (void *)cpu->filtered_features); 8564 8565 object_property_add_alias(obj, "sse3", obj, "pni"); 8566 object_property_add_alias(obj, "pclmuldq", obj, "pclmulqdq"); 8567 object_property_add_alias(obj, "sse4-1", obj, "sse4.1"); 8568 object_property_add_alias(obj, "sse4-2", obj, "sse4.2"); 8569 object_property_add_alias(obj, "xd", obj, "nx"); 8570 object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt"); 8571 object_property_add_alias(obj, "i64", obj, "lm"); 8572 8573 object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl"); 8574 object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust"); 8575 object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt"); 8576 object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm"); 8577 object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy"); 8578 object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr"); 8579 object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core"); 8580 object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb"); 8581 object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay"); 8582 object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu"); 8583 object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf"); 8584 object_property_add_alias(obj, "kvm_asyncpf_int", obj, "kvm-asyncpf-int"); 8585 object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time"); 8586 object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi"); 8587 object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt"); 8588 object_property_add_alias(obj, "kvm_poll_control", obj, "kvm-poll-control"); 8589 object_property_add_alias(obj, "svm_lock", obj, "svm-lock"); 8590 object_property_add_alias(obj, "nrip_save", obj, "nrip-save"); 8591 object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale"); 8592 object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean"); 8593 object_property_add_alias(obj, "pause_filter", obj, "pause-filter"); 8594 object_property_add_alias(obj, "sse4_1", obj, "sse4.1"); 8595 object_property_add_alias(obj, "sse4_2", obj, "sse4.2"); 8596 8597 object_property_add_alias(obj, "hv-apicv", obj, "hv-avic"); 8598 cpu->lbr_fmt = ~PERF_CAP_LBR_FMT; 8599 object_property_add_alias(obj, "lbr_fmt", obj, "lbr-fmt"); 8600 8601 if (xcc->model) { 8602 x86_cpu_load_model(cpu, xcc->model); 8603 } 8604 } 8605 8606 static int64_t x86_cpu_get_arch_id(CPUState *cs) 8607 { 8608 X86CPU *cpu = X86_CPU(cs); 8609 8610 return cpu->apic_id; 8611 } 8612 8613 #if !defined(CONFIG_USER_ONLY) 8614 static bool x86_cpu_get_paging_enabled(const CPUState *cs) 8615 { 8616 X86CPU *cpu = X86_CPU(cs); 8617 8618 return cpu->env.cr[0] & CR0_PG_MASK; 8619 } 8620 #endif /* !CONFIG_USER_ONLY */ 8621 8622 static void x86_cpu_set_pc(CPUState *cs, vaddr value) 8623 { 8624 X86CPU *cpu = X86_CPU(cs); 8625 8626 cpu->env.eip = value; 8627 } 8628 8629 static vaddr x86_cpu_get_pc(CPUState *cs) 8630 { 8631 X86CPU *cpu = X86_CPU(cs); 8632 8633 /* Match cpu_get_tb_cpu_state. */ 8634 return cpu->env.eip + cpu->env.segs[R_CS].base; 8635 } 8636 8637 #if !defined(CONFIG_USER_ONLY) 8638 int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request) 8639 { 8640 X86CPU *cpu = X86_CPU(cs); 8641 CPUX86State *env = &cpu->env; 8642 8643 if (interrupt_request & CPU_INTERRUPT_POLL) { 8644 return CPU_INTERRUPT_POLL; 8645 } 8646 if (interrupt_request & CPU_INTERRUPT_SIPI) { 8647 return CPU_INTERRUPT_SIPI; 8648 } 8649 8650 if (env->hflags2 & HF2_GIF_MASK) { 8651 if ((interrupt_request & CPU_INTERRUPT_SMI) && 8652 !(env->hflags & HF_SMM_MASK)) { 8653 return CPU_INTERRUPT_SMI; 8654 } else if ((interrupt_request & CPU_INTERRUPT_NMI) && 8655 !(env->hflags2 & HF2_NMI_MASK)) { 8656 return CPU_INTERRUPT_NMI; 8657 } else if (interrupt_request & CPU_INTERRUPT_MCE) { 8658 return CPU_INTERRUPT_MCE; 8659 } else if ((interrupt_request & CPU_INTERRUPT_HARD) && 8660 (((env->hflags2 & HF2_VINTR_MASK) && 8661 (env->hflags2 & HF2_HIF_MASK)) || 8662 (!(env->hflags2 & HF2_VINTR_MASK) && 8663 (env->eflags & IF_MASK && 8664 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) { 8665 return CPU_INTERRUPT_HARD; 8666 } else if (env->hflags2 & HF2_VGIF_MASK) { 8667 if((interrupt_request & CPU_INTERRUPT_VIRQ) && 8668 (env->eflags & IF_MASK) && 8669 !(env->hflags & HF_INHIBIT_IRQ_MASK)) { 8670 return CPU_INTERRUPT_VIRQ; 8671 } 8672 } 8673 } 8674 8675 return 0; 8676 } 8677 8678 static bool x86_cpu_has_work(CPUState *cs) 8679 { 8680 return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0; 8681 } 8682 #endif /* !CONFIG_USER_ONLY */ 8683 8684 static void x86_disas_set_info(CPUState *cs, disassemble_info *info) 8685 { 8686 X86CPU *cpu = X86_CPU(cs); 8687 CPUX86State *env = &cpu->env; 8688 8689 info->endian = BFD_ENDIAN_LITTLE; 8690 info->mach = (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64 8691 : env->hflags & HF_CS32_MASK ? bfd_mach_i386_i386 8692 : bfd_mach_i386_i8086); 8693 8694 info->cap_arch = CS_ARCH_X86; 8695 info->cap_mode = (env->hflags & HF_CS64_MASK ? CS_MODE_64 8696 : env->hflags & HF_CS32_MASK ? CS_MODE_32 8697 : CS_MODE_16); 8698 info->cap_insn_unit = 1; 8699 info->cap_insn_split = 8; 8700 } 8701 8702 void x86_update_hflags(CPUX86State *env) 8703 { 8704 uint32_t hflags; 8705 #define HFLAG_COPY_MASK \ 8706 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \ 8707 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \ 8708 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \ 8709 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK) 8710 8711 hflags = env->hflags & HFLAG_COPY_MASK; 8712 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK; 8713 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT); 8714 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) & 8715 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK); 8716 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK)); 8717 8718 if (env->cr[4] & CR4_OSFXSR_MASK) { 8719 hflags |= HF_OSFXSR_MASK; 8720 } 8721 8722 if (env->efer & MSR_EFER_LMA) { 8723 hflags |= HF_LMA_MASK; 8724 } 8725 8726 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) { 8727 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; 8728 } else { 8729 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >> 8730 (DESC_B_SHIFT - HF_CS32_SHIFT); 8731 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >> 8732 (DESC_B_SHIFT - HF_SS32_SHIFT); 8733 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) || 8734 !(hflags & HF_CS32_MASK)) { 8735 hflags |= HF_ADDSEG_MASK; 8736 } else { 8737 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base | 8738 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT; 8739 } 8740 } 8741 env->hflags = hflags; 8742 } 8743 8744 static const Property x86_cpu_properties[] = { 8745 #ifdef CONFIG_USER_ONLY 8746 /* apic_id = 0 by default for *-user, see commit 9886e834 */ 8747 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0), 8748 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0), 8749 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0), 8750 DEFINE_PROP_INT32("module-id", X86CPU, module_id, 0), 8751 DEFINE_PROP_INT32("die-id", X86CPU, die_id, 0), 8752 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0), 8753 #else 8754 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID), 8755 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1), 8756 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1), 8757 DEFINE_PROP_INT32("module-id", X86CPU, module_id, -1), 8758 DEFINE_PROP_INT32("die-id", X86CPU, die_id, -1), 8759 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1), 8760 #endif 8761 DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID), 8762 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false), 8763 DEFINE_PROP_UINT64_CHECKMASK("lbr-fmt", X86CPU, lbr_fmt, PERF_CAP_LBR_FMT), 8764 8765 DEFINE_PROP_UINT32("hv-spinlocks", X86CPU, hyperv_spinlock_attempts, 8766 HYPERV_SPINLOCK_NEVER_NOTIFY), 8767 DEFINE_PROP_BIT64("hv-relaxed", X86CPU, hyperv_features, 8768 HYPERV_FEAT_RELAXED, 0), 8769 DEFINE_PROP_BIT64("hv-vapic", X86CPU, hyperv_features, 8770 HYPERV_FEAT_VAPIC, 0), 8771 DEFINE_PROP_BIT64("hv-time", X86CPU, hyperv_features, 8772 HYPERV_FEAT_TIME, 0), 8773 DEFINE_PROP_BIT64("hv-crash", X86CPU, hyperv_features, 8774 HYPERV_FEAT_CRASH, 0), 8775 DEFINE_PROP_BIT64("hv-reset", X86CPU, hyperv_features, 8776 HYPERV_FEAT_RESET, 0), 8777 DEFINE_PROP_BIT64("hv-vpindex", X86CPU, hyperv_features, 8778 HYPERV_FEAT_VPINDEX, 0), 8779 DEFINE_PROP_BIT64("hv-runtime", X86CPU, hyperv_features, 8780 HYPERV_FEAT_RUNTIME, 0), 8781 DEFINE_PROP_BIT64("hv-synic", X86CPU, hyperv_features, 8782 HYPERV_FEAT_SYNIC, 0), 8783 DEFINE_PROP_BIT64("hv-stimer", X86CPU, hyperv_features, 8784 HYPERV_FEAT_STIMER, 0), 8785 DEFINE_PROP_BIT64("hv-frequencies", X86CPU, hyperv_features, 8786 HYPERV_FEAT_FREQUENCIES, 0), 8787 DEFINE_PROP_BIT64("hv-reenlightenment", X86CPU, hyperv_features, 8788 HYPERV_FEAT_REENLIGHTENMENT, 0), 8789 DEFINE_PROP_BIT64("hv-tlbflush", X86CPU, hyperv_features, 8790 HYPERV_FEAT_TLBFLUSH, 0), 8791 DEFINE_PROP_BIT64("hv-evmcs", X86CPU, hyperv_features, 8792 HYPERV_FEAT_EVMCS, 0), 8793 DEFINE_PROP_BIT64("hv-ipi", X86CPU, hyperv_features, 8794 HYPERV_FEAT_IPI, 0), 8795 DEFINE_PROP_BIT64("hv-stimer-direct", X86CPU, hyperv_features, 8796 HYPERV_FEAT_STIMER_DIRECT, 0), 8797 DEFINE_PROP_BIT64("hv-avic", X86CPU, hyperv_features, 8798 HYPERV_FEAT_AVIC, 0), 8799 DEFINE_PROP_BIT64("hv-emsr-bitmap", X86CPU, hyperv_features, 8800 HYPERV_FEAT_MSR_BITMAP, 0), 8801 DEFINE_PROP_BIT64("hv-xmm-input", X86CPU, hyperv_features, 8802 HYPERV_FEAT_XMM_INPUT, 0), 8803 DEFINE_PROP_BIT64("hv-tlbflush-ext", X86CPU, hyperv_features, 8804 HYPERV_FEAT_TLBFLUSH_EXT, 0), 8805 DEFINE_PROP_BIT64("hv-tlbflush-direct", X86CPU, hyperv_features, 8806 HYPERV_FEAT_TLBFLUSH_DIRECT, 0), 8807 DEFINE_PROP_ON_OFF_AUTO("hv-no-nonarch-coresharing", X86CPU, 8808 hyperv_no_nonarch_cs, ON_OFF_AUTO_OFF), 8809 #ifdef CONFIG_SYNDBG 8810 DEFINE_PROP_BIT64("hv-syndbg", X86CPU, hyperv_features, 8811 HYPERV_FEAT_SYNDBG, 0), 8812 #endif 8813 DEFINE_PROP_BOOL("hv-passthrough", X86CPU, hyperv_passthrough, false), 8814 DEFINE_PROP_BOOL("hv-enforce-cpuid", X86CPU, hyperv_enforce_cpuid, false), 8815 8816 /* WS2008R2 identify by default */ 8817 DEFINE_PROP_UINT32("hv-version-id-build", X86CPU, hyperv_ver_id_build, 8818 0x3839), 8819 DEFINE_PROP_UINT16("hv-version-id-major", X86CPU, hyperv_ver_id_major, 8820 0x000A), 8821 DEFINE_PROP_UINT16("hv-version-id-minor", X86CPU, hyperv_ver_id_minor, 8822 0x0000), 8823 DEFINE_PROP_UINT32("hv-version-id-spack", X86CPU, hyperv_ver_id_sp, 0), 8824 DEFINE_PROP_UINT8("hv-version-id-sbranch", X86CPU, hyperv_ver_id_sb, 0), 8825 DEFINE_PROP_UINT32("hv-version-id-snumber", X86CPU, hyperv_ver_id_sn, 0), 8826 8827 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true), 8828 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false), 8829 DEFINE_PROP_BOOL("x-force-features", X86CPU, force_features, false), 8830 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true), 8831 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0), 8832 DEFINE_PROP_UINT32("guest-phys-bits", X86CPU, guest_phys_bits, -1), 8833 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false), 8834 DEFINE_PROP_UINT8("host-phys-bits-limit", X86CPU, host_phys_bits_limit, 0), 8835 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true), 8836 DEFINE_PROP_UINT32("level-func7", X86CPU, env.cpuid_level_func7, 8837 UINT32_MAX), 8838 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX), 8839 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX), 8840 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX), 8841 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0), 8842 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0), 8843 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0), 8844 DEFINE_PROP_UINT8("avx10-version", X86CPU, env.avx10_version, 0), 8845 DEFINE_PROP_UINT64("ucode-rev", X86CPU, ucode_rev, 0), 8846 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true), 8847 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor), 8848 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true), 8849 DEFINE_PROP_BOOL("x-vendor-cpuid-only", X86CPU, vendor_cpuid_only, true), 8850 DEFINE_PROP_BOOL("x-amd-topoext-features-only", X86CPU, amd_topoext_features_only, true), 8851 DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false), 8852 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true), 8853 DEFINE_PROP_BOOL("kvm-pv-enforce-cpuid", X86CPU, kvm_pv_enforce_cpuid, 8854 false), 8855 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true), 8856 DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true), 8857 DEFINE_PROP_BOOL("x-migrate-smi-count", X86CPU, migrate_smi_count, 8858 true), 8859 /* 8860 * lecacy_cache defaults to true unless the CPU model provides its 8861 * own cache information (see x86_cpu_load_def()). 8862 */ 8863 DEFINE_PROP_BOOL("legacy-cache", X86CPU, legacy_cache, true), 8864 DEFINE_PROP_BOOL("legacy-multi-node", X86CPU, legacy_multi_node, false), 8865 DEFINE_PROP_BOOL("xen-vapic", X86CPU, xen_vapic, false), 8866 8867 /* 8868 * From "Requirements for Implementing the Microsoft 8869 * Hypervisor Interface": 8870 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs 8871 * 8872 * "Starting with Windows Server 2012 and Windows 8, if 8873 * CPUID.40000005.EAX contains a value of -1, Windows assumes that 8874 * the hypervisor imposes no specific limit to the number of VPs. 8875 * In this case, Windows Server 2012 guest VMs may use more than 8876 * 64 VPs, up to the maximum supported number of processors applicable 8877 * to the specific Windows version being used." 8878 */ 8879 DEFINE_PROP_INT32("x-hv-max-vps", X86CPU, hv_max_vps, -1), 8880 DEFINE_PROP_BOOL("x-hv-synic-kvm-only", X86CPU, hyperv_synic_kvm_only, 8881 false), 8882 DEFINE_PROP_BOOL("x-intel-pt-auto-level", X86CPU, intel_pt_auto_level, 8883 true), 8884 DEFINE_PROP_BOOL("x-l1-cache-per-thread", X86CPU, l1_cache_per_core, true), 8885 }; 8886 8887 #ifndef CONFIG_USER_ONLY 8888 #include "hw/core/sysemu-cpu-ops.h" 8889 8890 static const struct SysemuCPUOps i386_sysemu_ops = { 8891 .has_work = x86_cpu_has_work, 8892 .get_memory_mapping = x86_cpu_get_memory_mapping, 8893 .get_paging_enabled = x86_cpu_get_paging_enabled, 8894 .get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug, 8895 .asidx_from_attrs = x86_asidx_from_attrs, 8896 .get_crash_info = x86_cpu_get_crash_info, 8897 .write_elf32_note = x86_cpu_write_elf32_note, 8898 .write_elf64_note = x86_cpu_write_elf64_note, 8899 .write_elf32_qemunote = x86_cpu_write_elf32_qemunote, 8900 .write_elf64_qemunote = x86_cpu_write_elf64_qemunote, 8901 .legacy_vmsd = &vmstate_x86_cpu, 8902 }; 8903 #endif 8904 8905 static void x86_cpu_common_class_init(ObjectClass *oc, const void *data) 8906 { 8907 X86CPUClass *xcc = X86_CPU_CLASS(oc); 8908 CPUClass *cc = CPU_CLASS(oc); 8909 DeviceClass *dc = DEVICE_CLASS(oc); 8910 ResettableClass *rc = RESETTABLE_CLASS(oc); 8911 FeatureWord w; 8912 8913 device_class_set_parent_realize(dc, x86_cpu_realizefn, 8914 &xcc->parent_realize); 8915 device_class_set_parent_unrealize(dc, x86_cpu_unrealizefn, 8916 &xcc->parent_unrealize); 8917 device_class_set_props(dc, x86_cpu_properties); 8918 8919 resettable_class_set_parent_phases(rc, NULL, x86_cpu_reset_hold, NULL, 8920 &xcc->parent_phases); 8921 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP; 8922 8923 cc->class_by_name = x86_cpu_class_by_name; 8924 cc->list_cpus = x86_cpu_list; 8925 cc->parse_features = x86_cpu_parse_featurestr; 8926 cc->dump_state = x86_cpu_dump_state; 8927 cc->set_pc = x86_cpu_set_pc; 8928 cc->get_pc = x86_cpu_get_pc; 8929 cc->gdb_read_register = x86_cpu_gdb_read_register; 8930 cc->gdb_write_register = x86_cpu_gdb_write_register; 8931 cc->get_arch_id = x86_cpu_get_arch_id; 8932 8933 #ifndef CONFIG_USER_ONLY 8934 cc->sysemu_ops = &i386_sysemu_ops; 8935 #endif /* !CONFIG_USER_ONLY */ 8936 #ifdef CONFIG_TCG 8937 cc->tcg_ops = &x86_tcg_ops; 8938 #endif /* CONFIG_TCG */ 8939 8940 cc->gdb_arch_name = x86_gdb_arch_name; 8941 #ifdef TARGET_X86_64 8942 cc->gdb_core_xml_file = "i386-64bit.xml"; 8943 #else 8944 cc->gdb_core_xml_file = "i386-32bit.xml"; 8945 #endif 8946 cc->disas_set_info = x86_disas_set_info; 8947 8948 dc->user_creatable = true; 8949 8950 object_class_property_add(oc, "family", "int", 8951 x86_cpuid_version_get_family, 8952 x86_cpuid_version_set_family, NULL, NULL); 8953 object_class_property_add(oc, "model", "int", 8954 x86_cpuid_version_get_model, 8955 x86_cpuid_version_set_model, NULL, NULL); 8956 object_class_property_add(oc, "stepping", "int", 8957 x86_cpuid_version_get_stepping, 8958 x86_cpuid_version_set_stepping, NULL, NULL); 8959 object_class_property_add_str(oc, "vendor", 8960 x86_cpuid_get_vendor, 8961 x86_cpuid_set_vendor); 8962 object_class_property_add_str(oc, "model-id", 8963 x86_cpuid_get_model_id, 8964 x86_cpuid_set_model_id); 8965 object_class_property_add(oc, "tsc-frequency", "int", 8966 x86_cpuid_get_tsc_freq, 8967 x86_cpuid_set_tsc_freq, NULL, NULL); 8968 /* 8969 * The "unavailable-features" property has the same semantics as 8970 * CpuDefinitionInfo.unavailable-features on the "query-cpu-definitions" 8971 * QMP command: they list the features that would have prevented the 8972 * CPU from running if the "enforce" flag was set. 8973 */ 8974 object_class_property_add(oc, "unavailable-features", "strList", 8975 x86_cpu_get_unavailable_features, 8976 NULL, NULL, NULL); 8977 8978 #if !defined(CONFIG_USER_ONLY) 8979 object_class_property_add(oc, "crash-information", "GuestPanicInformation", 8980 x86_cpu_get_crash_info_qom, NULL, NULL, NULL); 8981 #endif 8982 8983 for (w = 0; w < FEATURE_WORDS; w++) { 8984 int bitnr; 8985 for (bitnr = 0; bitnr < 64; bitnr++) { 8986 x86_cpu_register_feature_bit_props(xcc, w, bitnr); 8987 } 8988 } 8989 } 8990 8991 static const TypeInfo x86_cpu_type_info = { 8992 .name = TYPE_X86_CPU, 8993 .parent = TYPE_CPU, 8994 .instance_size = sizeof(X86CPU), 8995 .instance_align = __alignof(X86CPU), 8996 .instance_init = x86_cpu_initfn, 8997 .instance_post_init = x86_cpu_post_initfn, 8998 8999 .abstract = true, 9000 .class_size = sizeof(X86CPUClass), 9001 .class_init = x86_cpu_common_class_init, 9002 }; 9003 9004 /* "base" CPU model, used by query-cpu-model-expansion */ 9005 static void x86_cpu_base_class_init(ObjectClass *oc, const void *data) 9006 { 9007 X86CPUClass *xcc = X86_CPU_CLASS(oc); 9008 9009 xcc->static_model = true; 9010 xcc->migration_safe = true; 9011 xcc->model_description = "base CPU model type with no features enabled"; 9012 xcc->ordering = 8; 9013 } 9014 9015 static const TypeInfo x86_base_cpu_type_info = { 9016 .name = X86_CPU_TYPE_NAME("base"), 9017 .parent = TYPE_X86_CPU, 9018 .class_init = x86_cpu_base_class_init, 9019 }; 9020 9021 static void x86_cpu_register_types(void) 9022 { 9023 int i; 9024 9025 type_register_static(&x86_cpu_type_info); 9026 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) { 9027 x86_register_cpudef_types(&builtin_x86_defs[i]); 9028 } 9029 type_register_static(&max_x86_cpu_type_info); 9030 type_register_static(&x86_base_cpu_type_info); 9031 } 9032 9033 type_init(x86_cpu_register_types) 9034