1 /* 2 * i386 CPUID, CPU class, definitions, models 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/units.h" 22 #include "qemu/cutils.h" 23 #include "qemu/qemu-print.h" 24 #include "qemu/hw-version.h" 25 #include "cpu.h" 26 #include "tcg/helper-tcg.h" 27 #include "sysemu/hvf.h" 28 #include "hvf/hvf-i386.h" 29 #include "kvm/kvm_i386.h" 30 #include "sev.h" 31 #include "qapi/error.h" 32 #include "qemu/error-report.h" 33 #include "qapi/qapi-visit-machine.h" 34 #include "qapi/qmp/qerror.h" 35 #include "standard-headers/asm-x86/kvm_para.h" 36 #include "hw/qdev-properties.h" 37 #include "hw/i386/topology.h" 38 #ifndef CONFIG_USER_ONLY 39 #include "sysemu/reset.h" 40 #include "qapi/qapi-commands-machine-target.h" 41 #include "exec/address-spaces.h" 42 #include "hw/boards.h" 43 #include "hw/i386/sgx-epc.h" 44 #endif 45 46 #include "disas/capstone.h" 47 #include "cpu-internal.h" 48 49 static void x86_cpu_realizefn(DeviceState *dev, Error **errp); 50 51 /* Helpers for building CPUID[2] descriptors: */ 52 53 struct CPUID2CacheDescriptorInfo { 54 enum CacheType type; 55 int level; 56 int size; 57 int line_size; 58 int associativity; 59 }; 60 61 /* 62 * Known CPUID 2 cache descriptors. 63 * From Intel SDM Volume 2A, CPUID instruction 64 */ 65 struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = { 66 [0x06] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 8 * KiB, 67 .associativity = 4, .line_size = 32, }, 68 [0x08] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 16 * KiB, 69 .associativity = 4, .line_size = 32, }, 70 [0x09] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB, 71 .associativity = 4, .line_size = 64, }, 72 [0x0A] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB, 73 .associativity = 2, .line_size = 32, }, 74 [0x0C] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 75 .associativity = 4, .line_size = 32, }, 76 [0x0D] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 77 .associativity = 4, .line_size = 64, }, 78 [0x0E] = { .level = 1, .type = DATA_CACHE, .size = 24 * KiB, 79 .associativity = 6, .line_size = 64, }, 80 [0x1D] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB, 81 .associativity = 2, .line_size = 64, }, 82 [0x21] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 83 .associativity = 8, .line_size = 64, }, 84 /* lines per sector is not supported cpuid2_cache_descriptor(), 85 * so descriptors 0x22, 0x23 are not included 86 */ 87 [0x24] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 88 .associativity = 16, .line_size = 64, }, 89 /* lines per sector is not supported cpuid2_cache_descriptor(), 90 * so descriptors 0x25, 0x20 are not included 91 */ 92 [0x2C] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB, 93 .associativity = 8, .line_size = 64, }, 94 [0x30] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB, 95 .associativity = 8, .line_size = 64, }, 96 [0x41] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB, 97 .associativity = 4, .line_size = 32, }, 98 [0x42] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 99 .associativity = 4, .line_size = 32, }, 100 [0x43] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 101 .associativity = 4, .line_size = 32, }, 102 [0x44] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 103 .associativity = 4, .line_size = 32, }, 104 [0x45] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 105 .associativity = 4, .line_size = 32, }, 106 [0x46] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 107 .associativity = 4, .line_size = 64, }, 108 [0x47] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 109 .associativity = 8, .line_size = 64, }, 110 [0x48] = { .level = 2, .type = UNIFIED_CACHE, .size = 3 * MiB, 111 .associativity = 12, .line_size = 64, }, 112 /* Descriptor 0x49 depends on CPU family/model, so it is not included */ 113 [0x4A] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB, 114 .associativity = 12, .line_size = 64, }, 115 [0x4B] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 116 .associativity = 16, .line_size = 64, }, 117 [0x4C] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB, 118 .associativity = 12, .line_size = 64, }, 119 [0x4D] = { .level = 3, .type = UNIFIED_CACHE, .size = 16 * MiB, 120 .associativity = 16, .line_size = 64, }, 121 [0x4E] = { .level = 2, .type = UNIFIED_CACHE, .size = 6 * MiB, 122 .associativity = 24, .line_size = 64, }, 123 [0x60] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 124 .associativity = 8, .line_size = 64, }, 125 [0x66] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB, 126 .associativity = 4, .line_size = 64, }, 127 [0x67] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 128 .associativity = 4, .line_size = 64, }, 129 [0x68] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB, 130 .associativity = 4, .line_size = 64, }, 131 [0x78] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 132 .associativity = 4, .line_size = 64, }, 133 /* lines per sector is not supported cpuid2_cache_descriptor(), 134 * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included. 135 */ 136 [0x7D] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 137 .associativity = 8, .line_size = 64, }, 138 [0x7F] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 139 .associativity = 2, .line_size = 64, }, 140 [0x80] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 141 .associativity = 8, .line_size = 64, }, 142 [0x82] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 143 .associativity = 8, .line_size = 32, }, 144 [0x83] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 145 .associativity = 8, .line_size = 32, }, 146 [0x84] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 147 .associativity = 8, .line_size = 32, }, 148 [0x85] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 149 .associativity = 8, .line_size = 32, }, 150 [0x86] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 151 .associativity = 4, .line_size = 64, }, 152 [0x87] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 153 .associativity = 8, .line_size = 64, }, 154 [0xD0] = { .level = 3, .type = UNIFIED_CACHE, .size = 512 * KiB, 155 .associativity = 4, .line_size = 64, }, 156 [0xD1] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB, 157 .associativity = 4, .line_size = 64, }, 158 [0xD2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 159 .associativity = 4, .line_size = 64, }, 160 [0xD6] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB, 161 .associativity = 8, .line_size = 64, }, 162 [0xD7] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 163 .associativity = 8, .line_size = 64, }, 164 [0xD8] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 165 .associativity = 8, .line_size = 64, }, 166 [0xDC] = { .level = 3, .type = UNIFIED_CACHE, .size = 1.5 * MiB, 167 .associativity = 12, .line_size = 64, }, 168 [0xDD] = { .level = 3, .type = UNIFIED_CACHE, .size = 3 * MiB, 169 .associativity = 12, .line_size = 64, }, 170 [0xDE] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB, 171 .associativity = 12, .line_size = 64, }, 172 [0xE2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 173 .associativity = 16, .line_size = 64, }, 174 [0xE3] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 175 .associativity = 16, .line_size = 64, }, 176 [0xE4] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 177 .associativity = 16, .line_size = 64, }, 178 [0xEA] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB, 179 .associativity = 24, .line_size = 64, }, 180 [0xEB] = { .level = 3, .type = UNIFIED_CACHE, .size = 18 * MiB, 181 .associativity = 24, .line_size = 64, }, 182 [0xEC] = { .level = 3, .type = UNIFIED_CACHE, .size = 24 * MiB, 183 .associativity = 24, .line_size = 64, }, 184 }; 185 186 /* 187 * "CPUID leaf 2 does not report cache descriptor information, 188 * use CPUID leaf 4 to query cache parameters" 189 */ 190 #define CACHE_DESCRIPTOR_UNAVAILABLE 0xFF 191 192 /* 193 * Return a CPUID 2 cache descriptor for a given cache. 194 * If no known descriptor is found, return CACHE_DESCRIPTOR_UNAVAILABLE 195 */ 196 static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache) 197 { 198 int i; 199 200 assert(cache->size > 0); 201 assert(cache->level > 0); 202 assert(cache->line_size > 0); 203 assert(cache->associativity > 0); 204 for (i = 0; i < ARRAY_SIZE(cpuid2_cache_descriptors); i++) { 205 struct CPUID2CacheDescriptorInfo *d = &cpuid2_cache_descriptors[i]; 206 if (d->level == cache->level && d->type == cache->type && 207 d->size == cache->size && d->line_size == cache->line_size && 208 d->associativity == cache->associativity) { 209 return i; 210 } 211 } 212 213 return CACHE_DESCRIPTOR_UNAVAILABLE; 214 } 215 216 /* CPUID Leaf 4 constants: */ 217 218 /* EAX: */ 219 #define CACHE_TYPE_D 1 220 #define CACHE_TYPE_I 2 221 #define CACHE_TYPE_UNIFIED 3 222 223 #define CACHE_LEVEL(l) (l << 5) 224 225 #define CACHE_SELF_INIT_LEVEL (1 << 8) 226 227 /* EDX: */ 228 #define CACHE_NO_INVD_SHARING (1 << 0) 229 #define CACHE_INCLUSIVE (1 << 1) 230 #define CACHE_COMPLEX_IDX (1 << 2) 231 232 /* Encode CacheType for CPUID[4].EAX */ 233 #define CACHE_TYPE(t) (((t) == DATA_CACHE) ? CACHE_TYPE_D : \ 234 ((t) == INSTRUCTION_CACHE) ? CACHE_TYPE_I : \ 235 ((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \ 236 0 /* Invalid value */) 237 238 static uint32_t max_thread_ids_for_cache(X86CPUTopoInfo *topo_info, 239 enum CPUTopoLevel share_level) 240 { 241 uint32_t num_ids = 0; 242 243 switch (share_level) { 244 case CPU_TOPO_LEVEL_CORE: 245 num_ids = 1 << apicid_core_offset(topo_info); 246 break; 247 case CPU_TOPO_LEVEL_DIE: 248 num_ids = 1 << apicid_die_offset(topo_info); 249 break; 250 case CPU_TOPO_LEVEL_PACKAGE: 251 num_ids = 1 << apicid_pkg_offset(topo_info); 252 break; 253 default: 254 /* 255 * Currently there is no use case for SMT and MODULE, so use 256 * assert directly to facilitate debugging. 257 */ 258 g_assert_not_reached(); 259 } 260 261 return num_ids - 1; 262 } 263 264 static uint32_t max_core_ids_in_package(X86CPUTopoInfo *topo_info) 265 { 266 uint32_t num_cores = 1 << (apicid_pkg_offset(topo_info) - 267 apicid_core_offset(topo_info)); 268 return num_cores - 1; 269 } 270 271 /* Encode cache info for CPUID[4] */ 272 static void encode_cache_cpuid4(CPUCacheInfo *cache, 273 X86CPUTopoInfo *topo_info, 274 uint32_t *eax, uint32_t *ebx, 275 uint32_t *ecx, uint32_t *edx) 276 { 277 assert(cache->size == cache->line_size * cache->associativity * 278 cache->partitions * cache->sets); 279 280 *eax = CACHE_TYPE(cache->type) | 281 CACHE_LEVEL(cache->level) | 282 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) | 283 (max_core_ids_in_package(topo_info) << 26) | 284 (max_thread_ids_for_cache(topo_info, cache->share_level) << 14); 285 286 assert(cache->line_size > 0); 287 assert(cache->partitions > 0); 288 assert(cache->associativity > 0); 289 /* We don't implement fully-associative caches */ 290 assert(cache->associativity < cache->sets); 291 *ebx = (cache->line_size - 1) | 292 ((cache->partitions - 1) << 12) | 293 ((cache->associativity - 1) << 22); 294 295 assert(cache->sets > 0); 296 *ecx = cache->sets - 1; 297 298 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) | 299 (cache->inclusive ? CACHE_INCLUSIVE : 0) | 300 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); 301 } 302 303 static uint32_t num_threads_by_topo_level(X86CPUTopoInfo *topo_info, 304 enum CPUTopoLevel topo_level) 305 { 306 switch (topo_level) { 307 case CPU_TOPO_LEVEL_SMT: 308 return 1; 309 case CPU_TOPO_LEVEL_CORE: 310 return topo_info->threads_per_core; 311 case CPU_TOPO_LEVEL_MODULE: 312 return topo_info->threads_per_core * topo_info->cores_per_module; 313 case CPU_TOPO_LEVEL_DIE: 314 return topo_info->threads_per_core * topo_info->cores_per_module * 315 topo_info->modules_per_die; 316 case CPU_TOPO_LEVEL_PACKAGE: 317 return topo_info->threads_per_core * topo_info->cores_per_module * 318 topo_info->modules_per_die * topo_info->dies_per_pkg; 319 default: 320 g_assert_not_reached(); 321 } 322 return 0; 323 } 324 325 static uint32_t apicid_offset_by_topo_level(X86CPUTopoInfo *topo_info, 326 enum CPUTopoLevel topo_level) 327 { 328 switch (topo_level) { 329 case CPU_TOPO_LEVEL_SMT: 330 return 0; 331 case CPU_TOPO_LEVEL_CORE: 332 return apicid_core_offset(topo_info); 333 case CPU_TOPO_LEVEL_MODULE: 334 return apicid_module_offset(topo_info); 335 case CPU_TOPO_LEVEL_DIE: 336 return apicid_die_offset(topo_info); 337 case CPU_TOPO_LEVEL_PACKAGE: 338 return apicid_pkg_offset(topo_info); 339 default: 340 g_assert_not_reached(); 341 } 342 return 0; 343 } 344 345 static uint32_t cpuid1f_topo_type(enum CPUTopoLevel topo_level) 346 { 347 switch (topo_level) { 348 case CPU_TOPO_LEVEL_INVALID: 349 return CPUID_1F_ECX_TOPO_LEVEL_INVALID; 350 case CPU_TOPO_LEVEL_SMT: 351 return CPUID_1F_ECX_TOPO_LEVEL_SMT; 352 case CPU_TOPO_LEVEL_CORE: 353 return CPUID_1F_ECX_TOPO_LEVEL_CORE; 354 case CPU_TOPO_LEVEL_MODULE: 355 return CPUID_1F_ECX_TOPO_LEVEL_MODULE; 356 case CPU_TOPO_LEVEL_DIE: 357 return CPUID_1F_ECX_TOPO_LEVEL_DIE; 358 default: 359 /* Other types are not supported in QEMU. */ 360 g_assert_not_reached(); 361 } 362 return 0; 363 } 364 365 static void encode_topo_cpuid1f(CPUX86State *env, uint32_t count, 366 X86CPUTopoInfo *topo_info, 367 uint32_t *eax, uint32_t *ebx, 368 uint32_t *ecx, uint32_t *edx) 369 { 370 X86CPU *cpu = env_archcpu(env); 371 unsigned long level, next_level; 372 uint32_t num_threads_next_level, offset_next_level; 373 374 assert(count + 1 < CPU_TOPO_LEVEL_MAX); 375 376 /* 377 * Find the No.(count + 1) topology level in avail_cpu_topo bitmap. 378 * The search starts from bit 1 (CPU_TOPO_LEVEL_INVALID + 1). 379 */ 380 level = CPU_TOPO_LEVEL_INVALID; 381 for (int i = 0; i <= count; i++) { 382 level = find_next_bit(env->avail_cpu_topo, 383 CPU_TOPO_LEVEL_PACKAGE, 384 level + 1); 385 386 /* 387 * CPUID[0x1f] doesn't explicitly encode the package level, 388 * and it just encodes the invalid level (all fields are 0) 389 * into the last subleaf of 0x1f. 390 */ 391 if (level == CPU_TOPO_LEVEL_PACKAGE) { 392 level = CPU_TOPO_LEVEL_INVALID; 393 break; 394 } 395 } 396 397 if (level == CPU_TOPO_LEVEL_INVALID) { 398 num_threads_next_level = 0; 399 offset_next_level = 0; 400 } else { 401 next_level = find_next_bit(env->avail_cpu_topo, 402 CPU_TOPO_LEVEL_PACKAGE, 403 level + 1); 404 num_threads_next_level = num_threads_by_topo_level(topo_info, 405 next_level); 406 offset_next_level = apicid_offset_by_topo_level(topo_info, 407 next_level); 408 } 409 410 *eax = offset_next_level; 411 /* The count (bits 15-00) doesn't need to be reliable. */ 412 *ebx = num_threads_next_level & 0xffff; 413 *ecx = (count & 0xff) | (cpuid1f_topo_type(level) << 8); 414 *edx = cpu->apic_id; 415 416 assert(!(*eax & ~0x1f)); 417 } 418 419 /* Encode cache info for CPUID[0x80000005].ECX or CPUID[0x80000005].EDX */ 420 static uint32_t encode_cache_cpuid80000005(CPUCacheInfo *cache) 421 { 422 assert(cache->size % 1024 == 0); 423 assert(cache->lines_per_tag > 0); 424 assert(cache->associativity > 0); 425 assert(cache->line_size > 0); 426 return ((cache->size / 1024) << 24) | (cache->associativity << 16) | 427 (cache->lines_per_tag << 8) | (cache->line_size); 428 } 429 430 #define ASSOC_FULL 0xFF 431 432 /* AMD associativity encoding used on CPUID Leaf 0x80000006: */ 433 #define AMD_ENC_ASSOC(a) (a <= 1 ? a : \ 434 a == 2 ? 0x2 : \ 435 a == 4 ? 0x4 : \ 436 a == 8 ? 0x6 : \ 437 a == 16 ? 0x8 : \ 438 a == 32 ? 0xA : \ 439 a == 48 ? 0xB : \ 440 a == 64 ? 0xC : \ 441 a == 96 ? 0xD : \ 442 a == 128 ? 0xE : \ 443 a == ASSOC_FULL ? 0xF : \ 444 0 /* invalid value */) 445 446 /* 447 * Encode cache info for CPUID[0x80000006].ECX and CPUID[0x80000006].EDX 448 * @l3 can be NULL. 449 */ 450 static void encode_cache_cpuid80000006(CPUCacheInfo *l2, 451 CPUCacheInfo *l3, 452 uint32_t *ecx, uint32_t *edx) 453 { 454 assert(l2->size % 1024 == 0); 455 assert(l2->associativity > 0); 456 assert(l2->lines_per_tag > 0); 457 assert(l2->line_size > 0); 458 *ecx = ((l2->size / 1024) << 16) | 459 (AMD_ENC_ASSOC(l2->associativity) << 12) | 460 (l2->lines_per_tag << 8) | (l2->line_size); 461 462 if (l3) { 463 assert(l3->size % (512 * 1024) == 0); 464 assert(l3->associativity > 0); 465 assert(l3->lines_per_tag > 0); 466 assert(l3->line_size > 0); 467 *edx = ((l3->size / (512 * 1024)) << 18) | 468 (AMD_ENC_ASSOC(l3->associativity) << 12) | 469 (l3->lines_per_tag << 8) | (l3->line_size); 470 } else { 471 *edx = 0; 472 } 473 } 474 475 /* Encode cache info for CPUID[8000001D] */ 476 static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, 477 X86CPUTopoInfo *topo_info, 478 uint32_t *eax, uint32_t *ebx, 479 uint32_t *ecx, uint32_t *edx) 480 { 481 assert(cache->size == cache->line_size * cache->associativity * 482 cache->partitions * cache->sets); 483 484 *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) | 485 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0); 486 *eax |= max_thread_ids_for_cache(topo_info, cache->share_level) << 14; 487 488 assert(cache->line_size > 0); 489 assert(cache->partitions > 0); 490 assert(cache->associativity > 0); 491 /* We don't implement fully-associative caches */ 492 assert(cache->associativity < cache->sets); 493 *ebx = (cache->line_size - 1) | 494 ((cache->partitions - 1) << 12) | 495 ((cache->associativity - 1) << 22); 496 497 assert(cache->sets > 0); 498 *ecx = cache->sets - 1; 499 500 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) | 501 (cache->inclusive ? CACHE_INCLUSIVE : 0) | 502 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); 503 } 504 505 /* Encode cache info for CPUID[8000001E] */ 506 static void encode_topo_cpuid8000001e(X86CPU *cpu, X86CPUTopoInfo *topo_info, 507 uint32_t *eax, uint32_t *ebx, 508 uint32_t *ecx, uint32_t *edx) 509 { 510 X86CPUTopoIDs topo_ids; 511 512 x86_topo_ids_from_apicid(cpu->apic_id, topo_info, &topo_ids); 513 514 *eax = cpu->apic_id; 515 516 /* 517 * CPUID_Fn8000001E_EBX [Core Identifiers] (CoreId) 518 * Read-only. Reset: 0000_XXXXh. 519 * See Core::X86::Cpuid::ExtApicId. 520 * Core::X86::Cpuid::CoreId_lthree[1:0]_core[3:0]_thread[1:0]; 521 * Bits Description 522 * 31:16 Reserved. 523 * 15:8 ThreadsPerCore: threads per core. Read-only. Reset: XXh. 524 * The number of threads per core is ThreadsPerCore+1. 525 * 7:0 CoreId: core ID. Read-only. Reset: XXh. 526 * 527 * NOTE: CoreId is already part of apic_id. Just use it. We can 528 * use all the 8 bits to represent the core_id here. 529 */ 530 *ebx = ((topo_info->threads_per_core - 1) << 8) | (topo_ids.core_id & 0xFF); 531 532 /* 533 * CPUID_Fn8000001E_ECX [Node Identifiers] (NodeId) 534 * Read-only. Reset: 0000_0XXXh. 535 * Core::X86::Cpuid::NodeId_lthree[1:0]_core[3:0]_thread[1:0]; 536 * Bits Description 537 * 31:11 Reserved. 538 * 10:8 NodesPerProcessor: Node per processor. Read-only. Reset: XXXb. 539 * ValidValues: 540 * Value Description 541 * 0h 1 node per processor. 542 * 7h-1h Reserved. 543 * 7:0 NodeId: Node ID. Read-only. Reset: XXh. 544 * 545 * NOTE: Hardware reserves 3 bits for number of nodes per processor. 546 * But users can create more nodes than the actual hardware can 547 * support. To genaralize we can use all the upper 8 bits for nodes. 548 * NodeId is combination of node and socket_id which is already decoded 549 * in apic_id. Just use it by shifting. 550 */ 551 if (cpu->legacy_multi_node) { 552 *ecx = ((topo_info->dies_per_pkg - 1) << 8) | 553 ((cpu->apic_id >> apicid_die_offset(topo_info)) & 0xFF); 554 } else { 555 *ecx = (cpu->apic_id >> apicid_pkg_offset(topo_info)) & 0xFF; 556 } 557 558 *edx = 0; 559 } 560 561 /* 562 * Definitions of the hardcoded cache entries we expose: 563 * These are legacy cache values. If there is a need to change any 564 * of these values please use builtin_x86_defs 565 */ 566 567 /* L1 data cache: */ 568 static CPUCacheInfo legacy_l1d_cache = { 569 .type = DATA_CACHE, 570 .level = 1, 571 .size = 32 * KiB, 572 .self_init = 1, 573 .line_size = 64, 574 .associativity = 8, 575 .sets = 64, 576 .partitions = 1, 577 .no_invd_sharing = true, 578 .share_level = CPU_TOPO_LEVEL_CORE, 579 }; 580 581 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ 582 static CPUCacheInfo legacy_l1d_cache_amd = { 583 .type = DATA_CACHE, 584 .level = 1, 585 .size = 64 * KiB, 586 .self_init = 1, 587 .line_size = 64, 588 .associativity = 2, 589 .sets = 512, 590 .partitions = 1, 591 .lines_per_tag = 1, 592 .no_invd_sharing = true, 593 .share_level = CPU_TOPO_LEVEL_CORE, 594 }; 595 596 /* L1 instruction cache: */ 597 static CPUCacheInfo legacy_l1i_cache = { 598 .type = INSTRUCTION_CACHE, 599 .level = 1, 600 .size = 32 * KiB, 601 .self_init = 1, 602 .line_size = 64, 603 .associativity = 8, 604 .sets = 64, 605 .partitions = 1, 606 .no_invd_sharing = true, 607 .share_level = CPU_TOPO_LEVEL_CORE, 608 }; 609 610 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ 611 static CPUCacheInfo legacy_l1i_cache_amd = { 612 .type = INSTRUCTION_CACHE, 613 .level = 1, 614 .size = 64 * KiB, 615 .self_init = 1, 616 .line_size = 64, 617 .associativity = 2, 618 .sets = 512, 619 .partitions = 1, 620 .lines_per_tag = 1, 621 .no_invd_sharing = true, 622 .share_level = CPU_TOPO_LEVEL_CORE, 623 }; 624 625 /* Level 2 unified cache: */ 626 static CPUCacheInfo legacy_l2_cache = { 627 .type = UNIFIED_CACHE, 628 .level = 2, 629 .size = 4 * MiB, 630 .self_init = 1, 631 .line_size = 64, 632 .associativity = 16, 633 .sets = 4096, 634 .partitions = 1, 635 .no_invd_sharing = true, 636 .share_level = CPU_TOPO_LEVEL_CORE, 637 }; 638 639 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */ 640 static CPUCacheInfo legacy_l2_cache_cpuid2 = { 641 .type = UNIFIED_CACHE, 642 .level = 2, 643 .size = 2 * MiB, 644 .line_size = 64, 645 .associativity = 8, 646 .share_level = CPU_TOPO_LEVEL_INVALID, 647 }; 648 649 650 /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */ 651 static CPUCacheInfo legacy_l2_cache_amd = { 652 .type = UNIFIED_CACHE, 653 .level = 2, 654 .size = 512 * KiB, 655 .line_size = 64, 656 .lines_per_tag = 1, 657 .associativity = 16, 658 .sets = 512, 659 .partitions = 1, 660 .share_level = CPU_TOPO_LEVEL_CORE, 661 }; 662 663 /* Level 3 unified cache: */ 664 static CPUCacheInfo legacy_l3_cache = { 665 .type = UNIFIED_CACHE, 666 .level = 3, 667 .size = 16 * MiB, 668 .line_size = 64, 669 .associativity = 16, 670 .sets = 16384, 671 .partitions = 1, 672 .lines_per_tag = 1, 673 .self_init = true, 674 .inclusive = true, 675 .complex_indexing = true, 676 .share_level = CPU_TOPO_LEVEL_DIE, 677 }; 678 679 /* TLB definitions: */ 680 681 #define L1_DTLB_2M_ASSOC 1 682 #define L1_DTLB_2M_ENTRIES 255 683 #define L1_DTLB_4K_ASSOC 1 684 #define L1_DTLB_4K_ENTRIES 255 685 686 #define L1_ITLB_2M_ASSOC 1 687 #define L1_ITLB_2M_ENTRIES 255 688 #define L1_ITLB_4K_ASSOC 1 689 #define L1_ITLB_4K_ENTRIES 255 690 691 #define L2_DTLB_2M_ASSOC 0 /* disabled */ 692 #define L2_DTLB_2M_ENTRIES 0 /* disabled */ 693 #define L2_DTLB_4K_ASSOC 4 694 #define L2_DTLB_4K_ENTRIES 512 695 696 #define L2_ITLB_2M_ASSOC 0 /* disabled */ 697 #define L2_ITLB_2M_ENTRIES 0 /* disabled */ 698 #define L2_ITLB_4K_ASSOC 4 699 #define L2_ITLB_4K_ENTRIES 512 700 701 /* CPUID Leaf 0x14 constants: */ 702 #define INTEL_PT_MAX_SUBLEAF 0x1 703 /* 704 * bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MATCH 705 * MSR can be accessed; 706 * bit[01]: Support Configurable PSB and Cycle-Accurate Mode; 707 * bit[02]: Support IP Filtering, TraceStop filtering, and preservation 708 * of Intel PT MSRs across warm reset; 709 * bit[03]: Support MTC timing packet and suppression of COFI-based packets; 710 */ 711 #define INTEL_PT_MINIMAL_EBX 0xf 712 /* 713 * bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 and 714 * IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be 715 * accessed; 716 * bit[01]: ToPA tables can hold any number of output entries, up to the 717 * maximum allowed by the MaskOrTableOffset field of 718 * IA32_RTIT_OUTPUT_MASK_PTRS; 719 * bit[02]: Support Single-Range Output scheme; 720 */ 721 #define INTEL_PT_MINIMAL_ECX 0x7 722 /* generated packets which contain IP payloads have LIP values */ 723 #define INTEL_PT_IP_LIP (1 << 31) 724 #define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */ 725 #define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3 726 #define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */ 727 #define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */ 728 #define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */ 729 730 /* CPUID Leaf 0x1D constants: */ 731 #define INTEL_AMX_TILE_MAX_SUBLEAF 0x1 732 #define INTEL_AMX_TOTAL_TILE_BYTES 0x2000 733 #define INTEL_AMX_BYTES_PER_TILE 0x400 734 #define INTEL_AMX_BYTES_PER_ROW 0x40 735 #define INTEL_AMX_TILE_MAX_NAMES 0x8 736 #define INTEL_AMX_TILE_MAX_ROWS 0x10 737 738 /* CPUID Leaf 0x1E constants: */ 739 #define INTEL_AMX_TMUL_MAX_K 0x10 740 #define INTEL_AMX_TMUL_MAX_N 0x40 741 742 void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1, 743 uint32_t vendor2, uint32_t vendor3) 744 { 745 int i; 746 for (i = 0; i < 4; i++) { 747 dst[i] = vendor1 >> (8 * i); 748 dst[i + 4] = vendor2 >> (8 * i); 749 dst[i + 8] = vendor3 >> (8 * i); 750 } 751 dst[CPUID_VENDOR_SZ] = '\0'; 752 } 753 754 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE) 755 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \ 756 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC) 757 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \ 758 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ 759 CPUID_PSE36 | CPUID_FXSR) 760 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE) 761 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \ 762 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \ 763 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \ 764 CPUID_PAE | CPUID_SEP | CPUID_APIC) 765 766 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \ 767 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \ 768 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ 769 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \ 770 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE) 771 /* partly implemented: 772 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */ 773 /* missing: 774 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */ 775 776 /* 777 * Kernel-only features that can be shown to usermode programs even if 778 * they aren't actually supported by TCG, because qemu-user only runs 779 * in CPL=3; remove them if they are ever implemented for system emulation. 780 */ 781 #if defined CONFIG_USER_ONLY 782 #define CPUID_EXT_KERNEL_FEATURES \ 783 (CPUID_EXT_PCID | CPUID_EXT_TSC_DEADLINE_TIMER) 784 #else 785 #define CPUID_EXT_KERNEL_FEATURES 0 786 #endif 787 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \ 788 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \ 789 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \ 790 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \ 791 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR | \ 792 CPUID_EXT_RDRAND | CPUID_EXT_AVX | CPUID_EXT_F16C | \ 793 CPUID_EXT_FMA | CPUID_EXT_X2APIC | CPUID_EXT_KERNEL_FEATURES) 794 /* missing: 795 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX, 796 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, 797 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA, 798 CPUID_EXT_TSC_DEADLINE_TIMER 799 */ 800 801 #ifdef TARGET_X86_64 802 #define TCG_EXT2_X86_64_FEATURES CPUID_EXT2_LM 803 #else 804 #define TCG_EXT2_X86_64_FEATURES 0 805 #endif 806 807 /* 808 * CPUID_*_KERNEL_FEATURES denotes bits and features that are not usable 809 * in usermode or by 32-bit programs. Those are added to supported 810 * TCG features unconditionally in user-mode emulation mode. This may 811 * indeed seem strange or incorrect, but it works because code running 812 * under usermode emulation cannot access them. 813 * 814 * Even for long mode, qemu-i386 is not running "a userspace program on a 815 * 32-bit CPU"; it's running "a userspace program with a 32-bit code segment" 816 * and therefore using the 32-bit ABI; the CPU itself might be 64-bit 817 * but again the difference is only visible in kernel mode. 818 */ 819 #if defined CONFIG_LINUX_USER 820 #define CPUID_EXT2_KERNEL_FEATURES (CPUID_EXT2_LM | CPUID_EXT2_FFXSR) 821 #elif defined CONFIG_USER_ONLY 822 /* FIXME: Long mode not yet supported for i386 bsd-user */ 823 #define CPUID_EXT2_KERNEL_FEATURES CPUID_EXT2_FFXSR 824 #else 825 #define CPUID_EXT2_KERNEL_FEATURES 0 826 #endif 827 828 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \ 829 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \ 830 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \ 831 CPUID_EXT2_SYSCALL | TCG_EXT2_X86_64_FEATURES | \ 832 CPUID_EXT2_KERNEL_FEATURES) 833 834 #if defined CONFIG_USER_ONLY 835 #define CPUID_EXT3_KERNEL_FEATURES CPUID_EXT3_OSVW 836 #else 837 #define CPUID_EXT3_KERNEL_FEATURES 0 838 #endif 839 840 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \ 841 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A | \ 842 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_KERNEL_FEATURES) 843 844 #define TCG_EXT4_FEATURES 0 845 846 #if defined CONFIG_USER_ONLY 847 #define CPUID_SVM_KERNEL_FEATURES (CPUID_SVM_NRIPSAVE | CPUID_SVM_VNMI) 848 #else 849 #define CPUID_SVM_KERNEL_FEATURES 0 850 #endif 851 #define TCG_SVM_FEATURES (CPUID_SVM_NPT | CPUID_SVM_VGIF | \ 852 CPUID_SVM_SVME_ADDR_CHK | CPUID_SVM_KERNEL_FEATURES) 853 854 #define TCG_KVM_FEATURES 0 855 856 #if defined CONFIG_USER_ONLY 857 #define CPUID_7_0_EBX_KERNEL_FEATURES CPUID_7_0_EBX_INVPCID 858 #else 859 #define CPUID_7_0_EBX_KERNEL_FEATURES 0 860 #endif 861 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \ 862 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \ 863 CPUID_7_0_EBX_CLFLUSHOPT | \ 864 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \ 865 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_RDSEED | \ 866 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_KERNEL_FEATURES) 867 /* missing: 868 CPUID_7_0_EBX_HLE 869 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM */ 870 871 #if !defined CONFIG_USER_ONLY || defined CONFIG_LINUX 872 #define TCG_7_0_ECX_RDPID CPUID_7_0_ECX_RDPID 873 #else 874 #define TCG_7_0_ECX_RDPID 0 875 #endif 876 #define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | \ 877 /* CPUID_7_0_ECX_OSPKE is dynamic */ \ 878 CPUID_7_0_ECX_LA57 | CPUID_7_0_ECX_PKS | CPUID_7_0_ECX_VAES | \ 879 TCG_7_0_ECX_RDPID) 880 881 #if defined CONFIG_USER_ONLY 882 #define CPUID_7_0_EDX_KERNEL_FEATURES (CPUID_7_0_EDX_SPEC_CTRL | \ 883 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD) 884 #else 885 #define CPUID_7_0_EDX_KERNEL_FEATURES 0 886 #endif 887 #define TCG_7_0_EDX_FEATURES (CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_KERNEL_FEATURES) 888 889 #define TCG_7_1_EAX_FEATURES (CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | \ 890 CPUID_7_1_EAX_FSRC | CPUID_7_1_EAX_CMPCCXADD) 891 #define TCG_7_1_EDX_FEATURES 0 892 #define TCG_7_2_EDX_FEATURES 0 893 #define TCG_APM_FEATURES 0 894 #define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT 895 #define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1) 896 /* missing: 897 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */ 898 #define TCG_14_0_ECX_FEATURES 0 899 #define TCG_SGX_12_0_EAX_FEATURES 0 900 #define TCG_SGX_12_0_EBX_FEATURES 0 901 #define TCG_SGX_12_1_EAX_FEATURES 0 902 903 #if defined CONFIG_USER_ONLY 904 #define CPUID_8000_0008_EBX_KERNEL_FEATURES (CPUID_8000_0008_EBX_IBPB | \ 905 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | \ 906 CPUID_8000_0008_EBX_STIBP_ALWAYS_ON | CPUID_8000_0008_EBX_AMD_SSBD | \ 907 CPUID_8000_0008_EBX_AMD_PSFD) 908 #else 909 #define CPUID_8000_0008_EBX_KERNEL_FEATURES 0 910 #endif 911 912 #define TCG_8000_0008_EBX (CPUID_8000_0008_EBX_XSAVEERPTR | \ 913 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_KERNEL_FEATURES) 914 915 FeatureWordInfo feature_word_info[FEATURE_WORDS] = { 916 [FEAT_1_EDX] = { 917 .type = CPUID_FEATURE_WORD, 918 .feat_names = { 919 "fpu", "vme", "de", "pse", 920 "tsc", "msr", "pae", "mce", 921 "cx8", "apic", NULL, "sep", 922 "mtrr", "pge", "mca", "cmov", 923 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */, 924 NULL, "ds" /* Intel dts */, "acpi", "mmx", 925 "fxsr", "sse", "sse2", "ss", 926 "ht" /* Intel htt */, "tm", "ia64", "pbe", 927 }, 928 .cpuid = {.eax = 1, .reg = R_EDX, }, 929 .tcg_features = TCG_FEATURES, 930 .no_autoenable_flags = CPUID_HT, 931 }, 932 [FEAT_1_ECX] = { 933 .type = CPUID_FEATURE_WORD, 934 .feat_names = { 935 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor", 936 "ds-cpl", "vmx", "smx", "est", 937 "tm2", "ssse3", "cid", NULL, 938 "fma", "cx16", "xtpr", "pdcm", 939 NULL, "pcid", "dca", "sse4.1", 940 "sse4.2", "x2apic", "movbe", "popcnt", 941 "tsc-deadline", "aes", "xsave", NULL /* osxsave */, 942 "avx", "f16c", "rdrand", "hypervisor", 943 }, 944 .cpuid = { .eax = 1, .reg = R_ECX, }, 945 .tcg_features = TCG_EXT_FEATURES, 946 }, 947 /* Feature names that are already defined on feature_name[] but 948 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their 949 * names on feat_names below. They are copied automatically 950 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD. 951 */ 952 [FEAT_8000_0001_EDX] = { 953 .type = CPUID_FEATURE_WORD, 954 .feat_names = { 955 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */, 956 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */, 957 NULL /* cx8 */, NULL /* apic */, NULL, "syscall", 958 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */, 959 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */, 960 "nx", NULL, "mmxext", NULL /* mmx */, 961 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp", 962 NULL, "lm", "3dnowext", "3dnow", 963 }, 964 .cpuid = { .eax = 0x80000001, .reg = R_EDX, }, 965 .tcg_features = TCG_EXT2_FEATURES, 966 }, 967 [FEAT_8000_0001_ECX] = { 968 .type = CPUID_FEATURE_WORD, 969 .feat_names = { 970 "lahf-lm", "cmp-legacy", "svm", "extapic", 971 "cr8legacy", "abm", "sse4a", "misalignsse", 972 "3dnowprefetch", "osvw", "ibs", "xop", 973 "skinit", "wdt", NULL, "lwp", 974 "fma4", "tce", NULL, "nodeid-msr", 975 NULL, "tbm", "topoext", "perfctr-core", 976 "perfctr-nb", NULL, NULL, NULL, 977 NULL, NULL, NULL, NULL, 978 }, 979 .cpuid = { .eax = 0x80000001, .reg = R_ECX, }, 980 .tcg_features = TCG_EXT3_FEATURES, 981 /* 982 * TOPOEXT is always allowed but can't be enabled blindly by 983 * "-cpu host", as it requires consistent cache topology info 984 * to be provided so it doesn't confuse guests. 985 */ 986 .no_autoenable_flags = CPUID_EXT3_TOPOEXT, 987 }, 988 [FEAT_C000_0001_EDX] = { 989 .type = CPUID_FEATURE_WORD, 990 .feat_names = { 991 NULL, NULL, "xstore", "xstore-en", 992 NULL, NULL, "xcrypt", "xcrypt-en", 993 "ace2", "ace2-en", "phe", "phe-en", 994 "pmm", "pmm-en", NULL, NULL, 995 NULL, NULL, NULL, NULL, 996 NULL, NULL, NULL, NULL, 997 NULL, NULL, NULL, NULL, 998 NULL, NULL, NULL, NULL, 999 }, 1000 .cpuid = { .eax = 0xC0000001, .reg = R_EDX, }, 1001 .tcg_features = TCG_EXT4_FEATURES, 1002 }, 1003 [FEAT_KVM] = { 1004 .type = CPUID_FEATURE_WORD, 1005 .feat_names = { 1006 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock", 1007 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt", 1008 NULL, "kvm-pv-tlb-flush", "kvm-asyncpf-vmexit", "kvm-pv-ipi", 1009 "kvm-poll-control", "kvm-pv-sched-yield", "kvm-asyncpf-int", "kvm-msi-ext-dest-id", 1010 NULL, NULL, NULL, NULL, 1011 NULL, NULL, NULL, NULL, 1012 "kvmclock-stable-bit", NULL, NULL, NULL, 1013 NULL, NULL, NULL, NULL, 1014 }, 1015 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EAX, }, 1016 .tcg_features = TCG_KVM_FEATURES, 1017 }, 1018 [FEAT_KVM_HINTS] = { 1019 .type = CPUID_FEATURE_WORD, 1020 .feat_names = { 1021 "kvm-hint-dedicated", NULL, NULL, NULL, 1022 NULL, NULL, NULL, NULL, 1023 NULL, NULL, NULL, NULL, 1024 NULL, NULL, NULL, NULL, 1025 NULL, NULL, NULL, NULL, 1026 NULL, NULL, NULL, NULL, 1027 NULL, NULL, NULL, NULL, 1028 NULL, NULL, NULL, NULL, 1029 }, 1030 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EDX, }, 1031 .tcg_features = TCG_KVM_FEATURES, 1032 /* 1033 * KVM hints aren't auto-enabled by -cpu host, they need to be 1034 * explicitly enabled in the command-line. 1035 */ 1036 .no_autoenable_flags = ~0U, 1037 }, 1038 [FEAT_SVM] = { 1039 .type = CPUID_FEATURE_WORD, 1040 .feat_names = { 1041 "npt", "lbrv", "svm-lock", "nrip-save", 1042 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists", 1043 NULL, NULL, "pause-filter", NULL, 1044 "pfthreshold", "avic", NULL, "v-vmsave-vmload", 1045 "vgif", NULL, NULL, NULL, 1046 NULL, NULL, NULL, NULL, 1047 NULL, "vnmi", NULL, NULL, 1048 "svme-addr-chk", NULL, NULL, NULL, 1049 }, 1050 .cpuid = { .eax = 0x8000000A, .reg = R_EDX, }, 1051 .tcg_features = TCG_SVM_FEATURES, 1052 }, 1053 [FEAT_7_0_EBX] = { 1054 .type = CPUID_FEATURE_WORD, 1055 .feat_names = { 1056 "fsgsbase", "tsc-adjust", "sgx", "bmi1", 1057 "hle", "avx2", NULL, "smep", 1058 "bmi2", "erms", "invpcid", "rtm", 1059 NULL, NULL, "mpx", NULL, 1060 "avx512f", "avx512dq", "rdseed", "adx", 1061 "smap", "avx512ifma", "pcommit", "clflushopt", 1062 "clwb", "intel-pt", "avx512pf", "avx512er", 1063 "avx512cd", "sha-ni", "avx512bw", "avx512vl", 1064 }, 1065 .cpuid = { 1066 .eax = 7, 1067 .needs_ecx = true, .ecx = 0, 1068 .reg = R_EBX, 1069 }, 1070 .tcg_features = TCG_7_0_EBX_FEATURES, 1071 }, 1072 [FEAT_7_0_ECX] = { 1073 .type = CPUID_FEATURE_WORD, 1074 .feat_names = { 1075 NULL, "avx512vbmi", "umip", "pku", 1076 NULL /* ospke */, "waitpkg", "avx512vbmi2", NULL, 1077 "gfni", "vaes", "vpclmulqdq", "avx512vnni", 1078 "avx512bitalg", NULL, "avx512-vpopcntdq", NULL, 1079 "la57", NULL, NULL, NULL, 1080 NULL, NULL, "rdpid", NULL, 1081 "bus-lock-detect", "cldemote", NULL, "movdiri", 1082 "movdir64b", NULL, "sgxlc", "pks", 1083 }, 1084 .cpuid = { 1085 .eax = 7, 1086 .needs_ecx = true, .ecx = 0, 1087 .reg = R_ECX, 1088 }, 1089 .tcg_features = TCG_7_0_ECX_FEATURES, 1090 }, 1091 [FEAT_7_0_EDX] = { 1092 .type = CPUID_FEATURE_WORD, 1093 .feat_names = { 1094 NULL, NULL, "avx512-4vnniw", "avx512-4fmaps", 1095 "fsrm", NULL, NULL, NULL, 1096 "avx512-vp2intersect", NULL, "md-clear", NULL, 1097 NULL, NULL, "serialize", NULL, 1098 "tsx-ldtrk", NULL, NULL /* pconfig */, "arch-lbr", 1099 NULL, NULL, "amx-bf16", "avx512-fp16", 1100 "amx-tile", "amx-int8", "spec-ctrl", "stibp", 1101 "flush-l1d", "arch-capabilities", "core-capability", "ssbd", 1102 }, 1103 .cpuid = { 1104 .eax = 7, 1105 .needs_ecx = true, .ecx = 0, 1106 .reg = R_EDX, 1107 }, 1108 .tcg_features = TCG_7_0_EDX_FEATURES, 1109 }, 1110 [FEAT_7_1_EAX] = { 1111 .type = CPUID_FEATURE_WORD, 1112 .feat_names = { 1113 NULL, NULL, NULL, NULL, 1114 "avx-vnni", "avx512-bf16", NULL, "cmpccxadd", 1115 NULL, NULL, "fzrm", "fsrs", 1116 "fsrc", NULL, NULL, NULL, 1117 NULL, NULL, NULL, NULL, 1118 NULL, "amx-fp16", NULL, "avx-ifma", 1119 NULL, NULL, "lam", NULL, 1120 NULL, NULL, NULL, NULL, 1121 }, 1122 .cpuid = { 1123 .eax = 7, 1124 .needs_ecx = true, .ecx = 1, 1125 .reg = R_EAX, 1126 }, 1127 .tcg_features = TCG_7_1_EAX_FEATURES, 1128 }, 1129 [FEAT_7_1_EDX] = { 1130 .type = CPUID_FEATURE_WORD, 1131 .feat_names = { 1132 NULL, NULL, NULL, NULL, 1133 "avx-vnni-int8", "avx-ne-convert", NULL, NULL, 1134 "amx-complex", NULL, NULL, NULL, 1135 NULL, NULL, "prefetchiti", NULL, 1136 NULL, NULL, NULL, NULL, 1137 NULL, NULL, NULL, NULL, 1138 NULL, NULL, NULL, NULL, 1139 NULL, NULL, NULL, NULL, 1140 }, 1141 .cpuid = { 1142 .eax = 7, 1143 .needs_ecx = true, .ecx = 1, 1144 .reg = R_EDX, 1145 }, 1146 .tcg_features = TCG_7_1_EDX_FEATURES, 1147 }, 1148 [FEAT_7_2_EDX] = { 1149 .type = CPUID_FEATURE_WORD, 1150 .feat_names = { 1151 NULL, NULL, NULL, NULL, 1152 NULL, "mcdt-no", NULL, NULL, 1153 NULL, NULL, NULL, NULL, 1154 NULL, NULL, NULL, NULL, 1155 NULL, NULL, NULL, NULL, 1156 NULL, NULL, NULL, NULL, 1157 NULL, NULL, NULL, NULL, 1158 NULL, NULL, NULL, NULL, 1159 }, 1160 .cpuid = { 1161 .eax = 7, 1162 .needs_ecx = true, .ecx = 2, 1163 .reg = R_EDX, 1164 }, 1165 .tcg_features = TCG_7_2_EDX_FEATURES, 1166 }, 1167 [FEAT_8000_0007_EDX] = { 1168 .type = CPUID_FEATURE_WORD, 1169 .feat_names = { 1170 NULL, NULL, NULL, NULL, 1171 NULL, NULL, NULL, NULL, 1172 "invtsc", NULL, NULL, NULL, 1173 NULL, NULL, NULL, NULL, 1174 NULL, NULL, NULL, NULL, 1175 NULL, NULL, NULL, NULL, 1176 NULL, NULL, NULL, NULL, 1177 NULL, NULL, NULL, NULL, 1178 }, 1179 .cpuid = { .eax = 0x80000007, .reg = R_EDX, }, 1180 .tcg_features = TCG_APM_FEATURES, 1181 .unmigratable_flags = CPUID_APM_INVTSC, 1182 }, 1183 [FEAT_8000_0008_EBX] = { 1184 .type = CPUID_FEATURE_WORD, 1185 .feat_names = { 1186 "clzero", NULL, "xsaveerptr", NULL, 1187 NULL, NULL, NULL, NULL, 1188 NULL, "wbnoinvd", NULL, NULL, 1189 "ibpb", NULL, "ibrs", "amd-stibp", 1190 NULL, "stibp-always-on", NULL, NULL, 1191 NULL, NULL, NULL, NULL, 1192 "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL, 1193 "amd-psfd", NULL, NULL, NULL, 1194 }, 1195 .cpuid = { .eax = 0x80000008, .reg = R_EBX, }, 1196 .tcg_features = TCG_8000_0008_EBX, 1197 .unmigratable_flags = 0, 1198 }, 1199 [FEAT_8000_0021_EAX] = { 1200 .type = CPUID_FEATURE_WORD, 1201 .feat_names = { 1202 "no-nested-data-bp", NULL, "lfence-always-serializing", NULL, 1203 NULL, NULL, "null-sel-clr-base", NULL, 1204 "auto-ibrs", NULL, NULL, NULL, 1205 NULL, NULL, NULL, NULL, 1206 NULL, NULL, NULL, NULL, 1207 NULL, NULL, NULL, NULL, 1208 NULL, NULL, NULL, NULL, 1209 NULL, NULL, NULL, NULL, 1210 }, 1211 .cpuid = { .eax = 0x80000021, .reg = R_EAX, }, 1212 .tcg_features = 0, 1213 .unmigratable_flags = 0, 1214 }, 1215 [FEAT_XSAVE] = { 1216 .type = CPUID_FEATURE_WORD, 1217 .feat_names = { 1218 "xsaveopt", "xsavec", "xgetbv1", "xsaves", 1219 "xfd", NULL, NULL, NULL, 1220 NULL, NULL, NULL, NULL, 1221 NULL, NULL, NULL, NULL, 1222 NULL, NULL, NULL, NULL, 1223 NULL, NULL, NULL, NULL, 1224 NULL, NULL, NULL, NULL, 1225 NULL, NULL, NULL, NULL, 1226 }, 1227 .cpuid = { 1228 .eax = 0xd, 1229 .needs_ecx = true, .ecx = 1, 1230 .reg = R_EAX, 1231 }, 1232 .tcg_features = TCG_XSAVE_FEATURES, 1233 }, 1234 [FEAT_XSAVE_XSS_LO] = { 1235 .type = CPUID_FEATURE_WORD, 1236 .feat_names = { 1237 NULL, NULL, NULL, NULL, 1238 NULL, NULL, NULL, NULL, 1239 NULL, NULL, NULL, NULL, 1240 NULL, NULL, NULL, NULL, 1241 NULL, NULL, NULL, NULL, 1242 NULL, NULL, NULL, NULL, 1243 NULL, NULL, NULL, NULL, 1244 NULL, NULL, NULL, NULL, 1245 }, 1246 .cpuid = { 1247 .eax = 0xD, 1248 .needs_ecx = true, 1249 .ecx = 1, 1250 .reg = R_ECX, 1251 }, 1252 }, 1253 [FEAT_XSAVE_XSS_HI] = { 1254 .type = CPUID_FEATURE_WORD, 1255 .cpuid = { 1256 .eax = 0xD, 1257 .needs_ecx = true, 1258 .ecx = 1, 1259 .reg = R_EDX 1260 }, 1261 }, 1262 [FEAT_6_EAX] = { 1263 .type = CPUID_FEATURE_WORD, 1264 .feat_names = { 1265 NULL, NULL, "arat", NULL, 1266 NULL, NULL, NULL, NULL, 1267 NULL, NULL, NULL, NULL, 1268 NULL, NULL, NULL, NULL, 1269 NULL, NULL, NULL, NULL, 1270 NULL, NULL, NULL, NULL, 1271 NULL, NULL, NULL, NULL, 1272 NULL, NULL, NULL, NULL, 1273 }, 1274 .cpuid = { .eax = 6, .reg = R_EAX, }, 1275 .tcg_features = TCG_6_EAX_FEATURES, 1276 }, 1277 [FEAT_XSAVE_XCR0_LO] = { 1278 .type = CPUID_FEATURE_WORD, 1279 .cpuid = { 1280 .eax = 0xD, 1281 .needs_ecx = true, .ecx = 0, 1282 .reg = R_EAX, 1283 }, 1284 .tcg_features = ~0U, 1285 .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK | 1286 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK | 1287 XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK | 1288 XSTATE_PKRU_MASK, 1289 }, 1290 [FEAT_XSAVE_XCR0_HI] = { 1291 .type = CPUID_FEATURE_WORD, 1292 .cpuid = { 1293 .eax = 0xD, 1294 .needs_ecx = true, .ecx = 0, 1295 .reg = R_EDX, 1296 }, 1297 .tcg_features = ~0U, 1298 }, 1299 /*Below are MSR exposed features*/ 1300 [FEAT_ARCH_CAPABILITIES] = { 1301 .type = MSR_FEATURE_WORD, 1302 .feat_names = { 1303 "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry", 1304 "ssb-no", "mds-no", "pschange-mc-no", "tsx-ctrl", 1305 "taa-no", NULL, NULL, NULL, 1306 NULL, "sbdr-ssdp-no", "fbsdp-no", "psdp-no", 1307 NULL, "fb-clear", NULL, NULL, 1308 NULL, NULL, NULL, NULL, 1309 "pbrsb-no", NULL, "gds-no", "rfds-no", 1310 "rfds-clear", NULL, NULL, NULL, 1311 }, 1312 .msr = { 1313 .index = MSR_IA32_ARCH_CAPABILITIES, 1314 }, 1315 /* 1316 * FEAT_ARCH_CAPABILITIES only affects a read-only MSR, which 1317 * cannot be read from user mode. Therefore, it has no impact 1318 > on any user-mode operation, and warnings about unsupported 1319 * features do not matter. 1320 */ 1321 .tcg_features = ~0U, 1322 }, 1323 [FEAT_CORE_CAPABILITY] = { 1324 .type = MSR_FEATURE_WORD, 1325 .feat_names = { 1326 NULL, NULL, NULL, NULL, 1327 NULL, "split-lock-detect", NULL, NULL, 1328 NULL, NULL, NULL, NULL, 1329 NULL, NULL, NULL, NULL, 1330 NULL, NULL, NULL, NULL, 1331 NULL, NULL, NULL, NULL, 1332 NULL, NULL, NULL, NULL, 1333 NULL, NULL, NULL, NULL, 1334 }, 1335 .msr = { 1336 .index = MSR_IA32_CORE_CAPABILITY, 1337 }, 1338 }, 1339 [FEAT_PERF_CAPABILITIES] = { 1340 .type = MSR_FEATURE_WORD, 1341 .feat_names = { 1342 NULL, NULL, NULL, NULL, 1343 NULL, NULL, NULL, NULL, 1344 NULL, NULL, NULL, NULL, 1345 NULL, "full-width-write", NULL, NULL, 1346 NULL, NULL, NULL, NULL, 1347 NULL, NULL, NULL, NULL, 1348 NULL, NULL, NULL, NULL, 1349 NULL, NULL, NULL, NULL, 1350 }, 1351 .msr = { 1352 .index = MSR_IA32_PERF_CAPABILITIES, 1353 }, 1354 }, 1355 1356 [FEAT_VMX_PROCBASED_CTLS] = { 1357 .type = MSR_FEATURE_WORD, 1358 .feat_names = { 1359 NULL, NULL, "vmx-vintr-pending", "vmx-tsc-offset", 1360 NULL, NULL, NULL, "vmx-hlt-exit", 1361 NULL, "vmx-invlpg-exit", "vmx-mwait-exit", "vmx-rdpmc-exit", 1362 "vmx-rdtsc-exit", NULL, NULL, "vmx-cr3-load-noexit", 1363 "vmx-cr3-store-noexit", NULL, NULL, "vmx-cr8-load-exit", 1364 "vmx-cr8-store-exit", "vmx-flexpriority", "vmx-vnmi-pending", "vmx-movdr-exit", 1365 "vmx-io-exit", "vmx-io-bitmap", NULL, "vmx-mtf", 1366 "vmx-msr-bitmap", "vmx-monitor-exit", "vmx-pause-exit", "vmx-secondary-ctls", 1367 }, 1368 .msr = { 1369 .index = MSR_IA32_VMX_TRUE_PROCBASED_CTLS, 1370 } 1371 }, 1372 1373 [FEAT_VMX_SECONDARY_CTLS] = { 1374 .type = MSR_FEATURE_WORD, 1375 .feat_names = { 1376 "vmx-apicv-xapic", "vmx-ept", "vmx-desc-exit", "vmx-rdtscp-exit", 1377 "vmx-apicv-x2apic", "vmx-vpid", "vmx-wbinvd-exit", "vmx-unrestricted-guest", 1378 "vmx-apicv-register", "vmx-apicv-vid", "vmx-ple", "vmx-rdrand-exit", 1379 "vmx-invpcid-exit", "vmx-vmfunc", "vmx-shadow-vmcs", "vmx-encls-exit", 1380 "vmx-rdseed-exit", "vmx-pml", NULL, NULL, 1381 "vmx-xsaves", NULL, NULL, NULL, 1382 NULL, "vmx-tsc-scaling", "vmx-enable-user-wait-pause", NULL, 1383 NULL, NULL, NULL, NULL, 1384 }, 1385 .msr = { 1386 .index = MSR_IA32_VMX_PROCBASED_CTLS2, 1387 } 1388 }, 1389 1390 [FEAT_VMX_PINBASED_CTLS] = { 1391 .type = MSR_FEATURE_WORD, 1392 .feat_names = { 1393 "vmx-intr-exit", NULL, NULL, "vmx-nmi-exit", 1394 NULL, "vmx-vnmi", "vmx-preemption-timer", "vmx-posted-intr", 1395 NULL, NULL, NULL, NULL, 1396 NULL, NULL, NULL, NULL, 1397 NULL, NULL, NULL, NULL, 1398 NULL, NULL, NULL, NULL, 1399 NULL, NULL, NULL, NULL, 1400 NULL, NULL, NULL, NULL, 1401 }, 1402 .msr = { 1403 .index = MSR_IA32_VMX_TRUE_PINBASED_CTLS, 1404 } 1405 }, 1406 1407 [FEAT_VMX_EXIT_CTLS] = { 1408 .type = MSR_FEATURE_WORD, 1409 /* 1410 * VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE is copied from 1411 * the LM CPUID bit. 1412 */ 1413 .feat_names = { 1414 NULL, NULL, "vmx-exit-nosave-debugctl", NULL, 1415 NULL, NULL, NULL, NULL, 1416 NULL, NULL /* vmx-exit-host-addr-space-size */, NULL, NULL, 1417 "vmx-exit-load-perf-global-ctrl", NULL, NULL, "vmx-exit-ack-intr", 1418 NULL, NULL, "vmx-exit-save-pat", "vmx-exit-load-pat", 1419 "vmx-exit-save-efer", "vmx-exit-load-efer", 1420 "vmx-exit-save-preemption-timer", "vmx-exit-clear-bndcfgs", 1421 NULL, "vmx-exit-clear-rtit-ctl", NULL, NULL, 1422 NULL, "vmx-exit-load-pkrs", NULL, NULL, 1423 }, 1424 .msr = { 1425 .index = MSR_IA32_VMX_TRUE_EXIT_CTLS, 1426 } 1427 }, 1428 1429 [FEAT_VMX_ENTRY_CTLS] = { 1430 .type = MSR_FEATURE_WORD, 1431 .feat_names = { 1432 NULL, NULL, "vmx-entry-noload-debugctl", NULL, 1433 NULL, NULL, NULL, NULL, 1434 NULL, "vmx-entry-ia32e-mode", NULL, NULL, 1435 NULL, "vmx-entry-load-perf-global-ctrl", "vmx-entry-load-pat", "vmx-entry-load-efer", 1436 "vmx-entry-load-bndcfgs", NULL, "vmx-entry-load-rtit-ctl", NULL, 1437 NULL, NULL, "vmx-entry-load-pkrs", NULL, 1438 NULL, NULL, NULL, NULL, 1439 NULL, NULL, NULL, NULL, 1440 }, 1441 .msr = { 1442 .index = MSR_IA32_VMX_TRUE_ENTRY_CTLS, 1443 } 1444 }, 1445 1446 [FEAT_VMX_MISC] = { 1447 .type = MSR_FEATURE_WORD, 1448 .feat_names = { 1449 NULL, NULL, NULL, NULL, 1450 NULL, "vmx-store-lma", "vmx-activity-hlt", "vmx-activity-shutdown", 1451 "vmx-activity-wait-sipi", NULL, NULL, NULL, 1452 NULL, NULL, NULL, NULL, 1453 NULL, NULL, NULL, NULL, 1454 NULL, NULL, NULL, NULL, 1455 NULL, NULL, NULL, NULL, 1456 NULL, "vmx-vmwrite-vmexit-fields", "vmx-zero-len-inject", NULL, 1457 }, 1458 .msr = { 1459 .index = MSR_IA32_VMX_MISC, 1460 } 1461 }, 1462 1463 [FEAT_VMX_EPT_VPID_CAPS] = { 1464 .type = MSR_FEATURE_WORD, 1465 .feat_names = { 1466 "vmx-ept-execonly", NULL, NULL, NULL, 1467 NULL, NULL, "vmx-page-walk-4", "vmx-page-walk-5", 1468 NULL, NULL, NULL, NULL, 1469 NULL, NULL, NULL, NULL, 1470 "vmx-ept-2mb", "vmx-ept-1gb", NULL, NULL, 1471 "vmx-invept", "vmx-eptad", "vmx-ept-advanced-exitinfo", NULL, 1472 NULL, "vmx-invept-single-context", "vmx-invept-all-context", NULL, 1473 NULL, NULL, NULL, NULL, 1474 "vmx-invvpid", NULL, NULL, NULL, 1475 NULL, NULL, NULL, NULL, 1476 "vmx-invvpid-single-addr", "vmx-invept-single-context", 1477 "vmx-invvpid-all-context", "vmx-invept-single-context-noglobals", 1478 NULL, NULL, NULL, NULL, 1479 NULL, NULL, NULL, NULL, 1480 NULL, NULL, NULL, NULL, 1481 NULL, NULL, NULL, NULL, 1482 NULL, NULL, NULL, NULL, 1483 }, 1484 .msr = { 1485 .index = MSR_IA32_VMX_EPT_VPID_CAP, 1486 } 1487 }, 1488 1489 [FEAT_VMX_BASIC] = { 1490 .type = MSR_FEATURE_WORD, 1491 .feat_names = { 1492 [54] = "vmx-ins-outs", 1493 [55] = "vmx-true-ctls", 1494 [56] = "vmx-any-errcode", 1495 }, 1496 .msr = { 1497 .index = MSR_IA32_VMX_BASIC, 1498 }, 1499 /* Just to be safe - we don't support setting the MSEG version field. */ 1500 .no_autoenable_flags = MSR_VMX_BASIC_DUAL_MONITOR, 1501 }, 1502 1503 [FEAT_VMX_VMFUNC] = { 1504 .type = MSR_FEATURE_WORD, 1505 .feat_names = { 1506 [0] = "vmx-eptp-switching", 1507 }, 1508 .msr = { 1509 .index = MSR_IA32_VMX_VMFUNC, 1510 } 1511 }, 1512 1513 [FEAT_14_0_ECX] = { 1514 .type = CPUID_FEATURE_WORD, 1515 .feat_names = { 1516 NULL, NULL, NULL, NULL, 1517 NULL, NULL, NULL, NULL, 1518 NULL, NULL, NULL, NULL, 1519 NULL, NULL, NULL, NULL, 1520 NULL, NULL, NULL, NULL, 1521 NULL, NULL, NULL, NULL, 1522 NULL, NULL, NULL, NULL, 1523 NULL, NULL, NULL, "intel-pt-lip", 1524 }, 1525 .cpuid = { 1526 .eax = 0x14, 1527 .needs_ecx = true, .ecx = 0, 1528 .reg = R_ECX, 1529 }, 1530 .tcg_features = TCG_14_0_ECX_FEATURES, 1531 }, 1532 1533 [FEAT_SGX_12_0_EAX] = { 1534 .type = CPUID_FEATURE_WORD, 1535 .feat_names = { 1536 "sgx1", "sgx2", NULL, NULL, 1537 NULL, NULL, NULL, NULL, 1538 NULL, NULL, NULL, "sgx-edeccssa", 1539 NULL, NULL, NULL, NULL, 1540 NULL, NULL, NULL, NULL, 1541 NULL, NULL, NULL, NULL, 1542 NULL, NULL, NULL, NULL, 1543 NULL, NULL, NULL, NULL, 1544 }, 1545 .cpuid = { 1546 .eax = 0x12, 1547 .needs_ecx = true, .ecx = 0, 1548 .reg = R_EAX, 1549 }, 1550 .tcg_features = TCG_SGX_12_0_EAX_FEATURES, 1551 }, 1552 1553 [FEAT_SGX_12_0_EBX] = { 1554 .type = CPUID_FEATURE_WORD, 1555 .feat_names = { 1556 "sgx-exinfo" , NULL, NULL, NULL, 1557 NULL, NULL, NULL, NULL, 1558 NULL, NULL, NULL, NULL, 1559 NULL, NULL, NULL, NULL, 1560 NULL, NULL, NULL, NULL, 1561 NULL, NULL, NULL, NULL, 1562 NULL, NULL, NULL, NULL, 1563 NULL, NULL, NULL, NULL, 1564 }, 1565 .cpuid = { 1566 .eax = 0x12, 1567 .needs_ecx = true, .ecx = 0, 1568 .reg = R_EBX, 1569 }, 1570 .tcg_features = TCG_SGX_12_0_EBX_FEATURES, 1571 }, 1572 1573 [FEAT_SGX_12_1_EAX] = { 1574 .type = CPUID_FEATURE_WORD, 1575 .feat_names = { 1576 NULL, "sgx-debug", "sgx-mode64", NULL, 1577 "sgx-provisionkey", "sgx-tokenkey", NULL, "sgx-kss", 1578 NULL, NULL, "sgx-aex-notify", NULL, 1579 NULL, NULL, NULL, NULL, 1580 NULL, NULL, NULL, NULL, 1581 NULL, NULL, NULL, NULL, 1582 NULL, NULL, NULL, NULL, 1583 NULL, NULL, NULL, NULL, 1584 }, 1585 .cpuid = { 1586 .eax = 0x12, 1587 .needs_ecx = true, .ecx = 1, 1588 .reg = R_EAX, 1589 }, 1590 .tcg_features = TCG_SGX_12_1_EAX_FEATURES, 1591 }, 1592 }; 1593 1594 typedef struct FeatureMask { 1595 FeatureWord index; 1596 uint64_t mask; 1597 } FeatureMask; 1598 1599 typedef struct FeatureDep { 1600 FeatureMask from, to; 1601 } FeatureDep; 1602 1603 static FeatureDep feature_dependencies[] = { 1604 { 1605 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_ARCH_CAPABILITIES }, 1606 .to = { FEAT_ARCH_CAPABILITIES, ~0ull }, 1607 }, 1608 { 1609 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_CORE_CAPABILITY }, 1610 .to = { FEAT_CORE_CAPABILITY, ~0ull }, 1611 }, 1612 { 1613 .from = { FEAT_1_ECX, CPUID_EXT_PDCM }, 1614 .to = { FEAT_PERF_CAPABILITIES, ~0ull }, 1615 }, 1616 { 1617 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1618 .to = { FEAT_VMX_PROCBASED_CTLS, ~0ull }, 1619 }, 1620 { 1621 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1622 .to = { FEAT_VMX_PINBASED_CTLS, ~0ull }, 1623 }, 1624 { 1625 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1626 .to = { FEAT_VMX_EXIT_CTLS, ~0ull }, 1627 }, 1628 { 1629 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1630 .to = { FEAT_VMX_ENTRY_CTLS, ~0ull }, 1631 }, 1632 { 1633 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1634 .to = { FEAT_VMX_MISC, ~0ull }, 1635 }, 1636 { 1637 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1638 .to = { FEAT_VMX_BASIC, ~0ull }, 1639 }, 1640 { 1641 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_LM }, 1642 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_IA32E_MODE }, 1643 }, 1644 { 1645 .from = { FEAT_VMX_PROCBASED_CTLS, VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS }, 1646 .to = { FEAT_VMX_SECONDARY_CTLS, ~0ull }, 1647 }, 1648 { 1649 .from = { FEAT_XSAVE, CPUID_XSAVE_XSAVES }, 1650 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_XSAVES }, 1651 }, 1652 { 1653 .from = { FEAT_1_ECX, CPUID_EXT_RDRAND }, 1654 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDRAND_EXITING }, 1655 }, 1656 { 1657 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INVPCID }, 1658 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_INVPCID }, 1659 }, 1660 { 1661 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_MPX }, 1662 .to = { FEAT_VMX_EXIT_CTLS, VMX_VM_EXIT_CLEAR_BNDCFGS }, 1663 }, 1664 { 1665 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_MPX }, 1666 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_LOAD_BNDCFGS }, 1667 }, 1668 { 1669 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_RDSEED }, 1670 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDSEED_EXITING }, 1671 }, 1672 { 1673 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT }, 1674 .to = { FEAT_14_0_ECX, ~0ull }, 1675 }, 1676 { 1677 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_RDTSCP }, 1678 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDTSCP }, 1679 }, 1680 { 1681 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT }, 1682 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull }, 1683 }, 1684 { 1685 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT }, 1686 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST }, 1687 }, 1688 { 1689 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VPID }, 1690 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull << 32 }, 1691 }, 1692 { 1693 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VMFUNC }, 1694 .to = { FEAT_VMX_VMFUNC, ~0ull }, 1695 }, 1696 { 1697 .from = { FEAT_8000_0001_ECX, CPUID_EXT3_SVM }, 1698 .to = { FEAT_SVM, ~0ull }, 1699 }, 1700 { 1701 .from = { FEAT_7_0_ECX, CPUID_7_0_ECX_WAITPKG }, 1702 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_USER_WAIT_PAUSE }, 1703 }, 1704 }; 1705 1706 typedef struct X86RegisterInfo32 { 1707 /* Name of register */ 1708 const char *name; 1709 /* QAPI enum value register */ 1710 X86CPURegister32 qapi_enum; 1711 } X86RegisterInfo32; 1712 1713 #define REGISTER(reg) \ 1714 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg } 1715 static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = { 1716 REGISTER(EAX), 1717 REGISTER(ECX), 1718 REGISTER(EDX), 1719 REGISTER(EBX), 1720 REGISTER(ESP), 1721 REGISTER(EBP), 1722 REGISTER(ESI), 1723 REGISTER(EDI), 1724 }; 1725 #undef REGISTER 1726 1727 /* CPUID feature bits available in XSS */ 1728 #define CPUID_XSTATE_XSS_MASK (XSTATE_ARCH_LBR_MASK) 1729 1730 ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUNT] = { 1731 [XSTATE_FP_BIT] = { 1732 /* x87 FP state component is always enabled if XSAVE is supported */ 1733 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE, 1734 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader), 1735 }, 1736 [XSTATE_SSE_BIT] = { 1737 /* SSE state component is always enabled if XSAVE is supported */ 1738 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE, 1739 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader), 1740 }, 1741 [XSTATE_YMM_BIT] = 1742 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX, 1743 .size = sizeof(XSaveAVX) }, 1744 [XSTATE_BNDREGS_BIT] = 1745 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX, 1746 .size = sizeof(XSaveBNDREG) }, 1747 [XSTATE_BNDCSR_BIT] = 1748 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX, 1749 .size = sizeof(XSaveBNDCSR) }, 1750 [XSTATE_OPMASK_BIT] = 1751 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1752 .size = sizeof(XSaveOpmask) }, 1753 [XSTATE_ZMM_Hi256_BIT] = 1754 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1755 .size = sizeof(XSaveZMM_Hi256) }, 1756 [XSTATE_Hi16_ZMM_BIT] = 1757 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1758 .size = sizeof(XSaveHi16_ZMM) }, 1759 [XSTATE_PKRU_BIT] = 1760 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU, 1761 .size = sizeof(XSavePKRU) }, 1762 [XSTATE_ARCH_LBR_BIT] = { 1763 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_ARCH_LBR, 1764 .offset = 0 /*supervisor mode component, offset = 0 */, 1765 .size = sizeof(XSavesArchLBR) }, 1766 [XSTATE_XTILE_CFG_BIT] = { 1767 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_AMX_TILE, 1768 .size = sizeof(XSaveXTILECFG), 1769 }, 1770 [XSTATE_XTILE_DATA_BIT] = { 1771 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_AMX_TILE, 1772 .size = sizeof(XSaveXTILEDATA) 1773 }, 1774 }; 1775 1776 uint32_t xsave_area_size(uint64_t mask, bool compacted) 1777 { 1778 uint64_t ret = x86_ext_save_areas[0].size; 1779 const ExtSaveArea *esa; 1780 uint32_t offset = 0; 1781 int i; 1782 1783 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 1784 esa = &x86_ext_save_areas[i]; 1785 if ((mask >> i) & 1) { 1786 offset = compacted ? ret : esa->offset; 1787 ret = MAX(ret, offset + esa->size); 1788 } 1789 } 1790 return ret; 1791 } 1792 1793 static inline bool accel_uses_host_cpuid(void) 1794 { 1795 return kvm_enabled() || hvf_enabled(); 1796 } 1797 1798 static inline uint64_t x86_cpu_xsave_xcr0_components(X86CPU *cpu) 1799 { 1800 return ((uint64_t)cpu->env.features[FEAT_XSAVE_XCR0_HI]) << 32 | 1801 cpu->env.features[FEAT_XSAVE_XCR0_LO]; 1802 } 1803 1804 /* Return name of 32-bit register, from a R_* constant */ 1805 static const char *get_register_name_32(unsigned int reg) 1806 { 1807 if (reg >= CPU_NB_REGS32) { 1808 return NULL; 1809 } 1810 return x86_reg_info_32[reg].name; 1811 } 1812 1813 static inline uint64_t x86_cpu_xsave_xss_components(X86CPU *cpu) 1814 { 1815 return ((uint64_t)cpu->env.features[FEAT_XSAVE_XSS_HI]) << 32 | 1816 cpu->env.features[FEAT_XSAVE_XSS_LO]; 1817 } 1818 1819 /* 1820 * Returns the set of feature flags that are supported and migratable by 1821 * QEMU, for a given FeatureWord. 1822 */ 1823 static uint64_t x86_cpu_get_migratable_flags(FeatureWord w) 1824 { 1825 FeatureWordInfo *wi = &feature_word_info[w]; 1826 uint64_t r = 0; 1827 int i; 1828 1829 for (i = 0; i < 64; i++) { 1830 uint64_t f = 1ULL << i; 1831 1832 /* If the feature name is known, it is implicitly considered migratable, 1833 * unless it is explicitly set in unmigratable_flags */ 1834 if ((wi->migratable_flags & f) || 1835 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) { 1836 r |= f; 1837 } 1838 } 1839 return r; 1840 } 1841 1842 void host_cpuid(uint32_t function, uint32_t count, 1843 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) 1844 { 1845 uint32_t vec[4]; 1846 1847 #ifdef __x86_64__ 1848 asm volatile("cpuid" 1849 : "=a"(vec[0]), "=b"(vec[1]), 1850 "=c"(vec[2]), "=d"(vec[3]) 1851 : "0"(function), "c"(count) : "cc"); 1852 #elif defined(__i386__) 1853 asm volatile("pusha \n\t" 1854 "cpuid \n\t" 1855 "mov %%eax, 0(%2) \n\t" 1856 "mov %%ebx, 4(%2) \n\t" 1857 "mov %%ecx, 8(%2) \n\t" 1858 "mov %%edx, 12(%2) \n\t" 1859 "popa" 1860 : : "a"(function), "c"(count), "S"(vec) 1861 : "memory", "cc"); 1862 #else 1863 abort(); 1864 #endif 1865 1866 if (eax) 1867 *eax = vec[0]; 1868 if (ebx) 1869 *ebx = vec[1]; 1870 if (ecx) 1871 *ecx = vec[2]; 1872 if (edx) 1873 *edx = vec[3]; 1874 } 1875 1876 /* CPU class name definitions: */ 1877 1878 /* Return type name for a given CPU model name 1879 * Caller is responsible for freeing the returned string. 1880 */ 1881 static char *x86_cpu_type_name(const char *model_name) 1882 { 1883 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name); 1884 } 1885 1886 static ObjectClass *x86_cpu_class_by_name(const char *cpu_model) 1887 { 1888 g_autofree char *typename = x86_cpu_type_name(cpu_model); 1889 return object_class_by_name(typename); 1890 } 1891 1892 static char *x86_cpu_class_get_model_name(X86CPUClass *cc) 1893 { 1894 const char *class_name = object_class_get_name(OBJECT_CLASS(cc)); 1895 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX)); 1896 return cpu_model_from_type(class_name); 1897 } 1898 1899 typedef struct X86CPUVersionDefinition { 1900 X86CPUVersion version; 1901 const char *alias; 1902 const char *note; 1903 PropValue *props; 1904 const CPUCaches *const cache_info; 1905 } X86CPUVersionDefinition; 1906 1907 /* Base definition for a CPU model */ 1908 typedef struct X86CPUDefinition { 1909 const char *name; 1910 uint32_t level; 1911 uint32_t xlevel; 1912 /* vendor is zero-terminated, 12 character ASCII string */ 1913 char vendor[CPUID_VENDOR_SZ + 1]; 1914 int family; 1915 int model; 1916 int stepping; 1917 FeatureWordArray features; 1918 const char *model_id; 1919 const CPUCaches *const cache_info; 1920 /* 1921 * Definitions for alternative versions of CPU model. 1922 * List is terminated by item with version == 0. 1923 * If NULL, version 1 will be registered automatically. 1924 */ 1925 const X86CPUVersionDefinition *versions; 1926 const char *deprecation_note; 1927 } X86CPUDefinition; 1928 1929 /* Reference to a specific CPU model version */ 1930 struct X86CPUModel { 1931 /* Base CPU definition */ 1932 const X86CPUDefinition *cpudef; 1933 /* CPU model version */ 1934 X86CPUVersion version; 1935 const char *note; 1936 /* 1937 * If true, this is an alias CPU model. 1938 * This matters only for "-cpu help" and query-cpu-definitions 1939 */ 1940 bool is_alias; 1941 }; 1942 1943 /* Get full model name for CPU version */ 1944 static char *x86_cpu_versioned_model_name(const X86CPUDefinition *cpudef, 1945 X86CPUVersion version) 1946 { 1947 assert(version > 0); 1948 return g_strdup_printf("%s-v%d", cpudef->name, (int)version); 1949 } 1950 1951 static const X86CPUVersionDefinition * 1952 x86_cpu_def_get_versions(const X86CPUDefinition *def) 1953 { 1954 /* When X86CPUDefinition::versions is NULL, we register only v1 */ 1955 static const X86CPUVersionDefinition default_version_list[] = { 1956 { 1 }, 1957 { /* end of list */ } 1958 }; 1959 1960 return def->versions ?: default_version_list; 1961 } 1962 1963 static const CPUCaches epyc_cache_info = { 1964 .l1d_cache = &(CPUCacheInfo) { 1965 .type = DATA_CACHE, 1966 .level = 1, 1967 .size = 32 * KiB, 1968 .line_size = 64, 1969 .associativity = 8, 1970 .partitions = 1, 1971 .sets = 64, 1972 .lines_per_tag = 1, 1973 .self_init = 1, 1974 .no_invd_sharing = true, 1975 .share_level = CPU_TOPO_LEVEL_CORE, 1976 }, 1977 .l1i_cache = &(CPUCacheInfo) { 1978 .type = INSTRUCTION_CACHE, 1979 .level = 1, 1980 .size = 64 * KiB, 1981 .line_size = 64, 1982 .associativity = 4, 1983 .partitions = 1, 1984 .sets = 256, 1985 .lines_per_tag = 1, 1986 .self_init = 1, 1987 .no_invd_sharing = true, 1988 .share_level = CPU_TOPO_LEVEL_CORE, 1989 }, 1990 .l2_cache = &(CPUCacheInfo) { 1991 .type = UNIFIED_CACHE, 1992 .level = 2, 1993 .size = 512 * KiB, 1994 .line_size = 64, 1995 .associativity = 8, 1996 .partitions = 1, 1997 .sets = 1024, 1998 .lines_per_tag = 1, 1999 .share_level = CPU_TOPO_LEVEL_CORE, 2000 }, 2001 .l3_cache = &(CPUCacheInfo) { 2002 .type = UNIFIED_CACHE, 2003 .level = 3, 2004 .size = 8 * MiB, 2005 .line_size = 64, 2006 .associativity = 16, 2007 .partitions = 1, 2008 .sets = 8192, 2009 .lines_per_tag = 1, 2010 .self_init = true, 2011 .inclusive = true, 2012 .complex_indexing = true, 2013 .share_level = CPU_TOPO_LEVEL_DIE, 2014 }, 2015 }; 2016 2017 static CPUCaches epyc_v4_cache_info = { 2018 .l1d_cache = &(CPUCacheInfo) { 2019 .type = DATA_CACHE, 2020 .level = 1, 2021 .size = 32 * KiB, 2022 .line_size = 64, 2023 .associativity = 8, 2024 .partitions = 1, 2025 .sets = 64, 2026 .lines_per_tag = 1, 2027 .self_init = 1, 2028 .no_invd_sharing = true, 2029 .share_level = CPU_TOPO_LEVEL_CORE, 2030 }, 2031 .l1i_cache = &(CPUCacheInfo) { 2032 .type = INSTRUCTION_CACHE, 2033 .level = 1, 2034 .size = 64 * KiB, 2035 .line_size = 64, 2036 .associativity = 4, 2037 .partitions = 1, 2038 .sets = 256, 2039 .lines_per_tag = 1, 2040 .self_init = 1, 2041 .no_invd_sharing = true, 2042 .share_level = CPU_TOPO_LEVEL_CORE, 2043 }, 2044 .l2_cache = &(CPUCacheInfo) { 2045 .type = UNIFIED_CACHE, 2046 .level = 2, 2047 .size = 512 * KiB, 2048 .line_size = 64, 2049 .associativity = 8, 2050 .partitions = 1, 2051 .sets = 1024, 2052 .lines_per_tag = 1, 2053 .share_level = CPU_TOPO_LEVEL_CORE, 2054 }, 2055 .l3_cache = &(CPUCacheInfo) { 2056 .type = UNIFIED_CACHE, 2057 .level = 3, 2058 .size = 8 * MiB, 2059 .line_size = 64, 2060 .associativity = 16, 2061 .partitions = 1, 2062 .sets = 8192, 2063 .lines_per_tag = 1, 2064 .self_init = true, 2065 .inclusive = true, 2066 .complex_indexing = false, 2067 .share_level = CPU_TOPO_LEVEL_DIE, 2068 }, 2069 }; 2070 2071 static const CPUCaches epyc_rome_cache_info = { 2072 .l1d_cache = &(CPUCacheInfo) { 2073 .type = DATA_CACHE, 2074 .level = 1, 2075 .size = 32 * KiB, 2076 .line_size = 64, 2077 .associativity = 8, 2078 .partitions = 1, 2079 .sets = 64, 2080 .lines_per_tag = 1, 2081 .self_init = 1, 2082 .no_invd_sharing = true, 2083 .share_level = CPU_TOPO_LEVEL_CORE, 2084 }, 2085 .l1i_cache = &(CPUCacheInfo) { 2086 .type = INSTRUCTION_CACHE, 2087 .level = 1, 2088 .size = 32 * KiB, 2089 .line_size = 64, 2090 .associativity = 8, 2091 .partitions = 1, 2092 .sets = 64, 2093 .lines_per_tag = 1, 2094 .self_init = 1, 2095 .no_invd_sharing = true, 2096 .share_level = CPU_TOPO_LEVEL_CORE, 2097 }, 2098 .l2_cache = &(CPUCacheInfo) { 2099 .type = UNIFIED_CACHE, 2100 .level = 2, 2101 .size = 512 * KiB, 2102 .line_size = 64, 2103 .associativity = 8, 2104 .partitions = 1, 2105 .sets = 1024, 2106 .lines_per_tag = 1, 2107 .share_level = CPU_TOPO_LEVEL_CORE, 2108 }, 2109 .l3_cache = &(CPUCacheInfo) { 2110 .type = UNIFIED_CACHE, 2111 .level = 3, 2112 .size = 16 * MiB, 2113 .line_size = 64, 2114 .associativity = 16, 2115 .partitions = 1, 2116 .sets = 16384, 2117 .lines_per_tag = 1, 2118 .self_init = true, 2119 .inclusive = true, 2120 .complex_indexing = true, 2121 .share_level = CPU_TOPO_LEVEL_DIE, 2122 }, 2123 }; 2124 2125 static const CPUCaches epyc_rome_v3_cache_info = { 2126 .l1d_cache = &(CPUCacheInfo) { 2127 .type = DATA_CACHE, 2128 .level = 1, 2129 .size = 32 * KiB, 2130 .line_size = 64, 2131 .associativity = 8, 2132 .partitions = 1, 2133 .sets = 64, 2134 .lines_per_tag = 1, 2135 .self_init = 1, 2136 .no_invd_sharing = true, 2137 .share_level = CPU_TOPO_LEVEL_CORE, 2138 }, 2139 .l1i_cache = &(CPUCacheInfo) { 2140 .type = INSTRUCTION_CACHE, 2141 .level = 1, 2142 .size = 32 * KiB, 2143 .line_size = 64, 2144 .associativity = 8, 2145 .partitions = 1, 2146 .sets = 64, 2147 .lines_per_tag = 1, 2148 .self_init = 1, 2149 .no_invd_sharing = true, 2150 .share_level = CPU_TOPO_LEVEL_CORE, 2151 }, 2152 .l2_cache = &(CPUCacheInfo) { 2153 .type = UNIFIED_CACHE, 2154 .level = 2, 2155 .size = 512 * KiB, 2156 .line_size = 64, 2157 .associativity = 8, 2158 .partitions = 1, 2159 .sets = 1024, 2160 .lines_per_tag = 1, 2161 .share_level = CPU_TOPO_LEVEL_CORE, 2162 }, 2163 .l3_cache = &(CPUCacheInfo) { 2164 .type = UNIFIED_CACHE, 2165 .level = 3, 2166 .size = 16 * MiB, 2167 .line_size = 64, 2168 .associativity = 16, 2169 .partitions = 1, 2170 .sets = 16384, 2171 .lines_per_tag = 1, 2172 .self_init = true, 2173 .inclusive = true, 2174 .complex_indexing = false, 2175 .share_level = CPU_TOPO_LEVEL_DIE, 2176 }, 2177 }; 2178 2179 static const CPUCaches epyc_milan_cache_info = { 2180 .l1d_cache = &(CPUCacheInfo) { 2181 .type = DATA_CACHE, 2182 .level = 1, 2183 .size = 32 * KiB, 2184 .line_size = 64, 2185 .associativity = 8, 2186 .partitions = 1, 2187 .sets = 64, 2188 .lines_per_tag = 1, 2189 .self_init = 1, 2190 .no_invd_sharing = true, 2191 .share_level = CPU_TOPO_LEVEL_CORE, 2192 }, 2193 .l1i_cache = &(CPUCacheInfo) { 2194 .type = INSTRUCTION_CACHE, 2195 .level = 1, 2196 .size = 32 * KiB, 2197 .line_size = 64, 2198 .associativity = 8, 2199 .partitions = 1, 2200 .sets = 64, 2201 .lines_per_tag = 1, 2202 .self_init = 1, 2203 .no_invd_sharing = true, 2204 .share_level = CPU_TOPO_LEVEL_CORE, 2205 }, 2206 .l2_cache = &(CPUCacheInfo) { 2207 .type = UNIFIED_CACHE, 2208 .level = 2, 2209 .size = 512 * KiB, 2210 .line_size = 64, 2211 .associativity = 8, 2212 .partitions = 1, 2213 .sets = 1024, 2214 .lines_per_tag = 1, 2215 .share_level = CPU_TOPO_LEVEL_CORE, 2216 }, 2217 .l3_cache = &(CPUCacheInfo) { 2218 .type = UNIFIED_CACHE, 2219 .level = 3, 2220 .size = 32 * MiB, 2221 .line_size = 64, 2222 .associativity = 16, 2223 .partitions = 1, 2224 .sets = 32768, 2225 .lines_per_tag = 1, 2226 .self_init = true, 2227 .inclusive = true, 2228 .complex_indexing = true, 2229 .share_level = CPU_TOPO_LEVEL_DIE, 2230 }, 2231 }; 2232 2233 static const CPUCaches epyc_milan_v2_cache_info = { 2234 .l1d_cache = &(CPUCacheInfo) { 2235 .type = DATA_CACHE, 2236 .level = 1, 2237 .size = 32 * KiB, 2238 .line_size = 64, 2239 .associativity = 8, 2240 .partitions = 1, 2241 .sets = 64, 2242 .lines_per_tag = 1, 2243 .self_init = 1, 2244 .no_invd_sharing = true, 2245 .share_level = CPU_TOPO_LEVEL_CORE, 2246 }, 2247 .l1i_cache = &(CPUCacheInfo) { 2248 .type = INSTRUCTION_CACHE, 2249 .level = 1, 2250 .size = 32 * KiB, 2251 .line_size = 64, 2252 .associativity = 8, 2253 .partitions = 1, 2254 .sets = 64, 2255 .lines_per_tag = 1, 2256 .self_init = 1, 2257 .no_invd_sharing = true, 2258 .share_level = CPU_TOPO_LEVEL_CORE, 2259 }, 2260 .l2_cache = &(CPUCacheInfo) { 2261 .type = UNIFIED_CACHE, 2262 .level = 2, 2263 .size = 512 * KiB, 2264 .line_size = 64, 2265 .associativity = 8, 2266 .partitions = 1, 2267 .sets = 1024, 2268 .lines_per_tag = 1, 2269 .share_level = CPU_TOPO_LEVEL_CORE, 2270 }, 2271 .l3_cache = &(CPUCacheInfo) { 2272 .type = UNIFIED_CACHE, 2273 .level = 3, 2274 .size = 32 * MiB, 2275 .line_size = 64, 2276 .associativity = 16, 2277 .partitions = 1, 2278 .sets = 32768, 2279 .lines_per_tag = 1, 2280 .self_init = true, 2281 .inclusive = true, 2282 .complex_indexing = false, 2283 .share_level = CPU_TOPO_LEVEL_DIE, 2284 }, 2285 }; 2286 2287 static const CPUCaches epyc_genoa_cache_info = { 2288 .l1d_cache = &(CPUCacheInfo) { 2289 .type = DATA_CACHE, 2290 .level = 1, 2291 .size = 32 * KiB, 2292 .line_size = 64, 2293 .associativity = 8, 2294 .partitions = 1, 2295 .sets = 64, 2296 .lines_per_tag = 1, 2297 .self_init = 1, 2298 .no_invd_sharing = true, 2299 .share_level = CPU_TOPO_LEVEL_CORE, 2300 }, 2301 .l1i_cache = &(CPUCacheInfo) { 2302 .type = INSTRUCTION_CACHE, 2303 .level = 1, 2304 .size = 32 * KiB, 2305 .line_size = 64, 2306 .associativity = 8, 2307 .partitions = 1, 2308 .sets = 64, 2309 .lines_per_tag = 1, 2310 .self_init = 1, 2311 .no_invd_sharing = true, 2312 .share_level = CPU_TOPO_LEVEL_CORE, 2313 }, 2314 .l2_cache = &(CPUCacheInfo) { 2315 .type = UNIFIED_CACHE, 2316 .level = 2, 2317 .size = 1 * MiB, 2318 .line_size = 64, 2319 .associativity = 8, 2320 .partitions = 1, 2321 .sets = 2048, 2322 .lines_per_tag = 1, 2323 .share_level = CPU_TOPO_LEVEL_CORE, 2324 }, 2325 .l3_cache = &(CPUCacheInfo) { 2326 .type = UNIFIED_CACHE, 2327 .level = 3, 2328 .size = 32 * MiB, 2329 .line_size = 64, 2330 .associativity = 16, 2331 .partitions = 1, 2332 .sets = 32768, 2333 .lines_per_tag = 1, 2334 .self_init = true, 2335 .inclusive = true, 2336 .complex_indexing = false, 2337 .share_level = CPU_TOPO_LEVEL_DIE, 2338 }, 2339 }; 2340 2341 /* The following VMX features are not supported by KVM and are left out in the 2342 * CPU definitions: 2343 * 2344 * Dual-monitor support (all processors) 2345 * Entry to SMM 2346 * Deactivate dual-monitor treatment 2347 * Number of CR3-target values 2348 * Shutdown activity state 2349 * Wait-for-SIPI activity state 2350 * PAUSE-loop exiting (Westmere and newer) 2351 * EPT-violation #VE (Broadwell and newer) 2352 * Inject event with insn length=0 (Skylake and newer) 2353 * Conceal non-root operation from PT 2354 * Conceal VM exits from PT 2355 * Conceal VM entries from PT 2356 * Enable ENCLS exiting 2357 * Mode-based execute control (XS/XU) 2358 * TSC scaling (Skylake Server and newer) 2359 * GPA translation for PT (IceLake and newer) 2360 * User wait and pause 2361 * ENCLV exiting 2362 * Load IA32_RTIT_CTL 2363 * Clear IA32_RTIT_CTL 2364 * Advanced VM-exit information for EPT violations 2365 * Sub-page write permissions 2366 * PT in VMX operation 2367 */ 2368 2369 static const X86CPUDefinition builtin_x86_defs[] = { 2370 { 2371 .name = "qemu64", 2372 .level = 0xd, 2373 .vendor = CPUID_VENDOR_AMD, 2374 .family = 15, 2375 .model = 107, 2376 .stepping = 1, 2377 .features[FEAT_1_EDX] = 2378 PPRO_FEATURES | 2379 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2380 CPUID_PSE36, 2381 .features[FEAT_1_ECX] = 2382 CPUID_EXT_SSE3 | CPUID_EXT_CX16, 2383 .features[FEAT_8000_0001_EDX] = 2384 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2385 .features[FEAT_8000_0001_ECX] = 2386 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM, 2387 .xlevel = 0x8000000A, 2388 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 2389 }, 2390 { 2391 .name = "phenom", 2392 .level = 5, 2393 .vendor = CPUID_VENDOR_AMD, 2394 .family = 16, 2395 .model = 2, 2396 .stepping = 3, 2397 /* Missing: CPUID_HT */ 2398 .features[FEAT_1_EDX] = 2399 PPRO_FEATURES | 2400 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2401 CPUID_PSE36 | CPUID_VME, 2402 .features[FEAT_1_ECX] = 2403 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 | 2404 CPUID_EXT_POPCNT, 2405 .features[FEAT_8000_0001_EDX] = 2406 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | 2407 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT | 2408 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP, 2409 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, 2410 CPUID_EXT3_CR8LEG, 2411 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, 2412 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */ 2413 .features[FEAT_8000_0001_ECX] = 2414 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | 2415 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A, 2416 /* Missing: CPUID_SVM_LBRV */ 2417 .features[FEAT_SVM] = 2418 CPUID_SVM_NPT, 2419 .xlevel = 0x8000001A, 2420 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor" 2421 }, 2422 { 2423 .name = "core2duo", 2424 .level = 10, 2425 .vendor = CPUID_VENDOR_INTEL, 2426 .family = 6, 2427 .model = 15, 2428 .stepping = 11, 2429 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2430 .features[FEAT_1_EDX] = 2431 PPRO_FEATURES | 2432 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2433 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS, 2434 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST, 2435 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */ 2436 .features[FEAT_1_ECX] = 2437 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | 2438 CPUID_EXT_CX16, 2439 .features[FEAT_8000_0001_EDX] = 2440 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2441 .features[FEAT_8000_0001_ECX] = 2442 CPUID_EXT3_LAHF_LM, 2443 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2444 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2445 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2446 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2447 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2448 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2449 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2450 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2451 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2452 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2453 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2454 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2455 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2456 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2457 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2458 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2459 .features[FEAT_VMX_SECONDARY_CTLS] = 2460 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES, 2461 .xlevel = 0x80000008, 2462 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz", 2463 }, 2464 { 2465 .name = "kvm64", 2466 .level = 0xd, 2467 .vendor = CPUID_VENDOR_INTEL, 2468 .family = 15, 2469 .model = 6, 2470 .stepping = 1, 2471 /* Missing: CPUID_HT */ 2472 .features[FEAT_1_EDX] = 2473 PPRO_FEATURES | CPUID_VME | 2474 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2475 CPUID_PSE36, 2476 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */ 2477 .features[FEAT_1_ECX] = 2478 CPUID_EXT_SSE3 | CPUID_EXT_CX16, 2479 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */ 2480 .features[FEAT_8000_0001_EDX] = 2481 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2482 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, 2483 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A, 2484 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, 2485 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */ 2486 .features[FEAT_8000_0001_ECX] = 2487 0, 2488 /* VMX features from Cedar Mill/Prescott */ 2489 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2490 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2491 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2492 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2493 VMX_PIN_BASED_NMI_EXITING, 2494 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2495 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2496 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2497 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2498 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2499 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2500 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2501 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING, 2502 .xlevel = 0x80000008, 2503 .model_id = "Common KVM processor" 2504 }, 2505 { 2506 .name = "qemu32", 2507 .level = 4, 2508 .vendor = CPUID_VENDOR_INTEL, 2509 .family = 6, 2510 .model = 6, 2511 .stepping = 3, 2512 .features[FEAT_1_EDX] = 2513 PPRO_FEATURES, 2514 .features[FEAT_1_ECX] = 2515 CPUID_EXT_SSE3, 2516 .xlevel = 0x80000004, 2517 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 2518 }, 2519 { 2520 .name = "kvm32", 2521 .level = 5, 2522 .vendor = CPUID_VENDOR_INTEL, 2523 .family = 15, 2524 .model = 6, 2525 .stepping = 1, 2526 .features[FEAT_1_EDX] = 2527 PPRO_FEATURES | CPUID_VME | 2528 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36, 2529 .features[FEAT_1_ECX] = 2530 CPUID_EXT_SSE3, 2531 .features[FEAT_8000_0001_ECX] = 2532 0, 2533 /* VMX features from Yonah */ 2534 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2535 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2536 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2537 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2538 VMX_PIN_BASED_NMI_EXITING, 2539 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2540 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2541 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2542 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2543 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 2544 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 2545 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS, 2546 .xlevel = 0x80000008, 2547 .model_id = "Common 32-bit KVM processor" 2548 }, 2549 { 2550 .name = "coreduo", 2551 .level = 10, 2552 .vendor = CPUID_VENDOR_INTEL, 2553 .family = 6, 2554 .model = 14, 2555 .stepping = 8, 2556 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2557 .features[FEAT_1_EDX] = 2558 PPRO_FEATURES | CPUID_VME | 2559 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI | 2560 CPUID_SS, 2561 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR, 2562 * CPUID_EXT_PDCM, CPUID_EXT_VMX */ 2563 .features[FEAT_1_ECX] = 2564 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR, 2565 .features[FEAT_8000_0001_EDX] = 2566 CPUID_EXT2_NX, 2567 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2568 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2569 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2570 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2571 VMX_PIN_BASED_NMI_EXITING, 2572 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2573 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2574 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2575 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2576 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 2577 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 2578 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS, 2579 .xlevel = 0x80000008, 2580 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz", 2581 }, 2582 { 2583 .name = "486", 2584 .level = 1, 2585 .vendor = CPUID_VENDOR_INTEL, 2586 .family = 4, 2587 .model = 8, 2588 .stepping = 0, 2589 .features[FEAT_1_EDX] = 2590 I486_FEATURES, 2591 .xlevel = 0, 2592 .model_id = "", 2593 }, 2594 { 2595 .name = "pentium", 2596 .level = 1, 2597 .vendor = CPUID_VENDOR_INTEL, 2598 .family = 5, 2599 .model = 4, 2600 .stepping = 3, 2601 .features[FEAT_1_EDX] = 2602 PENTIUM_FEATURES, 2603 .xlevel = 0, 2604 .model_id = "", 2605 }, 2606 { 2607 .name = "pentium2", 2608 .level = 2, 2609 .vendor = CPUID_VENDOR_INTEL, 2610 .family = 6, 2611 .model = 5, 2612 .stepping = 2, 2613 .features[FEAT_1_EDX] = 2614 PENTIUM2_FEATURES, 2615 .xlevel = 0, 2616 .model_id = "", 2617 }, 2618 { 2619 .name = "pentium3", 2620 .level = 3, 2621 .vendor = CPUID_VENDOR_INTEL, 2622 .family = 6, 2623 .model = 7, 2624 .stepping = 3, 2625 .features[FEAT_1_EDX] = 2626 PENTIUM3_FEATURES, 2627 .xlevel = 0, 2628 .model_id = "", 2629 }, 2630 { 2631 .name = "athlon", 2632 .level = 2, 2633 .vendor = CPUID_VENDOR_AMD, 2634 .family = 6, 2635 .model = 2, 2636 .stepping = 3, 2637 .features[FEAT_1_EDX] = 2638 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR | 2639 CPUID_MCA, 2640 .features[FEAT_8000_0001_EDX] = 2641 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT, 2642 .xlevel = 0x80000008, 2643 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 2644 }, 2645 { 2646 .name = "n270", 2647 .level = 10, 2648 .vendor = CPUID_VENDOR_INTEL, 2649 .family = 6, 2650 .model = 28, 2651 .stepping = 2, 2652 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2653 .features[FEAT_1_EDX] = 2654 PPRO_FEATURES | 2655 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | 2656 CPUID_ACPI | CPUID_SS, 2657 /* Some CPUs got no CPUID_SEP */ 2658 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2, 2659 * CPUID_EXT_XTPR */ 2660 .features[FEAT_1_ECX] = 2661 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | 2662 CPUID_EXT_MOVBE, 2663 .features[FEAT_8000_0001_EDX] = 2664 CPUID_EXT2_NX, 2665 .features[FEAT_8000_0001_ECX] = 2666 CPUID_EXT3_LAHF_LM, 2667 .xlevel = 0x80000008, 2668 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz", 2669 }, 2670 { 2671 .name = "Conroe", 2672 .level = 10, 2673 .vendor = CPUID_VENDOR_INTEL, 2674 .family = 6, 2675 .model = 15, 2676 .stepping = 3, 2677 .features[FEAT_1_EDX] = 2678 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2679 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2680 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2681 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2682 CPUID_DE | CPUID_FP87, 2683 .features[FEAT_1_ECX] = 2684 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, 2685 .features[FEAT_8000_0001_EDX] = 2686 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 2687 .features[FEAT_8000_0001_ECX] = 2688 CPUID_EXT3_LAHF_LM, 2689 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2690 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2691 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2692 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2693 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2694 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2695 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2696 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2697 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2698 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2699 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2700 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2701 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2702 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2703 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2704 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2705 .features[FEAT_VMX_SECONDARY_CTLS] = 2706 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES, 2707 .xlevel = 0x80000008, 2708 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)", 2709 }, 2710 { 2711 .name = "Penryn", 2712 .level = 10, 2713 .vendor = CPUID_VENDOR_INTEL, 2714 .family = 6, 2715 .model = 23, 2716 .stepping = 3, 2717 .features[FEAT_1_EDX] = 2718 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2719 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2720 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2721 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2722 CPUID_DE | CPUID_FP87, 2723 .features[FEAT_1_ECX] = 2724 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2725 CPUID_EXT_SSE3, 2726 .features[FEAT_8000_0001_EDX] = 2727 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 2728 .features[FEAT_8000_0001_ECX] = 2729 CPUID_EXT3_LAHF_LM, 2730 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2731 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2732 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, 2733 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT | 2734 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL, 2735 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2736 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2737 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2738 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2739 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2740 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2741 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2742 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2743 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2744 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2745 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2746 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2747 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2748 .features[FEAT_VMX_SECONDARY_CTLS] = 2749 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2750 VMX_SECONDARY_EXEC_WBINVD_EXITING, 2751 .xlevel = 0x80000008, 2752 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)", 2753 }, 2754 { 2755 .name = "Nehalem", 2756 .level = 11, 2757 .vendor = CPUID_VENDOR_INTEL, 2758 .family = 6, 2759 .model = 26, 2760 .stepping = 3, 2761 .features[FEAT_1_EDX] = 2762 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2763 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2764 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2765 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2766 CPUID_DE | CPUID_FP87, 2767 .features[FEAT_1_ECX] = 2768 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 2769 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, 2770 .features[FEAT_8000_0001_EDX] = 2771 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2772 .features[FEAT_8000_0001_ECX] = 2773 CPUID_EXT3_LAHF_LM, 2774 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2775 MSR_VMX_BASIC_TRUE_CTLS, 2776 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2777 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2778 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2779 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2780 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2781 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2782 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2783 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2784 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2785 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2786 .features[FEAT_VMX_EXIT_CTLS] = 2787 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2788 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2789 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2790 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2791 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2792 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2793 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2794 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2795 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2796 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2797 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2798 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2799 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2800 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2801 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2802 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2803 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2804 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2805 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2806 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2807 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2808 .features[FEAT_VMX_SECONDARY_CTLS] = 2809 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2810 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2811 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2812 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2813 VMX_SECONDARY_EXEC_ENABLE_VPID, 2814 .xlevel = 0x80000008, 2815 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)", 2816 .versions = (X86CPUVersionDefinition[]) { 2817 { .version = 1 }, 2818 { 2819 .version = 2, 2820 .alias = "Nehalem-IBRS", 2821 .props = (PropValue[]) { 2822 { "spec-ctrl", "on" }, 2823 { "model-id", 2824 "Intel Core i7 9xx (Nehalem Core i7, IBRS update)" }, 2825 { /* end of list */ } 2826 } 2827 }, 2828 { /* end of list */ } 2829 } 2830 }, 2831 { 2832 .name = "Westmere", 2833 .level = 11, 2834 .vendor = CPUID_VENDOR_INTEL, 2835 .family = 6, 2836 .model = 44, 2837 .stepping = 1, 2838 .features[FEAT_1_EDX] = 2839 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2840 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2841 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2842 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2843 CPUID_DE | CPUID_FP87, 2844 .features[FEAT_1_ECX] = 2845 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | 2846 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2847 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 2848 .features[FEAT_8000_0001_EDX] = 2849 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2850 .features[FEAT_8000_0001_ECX] = 2851 CPUID_EXT3_LAHF_LM, 2852 .features[FEAT_6_EAX] = 2853 CPUID_6_EAX_ARAT, 2854 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2855 MSR_VMX_BASIC_TRUE_CTLS, 2856 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2857 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2858 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2859 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2860 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2861 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2862 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2863 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2864 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2865 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2866 .features[FEAT_VMX_EXIT_CTLS] = 2867 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2868 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2869 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2870 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2871 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2872 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2873 MSR_VMX_MISC_STORE_LMA, 2874 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2875 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2876 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2877 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2878 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2879 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2880 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2881 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2882 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2883 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2884 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2885 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2886 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2887 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2888 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2889 .features[FEAT_VMX_SECONDARY_CTLS] = 2890 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2891 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2892 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2893 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2894 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST, 2895 .xlevel = 0x80000008, 2896 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)", 2897 .versions = (X86CPUVersionDefinition[]) { 2898 { .version = 1 }, 2899 { 2900 .version = 2, 2901 .alias = "Westmere-IBRS", 2902 .props = (PropValue[]) { 2903 { "spec-ctrl", "on" }, 2904 { "model-id", 2905 "Westmere E56xx/L56xx/X56xx (IBRS update)" }, 2906 { /* end of list */ } 2907 } 2908 }, 2909 { /* end of list */ } 2910 } 2911 }, 2912 { 2913 .name = "SandyBridge", 2914 .level = 0xd, 2915 .vendor = CPUID_VENDOR_INTEL, 2916 .family = 6, 2917 .model = 42, 2918 .stepping = 1, 2919 .features[FEAT_1_EDX] = 2920 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2921 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2922 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2923 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2924 CPUID_DE | CPUID_FP87, 2925 .features[FEAT_1_ECX] = 2926 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2927 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | 2928 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 2929 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 2930 CPUID_EXT_SSE3, 2931 .features[FEAT_8000_0001_EDX] = 2932 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 2933 CPUID_EXT2_SYSCALL, 2934 .features[FEAT_8000_0001_ECX] = 2935 CPUID_EXT3_LAHF_LM, 2936 .features[FEAT_XSAVE] = 2937 CPUID_XSAVE_XSAVEOPT, 2938 .features[FEAT_6_EAX] = 2939 CPUID_6_EAX_ARAT, 2940 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2941 MSR_VMX_BASIC_TRUE_CTLS, 2942 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2943 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2944 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2945 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2946 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2947 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2948 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2949 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2950 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2951 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2952 .features[FEAT_VMX_EXIT_CTLS] = 2953 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2954 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2955 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2956 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2957 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2958 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2959 MSR_VMX_MISC_STORE_LMA, 2960 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2961 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2962 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2963 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2964 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2965 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2966 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2967 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2968 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2969 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2970 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2971 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2972 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2973 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2974 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2975 .features[FEAT_VMX_SECONDARY_CTLS] = 2976 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2977 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2978 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2979 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2980 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST, 2981 .xlevel = 0x80000008, 2982 .model_id = "Intel Xeon E312xx (Sandy Bridge)", 2983 .versions = (X86CPUVersionDefinition[]) { 2984 { .version = 1 }, 2985 { 2986 .version = 2, 2987 .alias = "SandyBridge-IBRS", 2988 .props = (PropValue[]) { 2989 { "spec-ctrl", "on" }, 2990 { "model-id", 2991 "Intel Xeon E312xx (Sandy Bridge, IBRS update)" }, 2992 { /* end of list */ } 2993 } 2994 }, 2995 { /* end of list */ } 2996 } 2997 }, 2998 { 2999 .name = "IvyBridge", 3000 .level = 0xd, 3001 .vendor = CPUID_VENDOR_INTEL, 3002 .family = 6, 3003 .model = 58, 3004 .stepping = 9, 3005 .features[FEAT_1_EDX] = 3006 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3007 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3008 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3009 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3010 CPUID_DE | CPUID_FP87, 3011 .features[FEAT_1_ECX] = 3012 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3013 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | 3014 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 3015 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 3016 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3017 .features[FEAT_7_0_EBX] = 3018 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | 3019 CPUID_7_0_EBX_ERMS, 3020 .features[FEAT_8000_0001_EDX] = 3021 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3022 CPUID_EXT2_SYSCALL, 3023 .features[FEAT_8000_0001_ECX] = 3024 CPUID_EXT3_LAHF_LM, 3025 .features[FEAT_XSAVE] = 3026 CPUID_XSAVE_XSAVEOPT, 3027 .features[FEAT_6_EAX] = 3028 CPUID_6_EAX_ARAT, 3029 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3030 MSR_VMX_BASIC_TRUE_CTLS, 3031 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3032 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3033 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3034 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3035 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3036 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3037 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3038 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3039 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3040 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 3041 .features[FEAT_VMX_EXIT_CTLS] = 3042 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3043 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3044 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3045 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3046 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3047 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3048 MSR_VMX_MISC_STORE_LMA, 3049 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3050 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3051 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3052 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3053 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3054 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3055 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3056 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3057 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3058 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3059 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3060 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3061 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3062 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3063 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3064 .features[FEAT_VMX_SECONDARY_CTLS] = 3065 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3066 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3067 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3068 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3069 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3070 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3071 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3072 VMX_SECONDARY_EXEC_RDRAND_EXITING, 3073 .xlevel = 0x80000008, 3074 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)", 3075 .versions = (X86CPUVersionDefinition[]) { 3076 { .version = 1 }, 3077 { 3078 .version = 2, 3079 .alias = "IvyBridge-IBRS", 3080 .props = (PropValue[]) { 3081 { "spec-ctrl", "on" }, 3082 { "model-id", 3083 "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)" }, 3084 { /* end of list */ } 3085 } 3086 }, 3087 { /* end of list */ } 3088 } 3089 }, 3090 { 3091 .name = "Haswell", 3092 .level = 0xd, 3093 .vendor = CPUID_VENDOR_INTEL, 3094 .family = 6, 3095 .model = 60, 3096 .stepping = 4, 3097 .features[FEAT_1_EDX] = 3098 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3099 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3100 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3101 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3102 CPUID_DE | CPUID_FP87, 3103 .features[FEAT_1_ECX] = 3104 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3105 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3106 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3107 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3108 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3109 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3110 .features[FEAT_8000_0001_EDX] = 3111 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3112 CPUID_EXT2_SYSCALL, 3113 .features[FEAT_8000_0001_ECX] = 3114 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM, 3115 .features[FEAT_7_0_EBX] = 3116 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3117 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3118 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3119 CPUID_7_0_EBX_RTM, 3120 .features[FEAT_XSAVE] = 3121 CPUID_XSAVE_XSAVEOPT, 3122 .features[FEAT_6_EAX] = 3123 CPUID_6_EAX_ARAT, 3124 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3125 MSR_VMX_BASIC_TRUE_CTLS, 3126 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3127 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3128 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3129 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3130 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3131 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3132 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3133 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3134 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3135 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3136 .features[FEAT_VMX_EXIT_CTLS] = 3137 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3138 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3139 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3140 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3141 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3142 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3143 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3144 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3145 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3146 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3147 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3148 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3149 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3150 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3151 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3152 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3153 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3154 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3155 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3156 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3157 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3158 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3159 .features[FEAT_VMX_SECONDARY_CTLS] = 3160 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3161 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3162 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3163 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3164 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3165 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3166 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3167 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3168 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS, 3169 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3170 .xlevel = 0x80000008, 3171 .model_id = "Intel Core Processor (Haswell)", 3172 .versions = (X86CPUVersionDefinition[]) { 3173 { .version = 1 }, 3174 { 3175 .version = 2, 3176 .alias = "Haswell-noTSX", 3177 .props = (PropValue[]) { 3178 { "hle", "off" }, 3179 { "rtm", "off" }, 3180 { "stepping", "1" }, 3181 { "model-id", "Intel Core Processor (Haswell, no TSX)", }, 3182 { /* end of list */ } 3183 }, 3184 }, 3185 { 3186 .version = 3, 3187 .alias = "Haswell-IBRS", 3188 .props = (PropValue[]) { 3189 /* Restore TSX features removed by -v2 above */ 3190 { "hle", "on" }, 3191 { "rtm", "on" }, 3192 /* 3193 * Haswell and Haswell-IBRS had stepping=4 in 3194 * QEMU 4.0 and older 3195 */ 3196 { "stepping", "4" }, 3197 { "spec-ctrl", "on" }, 3198 { "model-id", 3199 "Intel Core Processor (Haswell, IBRS)" }, 3200 { /* end of list */ } 3201 } 3202 }, 3203 { 3204 .version = 4, 3205 .alias = "Haswell-noTSX-IBRS", 3206 .props = (PropValue[]) { 3207 { "hle", "off" }, 3208 { "rtm", "off" }, 3209 /* spec-ctrl was already enabled by -v3 above */ 3210 { "stepping", "1" }, 3211 { "model-id", 3212 "Intel Core Processor (Haswell, no TSX, IBRS)" }, 3213 { /* end of list */ } 3214 } 3215 }, 3216 { /* end of list */ } 3217 } 3218 }, 3219 { 3220 .name = "Broadwell", 3221 .level = 0xd, 3222 .vendor = CPUID_VENDOR_INTEL, 3223 .family = 6, 3224 .model = 61, 3225 .stepping = 2, 3226 .features[FEAT_1_EDX] = 3227 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3228 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3229 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3230 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3231 CPUID_DE | CPUID_FP87, 3232 .features[FEAT_1_ECX] = 3233 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3234 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3235 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3236 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3237 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3238 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3239 .features[FEAT_8000_0001_EDX] = 3240 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3241 CPUID_EXT2_SYSCALL, 3242 .features[FEAT_8000_0001_ECX] = 3243 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3244 .features[FEAT_7_0_EBX] = 3245 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3246 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3247 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3248 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3249 CPUID_7_0_EBX_SMAP, 3250 .features[FEAT_XSAVE] = 3251 CPUID_XSAVE_XSAVEOPT, 3252 .features[FEAT_6_EAX] = 3253 CPUID_6_EAX_ARAT, 3254 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3255 MSR_VMX_BASIC_TRUE_CTLS, 3256 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3257 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3258 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3259 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3260 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3261 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3262 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3263 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3264 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3265 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3266 .features[FEAT_VMX_EXIT_CTLS] = 3267 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3268 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3269 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3270 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3271 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3272 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3273 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3274 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3275 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3276 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3277 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3278 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3279 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3280 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3281 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3282 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3283 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3284 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3285 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3286 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3287 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3288 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3289 .features[FEAT_VMX_SECONDARY_CTLS] = 3290 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3291 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3292 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3293 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3294 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3295 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3296 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3297 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3298 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3299 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3300 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3301 .xlevel = 0x80000008, 3302 .model_id = "Intel Core Processor (Broadwell)", 3303 .versions = (X86CPUVersionDefinition[]) { 3304 { .version = 1 }, 3305 { 3306 .version = 2, 3307 .alias = "Broadwell-noTSX", 3308 .props = (PropValue[]) { 3309 { "hle", "off" }, 3310 { "rtm", "off" }, 3311 { "model-id", "Intel Core Processor (Broadwell, no TSX)", }, 3312 { /* end of list */ } 3313 }, 3314 }, 3315 { 3316 .version = 3, 3317 .alias = "Broadwell-IBRS", 3318 .props = (PropValue[]) { 3319 /* Restore TSX features removed by -v2 above */ 3320 { "hle", "on" }, 3321 { "rtm", "on" }, 3322 { "spec-ctrl", "on" }, 3323 { "model-id", 3324 "Intel Core Processor (Broadwell, IBRS)" }, 3325 { /* end of list */ } 3326 } 3327 }, 3328 { 3329 .version = 4, 3330 .alias = "Broadwell-noTSX-IBRS", 3331 .props = (PropValue[]) { 3332 { "hle", "off" }, 3333 { "rtm", "off" }, 3334 /* spec-ctrl was already enabled by -v3 above */ 3335 { "model-id", 3336 "Intel Core Processor (Broadwell, no TSX, IBRS)" }, 3337 { /* end of list */ } 3338 } 3339 }, 3340 { /* end of list */ } 3341 } 3342 }, 3343 { 3344 .name = "Skylake-Client", 3345 .level = 0xd, 3346 .vendor = CPUID_VENDOR_INTEL, 3347 .family = 6, 3348 .model = 94, 3349 .stepping = 3, 3350 .features[FEAT_1_EDX] = 3351 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3352 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3353 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3354 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3355 CPUID_DE | CPUID_FP87, 3356 .features[FEAT_1_ECX] = 3357 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3358 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3359 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3360 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3361 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3362 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3363 .features[FEAT_8000_0001_EDX] = 3364 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3365 CPUID_EXT2_SYSCALL, 3366 .features[FEAT_8000_0001_ECX] = 3367 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3368 .features[FEAT_7_0_EBX] = 3369 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3370 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3371 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3372 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3373 CPUID_7_0_EBX_SMAP, 3374 /* XSAVES is added in version 4 */ 3375 .features[FEAT_XSAVE] = 3376 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3377 CPUID_XSAVE_XGETBV1, 3378 .features[FEAT_6_EAX] = 3379 CPUID_6_EAX_ARAT, 3380 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3381 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3382 MSR_VMX_BASIC_TRUE_CTLS, 3383 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3384 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3385 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3386 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3387 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3388 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3389 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3390 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3391 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3392 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3393 .features[FEAT_VMX_EXIT_CTLS] = 3394 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3395 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3396 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3397 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3398 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3399 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3400 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3401 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3402 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3403 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 3404 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3405 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3406 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3407 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3408 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3409 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3410 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3411 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3412 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3413 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3414 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3415 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3416 .features[FEAT_VMX_SECONDARY_CTLS] = 3417 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3418 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3419 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3420 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3421 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3422 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3423 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3424 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3425 .xlevel = 0x80000008, 3426 .model_id = "Intel Core Processor (Skylake)", 3427 .versions = (X86CPUVersionDefinition[]) { 3428 { .version = 1 }, 3429 { 3430 .version = 2, 3431 .alias = "Skylake-Client-IBRS", 3432 .props = (PropValue[]) { 3433 { "spec-ctrl", "on" }, 3434 { "model-id", 3435 "Intel Core Processor (Skylake, IBRS)" }, 3436 { /* end of list */ } 3437 } 3438 }, 3439 { 3440 .version = 3, 3441 .alias = "Skylake-Client-noTSX-IBRS", 3442 .props = (PropValue[]) { 3443 { "hle", "off" }, 3444 { "rtm", "off" }, 3445 { "model-id", 3446 "Intel Core Processor (Skylake, IBRS, no TSX)" }, 3447 { /* end of list */ } 3448 } 3449 }, 3450 { 3451 .version = 4, 3452 .note = "IBRS, XSAVES, no TSX", 3453 .props = (PropValue[]) { 3454 { "xsaves", "on" }, 3455 { "vmx-xsaves", "on" }, 3456 { /* end of list */ } 3457 } 3458 }, 3459 { /* end of list */ } 3460 } 3461 }, 3462 { 3463 .name = "Skylake-Server", 3464 .level = 0xd, 3465 .vendor = CPUID_VENDOR_INTEL, 3466 .family = 6, 3467 .model = 85, 3468 .stepping = 4, 3469 .features[FEAT_1_EDX] = 3470 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3471 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3472 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3473 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3474 CPUID_DE | CPUID_FP87, 3475 .features[FEAT_1_ECX] = 3476 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3477 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3478 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3479 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3480 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3481 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3482 .features[FEAT_8000_0001_EDX] = 3483 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3484 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3485 .features[FEAT_8000_0001_ECX] = 3486 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3487 .features[FEAT_7_0_EBX] = 3488 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3489 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3490 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3491 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3492 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3493 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3494 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3495 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3496 .features[FEAT_7_0_ECX] = 3497 CPUID_7_0_ECX_PKU, 3498 /* XSAVES is added in version 5 */ 3499 .features[FEAT_XSAVE] = 3500 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3501 CPUID_XSAVE_XGETBV1, 3502 .features[FEAT_6_EAX] = 3503 CPUID_6_EAX_ARAT, 3504 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3505 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3506 MSR_VMX_BASIC_TRUE_CTLS, 3507 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3508 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3509 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3510 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3511 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3512 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3513 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3514 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3515 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3516 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3517 .features[FEAT_VMX_EXIT_CTLS] = 3518 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3519 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3520 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3521 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3522 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3523 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3524 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3525 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3526 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3527 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3528 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3529 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3530 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3531 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3532 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3533 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3534 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3535 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3536 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3537 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3538 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3539 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3540 .features[FEAT_VMX_SECONDARY_CTLS] = 3541 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3542 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3543 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3544 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3545 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3546 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3547 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3548 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3549 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3550 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3551 .xlevel = 0x80000008, 3552 .model_id = "Intel Xeon Processor (Skylake)", 3553 .versions = (X86CPUVersionDefinition[]) { 3554 { .version = 1 }, 3555 { 3556 .version = 2, 3557 .alias = "Skylake-Server-IBRS", 3558 .props = (PropValue[]) { 3559 /* clflushopt was not added to Skylake-Server-IBRS */ 3560 /* TODO: add -v3 including clflushopt */ 3561 { "clflushopt", "off" }, 3562 { "spec-ctrl", "on" }, 3563 { "model-id", 3564 "Intel Xeon Processor (Skylake, IBRS)" }, 3565 { /* end of list */ } 3566 } 3567 }, 3568 { 3569 .version = 3, 3570 .alias = "Skylake-Server-noTSX-IBRS", 3571 .props = (PropValue[]) { 3572 { "hle", "off" }, 3573 { "rtm", "off" }, 3574 { "model-id", 3575 "Intel Xeon Processor (Skylake, IBRS, no TSX)" }, 3576 { /* end of list */ } 3577 } 3578 }, 3579 { 3580 .version = 4, 3581 .props = (PropValue[]) { 3582 { "vmx-eptp-switching", "on" }, 3583 { /* end of list */ } 3584 } 3585 }, 3586 { 3587 .version = 5, 3588 .note = "IBRS, XSAVES, EPT switching, no TSX", 3589 .props = (PropValue[]) { 3590 { "xsaves", "on" }, 3591 { "vmx-xsaves", "on" }, 3592 { /* end of list */ } 3593 } 3594 }, 3595 { /* end of list */ } 3596 } 3597 }, 3598 { 3599 .name = "Cascadelake-Server", 3600 .level = 0xd, 3601 .vendor = CPUID_VENDOR_INTEL, 3602 .family = 6, 3603 .model = 85, 3604 .stepping = 6, 3605 .features[FEAT_1_EDX] = 3606 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3607 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3608 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3609 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3610 CPUID_DE | CPUID_FP87, 3611 .features[FEAT_1_ECX] = 3612 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3613 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3614 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3615 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3616 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3617 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3618 .features[FEAT_8000_0001_EDX] = 3619 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3620 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3621 .features[FEAT_8000_0001_ECX] = 3622 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3623 .features[FEAT_7_0_EBX] = 3624 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3625 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3626 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3627 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3628 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3629 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3630 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3631 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3632 .features[FEAT_7_0_ECX] = 3633 CPUID_7_0_ECX_PKU | 3634 CPUID_7_0_ECX_AVX512VNNI, 3635 .features[FEAT_7_0_EDX] = 3636 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 3637 /* XSAVES is added in version 5 */ 3638 .features[FEAT_XSAVE] = 3639 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3640 CPUID_XSAVE_XGETBV1, 3641 .features[FEAT_6_EAX] = 3642 CPUID_6_EAX_ARAT, 3643 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3644 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3645 MSR_VMX_BASIC_TRUE_CTLS, 3646 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3647 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3648 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3649 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3650 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3651 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3652 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3653 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3654 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3655 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3656 .features[FEAT_VMX_EXIT_CTLS] = 3657 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3658 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3659 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3660 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3661 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3662 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3663 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3664 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3665 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3666 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3667 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3668 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3669 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3670 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3671 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3672 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3673 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3674 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3675 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3676 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3677 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3678 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3679 .features[FEAT_VMX_SECONDARY_CTLS] = 3680 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3681 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3682 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3683 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3684 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3685 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3686 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3687 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3688 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3689 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3690 .xlevel = 0x80000008, 3691 .model_id = "Intel Xeon Processor (Cascadelake)", 3692 .versions = (X86CPUVersionDefinition[]) { 3693 { .version = 1 }, 3694 { .version = 2, 3695 .note = "ARCH_CAPABILITIES", 3696 .props = (PropValue[]) { 3697 { "arch-capabilities", "on" }, 3698 { "rdctl-no", "on" }, 3699 { "ibrs-all", "on" }, 3700 { "skip-l1dfl-vmentry", "on" }, 3701 { "mds-no", "on" }, 3702 { /* end of list */ } 3703 }, 3704 }, 3705 { .version = 3, 3706 .alias = "Cascadelake-Server-noTSX", 3707 .note = "ARCH_CAPABILITIES, no TSX", 3708 .props = (PropValue[]) { 3709 { "hle", "off" }, 3710 { "rtm", "off" }, 3711 { /* end of list */ } 3712 }, 3713 }, 3714 { .version = 4, 3715 .note = "ARCH_CAPABILITIES, no TSX", 3716 .props = (PropValue[]) { 3717 { "vmx-eptp-switching", "on" }, 3718 { /* end of list */ } 3719 }, 3720 }, 3721 { .version = 5, 3722 .note = "ARCH_CAPABILITIES, EPT switching, XSAVES, no TSX", 3723 .props = (PropValue[]) { 3724 { "xsaves", "on" }, 3725 { "vmx-xsaves", "on" }, 3726 { /* end of list */ } 3727 }, 3728 }, 3729 { /* end of list */ } 3730 } 3731 }, 3732 { 3733 .name = "Cooperlake", 3734 .level = 0xd, 3735 .vendor = CPUID_VENDOR_INTEL, 3736 .family = 6, 3737 .model = 85, 3738 .stepping = 10, 3739 .features[FEAT_1_EDX] = 3740 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3741 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3742 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3743 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3744 CPUID_DE | CPUID_FP87, 3745 .features[FEAT_1_ECX] = 3746 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3747 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3748 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3749 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3750 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3751 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3752 .features[FEAT_8000_0001_EDX] = 3753 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3754 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3755 .features[FEAT_8000_0001_ECX] = 3756 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3757 .features[FEAT_7_0_EBX] = 3758 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3759 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3760 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3761 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3762 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3763 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3764 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3765 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3766 .features[FEAT_7_0_ECX] = 3767 CPUID_7_0_ECX_PKU | 3768 CPUID_7_0_ECX_AVX512VNNI, 3769 .features[FEAT_7_0_EDX] = 3770 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_STIBP | 3771 CPUID_7_0_EDX_SPEC_CTRL_SSBD | CPUID_7_0_EDX_ARCH_CAPABILITIES, 3772 .features[FEAT_ARCH_CAPABILITIES] = 3773 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 3774 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 3775 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO, 3776 .features[FEAT_7_1_EAX] = 3777 CPUID_7_1_EAX_AVX512_BF16, 3778 /* XSAVES is added in version 2 */ 3779 .features[FEAT_XSAVE] = 3780 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3781 CPUID_XSAVE_XGETBV1, 3782 .features[FEAT_6_EAX] = 3783 CPUID_6_EAX_ARAT, 3784 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3785 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3786 MSR_VMX_BASIC_TRUE_CTLS, 3787 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3788 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3789 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3790 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3791 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3792 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3793 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3794 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3795 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3796 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3797 .features[FEAT_VMX_EXIT_CTLS] = 3798 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3799 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3800 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3801 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3802 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3803 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3804 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3805 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3806 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3807 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3808 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3809 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3810 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3811 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3812 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3813 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3814 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3815 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3816 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3817 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3818 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3819 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3820 .features[FEAT_VMX_SECONDARY_CTLS] = 3821 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3822 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3823 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3824 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3825 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3826 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3827 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3828 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3829 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3830 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3831 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3832 .xlevel = 0x80000008, 3833 .model_id = "Intel Xeon Processor (Cooperlake)", 3834 .versions = (X86CPUVersionDefinition[]) { 3835 { .version = 1 }, 3836 { .version = 2, 3837 .note = "XSAVES", 3838 .props = (PropValue[]) { 3839 { "xsaves", "on" }, 3840 { "vmx-xsaves", "on" }, 3841 { /* end of list */ } 3842 }, 3843 }, 3844 { /* end of list */ } 3845 } 3846 }, 3847 { 3848 .name = "Icelake-Server", 3849 .level = 0xd, 3850 .vendor = CPUID_VENDOR_INTEL, 3851 .family = 6, 3852 .model = 134, 3853 .stepping = 0, 3854 .features[FEAT_1_EDX] = 3855 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3856 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3857 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3858 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3859 CPUID_DE | CPUID_FP87, 3860 .features[FEAT_1_ECX] = 3861 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3862 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3863 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3864 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3865 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3866 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3867 .features[FEAT_8000_0001_EDX] = 3868 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3869 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3870 .features[FEAT_8000_0001_ECX] = 3871 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3872 .features[FEAT_8000_0008_EBX] = 3873 CPUID_8000_0008_EBX_WBNOINVD, 3874 .features[FEAT_7_0_EBX] = 3875 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3876 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3877 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3878 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3879 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3880 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3881 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3882 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3883 .features[FEAT_7_0_ECX] = 3884 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 3885 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 3886 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 3887 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 3888 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57, 3889 .features[FEAT_7_0_EDX] = 3890 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 3891 /* XSAVES is added in version 5 */ 3892 .features[FEAT_XSAVE] = 3893 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3894 CPUID_XSAVE_XGETBV1, 3895 .features[FEAT_6_EAX] = 3896 CPUID_6_EAX_ARAT, 3897 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3898 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3899 MSR_VMX_BASIC_TRUE_CTLS, 3900 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3901 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3902 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3903 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3904 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3905 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3906 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3907 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3908 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3909 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3910 .features[FEAT_VMX_EXIT_CTLS] = 3911 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3912 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3913 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3914 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3915 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3916 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3917 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3918 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3919 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3920 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3921 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3922 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3923 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3924 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3925 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3926 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3927 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3928 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3929 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3930 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3931 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3932 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3933 .features[FEAT_VMX_SECONDARY_CTLS] = 3934 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3935 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3936 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3937 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3938 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3939 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3940 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3941 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3942 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS, 3943 .xlevel = 0x80000008, 3944 .model_id = "Intel Xeon Processor (Icelake)", 3945 .versions = (X86CPUVersionDefinition[]) { 3946 { .version = 1 }, 3947 { 3948 .version = 2, 3949 .note = "no TSX", 3950 .alias = "Icelake-Server-noTSX", 3951 .props = (PropValue[]) { 3952 { "hle", "off" }, 3953 { "rtm", "off" }, 3954 { /* end of list */ } 3955 }, 3956 }, 3957 { 3958 .version = 3, 3959 .props = (PropValue[]) { 3960 { "arch-capabilities", "on" }, 3961 { "rdctl-no", "on" }, 3962 { "ibrs-all", "on" }, 3963 { "skip-l1dfl-vmentry", "on" }, 3964 { "mds-no", "on" }, 3965 { "pschange-mc-no", "on" }, 3966 { "taa-no", "on" }, 3967 { /* end of list */ } 3968 }, 3969 }, 3970 { 3971 .version = 4, 3972 .props = (PropValue[]) { 3973 { "sha-ni", "on" }, 3974 { "avx512ifma", "on" }, 3975 { "rdpid", "on" }, 3976 { "fsrm", "on" }, 3977 { "vmx-rdseed-exit", "on" }, 3978 { "vmx-pml", "on" }, 3979 { "vmx-eptp-switching", "on" }, 3980 { "model", "106" }, 3981 { /* end of list */ } 3982 }, 3983 }, 3984 { 3985 .version = 5, 3986 .note = "XSAVES", 3987 .props = (PropValue[]) { 3988 { "xsaves", "on" }, 3989 { "vmx-xsaves", "on" }, 3990 { /* end of list */ } 3991 }, 3992 }, 3993 { 3994 .version = 6, 3995 .note = "5-level EPT", 3996 .props = (PropValue[]) { 3997 { "vmx-page-walk-5", "on" }, 3998 { /* end of list */ } 3999 }, 4000 }, 4001 { 4002 .version = 7, 4003 .note = "TSX, taa-no", 4004 .props = (PropValue[]) { 4005 /* Restore TSX features removed by -v2 above */ 4006 { "hle", "on" }, 4007 { "rtm", "on" }, 4008 { /* end of list */ } 4009 }, 4010 }, 4011 { /* end of list */ } 4012 } 4013 }, 4014 { 4015 .name = "SapphireRapids", 4016 .level = 0x20, 4017 .vendor = CPUID_VENDOR_INTEL, 4018 .family = 6, 4019 .model = 143, 4020 .stepping = 4, 4021 /* 4022 * please keep the ascending order so that we can have a clear view of 4023 * bit position of each feature. 4024 */ 4025 .features[FEAT_1_EDX] = 4026 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4027 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4028 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4029 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4030 CPUID_SSE | CPUID_SSE2, 4031 .features[FEAT_1_ECX] = 4032 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 4033 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 4034 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4035 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 4036 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4037 .features[FEAT_8000_0001_EDX] = 4038 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4039 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4040 .features[FEAT_8000_0001_ECX] = 4041 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 4042 .features[FEAT_8000_0008_EBX] = 4043 CPUID_8000_0008_EBX_WBNOINVD, 4044 .features[FEAT_7_0_EBX] = 4045 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_HLE | 4046 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | 4047 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RTM | 4048 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 4049 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | 4050 CPUID_7_0_EBX_AVX512IFMA | CPUID_7_0_EBX_CLFLUSHOPT | 4051 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | 4052 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, 4053 .features[FEAT_7_0_ECX] = 4054 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 4055 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 4056 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4057 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 4058 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | 4059 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT, 4060 .features[FEAT_7_0_EDX] = 4061 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 4062 CPUID_7_0_EDX_TSX_LDTRK | CPUID_7_0_EDX_AMX_BF16 | 4063 CPUID_7_0_EDX_AVX512_FP16 | CPUID_7_0_EDX_AMX_TILE | 4064 CPUID_7_0_EDX_AMX_INT8 | CPUID_7_0_EDX_SPEC_CTRL | 4065 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4066 .features[FEAT_ARCH_CAPABILITIES] = 4067 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 4068 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 4069 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO, 4070 .features[FEAT_XSAVE] = 4071 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4072 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES | CPUID_D_1_EAX_XFD, 4073 .features[FEAT_6_EAX] = 4074 CPUID_6_EAX_ARAT, 4075 .features[FEAT_7_1_EAX] = 4076 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_AVX512_BF16 | 4077 CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC, 4078 .features[FEAT_VMX_BASIC] = 4079 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 4080 .features[FEAT_VMX_ENTRY_CTLS] = 4081 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 4082 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 4083 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 4084 .features[FEAT_VMX_EPT_VPID_CAPS] = 4085 MSR_VMX_EPT_EXECONLY | 4086 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_PAGE_WALK_LENGTH_5 | 4087 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 4088 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 4089 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4090 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4091 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 4092 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4093 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 4094 .features[FEAT_VMX_EXIT_CTLS] = 4095 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4096 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4097 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 4098 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4099 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4100 .features[FEAT_VMX_MISC] = 4101 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 4102 MSR_VMX_MISC_VMWRITE_VMEXIT, 4103 .features[FEAT_VMX_PINBASED_CTLS] = 4104 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 4105 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 4106 VMX_PIN_BASED_POSTED_INTR, 4107 .features[FEAT_VMX_PROCBASED_CTLS] = 4108 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4109 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4110 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4111 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4112 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4113 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4114 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 4115 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 4116 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4117 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 4118 VMX_CPU_BASED_PAUSE_EXITING | 4119 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4120 .features[FEAT_VMX_SECONDARY_CTLS] = 4121 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4122 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 4123 VMX_SECONDARY_EXEC_RDTSCP | 4124 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4125 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 4126 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4127 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4128 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4129 VMX_SECONDARY_EXEC_RDRAND_EXITING | 4130 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4131 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4132 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 4133 VMX_SECONDARY_EXEC_XSAVES, 4134 .features[FEAT_VMX_VMFUNC] = 4135 MSR_VMX_VMFUNC_EPT_SWITCHING, 4136 .xlevel = 0x80000008, 4137 .model_id = "Intel Xeon Processor (SapphireRapids)", 4138 .versions = (X86CPUVersionDefinition[]) { 4139 { .version = 1 }, 4140 { 4141 .version = 2, 4142 .props = (PropValue[]) { 4143 { "sbdr-ssdp-no", "on" }, 4144 { "fbsdp-no", "on" }, 4145 { "psdp-no", "on" }, 4146 { /* end of list */ } 4147 } 4148 }, 4149 { 4150 .version = 3, 4151 .props = (PropValue[]) { 4152 { "ss", "on" }, 4153 { "tsc-adjust", "on" }, 4154 { "cldemote", "on" }, 4155 { "movdiri", "on" }, 4156 { "movdir64b", "on" }, 4157 { /* end of list */ } 4158 } 4159 }, 4160 { /* end of list */ } 4161 } 4162 }, 4163 { 4164 .name = "GraniteRapids", 4165 .level = 0x20, 4166 .vendor = CPUID_VENDOR_INTEL, 4167 .family = 6, 4168 .model = 173, 4169 .stepping = 0, 4170 /* 4171 * please keep the ascending order so that we can have a clear view of 4172 * bit position of each feature. 4173 */ 4174 .features[FEAT_1_EDX] = 4175 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4176 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4177 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4178 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4179 CPUID_SSE | CPUID_SSE2, 4180 .features[FEAT_1_ECX] = 4181 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 4182 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 4183 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4184 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 4185 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4186 .features[FEAT_8000_0001_EDX] = 4187 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4188 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4189 .features[FEAT_8000_0001_ECX] = 4190 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 4191 .features[FEAT_8000_0008_EBX] = 4192 CPUID_8000_0008_EBX_WBNOINVD, 4193 .features[FEAT_7_0_EBX] = 4194 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_HLE | 4195 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | 4196 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RTM | 4197 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 4198 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | 4199 CPUID_7_0_EBX_AVX512IFMA | CPUID_7_0_EBX_CLFLUSHOPT | 4200 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | 4201 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, 4202 .features[FEAT_7_0_ECX] = 4203 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 4204 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 4205 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4206 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 4207 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | 4208 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT, 4209 .features[FEAT_7_0_EDX] = 4210 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 4211 CPUID_7_0_EDX_TSX_LDTRK | CPUID_7_0_EDX_AMX_BF16 | 4212 CPUID_7_0_EDX_AVX512_FP16 | CPUID_7_0_EDX_AMX_TILE | 4213 CPUID_7_0_EDX_AMX_INT8 | CPUID_7_0_EDX_SPEC_CTRL | 4214 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4215 .features[FEAT_ARCH_CAPABILITIES] = 4216 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 4217 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 4218 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO | 4219 MSR_ARCH_CAP_SBDR_SSDP_NO | MSR_ARCH_CAP_FBSDP_NO | 4220 MSR_ARCH_CAP_PSDP_NO | MSR_ARCH_CAP_PBRSB_NO, 4221 .features[FEAT_XSAVE] = 4222 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4223 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES | CPUID_D_1_EAX_XFD, 4224 .features[FEAT_6_EAX] = 4225 CPUID_6_EAX_ARAT, 4226 .features[FEAT_7_1_EAX] = 4227 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_AVX512_BF16 | 4228 CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC | 4229 CPUID_7_1_EAX_AMX_FP16, 4230 .features[FEAT_7_1_EDX] = 4231 CPUID_7_1_EDX_PREFETCHITI, 4232 .features[FEAT_7_2_EDX] = 4233 CPUID_7_2_EDX_MCDT_NO, 4234 .features[FEAT_VMX_BASIC] = 4235 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 4236 .features[FEAT_VMX_ENTRY_CTLS] = 4237 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 4238 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 4239 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 4240 .features[FEAT_VMX_EPT_VPID_CAPS] = 4241 MSR_VMX_EPT_EXECONLY | 4242 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_PAGE_WALK_LENGTH_5 | 4243 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 4244 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 4245 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4246 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4247 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 4248 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4249 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 4250 .features[FEAT_VMX_EXIT_CTLS] = 4251 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4252 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4253 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 4254 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4255 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4256 .features[FEAT_VMX_MISC] = 4257 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 4258 MSR_VMX_MISC_VMWRITE_VMEXIT, 4259 .features[FEAT_VMX_PINBASED_CTLS] = 4260 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 4261 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 4262 VMX_PIN_BASED_POSTED_INTR, 4263 .features[FEAT_VMX_PROCBASED_CTLS] = 4264 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4265 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4266 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4267 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4268 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4269 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4270 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 4271 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 4272 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4273 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 4274 VMX_CPU_BASED_PAUSE_EXITING | 4275 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4276 .features[FEAT_VMX_SECONDARY_CTLS] = 4277 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4278 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 4279 VMX_SECONDARY_EXEC_RDTSCP | 4280 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4281 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 4282 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4283 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4284 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4285 VMX_SECONDARY_EXEC_RDRAND_EXITING | 4286 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4287 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4288 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 4289 VMX_SECONDARY_EXEC_XSAVES, 4290 .features[FEAT_VMX_VMFUNC] = 4291 MSR_VMX_VMFUNC_EPT_SWITCHING, 4292 .xlevel = 0x80000008, 4293 .model_id = "Intel Xeon Processor (GraniteRapids)", 4294 .versions = (X86CPUVersionDefinition[]) { 4295 { .version = 1 }, 4296 { /* end of list */ }, 4297 }, 4298 }, 4299 { 4300 .name = "SierraForest", 4301 .level = 0x23, 4302 .vendor = CPUID_VENDOR_INTEL, 4303 .family = 6, 4304 .model = 175, 4305 .stepping = 0, 4306 /* 4307 * please keep the ascending order so that we can have a clear view of 4308 * bit position of each feature. 4309 */ 4310 .features[FEAT_1_EDX] = 4311 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4312 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4313 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4314 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4315 CPUID_SSE | CPUID_SSE2, 4316 .features[FEAT_1_ECX] = 4317 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 4318 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 4319 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4320 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 4321 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4322 .features[FEAT_8000_0001_EDX] = 4323 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4324 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4325 .features[FEAT_8000_0001_ECX] = 4326 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 4327 .features[FEAT_8000_0008_EBX] = 4328 CPUID_8000_0008_EBX_WBNOINVD, 4329 .features[FEAT_7_0_EBX] = 4330 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4331 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 4332 CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 4333 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB | 4334 CPUID_7_0_EBX_SHA_NI, 4335 .features[FEAT_7_0_ECX] = 4336 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_GFNI | 4337 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4338 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT, 4339 .features[FEAT_7_0_EDX] = 4340 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 4341 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES | 4342 CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4343 .features[FEAT_ARCH_CAPABILITIES] = 4344 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 4345 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 4346 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_SBDR_SSDP_NO | 4347 MSR_ARCH_CAP_FBSDP_NO | MSR_ARCH_CAP_PSDP_NO | 4348 MSR_ARCH_CAP_PBRSB_NO, 4349 .features[FEAT_XSAVE] = 4350 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4351 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 4352 .features[FEAT_6_EAX] = 4353 CPUID_6_EAX_ARAT, 4354 .features[FEAT_7_1_EAX] = 4355 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_CMPCCXADD | 4356 CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_AVX_IFMA, 4357 .features[FEAT_7_1_EDX] = 4358 CPUID_7_1_EDX_AVX_VNNI_INT8 | CPUID_7_1_EDX_AVX_NE_CONVERT, 4359 .features[FEAT_7_2_EDX] = 4360 CPUID_7_2_EDX_MCDT_NO, 4361 .features[FEAT_VMX_BASIC] = 4362 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 4363 .features[FEAT_VMX_ENTRY_CTLS] = 4364 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 4365 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 4366 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 4367 .features[FEAT_VMX_EPT_VPID_CAPS] = 4368 MSR_VMX_EPT_EXECONLY | MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | 4369 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 4370 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 4371 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4372 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4373 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 4374 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4375 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 4376 .features[FEAT_VMX_EXIT_CTLS] = 4377 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4378 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4379 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 4380 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4381 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4382 .features[FEAT_VMX_MISC] = 4383 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 4384 MSR_VMX_MISC_VMWRITE_VMEXIT, 4385 .features[FEAT_VMX_PINBASED_CTLS] = 4386 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 4387 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 4388 VMX_PIN_BASED_POSTED_INTR, 4389 .features[FEAT_VMX_PROCBASED_CTLS] = 4390 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4391 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4392 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4393 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4394 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4395 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4396 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 4397 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 4398 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4399 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 4400 VMX_CPU_BASED_PAUSE_EXITING | 4401 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4402 .features[FEAT_VMX_SECONDARY_CTLS] = 4403 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4404 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 4405 VMX_SECONDARY_EXEC_RDTSCP | 4406 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4407 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 4408 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4409 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4410 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4411 VMX_SECONDARY_EXEC_RDRAND_EXITING | 4412 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4413 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4414 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 4415 VMX_SECONDARY_EXEC_XSAVES, 4416 .features[FEAT_VMX_VMFUNC] = 4417 MSR_VMX_VMFUNC_EPT_SWITCHING, 4418 .xlevel = 0x80000008, 4419 .model_id = "Intel Xeon Processor (SierraForest)", 4420 .versions = (X86CPUVersionDefinition[]) { 4421 { .version = 1 }, 4422 { /* end of list */ }, 4423 }, 4424 }, 4425 { 4426 .name = "Denverton", 4427 .level = 21, 4428 .vendor = CPUID_VENDOR_INTEL, 4429 .family = 6, 4430 .model = 95, 4431 .stepping = 1, 4432 .features[FEAT_1_EDX] = 4433 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4434 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4435 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4436 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4437 CPUID_SSE | CPUID_SSE2, 4438 .features[FEAT_1_ECX] = 4439 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR | 4440 CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_SSE41 | 4441 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4442 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | 4443 CPUID_EXT_AES | CPUID_EXT_XSAVE | CPUID_EXT_RDRAND, 4444 .features[FEAT_8000_0001_EDX] = 4445 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4446 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4447 .features[FEAT_8000_0001_ECX] = 4448 CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 4449 .features[FEAT_7_0_EBX] = 4450 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_ERMS | 4451 CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_SMAP | 4452 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_SHA_NI, 4453 .features[FEAT_7_0_EDX] = 4454 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES | 4455 CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4456 /* XSAVES is added in version 3 */ 4457 .features[FEAT_XSAVE] = 4458 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | CPUID_XSAVE_XGETBV1, 4459 .features[FEAT_6_EAX] = 4460 CPUID_6_EAX_ARAT, 4461 .features[FEAT_ARCH_CAPABILITIES] = 4462 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY, 4463 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 4464 MSR_VMX_BASIC_TRUE_CTLS, 4465 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 4466 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 4467 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 4468 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 4469 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 4470 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 4471 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4472 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4473 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4474 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 4475 .features[FEAT_VMX_EXIT_CTLS] = 4476 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4477 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4478 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 4479 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4480 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4481 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 4482 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 4483 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 4484 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 4485 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 4486 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4487 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4488 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4489 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4490 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4491 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 4492 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 4493 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 4494 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 4495 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4496 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4497 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4498 .features[FEAT_VMX_SECONDARY_CTLS] = 4499 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4500 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 4501 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 4502 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4503 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4504 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4505 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4506 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4507 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4508 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 4509 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 4510 .xlevel = 0x80000008, 4511 .model_id = "Intel Atom Processor (Denverton)", 4512 .versions = (X86CPUVersionDefinition[]) { 4513 { .version = 1 }, 4514 { 4515 .version = 2, 4516 .note = "no MPX, no MONITOR", 4517 .props = (PropValue[]) { 4518 { "monitor", "off" }, 4519 { "mpx", "off" }, 4520 { /* end of list */ }, 4521 }, 4522 }, 4523 { 4524 .version = 3, 4525 .note = "XSAVES, no MPX, no MONITOR", 4526 .props = (PropValue[]) { 4527 { "xsaves", "on" }, 4528 { "vmx-xsaves", "on" }, 4529 { /* end of list */ }, 4530 }, 4531 }, 4532 { /* end of list */ }, 4533 }, 4534 }, 4535 { 4536 .name = "Snowridge", 4537 .level = 27, 4538 .vendor = CPUID_VENDOR_INTEL, 4539 .family = 6, 4540 .model = 134, 4541 .stepping = 1, 4542 .features[FEAT_1_EDX] = 4543 /* missing: CPUID_PN CPUID_IA64 */ 4544 /* missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 4545 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | 4546 CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_MCE | 4547 CPUID_CX8 | CPUID_APIC | CPUID_SEP | 4548 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4549 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | 4550 CPUID_MMX | 4551 CPUID_FXSR | CPUID_SSE | CPUID_SSE2, 4552 .features[FEAT_1_ECX] = 4553 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR | 4554 CPUID_EXT_SSSE3 | 4555 CPUID_EXT_CX16 | 4556 CPUID_EXT_SSE41 | 4557 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4558 CPUID_EXT_POPCNT | 4559 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | CPUID_EXT_XSAVE | 4560 CPUID_EXT_RDRAND, 4561 .features[FEAT_8000_0001_EDX] = 4562 CPUID_EXT2_SYSCALL | 4563 CPUID_EXT2_NX | 4564 CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 4565 CPUID_EXT2_LM, 4566 .features[FEAT_8000_0001_ECX] = 4567 CPUID_EXT3_LAHF_LM | 4568 CPUID_EXT3_3DNOWPREFETCH, 4569 .features[FEAT_7_0_EBX] = 4570 CPUID_7_0_EBX_FSGSBASE | 4571 CPUID_7_0_EBX_SMEP | 4572 CPUID_7_0_EBX_ERMS | 4573 CPUID_7_0_EBX_MPX | /* missing bits 13, 15 */ 4574 CPUID_7_0_EBX_RDSEED | 4575 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 4576 CPUID_7_0_EBX_CLWB | 4577 CPUID_7_0_EBX_SHA_NI, 4578 .features[FEAT_7_0_ECX] = 4579 CPUID_7_0_ECX_UMIP | 4580 /* missing bit 5 */ 4581 CPUID_7_0_ECX_GFNI | 4582 CPUID_7_0_ECX_MOVDIRI | CPUID_7_0_ECX_CLDEMOTE | 4583 CPUID_7_0_ECX_MOVDIR64B, 4584 .features[FEAT_7_0_EDX] = 4585 CPUID_7_0_EDX_SPEC_CTRL | 4586 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD | 4587 CPUID_7_0_EDX_CORE_CAPABILITY, 4588 .features[FEAT_CORE_CAPABILITY] = 4589 MSR_CORE_CAP_SPLIT_LOCK_DETECT, 4590 /* XSAVES is added in version 3 */ 4591 .features[FEAT_XSAVE] = 4592 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4593 CPUID_XSAVE_XGETBV1, 4594 .features[FEAT_6_EAX] = 4595 CPUID_6_EAX_ARAT, 4596 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 4597 MSR_VMX_BASIC_TRUE_CTLS, 4598 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 4599 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 4600 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 4601 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 4602 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 4603 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 4604 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4605 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4606 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4607 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 4608 .features[FEAT_VMX_EXIT_CTLS] = 4609 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4610 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4611 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 4612 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4613 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4614 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 4615 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 4616 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 4617 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 4618 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 4619 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4620 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4621 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4622 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4623 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4624 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 4625 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 4626 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 4627 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 4628 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4629 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4630 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4631 .features[FEAT_VMX_SECONDARY_CTLS] = 4632 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4633 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 4634 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 4635 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4636 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4637 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4638 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4639 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4640 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4641 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 4642 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 4643 .xlevel = 0x80000008, 4644 .model_id = "Intel Atom Processor (SnowRidge)", 4645 .versions = (X86CPUVersionDefinition[]) { 4646 { .version = 1 }, 4647 { 4648 .version = 2, 4649 .props = (PropValue[]) { 4650 { "mpx", "off" }, 4651 { "model-id", "Intel Atom Processor (Snowridge, no MPX)" }, 4652 { /* end of list */ }, 4653 }, 4654 }, 4655 { 4656 .version = 3, 4657 .note = "XSAVES, no MPX", 4658 .props = (PropValue[]) { 4659 { "xsaves", "on" }, 4660 { "vmx-xsaves", "on" }, 4661 { /* end of list */ }, 4662 }, 4663 }, 4664 { 4665 .version = 4, 4666 .note = "no split lock detect, no core-capability", 4667 .props = (PropValue[]) { 4668 { "split-lock-detect", "off" }, 4669 { "core-capability", "off" }, 4670 { /* end of list */ }, 4671 }, 4672 }, 4673 { /* end of list */ }, 4674 }, 4675 }, 4676 { 4677 .name = "KnightsMill", 4678 .level = 0xd, 4679 .vendor = CPUID_VENDOR_INTEL, 4680 .family = 6, 4681 .model = 133, 4682 .stepping = 0, 4683 .features[FEAT_1_EDX] = 4684 CPUID_VME | CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | 4685 CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | 4686 CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | 4687 CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | 4688 CPUID_PSE | CPUID_DE | CPUID_FP87, 4689 .features[FEAT_1_ECX] = 4690 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 4691 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 4692 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 4693 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 4694 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 4695 CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4696 .features[FEAT_8000_0001_EDX] = 4697 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 4698 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 4699 .features[FEAT_8000_0001_ECX] = 4700 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 4701 .features[FEAT_7_0_EBX] = 4702 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4703 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 4704 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_AVX512F | 4705 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_AVX512PF | 4706 CPUID_7_0_EBX_AVX512ER, 4707 .features[FEAT_7_0_ECX] = 4708 CPUID_7_0_ECX_AVX512_VPOPCNTDQ, 4709 .features[FEAT_7_0_EDX] = 4710 CPUID_7_0_EDX_AVX512_4VNNIW | CPUID_7_0_EDX_AVX512_4FMAPS, 4711 .features[FEAT_XSAVE] = 4712 CPUID_XSAVE_XSAVEOPT, 4713 .features[FEAT_6_EAX] = 4714 CPUID_6_EAX_ARAT, 4715 .xlevel = 0x80000008, 4716 .model_id = "Intel Xeon Phi Processor (Knights Mill)", 4717 }, 4718 { 4719 .name = "Opteron_G1", 4720 .level = 5, 4721 .vendor = CPUID_VENDOR_AMD, 4722 .family = 15, 4723 .model = 6, 4724 .stepping = 1, 4725 .features[FEAT_1_EDX] = 4726 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4727 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4728 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4729 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4730 CPUID_DE | CPUID_FP87, 4731 .features[FEAT_1_ECX] = 4732 CPUID_EXT_SSE3, 4733 .features[FEAT_8000_0001_EDX] = 4734 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 4735 .xlevel = 0x80000008, 4736 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)", 4737 }, 4738 { 4739 .name = "Opteron_G2", 4740 .level = 5, 4741 .vendor = CPUID_VENDOR_AMD, 4742 .family = 15, 4743 .model = 6, 4744 .stepping = 1, 4745 .features[FEAT_1_EDX] = 4746 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4747 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4748 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4749 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4750 CPUID_DE | CPUID_FP87, 4751 .features[FEAT_1_ECX] = 4752 CPUID_EXT_CX16 | CPUID_EXT_SSE3, 4753 .features[FEAT_8000_0001_EDX] = 4754 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 4755 .features[FEAT_8000_0001_ECX] = 4756 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, 4757 .xlevel = 0x80000008, 4758 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)", 4759 }, 4760 { 4761 .name = "Opteron_G3", 4762 .level = 5, 4763 .vendor = CPUID_VENDOR_AMD, 4764 .family = 16, 4765 .model = 2, 4766 .stepping = 3, 4767 .features[FEAT_1_EDX] = 4768 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4769 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4770 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4771 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4772 CPUID_DE | CPUID_FP87, 4773 .features[FEAT_1_ECX] = 4774 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR | 4775 CPUID_EXT_SSE3, 4776 .features[FEAT_8000_0001_EDX] = 4777 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL | 4778 CPUID_EXT2_RDTSCP, 4779 .features[FEAT_8000_0001_ECX] = 4780 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | 4781 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, 4782 .xlevel = 0x80000008, 4783 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)", 4784 }, 4785 { 4786 .name = "Opteron_G4", 4787 .level = 0xd, 4788 .vendor = CPUID_VENDOR_AMD, 4789 .family = 21, 4790 .model = 1, 4791 .stepping = 2, 4792 .features[FEAT_1_EDX] = 4793 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4794 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4795 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4796 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4797 CPUID_DE | CPUID_FP87, 4798 .features[FEAT_1_ECX] = 4799 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 4800 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 4801 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 4802 CPUID_EXT_SSE3, 4803 .features[FEAT_8000_0001_EDX] = 4804 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX | 4805 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP, 4806 .features[FEAT_8000_0001_ECX] = 4807 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP | 4808 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | 4809 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | 4810 CPUID_EXT3_LAHF_LM, 4811 .features[FEAT_SVM] = 4812 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 4813 /* no xsaveopt! */ 4814 .xlevel = 0x8000001A, 4815 .model_id = "AMD Opteron 62xx class CPU", 4816 }, 4817 { 4818 .name = "Opteron_G5", 4819 .level = 0xd, 4820 .vendor = CPUID_VENDOR_AMD, 4821 .family = 21, 4822 .model = 2, 4823 .stepping = 0, 4824 .features[FEAT_1_EDX] = 4825 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4826 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4827 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4828 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4829 CPUID_DE | CPUID_FP87, 4830 .features[FEAT_1_ECX] = 4831 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE | 4832 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | 4833 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA | 4834 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 4835 .features[FEAT_8000_0001_EDX] = 4836 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX | 4837 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP, 4838 .features[FEAT_8000_0001_ECX] = 4839 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP | 4840 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | 4841 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | 4842 CPUID_EXT3_LAHF_LM, 4843 .features[FEAT_SVM] = 4844 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 4845 /* no xsaveopt! */ 4846 .xlevel = 0x8000001A, 4847 .model_id = "AMD Opteron 63xx class CPU", 4848 }, 4849 { 4850 .name = "EPYC", 4851 .level = 0xd, 4852 .vendor = CPUID_VENDOR_AMD, 4853 .family = 23, 4854 .model = 1, 4855 .stepping = 2, 4856 .features[FEAT_1_EDX] = 4857 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 4858 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 4859 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 4860 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 4861 CPUID_VME | CPUID_FP87, 4862 .features[FEAT_1_ECX] = 4863 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 4864 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 4865 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 4866 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 4867 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 4868 .features[FEAT_8000_0001_EDX] = 4869 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 4870 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 4871 CPUID_EXT2_SYSCALL, 4872 .features[FEAT_8000_0001_ECX] = 4873 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 4874 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 4875 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 4876 CPUID_EXT3_TOPOEXT, 4877 .features[FEAT_7_0_EBX] = 4878 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4879 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 4880 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 4881 CPUID_7_0_EBX_SHA_NI, 4882 .features[FEAT_XSAVE] = 4883 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4884 CPUID_XSAVE_XGETBV1, 4885 .features[FEAT_6_EAX] = 4886 CPUID_6_EAX_ARAT, 4887 .features[FEAT_SVM] = 4888 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 4889 .xlevel = 0x8000001E, 4890 .model_id = "AMD EPYC Processor", 4891 .cache_info = &epyc_cache_info, 4892 .versions = (X86CPUVersionDefinition[]) { 4893 { .version = 1 }, 4894 { 4895 .version = 2, 4896 .alias = "EPYC-IBPB", 4897 .props = (PropValue[]) { 4898 { "ibpb", "on" }, 4899 { "model-id", 4900 "AMD EPYC Processor (with IBPB)" }, 4901 { /* end of list */ } 4902 } 4903 }, 4904 { 4905 .version = 3, 4906 .props = (PropValue[]) { 4907 { "ibpb", "on" }, 4908 { "perfctr-core", "on" }, 4909 { "clzero", "on" }, 4910 { "xsaveerptr", "on" }, 4911 { "xsaves", "on" }, 4912 { "model-id", 4913 "AMD EPYC Processor" }, 4914 { /* end of list */ } 4915 } 4916 }, 4917 { 4918 .version = 4, 4919 .props = (PropValue[]) { 4920 { "model-id", 4921 "AMD EPYC-v4 Processor" }, 4922 { /* end of list */ } 4923 }, 4924 .cache_info = &epyc_v4_cache_info 4925 }, 4926 { /* end of list */ } 4927 } 4928 }, 4929 { 4930 .name = "Dhyana", 4931 .level = 0xd, 4932 .vendor = CPUID_VENDOR_HYGON, 4933 .family = 24, 4934 .model = 0, 4935 .stepping = 1, 4936 .features[FEAT_1_EDX] = 4937 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 4938 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 4939 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 4940 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 4941 CPUID_VME | CPUID_FP87, 4942 .features[FEAT_1_ECX] = 4943 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 4944 CPUID_EXT_XSAVE | CPUID_EXT_POPCNT | 4945 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 4946 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 4947 CPUID_EXT_MONITOR | CPUID_EXT_SSE3, 4948 .features[FEAT_8000_0001_EDX] = 4949 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 4950 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 4951 CPUID_EXT2_SYSCALL, 4952 .features[FEAT_8000_0001_ECX] = 4953 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 4954 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 4955 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 4956 CPUID_EXT3_TOPOEXT, 4957 .features[FEAT_8000_0008_EBX] = 4958 CPUID_8000_0008_EBX_IBPB, 4959 .features[FEAT_7_0_EBX] = 4960 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4961 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 4962 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT, 4963 /* XSAVES is added in version 2 */ 4964 .features[FEAT_XSAVE] = 4965 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4966 CPUID_XSAVE_XGETBV1, 4967 .features[FEAT_6_EAX] = 4968 CPUID_6_EAX_ARAT, 4969 .features[FEAT_SVM] = 4970 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 4971 .xlevel = 0x8000001E, 4972 .model_id = "Hygon Dhyana Processor", 4973 .cache_info = &epyc_cache_info, 4974 .versions = (X86CPUVersionDefinition[]) { 4975 { .version = 1 }, 4976 { .version = 2, 4977 .note = "XSAVES", 4978 .props = (PropValue[]) { 4979 { "xsaves", "on" }, 4980 { /* end of list */ } 4981 }, 4982 }, 4983 { /* end of list */ } 4984 } 4985 }, 4986 { 4987 .name = "EPYC-Rome", 4988 .level = 0xd, 4989 .vendor = CPUID_VENDOR_AMD, 4990 .family = 23, 4991 .model = 49, 4992 .stepping = 0, 4993 .features[FEAT_1_EDX] = 4994 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 4995 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 4996 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 4997 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 4998 CPUID_VME | CPUID_FP87, 4999 .features[FEAT_1_ECX] = 5000 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5001 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 5002 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5003 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 5004 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 5005 .features[FEAT_8000_0001_EDX] = 5006 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5007 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5008 CPUID_EXT2_SYSCALL, 5009 .features[FEAT_8000_0001_ECX] = 5010 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5011 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5012 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5013 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 5014 .features[FEAT_8000_0008_EBX] = 5015 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 5016 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 5017 CPUID_8000_0008_EBX_STIBP, 5018 .features[FEAT_7_0_EBX] = 5019 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5020 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 5021 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 5022 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB, 5023 .features[FEAT_7_0_ECX] = 5024 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID, 5025 .features[FEAT_XSAVE] = 5026 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5027 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 5028 .features[FEAT_6_EAX] = 5029 CPUID_6_EAX_ARAT, 5030 .features[FEAT_SVM] = 5031 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 5032 .xlevel = 0x8000001E, 5033 .model_id = "AMD EPYC-Rome Processor", 5034 .cache_info = &epyc_rome_cache_info, 5035 .versions = (X86CPUVersionDefinition[]) { 5036 { .version = 1 }, 5037 { 5038 .version = 2, 5039 .props = (PropValue[]) { 5040 { "ibrs", "on" }, 5041 { "amd-ssbd", "on" }, 5042 { /* end of list */ } 5043 } 5044 }, 5045 { 5046 .version = 3, 5047 .props = (PropValue[]) { 5048 { "model-id", 5049 "AMD EPYC-Rome-v3 Processor" }, 5050 { /* end of list */ } 5051 }, 5052 .cache_info = &epyc_rome_v3_cache_info 5053 }, 5054 { 5055 .version = 4, 5056 .props = (PropValue[]) { 5057 /* Erratum 1386 */ 5058 { "model-id", 5059 "AMD EPYC-Rome-v4 Processor (no XSAVES)" }, 5060 { "xsaves", "off" }, 5061 { /* end of list */ } 5062 }, 5063 }, 5064 { /* end of list */ } 5065 } 5066 }, 5067 { 5068 .name = "EPYC-Milan", 5069 .level = 0xd, 5070 .vendor = CPUID_VENDOR_AMD, 5071 .family = 25, 5072 .model = 1, 5073 .stepping = 1, 5074 .features[FEAT_1_EDX] = 5075 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 5076 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 5077 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 5078 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 5079 CPUID_VME | CPUID_FP87, 5080 .features[FEAT_1_ECX] = 5081 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5082 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 5083 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5084 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 5085 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 5086 CPUID_EXT_PCID, 5087 .features[FEAT_8000_0001_EDX] = 5088 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5089 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5090 CPUID_EXT2_SYSCALL, 5091 .features[FEAT_8000_0001_ECX] = 5092 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5093 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5094 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5095 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 5096 .features[FEAT_8000_0008_EBX] = 5097 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 5098 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 5099 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | 5100 CPUID_8000_0008_EBX_AMD_SSBD, 5101 .features[FEAT_7_0_EBX] = 5102 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5103 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 5104 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 5105 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_ERMS | 5106 CPUID_7_0_EBX_INVPCID, 5107 .features[FEAT_7_0_ECX] = 5108 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_PKU, 5109 .features[FEAT_7_0_EDX] = 5110 CPUID_7_0_EDX_FSRM, 5111 .features[FEAT_XSAVE] = 5112 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5113 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 5114 .features[FEAT_6_EAX] = 5115 CPUID_6_EAX_ARAT, 5116 .features[FEAT_SVM] = 5117 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE | CPUID_SVM_SVME_ADDR_CHK, 5118 .xlevel = 0x8000001E, 5119 .model_id = "AMD EPYC-Milan Processor", 5120 .cache_info = &epyc_milan_cache_info, 5121 .versions = (X86CPUVersionDefinition[]) { 5122 { .version = 1 }, 5123 { 5124 .version = 2, 5125 .props = (PropValue[]) { 5126 { "model-id", 5127 "AMD EPYC-Milan-v2 Processor" }, 5128 { "vaes", "on" }, 5129 { "vpclmulqdq", "on" }, 5130 { "stibp-always-on", "on" }, 5131 { "amd-psfd", "on" }, 5132 { "no-nested-data-bp", "on" }, 5133 { "lfence-always-serializing", "on" }, 5134 { "null-sel-clr-base", "on" }, 5135 { /* end of list */ } 5136 }, 5137 .cache_info = &epyc_milan_v2_cache_info 5138 }, 5139 { /* end of list */ } 5140 } 5141 }, 5142 { 5143 .name = "EPYC-Genoa", 5144 .level = 0xd, 5145 .vendor = CPUID_VENDOR_AMD, 5146 .family = 25, 5147 .model = 17, 5148 .stepping = 0, 5149 .features[FEAT_1_EDX] = 5150 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 5151 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 5152 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 5153 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 5154 CPUID_VME | CPUID_FP87, 5155 .features[FEAT_1_ECX] = 5156 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5157 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 5158 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5159 CPUID_EXT_PCID | CPUID_EXT_CX16 | CPUID_EXT_FMA | 5160 CPUID_EXT_SSSE3 | CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | 5161 CPUID_EXT_SSE3, 5162 .features[FEAT_8000_0001_EDX] = 5163 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5164 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5165 CPUID_EXT2_SYSCALL, 5166 .features[FEAT_8000_0001_ECX] = 5167 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5168 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5169 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5170 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 5171 .features[FEAT_8000_0008_EBX] = 5172 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 5173 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 5174 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | 5175 CPUID_8000_0008_EBX_STIBP_ALWAYS_ON | 5176 CPUID_8000_0008_EBX_AMD_SSBD | CPUID_8000_0008_EBX_AMD_PSFD, 5177 .features[FEAT_8000_0021_EAX] = 5178 CPUID_8000_0021_EAX_No_NESTED_DATA_BP | 5179 CPUID_8000_0021_EAX_LFENCE_ALWAYS_SERIALIZING | 5180 CPUID_8000_0021_EAX_NULL_SEL_CLR_BASE | 5181 CPUID_8000_0021_EAX_AUTO_IBRS, 5182 .features[FEAT_7_0_EBX] = 5183 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5184 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 5185 CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_AVX512F | 5186 CPUID_7_0_EBX_AVX512DQ | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 5187 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_AVX512IFMA | 5188 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB | 5189 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | 5190 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, 5191 .features[FEAT_7_0_ECX] = 5192 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 5193 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 5194 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 5195 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 5196 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | 5197 CPUID_7_0_ECX_RDPID, 5198 .features[FEAT_7_0_EDX] = 5199 CPUID_7_0_EDX_FSRM, 5200 .features[FEAT_7_1_EAX] = 5201 CPUID_7_1_EAX_AVX512_BF16, 5202 .features[FEAT_XSAVE] = 5203 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5204 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 5205 .features[FEAT_6_EAX] = 5206 CPUID_6_EAX_ARAT, 5207 .features[FEAT_SVM] = 5208 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE | CPUID_SVM_VNMI | 5209 CPUID_SVM_SVME_ADDR_CHK, 5210 .xlevel = 0x80000022, 5211 .model_id = "AMD EPYC-Genoa Processor", 5212 .cache_info = &epyc_genoa_cache_info, 5213 }, 5214 }; 5215 5216 /* 5217 * We resolve CPU model aliases using -v1 when using "-machine 5218 * none", but this is just for compatibility while libvirt isn't 5219 * adapted to resolve CPU model versions before creating VMs. 5220 * See "Runnability guarantee of CPU models" at 5221 * docs/about/deprecated.rst. 5222 */ 5223 X86CPUVersion default_cpu_version = 1; 5224 5225 void x86_cpu_set_default_version(X86CPUVersion version) 5226 { 5227 /* Translating CPU_VERSION_AUTO to CPU_VERSION_AUTO doesn't make sense */ 5228 assert(version != CPU_VERSION_AUTO); 5229 default_cpu_version = version; 5230 } 5231 5232 static X86CPUVersion x86_cpu_model_last_version(const X86CPUModel *model) 5233 { 5234 int v = 0; 5235 const X86CPUVersionDefinition *vdef = 5236 x86_cpu_def_get_versions(model->cpudef); 5237 while (vdef->version) { 5238 v = vdef->version; 5239 vdef++; 5240 } 5241 return v; 5242 } 5243 5244 /* Return the actual version being used for a specific CPU model */ 5245 static X86CPUVersion x86_cpu_model_resolve_version(const X86CPUModel *model) 5246 { 5247 X86CPUVersion v = model->version; 5248 if (v == CPU_VERSION_AUTO) { 5249 v = default_cpu_version; 5250 } 5251 if (v == CPU_VERSION_LATEST) { 5252 return x86_cpu_model_last_version(model); 5253 } 5254 return v; 5255 } 5256 5257 static Property max_x86_cpu_properties[] = { 5258 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true), 5259 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false), 5260 DEFINE_PROP_END_OF_LIST() 5261 }; 5262 5263 static void max_x86_cpu_realize(DeviceState *dev, Error **errp) 5264 { 5265 Object *obj = OBJECT(dev); 5266 5267 if (!object_property_get_int(obj, "family", &error_abort)) { 5268 if (X86_CPU(obj)->env.features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 5269 object_property_set_int(obj, "family", 15, &error_abort); 5270 object_property_set_int(obj, "model", 107, &error_abort); 5271 object_property_set_int(obj, "stepping", 1, &error_abort); 5272 } else { 5273 object_property_set_int(obj, "family", 6, &error_abort); 5274 object_property_set_int(obj, "model", 6, &error_abort); 5275 object_property_set_int(obj, "stepping", 3, &error_abort); 5276 } 5277 } 5278 5279 x86_cpu_realizefn(dev, errp); 5280 } 5281 5282 static void max_x86_cpu_class_init(ObjectClass *oc, void *data) 5283 { 5284 DeviceClass *dc = DEVICE_CLASS(oc); 5285 X86CPUClass *xcc = X86_CPU_CLASS(oc); 5286 5287 xcc->ordering = 9; 5288 5289 xcc->model_description = 5290 "Enables all features supported by the accelerator in the current host"; 5291 5292 device_class_set_props(dc, max_x86_cpu_properties); 5293 dc->realize = max_x86_cpu_realize; 5294 } 5295 5296 static void max_x86_cpu_initfn(Object *obj) 5297 { 5298 X86CPU *cpu = X86_CPU(obj); 5299 5300 /* We can't fill the features array here because we don't know yet if 5301 * "migratable" is true or false. 5302 */ 5303 cpu->max_features = true; 5304 object_property_set_bool(OBJECT(cpu), "pmu", true, &error_abort); 5305 5306 /* 5307 * these defaults are used for TCG and all other accelerators 5308 * besides KVM and HVF, which overwrite these values 5309 */ 5310 object_property_set_str(OBJECT(cpu), "vendor", CPUID_VENDOR_AMD, 5311 &error_abort); 5312 object_property_set_str(OBJECT(cpu), "model-id", 5313 "QEMU TCG CPU version " QEMU_HW_VERSION, 5314 &error_abort); 5315 } 5316 5317 static const TypeInfo max_x86_cpu_type_info = { 5318 .name = X86_CPU_TYPE_NAME("max"), 5319 .parent = TYPE_X86_CPU, 5320 .instance_init = max_x86_cpu_initfn, 5321 .class_init = max_x86_cpu_class_init, 5322 }; 5323 5324 static char *feature_word_description(FeatureWordInfo *f, uint32_t bit) 5325 { 5326 assert(f->type == CPUID_FEATURE_WORD || f->type == MSR_FEATURE_WORD); 5327 5328 switch (f->type) { 5329 case CPUID_FEATURE_WORD: 5330 { 5331 const char *reg = get_register_name_32(f->cpuid.reg); 5332 assert(reg); 5333 return g_strdup_printf("CPUID.%02XH:%s", 5334 f->cpuid.eax, reg); 5335 } 5336 case MSR_FEATURE_WORD: 5337 return g_strdup_printf("MSR(%02XH)", 5338 f->msr.index); 5339 } 5340 5341 return NULL; 5342 } 5343 5344 static bool x86_cpu_have_filtered_features(X86CPU *cpu) 5345 { 5346 FeatureWord w; 5347 5348 for (w = 0; w < FEATURE_WORDS; w++) { 5349 if (cpu->filtered_features[w]) { 5350 return true; 5351 } 5352 } 5353 5354 return false; 5355 } 5356 5357 static void mark_unavailable_features(X86CPU *cpu, FeatureWord w, uint64_t mask, 5358 const char *verbose_prefix) 5359 { 5360 CPUX86State *env = &cpu->env; 5361 FeatureWordInfo *f = &feature_word_info[w]; 5362 int i; 5363 5364 if (!cpu->force_features) { 5365 env->features[w] &= ~mask; 5366 } 5367 cpu->filtered_features[w] |= mask; 5368 5369 if (!verbose_prefix) { 5370 return; 5371 } 5372 5373 for (i = 0; i < 64; ++i) { 5374 if ((1ULL << i) & mask) { 5375 g_autofree char *feat_word_str = feature_word_description(f, i); 5376 warn_report("%s: %s%s%s [bit %d]", 5377 verbose_prefix, 5378 feat_word_str, 5379 f->feat_names[i] ? "." : "", 5380 f->feat_names[i] ? f->feat_names[i] : "", i); 5381 } 5382 } 5383 } 5384 5385 static void x86_cpuid_version_get_family(Object *obj, Visitor *v, 5386 const char *name, void *opaque, 5387 Error **errp) 5388 { 5389 X86CPU *cpu = X86_CPU(obj); 5390 CPUX86State *env = &cpu->env; 5391 int64_t value; 5392 5393 value = (env->cpuid_version >> 8) & 0xf; 5394 if (value == 0xf) { 5395 value += (env->cpuid_version >> 20) & 0xff; 5396 } 5397 visit_type_int(v, name, &value, errp); 5398 } 5399 5400 static void x86_cpuid_version_set_family(Object *obj, Visitor *v, 5401 const char *name, void *opaque, 5402 Error **errp) 5403 { 5404 X86CPU *cpu = X86_CPU(obj); 5405 CPUX86State *env = &cpu->env; 5406 const int64_t min = 0; 5407 const int64_t max = 0xff + 0xf; 5408 int64_t value; 5409 5410 if (!visit_type_int(v, name, &value, errp)) { 5411 return; 5412 } 5413 if (value < min || value > max) { 5414 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", 5415 name ? name : "null", value, min, max); 5416 return; 5417 } 5418 5419 env->cpuid_version &= ~0xff00f00; 5420 if (value > 0x0f) { 5421 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20); 5422 } else { 5423 env->cpuid_version |= value << 8; 5424 } 5425 } 5426 5427 static void x86_cpuid_version_get_model(Object *obj, Visitor *v, 5428 const char *name, void *opaque, 5429 Error **errp) 5430 { 5431 X86CPU *cpu = X86_CPU(obj); 5432 CPUX86State *env = &cpu->env; 5433 int64_t value; 5434 5435 value = (env->cpuid_version >> 4) & 0xf; 5436 value |= ((env->cpuid_version >> 16) & 0xf) << 4; 5437 visit_type_int(v, name, &value, errp); 5438 } 5439 5440 static void x86_cpuid_version_set_model(Object *obj, Visitor *v, 5441 const char *name, void *opaque, 5442 Error **errp) 5443 { 5444 X86CPU *cpu = X86_CPU(obj); 5445 CPUX86State *env = &cpu->env; 5446 const int64_t min = 0; 5447 const int64_t max = 0xff; 5448 int64_t value; 5449 5450 if (!visit_type_int(v, name, &value, errp)) { 5451 return; 5452 } 5453 if (value < min || value > max) { 5454 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", 5455 name ? name : "null", value, min, max); 5456 return; 5457 } 5458 5459 env->cpuid_version &= ~0xf00f0; 5460 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16); 5461 } 5462 5463 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v, 5464 const char *name, void *opaque, 5465 Error **errp) 5466 { 5467 X86CPU *cpu = X86_CPU(obj); 5468 CPUX86State *env = &cpu->env; 5469 int64_t value; 5470 5471 value = env->cpuid_version & 0xf; 5472 visit_type_int(v, name, &value, errp); 5473 } 5474 5475 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v, 5476 const char *name, void *opaque, 5477 Error **errp) 5478 { 5479 X86CPU *cpu = X86_CPU(obj); 5480 CPUX86State *env = &cpu->env; 5481 const int64_t min = 0; 5482 const int64_t max = 0xf; 5483 int64_t value; 5484 5485 if (!visit_type_int(v, name, &value, errp)) { 5486 return; 5487 } 5488 if (value < min || value > max) { 5489 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", 5490 name ? name : "null", value, min, max); 5491 return; 5492 } 5493 5494 env->cpuid_version &= ~0xf; 5495 env->cpuid_version |= value & 0xf; 5496 } 5497 5498 static char *x86_cpuid_get_vendor(Object *obj, Error **errp) 5499 { 5500 X86CPU *cpu = X86_CPU(obj); 5501 CPUX86State *env = &cpu->env; 5502 char *value; 5503 5504 value = g_malloc(CPUID_VENDOR_SZ + 1); 5505 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2, 5506 env->cpuid_vendor3); 5507 return value; 5508 } 5509 5510 static void x86_cpuid_set_vendor(Object *obj, const char *value, 5511 Error **errp) 5512 { 5513 X86CPU *cpu = X86_CPU(obj); 5514 CPUX86State *env = &cpu->env; 5515 int i; 5516 5517 if (strlen(value) != CPUID_VENDOR_SZ) { 5518 error_setg(errp, "value of property 'vendor' must consist of" 5519 " exactly " stringify(CPUID_VENDOR_SZ) " characters"); 5520 return; 5521 } 5522 5523 env->cpuid_vendor1 = 0; 5524 env->cpuid_vendor2 = 0; 5525 env->cpuid_vendor3 = 0; 5526 for (i = 0; i < 4; i++) { 5527 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i); 5528 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i); 5529 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i); 5530 } 5531 } 5532 5533 static char *x86_cpuid_get_model_id(Object *obj, Error **errp) 5534 { 5535 X86CPU *cpu = X86_CPU(obj); 5536 CPUX86State *env = &cpu->env; 5537 char *value; 5538 int i; 5539 5540 value = g_malloc(48 + 1); 5541 for (i = 0; i < 48; i++) { 5542 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3)); 5543 } 5544 value[48] = '\0'; 5545 return value; 5546 } 5547 5548 static void x86_cpuid_set_model_id(Object *obj, const char *model_id, 5549 Error **errp) 5550 { 5551 X86CPU *cpu = X86_CPU(obj); 5552 CPUX86State *env = &cpu->env; 5553 int c, len, i; 5554 5555 if (model_id == NULL) { 5556 model_id = ""; 5557 } 5558 len = strlen(model_id); 5559 memset(env->cpuid_model, 0, 48); 5560 for (i = 0; i < 48; i++) { 5561 if (i >= len) { 5562 c = '\0'; 5563 } else { 5564 c = (uint8_t)model_id[i]; 5565 } 5566 env->cpuid_model[i >> 2] |= c << (8 * (i & 3)); 5567 } 5568 } 5569 5570 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name, 5571 void *opaque, Error **errp) 5572 { 5573 X86CPU *cpu = X86_CPU(obj); 5574 int64_t value; 5575 5576 value = cpu->env.tsc_khz * 1000; 5577 visit_type_int(v, name, &value, errp); 5578 } 5579 5580 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name, 5581 void *opaque, Error **errp) 5582 { 5583 X86CPU *cpu = X86_CPU(obj); 5584 const int64_t min = 0; 5585 const int64_t max = INT64_MAX; 5586 int64_t value; 5587 5588 if (!visit_type_int(v, name, &value, errp)) { 5589 return; 5590 } 5591 if (value < min || value > max) { 5592 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", 5593 name ? name : "null", value, min, max); 5594 return; 5595 } 5596 5597 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000; 5598 } 5599 5600 /* Generic getter for "feature-words" and "filtered-features" properties */ 5601 static void x86_cpu_get_feature_words(Object *obj, Visitor *v, 5602 const char *name, void *opaque, 5603 Error **errp) 5604 { 5605 uint64_t *array = (uint64_t *)opaque; 5606 FeatureWord w; 5607 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { }; 5608 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { }; 5609 X86CPUFeatureWordInfoList *list = NULL; 5610 5611 for (w = 0; w < FEATURE_WORDS; w++) { 5612 FeatureWordInfo *wi = &feature_word_info[w]; 5613 /* 5614 * We didn't have MSR features when "feature-words" was 5615 * introduced. Therefore skipped other type entries. 5616 */ 5617 if (wi->type != CPUID_FEATURE_WORD) { 5618 continue; 5619 } 5620 X86CPUFeatureWordInfo *qwi = &word_infos[w]; 5621 qwi->cpuid_input_eax = wi->cpuid.eax; 5622 qwi->has_cpuid_input_ecx = wi->cpuid.needs_ecx; 5623 qwi->cpuid_input_ecx = wi->cpuid.ecx; 5624 qwi->cpuid_register = x86_reg_info_32[wi->cpuid.reg].qapi_enum; 5625 qwi->features = array[w]; 5626 5627 /* List will be in reverse order, but order shouldn't matter */ 5628 list_entries[w].next = list; 5629 list_entries[w].value = &word_infos[w]; 5630 list = &list_entries[w]; 5631 } 5632 5633 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp); 5634 } 5635 5636 /* Convert all '_' in a feature string option name to '-', to make feature 5637 * name conform to QOM property naming rule, which uses '-' instead of '_'. 5638 */ 5639 static inline void feat2prop(char *s) 5640 { 5641 while ((s = strchr(s, '_'))) { 5642 *s = '-'; 5643 } 5644 } 5645 5646 /* Return the feature property name for a feature flag bit */ 5647 static const char *x86_cpu_feature_name(FeatureWord w, int bitnr) 5648 { 5649 const char *name; 5650 /* XSAVE components are automatically enabled by other features, 5651 * so return the original feature name instead 5652 */ 5653 if (w == FEAT_XSAVE_XCR0_LO || w == FEAT_XSAVE_XCR0_HI) { 5654 int comp = (w == FEAT_XSAVE_XCR0_HI) ? bitnr + 32 : bitnr; 5655 5656 if (comp < ARRAY_SIZE(x86_ext_save_areas) && 5657 x86_ext_save_areas[comp].bits) { 5658 w = x86_ext_save_areas[comp].feature; 5659 bitnr = ctz32(x86_ext_save_areas[comp].bits); 5660 } 5661 } 5662 5663 assert(bitnr < 64); 5664 assert(w < FEATURE_WORDS); 5665 name = feature_word_info[w].feat_names[bitnr]; 5666 assert(bitnr < 32 || !(name && feature_word_info[w].type == CPUID_FEATURE_WORD)); 5667 return name; 5668 } 5669 5670 /* Compatibility hack to maintain legacy +-feat semantic, 5671 * where +-feat overwrites any feature set by 5672 * feat=on|feat even if the later is parsed after +-feat 5673 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled) 5674 */ 5675 static GList *plus_features, *minus_features; 5676 5677 static gint compare_string(gconstpointer a, gconstpointer b) 5678 { 5679 return g_strcmp0(a, b); 5680 } 5681 5682 /* Parse "+feature,-feature,feature=foo" CPU feature string 5683 */ 5684 static void x86_cpu_parse_featurestr(const char *typename, char *features, 5685 Error **errp) 5686 { 5687 char *featurestr; /* Single 'key=value" string being parsed */ 5688 static bool cpu_globals_initialized; 5689 bool ambiguous = false; 5690 5691 if (cpu_globals_initialized) { 5692 return; 5693 } 5694 cpu_globals_initialized = true; 5695 5696 if (!features) { 5697 return; 5698 } 5699 5700 for (featurestr = strtok(features, ","); 5701 featurestr; 5702 featurestr = strtok(NULL, ",")) { 5703 const char *name; 5704 const char *val = NULL; 5705 char *eq = NULL; 5706 char num[32]; 5707 GlobalProperty *prop; 5708 5709 /* Compatibility syntax: */ 5710 if (featurestr[0] == '+') { 5711 plus_features = g_list_append(plus_features, 5712 g_strdup(featurestr + 1)); 5713 continue; 5714 } else if (featurestr[0] == '-') { 5715 minus_features = g_list_append(minus_features, 5716 g_strdup(featurestr + 1)); 5717 continue; 5718 } 5719 5720 eq = strchr(featurestr, '='); 5721 if (eq) { 5722 *eq++ = 0; 5723 val = eq; 5724 } else { 5725 val = "on"; 5726 } 5727 5728 feat2prop(featurestr); 5729 name = featurestr; 5730 5731 if (g_list_find_custom(plus_features, name, compare_string)) { 5732 warn_report("Ambiguous CPU model string. " 5733 "Don't mix both \"+%s\" and \"%s=%s\"", 5734 name, name, val); 5735 ambiguous = true; 5736 } 5737 if (g_list_find_custom(minus_features, name, compare_string)) { 5738 warn_report("Ambiguous CPU model string. " 5739 "Don't mix both \"-%s\" and \"%s=%s\"", 5740 name, name, val); 5741 ambiguous = true; 5742 } 5743 5744 /* Special case: */ 5745 if (!strcmp(name, "tsc-freq")) { 5746 int ret; 5747 uint64_t tsc_freq; 5748 5749 ret = qemu_strtosz_metric(val, NULL, &tsc_freq); 5750 if (ret < 0 || tsc_freq > INT64_MAX) { 5751 error_setg(errp, "bad numerical value %s", val); 5752 return; 5753 } 5754 snprintf(num, sizeof(num), "%" PRId64, tsc_freq); 5755 val = num; 5756 name = "tsc-frequency"; 5757 } 5758 5759 prop = g_new0(typeof(*prop), 1); 5760 prop->driver = typename; 5761 prop->property = g_strdup(name); 5762 prop->value = g_strdup(val); 5763 qdev_prop_register_global(prop); 5764 } 5765 5766 if (ambiguous) { 5767 warn_report("Compatibility of ambiguous CPU model " 5768 "strings won't be kept on future QEMU versions"); 5769 } 5770 } 5771 5772 static void x86_cpu_filter_features(X86CPU *cpu, bool verbose); 5773 5774 /* Build a list with the name of all features on a feature word array */ 5775 static void x86_cpu_list_feature_names(FeatureWordArray features, 5776 strList **list) 5777 { 5778 strList **tail = list; 5779 FeatureWord w; 5780 5781 for (w = 0; w < FEATURE_WORDS; w++) { 5782 uint64_t filtered = features[w]; 5783 int i; 5784 for (i = 0; i < 64; i++) { 5785 if (filtered & (1ULL << i)) { 5786 QAPI_LIST_APPEND(tail, g_strdup(x86_cpu_feature_name(w, i))); 5787 } 5788 } 5789 } 5790 } 5791 5792 static void x86_cpu_get_unavailable_features(Object *obj, Visitor *v, 5793 const char *name, void *opaque, 5794 Error **errp) 5795 { 5796 X86CPU *xc = X86_CPU(obj); 5797 strList *result = NULL; 5798 5799 x86_cpu_list_feature_names(xc->filtered_features, &result); 5800 visit_type_strList(v, "unavailable-features", &result, errp); 5801 } 5802 5803 /* Print all cpuid feature names in featureset 5804 */ 5805 static void listflags(GList *features) 5806 { 5807 size_t len = 0; 5808 GList *tmp; 5809 5810 for (tmp = features; tmp; tmp = tmp->next) { 5811 const char *name = tmp->data; 5812 if ((len + strlen(name) + 1) >= 75) { 5813 qemu_printf("\n"); 5814 len = 0; 5815 } 5816 qemu_printf("%s%s", len == 0 ? " " : " ", name); 5817 len += strlen(name) + 1; 5818 } 5819 qemu_printf("\n"); 5820 } 5821 5822 /* Sort alphabetically by type name, respecting X86CPUClass::ordering. */ 5823 static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b) 5824 { 5825 ObjectClass *class_a = (ObjectClass *)a; 5826 ObjectClass *class_b = (ObjectClass *)b; 5827 X86CPUClass *cc_a = X86_CPU_CLASS(class_a); 5828 X86CPUClass *cc_b = X86_CPU_CLASS(class_b); 5829 int ret; 5830 5831 if (cc_a->ordering != cc_b->ordering) { 5832 ret = cc_a->ordering - cc_b->ordering; 5833 } else { 5834 g_autofree char *name_a = x86_cpu_class_get_model_name(cc_a); 5835 g_autofree char *name_b = x86_cpu_class_get_model_name(cc_b); 5836 ret = strcmp(name_a, name_b); 5837 } 5838 return ret; 5839 } 5840 5841 static GSList *get_sorted_cpu_model_list(void) 5842 { 5843 GSList *list = object_class_get_list(TYPE_X86_CPU, false); 5844 list = g_slist_sort(list, x86_cpu_list_compare); 5845 return list; 5846 } 5847 5848 static char *x86_cpu_class_get_model_id(X86CPUClass *xc) 5849 { 5850 Object *obj = object_new_with_class(OBJECT_CLASS(xc)); 5851 char *r = object_property_get_str(obj, "model-id", &error_abort); 5852 object_unref(obj); 5853 return r; 5854 } 5855 5856 static char *x86_cpu_class_get_alias_of(X86CPUClass *cc) 5857 { 5858 X86CPUVersion version; 5859 5860 if (!cc->model || !cc->model->is_alias) { 5861 return NULL; 5862 } 5863 version = x86_cpu_model_resolve_version(cc->model); 5864 if (version <= 0) { 5865 return NULL; 5866 } 5867 return x86_cpu_versioned_model_name(cc->model->cpudef, version); 5868 } 5869 5870 static void x86_cpu_list_entry(gpointer data, gpointer user_data) 5871 { 5872 ObjectClass *oc = data; 5873 X86CPUClass *cc = X86_CPU_CLASS(oc); 5874 g_autofree char *name = x86_cpu_class_get_model_name(cc); 5875 g_autofree char *desc = g_strdup(cc->model_description); 5876 g_autofree char *alias_of = x86_cpu_class_get_alias_of(cc); 5877 g_autofree char *model_id = x86_cpu_class_get_model_id(cc); 5878 5879 if (!desc && alias_of) { 5880 if (cc->model && cc->model->version == CPU_VERSION_AUTO) { 5881 desc = g_strdup("(alias configured by machine type)"); 5882 } else { 5883 desc = g_strdup_printf("(alias of %s)", alias_of); 5884 } 5885 } 5886 if (!desc && cc->model && cc->model->note) { 5887 desc = g_strdup_printf("%s [%s]", model_id, cc->model->note); 5888 } 5889 if (!desc) { 5890 desc = g_strdup_printf("%s", model_id); 5891 } 5892 5893 if (cc->model && cc->model->cpudef->deprecation_note) { 5894 g_autofree char *olddesc = desc; 5895 desc = g_strdup_printf("%s (deprecated)", olddesc); 5896 } 5897 5898 qemu_printf(" %-20s %s\n", name, desc); 5899 } 5900 5901 /* list available CPU models and flags */ 5902 void x86_cpu_list(void) 5903 { 5904 int i, j; 5905 GSList *list; 5906 GList *names = NULL; 5907 5908 qemu_printf("Available CPUs:\n"); 5909 list = get_sorted_cpu_model_list(); 5910 g_slist_foreach(list, x86_cpu_list_entry, NULL); 5911 g_slist_free(list); 5912 5913 names = NULL; 5914 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) { 5915 FeatureWordInfo *fw = &feature_word_info[i]; 5916 for (j = 0; j < 64; j++) { 5917 if (fw->feat_names[j]) { 5918 names = g_list_append(names, (gpointer)fw->feat_names[j]); 5919 } 5920 } 5921 } 5922 5923 names = g_list_sort(names, (GCompareFunc)strcmp); 5924 5925 qemu_printf("\nRecognized CPUID flags:\n"); 5926 listflags(names); 5927 qemu_printf("\n"); 5928 g_list_free(names); 5929 } 5930 5931 #ifndef CONFIG_USER_ONLY 5932 5933 /* Check for missing features that may prevent the CPU class from 5934 * running using the current machine and accelerator. 5935 */ 5936 static void x86_cpu_class_check_missing_features(X86CPUClass *xcc, 5937 strList **list) 5938 { 5939 strList **tail = list; 5940 X86CPU *xc; 5941 Error *err = NULL; 5942 5943 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) { 5944 QAPI_LIST_APPEND(tail, g_strdup("kvm")); 5945 return; 5946 } 5947 5948 xc = X86_CPU(object_new_with_class(OBJECT_CLASS(xcc))); 5949 5950 x86_cpu_expand_features(xc, &err); 5951 if (err) { 5952 /* Errors at x86_cpu_expand_features should never happen, 5953 * but in case it does, just report the model as not 5954 * runnable at all using the "type" property. 5955 */ 5956 QAPI_LIST_APPEND(tail, g_strdup("type")); 5957 error_free(err); 5958 } 5959 5960 x86_cpu_filter_features(xc, false); 5961 5962 x86_cpu_list_feature_names(xc->filtered_features, tail); 5963 5964 object_unref(OBJECT(xc)); 5965 } 5966 5967 static void x86_cpu_definition_entry(gpointer data, gpointer user_data) 5968 { 5969 ObjectClass *oc = data; 5970 X86CPUClass *cc = X86_CPU_CLASS(oc); 5971 CpuDefinitionInfoList **cpu_list = user_data; 5972 CpuDefinitionInfo *info; 5973 5974 info = g_malloc0(sizeof(*info)); 5975 info->name = x86_cpu_class_get_model_name(cc); 5976 x86_cpu_class_check_missing_features(cc, &info->unavailable_features); 5977 info->has_unavailable_features = true; 5978 info->q_typename = g_strdup(object_class_get_name(oc)); 5979 info->migration_safe = cc->migration_safe; 5980 info->has_migration_safe = true; 5981 info->q_static = cc->static_model; 5982 if (cc->model && cc->model->cpudef->deprecation_note) { 5983 info->deprecated = true; 5984 } else { 5985 info->deprecated = false; 5986 } 5987 /* 5988 * Old machine types won't report aliases, so that alias translation 5989 * doesn't break compatibility with previous QEMU versions. 5990 */ 5991 if (default_cpu_version != CPU_VERSION_LEGACY) { 5992 info->alias_of = x86_cpu_class_get_alias_of(cc); 5993 } 5994 5995 QAPI_LIST_PREPEND(*cpu_list, info); 5996 } 5997 5998 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) 5999 { 6000 CpuDefinitionInfoList *cpu_list = NULL; 6001 GSList *list = get_sorted_cpu_model_list(); 6002 g_slist_foreach(list, x86_cpu_definition_entry, &cpu_list); 6003 g_slist_free(list); 6004 return cpu_list; 6005 } 6006 6007 #endif /* !CONFIG_USER_ONLY */ 6008 6009 uint64_t x86_cpu_get_supported_feature_word(FeatureWord w, 6010 bool migratable_only) 6011 { 6012 FeatureWordInfo *wi = &feature_word_info[w]; 6013 uint64_t r = 0; 6014 6015 if (kvm_enabled()) { 6016 switch (wi->type) { 6017 case CPUID_FEATURE_WORD: 6018 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid.eax, 6019 wi->cpuid.ecx, 6020 wi->cpuid.reg); 6021 break; 6022 case MSR_FEATURE_WORD: 6023 r = kvm_arch_get_supported_msr_feature(kvm_state, 6024 wi->msr.index); 6025 break; 6026 } 6027 } else if (hvf_enabled()) { 6028 if (wi->type != CPUID_FEATURE_WORD) { 6029 return 0; 6030 } 6031 r = hvf_get_supported_cpuid(wi->cpuid.eax, 6032 wi->cpuid.ecx, 6033 wi->cpuid.reg); 6034 } else if (tcg_enabled()) { 6035 r = wi->tcg_features; 6036 } else { 6037 return ~0; 6038 } 6039 #ifndef TARGET_X86_64 6040 if (w == FEAT_8000_0001_EDX) { 6041 /* 6042 * 32-bit TCG can emulate 64-bit compatibility mode. If there is no 6043 * way for userspace to get out of its 32-bit jail, we can leave 6044 * the LM bit set. 6045 */ 6046 uint32_t unavail = tcg_enabled() 6047 ? CPUID_EXT2_LM & ~CPUID_EXT2_KERNEL_FEATURES 6048 : CPUID_EXT2_LM; 6049 r &= ~unavail; 6050 } 6051 #endif 6052 if (migratable_only) { 6053 r &= x86_cpu_get_migratable_flags(w); 6054 } 6055 return r; 6056 } 6057 6058 static void x86_cpu_get_supported_cpuid(uint32_t func, uint32_t index, 6059 uint32_t *eax, uint32_t *ebx, 6060 uint32_t *ecx, uint32_t *edx) 6061 { 6062 if (kvm_enabled()) { 6063 *eax = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EAX); 6064 *ebx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EBX); 6065 *ecx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_ECX); 6066 *edx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EDX); 6067 } else if (hvf_enabled()) { 6068 *eax = hvf_get_supported_cpuid(func, index, R_EAX); 6069 *ebx = hvf_get_supported_cpuid(func, index, R_EBX); 6070 *ecx = hvf_get_supported_cpuid(func, index, R_ECX); 6071 *edx = hvf_get_supported_cpuid(func, index, R_EDX); 6072 } else { 6073 *eax = 0; 6074 *ebx = 0; 6075 *ecx = 0; 6076 *edx = 0; 6077 } 6078 } 6079 6080 static void x86_cpu_get_cache_cpuid(uint32_t func, uint32_t index, 6081 uint32_t *eax, uint32_t *ebx, 6082 uint32_t *ecx, uint32_t *edx) 6083 { 6084 uint32_t level, unused; 6085 6086 /* Only return valid host leaves. */ 6087 switch (func) { 6088 case 2: 6089 case 4: 6090 host_cpuid(0, 0, &level, &unused, &unused, &unused); 6091 break; 6092 case 0x80000005: 6093 case 0x80000006: 6094 case 0x8000001d: 6095 host_cpuid(0x80000000, 0, &level, &unused, &unused, &unused); 6096 break; 6097 default: 6098 return; 6099 } 6100 6101 if (func > level) { 6102 *eax = 0; 6103 *ebx = 0; 6104 *ecx = 0; 6105 *edx = 0; 6106 } else { 6107 host_cpuid(func, index, eax, ebx, ecx, edx); 6108 } 6109 } 6110 6111 /* 6112 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 6113 */ 6114 void x86_cpu_apply_props(X86CPU *cpu, PropValue *props) 6115 { 6116 PropValue *pv; 6117 for (pv = props; pv->prop; pv++) { 6118 if (!pv->value) { 6119 continue; 6120 } 6121 object_property_parse(OBJECT(cpu), pv->prop, pv->value, 6122 &error_abort); 6123 } 6124 } 6125 6126 /* 6127 * Apply properties for the CPU model version specified in model. 6128 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 6129 */ 6130 6131 static void x86_cpu_apply_version_props(X86CPU *cpu, X86CPUModel *model) 6132 { 6133 const X86CPUVersionDefinition *vdef; 6134 X86CPUVersion version = x86_cpu_model_resolve_version(model); 6135 6136 if (version == CPU_VERSION_LEGACY) { 6137 return; 6138 } 6139 6140 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) { 6141 PropValue *p; 6142 6143 for (p = vdef->props; p && p->prop; p++) { 6144 object_property_parse(OBJECT(cpu), p->prop, p->value, 6145 &error_abort); 6146 } 6147 6148 if (vdef->version == version) { 6149 break; 6150 } 6151 } 6152 6153 /* 6154 * If we reached the end of the list, version number was invalid 6155 */ 6156 assert(vdef->version == version); 6157 } 6158 6159 static const CPUCaches *x86_cpu_get_versioned_cache_info(X86CPU *cpu, 6160 X86CPUModel *model) 6161 { 6162 const X86CPUVersionDefinition *vdef; 6163 X86CPUVersion version = x86_cpu_model_resolve_version(model); 6164 const CPUCaches *cache_info = model->cpudef->cache_info; 6165 6166 if (version == CPU_VERSION_LEGACY) { 6167 return cache_info; 6168 } 6169 6170 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) { 6171 if (vdef->cache_info) { 6172 cache_info = vdef->cache_info; 6173 } 6174 6175 if (vdef->version == version) { 6176 break; 6177 } 6178 } 6179 6180 assert(vdef->version == version); 6181 return cache_info; 6182 } 6183 6184 /* 6185 * Load data from X86CPUDefinition into a X86CPU object. 6186 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 6187 */ 6188 static void x86_cpu_load_model(X86CPU *cpu, X86CPUModel *model) 6189 { 6190 const X86CPUDefinition *def = model->cpudef; 6191 CPUX86State *env = &cpu->env; 6192 FeatureWord w; 6193 6194 /*NOTE: any property set by this function should be returned by 6195 * x86_cpu_static_props(), so static expansion of 6196 * query-cpu-model-expansion is always complete. 6197 */ 6198 6199 /* CPU models only set _minimum_ values for level/xlevel: */ 6200 object_property_set_uint(OBJECT(cpu), "min-level", def->level, 6201 &error_abort); 6202 object_property_set_uint(OBJECT(cpu), "min-xlevel", def->xlevel, 6203 &error_abort); 6204 6205 object_property_set_int(OBJECT(cpu), "family", def->family, &error_abort); 6206 object_property_set_int(OBJECT(cpu), "model", def->model, &error_abort); 6207 object_property_set_int(OBJECT(cpu), "stepping", def->stepping, 6208 &error_abort); 6209 object_property_set_str(OBJECT(cpu), "model-id", def->model_id, 6210 &error_abort); 6211 for (w = 0; w < FEATURE_WORDS; w++) { 6212 env->features[w] = def->features[w]; 6213 } 6214 6215 /* legacy-cache defaults to 'off' if CPU model provides cache info */ 6216 cpu->legacy_cache = !x86_cpu_get_versioned_cache_info(cpu, model); 6217 6218 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR; 6219 6220 /* sysenter isn't supported in compatibility mode on AMD, 6221 * syscall isn't supported in compatibility mode on Intel. 6222 * Normally we advertise the actual CPU vendor, but you can 6223 * override this using the 'vendor' property if you want to use 6224 * KVM's sysenter/syscall emulation in compatibility mode and 6225 * when doing cross vendor migration 6226 */ 6227 6228 /* 6229 * vendor property is set here but then overloaded with the 6230 * host cpu vendor for KVM and HVF. 6231 */ 6232 object_property_set_str(OBJECT(cpu), "vendor", def->vendor, &error_abort); 6233 6234 x86_cpu_apply_version_props(cpu, model); 6235 6236 /* 6237 * Properties in versioned CPU model are not user specified features. 6238 * We can simply clear env->user_features here since it will be filled later 6239 * in x86_cpu_expand_features() based on plus_features and minus_features. 6240 */ 6241 memset(&env->user_features, 0, sizeof(env->user_features)); 6242 } 6243 6244 static const gchar *x86_gdb_arch_name(CPUState *cs) 6245 { 6246 #ifdef TARGET_X86_64 6247 return "i386:x86-64"; 6248 #else 6249 return "i386"; 6250 #endif 6251 } 6252 6253 static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data) 6254 { 6255 X86CPUModel *model = data; 6256 X86CPUClass *xcc = X86_CPU_CLASS(oc); 6257 CPUClass *cc = CPU_CLASS(oc); 6258 6259 xcc->model = model; 6260 xcc->migration_safe = true; 6261 cc->deprecation_note = model->cpudef->deprecation_note; 6262 } 6263 6264 static void x86_register_cpu_model_type(const char *name, X86CPUModel *model) 6265 { 6266 g_autofree char *typename = x86_cpu_type_name(name); 6267 TypeInfo ti = { 6268 .name = typename, 6269 .parent = TYPE_X86_CPU, 6270 .class_init = x86_cpu_cpudef_class_init, 6271 .class_data = model, 6272 }; 6273 6274 type_register(&ti); 6275 } 6276 6277 6278 /* 6279 * register builtin_x86_defs; 6280 * "max", "base" and subclasses ("host") are not registered here. 6281 * See x86_cpu_register_types for all model registrations. 6282 */ 6283 static void x86_register_cpudef_types(const X86CPUDefinition *def) 6284 { 6285 X86CPUModel *m; 6286 const X86CPUVersionDefinition *vdef; 6287 6288 /* AMD aliases are handled at runtime based on CPUID vendor, so 6289 * they shouldn't be set on the CPU model table. 6290 */ 6291 assert(!(def->features[FEAT_8000_0001_EDX] & CPUID_EXT2_AMD_ALIASES)); 6292 /* catch mistakes instead of silently truncating model_id when too long */ 6293 assert(def->model_id && strlen(def->model_id) <= 48); 6294 6295 /* Unversioned model: */ 6296 m = g_new0(X86CPUModel, 1); 6297 m->cpudef = def; 6298 m->version = CPU_VERSION_AUTO; 6299 m->is_alias = true; 6300 x86_register_cpu_model_type(def->name, m); 6301 6302 /* Versioned models: */ 6303 6304 for (vdef = x86_cpu_def_get_versions(def); vdef->version; vdef++) { 6305 g_autofree char *name = 6306 x86_cpu_versioned_model_name(def, vdef->version); 6307 6308 m = g_new0(X86CPUModel, 1); 6309 m->cpudef = def; 6310 m->version = vdef->version; 6311 m->note = vdef->note; 6312 x86_register_cpu_model_type(name, m); 6313 6314 if (vdef->alias) { 6315 X86CPUModel *am = g_new0(X86CPUModel, 1); 6316 am->cpudef = def; 6317 am->version = vdef->version; 6318 am->is_alias = true; 6319 x86_register_cpu_model_type(vdef->alias, am); 6320 } 6321 } 6322 6323 } 6324 6325 uint32_t cpu_x86_virtual_addr_width(CPUX86State *env) 6326 { 6327 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57) { 6328 return 57; /* 57 bits virtual */ 6329 } else { 6330 return 48; /* 48 bits virtual */ 6331 } 6332 } 6333 6334 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, 6335 uint32_t *eax, uint32_t *ebx, 6336 uint32_t *ecx, uint32_t *edx) 6337 { 6338 X86CPU *cpu = env_archcpu(env); 6339 CPUState *cs = env_cpu(env); 6340 uint32_t limit; 6341 uint32_t signature[3]; 6342 X86CPUTopoInfo topo_info; 6343 uint32_t cores_per_pkg; 6344 uint32_t threads_per_pkg; 6345 6346 topo_info.dies_per_pkg = env->nr_dies; 6347 topo_info.modules_per_die = env->nr_modules; 6348 topo_info.cores_per_module = cs->nr_cores / env->nr_dies / env->nr_modules; 6349 topo_info.threads_per_core = cs->nr_threads; 6350 6351 cores_per_pkg = topo_info.cores_per_module * topo_info.modules_per_die * 6352 topo_info.dies_per_pkg; 6353 threads_per_pkg = cores_per_pkg * topo_info.threads_per_core; 6354 6355 /* Calculate & apply limits for different index ranges */ 6356 if (index >= 0xC0000000) { 6357 limit = env->cpuid_xlevel2; 6358 } else if (index >= 0x80000000) { 6359 limit = env->cpuid_xlevel; 6360 } else if (index >= 0x40000000) { 6361 limit = 0x40000001; 6362 } else { 6363 limit = env->cpuid_level; 6364 } 6365 6366 if (index > limit) { 6367 /* Intel documentation states that invalid EAX input will 6368 * return the same information as EAX=cpuid_level 6369 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID) 6370 */ 6371 index = env->cpuid_level; 6372 } 6373 6374 switch(index) { 6375 case 0: 6376 *eax = env->cpuid_level; 6377 *ebx = env->cpuid_vendor1; 6378 *edx = env->cpuid_vendor2; 6379 *ecx = env->cpuid_vendor3; 6380 break; 6381 case 1: 6382 *eax = env->cpuid_version; 6383 *ebx = (cpu->apic_id << 24) | 6384 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */ 6385 *ecx = env->features[FEAT_1_ECX]; 6386 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) { 6387 *ecx |= CPUID_EXT_OSXSAVE; 6388 } 6389 *edx = env->features[FEAT_1_EDX]; 6390 if (threads_per_pkg > 1) { 6391 *ebx |= threads_per_pkg << 16; 6392 *edx |= CPUID_HT; 6393 } 6394 if (!cpu->enable_pmu) { 6395 *ecx &= ~CPUID_EXT_PDCM; 6396 } 6397 break; 6398 case 2: 6399 /* cache info: needed for Pentium Pro compatibility */ 6400 if (cpu->cache_info_passthrough) { 6401 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 6402 break; 6403 } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { 6404 *eax = *ebx = *ecx = *edx = 0; 6405 break; 6406 } 6407 *eax = 1; /* Number of CPUID[EAX=2] calls required */ 6408 *ebx = 0; 6409 if (!cpu->enable_l3_cache) { 6410 *ecx = 0; 6411 } else { 6412 *ecx = cpuid2_cache_descriptor(env->cache_info_cpuid2.l3_cache); 6413 } 6414 *edx = (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1d_cache) << 16) | 6415 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1i_cache) << 8) | 6416 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l2_cache)); 6417 break; 6418 case 4: 6419 /* cache info: needed for Core compatibility */ 6420 if (cpu->cache_info_passthrough) { 6421 x86_cpu_get_cache_cpuid(index, count, eax, ebx, ecx, edx); 6422 /* 6423 * QEMU has its own number of cores/logical cpus, 6424 * set 24..14, 31..26 bit to configured values 6425 */ 6426 if (*eax & 31) { 6427 int host_vcpus_per_cache = 1 + ((*eax & 0x3FFC000) >> 14); 6428 6429 if (cores_per_pkg > 1) { 6430 *eax &= ~0xFC000000; 6431 *eax |= max_core_ids_in_package(&topo_info) << 26; 6432 } 6433 if (host_vcpus_per_cache > threads_per_pkg) { 6434 *eax &= ~0x3FFC000; 6435 6436 /* Share the cache at package level. */ 6437 *eax |= max_thread_ids_for_cache(&topo_info, 6438 CPU_TOPO_LEVEL_PACKAGE) << 14; 6439 } 6440 } 6441 } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { 6442 *eax = *ebx = *ecx = *edx = 0; 6443 } else { 6444 *eax = 0; 6445 6446 switch (count) { 6447 case 0: /* L1 dcache info */ 6448 encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache, 6449 &topo_info, 6450 eax, ebx, ecx, edx); 6451 if (!cpu->l1_cache_per_core) { 6452 *eax &= ~MAKE_64BIT_MASK(14, 12); 6453 } 6454 break; 6455 case 1: /* L1 icache info */ 6456 encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache, 6457 &topo_info, 6458 eax, ebx, ecx, edx); 6459 if (!cpu->l1_cache_per_core) { 6460 *eax &= ~MAKE_64BIT_MASK(14, 12); 6461 } 6462 break; 6463 case 2: /* L2 cache info */ 6464 encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache, 6465 &topo_info, 6466 eax, ebx, ecx, edx); 6467 break; 6468 case 3: /* L3 cache info */ 6469 if (cpu->enable_l3_cache) { 6470 encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache, 6471 &topo_info, 6472 eax, ebx, ecx, edx); 6473 break; 6474 } 6475 /* fall through */ 6476 default: /* end of info */ 6477 *eax = *ebx = *ecx = *edx = 0; 6478 break; 6479 } 6480 } 6481 break; 6482 case 5: 6483 /* MONITOR/MWAIT Leaf */ 6484 *eax = cpu->mwait.eax; /* Smallest monitor-line size in bytes */ 6485 *ebx = cpu->mwait.ebx; /* Largest monitor-line size in bytes */ 6486 *ecx = cpu->mwait.ecx; /* flags */ 6487 *edx = cpu->mwait.edx; /* mwait substates */ 6488 break; 6489 case 6: 6490 /* Thermal and Power Leaf */ 6491 *eax = env->features[FEAT_6_EAX]; 6492 *ebx = 0; 6493 *ecx = 0; 6494 *edx = 0; 6495 break; 6496 case 7: 6497 /* Structured Extended Feature Flags Enumeration Leaf */ 6498 if (count == 0) { 6499 uint32_t eax_0_unused, ebx_0, ecx_0, edx_0_unused; 6500 6501 /* Maximum ECX value for sub-leaves */ 6502 *eax = env->cpuid_level_func7; 6503 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */ 6504 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */ 6505 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) { 6506 *ecx |= CPUID_7_0_ECX_OSPKE; 6507 } 6508 *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */ 6509 6510 /* 6511 * SGX cannot be emulated in software. If hardware does not 6512 * support enabling SGX and/or SGX flexible launch control, 6513 * then we need to update the VM's CPUID values accordingly. 6514 */ 6515 x86_cpu_get_supported_cpuid(0x7, 0, 6516 &eax_0_unused, &ebx_0, 6517 &ecx_0, &edx_0_unused); 6518 if ((*ebx & CPUID_7_0_EBX_SGX) && !(ebx_0 & CPUID_7_0_EBX_SGX)) { 6519 *ebx &= ~CPUID_7_0_EBX_SGX; 6520 } 6521 6522 if ((*ecx & CPUID_7_0_ECX_SGX_LC) 6523 && (!(*ebx & CPUID_7_0_EBX_SGX) || !(ecx_0 & CPUID_7_0_ECX_SGX_LC))) { 6524 *ecx &= ~CPUID_7_0_ECX_SGX_LC; 6525 } 6526 } else if (count == 1) { 6527 *eax = env->features[FEAT_7_1_EAX]; 6528 *edx = env->features[FEAT_7_1_EDX]; 6529 *ebx = 0; 6530 *ecx = 0; 6531 } else if (count == 2) { 6532 *edx = env->features[FEAT_7_2_EDX]; 6533 *eax = 0; 6534 *ebx = 0; 6535 *ecx = 0; 6536 } else { 6537 *eax = 0; 6538 *ebx = 0; 6539 *ecx = 0; 6540 *edx = 0; 6541 } 6542 break; 6543 case 9: 6544 /* Direct Cache Access Information Leaf */ 6545 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */ 6546 *ebx = 0; 6547 *ecx = 0; 6548 *edx = 0; 6549 break; 6550 case 0xA: 6551 /* Architectural Performance Monitoring Leaf */ 6552 if (cpu->enable_pmu) { 6553 x86_cpu_get_supported_cpuid(0xA, count, eax, ebx, ecx, edx); 6554 } else { 6555 *eax = 0; 6556 *ebx = 0; 6557 *ecx = 0; 6558 *edx = 0; 6559 } 6560 break; 6561 case 0xB: 6562 /* Extended Topology Enumeration Leaf */ 6563 if (!cpu->enable_cpuid_0xb) { 6564 *eax = *ebx = *ecx = *edx = 0; 6565 break; 6566 } 6567 6568 *ecx = count & 0xff; 6569 *edx = cpu->apic_id; 6570 6571 switch (count) { 6572 case 0: 6573 *eax = apicid_core_offset(&topo_info); 6574 *ebx = topo_info.threads_per_core; 6575 *ecx |= CPUID_B_ECX_TOPO_LEVEL_SMT << 8; 6576 break; 6577 case 1: 6578 *eax = apicid_pkg_offset(&topo_info); 6579 *ebx = threads_per_pkg; 6580 *ecx |= CPUID_B_ECX_TOPO_LEVEL_CORE << 8; 6581 break; 6582 default: 6583 *eax = 0; 6584 *ebx = 0; 6585 *ecx |= CPUID_B_ECX_TOPO_LEVEL_INVALID << 8; 6586 } 6587 6588 assert(!(*eax & ~0x1f)); 6589 *ebx &= 0xffff; /* The count doesn't need to be reliable. */ 6590 break; 6591 case 0x1C: 6592 if (cpu->enable_pmu && (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) { 6593 x86_cpu_get_supported_cpuid(0x1C, 0, eax, ebx, ecx, edx); 6594 *edx = 0; 6595 } 6596 break; 6597 case 0x1F: 6598 /* V2 Extended Topology Enumeration Leaf */ 6599 if (!x86_has_extended_topo(env->avail_cpu_topo)) { 6600 *eax = *ebx = *ecx = *edx = 0; 6601 break; 6602 } 6603 6604 encode_topo_cpuid1f(env, count, &topo_info, eax, ebx, ecx, edx); 6605 break; 6606 case 0xD: { 6607 /* Processor Extended State */ 6608 *eax = 0; 6609 *ebx = 0; 6610 *ecx = 0; 6611 *edx = 0; 6612 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { 6613 break; 6614 } 6615 6616 if (count == 0) { 6617 *ecx = xsave_area_size(x86_cpu_xsave_xcr0_components(cpu), false); 6618 *eax = env->features[FEAT_XSAVE_XCR0_LO]; 6619 *edx = env->features[FEAT_XSAVE_XCR0_HI]; 6620 /* 6621 * The initial value of xcr0 and ebx == 0, On host without kvm 6622 * commit 412a3c41(e.g., CentOS 6), the ebx's value always == 0 6623 * even through guest update xcr0, this will crash some legacy guest 6624 * (e.g., CentOS 6), So set ebx == ecx to workaround it. 6625 */ 6626 *ebx = kvm_enabled() ? *ecx : xsave_area_size(env->xcr0, false); 6627 } else if (count == 1) { 6628 uint64_t xstate = x86_cpu_xsave_xcr0_components(cpu) | 6629 x86_cpu_xsave_xss_components(cpu); 6630 6631 *eax = env->features[FEAT_XSAVE]; 6632 *ebx = xsave_area_size(xstate, true); 6633 *ecx = env->features[FEAT_XSAVE_XSS_LO]; 6634 *edx = env->features[FEAT_XSAVE_XSS_HI]; 6635 if (kvm_enabled() && cpu->enable_pmu && 6636 (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR) && 6637 (*eax & CPUID_XSAVE_XSAVES)) { 6638 *ecx |= XSTATE_ARCH_LBR_MASK; 6639 } else { 6640 *ecx &= ~XSTATE_ARCH_LBR_MASK; 6641 } 6642 } else if (count == 0xf && cpu->enable_pmu 6643 && (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) { 6644 x86_cpu_get_supported_cpuid(0xD, count, eax, ebx, ecx, edx); 6645 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) { 6646 const ExtSaveArea *esa = &x86_ext_save_areas[count]; 6647 6648 if (x86_cpu_xsave_xcr0_components(cpu) & (1ULL << count)) { 6649 *eax = esa->size; 6650 *ebx = esa->offset; 6651 *ecx = esa->ecx & 6652 (ESA_FEATURE_ALIGN64_MASK | ESA_FEATURE_XFD_MASK); 6653 } else if (x86_cpu_xsave_xss_components(cpu) & (1ULL << count)) { 6654 *eax = esa->size; 6655 *ebx = 0; 6656 *ecx = 1; 6657 } 6658 } 6659 break; 6660 } 6661 case 0x12: 6662 #ifndef CONFIG_USER_ONLY 6663 if (!kvm_enabled() || 6664 !(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX)) { 6665 *eax = *ebx = *ecx = *edx = 0; 6666 break; 6667 } 6668 6669 /* 6670 * SGX sub-leafs CPUID.0x12.{0x2..N} enumerate EPC sections. Retrieve 6671 * the EPC properties, e.g. confidentiality and integrity, from the 6672 * host's first EPC section, i.e. assume there is one EPC section or 6673 * that all EPC sections have the same security properties. 6674 */ 6675 if (count > 1) { 6676 uint64_t epc_addr, epc_size; 6677 6678 if (sgx_epc_get_section(count - 2, &epc_addr, &epc_size)) { 6679 *eax = *ebx = *ecx = *edx = 0; 6680 break; 6681 } 6682 host_cpuid(index, 2, eax, ebx, ecx, edx); 6683 *eax = (uint32_t)(epc_addr & 0xfffff000) | 0x1; 6684 *ebx = (uint32_t)(epc_addr >> 32); 6685 *ecx = (uint32_t)(epc_size & 0xfffff000) | (*ecx & 0xf); 6686 *edx = (uint32_t)(epc_size >> 32); 6687 break; 6688 } 6689 6690 /* 6691 * SGX sub-leafs CPUID.0x12.{0x0,0x1} are heavily dependent on hardware 6692 * and KVM, i.e. QEMU cannot emulate features to override what KVM 6693 * supports. Features can be further restricted by userspace, but not 6694 * made more permissive. 6695 */ 6696 x86_cpu_get_supported_cpuid(0x12, count, eax, ebx, ecx, edx); 6697 6698 if (count == 0) { 6699 *eax &= env->features[FEAT_SGX_12_0_EAX]; 6700 *ebx &= env->features[FEAT_SGX_12_0_EBX]; 6701 } else { 6702 *eax &= env->features[FEAT_SGX_12_1_EAX]; 6703 *ebx &= 0; /* ebx reserve */ 6704 *ecx &= env->features[FEAT_XSAVE_XCR0_LO]; 6705 *edx &= env->features[FEAT_XSAVE_XCR0_HI]; 6706 6707 /* FP and SSE are always allowed regardless of XSAVE/XCR0. */ 6708 *ecx |= XSTATE_FP_MASK | XSTATE_SSE_MASK; 6709 6710 /* Access to PROVISIONKEY requires additional credentials. */ 6711 if ((*eax & (1U << 4)) && 6712 !kvm_enable_sgx_provisioning(cs->kvm_state)) { 6713 *eax &= ~(1U << 4); 6714 } 6715 } 6716 #endif 6717 break; 6718 case 0x14: { 6719 /* Intel Processor Trace Enumeration */ 6720 *eax = 0; 6721 *ebx = 0; 6722 *ecx = 0; 6723 *edx = 0; 6724 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) || 6725 !kvm_enabled()) { 6726 break; 6727 } 6728 6729 /* 6730 * If these are changed, they should stay in sync with 6731 * x86_cpu_filter_features(). 6732 */ 6733 if (count == 0) { 6734 *eax = INTEL_PT_MAX_SUBLEAF; 6735 *ebx = INTEL_PT_MINIMAL_EBX; 6736 *ecx = INTEL_PT_MINIMAL_ECX; 6737 if (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP) { 6738 *ecx |= CPUID_14_0_ECX_LIP; 6739 } 6740 } else if (count == 1) { 6741 *eax = INTEL_PT_MTC_BITMAP | INTEL_PT_ADDR_RANGES_NUM; 6742 *ebx = INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP; 6743 } 6744 break; 6745 } 6746 case 0x1D: { 6747 /* AMX TILE, for now hardcoded for Sapphire Rapids*/ 6748 *eax = 0; 6749 *ebx = 0; 6750 *ecx = 0; 6751 *edx = 0; 6752 if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) { 6753 break; 6754 } 6755 6756 if (count == 0) { 6757 /* Highest numbered palette subleaf */ 6758 *eax = INTEL_AMX_TILE_MAX_SUBLEAF; 6759 } else if (count == 1) { 6760 *eax = INTEL_AMX_TOTAL_TILE_BYTES | 6761 (INTEL_AMX_BYTES_PER_TILE << 16); 6762 *ebx = INTEL_AMX_BYTES_PER_ROW | (INTEL_AMX_TILE_MAX_NAMES << 16); 6763 *ecx = INTEL_AMX_TILE_MAX_ROWS; 6764 } 6765 break; 6766 } 6767 case 0x1E: { 6768 /* AMX TMUL, for now hardcoded for Sapphire Rapids */ 6769 *eax = 0; 6770 *ebx = 0; 6771 *ecx = 0; 6772 *edx = 0; 6773 if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) { 6774 break; 6775 } 6776 6777 if (count == 0) { 6778 /* Highest numbered palette subleaf */ 6779 *ebx = INTEL_AMX_TMUL_MAX_K | (INTEL_AMX_TMUL_MAX_N << 8); 6780 } 6781 break; 6782 } 6783 case 0x40000000: 6784 /* 6785 * CPUID code in kvm_arch_init_vcpu() ignores stuff 6786 * set here, but we restrict to TCG none the less. 6787 */ 6788 if (tcg_enabled() && cpu->expose_tcg) { 6789 memcpy(signature, "TCGTCGTCGTCG", 12); 6790 *eax = 0x40000001; 6791 *ebx = signature[0]; 6792 *ecx = signature[1]; 6793 *edx = signature[2]; 6794 } else { 6795 *eax = 0; 6796 *ebx = 0; 6797 *ecx = 0; 6798 *edx = 0; 6799 } 6800 break; 6801 case 0x40000001: 6802 *eax = 0; 6803 *ebx = 0; 6804 *ecx = 0; 6805 *edx = 0; 6806 break; 6807 case 0x80000000: 6808 *eax = env->cpuid_xlevel; 6809 *ebx = env->cpuid_vendor1; 6810 *edx = env->cpuid_vendor2; 6811 *ecx = env->cpuid_vendor3; 6812 break; 6813 case 0x80000001: 6814 *eax = env->cpuid_version; 6815 *ebx = 0; 6816 *ecx = env->features[FEAT_8000_0001_ECX]; 6817 *edx = env->features[FEAT_8000_0001_EDX]; 6818 6819 /* The Linux kernel checks for the CMPLegacy bit and 6820 * discards multiple thread information if it is set. 6821 * So don't set it here for Intel to make Linux guests happy. 6822 */ 6823 if (threads_per_pkg > 1) { 6824 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 || 6825 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 || 6826 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) { 6827 *ecx |= 1 << 1; /* CmpLegacy bit */ 6828 } 6829 } 6830 if (tcg_enabled() && env->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && 6831 !(env->hflags & HF_LMA_MASK)) { 6832 *edx &= ~CPUID_EXT2_SYSCALL; 6833 } 6834 break; 6835 case 0x80000002: 6836 case 0x80000003: 6837 case 0x80000004: 6838 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0]; 6839 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1]; 6840 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2]; 6841 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3]; 6842 break; 6843 case 0x80000005: 6844 /* cache info (L1 cache) */ 6845 if (cpu->cache_info_passthrough) { 6846 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 6847 break; 6848 } 6849 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | 6850 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES); 6851 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | 6852 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES); 6853 *ecx = encode_cache_cpuid80000005(env->cache_info_amd.l1d_cache); 6854 *edx = encode_cache_cpuid80000005(env->cache_info_amd.l1i_cache); 6855 break; 6856 case 0x80000006: 6857 /* cache info (L2 cache) */ 6858 if (cpu->cache_info_passthrough) { 6859 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 6860 break; 6861 } 6862 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | 6863 (L2_DTLB_2M_ENTRIES << 16) | 6864 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | 6865 (L2_ITLB_2M_ENTRIES); 6866 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | 6867 (L2_DTLB_4K_ENTRIES << 16) | 6868 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | 6869 (L2_ITLB_4K_ENTRIES); 6870 encode_cache_cpuid80000006(env->cache_info_amd.l2_cache, 6871 cpu->enable_l3_cache ? 6872 env->cache_info_amd.l3_cache : NULL, 6873 ecx, edx); 6874 break; 6875 case 0x80000007: 6876 *eax = 0; 6877 *ebx = 0; 6878 *ecx = 0; 6879 *edx = env->features[FEAT_8000_0007_EDX]; 6880 break; 6881 case 0x80000008: 6882 /* virtual & phys address size in low 2 bytes. */ 6883 *eax = cpu->phys_bits; 6884 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 6885 /* 64 bit processor */ 6886 *eax |= (cpu_x86_virtual_addr_width(env) << 8); 6887 *eax |= (cpu->guest_phys_bits << 16); 6888 } 6889 *ebx = env->features[FEAT_8000_0008_EBX]; 6890 if (threads_per_pkg > 1) { 6891 /* 6892 * Bits 15:12 is "The number of bits in the initial 6893 * Core::X86::Apic::ApicId[ApicId] value that indicate 6894 * thread ID within a package". 6895 * Bits 7:0 is "The number of threads in the package is NC+1" 6896 */ 6897 *ecx = (apicid_pkg_offset(&topo_info) << 12) | 6898 (threads_per_pkg - 1); 6899 } else { 6900 *ecx = 0; 6901 } 6902 *edx = 0; 6903 break; 6904 case 0x8000000A: 6905 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { 6906 *eax = 0x00000001; /* SVM Revision */ 6907 *ebx = 0x00000010; /* nr of ASIDs */ 6908 *ecx = 0; 6909 *edx = env->features[FEAT_SVM]; /* optional features */ 6910 } else { 6911 *eax = 0; 6912 *ebx = 0; 6913 *ecx = 0; 6914 *edx = 0; 6915 } 6916 break; 6917 case 0x8000001D: 6918 *eax = 0; 6919 if (cpu->cache_info_passthrough) { 6920 x86_cpu_get_cache_cpuid(index, count, eax, ebx, ecx, edx); 6921 break; 6922 } 6923 switch (count) { 6924 case 0: /* L1 dcache info */ 6925 encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache, 6926 &topo_info, eax, ebx, ecx, edx); 6927 break; 6928 case 1: /* L1 icache info */ 6929 encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache, 6930 &topo_info, eax, ebx, ecx, edx); 6931 break; 6932 case 2: /* L2 cache info */ 6933 encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache, 6934 &topo_info, eax, ebx, ecx, edx); 6935 break; 6936 case 3: /* L3 cache info */ 6937 encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache, 6938 &topo_info, eax, ebx, ecx, edx); 6939 break; 6940 default: /* end of info */ 6941 *eax = *ebx = *ecx = *edx = 0; 6942 break; 6943 } 6944 break; 6945 case 0x8000001E: 6946 if (cpu->core_id <= 255) { 6947 encode_topo_cpuid8000001e(cpu, &topo_info, eax, ebx, ecx, edx); 6948 } else { 6949 *eax = 0; 6950 *ebx = 0; 6951 *ecx = 0; 6952 *edx = 0; 6953 } 6954 break; 6955 case 0xC0000000: 6956 *eax = env->cpuid_xlevel2; 6957 *ebx = 0; 6958 *ecx = 0; 6959 *edx = 0; 6960 break; 6961 case 0xC0000001: 6962 /* Support for VIA CPU's CPUID instruction */ 6963 *eax = env->cpuid_version; 6964 *ebx = 0; 6965 *ecx = 0; 6966 *edx = env->features[FEAT_C000_0001_EDX]; 6967 break; 6968 case 0xC0000002: 6969 case 0xC0000003: 6970 case 0xC0000004: 6971 /* Reserved for the future, and now filled with zero */ 6972 *eax = 0; 6973 *ebx = 0; 6974 *ecx = 0; 6975 *edx = 0; 6976 break; 6977 case 0x8000001F: 6978 *eax = *ebx = *ecx = *edx = 0; 6979 if (sev_enabled()) { 6980 *eax = 0x2; 6981 *eax |= sev_es_enabled() ? 0x8 : 0; 6982 *eax |= sev_snp_enabled() ? 0x10 : 0; 6983 *ebx = sev_get_cbit_position() & 0x3f; /* EBX[5:0] */ 6984 *ebx |= (sev_get_reduced_phys_bits() & 0x3f) << 6; /* EBX[11:6] */ 6985 } 6986 break; 6987 case 0x80000021: 6988 *eax = env->features[FEAT_8000_0021_EAX]; 6989 *ebx = *ecx = *edx = 0; 6990 break; 6991 default: 6992 /* reserved values: zero */ 6993 *eax = 0; 6994 *ebx = 0; 6995 *ecx = 0; 6996 *edx = 0; 6997 break; 6998 } 6999 } 7000 7001 static void x86_cpu_set_sgxlepubkeyhash(CPUX86State *env) 7002 { 7003 #ifndef CONFIG_USER_ONLY 7004 /* Those default values are defined in Skylake HW */ 7005 env->msr_ia32_sgxlepubkeyhash[0] = 0xa6053e051270b7acULL; 7006 env->msr_ia32_sgxlepubkeyhash[1] = 0x6cfbe8ba8b3b413dULL; 7007 env->msr_ia32_sgxlepubkeyhash[2] = 0xc4916d99f2b3735dULL; 7008 env->msr_ia32_sgxlepubkeyhash[3] = 0xd4f8c05909f9bb3bULL; 7009 #endif 7010 } 7011 7012 static void x86_cpu_reset_hold(Object *obj, ResetType type) 7013 { 7014 CPUState *cs = CPU(obj); 7015 X86CPU *cpu = X86_CPU(cs); 7016 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj); 7017 CPUX86State *env = &cpu->env; 7018 target_ulong cr4; 7019 uint64_t xcr0; 7020 int i; 7021 7022 if (xcc->parent_phases.hold) { 7023 xcc->parent_phases.hold(obj, type); 7024 } 7025 7026 memset(env, 0, offsetof(CPUX86State, end_reset_fields)); 7027 7028 env->old_exception = -1; 7029 7030 /* init to reset state */ 7031 env->int_ctl = 0; 7032 env->hflags2 |= HF2_GIF_MASK; 7033 env->hflags2 |= HF2_VGIF_MASK; 7034 env->hflags &= ~HF_GUEST_MASK; 7035 7036 cpu_x86_update_cr0(env, 0x60000010); 7037 env->a20_mask = ~0x0; 7038 env->smbase = 0x30000; 7039 env->msr_smi_count = 0; 7040 7041 env->idt.limit = 0xffff; 7042 env->gdt.limit = 0xffff; 7043 env->ldt.limit = 0xffff; 7044 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT); 7045 env->tr.limit = 0xffff; 7046 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT); 7047 7048 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff, 7049 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK | 7050 DESC_R_MASK | DESC_A_MASK); 7051 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff, 7052 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7053 DESC_A_MASK); 7054 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff, 7055 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7056 DESC_A_MASK); 7057 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff, 7058 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7059 DESC_A_MASK); 7060 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff, 7061 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7062 DESC_A_MASK); 7063 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff, 7064 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7065 DESC_A_MASK); 7066 7067 env->eip = 0xfff0; 7068 env->regs[R_EDX] = env->cpuid_version; 7069 7070 env->eflags = 0x2; 7071 7072 /* FPU init */ 7073 for (i = 0; i < 8; i++) { 7074 env->fptags[i] = 1; 7075 } 7076 cpu_set_fpuc(env, 0x37f); 7077 7078 env->mxcsr = 0x1f80; 7079 /* All units are in INIT state. */ 7080 env->xstate_bv = 0; 7081 7082 env->pat = 0x0007040600070406ULL; 7083 7084 if (kvm_enabled()) { 7085 /* 7086 * KVM handles TSC = 0 specially and thinks we are hot-plugging 7087 * a new CPU, use 1 instead to force a reset. 7088 */ 7089 if (env->tsc != 0) { 7090 env->tsc = 1; 7091 } 7092 } else { 7093 env->tsc = 0; 7094 } 7095 7096 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT; 7097 if (env->features[FEAT_1_ECX] & CPUID_EXT_MONITOR) { 7098 env->msr_ia32_misc_enable |= MSR_IA32_MISC_ENABLE_MWAIT; 7099 } 7100 7101 memset(env->dr, 0, sizeof(env->dr)); 7102 env->dr[6] = DR6_FIXED_1; 7103 env->dr[7] = DR7_FIXED_1; 7104 cpu_breakpoint_remove_all(cs, BP_CPU); 7105 cpu_watchpoint_remove_all(cs, BP_CPU); 7106 7107 cr4 = 0; 7108 xcr0 = XSTATE_FP_MASK; 7109 7110 #ifdef CONFIG_USER_ONLY 7111 /* Enable all the features for user-mode. */ 7112 if (env->features[FEAT_1_EDX] & CPUID_SSE) { 7113 xcr0 |= XSTATE_SSE_MASK; 7114 } 7115 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 7116 const ExtSaveArea *esa = &x86_ext_save_areas[i]; 7117 if (!((1 << i) & CPUID_XSTATE_XCR0_MASK)) { 7118 continue; 7119 } 7120 if (env->features[esa->feature] & esa->bits) { 7121 xcr0 |= 1ull << i; 7122 } 7123 } 7124 7125 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) { 7126 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK; 7127 } 7128 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) { 7129 cr4 |= CR4_FSGSBASE_MASK; 7130 } 7131 #endif 7132 7133 env->xcr0 = xcr0; 7134 cpu_x86_update_cr4(env, cr4); 7135 7136 /* 7137 * SDM 11.11.5 requires: 7138 * - IA32_MTRR_DEF_TYPE MSR.E = 0 7139 * - IA32_MTRR_PHYSMASKn.V = 0 7140 * All other bits are undefined. For simplification, zero it all. 7141 */ 7142 env->mtrr_deftype = 0; 7143 memset(env->mtrr_var, 0, sizeof(env->mtrr_var)); 7144 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed)); 7145 7146 env->interrupt_injected = -1; 7147 env->exception_nr = -1; 7148 env->exception_pending = 0; 7149 env->exception_injected = 0; 7150 env->exception_has_payload = false; 7151 env->exception_payload = 0; 7152 env->nmi_injected = false; 7153 env->triple_fault_pending = false; 7154 #if !defined(CONFIG_USER_ONLY) 7155 /* We hard-wire the BSP to the first CPU. */ 7156 apic_designate_bsp(cpu->apic_state, cs->cpu_index == 0); 7157 7158 cs->halted = !cpu_is_bsp(cpu); 7159 7160 if (kvm_enabled()) { 7161 kvm_arch_reset_vcpu(cpu); 7162 } 7163 7164 x86_cpu_set_sgxlepubkeyhash(env); 7165 7166 env->amd_tsc_scale_msr = MSR_AMD64_TSC_RATIO_DEFAULT; 7167 7168 #endif 7169 } 7170 7171 void x86_cpu_after_reset(X86CPU *cpu) 7172 { 7173 #ifndef CONFIG_USER_ONLY 7174 if (kvm_enabled()) { 7175 kvm_arch_after_reset_vcpu(cpu); 7176 } 7177 7178 if (cpu->apic_state) { 7179 device_cold_reset(cpu->apic_state); 7180 } 7181 #endif 7182 } 7183 7184 static void mce_init(X86CPU *cpu) 7185 { 7186 CPUX86State *cenv = &cpu->env; 7187 unsigned int bank; 7188 7189 if (((cenv->cpuid_version >> 8) & 0xf) >= 6 7190 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) == 7191 (CPUID_MCE | CPUID_MCA)) { 7192 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF | 7193 (cpu->enable_lmce ? MCG_LMCE_P : 0); 7194 cenv->mcg_ctl = ~(uint64_t)0; 7195 for (bank = 0; bank < MCE_BANKS_DEF; bank++) { 7196 cenv->mce_banks[bank * 4] = ~(uint64_t)0; 7197 } 7198 } 7199 } 7200 7201 static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value) 7202 { 7203 if (*min < value) { 7204 *min = value; 7205 } 7206 } 7207 7208 /* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */ 7209 static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w) 7210 { 7211 CPUX86State *env = &cpu->env; 7212 FeatureWordInfo *fi = &feature_word_info[w]; 7213 uint32_t eax = fi->cpuid.eax; 7214 uint32_t region = eax & 0xF0000000; 7215 7216 assert(feature_word_info[w].type == CPUID_FEATURE_WORD); 7217 if (!env->features[w]) { 7218 return; 7219 } 7220 7221 switch (region) { 7222 case 0x00000000: 7223 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax); 7224 break; 7225 case 0x80000000: 7226 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax); 7227 break; 7228 case 0xC0000000: 7229 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax); 7230 break; 7231 } 7232 7233 if (eax == 7) { 7234 x86_cpu_adjust_level(cpu, &env->cpuid_min_level_func7, 7235 fi->cpuid.ecx); 7236 } 7237 } 7238 7239 /* Calculate XSAVE components based on the configured CPU feature flags */ 7240 static void x86_cpu_enable_xsave_components(X86CPU *cpu) 7241 { 7242 CPUX86State *env = &cpu->env; 7243 int i; 7244 uint64_t mask; 7245 static bool request_perm; 7246 7247 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { 7248 env->features[FEAT_XSAVE_XCR0_LO] = 0; 7249 env->features[FEAT_XSAVE_XCR0_HI] = 0; 7250 env->features[FEAT_XSAVE_XSS_LO] = 0; 7251 env->features[FEAT_XSAVE_XSS_HI] = 0; 7252 return; 7253 } 7254 7255 mask = 0; 7256 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 7257 const ExtSaveArea *esa = &x86_ext_save_areas[i]; 7258 if (env->features[esa->feature] & esa->bits) { 7259 mask |= (1ULL << i); 7260 } 7261 } 7262 7263 /* Only request permission for first vcpu */ 7264 if (kvm_enabled() && !request_perm) { 7265 kvm_request_xsave_components(cpu, mask); 7266 request_perm = true; 7267 } 7268 7269 env->features[FEAT_XSAVE_XCR0_LO] = mask & CPUID_XSTATE_XCR0_MASK; 7270 env->features[FEAT_XSAVE_XCR0_HI] = (mask & CPUID_XSTATE_XCR0_MASK) >> 32; 7271 env->features[FEAT_XSAVE_XSS_LO] = mask & CPUID_XSTATE_XSS_MASK; 7272 env->features[FEAT_XSAVE_XSS_HI] = (mask & CPUID_XSTATE_XSS_MASK) >> 32; 7273 } 7274 7275 /***** Steps involved on loading and filtering CPUID data 7276 * 7277 * When initializing and realizing a CPU object, the steps 7278 * involved in setting up CPUID data are: 7279 * 7280 * 1) Loading CPU model definition (X86CPUDefinition). This is 7281 * implemented by x86_cpu_load_model() and should be completely 7282 * transparent, as it is done automatically by instance_init. 7283 * No code should need to look at X86CPUDefinition structs 7284 * outside instance_init. 7285 * 7286 * 2) CPU expansion. This is done by realize before CPUID 7287 * filtering, and will make sure host/accelerator data is 7288 * loaded for CPU models that depend on host capabilities 7289 * (e.g. "host"). Done by x86_cpu_expand_features(). 7290 * 7291 * 3) CPUID filtering. This initializes extra data related to 7292 * CPUID, and checks if the host supports all capabilities 7293 * required by the CPU. Runnability of a CPU model is 7294 * determined at this step. Done by x86_cpu_filter_features(). 7295 * 7296 * Some operations don't require all steps to be performed. 7297 * More precisely: 7298 * 7299 * - CPU instance creation (instance_init) will run only CPU 7300 * model loading. CPU expansion can't run at instance_init-time 7301 * because host/accelerator data may be not available yet. 7302 * - CPU realization will perform both CPU model expansion and CPUID 7303 * filtering, and return an error in case one of them fails. 7304 * - query-cpu-definitions needs to run all 3 steps. It needs 7305 * to run CPUID filtering, as the 'unavailable-features' 7306 * field is set based on the filtering results. 7307 * - The query-cpu-model-expansion QMP command only needs to run 7308 * CPU model loading and CPU expansion. It should not filter 7309 * any CPUID data based on host capabilities. 7310 */ 7311 7312 /* Expand CPU configuration data, based on configured features 7313 * and host/accelerator capabilities when appropriate. 7314 */ 7315 void x86_cpu_expand_features(X86CPU *cpu, Error **errp) 7316 { 7317 CPUX86State *env = &cpu->env; 7318 FeatureWord w; 7319 int i; 7320 GList *l; 7321 7322 for (l = plus_features; l; l = l->next) { 7323 const char *prop = l->data; 7324 if (!object_property_set_bool(OBJECT(cpu), prop, true, errp)) { 7325 return; 7326 } 7327 } 7328 7329 for (l = minus_features; l; l = l->next) { 7330 const char *prop = l->data; 7331 if (!object_property_set_bool(OBJECT(cpu), prop, false, errp)) { 7332 return; 7333 } 7334 } 7335 7336 /*TODO: Now cpu->max_features doesn't overwrite features 7337 * set using QOM properties, and we can convert 7338 * plus_features & minus_features to global properties 7339 * inside x86_cpu_parse_featurestr() too. 7340 */ 7341 if (cpu->max_features) { 7342 for (w = 0; w < FEATURE_WORDS; w++) { 7343 /* Override only features that weren't set explicitly 7344 * by the user. 7345 */ 7346 env->features[w] |= 7347 x86_cpu_get_supported_feature_word(w, cpu->migratable) & 7348 ~env->user_features[w] & 7349 ~feature_word_info[w].no_autoenable_flags; 7350 } 7351 } 7352 7353 for (i = 0; i < ARRAY_SIZE(feature_dependencies); i++) { 7354 FeatureDep *d = &feature_dependencies[i]; 7355 if (!(env->features[d->from.index] & d->from.mask)) { 7356 uint64_t unavailable_features = env->features[d->to.index] & d->to.mask; 7357 7358 /* Not an error unless the dependent feature was added explicitly. */ 7359 mark_unavailable_features(cpu, d->to.index, 7360 unavailable_features & env->user_features[d->to.index], 7361 "This feature depends on other features that were not requested"); 7362 7363 env->features[d->to.index] &= ~unavailable_features; 7364 } 7365 } 7366 7367 if (!kvm_enabled() || !cpu->expose_kvm) { 7368 env->features[FEAT_KVM] = 0; 7369 } 7370 7371 x86_cpu_enable_xsave_components(cpu); 7372 7373 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */ 7374 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX); 7375 if (cpu->full_cpuid_auto_level) { 7376 x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX); 7377 x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX); 7378 x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX); 7379 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX); 7380 x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EAX); 7381 x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EDX); 7382 x86_cpu_adjust_feat_level(cpu, FEAT_7_2_EDX); 7383 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX); 7384 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX); 7385 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX); 7386 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0008_EBX); 7387 x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX); 7388 x86_cpu_adjust_feat_level(cpu, FEAT_SVM); 7389 x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE); 7390 7391 /* Intel Processor Trace requires CPUID[0x14] */ 7392 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT)) { 7393 if (cpu->intel_pt_auto_level) { 7394 x86_cpu_adjust_level(cpu, &cpu->env.cpuid_min_level, 0x14); 7395 } else if (cpu->env.cpuid_min_level < 0x14) { 7396 mark_unavailable_features(cpu, FEAT_7_0_EBX, 7397 CPUID_7_0_EBX_INTEL_PT, 7398 "Intel PT need CPUID leaf 0x14, please set by \"-cpu ...,intel-pt=on,min-level=0x14\""); 7399 } 7400 } 7401 7402 /* 7403 * Intel CPU topology with multi-dies support requires CPUID[0x1F]. 7404 * For AMD Rome/Milan, cpuid level is 0x10, and guest OS should detect 7405 * extended toplogy by leaf 0xB. Only adjust it for Intel CPU, unless 7406 * cpu->vendor_cpuid_only has been unset for compatibility with older 7407 * machine types. 7408 */ 7409 if (x86_has_extended_topo(env->avail_cpu_topo) && 7410 (IS_INTEL_CPU(env) || !cpu->vendor_cpuid_only)) { 7411 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x1F); 7412 } 7413 7414 /* SVM requires CPUID[0x8000000A] */ 7415 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { 7416 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A); 7417 } 7418 7419 /* SEV requires CPUID[0x8000001F] */ 7420 if (sev_enabled()) { 7421 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F); 7422 } 7423 7424 if (env->features[FEAT_8000_0021_EAX]) { 7425 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x80000021); 7426 } 7427 7428 /* SGX requires CPUID[0x12] for EPC enumeration */ 7429 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX) { 7430 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x12); 7431 } 7432 } 7433 7434 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */ 7435 if (env->cpuid_level_func7 == UINT32_MAX) { 7436 env->cpuid_level_func7 = env->cpuid_min_level_func7; 7437 } 7438 if (env->cpuid_level == UINT32_MAX) { 7439 env->cpuid_level = env->cpuid_min_level; 7440 } 7441 if (env->cpuid_xlevel == UINT32_MAX) { 7442 env->cpuid_xlevel = env->cpuid_min_xlevel; 7443 } 7444 if (env->cpuid_xlevel2 == UINT32_MAX) { 7445 env->cpuid_xlevel2 = env->cpuid_min_xlevel2; 7446 } 7447 7448 if (kvm_enabled() && !kvm_hyperv_expand_features(cpu, errp)) { 7449 return; 7450 } 7451 } 7452 7453 /* 7454 * Finishes initialization of CPUID data, filters CPU feature 7455 * words based on host availability of each feature. 7456 * 7457 * Returns: 0 if all flags are supported by the host, non-zero otherwise. 7458 */ 7459 static void x86_cpu_filter_features(X86CPU *cpu, bool verbose) 7460 { 7461 CPUX86State *env = &cpu->env; 7462 FeatureWord w; 7463 const char *prefix = NULL; 7464 7465 if (verbose) { 7466 prefix = accel_uses_host_cpuid() 7467 ? "host doesn't support requested feature" 7468 : "TCG doesn't support requested feature"; 7469 } 7470 7471 for (w = 0; w < FEATURE_WORDS; w++) { 7472 uint64_t host_feat = 7473 x86_cpu_get_supported_feature_word(w, false); 7474 uint64_t requested_features = env->features[w]; 7475 uint64_t unavailable_features = requested_features & ~host_feat; 7476 mark_unavailable_features(cpu, w, unavailable_features, prefix); 7477 } 7478 7479 /* 7480 * Check that KVM actually allows the processor tracing features that 7481 * are advertised by cpu_x86_cpuid(). Keep these two in sync. 7482 */ 7483 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) && 7484 kvm_enabled()) { 7485 uint32_t eax_0, ebx_0, ecx_0, edx_0_unused; 7486 uint32_t eax_1, ebx_1, ecx_1_unused, edx_1_unused; 7487 7488 x86_cpu_get_supported_cpuid(0x14, 0, 7489 &eax_0, &ebx_0, &ecx_0, &edx_0_unused); 7490 x86_cpu_get_supported_cpuid(0x14, 1, 7491 &eax_1, &ebx_1, &ecx_1_unused, &edx_1_unused); 7492 7493 if (!eax_0 || 7494 ((ebx_0 & INTEL_PT_MINIMAL_EBX) != INTEL_PT_MINIMAL_EBX) || 7495 ((ecx_0 & INTEL_PT_MINIMAL_ECX) != INTEL_PT_MINIMAL_ECX) || 7496 ((eax_1 & INTEL_PT_MTC_BITMAP) != INTEL_PT_MTC_BITMAP) || 7497 ((eax_1 & INTEL_PT_ADDR_RANGES_NUM_MASK) < 7498 INTEL_PT_ADDR_RANGES_NUM) || 7499 ((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) != 7500 (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) || 7501 ((ecx_0 & CPUID_14_0_ECX_LIP) != 7502 (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP))) { 7503 /* 7504 * Processor Trace capabilities aren't configurable, so if the 7505 * host can't emulate the capabilities we report on 7506 * cpu_x86_cpuid(), intel-pt can't be enabled on the current host. 7507 */ 7508 mark_unavailable_features(cpu, FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT, prefix); 7509 } 7510 } 7511 } 7512 7513 static void x86_cpu_hyperv_realize(X86CPU *cpu) 7514 { 7515 size_t len; 7516 7517 /* Hyper-V vendor id */ 7518 if (!cpu->hyperv_vendor) { 7519 object_property_set_str(OBJECT(cpu), "hv-vendor-id", "Microsoft Hv", 7520 &error_abort); 7521 } 7522 len = strlen(cpu->hyperv_vendor); 7523 if (len > 12) { 7524 warn_report("hv-vendor-id truncated to 12 characters"); 7525 len = 12; 7526 } 7527 memset(cpu->hyperv_vendor_id, 0, 12); 7528 memcpy(cpu->hyperv_vendor_id, cpu->hyperv_vendor, len); 7529 7530 /* 'Hv#1' interface identification*/ 7531 cpu->hyperv_interface_id[0] = 0x31237648; 7532 cpu->hyperv_interface_id[1] = 0; 7533 cpu->hyperv_interface_id[2] = 0; 7534 cpu->hyperv_interface_id[3] = 0; 7535 7536 /* Hypervisor implementation limits */ 7537 cpu->hyperv_limits[0] = 64; 7538 cpu->hyperv_limits[1] = 0; 7539 cpu->hyperv_limits[2] = 0; 7540 } 7541 7542 static void x86_cpu_realizefn(DeviceState *dev, Error **errp) 7543 { 7544 CPUState *cs = CPU(dev); 7545 X86CPU *cpu = X86_CPU(dev); 7546 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev); 7547 CPUX86State *env = &cpu->env; 7548 Error *local_err = NULL; 7549 unsigned requested_lbr_fmt; 7550 7551 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) 7552 /* Use pc-relative instructions in system-mode */ 7553 tcg_cflags_set(cs, CF_PCREL); 7554 #endif 7555 7556 if (cpu->apic_id == UNASSIGNED_APIC_ID) { 7557 error_setg(errp, "apic-id property was not initialized properly"); 7558 return; 7559 } 7560 7561 /* 7562 * Process Hyper-V enlightenments. 7563 * Note: this currently has to happen before the expansion of CPU features. 7564 */ 7565 x86_cpu_hyperv_realize(cpu); 7566 7567 x86_cpu_expand_features(cpu, &local_err); 7568 if (local_err) { 7569 goto out; 7570 } 7571 7572 /* 7573 * Override env->features[FEAT_PERF_CAPABILITIES].LBR_FMT 7574 * with user-provided setting. 7575 */ 7576 if (cpu->lbr_fmt != ~PERF_CAP_LBR_FMT) { 7577 if ((cpu->lbr_fmt & PERF_CAP_LBR_FMT) != cpu->lbr_fmt) { 7578 error_setg(errp, "invalid lbr-fmt"); 7579 return; 7580 } 7581 env->features[FEAT_PERF_CAPABILITIES] &= ~PERF_CAP_LBR_FMT; 7582 env->features[FEAT_PERF_CAPABILITIES] |= cpu->lbr_fmt; 7583 } 7584 7585 /* 7586 * vPMU LBR is supported when 1) KVM is enabled 2) Option pmu=on and 7587 * 3)vPMU LBR format matches that of host setting. 7588 */ 7589 requested_lbr_fmt = 7590 env->features[FEAT_PERF_CAPABILITIES] & PERF_CAP_LBR_FMT; 7591 if (requested_lbr_fmt && kvm_enabled()) { 7592 uint64_t host_perf_cap = 7593 x86_cpu_get_supported_feature_word(FEAT_PERF_CAPABILITIES, false); 7594 unsigned host_lbr_fmt = host_perf_cap & PERF_CAP_LBR_FMT; 7595 7596 if (!cpu->enable_pmu) { 7597 error_setg(errp, "vPMU: LBR is unsupported without pmu=on"); 7598 return; 7599 } 7600 if (requested_lbr_fmt != host_lbr_fmt) { 7601 error_setg(errp, "vPMU: the lbr-fmt value (0x%x) does not match " 7602 "the host value (0x%x).", 7603 requested_lbr_fmt, host_lbr_fmt); 7604 return; 7605 } 7606 } 7607 7608 x86_cpu_filter_features(cpu, cpu->check_cpuid || cpu->enforce_cpuid); 7609 7610 if (cpu->enforce_cpuid && x86_cpu_have_filtered_features(cpu)) { 7611 error_setg(&local_err, 7612 accel_uses_host_cpuid() ? 7613 "Host doesn't support requested features" : 7614 "TCG doesn't support requested features"); 7615 goto out; 7616 } 7617 7618 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on 7619 * CPUID[1].EDX. 7620 */ 7621 if (IS_AMD_CPU(env)) { 7622 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES; 7623 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX] 7624 & CPUID_EXT2_AMD_ALIASES); 7625 } 7626 7627 x86_cpu_set_sgxlepubkeyhash(env); 7628 7629 /* 7630 * note: the call to the framework needs to happen after feature expansion, 7631 * but before the checks/modifications to ucode_rev, mwait, phys_bits. 7632 * These may be set by the accel-specific code, 7633 * and the results are subsequently checked / assumed in this function. 7634 */ 7635 cpu_exec_realizefn(cs, &local_err); 7636 if (local_err != NULL) { 7637 error_propagate(errp, local_err); 7638 return; 7639 } 7640 7641 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) { 7642 g_autofree char *name = x86_cpu_class_get_model_name(xcc); 7643 error_setg(&local_err, "CPU model '%s' requires KVM or HVF", name); 7644 goto out; 7645 } 7646 7647 if (cpu->guest_phys_bits == -1) { 7648 /* 7649 * If it was not set by the user, or by the accelerator via 7650 * cpu_exec_realizefn, clear. 7651 */ 7652 cpu->guest_phys_bits = 0; 7653 } 7654 7655 if (cpu->ucode_rev == 0) { 7656 /* 7657 * The default is the same as KVM's. Note that this check 7658 * needs to happen after the evenual setting of ucode_rev in 7659 * accel-specific code in cpu_exec_realizefn. 7660 */ 7661 if (IS_AMD_CPU(env)) { 7662 cpu->ucode_rev = 0x01000065; 7663 } else { 7664 cpu->ucode_rev = 0x100000000ULL; 7665 } 7666 } 7667 7668 /* 7669 * mwait extended info: needed for Core compatibility 7670 * We always wake on interrupt even if host does not have the capability. 7671 * 7672 * requires the accel-specific code in cpu_exec_realizefn to 7673 * have already acquired the CPUID data into cpu->mwait. 7674 */ 7675 cpu->mwait.ecx |= CPUID_MWAIT_EMX | CPUID_MWAIT_IBE; 7676 7677 /* For 64bit systems think about the number of physical bits to present. 7678 * ideally this should be the same as the host; anything other than matching 7679 * the host can cause incorrect guest behaviour. 7680 * QEMU used to pick the magic value of 40 bits that corresponds to 7681 * consumer AMD devices but nothing else. 7682 * 7683 * Note that this code assumes features expansion has already been done 7684 * (as it checks for CPUID_EXT2_LM), and also assumes that potential 7685 * phys_bits adjustments to match the host have been already done in 7686 * accel-specific code in cpu_exec_realizefn. 7687 */ 7688 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 7689 if (cpu->phys_bits && 7690 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS || 7691 cpu->phys_bits < 32)) { 7692 error_setg(errp, "phys-bits should be between 32 and %u " 7693 " (but is %u)", 7694 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits); 7695 return; 7696 } 7697 /* 7698 * 0 means it was not explicitly set by the user (or by machine 7699 * compat_props or by the host code in host-cpu.c). 7700 * In this case, the default is the value used by TCG (40). 7701 */ 7702 if (cpu->phys_bits == 0) { 7703 cpu->phys_bits = TCG_PHYS_ADDR_BITS; 7704 } 7705 if (cpu->guest_phys_bits && 7706 (cpu->guest_phys_bits > cpu->phys_bits || 7707 cpu->guest_phys_bits < 32)) { 7708 error_setg(errp, "guest-phys-bits should be between 32 and %u " 7709 " (but is %u)", 7710 cpu->phys_bits, cpu->guest_phys_bits); 7711 return; 7712 } 7713 } else { 7714 /* For 32 bit systems don't use the user set value, but keep 7715 * phys_bits consistent with what we tell the guest. 7716 */ 7717 if (cpu->phys_bits != 0) { 7718 error_setg(errp, "phys-bits is not user-configurable in 32 bit"); 7719 return; 7720 } 7721 if (cpu->guest_phys_bits != 0) { 7722 error_setg(errp, "guest-phys-bits is not user-configurable in 32 bit"); 7723 return; 7724 } 7725 7726 if (env->features[FEAT_1_EDX] & (CPUID_PSE36 | CPUID_PAE)) { 7727 cpu->phys_bits = 36; 7728 } else { 7729 cpu->phys_bits = 32; 7730 } 7731 } 7732 7733 /* Cache information initialization */ 7734 if (!cpu->legacy_cache) { 7735 const CPUCaches *cache_info = 7736 x86_cpu_get_versioned_cache_info(cpu, xcc->model); 7737 7738 if (!xcc->model || !cache_info) { 7739 g_autofree char *name = x86_cpu_class_get_model_name(xcc); 7740 error_setg(errp, 7741 "CPU model '%s' doesn't support legacy-cache=off", name); 7742 return; 7743 } 7744 env->cache_info_cpuid2 = env->cache_info_cpuid4 = env->cache_info_amd = 7745 *cache_info; 7746 } else { 7747 /* Build legacy cache information */ 7748 env->cache_info_cpuid2.l1d_cache = &legacy_l1d_cache; 7749 env->cache_info_cpuid2.l1i_cache = &legacy_l1i_cache; 7750 env->cache_info_cpuid2.l2_cache = &legacy_l2_cache_cpuid2; 7751 env->cache_info_cpuid2.l3_cache = &legacy_l3_cache; 7752 7753 env->cache_info_cpuid4.l1d_cache = &legacy_l1d_cache; 7754 env->cache_info_cpuid4.l1i_cache = &legacy_l1i_cache; 7755 env->cache_info_cpuid4.l2_cache = &legacy_l2_cache; 7756 env->cache_info_cpuid4.l3_cache = &legacy_l3_cache; 7757 7758 env->cache_info_amd.l1d_cache = &legacy_l1d_cache_amd; 7759 env->cache_info_amd.l1i_cache = &legacy_l1i_cache_amd; 7760 env->cache_info_amd.l2_cache = &legacy_l2_cache_amd; 7761 env->cache_info_amd.l3_cache = &legacy_l3_cache; 7762 } 7763 7764 #ifndef CONFIG_USER_ONLY 7765 MachineState *ms = MACHINE(qdev_get_machine()); 7766 qemu_register_reset(x86_cpu_machine_reset_cb, cpu); 7767 7768 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || ms->smp.cpus > 1) { 7769 x86_cpu_apic_create(cpu, &local_err); 7770 if (local_err != NULL) { 7771 goto out; 7772 } 7773 } 7774 #endif 7775 7776 mce_init(cpu); 7777 7778 qemu_init_vcpu(cs); 7779 7780 /* 7781 * Most Intel and certain AMD CPUs support hyperthreading. Even though QEMU 7782 * fixes this issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX 7783 * based on inputs (sockets,cores,threads), it is still better to give 7784 * users a warning. 7785 * 7786 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise 7787 * cs->nr_threads hasn't be populated yet and the checking is incorrect. 7788 */ 7789 if (IS_AMD_CPU(env) && 7790 !(env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) && 7791 cs->nr_threads > 1) { 7792 warn_report_once("This family of AMD CPU doesn't support " 7793 "hyperthreading(%d). Please configure -smp " 7794 "options properly or try enabling topoext " 7795 "feature.", cs->nr_threads); 7796 } 7797 7798 #ifndef CONFIG_USER_ONLY 7799 x86_cpu_apic_realize(cpu, &local_err); 7800 if (local_err != NULL) { 7801 goto out; 7802 } 7803 #endif /* !CONFIG_USER_ONLY */ 7804 cpu_reset(cs); 7805 7806 xcc->parent_realize(dev, &local_err); 7807 7808 out: 7809 if (local_err != NULL) { 7810 error_propagate(errp, local_err); 7811 return; 7812 } 7813 } 7814 7815 static void x86_cpu_unrealizefn(DeviceState *dev) 7816 { 7817 X86CPU *cpu = X86_CPU(dev); 7818 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev); 7819 7820 #ifndef CONFIG_USER_ONLY 7821 cpu_remove_sync(CPU(dev)); 7822 qemu_unregister_reset(x86_cpu_machine_reset_cb, dev); 7823 #endif 7824 7825 if (cpu->apic_state) { 7826 object_unparent(OBJECT(cpu->apic_state)); 7827 cpu->apic_state = NULL; 7828 } 7829 7830 xcc->parent_unrealize(dev); 7831 } 7832 7833 typedef struct BitProperty { 7834 FeatureWord w; 7835 uint64_t mask; 7836 } BitProperty; 7837 7838 static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name, 7839 void *opaque, Error **errp) 7840 { 7841 X86CPU *cpu = X86_CPU(obj); 7842 BitProperty *fp = opaque; 7843 uint64_t f = cpu->env.features[fp->w]; 7844 bool value = (f & fp->mask) == fp->mask; 7845 visit_type_bool(v, name, &value, errp); 7846 } 7847 7848 static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name, 7849 void *opaque, Error **errp) 7850 { 7851 DeviceState *dev = DEVICE(obj); 7852 X86CPU *cpu = X86_CPU(obj); 7853 BitProperty *fp = opaque; 7854 bool value; 7855 7856 if (dev->realized) { 7857 qdev_prop_set_after_realize(dev, name, errp); 7858 return; 7859 } 7860 7861 if (!visit_type_bool(v, name, &value, errp)) { 7862 return; 7863 } 7864 7865 if (value) { 7866 cpu->env.features[fp->w] |= fp->mask; 7867 } else { 7868 cpu->env.features[fp->w] &= ~fp->mask; 7869 } 7870 cpu->env.user_features[fp->w] |= fp->mask; 7871 } 7872 7873 /* Register a boolean property to get/set a single bit in a uint32_t field. 7874 * 7875 * The same property name can be registered multiple times to make it affect 7876 * multiple bits in the same FeatureWord. In that case, the getter will return 7877 * true only if all bits are set. 7878 */ 7879 static void x86_cpu_register_bit_prop(X86CPUClass *xcc, 7880 const char *prop_name, 7881 FeatureWord w, 7882 int bitnr) 7883 { 7884 ObjectClass *oc = OBJECT_CLASS(xcc); 7885 BitProperty *fp; 7886 ObjectProperty *op; 7887 uint64_t mask = (1ULL << bitnr); 7888 7889 op = object_class_property_find(oc, prop_name); 7890 if (op) { 7891 fp = op->opaque; 7892 assert(fp->w == w); 7893 fp->mask |= mask; 7894 } else { 7895 fp = g_new0(BitProperty, 1); 7896 fp->w = w; 7897 fp->mask = mask; 7898 object_class_property_add(oc, prop_name, "bool", 7899 x86_cpu_get_bit_prop, 7900 x86_cpu_set_bit_prop, 7901 NULL, fp); 7902 } 7903 } 7904 7905 static void x86_cpu_register_feature_bit_props(X86CPUClass *xcc, 7906 FeatureWord w, 7907 int bitnr) 7908 { 7909 FeatureWordInfo *fi = &feature_word_info[w]; 7910 const char *name = fi->feat_names[bitnr]; 7911 7912 if (!name) { 7913 return; 7914 } 7915 7916 /* Property names should use "-" instead of "_". 7917 * Old names containing underscores are registered as aliases 7918 * using object_property_add_alias() 7919 */ 7920 assert(!strchr(name, '_')); 7921 /* aliases don't use "|" delimiters anymore, they are registered 7922 * manually using object_property_add_alias() */ 7923 assert(!strchr(name, '|')); 7924 x86_cpu_register_bit_prop(xcc, name, w, bitnr); 7925 } 7926 7927 static void x86_cpu_post_initfn(Object *obj) 7928 { 7929 accel_cpu_instance_init(CPU(obj)); 7930 } 7931 7932 static void x86_cpu_init_default_topo(X86CPU *cpu) 7933 { 7934 CPUX86State *env = &cpu->env; 7935 7936 env->nr_modules = 1; 7937 env->nr_dies = 1; 7938 7939 /* SMT, core and package levels are set by default. */ 7940 set_bit(CPU_TOPO_LEVEL_SMT, env->avail_cpu_topo); 7941 set_bit(CPU_TOPO_LEVEL_CORE, env->avail_cpu_topo); 7942 set_bit(CPU_TOPO_LEVEL_PACKAGE, env->avail_cpu_topo); 7943 } 7944 7945 static void x86_cpu_initfn(Object *obj) 7946 { 7947 X86CPU *cpu = X86_CPU(obj); 7948 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj); 7949 CPUX86State *env = &cpu->env; 7950 7951 x86_cpu_init_default_topo(cpu); 7952 7953 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo", 7954 x86_cpu_get_feature_words, 7955 NULL, NULL, (void *)env->features); 7956 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo", 7957 x86_cpu_get_feature_words, 7958 NULL, NULL, (void *)cpu->filtered_features); 7959 7960 object_property_add_alias(obj, "sse3", obj, "pni"); 7961 object_property_add_alias(obj, "pclmuldq", obj, "pclmulqdq"); 7962 object_property_add_alias(obj, "sse4-1", obj, "sse4.1"); 7963 object_property_add_alias(obj, "sse4-2", obj, "sse4.2"); 7964 object_property_add_alias(obj, "xd", obj, "nx"); 7965 object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt"); 7966 object_property_add_alias(obj, "i64", obj, "lm"); 7967 7968 object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl"); 7969 object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust"); 7970 object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt"); 7971 object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm"); 7972 object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy"); 7973 object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr"); 7974 object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core"); 7975 object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb"); 7976 object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay"); 7977 object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu"); 7978 object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf"); 7979 object_property_add_alias(obj, "kvm_asyncpf_int", obj, "kvm-asyncpf-int"); 7980 object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time"); 7981 object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi"); 7982 object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt"); 7983 object_property_add_alias(obj, "kvm_poll_control", obj, "kvm-poll-control"); 7984 object_property_add_alias(obj, "svm_lock", obj, "svm-lock"); 7985 object_property_add_alias(obj, "nrip_save", obj, "nrip-save"); 7986 object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale"); 7987 object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean"); 7988 object_property_add_alias(obj, "pause_filter", obj, "pause-filter"); 7989 object_property_add_alias(obj, "sse4_1", obj, "sse4.1"); 7990 object_property_add_alias(obj, "sse4_2", obj, "sse4.2"); 7991 7992 object_property_add_alias(obj, "hv-apicv", obj, "hv-avic"); 7993 cpu->lbr_fmt = ~PERF_CAP_LBR_FMT; 7994 object_property_add_alias(obj, "lbr_fmt", obj, "lbr-fmt"); 7995 7996 if (xcc->model) { 7997 x86_cpu_load_model(cpu, xcc->model); 7998 } 7999 } 8000 8001 static int64_t x86_cpu_get_arch_id(CPUState *cs) 8002 { 8003 X86CPU *cpu = X86_CPU(cs); 8004 8005 return cpu->apic_id; 8006 } 8007 8008 #if !defined(CONFIG_USER_ONLY) 8009 static bool x86_cpu_get_paging_enabled(const CPUState *cs) 8010 { 8011 X86CPU *cpu = X86_CPU(cs); 8012 8013 return cpu->env.cr[0] & CR0_PG_MASK; 8014 } 8015 #endif /* !CONFIG_USER_ONLY */ 8016 8017 static void x86_cpu_set_pc(CPUState *cs, vaddr value) 8018 { 8019 X86CPU *cpu = X86_CPU(cs); 8020 8021 cpu->env.eip = value; 8022 } 8023 8024 static vaddr x86_cpu_get_pc(CPUState *cs) 8025 { 8026 X86CPU *cpu = X86_CPU(cs); 8027 8028 /* Match cpu_get_tb_cpu_state. */ 8029 return cpu->env.eip + cpu->env.segs[R_CS].base; 8030 } 8031 8032 int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request) 8033 { 8034 X86CPU *cpu = X86_CPU(cs); 8035 CPUX86State *env = &cpu->env; 8036 8037 #if !defined(CONFIG_USER_ONLY) 8038 if (interrupt_request & CPU_INTERRUPT_POLL) { 8039 return CPU_INTERRUPT_POLL; 8040 } 8041 #endif 8042 if (interrupt_request & CPU_INTERRUPT_SIPI) { 8043 return CPU_INTERRUPT_SIPI; 8044 } 8045 8046 if (env->hflags2 & HF2_GIF_MASK) { 8047 if ((interrupt_request & CPU_INTERRUPT_SMI) && 8048 !(env->hflags & HF_SMM_MASK)) { 8049 return CPU_INTERRUPT_SMI; 8050 } else if ((interrupt_request & CPU_INTERRUPT_NMI) && 8051 !(env->hflags2 & HF2_NMI_MASK)) { 8052 return CPU_INTERRUPT_NMI; 8053 } else if (interrupt_request & CPU_INTERRUPT_MCE) { 8054 return CPU_INTERRUPT_MCE; 8055 } else if ((interrupt_request & CPU_INTERRUPT_HARD) && 8056 (((env->hflags2 & HF2_VINTR_MASK) && 8057 (env->hflags2 & HF2_HIF_MASK)) || 8058 (!(env->hflags2 & HF2_VINTR_MASK) && 8059 (env->eflags & IF_MASK && 8060 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) { 8061 return CPU_INTERRUPT_HARD; 8062 #if !defined(CONFIG_USER_ONLY) 8063 } else if (env->hflags2 & HF2_VGIF_MASK) { 8064 if((interrupt_request & CPU_INTERRUPT_VIRQ) && 8065 (env->eflags & IF_MASK) && 8066 !(env->hflags & HF_INHIBIT_IRQ_MASK)) { 8067 return CPU_INTERRUPT_VIRQ; 8068 } 8069 #endif 8070 } 8071 } 8072 8073 return 0; 8074 } 8075 8076 static bool x86_cpu_has_work(CPUState *cs) 8077 { 8078 return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0; 8079 } 8080 8081 static int x86_cpu_mmu_index(CPUState *cs, bool ifetch) 8082 { 8083 CPUX86State *env = cpu_env(cs); 8084 int mmu_index_32 = (env->hflags & HF_CS64_MASK) ? 0 : 1; 8085 int mmu_index_base = 8086 (env->hflags & HF_CPL_MASK) == 3 ? MMU_USER64_IDX : 8087 !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP64_IDX : 8088 (env->eflags & AC_MASK) ? MMU_KNOSMAP64_IDX : MMU_KSMAP64_IDX; 8089 8090 return mmu_index_base + mmu_index_32; 8091 } 8092 8093 static void x86_disas_set_info(CPUState *cs, disassemble_info *info) 8094 { 8095 X86CPU *cpu = X86_CPU(cs); 8096 CPUX86State *env = &cpu->env; 8097 8098 info->mach = (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64 8099 : env->hflags & HF_CS32_MASK ? bfd_mach_i386_i386 8100 : bfd_mach_i386_i8086); 8101 8102 info->cap_arch = CS_ARCH_X86; 8103 info->cap_mode = (env->hflags & HF_CS64_MASK ? CS_MODE_64 8104 : env->hflags & HF_CS32_MASK ? CS_MODE_32 8105 : CS_MODE_16); 8106 info->cap_insn_unit = 1; 8107 info->cap_insn_split = 8; 8108 } 8109 8110 void x86_update_hflags(CPUX86State *env) 8111 { 8112 uint32_t hflags; 8113 #define HFLAG_COPY_MASK \ 8114 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \ 8115 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \ 8116 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \ 8117 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK) 8118 8119 hflags = env->hflags & HFLAG_COPY_MASK; 8120 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK; 8121 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT); 8122 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) & 8123 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK); 8124 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK)); 8125 8126 if (env->cr[4] & CR4_OSFXSR_MASK) { 8127 hflags |= HF_OSFXSR_MASK; 8128 } 8129 8130 if (env->efer & MSR_EFER_LMA) { 8131 hflags |= HF_LMA_MASK; 8132 } 8133 8134 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) { 8135 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; 8136 } else { 8137 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >> 8138 (DESC_B_SHIFT - HF_CS32_SHIFT); 8139 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >> 8140 (DESC_B_SHIFT - HF_SS32_SHIFT); 8141 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) || 8142 !(hflags & HF_CS32_MASK)) { 8143 hflags |= HF_ADDSEG_MASK; 8144 } else { 8145 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base | 8146 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT; 8147 } 8148 } 8149 env->hflags = hflags; 8150 } 8151 8152 static Property x86_cpu_properties[] = { 8153 #ifdef CONFIG_USER_ONLY 8154 /* apic_id = 0 by default for *-user, see commit 9886e834 */ 8155 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0), 8156 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0), 8157 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0), 8158 DEFINE_PROP_INT32("module-id", X86CPU, module_id, 0), 8159 DEFINE_PROP_INT32("die-id", X86CPU, die_id, 0), 8160 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0), 8161 #else 8162 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID), 8163 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1), 8164 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1), 8165 DEFINE_PROP_INT32("module-id", X86CPU, module_id, -1), 8166 DEFINE_PROP_INT32("die-id", X86CPU, die_id, -1), 8167 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1), 8168 #endif 8169 DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID), 8170 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false), 8171 DEFINE_PROP_UINT64_CHECKMASK("lbr-fmt", X86CPU, lbr_fmt, PERF_CAP_LBR_FMT), 8172 8173 DEFINE_PROP_UINT32("hv-spinlocks", X86CPU, hyperv_spinlock_attempts, 8174 HYPERV_SPINLOCK_NEVER_NOTIFY), 8175 DEFINE_PROP_BIT64("hv-relaxed", X86CPU, hyperv_features, 8176 HYPERV_FEAT_RELAXED, 0), 8177 DEFINE_PROP_BIT64("hv-vapic", X86CPU, hyperv_features, 8178 HYPERV_FEAT_VAPIC, 0), 8179 DEFINE_PROP_BIT64("hv-time", X86CPU, hyperv_features, 8180 HYPERV_FEAT_TIME, 0), 8181 DEFINE_PROP_BIT64("hv-crash", X86CPU, hyperv_features, 8182 HYPERV_FEAT_CRASH, 0), 8183 DEFINE_PROP_BIT64("hv-reset", X86CPU, hyperv_features, 8184 HYPERV_FEAT_RESET, 0), 8185 DEFINE_PROP_BIT64("hv-vpindex", X86CPU, hyperv_features, 8186 HYPERV_FEAT_VPINDEX, 0), 8187 DEFINE_PROP_BIT64("hv-runtime", X86CPU, hyperv_features, 8188 HYPERV_FEAT_RUNTIME, 0), 8189 DEFINE_PROP_BIT64("hv-synic", X86CPU, hyperv_features, 8190 HYPERV_FEAT_SYNIC, 0), 8191 DEFINE_PROP_BIT64("hv-stimer", X86CPU, hyperv_features, 8192 HYPERV_FEAT_STIMER, 0), 8193 DEFINE_PROP_BIT64("hv-frequencies", X86CPU, hyperv_features, 8194 HYPERV_FEAT_FREQUENCIES, 0), 8195 DEFINE_PROP_BIT64("hv-reenlightenment", X86CPU, hyperv_features, 8196 HYPERV_FEAT_REENLIGHTENMENT, 0), 8197 DEFINE_PROP_BIT64("hv-tlbflush", X86CPU, hyperv_features, 8198 HYPERV_FEAT_TLBFLUSH, 0), 8199 DEFINE_PROP_BIT64("hv-evmcs", X86CPU, hyperv_features, 8200 HYPERV_FEAT_EVMCS, 0), 8201 DEFINE_PROP_BIT64("hv-ipi", X86CPU, hyperv_features, 8202 HYPERV_FEAT_IPI, 0), 8203 DEFINE_PROP_BIT64("hv-stimer-direct", X86CPU, hyperv_features, 8204 HYPERV_FEAT_STIMER_DIRECT, 0), 8205 DEFINE_PROP_BIT64("hv-avic", X86CPU, hyperv_features, 8206 HYPERV_FEAT_AVIC, 0), 8207 DEFINE_PROP_BIT64("hv-emsr-bitmap", X86CPU, hyperv_features, 8208 HYPERV_FEAT_MSR_BITMAP, 0), 8209 DEFINE_PROP_BIT64("hv-xmm-input", X86CPU, hyperv_features, 8210 HYPERV_FEAT_XMM_INPUT, 0), 8211 DEFINE_PROP_BIT64("hv-tlbflush-ext", X86CPU, hyperv_features, 8212 HYPERV_FEAT_TLBFLUSH_EXT, 0), 8213 DEFINE_PROP_BIT64("hv-tlbflush-direct", X86CPU, hyperv_features, 8214 HYPERV_FEAT_TLBFLUSH_DIRECT, 0), 8215 DEFINE_PROP_ON_OFF_AUTO("hv-no-nonarch-coresharing", X86CPU, 8216 hyperv_no_nonarch_cs, ON_OFF_AUTO_OFF), 8217 DEFINE_PROP_BIT64("hv-syndbg", X86CPU, hyperv_features, 8218 HYPERV_FEAT_SYNDBG, 0), 8219 DEFINE_PROP_BOOL("hv-passthrough", X86CPU, hyperv_passthrough, false), 8220 DEFINE_PROP_BOOL("hv-enforce-cpuid", X86CPU, hyperv_enforce_cpuid, false), 8221 8222 /* WS2008R2 identify by default */ 8223 DEFINE_PROP_UINT32("hv-version-id-build", X86CPU, hyperv_ver_id_build, 8224 0x3839), 8225 DEFINE_PROP_UINT16("hv-version-id-major", X86CPU, hyperv_ver_id_major, 8226 0x000A), 8227 DEFINE_PROP_UINT16("hv-version-id-minor", X86CPU, hyperv_ver_id_minor, 8228 0x0000), 8229 DEFINE_PROP_UINT32("hv-version-id-spack", X86CPU, hyperv_ver_id_sp, 0), 8230 DEFINE_PROP_UINT8("hv-version-id-sbranch", X86CPU, hyperv_ver_id_sb, 0), 8231 DEFINE_PROP_UINT32("hv-version-id-snumber", X86CPU, hyperv_ver_id_sn, 0), 8232 8233 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true), 8234 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false), 8235 DEFINE_PROP_BOOL("x-force-features", X86CPU, force_features, false), 8236 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true), 8237 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0), 8238 DEFINE_PROP_UINT32("guest-phys-bits", X86CPU, guest_phys_bits, -1), 8239 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false), 8240 DEFINE_PROP_UINT8("host-phys-bits-limit", X86CPU, host_phys_bits_limit, 0), 8241 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true), 8242 DEFINE_PROP_UINT32("level-func7", X86CPU, env.cpuid_level_func7, 8243 UINT32_MAX), 8244 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX), 8245 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX), 8246 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX), 8247 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0), 8248 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0), 8249 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0), 8250 DEFINE_PROP_UINT64("ucode-rev", X86CPU, ucode_rev, 0), 8251 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true), 8252 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor), 8253 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true), 8254 DEFINE_PROP_BOOL("x-vendor-cpuid-only", X86CPU, vendor_cpuid_only, true), 8255 DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false), 8256 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true), 8257 DEFINE_PROP_BOOL("kvm-no-smi-migration", X86CPU, kvm_no_smi_migration, 8258 false), 8259 DEFINE_PROP_BOOL("kvm-pv-enforce-cpuid", X86CPU, kvm_pv_enforce_cpuid, 8260 false), 8261 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true), 8262 DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true), 8263 DEFINE_PROP_BOOL("x-migrate-smi-count", X86CPU, migrate_smi_count, 8264 true), 8265 /* 8266 * lecacy_cache defaults to true unless the CPU model provides its 8267 * own cache information (see x86_cpu_load_def()). 8268 */ 8269 DEFINE_PROP_BOOL("legacy-cache", X86CPU, legacy_cache, true), 8270 DEFINE_PROP_BOOL("legacy-multi-node", X86CPU, legacy_multi_node, false), 8271 DEFINE_PROP_BOOL("xen-vapic", X86CPU, xen_vapic, false), 8272 8273 /* 8274 * From "Requirements for Implementing the Microsoft 8275 * Hypervisor Interface": 8276 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs 8277 * 8278 * "Starting with Windows Server 2012 and Windows 8, if 8279 * CPUID.40000005.EAX contains a value of -1, Windows assumes that 8280 * the hypervisor imposes no specific limit to the number of VPs. 8281 * In this case, Windows Server 2012 guest VMs may use more than 8282 * 64 VPs, up to the maximum supported number of processors applicable 8283 * to the specific Windows version being used." 8284 */ 8285 DEFINE_PROP_INT32("x-hv-max-vps", X86CPU, hv_max_vps, -1), 8286 DEFINE_PROP_BOOL("x-hv-synic-kvm-only", X86CPU, hyperv_synic_kvm_only, 8287 false), 8288 DEFINE_PROP_BOOL("x-intel-pt-auto-level", X86CPU, intel_pt_auto_level, 8289 true), 8290 DEFINE_PROP_BOOL("x-l1-cache-per-thread", X86CPU, l1_cache_per_core, true), 8291 DEFINE_PROP_END_OF_LIST() 8292 }; 8293 8294 #ifndef CONFIG_USER_ONLY 8295 #include "hw/core/sysemu-cpu-ops.h" 8296 8297 static const struct SysemuCPUOps i386_sysemu_ops = { 8298 .get_memory_mapping = x86_cpu_get_memory_mapping, 8299 .get_paging_enabled = x86_cpu_get_paging_enabled, 8300 .get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug, 8301 .asidx_from_attrs = x86_asidx_from_attrs, 8302 .get_crash_info = x86_cpu_get_crash_info, 8303 .write_elf32_note = x86_cpu_write_elf32_note, 8304 .write_elf64_note = x86_cpu_write_elf64_note, 8305 .write_elf32_qemunote = x86_cpu_write_elf32_qemunote, 8306 .write_elf64_qemunote = x86_cpu_write_elf64_qemunote, 8307 .legacy_vmsd = &vmstate_x86_cpu, 8308 }; 8309 #endif 8310 8311 static void x86_cpu_common_class_init(ObjectClass *oc, void *data) 8312 { 8313 X86CPUClass *xcc = X86_CPU_CLASS(oc); 8314 CPUClass *cc = CPU_CLASS(oc); 8315 DeviceClass *dc = DEVICE_CLASS(oc); 8316 ResettableClass *rc = RESETTABLE_CLASS(oc); 8317 FeatureWord w; 8318 8319 device_class_set_parent_realize(dc, x86_cpu_realizefn, 8320 &xcc->parent_realize); 8321 device_class_set_parent_unrealize(dc, x86_cpu_unrealizefn, 8322 &xcc->parent_unrealize); 8323 device_class_set_props(dc, x86_cpu_properties); 8324 8325 resettable_class_set_parent_phases(rc, NULL, x86_cpu_reset_hold, NULL, 8326 &xcc->parent_phases); 8327 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP; 8328 8329 cc->class_by_name = x86_cpu_class_by_name; 8330 cc->parse_features = x86_cpu_parse_featurestr; 8331 cc->has_work = x86_cpu_has_work; 8332 cc->mmu_index = x86_cpu_mmu_index; 8333 cc->dump_state = x86_cpu_dump_state; 8334 cc->set_pc = x86_cpu_set_pc; 8335 cc->get_pc = x86_cpu_get_pc; 8336 cc->gdb_read_register = x86_cpu_gdb_read_register; 8337 cc->gdb_write_register = x86_cpu_gdb_write_register; 8338 cc->get_arch_id = x86_cpu_get_arch_id; 8339 8340 #ifndef CONFIG_USER_ONLY 8341 cc->sysemu_ops = &i386_sysemu_ops; 8342 #endif /* !CONFIG_USER_ONLY */ 8343 8344 cc->gdb_arch_name = x86_gdb_arch_name; 8345 #ifdef TARGET_X86_64 8346 cc->gdb_core_xml_file = "i386-64bit.xml"; 8347 #else 8348 cc->gdb_core_xml_file = "i386-32bit.xml"; 8349 #endif 8350 cc->disas_set_info = x86_disas_set_info; 8351 8352 dc->user_creatable = true; 8353 8354 object_class_property_add(oc, "family", "int", 8355 x86_cpuid_version_get_family, 8356 x86_cpuid_version_set_family, NULL, NULL); 8357 object_class_property_add(oc, "model", "int", 8358 x86_cpuid_version_get_model, 8359 x86_cpuid_version_set_model, NULL, NULL); 8360 object_class_property_add(oc, "stepping", "int", 8361 x86_cpuid_version_get_stepping, 8362 x86_cpuid_version_set_stepping, NULL, NULL); 8363 object_class_property_add_str(oc, "vendor", 8364 x86_cpuid_get_vendor, 8365 x86_cpuid_set_vendor); 8366 object_class_property_add_str(oc, "model-id", 8367 x86_cpuid_get_model_id, 8368 x86_cpuid_set_model_id); 8369 object_class_property_add(oc, "tsc-frequency", "int", 8370 x86_cpuid_get_tsc_freq, 8371 x86_cpuid_set_tsc_freq, NULL, NULL); 8372 /* 8373 * The "unavailable-features" property has the same semantics as 8374 * CpuDefinitionInfo.unavailable-features on the "query-cpu-definitions" 8375 * QMP command: they list the features that would have prevented the 8376 * CPU from running if the "enforce" flag was set. 8377 */ 8378 object_class_property_add(oc, "unavailable-features", "strList", 8379 x86_cpu_get_unavailable_features, 8380 NULL, NULL, NULL); 8381 8382 #if !defined(CONFIG_USER_ONLY) 8383 object_class_property_add(oc, "crash-information", "GuestPanicInformation", 8384 x86_cpu_get_crash_info_qom, NULL, NULL, NULL); 8385 #endif 8386 8387 for (w = 0; w < FEATURE_WORDS; w++) { 8388 int bitnr; 8389 for (bitnr = 0; bitnr < 64; bitnr++) { 8390 x86_cpu_register_feature_bit_props(xcc, w, bitnr); 8391 } 8392 } 8393 } 8394 8395 static const TypeInfo x86_cpu_type_info = { 8396 .name = TYPE_X86_CPU, 8397 .parent = TYPE_CPU, 8398 .instance_size = sizeof(X86CPU), 8399 .instance_align = __alignof(X86CPU), 8400 .instance_init = x86_cpu_initfn, 8401 .instance_post_init = x86_cpu_post_initfn, 8402 8403 .abstract = true, 8404 .class_size = sizeof(X86CPUClass), 8405 .class_init = x86_cpu_common_class_init, 8406 }; 8407 8408 /* "base" CPU model, used by query-cpu-model-expansion */ 8409 static void x86_cpu_base_class_init(ObjectClass *oc, void *data) 8410 { 8411 X86CPUClass *xcc = X86_CPU_CLASS(oc); 8412 8413 xcc->static_model = true; 8414 xcc->migration_safe = true; 8415 xcc->model_description = "base CPU model type with no features enabled"; 8416 xcc->ordering = 8; 8417 } 8418 8419 static const TypeInfo x86_base_cpu_type_info = { 8420 .name = X86_CPU_TYPE_NAME("base"), 8421 .parent = TYPE_X86_CPU, 8422 .class_init = x86_cpu_base_class_init, 8423 }; 8424 8425 static void x86_cpu_register_types(void) 8426 { 8427 int i; 8428 8429 type_register_static(&x86_cpu_type_info); 8430 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) { 8431 x86_register_cpudef_types(&builtin_x86_defs[i]); 8432 } 8433 type_register_static(&max_x86_cpu_type_info); 8434 type_register_static(&x86_base_cpu_type_info); 8435 } 8436 8437 type_init(x86_cpu_register_types) 8438