1 /* 2 * i386 CPUID, CPU class, definitions, models 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/units.h" 22 #include "qemu/cutils.h" 23 #include "qemu/qemu-print.h" 24 #include "qemu/hw-version.h" 25 #include "cpu.h" 26 #include "tcg/helper-tcg.h" 27 #include "sysemu/reset.h" 28 #include "sysemu/hvf.h" 29 #include "kvm/kvm_i386.h" 30 #include "sev.h" 31 #include "qapi/error.h" 32 #include "qemu/error-report.h" 33 #include "qapi/qapi-visit-machine.h" 34 #include "qapi/qmp/qerror.h" 35 #include "standard-headers/asm-x86/kvm_para.h" 36 #include "hw/qdev-properties.h" 37 #include "hw/i386/topology.h" 38 #ifndef CONFIG_USER_ONLY 39 #include "qapi/qapi-commands-machine-target.h" 40 #include "exec/address-spaces.h" 41 #include "hw/boards.h" 42 #include "hw/i386/sgx-epc.h" 43 #endif 44 45 #include "disas/capstone.h" 46 #include "cpu-internal.h" 47 48 static void x86_cpu_realizefn(DeviceState *dev, Error **errp); 49 50 /* Helpers for building CPUID[2] descriptors: */ 51 52 struct CPUID2CacheDescriptorInfo { 53 enum CacheType type; 54 int level; 55 int size; 56 int line_size; 57 int associativity; 58 }; 59 60 /* 61 * Known CPUID 2 cache descriptors. 62 * From Intel SDM Volume 2A, CPUID instruction 63 */ 64 struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = { 65 [0x06] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 8 * KiB, 66 .associativity = 4, .line_size = 32, }, 67 [0x08] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 16 * KiB, 68 .associativity = 4, .line_size = 32, }, 69 [0x09] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB, 70 .associativity = 4, .line_size = 64, }, 71 [0x0A] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB, 72 .associativity = 2, .line_size = 32, }, 73 [0x0C] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 74 .associativity = 4, .line_size = 32, }, 75 [0x0D] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 76 .associativity = 4, .line_size = 64, }, 77 [0x0E] = { .level = 1, .type = DATA_CACHE, .size = 24 * KiB, 78 .associativity = 6, .line_size = 64, }, 79 [0x1D] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB, 80 .associativity = 2, .line_size = 64, }, 81 [0x21] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 82 .associativity = 8, .line_size = 64, }, 83 /* lines per sector is not supported cpuid2_cache_descriptor(), 84 * so descriptors 0x22, 0x23 are not included 85 */ 86 [0x24] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 87 .associativity = 16, .line_size = 64, }, 88 /* lines per sector is not supported cpuid2_cache_descriptor(), 89 * so descriptors 0x25, 0x20 are not included 90 */ 91 [0x2C] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB, 92 .associativity = 8, .line_size = 64, }, 93 [0x30] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB, 94 .associativity = 8, .line_size = 64, }, 95 [0x41] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB, 96 .associativity = 4, .line_size = 32, }, 97 [0x42] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 98 .associativity = 4, .line_size = 32, }, 99 [0x43] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 100 .associativity = 4, .line_size = 32, }, 101 [0x44] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 102 .associativity = 4, .line_size = 32, }, 103 [0x45] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 104 .associativity = 4, .line_size = 32, }, 105 [0x46] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 106 .associativity = 4, .line_size = 64, }, 107 [0x47] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 108 .associativity = 8, .line_size = 64, }, 109 [0x48] = { .level = 2, .type = UNIFIED_CACHE, .size = 3 * MiB, 110 .associativity = 12, .line_size = 64, }, 111 /* Descriptor 0x49 depends on CPU family/model, so it is not included */ 112 [0x4A] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB, 113 .associativity = 12, .line_size = 64, }, 114 [0x4B] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 115 .associativity = 16, .line_size = 64, }, 116 [0x4C] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB, 117 .associativity = 12, .line_size = 64, }, 118 [0x4D] = { .level = 3, .type = UNIFIED_CACHE, .size = 16 * MiB, 119 .associativity = 16, .line_size = 64, }, 120 [0x4E] = { .level = 2, .type = UNIFIED_CACHE, .size = 6 * MiB, 121 .associativity = 24, .line_size = 64, }, 122 [0x60] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 123 .associativity = 8, .line_size = 64, }, 124 [0x66] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB, 125 .associativity = 4, .line_size = 64, }, 126 [0x67] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 127 .associativity = 4, .line_size = 64, }, 128 [0x68] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB, 129 .associativity = 4, .line_size = 64, }, 130 [0x78] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 131 .associativity = 4, .line_size = 64, }, 132 /* lines per sector is not supported cpuid2_cache_descriptor(), 133 * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included. 134 */ 135 [0x7D] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 136 .associativity = 8, .line_size = 64, }, 137 [0x7F] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 138 .associativity = 2, .line_size = 64, }, 139 [0x80] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 140 .associativity = 8, .line_size = 64, }, 141 [0x82] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 142 .associativity = 8, .line_size = 32, }, 143 [0x83] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 144 .associativity = 8, .line_size = 32, }, 145 [0x84] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 146 .associativity = 8, .line_size = 32, }, 147 [0x85] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 148 .associativity = 8, .line_size = 32, }, 149 [0x86] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 150 .associativity = 4, .line_size = 64, }, 151 [0x87] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 152 .associativity = 8, .line_size = 64, }, 153 [0xD0] = { .level = 3, .type = UNIFIED_CACHE, .size = 512 * KiB, 154 .associativity = 4, .line_size = 64, }, 155 [0xD1] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB, 156 .associativity = 4, .line_size = 64, }, 157 [0xD2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 158 .associativity = 4, .line_size = 64, }, 159 [0xD6] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB, 160 .associativity = 8, .line_size = 64, }, 161 [0xD7] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 162 .associativity = 8, .line_size = 64, }, 163 [0xD8] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 164 .associativity = 8, .line_size = 64, }, 165 [0xDC] = { .level = 3, .type = UNIFIED_CACHE, .size = 1.5 * MiB, 166 .associativity = 12, .line_size = 64, }, 167 [0xDD] = { .level = 3, .type = UNIFIED_CACHE, .size = 3 * MiB, 168 .associativity = 12, .line_size = 64, }, 169 [0xDE] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB, 170 .associativity = 12, .line_size = 64, }, 171 [0xE2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 172 .associativity = 16, .line_size = 64, }, 173 [0xE3] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 174 .associativity = 16, .line_size = 64, }, 175 [0xE4] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 176 .associativity = 16, .line_size = 64, }, 177 [0xEA] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB, 178 .associativity = 24, .line_size = 64, }, 179 [0xEB] = { .level = 3, .type = UNIFIED_CACHE, .size = 18 * MiB, 180 .associativity = 24, .line_size = 64, }, 181 [0xEC] = { .level = 3, .type = UNIFIED_CACHE, .size = 24 * MiB, 182 .associativity = 24, .line_size = 64, }, 183 }; 184 185 /* 186 * "CPUID leaf 2 does not report cache descriptor information, 187 * use CPUID leaf 4 to query cache parameters" 188 */ 189 #define CACHE_DESCRIPTOR_UNAVAILABLE 0xFF 190 191 /* 192 * Return a CPUID 2 cache descriptor for a given cache. 193 * If no known descriptor is found, return CACHE_DESCRIPTOR_UNAVAILABLE 194 */ 195 static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache) 196 { 197 int i; 198 199 assert(cache->size > 0); 200 assert(cache->level > 0); 201 assert(cache->line_size > 0); 202 assert(cache->associativity > 0); 203 for (i = 0; i < ARRAY_SIZE(cpuid2_cache_descriptors); i++) { 204 struct CPUID2CacheDescriptorInfo *d = &cpuid2_cache_descriptors[i]; 205 if (d->level == cache->level && d->type == cache->type && 206 d->size == cache->size && d->line_size == cache->line_size && 207 d->associativity == cache->associativity) { 208 return i; 209 } 210 } 211 212 return CACHE_DESCRIPTOR_UNAVAILABLE; 213 } 214 215 /* CPUID Leaf 4 constants: */ 216 217 /* EAX: */ 218 #define CACHE_TYPE_D 1 219 #define CACHE_TYPE_I 2 220 #define CACHE_TYPE_UNIFIED 3 221 222 #define CACHE_LEVEL(l) (l << 5) 223 224 #define CACHE_SELF_INIT_LEVEL (1 << 8) 225 226 /* EDX: */ 227 #define CACHE_NO_INVD_SHARING (1 << 0) 228 #define CACHE_INCLUSIVE (1 << 1) 229 #define CACHE_COMPLEX_IDX (1 << 2) 230 231 /* Encode CacheType for CPUID[4].EAX */ 232 #define CACHE_TYPE(t) (((t) == DATA_CACHE) ? CACHE_TYPE_D : \ 233 ((t) == INSTRUCTION_CACHE) ? CACHE_TYPE_I : \ 234 ((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \ 235 0 /* Invalid value */) 236 237 238 /* Encode cache info for CPUID[4] */ 239 static void encode_cache_cpuid4(CPUCacheInfo *cache, 240 int num_apic_ids, int num_cores, 241 uint32_t *eax, uint32_t *ebx, 242 uint32_t *ecx, uint32_t *edx) 243 { 244 assert(cache->size == cache->line_size * cache->associativity * 245 cache->partitions * cache->sets); 246 247 assert(num_apic_ids > 0); 248 *eax = CACHE_TYPE(cache->type) | 249 CACHE_LEVEL(cache->level) | 250 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) | 251 ((num_cores - 1) << 26) | 252 ((num_apic_ids - 1) << 14); 253 254 assert(cache->line_size > 0); 255 assert(cache->partitions > 0); 256 assert(cache->associativity > 0); 257 /* We don't implement fully-associative caches */ 258 assert(cache->associativity < cache->sets); 259 *ebx = (cache->line_size - 1) | 260 ((cache->partitions - 1) << 12) | 261 ((cache->associativity - 1) << 22); 262 263 assert(cache->sets > 0); 264 *ecx = cache->sets - 1; 265 266 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) | 267 (cache->inclusive ? CACHE_INCLUSIVE : 0) | 268 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); 269 } 270 271 /* Encode cache info for CPUID[0x80000005].ECX or CPUID[0x80000005].EDX */ 272 static uint32_t encode_cache_cpuid80000005(CPUCacheInfo *cache) 273 { 274 assert(cache->size % 1024 == 0); 275 assert(cache->lines_per_tag > 0); 276 assert(cache->associativity > 0); 277 assert(cache->line_size > 0); 278 return ((cache->size / 1024) << 24) | (cache->associativity << 16) | 279 (cache->lines_per_tag << 8) | (cache->line_size); 280 } 281 282 #define ASSOC_FULL 0xFF 283 284 /* AMD associativity encoding used on CPUID Leaf 0x80000006: */ 285 #define AMD_ENC_ASSOC(a) (a <= 1 ? a : \ 286 a == 2 ? 0x2 : \ 287 a == 4 ? 0x4 : \ 288 a == 8 ? 0x6 : \ 289 a == 16 ? 0x8 : \ 290 a == 32 ? 0xA : \ 291 a == 48 ? 0xB : \ 292 a == 64 ? 0xC : \ 293 a == 96 ? 0xD : \ 294 a == 128 ? 0xE : \ 295 a == ASSOC_FULL ? 0xF : \ 296 0 /* invalid value */) 297 298 /* 299 * Encode cache info for CPUID[0x80000006].ECX and CPUID[0x80000006].EDX 300 * @l3 can be NULL. 301 */ 302 static void encode_cache_cpuid80000006(CPUCacheInfo *l2, 303 CPUCacheInfo *l3, 304 uint32_t *ecx, uint32_t *edx) 305 { 306 assert(l2->size % 1024 == 0); 307 assert(l2->associativity > 0); 308 assert(l2->lines_per_tag > 0); 309 assert(l2->line_size > 0); 310 *ecx = ((l2->size / 1024) << 16) | 311 (AMD_ENC_ASSOC(l2->associativity) << 12) | 312 (l2->lines_per_tag << 8) | (l2->line_size); 313 314 if (l3) { 315 assert(l3->size % (512 * 1024) == 0); 316 assert(l3->associativity > 0); 317 assert(l3->lines_per_tag > 0); 318 assert(l3->line_size > 0); 319 *edx = ((l3->size / (512 * 1024)) << 18) | 320 (AMD_ENC_ASSOC(l3->associativity) << 12) | 321 (l3->lines_per_tag << 8) | (l3->line_size); 322 } else { 323 *edx = 0; 324 } 325 } 326 327 /* Encode cache info for CPUID[8000001D] */ 328 static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, 329 X86CPUTopoInfo *topo_info, 330 uint32_t *eax, uint32_t *ebx, 331 uint32_t *ecx, uint32_t *edx) 332 { 333 uint32_t l3_threads; 334 assert(cache->size == cache->line_size * cache->associativity * 335 cache->partitions * cache->sets); 336 337 *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) | 338 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0); 339 340 /* L3 is shared among multiple cores */ 341 if (cache->level == 3) { 342 l3_threads = topo_info->cores_per_die * topo_info->threads_per_core; 343 *eax |= (l3_threads - 1) << 14; 344 } else { 345 *eax |= ((topo_info->threads_per_core - 1) << 14); 346 } 347 348 assert(cache->line_size > 0); 349 assert(cache->partitions > 0); 350 assert(cache->associativity > 0); 351 /* We don't implement fully-associative caches */ 352 assert(cache->associativity < cache->sets); 353 *ebx = (cache->line_size - 1) | 354 ((cache->partitions - 1) << 12) | 355 ((cache->associativity - 1) << 22); 356 357 assert(cache->sets > 0); 358 *ecx = cache->sets - 1; 359 360 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) | 361 (cache->inclusive ? CACHE_INCLUSIVE : 0) | 362 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); 363 } 364 365 /* Encode cache info for CPUID[8000001E] */ 366 static void encode_topo_cpuid8000001e(X86CPU *cpu, X86CPUTopoInfo *topo_info, 367 uint32_t *eax, uint32_t *ebx, 368 uint32_t *ecx, uint32_t *edx) 369 { 370 X86CPUTopoIDs topo_ids; 371 372 x86_topo_ids_from_apicid(cpu->apic_id, topo_info, &topo_ids); 373 374 *eax = cpu->apic_id; 375 376 /* 377 * CPUID_Fn8000001E_EBX [Core Identifiers] (CoreId) 378 * Read-only. Reset: 0000_XXXXh. 379 * See Core::X86::Cpuid::ExtApicId. 380 * Core::X86::Cpuid::CoreId_lthree[1:0]_core[3:0]_thread[1:0]; 381 * Bits Description 382 * 31:16 Reserved. 383 * 15:8 ThreadsPerCore: threads per core. Read-only. Reset: XXh. 384 * The number of threads per core is ThreadsPerCore+1. 385 * 7:0 CoreId: core ID. Read-only. Reset: XXh. 386 * 387 * NOTE: CoreId is already part of apic_id. Just use it. We can 388 * use all the 8 bits to represent the core_id here. 389 */ 390 *ebx = ((topo_info->threads_per_core - 1) << 8) | (topo_ids.core_id & 0xFF); 391 392 /* 393 * CPUID_Fn8000001E_ECX [Node Identifiers] (NodeId) 394 * Read-only. Reset: 0000_0XXXh. 395 * Core::X86::Cpuid::NodeId_lthree[1:0]_core[3:0]_thread[1:0]; 396 * Bits Description 397 * 31:11 Reserved. 398 * 10:8 NodesPerProcessor: Node per processor. Read-only. Reset: XXXb. 399 * ValidValues: 400 * Value Description 401 * 000b 1 node per processor. 402 * 001b 2 nodes per processor. 403 * 010b Reserved. 404 * 011b 4 nodes per processor. 405 * 111b-100b Reserved. 406 * 7:0 NodeId: Node ID. Read-only. Reset: XXh. 407 * 408 * NOTE: Hardware reserves 3 bits for number of nodes per processor. 409 * But users can create more nodes than the actual hardware can 410 * support. To genaralize we can use all the upper 8 bits for nodes. 411 * NodeId is combination of node and socket_id which is already decoded 412 * in apic_id. Just use it by shifting. 413 */ 414 *ecx = ((topo_info->dies_per_pkg - 1) << 8) | 415 ((cpu->apic_id >> apicid_die_offset(topo_info)) & 0xFF); 416 417 *edx = 0; 418 } 419 420 /* 421 * Definitions of the hardcoded cache entries we expose: 422 * These are legacy cache values. If there is a need to change any 423 * of these values please use builtin_x86_defs 424 */ 425 426 /* L1 data cache: */ 427 static CPUCacheInfo legacy_l1d_cache = { 428 .type = DATA_CACHE, 429 .level = 1, 430 .size = 32 * KiB, 431 .self_init = 1, 432 .line_size = 64, 433 .associativity = 8, 434 .sets = 64, 435 .partitions = 1, 436 .no_invd_sharing = true, 437 }; 438 439 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ 440 static CPUCacheInfo legacy_l1d_cache_amd = { 441 .type = DATA_CACHE, 442 .level = 1, 443 .size = 64 * KiB, 444 .self_init = 1, 445 .line_size = 64, 446 .associativity = 2, 447 .sets = 512, 448 .partitions = 1, 449 .lines_per_tag = 1, 450 .no_invd_sharing = true, 451 }; 452 453 /* L1 instruction cache: */ 454 static CPUCacheInfo legacy_l1i_cache = { 455 .type = INSTRUCTION_CACHE, 456 .level = 1, 457 .size = 32 * KiB, 458 .self_init = 1, 459 .line_size = 64, 460 .associativity = 8, 461 .sets = 64, 462 .partitions = 1, 463 .no_invd_sharing = true, 464 }; 465 466 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ 467 static CPUCacheInfo legacy_l1i_cache_amd = { 468 .type = INSTRUCTION_CACHE, 469 .level = 1, 470 .size = 64 * KiB, 471 .self_init = 1, 472 .line_size = 64, 473 .associativity = 2, 474 .sets = 512, 475 .partitions = 1, 476 .lines_per_tag = 1, 477 .no_invd_sharing = true, 478 }; 479 480 /* Level 2 unified cache: */ 481 static CPUCacheInfo legacy_l2_cache = { 482 .type = UNIFIED_CACHE, 483 .level = 2, 484 .size = 4 * MiB, 485 .self_init = 1, 486 .line_size = 64, 487 .associativity = 16, 488 .sets = 4096, 489 .partitions = 1, 490 .no_invd_sharing = true, 491 }; 492 493 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */ 494 static CPUCacheInfo legacy_l2_cache_cpuid2 = { 495 .type = UNIFIED_CACHE, 496 .level = 2, 497 .size = 2 * MiB, 498 .line_size = 64, 499 .associativity = 8, 500 }; 501 502 503 /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */ 504 static CPUCacheInfo legacy_l2_cache_amd = { 505 .type = UNIFIED_CACHE, 506 .level = 2, 507 .size = 512 * KiB, 508 .line_size = 64, 509 .lines_per_tag = 1, 510 .associativity = 16, 511 .sets = 512, 512 .partitions = 1, 513 }; 514 515 /* Level 3 unified cache: */ 516 static CPUCacheInfo legacy_l3_cache = { 517 .type = UNIFIED_CACHE, 518 .level = 3, 519 .size = 16 * MiB, 520 .line_size = 64, 521 .associativity = 16, 522 .sets = 16384, 523 .partitions = 1, 524 .lines_per_tag = 1, 525 .self_init = true, 526 .inclusive = true, 527 .complex_indexing = true, 528 }; 529 530 /* TLB definitions: */ 531 532 #define L1_DTLB_2M_ASSOC 1 533 #define L1_DTLB_2M_ENTRIES 255 534 #define L1_DTLB_4K_ASSOC 1 535 #define L1_DTLB_4K_ENTRIES 255 536 537 #define L1_ITLB_2M_ASSOC 1 538 #define L1_ITLB_2M_ENTRIES 255 539 #define L1_ITLB_4K_ASSOC 1 540 #define L1_ITLB_4K_ENTRIES 255 541 542 #define L2_DTLB_2M_ASSOC 0 /* disabled */ 543 #define L2_DTLB_2M_ENTRIES 0 /* disabled */ 544 #define L2_DTLB_4K_ASSOC 4 545 #define L2_DTLB_4K_ENTRIES 512 546 547 #define L2_ITLB_2M_ASSOC 0 /* disabled */ 548 #define L2_ITLB_2M_ENTRIES 0 /* disabled */ 549 #define L2_ITLB_4K_ASSOC 4 550 #define L2_ITLB_4K_ENTRIES 512 551 552 /* CPUID Leaf 0x14 constants: */ 553 #define INTEL_PT_MAX_SUBLEAF 0x1 554 /* 555 * bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MATCH 556 * MSR can be accessed; 557 * bit[01]: Support Configurable PSB and Cycle-Accurate Mode; 558 * bit[02]: Support IP Filtering, TraceStop filtering, and preservation 559 * of Intel PT MSRs across warm reset; 560 * bit[03]: Support MTC timing packet and suppression of COFI-based packets; 561 */ 562 #define INTEL_PT_MINIMAL_EBX 0xf 563 /* 564 * bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 and 565 * IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be 566 * accessed; 567 * bit[01]: ToPA tables can hold any number of output entries, up to the 568 * maximum allowed by the MaskOrTableOffset field of 569 * IA32_RTIT_OUTPUT_MASK_PTRS; 570 * bit[02]: Support Single-Range Output scheme; 571 */ 572 #define INTEL_PT_MINIMAL_ECX 0x7 573 /* generated packets which contain IP payloads have LIP values */ 574 #define INTEL_PT_IP_LIP (1 << 31) 575 #define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */ 576 #define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3 577 #define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */ 578 #define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */ 579 #define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */ 580 581 /* CPUID Leaf 0x1D constants: */ 582 #define INTEL_AMX_TILE_MAX_SUBLEAF 0x1 583 #define INTEL_AMX_TOTAL_TILE_BYTES 0x2000 584 #define INTEL_AMX_BYTES_PER_TILE 0x400 585 #define INTEL_AMX_BYTES_PER_ROW 0x40 586 #define INTEL_AMX_TILE_MAX_NAMES 0x8 587 #define INTEL_AMX_TILE_MAX_ROWS 0x10 588 589 /* CPUID Leaf 0x1E constants: */ 590 #define INTEL_AMX_TMUL_MAX_K 0x10 591 #define INTEL_AMX_TMUL_MAX_N 0x40 592 593 void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1, 594 uint32_t vendor2, uint32_t vendor3) 595 { 596 int i; 597 for (i = 0; i < 4; i++) { 598 dst[i] = vendor1 >> (8 * i); 599 dst[i + 4] = vendor2 >> (8 * i); 600 dst[i + 8] = vendor3 >> (8 * i); 601 } 602 dst[CPUID_VENDOR_SZ] = '\0'; 603 } 604 605 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE) 606 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \ 607 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC) 608 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \ 609 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ 610 CPUID_PSE36 | CPUID_FXSR) 611 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE) 612 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \ 613 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \ 614 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \ 615 CPUID_PAE | CPUID_SEP | CPUID_APIC) 616 617 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \ 618 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \ 619 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ 620 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \ 621 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE) 622 /* partly implemented: 623 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */ 624 /* missing: 625 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */ 626 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \ 627 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \ 628 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \ 629 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \ 630 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR | \ 631 CPUID_EXT_RDRAND | CPUID_EXT_AVX | CPUID_EXT_F16C | \ 632 CPUID_EXT_FMA) 633 /* missing: 634 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX, 635 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, 636 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA, 637 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER */ 638 639 #ifdef TARGET_X86_64 640 #define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM) 641 #else 642 #define TCG_EXT2_X86_64_FEATURES 0 643 #endif 644 645 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \ 646 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \ 647 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \ 648 TCG_EXT2_X86_64_FEATURES) 649 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \ 650 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A) 651 #define TCG_EXT4_FEATURES 0 652 #define TCG_SVM_FEATURES (CPUID_SVM_NPT | CPUID_SVM_VGIF | \ 653 CPUID_SVM_SVME_ADDR_CHK) 654 #define TCG_KVM_FEATURES 0 655 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \ 656 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \ 657 CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \ 658 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \ 659 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_AVX2) 660 /* missing: 661 CPUID_7_0_EBX_HLE 662 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM, 663 CPUID_7_0_EBX_RDSEED */ 664 #define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | \ 665 /* CPUID_7_0_ECX_OSPKE is dynamic */ \ 666 CPUID_7_0_ECX_LA57 | CPUID_7_0_ECX_PKS | CPUID_7_0_ECX_VAES) 667 #define TCG_7_0_EDX_FEATURES CPUID_7_0_EDX_FSRM 668 #define TCG_7_1_EAX_FEATURES (CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | \ 669 CPUID_7_1_EAX_FSRC) 670 #define TCG_7_1_EDX_FEATURES 0 671 #define TCG_APM_FEATURES 0 672 #define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT 673 #define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1) 674 /* missing: 675 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */ 676 #define TCG_14_0_ECX_FEATURES 0 677 #define TCG_SGX_12_0_EAX_FEATURES 0 678 #define TCG_SGX_12_0_EBX_FEATURES 0 679 #define TCG_SGX_12_1_EAX_FEATURES 0 680 681 FeatureWordInfo feature_word_info[FEATURE_WORDS] = { 682 [FEAT_1_EDX] = { 683 .type = CPUID_FEATURE_WORD, 684 .feat_names = { 685 "fpu", "vme", "de", "pse", 686 "tsc", "msr", "pae", "mce", 687 "cx8", "apic", NULL, "sep", 688 "mtrr", "pge", "mca", "cmov", 689 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */, 690 NULL, "ds" /* Intel dts */, "acpi", "mmx", 691 "fxsr", "sse", "sse2", "ss", 692 "ht" /* Intel htt */, "tm", "ia64", "pbe", 693 }, 694 .cpuid = {.eax = 1, .reg = R_EDX, }, 695 .tcg_features = TCG_FEATURES, 696 }, 697 [FEAT_1_ECX] = { 698 .type = CPUID_FEATURE_WORD, 699 .feat_names = { 700 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor", 701 "ds-cpl", "vmx", "smx", "est", 702 "tm2", "ssse3", "cid", NULL, 703 "fma", "cx16", "xtpr", "pdcm", 704 NULL, "pcid", "dca", "sse4.1", 705 "sse4.2", "x2apic", "movbe", "popcnt", 706 "tsc-deadline", "aes", "xsave", NULL /* osxsave */, 707 "avx", "f16c", "rdrand", "hypervisor", 708 }, 709 .cpuid = { .eax = 1, .reg = R_ECX, }, 710 .tcg_features = TCG_EXT_FEATURES, 711 }, 712 /* Feature names that are already defined on feature_name[] but 713 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their 714 * names on feat_names below. They are copied automatically 715 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD. 716 */ 717 [FEAT_8000_0001_EDX] = { 718 .type = CPUID_FEATURE_WORD, 719 .feat_names = { 720 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */, 721 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */, 722 NULL /* cx8 */, NULL /* apic */, NULL, "syscall", 723 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */, 724 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */, 725 "nx", NULL, "mmxext", NULL /* mmx */, 726 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp", 727 NULL, "lm", "3dnowext", "3dnow", 728 }, 729 .cpuid = { .eax = 0x80000001, .reg = R_EDX, }, 730 .tcg_features = TCG_EXT2_FEATURES, 731 }, 732 [FEAT_8000_0001_ECX] = { 733 .type = CPUID_FEATURE_WORD, 734 .feat_names = { 735 "lahf-lm", "cmp-legacy", "svm", "extapic", 736 "cr8legacy", "abm", "sse4a", "misalignsse", 737 "3dnowprefetch", "osvw", "ibs", "xop", 738 "skinit", "wdt", NULL, "lwp", 739 "fma4", "tce", NULL, "nodeid-msr", 740 NULL, "tbm", "topoext", "perfctr-core", 741 "perfctr-nb", NULL, NULL, NULL, 742 NULL, NULL, NULL, NULL, 743 }, 744 .cpuid = { .eax = 0x80000001, .reg = R_ECX, }, 745 .tcg_features = TCG_EXT3_FEATURES, 746 /* 747 * TOPOEXT is always allowed but can't be enabled blindly by 748 * "-cpu host", as it requires consistent cache topology info 749 * to be provided so it doesn't confuse guests. 750 */ 751 .no_autoenable_flags = CPUID_EXT3_TOPOEXT, 752 }, 753 [FEAT_C000_0001_EDX] = { 754 .type = CPUID_FEATURE_WORD, 755 .feat_names = { 756 NULL, NULL, "xstore", "xstore-en", 757 NULL, NULL, "xcrypt", "xcrypt-en", 758 "ace2", "ace2-en", "phe", "phe-en", 759 "pmm", "pmm-en", NULL, NULL, 760 NULL, NULL, NULL, NULL, 761 NULL, NULL, NULL, NULL, 762 NULL, NULL, NULL, NULL, 763 NULL, NULL, NULL, NULL, 764 }, 765 .cpuid = { .eax = 0xC0000001, .reg = R_EDX, }, 766 .tcg_features = TCG_EXT4_FEATURES, 767 }, 768 [FEAT_KVM] = { 769 .type = CPUID_FEATURE_WORD, 770 .feat_names = { 771 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock", 772 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt", 773 NULL, "kvm-pv-tlb-flush", NULL, "kvm-pv-ipi", 774 "kvm-poll-control", "kvm-pv-sched-yield", "kvm-asyncpf-int", "kvm-msi-ext-dest-id", 775 NULL, NULL, NULL, NULL, 776 NULL, NULL, NULL, NULL, 777 "kvmclock-stable-bit", NULL, NULL, NULL, 778 NULL, NULL, NULL, NULL, 779 }, 780 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EAX, }, 781 .tcg_features = TCG_KVM_FEATURES, 782 }, 783 [FEAT_KVM_HINTS] = { 784 .type = CPUID_FEATURE_WORD, 785 .feat_names = { 786 "kvm-hint-dedicated", NULL, NULL, NULL, 787 NULL, NULL, NULL, NULL, 788 NULL, NULL, NULL, NULL, 789 NULL, NULL, NULL, NULL, 790 NULL, NULL, NULL, NULL, 791 NULL, NULL, NULL, NULL, 792 NULL, NULL, NULL, NULL, 793 NULL, NULL, NULL, NULL, 794 }, 795 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EDX, }, 796 .tcg_features = TCG_KVM_FEATURES, 797 /* 798 * KVM hints aren't auto-enabled by -cpu host, they need to be 799 * explicitly enabled in the command-line. 800 */ 801 .no_autoenable_flags = ~0U, 802 }, 803 [FEAT_SVM] = { 804 .type = CPUID_FEATURE_WORD, 805 .feat_names = { 806 "npt", "lbrv", "svm-lock", "nrip-save", 807 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists", 808 NULL, NULL, "pause-filter", NULL, 809 "pfthreshold", "avic", NULL, "v-vmsave-vmload", 810 "vgif", NULL, NULL, NULL, 811 NULL, NULL, NULL, NULL, 812 NULL, NULL, NULL, NULL, 813 "svme-addr-chk", NULL, NULL, NULL, 814 }, 815 .cpuid = { .eax = 0x8000000A, .reg = R_EDX, }, 816 .tcg_features = TCG_SVM_FEATURES, 817 }, 818 [FEAT_7_0_EBX] = { 819 .type = CPUID_FEATURE_WORD, 820 .feat_names = { 821 "fsgsbase", "tsc-adjust", "sgx", "bmi1", 822 "hle", "avx2", NULL, "smep", 823 "bmi2", "erms", "invpcid", "rtm", 824 NULL, NULL, "mpx", NULL, 825 "avx512f", "avx512dq", "rdseed", "adx", 826 "smap", "avx512ifma", "pcommit", "clflushopt", 827 "clwb", "intel-pt", "avx512pf", "avx512er", 828 "avx512cd", "sha-ni", "avx512bw", "avx512vl", 829 }, 830 .cpuid = { 831 .eax = 7, 832 .needs_ecx = true, .ecx = 0, 833 .reg = R_EBX, 834 }, 835 .tcg_features = TCG_7_0_EBX_FEATURES, 836 }, 837 [FEAT_7_0_ECX] = { 838 .type = CPUID_FEATURE_WORD, 839 .feat_names = { 840 NULL, "avx512vbmi", "umip", "pku", 841 NULL /* ospke */, "waitpkg", "avx512vbmi2", NULL, 842 "gfni", "vaes", "vpclmulqdq", "avx512vnni", 843 "avx512bitalg", NULL, "avx512-vpopcntdq", NULL, 844 "la57", NULL, NULL, NULL, 845 NULL, NULL, "rdpid", NULL, 846 "bus-lock-detect", "cldemote", NULL, "movdiri", 847 "movdir64b", NULL, "sgxlc", "pks", 848 }, 849 .cpuid = { 850 .eax = 7, 851 .needs_ecx = true, .ecx = 0, 852 .reg = R_ECX, 853 }, 854 .tcg_features = TCG_7_0_ECX_FEATURES, 855 }, 856 [FEAT_7_0_EDX] = { 857 .type = CPUID_FEATURE_WORD, 858 .feat_names = { 859 NULL, NULL, "avx512-4vnniw", "avx512-4fmaps", 860 "fsrm", NULL, NULL, NULL, 861 "avx512-vp2intersect", NULL, "md-clear", NULL, 862 NULL, NULL, "serialize", NULL, 863 "tsx-ldtrk", NULL, NULL /* pconfig */, "arch-lbr", 864 NULL, NULL, "amx-bf16", "avx512-fp16", 865 "amx-tile", "amx-int8", "spec-ctrl", "stibp", 866 NULL, "arch-capabilities", "core-capability", "ssbd", 867 }, 868 .cpuid = { 869 .eax = 7, 870 .needs_ecx = true, .ecx = 0, 871 .reg = R_EDX, 872 }, 873 .tcg_features = TCG_7_0_EDX_FEATURES, 874 }, 875 [FEAT_7_1_EAX] = { 876 .type = CPUID_FEATURE_WORD, 877 .feat_names = { 878 NULL, NULL, NULL, NULL, 879 "avx-vnni", "avx512-bf16", NULL, "cmpccxadd", 880 NULL, NULL, "fzrm", "fsrs", 881 "fsrc", NULL, NULL, NULL, 882 NULL, NULL, NULL, NULL, 883 NULL, "amx-fp16", NULL, "avx-ifma", 884 NULL, NULL, NULL, NULL, 885 NULL, NULL, NULL, NULL, 886 }, 887 .cpuid = { 888 .eax = 7, 889 .needs_ecx = true, .ecx = 1, 890 .reg = R_EAX, 891 }, 892 .tcg_features = TCG_7_1_EAX_FEATURES, 893 }, 894 [FEAT_7_1_EDX] = { 895 .type = CPUID_FEATURE_WORD, 896 .feat_names = { 897 NULL, NULL, NULL, NULL, 898 "avx-vnni-int8", "avx-ne-convert", NULL, NULL, 899 NULL, NULL, NULL, NULL, 900 NULL, NULL, "prefetchiti", NULL, 901 NULL, NULL, NULL, NULL, 902 NULL, NULL, NULL, NULL, 903 NULL, NULL, NULL, NULL, 904 NULL, NULL, NULL, NULL, 905 }, 906 .cpuid = { 907 .eax = 7, 908 .needs_ecx = true, .ecx = 1, 909 .reg = R_EDX, 910 }, 911 .tcg_features = TCG_7_1_EDX_FEATURES, 912 }, 913 [FEAT_8000_0007_EDX] = { 914 .type = CPUID_FEATURE_WORD, 915 .feat_names = { 916 NULL, NULL, NULL, NULL, 917 NULL, NULL, NULL, NULL, 918 "invtsc", NULL, NULL, NULL, 919 NULL, NULL, NULL, NULL, 920 NULL, NULL, NULL, NULL, 921 NULL, NULL, NULL, NULL, 922 NULL, NULL, NULL, NULL, 923 NULL, NULL, NULL, NULL, 924 }, 925 .cpuid = { .eax = 0x80000007, .reg = R_EDX, }, 926 .tcg_features = TCG_APM_FEATURES, 927 .unmigratable_flags = CPUID_APM_INVTSC, 928 }, 929 [FEAT_8000_0008_EBX] = { 930 .type = CPUID_FEATURE_WORD, 931 .feat_names = { 932 "clzero", NULL, "xsaveerptr", NULL, 933 NULL, NULL, NULL, NULL, 934 NULL, "wbnoinvd", NULL, NULL, 935 "ibpb", NULL, "ibrs", "amd-stibp", 936 NULL, NULL, NULL, NULL, 937 NULL, NULL, NULL, NULL, 938 "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL, 939 NULL, NULL, NULL, NULL, 940 }, 941 .cpuid = { .eax = 0x80000008, .reg = R_EBX, }, 942 .tcg_features = 0, 943 .unmigratable_flags = 0, 944 }, 945 [FEAT_XSAVE] = { 946 .type = CPUID_FEATURE_WORD, 947 .feat_names = { 948 "xsaveopt", "xsavec", "xgetbv1", "xsaves", 949 "xfd", NULL, NULL, NULL, 950 NULL, NULL, NULL, NULL, 951 NULL, NULL, NULL, NULL, 952 NULL, NULL, NULL, NULL, 953 NULL, NULL, NULL, NULL, 954 NULL, NULL, NULL, NULL, 955 NULL, NULL, NULL, NULL, 956 }, 957 .cpuid = { 958 .eax = 0xd, 959 .needs_ecx = true, .ecx = 1, 960 .reg = R_EAX, 961 }, 962 .tcg_features = TCG_XSAVE_FEATURES, 963 }, 964 [FEAT_XSAVE_XSS_LO] = { 965 .type = CPUID_FEATURE_WORD, 966 .feat_names = { 967 NULL, NULL, NULL, NULL, 968 NULL, NULL, NULL, NULL, 969 NULL, NULL, NULL, NULL, 970 NULL, NULL, NULL, NULL, 971 NULL, NULL, NULL, NULL, 972 NULL, NULL, NULL, NULL, 973 NULL, NULL, NULL, NULL, 974 NULL, NULL, NULL, NULL, 975 }, 976 .cpuid = { 977 .eax = 0xD, 978 .needs_ecx = true, 979 .ecx = 1, 980 .reg = R_ECX, 981 }, 982 }, 983 [FEAT_XSAVE_XSS_HI] = { 984 .type = CPUID_FEATURE_WORD, 985 .cpuid = { 986 .eax = 0xD, 987 .needs_ecx = true, 988 .ecx = 1, 989 .reg = R_EDX 990 }, 991 }, 992 [FEAT_6_EAX] = { 993 .type = CPUID_FEATURE_WORD, 994 .feat_names = { 995 NULL, NULL, "arat", NULL, 996 NULL, NULL, NULL, NULL, 997 NULL, NULL, NULL, NULL, 998 NULL, NULL, NULL, NULL, 999 NULL, NULL, NULL, NULL, 1000 NULL, NULL, NULL, NULL, 1001 NULL, NULL, NULL, NULL, 1002 NULL, NULL, NULL, NULL, 1003 }, 1004 .cpuid = { .eax = 6, .reg = R_EAX, }, 1005 .tcg_features = TCG_6_EAX_FEATURES, 1006 }, 1007 [FEAT_XSAVE_XCR0_LO] = { 1008 .type = CPUID_FEATURE_WORD, 1009 .cpuid = { 1010 .eax = 0xD, 1011 .needs_ecx = true, .ecx = 0, 1012 .reg = R_EAX, 1013 }, 1014 .tcg_features = ~0U, 1015 .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK | 1016 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK | 1017 XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK | 1018 XSTATE_PKRU_MASK, 1019 }, 1020 [FEAT_XSAVE_XCR0_HI] = { 1021 .type = CPUID_FEATURE_WORD, 1022 .cpuid = { 1023 .eax = 0xD, 1024 .needs_ecx = true, .ecx = 0, 1025 .reg = R_EDX, 1026 }, 1027 .tcg_features = ~0U, 1028 }, 1029 /*Below are MSR exposed features*/ 1030 [FEAT_ARCH_CAPABILITIES] = { 1031 .type = MSR_FEATURE_WORD, 1032 .feat_names = { 1033 "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry", 1034 "ssb-no", "mds-no", "pschange-mc-no", "tsx-ctrl", 1035 "taa-no", NULL, NULL, NULL, 1036 NULL, NULL, NULL, NULL, 1037 NULL, NULL, NULL, NULL, 1038 NULL, NULL, NULL, NULL, 1039 NULL, NULL, NULL, NULL, 1040 NULL, NULL, NULL, NULL, 1041 }, 1042 .msr = { 1043 .index = MSR_IA32_ARCH_CAPABILITIES, 1044 }, 1045 }, 1046 [FEAT_CORE_CAPABILITY] = { 1047 .type = MSR_FEATURE_WORD, 1048 .feat_names = { 1049 NULL, NULL, NULL, NULL, 1050 NULL, "split-lock-detect", NULL, NULL, 1051 NULL, NULL, NULL, NULL, 1052 NULL, NULL, NULL, NULL, 1053 NULL, NULL, NULL, NULL, 1054 NULL, NULL, NULL, NULL, 1055 NULL, NULL, NULL, NULL, 1056 NULL, NULL, NULL, NULL, 1057 }, 1058 .msr = { 1059 .index = MSR_IA32_CORE_CAPABILITY, 1060 }, 1061 }, 1062 [FEAT_PERF_CAPABILITIES] = { 1063 .type = MSR_FEATURE_WORD, 1064 .feat_names = { 1065 NULL, NULL, NULL, NULL, 1066 NULL, NULL, NULL, NULL, 1067 NULL, NULL, NULL, NULL, 1068 NULL, "full-width-write", NULL, NULL, 1069 NULL, NULL, NULL, NULL, 1070 NULL, NULL, NULL, NULL, 1071 NULL, NULL, NULL, NULL, 1072 NULL, NULL, NULL, NULL, 1073 }, 1074 .msr = { 1075 .index = MSR_IA32_PERF_CAPABILITIES, 1076 }, 1077 }, 1078 1079 [FEAT_VMX_PROCBASED_CTLS] = { 1080 .type = MSR_FEATURE_WORD, 1081 .feat_names = { 1082 NULL, NULL, "vmx-vintr-pending", "vmx-tsc-offset", 1083 NULL, NULL, NULL, "vmx-hlt-exit", 1084 NULL, "vmx-invlpg-exit", "vmx-mwait-exit", "vmx-rdpmc-exit", 1085 "vmx-rdtsc-exit", NULL, NULL, "vmx-cr3-load-noexit", 1086 "vmx-cr3-store-noexit", NULL, NULL, "vmx-cr8-load-exit", 1087 "vmx-cr8-store-exit", "vmx-flexpriority", "vmx-vnmi-pending", "vmx-movdr-exit", 1088 "vmx-io-exit", "vmx-io-bitmap", NULL, "vmx-mtf", 1089 "vmx-msr-bitmap", "vmx-monitor-exit", "vmx-pause-exit", "vmx-secondary-ctls", 1090 }, 1091 .msr = { 1092 .index = MSR_IA32_VMX_TRUE_PROCBASED_CTLS, 1093 } 1094 }, 1095 1096 [FEAT_VMX_SECONDARY_CTLS] = { 1097 .type = MSR_FEATURE_WORD, 1098 .feat_names = { 1099 "vmx-apicv-xapic", "vmx-ept", "vmx-desc-exit", "vmx-rdtscp-exit", 1100 "vmx-apicv-x2apic", "vmx-vpid", "vmx-wbinvd-exit", "vmx-unrestricted-guest", 1101 "vmx-apicv-register", "vmx-apicv-vid", "vmx-ple", "vmx-rdrand-exit", 1102 "vmx-invpcid-exit", "vmx-vmfunc", "vmx-shadow-vmcs", "vmx-encls-exit", 1103 "vmx-rdseed-exit", "vmx-pml", NULL, NULL, 1104 "vmx-xsaves", NULL, NULL, NULL, 1105 NULL, "vmx-tsc-scaling", NULL, NULL, 1106 NULL, NULL, NULL, NULL, 1107 }, 1108 .msr = { 1109 .index = MSR_IA32_VMX_PROCBASED_CTLS2, 1110 } 1111 }, 1112 1113 [FEAT_VMX_PINBASED_CTLS] = { 1114 .type = MSR_FEATURE_WORD, 1115 .feat_names = { 1116 "vmx-intr-exit", NULL, NULL, "vmx-nmi-exit", 1117 NULL, "vmx-vnmi", "vmx-preemption-timer", "vmx-posted-intr", 1118 NULL, NULL, NULL, NULL, 1119 NULL, NULL, NULL, NULL, 1120 NULL, NULL, NULL, NULL, 1121 NULL, NULL, NULL, NULL, 1122 NULL, NULL, NULL, NULL, 1123 NULL, NULL, NULL, NULL, 1124 }, 1125 .msr = { 1126 .index = MSR_IA32_VMX_TRUE_PINBASED_CTLS, 1127 } 1128 }, 1129 1130 [FEAT_VMX_EXIT_CTLS] = { 1131 .type = MSR_FEATURE_WORD, 1132 /* 1133 * VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE is copied from 1134 * the LM CPUID bit. 1135 */ 1136 .feat_names = { 1137 NULL, NULL, "vmx-exit-nosave-debugctl", NULL, 1138 NULL, NULL, NULL, NULL, 1139 NULL, NULL /* vmx-exit-host-addr-space-size */, NULL, NULL, 1140 "vmx-exit-load-perf-global-ctrl", NULL, NULL, "vmx-exit-ack-intr", 1141 NULL, NULL, "vmx-exit-save-pat", "vmx-exit-load-pat", 1142 "vmx-exit-save-efer", "vmx-exit-load-efer", 1143 "vmx-exit-save-preemption-timer", "vmx-exit-clear-bndcfgs", 1144 NULL, "vmx-exit-clear-rtit-ctl", NULL, NULL, 1145 NULL, "vmx-exit-load-pkrs", NULL, NULL, 1146 }, 1147 .msr = { 1148 .index = MSR_IA32_VMX_TRUE_EXIT_CTLS, 1149 } 1150 }, 1151 1152 [FEAT_VMX_ENTRY_CTLS] = { 1153 .type = MSR_FEATURE_WORD, 1154 .feat_names = { 1155 NULL, NULL, "vmx-entry-noload-debugctl", NULL, 1156 NULL, NULL, NULL, NULL, 1157 NULL, "vmx-entry-ia32e-mode", NULL, NULL, 1158 NULL, "vmx-entry-load-perf-global-ctrl", "vmx-entry-load-pat", "vmx-entry-load-efer", 1159 "vmx-entry-load-bndcfgs", NULL, "vmx-entry-load-rtit-ctl", NULL, 1160 NULL, NULL, "vmx-entry-load-pkrs", NULL, 1161 NULL, NULL, NULL, NULL, 1162 NULL, NULL, NULL, NULL, 1163 }, 1164 .msr = { 1165 .index = MSR_IA32_VMX_TRUE_ENTRY_CTLS, 1166 } 1167 }, 1168 1169 [FEAT_VMX_MISC] = { 1170 .type = MSR_FEATURE_WORD, 1171 .feat_names = { 1172 NULL, NULL, NULL, NULL, 1173 NULL, "vmx-store-lma", "vmx-activity-hlt", "vmx-activity-shutdown", 1174 "vmx-activity-wait-sipi", NULL, NULL, NULL, 1175 NULL, NULL, NULL, NULL, 1176 NULL, NULL, NULL, NULL, 1177 NULL, NULL, NULL, NULL, 1178 NULL, NULL, NULL, NULL, 1179 NULL, "vmx-vmwrite-vmexit-fields", "vmx-zero-len-inject", NULL, 1180 }, 1181 .msr = { 1182 .index = MSR_IA32_VMX_MISC, 1183 } 1184 }, 1185 1186 [FEAT_VMX_EPT_VPID_CAPS] = { 1187 .type = MSR_FEATURE_WORD, 1188 .feat_names = { 1189 "vmx-ept-execonly", NULL, NULL, NULL, 1190 NULL, NULL, "vmx-page-walk-4", "vmx-page-walk-5", 1191 NULL, NULL, NULL, NULL, 1192 NULL, NULL, NULL, NULL, 1193 "vmx-ept-2mb", "vmx-ept-1gb", NULL, NULL, 1194 "vmx-invept", "vmx-eptad", "vmx-ept-advanced-exitinfo", NULL, 1195 NULL, "vmx-invept-single-context", "vmx-invept-all-context", NULL, 1196 NULL, NULL, NULL, NULL, 1197 "vmx-invvpid", NULL, NULL, NULL, 1198 NULL, NULL, NULL, NULL, 1199 "vmx-invvpid-single-addr", "vmx-invept-single-context", 1200 "vmx-invvpid-all-context", "vmx-invept-single-context-noglobals", 1201 NULL, NULL, NULL, NULL, 1202 NULL, NULL, NULL, NULL, 1203 NULL, NULL, NULL, NULL, 1204 NULL, NULL, NULL, NULL, 1205 NULL, NULL, NULL, NULL, 1206 }, 1207 .msr = { 1208 .index = MSR_IA32_VMX_EPT_VPID_CAP, 1209 } 1210 }, 1211 1212 [FEAT_VMX_BASIC] = { 1213 .type = MSR_FEATURE_WORD, 1214 .feat_names = { 1215 [54] = "vmx-ins-outs", 1216 [55] = "vmx-true-ctls", 1217 }, 1218 .msr = { 1219 .index = MSR_IA32_VMX_BASIC, 1220 }, 1221 /* Just to be safe - we don't support setting the MSEG version field. */ 1222 .no_autoenable_flags = MSR_VMX_BASIC_DUAL_MONITOR, 1223 }, 1224 1225 [FEAT_VMX_VMFUNC] = { 1226 .type = MSR_FEATURE_WORD, 1227 .feat_names = { 1228 [0] = "vmx-eptp-switching", 1229 }, 1230 .msr = { 1231 .index = MSR_IA32_VMX_VMFUNC, 1232 } 1233 }, 1234 1235 [FEAT_14_0_ECX] = { 1236 .type = CPUID_FEATURE_WORD, 1237 .feat_names = { 1238 NULL, NULL, NULL, NULL, 1239 NULL, NULL, NULL, NULL, 1240 NULL, NULL, NULL, NULL, 1241 NULL, NULL, NULL, NULL, 1242 NULL, NULL, NULL, NULL, 1243 NULL, NULL, NULL, NULL, 1244 NULL, NULL, NULL, NULL, 1245 NULL, NULL, NULL, "intel-pt-lip", 1246 }, 1247 .cpuid = { 1248 .eax = 0x14, 1249 .needs_ecx = true, .ecx = 0, 1250 .reg = R_ECX, 1251 }, 1252 .tcg_features = TCG_14_0_ECX_FEATURES, 1253 }, 1254 1255 [FEAT_SGX_12_0_EAX] = { 1256 .type = CPUID_FEATURE_WORD, 1257 .feat_names = { 1258 "sgx1", "sgx2", NULL, NULL, 1259 NULL, NULL, NULL, NULL, 1260 NULL, NULL, NULL, "sgx-edeccssa", 1261 NULL, NULL, NULL, NULL, 1262 NULL, NULL, NULL, NULL, 1263 NULL, NULL, NULL, NULL, 1264 NULL, NULL, NULL, NULL, 1265 NULL, NULL, NULL, NULL, 1266 }, 1267 .cpuid = { 1268 .eax = 0x12, 1269 .needs_ecx = true, .ecx = 0, 1270 .reg = R_EAX, 1271 }, 1272 .tcg_features = TCG_SGX_12_0_EAX_FEATURES, 1273 }, 1274 1275 [FEAT_SGX_12_0_EBX] = { 1276 .type = CPUID_FEATURE_WORD, 1277 .feat_names = { 1278 "sgx-exinfo" , NULL, NULL, NULL, 1279 NULL, NULL, NULL, NULL, 1280 NULL, NULL, NULL, NULL, 1281 NULL, NULL, NULL, NULL, 1282 NULL, NULL, NULL, NULL, 1283 NULL, NULL, NULL, NULL, 1284 NULL, NULL, NULL, NULL, 1285 NULL, NULL, NULL, NULL, 1286 }, 1287 .cpuid = { 1288 .eax = 0x12, 1289 .needs_ecx = true, .ecx = 0, 1290 .reg = R_EBX, 1291 }, 1292 .tcg_features = TCG_SGX_12_0_EBX_FEATURES, 1293 }, 1294 1295 [FEAT_SGX_12_1_EAX] = { 1296 .type = CPUID_FEATURE_WORD, 1297 .feat_names = { 1298 NULL, "sgx-debug", "sgx-mode64", NULL, 1299 "sgx-provisionkey", "sgx-tokenkey", NULL, "sgx-kss", 1300 NULL, NULL, "sgx-aex-notify", NULL, 1301 NULL, NULL, NULL, NULL, 1302 NULL, NULL, NULL, NULL, 1303 NULL, NULL, NULL, NULL, 1304 NULL, NULL, NULL, NULL, 1305 NULL, NULL, NULL, NULL, 1306 }, 1307 .cpuid = { 1308 .eax = 0x12, 1309 .needs_ecx = true, .ecx = 1, 1310 .reg = R_EAX, 1311 }, 1312 .tcg_features = TCG_SGX_12_1_EAX_FEATURES, 1313 }, 1314 }; 1315 1316 typedef struct FeatureMask { 1317 FeatureWord index; 1318 uint64_t mask; 1319 } FeatureMask; 1320 1321 typedef struct FeatureDep { 1322 FeatureMask from, to; 1323 } FeatureDep; 1324 1325 static FeatureDep feature_dependencies[] = { 1326 { 1327 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_ARCH_CAPABILITIES }, 1328 .to = { FEAT_ARCH_CAPABILITIES, ~0ull }, 1329 }, 1330 { 1331 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_CORE_CAPABILITY }, 1332 .to = { FEAT_CORE_CAPABILITY, ~0ull }, 1333 }, 1334 { 1335 .from = { FEAT_1_ECX, CPUID_EXT_PDCM }, 1336 .to = { FEAT_PERF_CAPABILITIES, ~0ull }, 1337 }, 1338 { 1339 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1340 .to = { FEAT_VMX_PROCBASED_CTLS, ~0ull }, 1341 }, 1342 { 1343 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1344 .to = { FEAT_VMX_PINBASED_CTLS, ~0ull }, 1345 }, 1346 { 1347 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1348 .to = { FEAT_VMX_EXIT_CTLS, ~0ull }, 1349 }, 1350 { 1351 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1352 .to = { FEAT_VMX_ENTRY_CTLS, ~0ull }, 1353 }, 1354 { 1355 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1356 .to = { FEAT_VMX_MISC, ~0ull }, 1357 }, 1358 { 1359 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1360 .to = { FEAT_VMX_BASIC, ~0ull }, 1361 }, 1362 { 1363 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_LM }, 1364 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_IA32E_MODE }, 1365 }, 1366 { 1367 .from = { FEAT_VMX_PROCBASED_CTLS, VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS }, 1368 .to = { FEAT_VMX_SECONDARY_CTLS, ~0ull }, 1369 }, 1370 { 1371 .from = { FEAT_XSAVE, CPUID_XSAVE_XSAVES }, 1372 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_XSAVES }, 1373 }, 1374 { 1375 .from = { FEAT_1_ECX, CPUID_EXT_RDRAND }, 1376 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDRAND_EXITING }, 1377 }, 1378 { 1379 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INVPCID }, 1380 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_INVPCID }, 1381 }, 1382 { 1383 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_MPX }, 1384 .to = { FEAT_VMX_EXIT_CTLS, VMX_VM_EXIT_CLEAR_BNDCFGS }, 1385 }, 1386 { 1387 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_MPX }, 1388 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_LOAD_BNDCFGS }, 1389 }, 1390 { 1391 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_RDSEED }, 1392 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDSEED_EXITING }, 1393 }, 1394 { 1395 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT }, 1396 .to = { FEAT_14_0_ECX, ~0ull }, 1397 }, 1398 { 1399 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_RDTSCP }, 1400 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDTSCP }, 1401 }, 1402 { 1403 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT }, 1404 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull }, 1405 }, 1406 { 1407 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT }, 1408 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST }, 1409 }, 1410 { 1411 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VPID }, 1412 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull << 32 }, 1413 }, 1414 { 1415 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VMFUNC }, 1416 .to = { FEAT_VMX_VMFUNC, ~0ull }, 1417 }, 1418 { 1419 .from = { FEAT_8000_0001_ECX, CPUID_EXT3_SVM }, 1420 .to = { FEAT_SVM, ~0ull }, 1421 }, 1422 }; 1423 1424 typedef struct X86RegisterInfo32 { 1425 /* Name of register */ 1426 const char *name; 1427 /* QAPI enum value register */ 1428 X86CPURegister32 qapi_enum; 1429 } X86RegisterInfo32; 1430 1431 #define REGISTER(reg) \ 1432 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg } 1433 static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = { 1434 REGISTER(EAX), 1435 REGISTER(ECX), 1436 REGISTER(EDX), 1437 REGISTER(EBX), 1438 REGISTER(ESP), 1439 REGISTER(EBP), 1440 REGISTER(ESI), 1441 REGISTER(EDI), 1442 }; 1443 #undef REGISTER 1444 1445 /* CPUID feature bits available in XSS */ 1446 #define CPUID_XSTATE_XSS_MASK (XSTATE_ARCH_LBR_MASK) 1447 1448 ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUNT] = { 1449 [XSTATE_FP_BIT] = { 1450 /* x87 FP state component is always enabled if XSAVE is supported */ 1451 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE, 1452 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader), 1453 }, 1454 [XSTATE_SSE_BIT] = { 1455 /* SSE state component is always enabled if XSAVE is supported */ 1456 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE, 1457 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader), 1458 }, 1459 [XSTATE_YMM_BIT] = 1460 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX, 1461 .size = sizeof(XSaveAVX) }, 1462 [XSTATE_BNDREGS_BIT] = 1463 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX, 1464 .size = sizeof(XSaveBNDREG) }, 1465 [XSTATE_BNDCSR_BIT] = 1466 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX, 1467 .size = sizeof(XSaveBNDCSR) }, 1468 [XSTATE_OPMASK_BIT] = 1469 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1470 .size = sizeof(XSaveOpmask) }, 1471 [XSTATE_ZMM_Hi256_BIT] = 1472 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1473 .size = sizeof(XSaveZMM_Hi256) }, 1474 [XSTATE_Hi16_ZMM_BIT] = 1475 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1476 .size = sizeof(XSaveHi16_ZMM) }, 1477 [XSTATE_PKRU_BIT] = 1478 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU, 1479 .size = sizeof(XSavePKRU) }, 1480 [XSTATE_ARCH_LBR_BIT] = { 1481 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_ARCH_LBR, 1482 .offset = 0 /*supervisor mode component, offset = 0 */, 1483 .size = sizeof(XSavesArchLBR) }, 1484 [XSTATE_XTILE_CFG_BIT] = { 1485 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_AMX_TILE, 1486 .size = sizeof(XSaveXTILECFG), 1487 }, 1488 [XSTATE_XTILE_DATA_BIT] = { 1489 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_AMX_TILE, 1490 .size = sizeof(XSaveXTILEDATA) 1491 }, 1492 }; 1493 1494 uint32_t xsave_area_size(uint64_t mask, bool compacted) 1495 { 1496 uint64_t ret = x86_ext_save_areas[0].size; 1497 const ExtSaveArea *esa; 1498 uint32_t offset = 0; 1499 int i; 1500 1501 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 1502 esa = &x86_ext_save_areas[i]; 1503 if ((mask >> i) & 1) { 1504 offset = compacted ? ret : esa->offset; 1505 ret = MAX(ret, offset + esa->size); 1506 } 1507 } 1508 return ret; 1509 } 1510 1511 static inline bool accel_uses_host_cpuid(void) 1512 { 1513 return kvm_enabled() || hvf_enabled(); 1514 } 1515 1516 static inline uint64_t x86_cpu_xsave_xcr0_components(X86CPU *cpu) 1517 { 1518 return ((uint64_t)cpu->env.features[FEAT_XSAVE_XCR0_HI]) << 32 | 1519 cpu->env.features[FEAT_XSAVE_XCR0_LO]; 1520 } 1521 1522 /* Return name of 32-bit register, from a R_* constant */ 1523 static const char *get_register_name_32(unsigned int reg) 1524 { 1525 if (reg >= CPU_NB_REGS32) { 1526 return NULL; 1527 } 1528 return x86_reg_info_32[reg].name; 1529 } 1530 1531 static inline uint64_t x86_cpu_xsave_xss_components(X86CPU *cpu) 1532 { 1533 return ((uint64_t)cpu->env.features[FEAT_XSAVE_XSS_HI]) << 32 | 1534 cpu->env.features[FEAT_XSAVE_XSS_LO]; 1535 } 1536 1537 /* 1538 * Returns the set of feature flags that are supported and migratable by 1539 * QEMU, for a given FeatureWord. 1540 */ 1541 static uint64_t x86_cpu_get_migratable_flags(FeatureWord w) 1542 { 1543 FeatureWordInfo *wi = &feature_word_info[w]; 1544 uint64_t r = 0; 1545 int i; 1546 1547 for (i = 0; i < 64; i++) { 1548 uint64_t f = 1ULL << i; 1549 1550 /* If the feature name is known, it is implicitly considered migratable, 1551 * unless it is explicitly set in unmigratable_flags */ 1552 if ((wi->migratable_flags & f) || 1553 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) { 1554 r |= f; 1555 } 1556 } 1557 return r; 1558 } 1559 1560 void host_cpuid(uint32_t function, uint32_t count, 1561 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) 1562 { 1563 uint32_t vec[4]; 1564 1565 #ifdef __x86_64__ 1566 asm volatile("cpuid" 1567 : "=a"(vec[0]), "=b"(vec[1]), 1568 "=c"(vec[2]), "=d"(vec[3]) 1569 : "0"(function), "c"(count) : "cc"); 1570 #elif defined(__i386__) 1571 asm volatile("pusha \n\t" 1572 "cpuid \n\t" 1573 "mov %%eax, 0(%2) \n\t" 1574 "mov %%ebx, 4(%2) \n\t" 1575 "mov %%ecx, 8(%2) \n\t" 1576 "mov %%edx, 12(%2) \n\t" 1577 "popa" 1578 : : "a"(function), "c"(count), "S"(vec) 1579 : "memory", "cc"); 1580 #else 1581 abort(); 1582 #endif 1583 1584 if (eax) 1585 *eax = vec[0]; 1586 if (ebx) 1587 *ebx = vec[1]; 1588 if (ecx) 1589 *ecx = vec[2]; 1590 if (edx) 1591 *edx = vec[3]; 1592 } 1593 1594 /* CPU class name definitions: */ 1595 1596 /* Return type name for a given CPU model name 1597 * Caller is responsible for freeing the returned string. 1598 */ 1599 static char *x86_cpu_type_name(const char *model_name) 1600 { 1601 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name); 1602 } 1603 1604 static ObjectClass *x86_cpu_class_by_name(const char *cpu_model) 1605 { 1606 g_autofree char *typename = x86_cpu_type_name(cpu_model); 1607 return object_class_by_name(typename); 1608 } 1609 1610 static char *x86_cpu_class_get_model_name(X86CPUClass *cc) 1611 { 1612 const char *class_name = object_class_get_name(OBJECT_CLASS(cc)); 1613 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX)); 1614 return g_strndup(class_name, 1615 strlen(class_name) - strlen(X86_CPU_TYPE_SUFFIX)); 1616 } 1617 1618 typedef struct X86CPUVersionDefinition { 1619 X86CPUVersion version; 1620 const char *alias; 1621 const char *note; 1622 PropValue *props; 1623 } X86CPUVersionDefinition; 1624 1625 /* Base definition for a CPU model */ 1626 typedef struct X86CPUDefinition { 1627 const char *name; 1628 uint32_t level; 1629 uint32_t xlevel; 1630 /* vendor is zero-terminated, 12 character ASCII string */ 1631 char vendor[CPUID_VENDOR_SZ + 1]; 1632 int family; 1633 int model; 1634 int stepping; 1635 FeatureWordArray features; 1636 const char *model_id; 1637 const CPUCaches *const cache_info; 1638 /* 1639 * Definitions for alternative versions of CPU model. 1640 * List is terminated by item with version == 0. 1641 * If NULL, version 1 will be registered automatically. 1642 */ 1643 const X86CPUVersionDefinition *versions; 1644 const char *deprecation_note; 1645 } X86CPUDefinition; 1646 1647 /* Reference to a specific CPU model version */ 1648 struct X86CPUModel { 1649 /* Base CPU definition */ 1650 const X86CPUDefinition *cpudef; 1651 /* CPU model version */ 1652 X86CPUVersion version; 1653 const char *note; 1654 /* 1655 * If true, this is an alias CPU model. 1656 * This matters only for "-cpu help" and query-cpu-definitions 1657 */ 1658 bool is_alias; 1659 }; 1660 1661 /* Get full model name for CPU version */ 1662 static char *x86_cpu_versioned_model_name(const X86CPUDefinition *cpudef, 1663 X86CPUVersion version) 1664 { 1665 assert(version > 0); 1666 return g_strdup_printf("%s-v%d", cpudef->name, (int)version); 1667 } 1668 1669 static const X86CPUVersionDefinition * 1670 x86_cpu_def_get_versions(const X86CPUDefinition *def) 1671 { 1672 /* When X86CPUDefinition::versions is NULL, we register only v1 */ 1673 static const X86CPUVersionDefinition default_version_list[] = { 1674 { 1 }, 1675 { /* end of list */ } 1676 }; 1677 1678 return def->versions ?: default_version_list; 1679 } 1680 1681 static const CPUCaches epyc_cache_info = { 1682 .l1d_cache = &(CPUCacheInfo) { 1683 .type = DATA_CACHE, 1684 .level = 1, 1685 .size = 32 * KiB, 1686 .line_size = 64, 1687 .associativity = 8, 1688 .partitions = 1, 1689 .sets = 64, 1690 .lines_per_tag = 1, 1691 .self_init = 1, 1692 .no_invd_sharing = true, 1693 }, 1694 .l1i_cache = &(CPUCacheInfo) { 1695 .type = INSTRUCTION_CACHE, 1696 .level = 1, 1697 .size = 64 * KiB, 1698 .line_size = 64, 1699 .associativity = 4, 1700 .partitions = 1, 1701 .sets = 256, 1702 .lines_per_tag = 1, 1703 .self_init = 1, 1704 .no_invd_sharing = true, 1705 }, 1706 .l2_cache = &(CPUCacheInfo) { 1707 .type = UNIFIED_CACHE, 1708 .level = 2, 1709 .size = 512 * KiB, 1710 .line_size = 64, 1711 .associativity = 8, 1712 .partitions = 1, 1713 .sets = 1024, 1714 .lines_per_tag = 1, 1715 }, 1716 .l3_cache = &(CPUCacheInfo) { 1717 .type = UNIFIED_CACHE, 1718 .level = 3, 1719 .size = 8 * MiB, 1720 .line_size = 64, 1721 .associativity = 16, 1722 .partitions = 1, 1723 .sets = 8192, 1724 .lines_per_tag = 1, 1725 .self_init = true, 1726 .inclusive = true, 1727 .complex_indexing = true, 1728 }, 1729 }; 1730 1731 static const CPUCaches epyc_rome_cache_info = { 1732 .l1d_cache = &(CPUCacheInfo) { 1733 .type = DATA_CACHE, 1734 .level = 1, 1735 .size = 32 * KiB, 1736 .line_size = 64, 1737 .associativity = 8, 1738 .partitions = 1, 1739 .sets = 64, 1740 .lines_per_tag = 1, 1741 .self_init = 1, 1742 .no_invd_sharing = true, 1743 }, 1744 .l1i_cache = &(CPUCacheInfo) { 1745 .type = INSTRUCTION_CACHE, 1746 .level = 1, 1747 .size = 32 * KiB, 1748 .line_size = 64, 1749 .associativity = 8, 1750 .partitions = 1, 1751 .sets = 64, 1752 .lines_per_tag = 1, 1753 .self_init = 1, 1754 .no_invd_sharing = true, 1755 }, 1756 .l2_cache = &(CPUCacheInfo) { 1757 .type = UNIFIED_CACHE, 1758 .level = 2, 1759 .size = 512 * KiB, 1760 .line_size = 64, 1761 .associativity = 8, 1762 .partitions = 1, 1763 .sets = 1024, 1764 .lines_per_tag = 1, 1765 }, 1766 .l3_cache = &(CPUCacheInfo) { 1767 .type = UNIFIED_CACHE, 1768 .level = 3, 1769 .size = 16 * MiB, 1770 .line_size = 64, 1771 .associativity = 16, 1772 .partitions = 1, 1773 .sets = 16384, 1774 .lines_per_tag = 1, 1775 .self_init = true, 1776 .inclusive = true, 1777 .complex_indexing = true, 1778 }, 1779 }; 1780 1781 static const CPUCaches epyc_milan_cache_info = { 1782 .l1d_cache = &(CPUCacheInfo) { 1783 .type = DATA_CACHE, 1784 .level = 1, 1785 .size = 32 * KiB, 1786 .line_size = 64, 1787 .associativity = 8, 1788 .partitions = 1, 1789 .sets = 64, 1790 .lines_per_tag = 1, 1791 .self_init = 1, 1792 .no_invd_sharing = true, 1793 }, 1794 .l1i_cache = &(CPUCacheInfo) { 1795 .type = INSTRUCTION_CACHE, 1796 .level = 1, 1797 .size = 32 * KiB, 1798 .line_size = 64, 1799 .associativity = 8, 1800 .partitions = 1, 1801 .sets = 64, 1802 .lines_per_tag = 1, 1803 .self_init = 1, 1804 .no_invd_sharing = true, 1805 }, 1806 .l2_cache = &(CPUCacheInfo) { 1807 .type = UNIFIED_CACHE, 1808 .level = 2, 1809 .size = 512 * KiB, 1810 .line_size = 64, 1811 .associativity = 8, 1812 .partitions = 1, 1813 .sets = 1024, 1814 .lines_per_tag = 1, 1815 }, 1816 .l3_cache = &(CPUCacheInfo) { 1817 .type = UNIFIED_CACHE, 1818 .level = 3, 1819 .size = 32 * MiB, 1820 .line_size = 64, 1821 .associativity = 16, 1822 .partitions = 1, 1823 .sets = 32768, 1824 .lines_per_tag = 1, 1825 .self_init = true, 1826 .inclusive = true, 1827 .complex_indexing = true, 1828 }, 1829 }; 1830 1831 /* The following VMX features are not supported by KVM and are left out in the 1832 * CPU definitions: 1833 * 1834 * Dual-monitor support (all processors) 1835 * Entry to SMM 1836 * Deactivate dual-monitor treatment 1837 * Number of CR3-target values 1838 * Shutdown activity state 1839 * Wait-for-SIPI activity state 1840 * PAUSE-loop exiting (Westmere and newer) 1841 * EPT-violation #VE (Broadwell and newer) 1842 * Inject event with insn length=0 (Skylake and newer) 1843 * Conceal non-root operation from PT 1844 * Conceal VM exits from PT 1845 * Conceal VM entries from PT 1846 * Enable ENCLS exiting 1847 * Mode-based execute control (XS/XU) 1848 s TSC scaling (Skylake Server and newer) 1849 * GPA translation for PT (IceLake and newer) 1850 * User wait and pause 1851 * ENCLV exiting 1852 * Load IA32_RTIT_CTL 1853 * Clear IA32_RTIT_CTL 1854 * Advanced VM-exit information for EPT violations 1855 * Sub-page write permissions 1856 * PT in VMX operation 1857 */ 1858 1859 static const X86CPUDefinition builtin_x86_defs[] = { 1860 { 1861 .name = "qemu64", 1862 .level = 0xd, 1863 .vendor = CPUID_VENDOR_AMD, 1864 .family = 15, 1865 .model = 107, 1866 .stepping = 1, 1867 .features[FEAT_1_EDX] = 1868 PPRO_FEATURES | 1869 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 1870 CPUID_PSE36, 1871 .features[FEAT_1_ECX] = 1872 CPUID_EXT_SSE3 | CPUID_EXT_CX16, 1873 .features[FEAT_8000_0001_EDX] = 1874 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 1875 .features[FEAT_8000_0001_ECX] = 1876 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM, 1877 .xlevel = 0x8000000A, 1878 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 1879 }, 1880 { 1881 .name = "phenom", 1882 .level = 5, 1883 .vendor = CPUID_VENDOR_AMD, 1884 .family = 16, 1885 .model = 2, 1886 .stepping = 3, 1887 /* Missing: CPUID_HT */ 1888 .features[FEAT_1_EDX] = 1889 PPRO_FEATURES | 1890 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 1891 CPUID_PSE36 | CPUID_VME, 1892 .features[FEAT_1_ECX] = 1893 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 | 1894 CPUID_EXT_POPCNT, 1895 .features[FEAT_8000_0001_EDX] = 1896 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | 1897 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT | 1898 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP, 1899 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, 1900 CPUID_EXT3_CR8LEG, 1901 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, 1902 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */ 1903 .features[FEAT_8000_0001_ECX] = 1904 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | 1905 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A, 1906 /* Missing: CPUID_SVM_LBRV */ 1907 .features[FEAT_SVM] = 1908 CPUID_SVM_NPT, 1909 .xlevel = 0x8000001A, 1910 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor" 1911 }, 1912 { 1913 .name = "core2duo", 1914 .level = 10, 1915 .vendor = CPUID_VENDOR_INTEL, 1916 .family = 6, 1917 .model = 15, 1918 .stepping = 11, 1919 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 1920 .features[FEAT_1_EDX] = 1921 PPRO_FEATURES | 1922 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 1923 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS, 1924 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST, 1925 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */ 1926 .features[FEAT_1_ECX] = 1927 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | 1928 CPUID_EXT_CX16, 1929 .features[FEAT_8000_0001_EDX] = 1930 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 1931 .features[FEAT_8000_0001_ECX] = 1932 CPUID_EXT3_LAHF_LM, 1933 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 1934 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 1935 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 1936 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 1937 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 1938 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 1939 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 1940 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 1941 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 1942 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 1943 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 1944 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 1945 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 1946 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 1947 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 1948 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 1949 .features[FEAT_VMX_SECONDARY_CTLS] = 1950 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES, 1951 .xlevel = 0x80000008, 1952 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz", 1953 }, 1954 { 1955 .name = "kvm64", 1956 .level = 0xd, 1957 .vendor = CPUID_VENDOR_INTEL, 1958 .family = 15, 1959 .model = 6, 1960 .stepping = 1, 1961 /* Missing: CPUID_HT */ 1962 .features[FEAT_1_EDX] = 1963 PPRO_FEATURES | CPUID_VME | 1964 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 1965 CPUID_PSE36, 1966 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */ 1967 .features[FEAT_1_ECX] = 1968 CPUID_EXT_SSE3 | CPUID_EXT_CX16, 1969 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */ 1970 .features[FEAT_8000_0001_EDX] = 1971 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 1972 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, 1973 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A, 1974 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, 1975 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */ 1976 .features[FEAT_8000_0001_ECX] = 1977 0, 1978 /* VMX features from Cedar Mill/Prescott */ 1979 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 1980 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 1981 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 1982 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 1983 VMX_PIN_BASED_NMI_EXITING, 1984 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 1985 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 1986 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 1987 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 1988 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 1989 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 1990 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 1991 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING, 1992 .xlevel = 0x80000008, 1993 .model_id = "Common KVM processor" 1994 }, 1995 { 1996 .name = "qemu32", 1997 .level = 4, 1998 .vendor = CPUID_VENDOR_INTEL, 1999 .family = 6, 2000 .model = 6, 2001 .stepping = 3, 2002 .features[FEAT_1_EDX] = 2003 PPRO_FEATURES, 2004 .features[FEAT_1_ECX] = 2005 CPUID_EXT_SSE3, 2006 .xlevel = 0x80000004, 2007 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 2008 }, 2009 { 2010 .name = "kvm32", 2011 .level = 5, 2012 .vendor = CPUID_VENDOR_INTEL, 2013 .family = 15, 2014 .model = 6, 2015 .stepping = 1, 2016 .features[FEAT_1_EDX] = 2017 PPRO_FEATURES | CPUID_VME | 2018 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36, 2019 .features[FEAT_1_ECX] = 2020 CPUID_EXT_SSE3, 2021 .features[FEAT_8000_0001_ECX] = 2022 0, 2023 /* VMX features from Yonah */ 2024 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2025 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2026 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2027 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2028 VMX_PIN_BASED_NMI_EXITING, 2029 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2030 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2031 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2032 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2033 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 2034 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 2035 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS, 2036 .xlevel = 0x80000008, 2037 .model_id = "Common 32-bit KVM processor" 2038 }, 2039 { 2040 .name = "coreduo", 2041 .level = 10, 2042 .vendor = CPUID_VENDOR_INTEL, 2043 .family = 6, 2044 .model = 14, 2045 .stepping = 8, 2046 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2047 .features[FEAT_1_EDX] = 2048 PPRO_FEATURES | CPUID_VME | 2049 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI | 2050 CPUID_SS, 2051 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR, 2052 * CPUID_EXT_PDCM, CPUID_EXT_VMX */ 2053 .features[FEAT_1_ECX] = 2054 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR, 2055 .features[FEAT_8000_0001_EDX] = 2056 CPUID_EXT2_NX, 2057 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2058 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2059 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2060 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2061 VMX_PIN_BASED_NMI_EXITING, 2062 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2063 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2064 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2065 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2066 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 2067 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 2068 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS, 2069 .xlevel = 0x80000008, 2070 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz", 2071 }, 2072 { 2073 .name = "486", 2074 .level = 1, 2075 .vendor = CPUID_VENDOR_INTEL, 2076 .family = 4, 2077 .model = 8, 2078 .stepping = 0, 2079 .features[FEAT_1_EDX] = 2080 I486_FEATURES, 2081 .xlevel = 0, 2082 .model_id = "", 2083 }, 2084 { 2085 .name = "pentium", 2086 .level = 1, 2087 .vendor = CPUID_VENDOR_INTEL, 2088 .family = 5, 2089 .model = 4, 2090 .stepping = 3, 2091 .features[FEAT_1_EDX] = 2092 PENTIUM_FEATURES, 2093 .xlevel = 0, 2094 .model_id = "", 2095 }, 2096 { 2097 .name = "pentium2", 2098 .level = 2, 2099 .vendor = CPUID_VENDOR_INTEL, 2100 .family = 6, 2101 .model = 5, 2102 .stepping = 2, 2103 .features[FEAT_1_EDX] = 2104 PENTIUM2_FEATURES, 2105 .xlevel = 0, 2106 .model_id = "", 2107 }, 2108 { 2109 .name = "pentium3", 2110 .level = 3, 2111 .vendor = CPUID_VENDOR_INTEL, 2112 .family = 6, 2113 .model = 7, 2114 .stepping = 3, 2115 .features[FEAT_1_EDX] = 2116 PENTIUM3_FEATURES, 2117 .xlevel = 0, 2118 .model_id = "", 2119 }, 2120 { 2121 .name = "athlon", 2122 .level = 2, 2123 .vendor = CPUID_VENDOR_AMD, 2124 .family = 6, 2125 .model = 2, 2126 .stepping = 3, 2127 .features[FEAT_1_EDX] = 2128 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR | 2129 CPUID_MCA, 2130 .features[FEAT_8000_0001_EDX] = 2131 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT, 2132 .xlevel = 0x80000008, 2133 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 2134 }, 2135 { 2136 .name = "n270", 2137 .level = 10, 2138 .vendor = CPUID_VENDOR_INTEL, 2139 .family = 6, 2140 .model = 28, 2141 .stepping = 2, 2142 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2143 .features[FEAT_1_EDX] = 2144 PPRO_FEATURES | 2145 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | 2146 CPUID_ACPI | CPUID_SS, 2147 /* Some CPUs got no CPUID_SEP */ 2148 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2, 2149 * CPUID_EXT_XTPR */ 2150 .features[FEAT_1_ECX] = 2151 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | 2152 CPUID_EXT_MOVBE, 2153 .features[FEAT_8000_0001_EDX] = 2154 CPUID_EXT2_NX, 2155 .features[FEAT_8000_0001_ECX] = 2156 CPUID_EXT3_LAHF_LM, 2157 .xlevel = 0x80000008, 2158 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz", 2159 }, 2160 { 2161 .name = "Conroe", 2162 .level = 10, 2163 .vendor = CPUID_VENDOR_INTEL, 2164 .family = 6, 2165 .model = 15, 2166 .stepping = 3, 2167 .features[FEAT_1_EDX] = 2168 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2169 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2170 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2171 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2172 CPUID_DE | CPUID_FP87, 2173 .features[FEAT_1_ECX] = 2174 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, 2175 .features[FEAT_8000_0001_EDX] = 2176 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 2177 .features[FEAT_8000_0001_ECX] = 2178 CPUID_EXT3_LAHF_LM, 2179 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2180 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2181 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2182 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2183 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2184 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2185 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2186 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2187 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2188 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2189 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2190 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2191 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2192 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2193 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2194 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2195 .features[FEAT_VMX_SECONDARY_CTLS] = 2196 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES, 2197 .xlevel = 0x80000008, 2198 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)", 2199 }, 2200 { 2201 .name = "Penryn", 2202 .level = 10, 2203 .vendor = CPUID_VENDOR_INTEL, 2204 .family = 6, 2205 .model = 23, 2206 .stepping = 3, 2207 .features[FEAT_1_EDX] = 2208 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2209 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2210 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2211 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2212 CPUID_DE | CPUID_FP87, 2213 .features[FEAT_1_ECX] = 2214 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2215 CPUID_EXT_SSE3, 2216 .features[FEAT_8000_0001_EDX] = 2217 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 2218 .features[FEAT_8000_0001_ECX] = 2219 CPUID_EXT3_LAHF_LM, 2220 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2221 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2222 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, 2223 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT | 2224 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL, 2225 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2226 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2227 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2228 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2229 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2230 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2231 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2232 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2233 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2234 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2235 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2236 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2237 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2238 .features[FEAT_VMX_SECONDARY_CTLS] = 2239 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2240 VMX_SECONDARY_EXEC_WBINVD_EXITING, 2241 .xlevel = 0x80000008, 2242 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)", 2243 }, 2244 { 2245 .name = "Nehalem", 2246 .level = 11, 2247 .vendor = CPUID_VENDOR_INTEL, 2248 .family = 6, 2249 .model = 26, 2250 .stepping = 3, 2251 .features[FEAT_1_EDX] = 2252 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2253 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2254 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2255 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2256 CPUID_DE | CPUID_FP87, 2257 .features[FEAT_1_ECX] = 2258 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 2259 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, 2260 .features[FEAT_8000_0001_EDX] = 2261 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2262 .features[FEAT_8000_0001_ECX] = 2263 CPUID_EXT3_LAHF_LM, 2264 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2265 MSR_VMX_BASIC_TRUE_CTLS, 2266 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2267 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2268 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2269 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2270 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2271 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2272 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2273 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2274 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2275 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2276 .features[FEAT_VMX_EXIT_CTLS] = 2277 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2278 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2279 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2280 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2281 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2282 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2283 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2284 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2285 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2286 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2287 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2288 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2289 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2290 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2291 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2292 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2293 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2294 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2295 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2296 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2297 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2298 .features[FEAT_VMX_SECONDARY_CTLS] = 2299 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2300 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2301 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2302 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2303 VMX_SECONDARY_EXEC_ENABLE_VPID, 2304 .xlevel = 0x80000008, 2305 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)", 2306 .versions = (X86CPUVersionDefinition[]) { 2307 { .version = 1 }, 2308 { 2309 .version = 2, 2310 .alias = "Nehalem-IBRS", 2311 .props = (PropValue[]) { 2312 { "spec-ctrl", "on" }, 2313 { "model-id", 2314 "Intel Core i7 9xx (Nehalem Core i7, IBRS update)" }, 2315 { /* end of list */ } 2316 } 2317 }, 2318 { /* end of list */ } 2319 } 2320 }, 2321 { 2322 .name = "Westmere", 2323 .level = 11, 2324 .vendor = CPUID_VENDOR_INTEL, 2325 .family = 6, 2326 .model = 44, 2327 .stepping = 1, 2328 .features[FEAT_1_EDX] = 2329 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2330 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2331 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2332 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2333 CPUID_DE | CPUID_FP87, 2334 .features[FEAT_1_ECX] = 2335 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | 2336 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2337 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 2338 .features[FEAT_8000_0001_EDX] = 2339 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2340 .features[FEAT_8000_0001_ECX] = 2341 CPUID_EXT3_LAHF_LM, 2342 .features[FEAT_6_EAX] = 2343 CPUID_6_EAX_ARAT, 2344 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2345 MSR_VMX_BASIC_TRUE_CTLS, 2346 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2347 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2348 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2349 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2350 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2351 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2352 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2353 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2354 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2355 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2356 .features[FEAT_VMX_EXIT_CTLS] = 2357 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2358 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2359 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2360 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2361 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2362 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2363 MSR_VMX_MISC_STORE_LMA, 2364 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2365 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2366 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2367 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2368 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2369 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2370 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2371 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2372 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2373 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2374 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2375 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2376 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2377 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2378 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2379 .features[FEAT_VMX_SECONDARY_CTLS] = 2380 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2381 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2382 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2383 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2384 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST, 2385 .xlevel = 0x80000008, 2386 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)", 2387 .versions = (X86CPUVersionDefinition[]) { 2388 { .version = 1 }, 2389 { 2390 .version = 2, 2391 .alias = "Westmere-IBRS", 2392 .props = (PropValue[]) { 2393 { "spec-ctrl", "on" }, 2394 { "model-id", 2395 "Westmere E56xx/L56xx/X56xx (IBRS update)" }, 2396 { /* end of list */ } 2397 } 2398 }, 2399 { /* end of list */ } 2400 } 2401 }, 2402 { 2403 .name = "SandyBridge", 2404 .level = 0xd, 2405 .vendor = CPUID_VENDOR_INTEL, 2406 .family = 6, 2407 .model = 42, 2408 .stepping = 1, 2409 .features[FEAT_1_EDX] = 2410 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2411 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2412 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2413 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2414 CPUID_DE | CPUID_FP87, 2415 .features[FEAT_1_ECX] = 2416 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2417 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | 2418 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 2419 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 2420 CPUID_EXT_SSE3, 2421 .features[FEAT_8000_0001_EDX] = 2422 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 2423 CPUID_EXT2_SYSCALL, 2424 .features[FEAT_8000_0001_ECX] = 2425 CPUID_EXT3_LAHF_LM, 2426 .features[FEAT_XSAVE] = 2427 CPUID_XSAVE_XSAVEOPT, 2428 .features[FEAT_6_EAX] = 2429 CPUID_6_EAX_ARAT, 2430 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2431 MSR_VMX_BASIC_TRUE_CTLS, 2432 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2433 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2434 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2435 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2436 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2437 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2438 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2439 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2440 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2441 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2442 .features[FEAT_VMX_EXIT_CTLS] = 2443 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2444 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2445 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2446 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2447 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2448 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2449 MSR_VMX_MISC_STORE_LMA, 2450 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2451 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2452 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2453 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2454 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2455 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2456 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2457 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2458 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2459 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2460 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2461 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2462 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2463 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2464 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2465 .features[FEAT_VMX_SECONDARY_CTLS] = 2466 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2467 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2468 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2469 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2470 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST, 2471 .xlevel = 0x80000008, 2472 .model_id = "Intel Xeon E312xx (Sandy Bridge)", 2473 .versions = (X86CPUVersionDefinition[]) { 2474 { .version = 1 }, 2475 { 2476 .version = 2, 2477 .alias = "SandyBridge-IBRS", 2478 .props = (PropValue[]) { 2479 { "spec-ctrl", "on" }, 2480 { "model-id", 2481 "Intel Xeon E312xx (Sandy Bridge, IBRS update)" }, 2482 { /* end of list */ } 2483 } 2484 }, 2485 { /* end of list */ } 2486 } 2487 }, 2488 { 2489 .name = "IvyBridge", 2490 .level = 0xd, 2491 .vendor = CPUID_VENDOR_INTEL, 2492 .family = 6, 2493 .model = 58, 2494 .stepping = 9, 2495 .features[FEAT_1_EDX] = 2496 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2497 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2498 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2499 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2500 CPUID_DE | CPUID_FP87, 2501 .features[FEAT_1_ECX] = 2502 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2503 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | 2504 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 2505 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 2506 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 2507 .features[FEAT_7_0_EBX] = 2508 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | 2509 CPUID_7_0_EBX_ERMS, 2510 .features[FEAT_8000_0001_EDX] = 2511 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 2512 CPUID_EXT2_SYSCALL, 2513 .features[FEAT_8000_0001_ECX] = 2514 CPUID_EXT3_LAHF_LM, 2515 .features[FEAT_XSAVE] = 2516 CPUID_XSAVE_XSAVEOPT, 2517 .features[FEAT_6_EAX] = 2518 CPUID_6_EAX_ARAT, 2519 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2520 MSR_VMX_BASIC_TRUE_CTLS, 2521 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2522 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2523 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2524 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2525 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2526 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2527 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2528 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2529 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2530 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2531 .features[FEAT_VMX_EXIT_CTLS] = 2532 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2533 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2534 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2535 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2536 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2537 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2538 MSR_VMX_MISC_STORE_LMA, 2539 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2540 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2541 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 2542 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2543 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2544 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2545 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2546 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2547 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2548 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2549 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2550 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2551 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2552 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2553 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2554 .features[FEAT_VMX_SECONDARY_CTLS] = 2555 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2556 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2557 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2558 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2559 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 2560 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 2561 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 2562 VMX_SECONDARY_EXEC_RDRAND_EXITING, 2563 .xlevel = 0x80000008, 2564 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)", 2565 .versions = (X86CPUVersionDefinition[]) { 2566 { .version = 1 }, 2567 { 2568 .version = 2, 2569 .alias = "IvyBridge-IBRS", 2570 .props = (PropValue[]) { 2571 { "spec-ctrl", "on" }, 2572 { "model-id", 2573 "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)" }, 2574 { /* end of list */ } 2575 } 2576 }, 2577 { /* end of list */ } 2578 } 2579 }, 2580 { 2581 .name = "Haswell", 2582 .level = 0xd, 2583 .vendor = CPUID_VENDOR_INTEL, 2584 .family = 6, 2585 .model = 60, 2586 .stepping = 4, 2587 .features[FEAT_1_EDX] = 2588 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2589 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2590 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2591 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2592 CPUID_DE | CPUID_FP87, 2593 .features[FEAT_1_ECX] = 2594 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2595 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 2596 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2597 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 2598 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 2599 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 2600 .features[FEAT_8000_0001_EDX] = 2601 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 2602 CPUID_EXT2_SYSCALL, 2603 .features[FEAT_8000_0001_ECX] = 2604 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM, 2605 .features[FEAT_7_0_EBX] = 2606 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 2607 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 2608 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 2609 CPUID_7_0_EBX_RTM, 2610 .features[FEAT_XSAVE] = 2611 CPUID_XSAVE_XSAVEOPT, 2612 .features[FEAT_6_EAX] = 2613 CPUID_6_EAX_ARAT, 2614 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2615 MSR_VMX_BASIC_TRUE_CTLS, 2616 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2617 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2618 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2619 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2620 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2621 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2622 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2623 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2624 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2625 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 2626 .features[FEAT_VMX_EXIT_CTLS] = 2627 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2628 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2629 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2630 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2631 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2632 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2633 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 2634 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2635 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2636 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 2637 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2638 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2639 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2640 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2641 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2642 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2643 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2644 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2645 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2646 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2647 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2648 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2649 .features[FEAT_VMX_SECONDARY_CTLS] = 2650 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2651 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2652 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2653 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2654 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 2655 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 2656 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 2657 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 2658 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS, 2659 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 2660 .xlevel = 0x80000008, 2661 .model_id = "Intel Core Processor (Haswell)", 2662 .versions = (X86CPUVersionDefinition[]) { 2663 { .version = 1 }, 2664 { 2665 .version = 2, 2666 .alias = "Haswell-noTSX", 2667 .props = (PropValue[]) { 2668 { "hle", "off" }, 2669 { "rtm", "off" }, 2670 { "stepping", "1" }, 2671 { "model-id", "Intel Core Processor (Haswell, no TSX)", }, 2672 { /* end of list */ } 2673 }, 2674 }, 2675 { 2676 .version = 3, 2677 .alias = "Haswell-IBRS", 2678 .props = (PropValue[]) { 2679 /* Restore TSX features removed by -v2 above */ 2680 { "hle", "on" }, 2681 { "rtm", "on" }, 2682 /* 2683 * Haswell and Haswell-IBRS had stepping=4 in 2684 * QEMU 4.0 and older 2685 */ 2686 { "stepping", "4" }, 2687 { "spec-ctrl", "on" }, 2688 { "model-id", 2689 "Intel Core Processor (Haswell, IBRS)" }, 2690 { /* end of list */ } 2691 } 2692 }, 2693 { 2694 .version = 4, 2695 .alias = "Haswell-noTSX-IBRS", 2696 .props = (PropValue[]) { 2697 { "hle", "off" }, 2698 { "rtm", "off" }, 2699 /* spec-ctrl was already enabled by -v3 above */ 2700 { "stepping", "1" }, 2701 { "model-id", 2702 "Intel Core Processor (Haswell, no TSX, IBRS)" }, 2703 { /* end of list */ } 2704 } 2705 }, 2706 { /* end of list */ } 2707 } 2708 }, 2709 { 2710 .name = "Broadwell", 2711 .level = 0xd, 2712 .vendor = CPUID_VENDOR_INTEL, 2713 .family = 6, 2714 .model = 61, 2715 .stepping = 2, 2716 .features[FEAT_1_EDX] = 2717 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2718 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2719 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2720 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2721 CPUID_DE | CPUID_FP87, 2722 .features[FEAT_1_ECX] = 2723 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2724 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 2725 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2726 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 2727 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 2728 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 2729 .features[FEAT_8000_0001_EDX] = 2730 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 2731 CPUID_EXT2_SYSCALL, 2732 .features[FEAT_8000_0001_ECX] = 2733 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 2734 .features[FEAT_7_0_EBX] = 2735 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 2736 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 2737 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 2738 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 2739 CPUID_7_0_EBX_SMAP, 2740 .features[FEAT_XSAVE] = 2741 CPUID_XSAVE_XSAVEOPT, 2742 .features[FEAT_6_EAX] = 2743 CPUID_6_EAX_ARAT, 2744 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2745 MSR_VMX_BASIC_TRUE_CTLS, 2746 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2747 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2748 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2749 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2750 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2751 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2752 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2753 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2754 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2755 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 2756 .features[FEAT_VMX_EXIT_CTLS] = 2757 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2758 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2759 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2760 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2761 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2762 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2763 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 2764 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2765 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2766 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 2767 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2768 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2769 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2770 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2771 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2772 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2773 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2774 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2775 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2776 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2777 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2778 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2779 .features[FEAT_VMX_SECONDARY_CTLS] = 2780 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2781 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2782 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2783 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2784 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 2785 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 2786 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 2787 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 2788 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 2789 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 2790 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 2791 .xlevel = 0x80000008, 2792 .model_id = "Intel Core Processor (Broadwell)", 2793 .versions = (X86CPUVersionDefinition[]) { 2794 { .version = 1 }, 2795 { 2796 .version = 2, 2797 .alias = "Broadwell-noTSX", 2798 .props = (PropValue[]) { 2799 { "hle", "off" }, 2800 { "rtm", "off" }, 2801 { "model-id", "Intel Core Processor (Broadwell, no TSX)", }, 2802 { /* end of list */ } 2803 }, 2804 }, 2805 { 2806 .version = 3, 2807 .alias = "Broadwell-IBRS", 2808 .props = (PropValue[]) { 2809 /* Restore TSX features removed by -v2 above */ 2810 { "hle", "on" }, 2811 { "rtm", "on" }, 2812 { "spec-ctrl", "on" }, 2813 { "model-id", 2814 "Intel Core Processor (Broadwell, IBRS)" }, 2815 { /* end of list */ } 2816 } 2817 }, 2818 { 2819 .version = 4, 2820 .alias = "Broadwell-noTSX-IBRS", 2821 .props = (PropValue[]) { 2822 { "hle", "off" }, 2823 { "rtm", "off" }, 2824 /* spec-ctrl was already enabled by -v3 above */ 2825 { "model-id", 2826 "Intel Core Processor (Broadwell, no TSX, IBRS)" }, 2827 { /* end of list */ } 2828 } 2829 }, 2830 { /* end of list */ } 2831 } 2832 }, 2833 { 2834 .name = "Skylake-Client", 2835 .level = 0xd, 2836 .vendor = CPUID_VENDOR_INTEL, 2837 .family = 6, 2838 .model = 94, 2839 .stepping = 3, 2840 .features[FEAT_1_EDX] = 2841 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2842 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2843 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2844 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2845 CPUID_DE | CPUID_FP87, 2846 .features[FEAT_1_ECX] = 2847 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2848 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 2849 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2850 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 2851 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 2852 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 2853 .features[FEAT_8000_0001_EDX] = 2854 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 2855 CPUID_EXT2_SYSCALL, 2856 .features[FEAT_8000_0001_ECX] = 2857 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 2858 .features[FEAT_7_0_EBX] = 2859 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 2860 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 2861 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 2862 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 2863 CPUID_7_0_EBX_SMAP, 2864 /* XSAVES is added in version 4 */ 2865 .features[FEAT_XSAVE] = 2866 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 2867 CPUID_XSAVE_XGETBV1, 2868 .features[FEAT_6_EAX] = 2869 CPUID_6_EAX_ARAT, 2870 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 2871 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2872 MSR_VMX_BASIC_TRUE_CTLS, 2873 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2874 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2875 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2876 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2877 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2878 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2879 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2880 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2881 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2882 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 2883 .features[FEAT_VMX_EXIT_CTLS] = 2884 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2885 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2886 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2887 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2888 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2889 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2890 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 2891 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2892 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2893 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2894 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2895 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2896 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2897 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2898 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2899 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2900 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2901 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2902 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2903 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2904 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2905 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2906 .features[FEAT_VMX_SECONDARY_CTLS] = 2907 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2908 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2909 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2910 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 2911 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 2912 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 2913 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 2914 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 2915 .xlevel = 0x80000008, 2916 .model_id = "Intel Core Processor (Skylake)", 2917 .versions = (X86CPUVersionDefinition[]) { 2918 { .version = 1 }, 2919 { 2920 .version = 2, 2921 .alias = "Skylake-Client-IBRS", 2922 .props = (PropValue[]) { 2923 { "spec-ctrl", "on" }, 2924 { "model-id", 2925 "Intel Core Processor (Skylake, IBRS)" }, 2926 { /* end of list */ } 2927 } 2928 }, 2929 { 2930 .version = 3, 2931 .alias = "Skylake-Client-noTSX-IBRS", 2932 .props = (PropValue[]) { 2933 { "hle", "off" }, 2934 { "rtm", "off" }, 2935 { "model-id", 2936 "Intel Core Processor (Skylake, IBRS, no TSX)" }, 2937 { /* end of list */ } 2938 } 2939 }, 2940 { 2941 .version = 4, 2942 .note = "IBRS, XSAVES, no TSX", 2943 .props = (PropValue[]) { 2944 { "xsaves", "on" }, 2945 { "vmx-xsaves", "on" }, 2946 { /* end of list */ } 2947 } 2948 }, 2949 { /* end of list */ } 2950 } 2951 }, 2952 { 2953 .name = "Skylake-Server", 2954 .level = 0xd, 2955 .vendor = CPUID_VENDOR_INTEL, 2956 .family = 6, 2957 .model = 85, 2958 .stepping = 4, 2959 .features[FEAT_1_EDX] = 2960 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2961 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2962 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2963 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2964 CPUID_DE | CPUID_FP87, 2965 .features[FEAT_1_ECX] = 2966 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2967 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 2968 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2969 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 2970 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 2971 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 2972 .features[FEAT_8000_0001_EDX] = 2973 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 2974 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 2975 .features[FEAT_8000_0001_ECX] = 2976 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 2977 .features[FEAT_7_0_EBX] = 2978 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 2979 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 2980 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 2981 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 2982 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 2983 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 2984 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 2985 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 2986 .features[FEAT_7_0_ECX] = 2987 CPUID_7_0_ECX_PKU, 2988 /* XSAVES is added in version 5 */ 2989 .features[FEAT_XSAVE] = 2990 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 2991 CPUID_XSAVE_XGETBV1, 2992 .features[FEAT_6_EAX] = 2993 CPUID_6_EAX_ARAT, 2994 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 2995 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2996 MSR_VMX_BASIC_TRUE_CTLS, 2997 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2998 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2999 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3000 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3001 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3002 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3003 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3004 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3005 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3006 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3007 .features[FEAT_VMX_EXIT_CTLS] = 3008 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3009 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3010 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3011 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3012 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3013 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3014 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3015 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3016 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3017 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3018 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3019 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3020 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3021 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3022 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3023 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3024 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3025 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3026 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3027 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3028 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3029 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3030 .features[FEAT_VMX_SECONDARY_CTLS] = 3031 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3032 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3033 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3034 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3035 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3036 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3037 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3038 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3039 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3040 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3041 .xlevel = 0x80000008, 3042 .model_id = "Intel Xeon Processor (Skylake)", 3043 .versions = (X86CPUVersionDefinition[]) { 3044 { .version = 1 }, 3045 { 3046 .version = 2, 3047 .alias = "Skylake-Server-IBRS", 3048 .props = (PropValue[]) { 3049 /* clflushopt was not added to Skylake-Server-IBRS */ 3050 /* TODO: add -v3 including clflushopt */ 3051 { "clflushopt", "off" }, 3052 { "spec-ctrl", "on" }, 3053 { "model-id", 3054 "Intel Xeon Processor (Skylake, IBRS)" }, 3055 { /* end of list */ } 3056 } 3057 }, 3058 { 3059 .version = 3, 3060 .alias = "Skylake-Server-noTSX-IBRS", 3061 .props = (PropValue[]) { 3062 { "hle", "off" }, 3063 { "rtm", "off" }, 3064 { "model-id", 3065 "Intel Xeon Processor (Skylake, IBRS, no TSX)" }, 3066 { /* end of list */ } 3067 } 3068 }, 3069 { 3070 .version = 4, 3071 .props = (PropValue[]) { 3072 { "vmx-eptp-switching", "on" }, 3073 { /* end of list */ } 3074 } 3075 }, 3076 { 3077 .version = 5, 3078 .note = "IBRS, XSAVES, EPT switching, no TSX", 3079 .props = (PropValue[]) { 3080 { "xsaves", "on" }, 3081 { "vmx-xsaves", "on" }, 3082 { /* end of list */ } 3083 } 3084 }, 3085 { /* end of list */ } 3086 } 3087 }, 3088 { 3089 .name = "Cascadelake-Server", 3090 .level = 0xd, 3091 .vendor = CPUID_VENDOR_INTEL, 3092 .family = 6, 3093 .model = 85, 3094 .stepping = 6, 3095 .features[FEAT_1_EDX] = 3096 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3097 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3098 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3099 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3100 CPUID_DE | CPUID_FP87, 3101 .features[FEAT_1_ECX] = 3102 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3103 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3104 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3105 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3106 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3107 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3108 .features[FEAT_8000_0001_EDX] = 3109 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3110 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3111 .features[FEAT_8000_0001_ECX] = 3112 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3113 .features[FEAT_7_0_EBX] = 3114 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3115 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3116 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3117 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3118 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3119 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3120 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3121 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3122 .features[FEAT_7_0_ECX] = 3123 CPUID_7_0_ECX_PKU | 3124 CPUID_7_0_ECX_AVX512VNNI, 3125 .features[FEAT_7_0_EDX] = 3126 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 3127 /* XSAVES is added in version 5 */ 3128 .features[FEAT_XSAVE] = 3129 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3130 CPUID_XSAVE_XGETBV1, 3131 .features[FEAT_6_EAX] = 3132 CPUID_6_EAX_ARAT, 3133 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3134 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3135 MSR_VMX_BASIC_TRUE_CTLS, 3136 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3137 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3138 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3139 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3140 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3141 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3142 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3143 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3144 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3145 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3146 .features[FEAT_VMX_EXIT_CTLS] = 3147 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3148 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3149 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3150 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3151 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3152 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3153 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3154 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3155 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3156 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3157 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3158 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3159 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3160 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3161 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3162 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3163 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3164 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3165 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3166 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3167 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3168 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3169 .features[FEAT_VMX_SECONDARY_CTLS] = 3170 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3171 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3172 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3173 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3174 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3175 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3176 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3177 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3178 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3179 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3180 .xlevel = 0x80000008, 3181 .model_id = "Intel Xeon Processor (Cascadelake)", 3182 .versions = (X86CPUVersionDefinition[]) { 3183 { .version = 1 }, 3184 { .version = 2, 3185 .note = "ARCH_CAPABILITIES", 3186 .props = (PropValue[]) { 3187 { "arch-capabilities", "on" }, 3188 { "rdctl-no", "on" }, 3189 { "ibrs-all", "on" }, 3190 { "skip-l1dfl-vmentry", "on" }, 3191 { "mds-no", "on" }, 3192 { /* end of list */ } 3193 }, 3194 }, 3195 { .version = 3, 3196 .alias = "Cascadelake-Server-noTSX", 3197 .note = "ARCH_CAPABILITIES, no TSX", 3198 .props = (PropValue[]) { 3199 { "hle", "off" }, 3200 { "rtm", "off" }, 3201 { /* end of list */ } 3202 }, 3203 }, 3204 { .version = 4, 3205 .note = "ARCH_CAPABILITIES, no TSX", 3206 .props = (PropValue[]) { 3207 { "vmx-eptp-switching", "on" }, 3208 { /* end of list */ } 3209 }, 3210 }, 3211 { .version = 5, 3212 .note = "ARCH_CAPABILITIES, EPT switching, XSAVES, no TSX", 3213 .props = (PropValue[]) { 3214 { "xsaves", "on" }, 3215 { "vmx-xsaves", "on" }, 3216 { /* end of list */ } 3217 }, 3218 }, 3219 { /* end of list */ } 3220 } 3221 }, 3222 { 3223 .name = "Cooperlake", 3224 .level = 0xd, 3225 .vendor = CPUID_VENDOR_INTEL, 3226 .family = 6, 3227 .model = 85, 3228 .stepping = 10, 3229 .features[FEAT_1_EDX] = 3230 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3231 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3232 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3233 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3234 CPUID_DE | CPUID_FP87, 3235 .features[FEAT_1_ECX] = 3236 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3237 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3238 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3239 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3240 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3241 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3242 .features[FEAT_8000_0001_EDX] = 3243 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3244 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3245 .features[FEAT_8000_0001_ECX] = 3246 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3247 .features[FEAT_7_0_EBX] = 3248 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3249 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3250 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3251 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3252 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3253 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3254 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3255 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3256 .features[FEAT_7_0_ECX] = 3257 CPUID_7_0_ECX_PKU | 3258 CPUID_7_0_ECX_AVX512VNNI, 3259 .features[FEAT_7_0_EDX] = 3260 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_STIBP | 3261 CPUID_7_0_EDX_SPEC_CTRL_SSBD | CPUID_7_0_EDX_ARCH_CAPABILITIES, 3262 .features[FEAT_ARCH_CAPABILITIES] = 3263 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 3264 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 3265 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO, 3266 .features[FEAT_7_1_EAX] = 3267 CPUID_7_1_EAX_AVX512_BF16, 3268 /* XSAVES is added in version 2 */ 3269 .features[FEAT_XSAVE] = 3270 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3271 CPUID_XSAVE_XGETBV1, 3272 .features[FEAT_6_EAX] = 3273 CPUID_6_EAX_ARAT, 3274 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3275 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3276 MSR_VMX_BASIC_TRUE_CTLS, 3277 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3278 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3279 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3280 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3281 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3282 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3283 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3284 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3285 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3286 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3287 .features[FEAT_VMX_EXIT_CTLS] = 3288 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3289 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3290 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3291 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3292 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3293 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3294 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3295 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3296 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3297 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3298 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3299 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3300 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3301 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3302 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3303 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3304 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3305 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3306 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3307 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3308 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3309 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3310 .features[FEAT_VMX_SECONDARY_CTLS] = 3311 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3312 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3313 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3314 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3315 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3316 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3317 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3318 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3319 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3320 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3321 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3322 .xlevel = 0x80000008, 3323 .model_id = "Intel Xeon Processor (Cooperlake)", 3324 .versions = (X86CPUVersionDefinition[]) { 3325 { .version = 1 }, 3326 { .version = 2, 3327 .note = "XSAVES", 3328 .props = (PropValue[]) { 3329 { "xsaves", "on" }, 3330 { "vmx-xsaves", "on" }, 3331 { /* end of list */ } 3332 }, 3333 }, 3334 { /* end of list */ } 3335 } 3336 }, 3337 { 3338 .name = "Icelake-Server", 3339 .level = 0xd, 3340 .vendor = CPUID_VENDOR_INTEL, 3341 .family = 6, 3342 .model = 134, 3343 .stepping = 0, 3344 .features[FEAT_1_EDX] = 3345 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3346 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3347 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3348 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3349 CPUID_DE | CPUID_FP87, 3350 .features[FEAT_1_ECX] = 3351 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3352 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3353 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3354 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3355 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3356 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3357 .features[FEAT_8000_0001_EDX] = 3358 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3359 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3360 .features[FEAT_8000_0001_ECX] = 3361 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3362 .features[FEAT_8000_0008_EBX] = 3363 CPUID_8000_0008_EBX_WBNOINVD, 3364 .features[FEAT_7_0_EBX] = 3365 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3366 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3367 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3368 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3369 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3370 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3371 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3372 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3373 .features[FEAT_7_0_ECX] = 3374 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 3375 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 3376 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 3377 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 3378 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57, 3379 .features[FEAT_7_0_EDX] = 3380 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 3381 /* XSAVES is added in version 5 */ 3382 .features[FEAT_XSAVE] = 3383 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3384 CPUID_XSAVE_XGETBV1, 3385 .features[FEAT_6_EAX] = 3386 CPUID_6_EAX_ARAT, 3387 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3388 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3389 MSR_VMX_BASIC_TRUE_CTLS, 3390 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3391 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3392 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3393 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3394 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3395 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3396 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3397 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3398 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3399 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3400 .features[FEAT_VMX_EXIT_CTLS] = 3401 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3402 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3403 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3404 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3405 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3406 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3407 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3408 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3409 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3410 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3411 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3412 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3413 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3414 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3415 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3416 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3417 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3418 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3419 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3420 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3421 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3422 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3423 .features[FEAT_VMX_SECONDARY_CTLS] = 3424 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3425 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3426 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3427 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3428 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3429 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3430 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3431 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3432 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS, 3433 .xlevel = 0x80000008, 3434 .model_id = "Intel Xeon Processor (Icelake)", 3435 .versions = (X86CPUVersionDefinition[]) { 3436 { .version = 1 }, 3437 { 3438 .version = 2, 3439 .note = "no TSX", 3440 .alias = "Icelake-Server-noTSX", 3441 .props = (PropValue[]) { 3442 { "hle", "off" }, 3443 { "rtm", "off" }, 3444 { /* end of list */ } 3445 }, 3446 }, 3447 { 3448 .version = 3, 3449 .props = (PropValue[]) { 3450 { "arch-capabilities", "on" }, 3451 { "rdctl-no", "on" }, 3452 { "ibrs-all", "on" }, 3453 { "skip-l1dfl-vmentry", "on" }, 3454 { "mds-no", "on" }, 3455 { "pschange-mc-no", "on" }, 3456 { "taa-no", "on" }, 3457 { /* end of list */ } 3458 }, 3459 }, 3460 { 3461 .version = 4, 3462 .props = (PropValue[]) { 3463 { "sha-ni", "on" }, 3464 { "avx512ifma", "on" }, 3465 { "rdpid", "on" }, 3466 { "fsrm", "on" }, 3467 { "vmx-rdseed-exit", "on" }, 3468 { "vmx-pml", "on" }, 3469 { "vmx-eptp-switching", "on" }, 3470 { "model", "106" }, 3471 { /* end of list */ } 3472 }, 3473 }, 3474 { 3475 .version = 5, 3476 .note = "XSAVES", 3477 .props = (PropValue[]) { 3478 { "xsaves", "on" }, 3479 { "vmx-xsaves", "on" }, 3480 { /* end of list */ } 3481 }, 3482 }, 3483 { 3484 .version = 6, 3485 .note = "5-level EPT", 3486 .props = (PropValue[]) { 3487 { "vmx-page-walk-5", "on" }, 3488 { /* end of list */ } 3489 }, 3490 }, 3491 { /* end of list */ } 3492 } 3493 }, 3494 { 3495 .name = "SapphireRapids", 3496 .level = 0x20, 3497 .vendor = CPUID_VENDOR_INTEL, 3498 .family = 6, 3499 .model = 143, 3500 .stepping = 4, 3501 /* 3502 * please keep the ascending order so that we can have a clear view of 3503 * bit position of each feature. 3504 */ 3505 .features[FEAT_1_EDX] = 3506 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 3507 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 3508 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 3509 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 3510 CPUID_SSE | CPUID_SSE2, 3511 .features[FEAT_1_ECX] = 3512 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 3513 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 3514 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 3515 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 3516 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3517 .features[FEAT_8000_0001_EDX] = 3518 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 3519 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 3520 .features[FEAT_8000_0001_ECX] = 3521 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 3522 .features[FEAT_8000_0008_EBX] = 3523 CPUID_8000_0008_EBX_WBNOINVD, 3524 .features[FEAT_7_0_EBX] = 3525 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_HLE | 3526 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | 3527 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RTM | 3528 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3529 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | 3530 CPUID_7_0_EBX_AVX512IFMA | CPUID_7_0_EBX_CLFLUSHOPT | 3531 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | 3532 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, 3533 .features[FEAT_7_0_ECX] = 3534 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 3535 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 3536 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 3537 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 3538 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | 3539 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT, 3540 .features[FEAT_7_0_EDX] = 3541 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 3542 CPUID_7_0_EDX_TSX_LDTRK | CPUID_7_0_EDX_AMX_BF16 | 3543 CPUID_7_0_EDX_AVX512_FP16 | CPUID_7_0_EDX_AMX_TILE | 3544 CPUID_7_0_EDX_AMX_INT8 | CPUID_7_0_EDX_SPEC_CTRL | 3545 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 3546 .features[FEAT_ARCH_CAPABILITIES] = 3547 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 3548 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 3549 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO, 3550 .features[FEAT_XSAVE] = 3551 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3552 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES | CPUID_D_1_EAX_XFD, 3553 .features[FEAT_6_EAX] = 3554 CPUID_6_EAX_ARAT, 3555 .features[FEAT_7_1_EAX] = 3556 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_AVX512_BF16 | 3557 CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC, 3558 .features[FEAT_VMX_BASIC] = 3559 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 3560 .features[FEAT_VMX_ENTRY_CTLS] = 3561 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 3562 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 3563 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 3564 .features[FEAT_VMX_EPT_VPID_CAPS] = 3565 MSR_VMX_EPT_EXECONLY | 3566 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_PAGE_WALK_LENGTH_5 | 3567 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 3568 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 3569 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3570 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3571 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 3572 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3573 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 3574 .features[FEAT_VMX_EXIT_CTLS] = 3575 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3576 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3577 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 3578 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3579 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3580 .features[FEAT_VMX_MISC] = 3581 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 3582 MSR_VMX_MISC_VMWRITE_VMEXIT, 3583 .features[FEAT_VMX_PINBASED_CTLS] = 3584 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 3585 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 3586 VMX_PIN_BASED_POSTED_INTR, 3587 .features[FEAT_VMX_PROCBASED_CTLS] = 3588 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3589 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3590 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3591 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3592 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3593 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3594 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 3595 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 3596 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3597 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 3598 VMX_CPU_BASED_PAUSE_EXITING | 3599 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3600 .features[FEAT_VMX_SECONDARY_CTLS] = 3601 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3602 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 3603 VMX_SECONDARY_EXEC_RDTSCP | 3604 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3605 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 3606 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3607 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3608 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3609 VMX_SECONDARY_EXEC_RDRAND_EXITING | 3610 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3611 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3612 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 3613 VMX_SECONDARY_EXEC_XSAVES, 3614 .features[FEAT_VMX_VMFUNC] = 3615 MSR_VMX_VMFUNC_EPT_SWITCHING, 3616 .xlevel = 0x80000008, 3617 .model_id = "Intel Xeon Processor (SapphireRapids)", 3618 .versions = (X86CPUVersionDefinition[]) { 3619 { .version = 1 }, 3620 { /* end of list */ }, 3621 }, 3622 }, 3623 { 3624 .name = "Denverton", 3625 .level = 21, 3626 .vendor = CPUID_VENDOR_INTEL, 3627 .family = 6, 3628 .model = 95, 3629 .stepping = 1, 3630 .features[FEAT_1_EDX] = 3631 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 3632 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 3633 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 3634 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 3635 CPUID_SSE | CPUID_SSE2, 3636 .features[FEAT_1_ECX] = 3637 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR | 3638 CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_SSE41 | 3639 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 3640 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | 3641 CPUID_EXT_AES | CPUID_EXT_XSAVE | CPUID_EXT_RDRAND, 3642 .features[FEAT_8000_0001_EDX] = 3643 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 3644 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 3645 .features[FEAT_8000_0001_ECX] = 3646 CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3647 .features[FEAT_7_0_EBX] = 3648 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_ERMS | 3649 CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_SMAP | 3650 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_SHA_NI, 3651 .features[FEAT_7_0_EDX] = 3652 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES | 3653 CPUID_7_0_EDX_SPEC_CTRL_SSBD, 3654 /* XSAVES is added in version 3 */ 3655 .features[FEAT_XSAVE] = 3656 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | CPUID_XSAVE_XGETBV1, 3657 .features[FEAT_6_EAX] = 3658 CPUID_6_EAX_ARAT, 3659 .features[FEAT_ARCH_CAPABILITIES] = 3660 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY, 3661 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3662 MSR_VMX_BASIC_TRUE_CTLS, 3663 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3664 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3665 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3666 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3667 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3668 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3669 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3670 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3671 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3672 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3673 .features[FEAT_VMX_EXIT_CTLS] = 3674 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3675 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3676 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3677 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3678 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3679 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3680 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3681 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3682 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3683 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3684 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3685 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3686 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3687 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3688 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3689 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3690 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3691 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3692 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3693 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3694 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3695 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3696 .features[FEAT_VMX_SECONDARY_CTLS] = 3697 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3698 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3699 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3700 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3701 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3702 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3703 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3704 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3705 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3706 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3707 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3708 .xlevel = 0x80000008, 3709 .model_id = "Intel Atom Processor (Denverton)", 3710 .versions = (X86CPUVersionDefinition[]) { 3711 { .version = 1 }, 3712 { 3713 .version = 2, 3714 .note = "no MPX, no MONITOR", 3715 .props = (PropValue[]) { 3716 { "monitor", "off" }, 3717 { "mpx", "off" }, 3718 { /* end of list */ }, 3719 }, 3720 }, 3721 { 3722 .version = 3, 3723 .note = "XSAVES, no MPX, no MONITOR", 3724 .props = (PropValue[]) { 3725 { "xsaves", "on" }, 3726 { "vmx-xsaves", "on" }, 3727 { /* end of list */ }, 3728 }, 3729 }, 3730 { /* end of list */ }, 3731 }, 3732 }, 3733 { 3734 .name = "Snowridge", 3735 .level = 27, 3736 .vendor = CPUID_VENDOR_INTEL, 3737 .family = 6, 3738 .model = 134, 3739 .stepping = 1, 3740 .features[FEAT_1_EDX] = 3741 /* missing: CPUID_PN CPUID_IA64 */ 3742 /* missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 3743 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | 3744 CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_MCE | 3745 CPUID_CX8 | CPUID_APIC | CPUID_SEP | 3746 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 3747 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | 3748 CPUID_MMX | 3749 CPUID_FXSR | CPUID_SSE | CPUID_SSE2, 3750 .features[FEAT_1_ECX] = 3751 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR | 3752 CPUID_EXT_SSSE3 | 3753 CPUID_EXT_CX16 | 3754 CPUID_EXT_SSE41 | 3755 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 3756 CPUID_EXT_POPCNT | 3757 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | CPUID_EXT_XSAVE | 3758 CPUID_EXT_RDRAND, 3759 .features[FEAT_8000_0001_EDX] = 3760 CPUID_EXT2_SYSCALL | 3761 CPUID_EXT2_NX | 3762 CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3763 CPUID_EXT2_LM, 3764 .features[FEAT_8000_0001_ECX] = 3765 CPUID_EXT3_LAHF_LM | 3766 CPUID_EXT3_3DNOWPREFETCH, 3767 .features[FEAT_7_0_EBX] = 3768 CPUID_7_0_EBX_FSGSBASE | 3769 CPUID_7_0_EBX_SMEP | 3770 CPUID_7_0_EBX_ERMS | 3771 CPUID_7_0_EBX_MPX | /* missing bits 13, 15 */ 3772 CPUID_7_0_EBX_RDSEED | 3773 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 3774 CPUID_7_0_EBX_CLWB | 3775 CPUID_7_0_EBX_SHA_NI, 3776 .features[FEAT_7_0_ECX] = 3777 CPUID_7_0_ECX_UMIP | 3778 /* missing bit 5 */ 3779 CPUID_7_0_ECX_GFNI | 3780 CPUID_7_0_ECX_MOVDIRI | CPUID_7_0_ECX_CLDEMOTE | 3781 CPUID_7_0_ECX_MOVDIR64B, 3782 .features[FEAT_7_0_EDX] = 3783 CPUID_7_0_EDX_SPEC_CTRL | 3784 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD | 3785 CPUID_7_0_EDX_CORE_CAPABILITY, 3786 .features[FEAT_CORE_CAPABILITY] = 3787 MSR_CORE_CAP_SPLIT_LOCK_DETECT, 3788 /* XSAVES is added in version 3 */ 3789 .features[FEAT_XSAVE] = 3790 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3791 CPUID_XSAVE_XGETBV1, 3792 .features[FEAT_6_EAX] = 3793 CPUID_6_EAX_ARAT, 3794 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3795 MSR_VMX_BASIC_TRUE_CTLS, 3796 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3797 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3798 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3799 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3800 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3801 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3802 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3803 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3804 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3805 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3806 .features[FEAT_VMX_EXIT_CTLS] = 3807 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3808 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3809 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3810 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3811 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3812 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3813 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3814 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3815 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3816 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3817 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3818 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3819 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3820 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3821 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3822 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3823 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3824 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3825 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3826 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3827 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3828 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3829 .features[FEAT_VMX_SECONDARY_CTLS] = 3830 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3831 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3832 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3833 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3834 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3835 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3836 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3837 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3838 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3839 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3840 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3841 .xlevel = 0x80000008, 3842 .model_id = "Intel Atom Processor (SnowRidge)", 3843 .versions = (X86CPUVersionDefinition[]) { 3844 { .version = 1 }, 3845 { 3846 .version = 2, 3847 .props = (PropValue[]) { 3848 { "mpx", "off" }, 3849 { "model-id", "Intel Atom Processor (Snowridge, no MPX)" }, 3850 { /* end of list */ }, 3851 }, 3852 }, 3853 { 3854 .version = 3, 3855 .note = "XSAVES, no MPX", 3856 .props = (PropValue[]) { 3857 { "xsaves", "on" }, 3858 { "vmx-xsaves", "on" }, 3859 { /* end of list */ }, 3860 }, 3861 }, 3862 { 3863 .version = 4, 3864 .note = "no split lock detect, no core-capability", 3865 .props = (PropValue[]) { 3866 { "split-lock-detect", "off" }, 3867 { "core-capability", "off" }, 3868 { /* end of list */ }, 3869 }, 3870 }, 3871 { /* end of list */ }, 3872 }, 3873 }, 3874 { 3875 .name = "KnightsMill", 3876 .level = 0xd, 3877 .vendor = CPUID_VENDOR_INTEL, 3878 .family = 6, 3879 .model = 133, 3880 .stepping = 0, 3881 .features[FEAT_1_EDX] = 3882 CPUID_VME | CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | 3883 CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | 3884 CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | 3885 CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | 3886 CPUID_PSE | CPUID_DE | CPUID_FP87, 3887 .features[FEAT_1_ECX] = 3888 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3889 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3890 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3891 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3892 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3893 CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3894 .features[FEAT_8000_0001_EDX] = 3895 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3896 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3897 .features[FEAT_8000_0001_ECX] = 3898 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3899 .features[FEAT_7_0_EBX] = 3900 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 3901 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 3902 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_AVX512F | 3903 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_AVX512PF | 3904 CPUID_7_0_EBX_AVX512ER, 3905 .features[FEAT_7_0_ECX] = 3906 CPUID_7_0_ECX_AVX512_VPOPCNTDQ, 3907 .features[FEAT_7_0_EDX] = 3908 CPUID_7_0_EDX_AVX512_4VNNIW | CPUID_7_0_EDX_AVX512_4FMAPS, 3909 .features[FEAT_XSAVE] = 3910 CPUID_XSAVE_XSAVEOPT, 3911 .features[FEAT_6_EAX] = 3912 CPUID_6_EAX_ARAT, 3913 .xlevel = 0x80000008, 3914 .model_id = "Intel Xeon Phi Processor (Knights Mill)", 3915 }, 3916 { 3917 .name = "Opteron_G1", 3918 .level = 5, 3919 .vendor = CPUID_VENDOR_AMD, 3920 .family = 15, 3921 .model = 6, 3922 .stepping = 1, 3923 .features[FEAT_1_EDX] = 3924 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3925 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3926 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3927 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3928 CPUID_DE | CPUID_FP87, 3929 .features[FEAT_1_ECX] = 3930 CPUID_EXT_SSE3, 3931 .features[FEAT_8000_0001_EDX] = 3932 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3933 .xlevel = 0x80000008, 3934 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)", 3935 }, 3936 { 3937 .name = "Opteron_G2", 3938 .level = 5, 3939 .vendor = CPUID_VENDOR_AMD, 3940 .family = 15, 3941 .model = 6, 3942 .stepping = 1, 3943 .features[FEAT_1_EDX] = 3944 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3945 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3946 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3947 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3948 CPUID_DE | CPUID_FP87, 3949 .features[FEAT_1_ECX] = 3950 CPUID_EXT_CX16 | CPUID_EXT_SSE3, 3951 .features[FEAT_8000_0001_EDX] = 3952 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3953 .features[FEAT_8000_0001_ECX] = 3954 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, 3955 .xlevel = 0x80000008, 3956 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)", 3957 }, 3958 { 3959 .name = "Opteron_G3", 3960 .level = 5, 3961 .vendor = CPUID_VENDOR_AMD, 3962 .family = 16, 3963 .model = 2, 3964 .stepping = 3, 3965 .features[FEAT_1_EDX] = 3966 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3967 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3968 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3969 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3970 CPUID_DE | CPUID_FP87, 3971 .features[FEAT_1_ECX] = 3972 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR | 3973 CPUID_EXT_SSE3, 3974 .features[FEAT_8000_0001_EDX] = 3975 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL | 3976 CPUID_EXT2_RDTSCP, 3977 .features[FEAT_8000_0001_ECX] = 3978 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | 3979 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, 3980 .xlevel = 0x80000008, 3981 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)", 3982 }, 3983 { 3984 .name = "Opteron_G4", 3985 .level = 0xd, 3986 .vendor = CPUID_VENDOR_AMD, 3987 .family = 21, 3988 .model = 1, 3989 .stepping = 2, 3990 .features[FEAT_1_EDX] = 3991 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3992 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3993 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3994 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3995 CPUID_DE | CPUID_FP87, 3996 .features[FEAT_1_ECX] = 3997 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3998 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 3999 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 4000 CPUID_EXT_SSE3, 4001 .features[FEAT_8000_0001_EDX] = 4002 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX | 4003 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP, 4004 .features[FEAT_8000_0001_ECX] = 4005 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP | 4006 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | 4007 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | 4008 CPUID_EXT3_LAHF_LM, 4009 .features[FEAT_SVM] = 4010 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 4011 /* no xsaveopt! */ 4012 .xlevel = 0x8000001A, 4013 .model_id = "AMD Opteron 62xx class CPU", 4014 }, 4015 { 4016 .name = "Opteron_G5", 4017 .level = 0xd, 4018 .vendor = CPUID_VENDOR_AMD, 4019 .family = 21, 4020 .model = 2, 4021 .stepping = 0, 4022 .features[FEAT_1_EDX] = 4023 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4024 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4025 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4026 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4027 CPUID_DE | CPUID_FP87, 4028 .features[FEAT_1_ECX] = 4029 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE | 4030 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | 4031 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA | 4032 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 4033 .features[FEAT_8000_0001_EDX] = 4034 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX | 4035 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP, 4036 .features[FEAT_8000_0001_ECX] = 4037 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP | 4038 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | 4039 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | 4040 CPUID_EXT3_LAHF_LM, 4041 .features[FEAT_SVM] = 4042 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 4043 /* no xsaveopt! */ 4044 .xlevel = 0x8000001A, 4045 .model_id = "AMD Opteron 63xx class CPU", 4046 }, 4047 { 4048 .name = "EPYC", 4049 .level = 0xd, 4050 .vendor = CPUID_VENDOR_AMD, 4051 .family = 23, 4052 .model = 1, 4053 .stepping = 2, 4054 .features[FEAT_1_EDX] = 4055 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 4056 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 4057 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 4058 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 4059 CPUID_VME | CPUID_FP87, 4060 .features[FEAT_1_ECX] = 4061 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 4062 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 4063 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 4064 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 4065 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 4066 .features[FEAT_8000_0001_EDX] = 4067 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 4068 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 4069 CPUID_EXT2_SYSCALL, 4070 .features[FEAT_8000_0001_ECX] = 4071 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 4072 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 4073 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 4074 CPUID_EXT3_TOPOEXT, 4075 .features[FEAT_7_0_EBX] = 4076 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4077 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 4078 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 4079 CPUID_7_0_EBX_SHA_NI, 4080 .features[FEAT_XSAVE] = 4081 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4082 CPUID_XSAVE_XGETBV1, 4083 .features[FEAT_6_EAX] = 4084 CPUID_6_EAX_ARAT, 4085 .features[FEAT_SVM] = 4086 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 4087 .xlevel = 0x8000001E, 4088 .model_id = "AMD EPYC Processor", 4089 .cache_info = &epyc_cache_info, 4090 .versions = (X86CPUVersionDefinition[]) { 4091 { .version = 1 }, 4092 { 4093 .version = 2, 4094 .alias = "EPYC-IBPB", 4095 .props = (PropValue[]) { 4096 { "ibpb", "on" }, 4097 { "model-id", 4098 "AMD EPYC Processor (with IBPB)" }, 4099 { /* end of list */ } 4100 } 4101 }, 4102 { 4103 .version = 3, 4104 .props = (PropValue[]) { 4105 { "ibpb", "on" }, 4106 { "perfctr-core", "on" }, 4107 { "clzero", "on" }, 4108 { "xsaveerptr", "on" }, 4109 { "xsaves", "on" }, 4110 { "model-id", 4111 "AMD EPYC Processor" }, 4112 { /* end of list */ } 4113 } 4114 }, 4115 { /* end of list */ } 4116 } 4117 }, 4118 { 4119 .name = "Dhyana", 4120 .level = 0xd, 4121 .vendor = CPUID_VENDOR_HYGON, 4122 .family = 24, 4123 .model = 0, 4124 .stepping = 1, 4125 .features[FEAT_1_EDX] = 4126 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 4127 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 4128 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 4129 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 4130 CPUID_VME | CPUID_FP87, 4131 .features[FEAT_1_ECX] = 4132 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 4133 CPUID_EXT_XSAVE | CPUID_EXT_POPCNT | 4134 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 4135 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 4136 CPUID_EXT_MONITOR | CPUID_EXT_SSE3, 4137 .features[FEAT_8000_0001_EDX] = 4138 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 4139 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 4140 CPUID_EXT2_SYSCALL, 4141 .features[FEAT_8000_0001_ECX] = 4142 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 4143 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 4144 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 4145 CPUID_EXT3_TOPOEXT, 4146 .features[FEAT_8000_0008_EBX] = 4147 CPUID_8000_0008_EBX_IBPB, 4148 .features[FEAT_7_0_EBX] = 4149 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4150 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 4151 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT, 4152 /* XSAVES is added in version 2 */ 4153 .features[FEAT_XSAVE] = 4154 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4155 CPUID_XSAVE_XGETBV1, 4156 .features[FEAT_6_EAX] = 4157 CPUID_6_EAX_ARAT, 4158 .features[FEAT_SVM] = 4159 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 4160 .xlevel = 0x8000001E, 4161 .model_id = "Hygon Dhyana Processor", 4162 .cache_info = &epyc_cache_info, 4163 .versions = (X86CPUVersionDefinition[]) { 4164 { .version = 1 }, 4165 { .version = 2, 4166 .note = "XSAVES", 4167 .props = (PropValue[]) { 4168 { "xsaves", "on" }, 4169 { /* end of list */ } 4170 }, 4171 }, 4172 { /* end of list */ } 4173 } 4174 }, 4175 { 4176 .name = "EPYC-Rome", 4177 .level = 0xd, 4178 .vendor = CPUID_VENDOR_AMD, 4179 .family = 23, 4180 .model = 49, 4181 .stepping = 0, 4182 .features[FEAT_1_EDX] = 4183 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 4184 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 4185 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 4186 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 4187 CPUID_VME | CPUID_FP87, 4188 .features[FEAT_1_ECX] = 4189 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 4190 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 4191 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 4192 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 4193 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 4194 .features[FEAT_8000_0001_EDX] = 4195 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 4196 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 4197 CPUID_EXT2_SYSCALL, 4198 .features[FEAT_8000_0001_ECX] = 4199 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 4200 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 4201 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 4202 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 4203 .features[FEAT_8000_0008_EBX] = 4204 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 4205 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 4206 CPUID_8000_0008_EBX_STIBP, 4207 .features[FEAT_7_0_EBX] = 4208 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4209 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 4210 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 4211 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB, 4212 .features[FEAT_7_0_ECX] = 4213 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID, 4214 .features[FEAT_XSAVE] = 4215 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4216 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 4217 .features[FEAT_6_EAX] = 4218 CPUID_6_EAX_ARAT, 4219 .features[FEAT_SVM] = 4220 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 4221 .xlevel = 0x8000001E, 4222 .model_id = "AMD EPYC-Rome Processor", 4223 .cache_info = &epyc_rome_cache_info, 4224 .versions = (X86CPUVersionDefinition[]) { 4225 { .version = 1 }, 4226 { 4227 .version = 2, 4228 .props = (PropValue[]) { 4229 { "ibrs", "on" }, 4230 { "amd-ssbd", "on" }, 4231 { /* end of list */ } 4232 } 4233 }, 4234 { /* end of list */ } 4235 } 4236 }, 4237 { 4238 .name = "EPYC-Milan", 4239 .level = 0xd, 4240 .vendor = CPUID_VENDOR_AMD, 4241 .family = 25, 4242 .model = 1, 4243 .stepping = 1, 4244 .features[FEAT_1_EDX] = 4245 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 4246 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 4247 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 4248 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 4249 CPUID_VME | CPUID_FP87, 4250 .features[FEAT_1_ECX] = 4251 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 4252 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 4253 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 4254 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 4255 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 4256 CPUID_EXT_PCID, 4257 .features[FEAT_8000_0001_EDX] = 4258 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 4259 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 4260 CPUID_EXT2_SYSCALL, 4261 .features[FEAT_8000_0001_ECX] = 4262 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 4263 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 4264 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 4265 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 4266 .features[FEAT_8000_0008_EBX] = 4267 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 4268 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 4269 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | 4270 CPUID_8000_0008_EBX_AMD_SSBD, 4271 .features[FEAT_7_0_EBX] = 4272 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4273 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 4274 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 4275 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_ERMS | 4276 CPUID_7_0_EBX_INVPCID, 4277 .features[FEAT_7_0_ECX] = 4278 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_PKU, 4279 .features[FEAT_7_0_EDX] = 4280 CPUID_7_0_EDX_FSRM, 4281 .features[FEAT_XSAVE] = 4282 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4283 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 4284 .features[FEAT_6_EAX] = 4285 CPUID_6_EAX_ARAT, 4286 .features[FEAT_SVM] = 4287 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE | CPUID_SVM_SVME_ADDR_CHK, 4288 .xlevel = 0x8000001E, 4289 .model_id = "AMD EPYC-Milan Processor", 4290 .cache_info = &epyc_milan_cache_info, 4291 }, 4292 }; 4293 4294 /* 4295 * We resolve CPU model aliases using -v1 when using "-machine 4296 * none", but this is just for compatibility while libvirt isn't 4297 * adapted to resolve CPU model versions before creating VMs. 4298 * See "Runnability guarantee of CPU models" at 4299 * docs/about/deprecated.rst. 4300 */ 4301 X86CPUVersion default_cpu_version = 1; 4302 4303 void x86_cpu_set_default_version(X86CPUVersion version) 4304 { 4305 /* Translating CPU_VERSION_AUTO to CPU_VERSION_AUTO doesn't make sense */ 4306 assert(version != CPU_VERSION_AUTO); 4307 default_cpu_version = version; 4308 } 4309 4310 static X86CPUVersion x86_cpu_model_last_version(const X86CPUModel *model) 4311 { 4312 int v = 0; 4313 const X86CPUVersionDefinition *vdef = 4314 x86_cpu_def_get_versions(model->cpudef); 4315 while (vdef->version) { 4316 v = vdef->version; 4317 vdef++; 4318 } 4319 return v; 4320 } 4321 4322 /* Return the actual version being used for a specific CPU model */ 4323 static X86CPUVersion x86_cpu_model_resolve_version(const X86CPUModel *model) 4324 { 4325 X86CPUVersion v = model->version; 4326 if (v == CPU_VERSION_AUTO) { 4327 v = default_cpu_version; 4328 } 4329 if (v == CPU_VERSION_LATEST) { 4330 return x86_cpu_model_last_version(model); 4331 } 4332 return v; 4333 } 4334 4335 static Property max_x86_cpu_properties[] = { 4336 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true), 4337 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false), 4338 DEFINE_PROP_END_OF_LIST() 4339 }; 4340 4341 static void max_x86_cpu_realize(DeviceState *dev, Error **errp) 4342 { 4343 Object *obj = OBJECT(dev); 4344 4345 if (!object_property_get_int(obj, "family", &error_abort)) { 4346 if (X86_CPU(obj)->env.features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 4347 object_property_set_int(obj, "family", 15, &error_abort); 4348 object_property_set_int(obj, "model", 107, &error_abort); 4349 object_property_set_int(obj, "stepping", 1, &error_abort); 4350 } else { 4351 object_property_set_int(obj, "family", 6, &error_abort); 4352 object_property_set_int(obj, "model", 6, &error_abort); 4353 object_property_set_int(obj, "stepping", 3, &error_abort); 4354 } 4355 } 4356 4357 x86_cpu_realizefn(dev, errp); 4358 } 4359 4360 static void max_x86_cpu_class_init(ObjectClass *oc, void *data) 4361 { 4362 DeviceClass *dc = DEVICE_CLASS(oc); 4363 X86CPUClass *xcc = X86_CPU_CLASS(oc); 4364 4365 xcc->ordering = 9; 4366 4367 xcc->model_description = 4368 "Enables all features supported by the accelerator in the current host"; 4369 4370 device_class_set_props(dc, max_x86_cpu_properties); 4371 dc->realize = max_x86_cpu_realize; 4372 } 4373 4374 static void max_x86_cpu_initfn(Object *obj) 4375 { 4376 X86CPU *cpu = X86_CPU(obj); 4377 4378 /* We can't fill the features array here because we don't know yet if 4379 * "migratable" is true or false. 4380 */ 4381 cpu->max_features = true; 4382 object_property_set_bool(OBJECT(cpu), "pmu", true, &error_abort); 4383 4384 /* 4385 * these defaults are used for TCG and all other accelerators 4386 * besides KVM and HVF, which overwrite these values 4387 */ 4388 object_property_set_str(OBJECT(cpu), "vendor", CPUID_VENDOR_AMD, 4389 &error_abort); 4390 object_property_set_str(OBJECT(cpu), "model-id", 4391 "QEMU TCG CPU version " QEMU_HW_VERSION, 4392 &error_abort); 4393 } 4394 4395 static const TypeInfo max_x86_cpu_type_info = { 4396 .name = X86_CPU_TYPE_NAME("max"), 4397 .parent = TYPE_X86_CPU, 4398 .instance_init = max_x86_cpu_initfn, 4399 .class_init = max_x86_cpu_class_init, 4400 }; 4401 4402 static char *feature_word_description(FeatureWordInfo *f, uint32_t bit) 4403 { 4404 assert(f->type == CPUID_FEATURE_WORD || f->type == MSR_FEATURE_WORD); 4405 4406 switch (f->type) { 4407 case CPUID_FEATURE_WORD: 4408 { 4409 const char *reg = get_register_name_32(f->cpuid.reg); 4410 assert(reg); 4411 return g_strdup_printf("CPUID.%02XH:%s", 4412 f->cpuid.eax, reg); 4413 } 4414 case MSR_FEATURE_WORD: 4415 return g_strdup_printf("MSR(%02XH)", 4416 f->msr.index); 4417 } 4418 4419 return NULL; 4420 } 4421 4422 static bool x86_cpu_have_filtered_features(X86CPU *cpu) 4423 { 4424 FeatureWord w; 4425 4426 for (w = 0; w < FEATURE_WORDS; w++) { 4427 if (cpu->filtered_features[w]) { 4428 return true; 4429 } 4430 } 4431 4432 return false; 4433 } 4434 4435 static void mark_unavailable_features(X86CPU *cpu, FeatureWord w, uint64_t mask, 4436 const char *verbose_prefix) 4437 { 4438 CPUX86State *env = &cpu->env; 4439 FeatureWordInfo *f = &feature_word_info[w]; 4440 int i; 4441 4442 if (!cpu->force_features) { 4443 env->features[w] &= ~mask; 4444 } 4445 cpu->filtered_features[w] |= mask; 4446 4447 if (!verbose_prefix) { 4448 return; 4449 } 4450 4451 for (i = 0; i < 64; ++i) { 4452 if ((1ULL << i) & mask) { 4453 g_autofree char *feat_word_str = feature_word_description(f, i); 4454 warn_report("%s: %s%s%s [bit %d]", 4455 verbose_prefix, 4456 feat_word_str, 4457 f->feat_names[i] ? "." : "", 4458 f->feat_names[i] ? f->feat_names[i] : "", i); 4459 } 4460 } 4461 } 4462 4463 static void x86_cpuid_version_get_family(Object *obj, Visitor *v, 4464 const char *name, void *opaque, 4465 Error **errp) 4466 { 4467 X86CPU *cpu = X86_CPU(obj); 4468 CPUX86State *env = &cpu->env; 4469 int64_t value; 4470 4471 value = (env->cpuid_version >> 8) & 0xf; 4472 if (value == 0xf) { 4473 value += (env->cpuid_version >> 20) & 0xff; 4474 } 4475 visit_type_int(v, name, &value, errp); 4476 } 4477 4478 static void x86_cpuid_version_set_family(Object *obj, Visitor *v, 4479 const char *name, void *opaque, 4480 Error **errp) 4481 { 4482 X86CPU *cpu = X86_CPU(obj); 4483 CPUX86State *env = &cpu->env; 4484 const int64_t min = 0; 4485 const int64_t max = 0xff + 0xf; 4486 int64_t value; 4487 4488 if (!visit_type_int(v, name, &value, errp)) { 4489 return; 4490 } 4491 if (value < min || value > max) { 4492 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", 4493 name ? name : "null", value, min, max); 4494 return; 4495 } 4496 4497 env->cpuid_version &= ~0xff00f00; 4498 if (value > 0x0f) { 4499 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20); 4500 } else { 4501 env->cpuid_version |= value << 8; 4502 } 4503 } 4504 4505 static void x86_cpuid_version_get_model(Object *obj, Visitor *v, 4506 const char *name, void *opaque, 4507 Error **errp) 4508 { 4509 X86CPU *cpu = X86_CPU(obj); 4510 CPUX86State *env = &cpu->env; 4511 int64_t value; 4512 4513 value = (env->cpuid_version >> 4) & 0xf; 4514 value |= ((env->cpuid_version >> 16) & 0xf) << 4; 4515 visit_type_int(v, name, &value, errp); 4516 } 4517 4518 static void x86_cpuid_version_set_model(Object *obj, Visitor *v, 4519 const char *name, void *opaque, 4520 Error **errp) 4521 { 4522 X86CPU *cpu = X86_CPU(obj); 4523 CPUX86State *env = &cpu->env; 4524 const int64_t min = 0; 4525 const int64_t max = 0xff; 4526 int64_t value; 4527 4528 if (!visit_type_int(v, name, &value, errp)) { 4529 return; 4530 } 4531 if (value < min || value > max) { 4532 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", 4533 name ? name : "null", value, min, max); 4534 return; 4535 } 4536 4537 env->cpuid_version &= ~0xf00f0; 4538 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16); 4539 } 4540 4541 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v, 4542 const char *name, void *opaque, 4543 Error **errp) 4544 { 4545 X86CPU *cpu = X86_CPU(obj); 4546 CPUX86State *env = &cpu->env; 4547 int64_t value; 4548 4549 value = env->cpuid_version & 0xf; 4550 visit_type_int(v, name, &value, errp); 4551 } 4552 4553 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v, 4554 const char *name, void *opaque, 4555 Error **errp) 4556 { 4557 X86CPU *cpu = X86_CPU(obj); 4558 CPUX86State *env = &cpu->env; 4559 const int64_t min = 0; 4560 const int64_t max = 0xf; 4561 int64_t value; 4562 4563 if (!visit_type_int(v, name, &value, errp)) { 4564 return; 4565 } 4566 if (value < min || value > max) { 4567 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", 4568 name ? name : "null", value, min, max); 4569 return; 4570 } 4571 4572 env->cpuid_version &= ~0xf; 4573 env->cpuid_version |= value & 0xf; 4574 } 4575 4576 static char *x86_cpuid_get_vendor(Object *obj, Error **errp) 4577 { 4578 X86CPU *cpu = X86_CPU(obj); 4579 CPUX86State *env = &cpu->env; 4580 char *value; 4581 4582 value = g_malloc(CPUID_VENDOR_SZ + 1); 4583 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2, 4584 env->cpuid_vendor3); 4585 return value; 4586 } 4587 4588 static void x86_cpuid_set_vendor(Object *obj, const char *value, 4589 Error **errp) 4590 { 4591 X86CPU *cpu = X86_CPU(obj); 4592 CPUX86State *env = &cpu->env; 4593 int i; 4594 4595 if (strlen(value) != CPUID_VENDOR_SZ) { 4596 error_setg(errp, QERR_PROPERTY_VALUE_BAD, "", "vendor", value); 4597 return; 4598 } 4599 4600 env->cpuid_vendor1 = 0; 4601 env->cpuid_vendor2 = 0; 4602 env->cpuid_vendor3 = 0; 4603 for (i = 0; i < 4; i++) { 4604 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i); 4605 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i); 4606 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i); 4607 } 4608 } 4609 4610 static char *x86_cpuid_get_model_id(Object *obj, Error **errp) 4611 { 4612 X86CPU *cpu = X86_CPU(obj); 4613 CPUX86State *env = &cpu->env; 4614 char *value; 4615 int i; 4616 4617 value = g_malloc(48 + 1); 4618 for (i = 0; i < 48; i++) { 4619 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3)); 4620 } 4621 value[48] = '\0'; 4622 return value; 4623 } 4624 4625 static void x86_cpuid_set_model_id(Object *obj, const char *model_id, 4626 Error **errp) 4627 { 4628 X86CPU *cpu = X86_CPU(obj); 4629 CPUX86State *env = &cpu->env; 4630 int c, len, i; 4631 4632 if (model_id == NULL) { 4633 model_id = ""; 4634 } 4635 len = strlen(model_id); 4636 memset(env->cpuid_model, 0, 48); 4637 for (i = 0; i < 48; i++) { 4638 if (i >= len) { 4639 c = '\0'; 4640 } else { 4641 c = (uint8_t)model_id[i]; 4642 } 4643 env->cpuid_model[i >> 2] |= c << (8 * (i & 3)); 4644 } 4645 } 4646 4647 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name, 4648 void *opaque, Error **errp) 4649 { 4650 X86CPU *cpu = X86_CPU(obj); 4651 int64_t value; 4652 4653 value = cpu->env.tsc_khz * 1000; 4654 visit_type_int(v, name, &value, errp); 4655 } 4656 4657 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name, 4658 void *opaque, Error **errp) 4659 { 4660 X86CPU *cpu = X86_CPU(obj); 4661 const int64_t min = 0; 4662 const int64_t max = INT64_MAX; 4663 int64_t value; 4664 4665 if (!visit_type_int(v, name, &value, errp)) { 4666 return; 4667 } 4668 if (value < min || value > max) { 4669 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", 4670 name ? name : "null", value, min, max); 4671 return; 4672 } 4673 4674 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000; 4675 } 4676 4677 /* Generic getter for "feature-words" and "filtered-features" properties */ 4678 static void x86_cpu_get_feature_words(Object *obj, Visitor *v, 4679 const char *name, void *opaque, 4680 Error **errp) 4681 { 4682 uint64_t *array = (uint64_t *)opaque; 4683 FeatureWord w; 4684 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { }; 4685 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { }; 4686 X86CPUFeatureWordInfoList *list = NULL; 4687 4688 for (w = 0; w < FEATURE_WORDS; w++) { 4689 FeatureWordInfo *wi = &feature_word_info[w]; 4690 /* 4691 * We didn't have MSR features when "feature-words" was 4692 * introduced. Therefore skipped other type entries. 4693 */ 4694 if (wi->type != CPUID_FEATURE_WORD) { 4695 continue; 4696 } 4697 X86CPUFeatureWordInfo *qwi = &word_infos[w]; 4698 qwi->cpuid_input_eax = wi->cpuid.eax; 4699 qwi->has_cpuid_input_ecx = wi->cpuid.needs_ecx; 4700 qwi->cpuid_input_ecx = wi->cpuid.ecx; 4701 qwi->cpuid_register = x86_reg_info_32[wi->cpuid.reg].qapi_enum; 4702 qwi->features = array[w]; 4703 4704 /* List will be in reverse order, but order shouldn't matter */ 4705 list_entries[w].next = list; 4706 list_entries[w].value = &word_infos[w]; 4707 list = &list_entries[w]; 4708 } 4709 4710 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp); 4711 } 4712 4713 /* Convert all '_' in a feature string option name to '-', to make feature 4714 * name conform to QOM property naming rule, which uses '-' instead of '_'. 4715 */ 4716 static inline void feat2prop(char *s) 4717 { 4718 while ((s = strchr(s, '_'))) { 4719 *s = '-'; 4720 } 4721 } 4722 4723 /* Return the feature property name for a feature flag bit */ 4724 static const char *x86_cpu_feature_name(FeatureWord w, int bitnr) 4725 { 4726 const char *name; 4727 /* XSAVE components are automatically enabled by other features, 4728 * so return the original feature name instead 4729 */ 4730 if (w == FEAT_XSAVE_XCR0_LO || w == FEAT_XSAVE_XCR0_HI) { 4731 int comp = (w == FEAT_XSAVE_XCR0_HI) ? bitnr + 32 : bitnr; 4732 4733 if (comp < ARRAY_SIZE(x86_ext_save_areas) && 4734 x86_ext_save_areas[comp].bits) { 4735 w = x86_ext_save_areas[comp].feature; 4736 bitnr = ctz32(x86_ext_save_areas[comp].bits); 4737 } 4738 } 4739 4740 assert(bitnr < 64); 4741 assert(w < FEATURE_WORDS); 4742 name = feature_word_info[w].feat_names[bitnr]; 4743 assert(bitnr < 32 || !(name && feature_word_info[w].type == CPUID_FEATURE_WORD)); 4744 return name; 4745 } 4746 4747 /* Compatibily hack to maintain legacy +-feat semantic, 4748 * where +-feat overwrites any feature set by 4749 * feat=on|feat even if the later is parsed after +-feat 4750 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled) 4751 */ 4752 static GList *plus_features, *minus_features; 4753 4754 static gint compare_string(gconstpointer a, gconstpointer b) 4755 { 4756 return g_strcmp0(a, b); 4757 } 4758 4759 /* Parse "+feature,-feature,feature=foo" CPU feature string 4760 */ 4761 static void x86_cpu_parse_featurestr(const char *typename, char *features, 4762 Error **errp) 4763 { 4764 char *featurestr; /* Single 'key=value" string being parsed */ 4765 static bool cpu_globals_initialized; 4766 bool ambiguous = false; 4767 4768 if (cpu_globals_initialized) { 4769 return; 4770 } 4771 cpu_globals_initialized = true; 4772 4773 if (!features) { 4774 return; 4775 } 4776 4777 for (featurestr = strtok(features, ","); 4778 featurestr; 4779 featurestr = strtok(NULL, ",")) { 4780 const char *name; 4781 const char *val = NULL; 4782 char *eq = NULL; 4783 char num[32]; 4784 GlobalProperty *prop; 4785 4786 /* Compatibility syntax: */ 4787 if (featurestr[0] == '+') { 4788 plus_features = g_list_append(plus_features, 4789 g_strdup(featurestr + 1)); 4790 continue; 4791 } else if (featurestr[0] == '-') { 4792 minus_features = g_list_append(minus_features, 4793 g_strdup(featurestr + 1)); 4794 continue; 4795 } 4796 4797 eq = strchr(featurestr, '='); 4798 if (eq) { 4799 *eq++ = 0; 4800 val = eq; 4801 } else { 4802 val = "on"; 4803 } 4804 4805 feat2prop(featurestr); 4806 name = featurestr; 4807 4808 if (g_list_find_custom(plus_features, name, compare_string)) { 4809 warn_report("Ambiguous CPU model string. " 4810 "Don't mix both \"+%s\" and \"%s=%s\"", 4811 name, name, val); 4812 ambiguous = true; 4813 } 4814 if (g_list_find_custom(minus_features, name, compare_string)) { 4815 warn_report("Ambiguous CPU model string. " 4816 "Don't mix both \"-%s\" and \"%s=%s\"", 4817 name, name, val); 4818 ambiguous = true; 4819 } 4820 4821 /* Special case: */ 4822 if (!strcmp(name, "tsc-freq")) { 4823 int ret; 4824 uint64_t tsc_freq; 4825 4826 ret = qemu_strtosz_metric(val, NULL, &tsc_freq); 4827 if (ret < 0 || tsc_freq > INT64_MAX) { 4828 error_setg(errp, "bad numerical value %s", val); 4829 return; 4830 } 4831 snprintf(num, sizeof(num), "%" PRId64, tsc_freq); 4832 val = num; 4833 name = "tsc-frequency"; 4834 } 4835 4836 prop = g_new0(typeof(*prop), 1); 4837 prop->driver = typename; 4838 prop->property = g_strdup(name); 4839 prop->value = g_strdup(val); 4840 qdev_prop_register_global(prop); 4841 } 4842 4843 if (ambiguous) { 4844 warn_report("Compatibility of ambiguous CPU model " 4845 "strings won't be kept on future QEMU versions"); 4846 } 4847 } 4848 4849 static void x86_cpu_filter_features(X86CPU *cpu, bool verbose); 4850 4851 /* Build a list with the name of all features on a feature word array */ 4852 static void x86_cpu_list_feature_names(FeatureWordArray features, 4853 strList **list) 4854 { 4855 strList **tail = list; 4856 FeatureWord w; 4857 4858 for (w = 0; w < FEATURE_WORDS; w++) { 4859 uint64_t filtered = features[w]; 4860 int i; 4861 for (i = 0; i < 64; i++) { 4862 if (filtered & (1ULL << i)) { 4863 QAPI_LIST_APPEND(tail, g_strdup(x86_cpu_feature_name(w, i))); 4864 } 4865 } 4866 } 4867 } 4868 4869 static void x86_cpu_get_unavailable_features(Object *obj, Visitor *v, 4870 const char *name, void *opaque, 4871 Error **errp) 4872 { 4873 X86CPU *xc = X86_CPU(obj); 4874 strList *result = NULL; 4875 4876 x86_cpu_list_feature_names(xc->filtered_features, &result); 4877 visit_type_strList(v, "unavailable-features", &result, errp); 4878 } 4879 4880 /* Print all cpuid feature names in featureset 4881 */ 4882 static void listflags(GList *features) 4883 { 4884 size_t len = 0; 4885 GList *tmp; 4886 4887 for (tmp = features; tmp; tmp = tmp->next) { 4888 const char *name = tmp->data; 4889 if ((len + strlen(name) + 1) >= 75) { 4890 qemu_printf("\n"); 4891 len = 0; 4892 } 4893 qemu_printf("%s%s", len == 0 ? " " : " ", name); 4894 len += strlen(name) + 1; 4895 } 4896 qemu_printf("\n"); 4897 } 4898 4899 /* Sort alphabetically by type name, respecting X86CPUClass::ordering. */ 4900 static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b) 4901 { 4902 ObjectClass *class_a = (ObjectClass *)a; 4903 ObjectClass *class_b = (ObjectClass *)b; 4904 X86CPUClass *cc_a = X86_CPU_CLASS(class_a); 4905 X86CPUClass *cc_b = X86_CPU_CLASS(class_b); 4906 int ret; 4907 4908 if (cc_a->ordering != cc_b->ordering) { 4909 ret = cc_a->ordering - cc_b->ordering; 4910 } else { 4911 g_autofree char *name_a = x86_cpu_class_get_model_name(cc_a); 4912 g_autofree char *name_b = x86_cpu_class_get_model_name(cc_b); 4913 ret = strcmp(name_a, name_b); 4914 } 4915 return ret; 4916 } 4917 4918 static GSList *get_sorted_cpu_model_list(void) 4919 { 4920 GSList *list = object_class_get_list(TYPE_X86_CPU, false); 4921 list = g_slist_sort(list, x86_cpu_list_compare); 4922 return list; 4923 } 4924 4925 static char *x86_cpu_class_get_model_id(X86CPUClass *xc) 4926 { 4927 Object *obj = object_new_with_class(OBJECT_CLASS(xc)); 4928 char *r = object_property_get_str(obj, "model-id", &error_abort); 4929 object_unref(obj); 4930 return r; 4931 } 4932 4933 static char *x86_cpu_class_get_alias_of(X86CPUClass *cc) 4934 { 4935 X86CPUVersion version; 4936 4937 if (!cc->model || !cc->model->is_alias) { 4938 return NULL; 4939 } 4940 version = x86_cpu_model_resolve_version(cc->model); 4941 if (version <= 0) { 4942 return NULL; 4943 } 4944 return x86_cpu_versioned_model_name(cc->model->cpudef, version); 4945 } 4946 4947 static void x86_cpu_list_entry(gpointer data, gpointer user_data) 4948 { 4949 ObjectClass *oc = data; 4950 X86CPUClass *cc = X86_CPU_CLASS(oc); 4951 g_autofree char *name = x86_cpu_class_get_model_name(cc); 4952 g_autofree char *desc = g_strdup(cc->model_description); 4953 g_autofree char *alias_of = x86_cpu_class_get_alias_of(cc); 4954 g_autofree char *model_id = x86_cpu_class_get_model_id(cc); 4955 4956 if (!desc && alias_of) { 4957 if (cc->model && cc->model->version == CPU_VERSION_AUTO) { 4958 desc = g_strdup("(alias configured by machine type)"); 4959 } else { 4960 desc = g_strdup_printf("(alias of %s)", alias_of); 4961 } 4962 } 4963 if (!desc && cc->model && cc->model->note) { 4964 desc = g_strdup_printf("%s [%s]", model_id, cc->model->note); 4965 } 4966 if (!desc) { 4967 desc = g_strdup_printf("%s", model_id); 4968 } 4969 4970 if (cc->model && cc->model->cpudef->deprecation_note) { 4971 g_autofree char *olddesc = desc; 4972 desc = g_strdup_printf("%s (deprecated)", olddesc); 4973 } 4974 4975 qemu_printf("x86 %-20s %s\n", name, desc); 4976 } 4977 4978 /* list available CPU models and flags */ 4979 void x86_cpu_list(void) 4980 { 4981 int i, j; 4982 GSList *list; 4983 GList *names = NULL; 4984 4985 qemu_printf("Available CPUs:\n"); 4986 list = get_sorted_cpu_model_list(); 4987 g_slist_foreach(list, x86_cpu_list_entry, NULL); 4988 g_slist_free(list); 4989 4990 names = NULL; 4991 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) { 4992 FeatureWordInfo *fw = &feature_word_info[i]; 4993 for (j = 0; j < 64; j++) { 4994 if (fw->feat_names[j]) { 4995 names = g_list_append(names, (gpointer)fw->feat_names[j]); 4996 } 4997 } 4998 } 4999 5000 names = g_list_sort(names, (GCompareFunc)strcmp); 5001 5002 qemu_printf("\nRecognized CPUID flags:\n"); 5003 listflags(names); 5004 qemu_printf("\n"); 5005 g_list_free(names); 5006 } 5007 5008 #ifndef CONFIG_USER_ONLY 5009 5010 /* Check for missing features that may prevent the CPU class from 5011 * running using the current machine and accelerator. 5012 */ 5013 static void x86_cpu_class_check_missing_features(X86CPUClass *xcc, 5014 strList **list) 5015 { 5016 strList **tail = list; 5017 X86CPU *xc; 5018 Error *err = NULL; 5019 5020 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) { 5021 QAPI_LIST_APPEND(tail, g_strdup("kvm")); 5022 return; 5023 } 5024 5025 xc = X86_CPU(object_new_with_class(OBJECT_CLASS(xcc))); 5026 5027 x86_cpu_expand_features(xc, &err); 5028 if (err) { 5029 /* Errors at x86_cpu_expand_features should never happen, 5030 * but in case it does, just report the model as not 5031 * runnable at all using the "type" property. 5032 */ 5033 QAPI_LIST_APPEND(tail, g_strdup("type")); 5034 error_free(err); 5035 } 5036 5037 x86_cpu_filter_features(xc, false); 5038 5039 x86_cpu_list_feature_names(xc->filtered_features, tail); 5040 5041 object_unref(OBJECT(xc)); 5042 } 5043 5044 static void x86_cpu_definition_entry(gpointer data, gpointer user_data) 5045 { 5046 ObjectClass *oc = data; 5047 X86CPUClass *cc = X86_CPU_CLASS(oc); 5048 CpuDefinitionInfoList **cpu_list = user_data; 5049 CpuDefinitionInfo *info; 5050 5051 info = g_malloc0(sizeof(*info)); 5052 info->name = x86_cpu_class_get_model_name(cc); 5053 x86_cpu_class_check_missing_features(cc, &info->unavailable_features); 5054 info->has_unavailable_features = true; 5055 info->q_typename = g_strdup(object_class_get_name(oc)); 5056 info->migration_safe = cc->migration_safe; 5057 info->has_migration_safe = true; 5058 info->q_static = cc->static_model; 5059 if (cc->model && cc->model->cpudef->deprecation_note) { 5060 info->deprecated = true; 5061 } else { 5062 info->deprecated = false; 5063 } 5064 /* 5065 * Old machine types won't report aliases, so that alias translation 5066 * doesn't break compatibility with previous QEMU versions. 5067 */ 5068 if (default_cpu_version != CPU_VERSION_LEGACY) { 5069 info->alias_of = x86_cpu_class_get_alias_of(cc); 5070 } 5071 5072 QAPI_LIST_PREPEND(*cpu_list, info); 5073 } 5074 5075 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) 5076 { 5077 CpuDefinitionInfoList *cpu_list = NULL; 5078 GSList *list = get_sorted_cpu_model_list(); 5079 g_slist_foreach(list, x86_cpu_definition_entry, &cpu_list); 5080 g_slist_free(list); 5081 return cpu_list; 5082 } 5083 5084 #endif /* !CONFIG_USER_ONLY */ 5085 5086 uint64_t x86_cpu_get_supported_feature_word(FeatureWord w, 5087 bool migratable_only) 5088 { 5089 FeatureWordInfo *wi = &feature_word_info[w]; 5090 uint64_t r = 0; 5091 5092 if (kvm_enabled()) { 5093 switch (wi->type) { 5094 case CPUID_FEATURE_WORD: 5095 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid.eax, 5096 wi->cpuid.ecx, 5097 wi->cpuid.reg); 5098 break; 5099 case MSR_FEATURE_WORD: 5100 r = kvm_arch_get_supported_msr_feature(kvm_state, 5101 wi->msr.index); 5102 break; 5103 } 5104 } else if (hvf_enabled()) { 5105 if (wi->type != CPUID_FEATURE_WORD) { 5106 return 0; 5107 } 5108 r = hvf_get_supported_cpuid(wi->cpuid.eax, 5109 wi->cpuid.ecx, 5110 wi->cpuid.reg); 5111 } else if (tcg_enabled()) { 5112 r = wi->tcg_features; 5113 } else { 5114 return ~0; 5115 } 5116 #ifndef TARGET_X86_64 5117 if (w == FEAT_8000_0001_EDX) { 5118 r &= ~CPUID_EXT2_LM; 5119 } 5120 #endif 5121 if (migratable_only) { 5122 r &= x86_cpu_get_migratable_flags(w); 5123 } 5124 return r; 5125 } 5126 5127 static void x86_cpu_get_supported_cpuid(uint32_t func, uint32_t index, 5128 uint32_t *eax, uint32_t *ebx, 5129 uint32_t *ecx, uint32_t *edx) 5130 { 5131 if (kvm_enabled()) { 5132 *eax = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EAX); 5133 *ebx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EBX); 5134 *ecx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_ECX); 5135 *edx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EDX); 5136 } else if (hvf_enabled()) { 5137 *eax = hvf_get_supported_cpuid(func, index, R_EAX); 5138 *ebx = hvf_get_supported_cpuid(func, index, R_EBX); 5139 *ecx = hvf_get_supported_cpuid(func, index, R_ECX); 5140 *edx = hvf_get_supported_cpuid(func, index, R_EDX); 5141 } else { 5142 *eax = 0; 5143 *ebx = 0; 5144 *ecx = 0; 5145 *edx = 0; 5146 } 5147 } 5148 5149 static void x86_cpu_get_cache_cpuid(uint32_t func, uint32_t index, 5150 uint32_t *eax, uint32_t *ebx, 5151 uint32_t *ecx, uint32_t *edx) 5152 { 5153 uint32_t level, unused; 5154 5155 /* Only return valid host leaves. */ 5156 switch (func) { 5157 case 2: 5158 case 4: 5159 host_cpuid(0, 0, &level, &unused, &unused, &unused); 5160 break; 5161 case 0x80000005: 5162 case 0x80000006: 5163 case 0x8000001d: 5164 host_cpuid(0x80000000, 0, &level, &unused, &unused, &unused); 5165 break; 5166 default: 5167 return; 5168 } 5169 5170 if (func > level) { 5171 *eax = 0; 5172 *ebx = 0; 5173 *ecx = 0; 5174 *edx = 0; 5175 } else { 5176 host_cpuid(func, index, eax, ebx, ecx, edx); 5177 } 5178 } 5179 5180 /* 5181 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 5182 */ 5183 void x86_cpu_apply_props(X86CPU *cpu, PropValue *props) 5184 { 5185 PropValue *pv; 5186 for (pv = props; pv->prop; pv++) { 5187 if (!pv->value) { 5188 continue; 5189 } 5190 object_property_parse(OBJECT(cpu), pv->prop, pv->value, 5191 &error_abort); 5192 } 5193 } 5194 5195 /* 5196 * Apply properties for the CPU model version specified in model. 5197 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 5198 */ 5199 5200 static void x86_cpu_apply_version_props(X86CPU *cpu, X86CPUModel *model) 5201 { 5202 const X86CPUVersionDefinition *vdef; 5203 X86CPUVersion version = x86_cpu_model_resolve_version(model); 5204 5205 if (version == CPU_VERSION_LEGACY) { 5206 return; 5207 } 5208 5209 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) { 5210 PropValue *p; 5211 5212 for (p = vdef->props; p && p->prop; p++) { 5213 object_property_parse(OBJECT(cpu), p->prop, p->value, 5214 &error_abort); 5215 } 5216 5217 if (vdef->version == version) { 5218 break; 5219 } 5220 } 5221 5222 /* 5223 * If we reached the end of the list, version number was invalid 5224 */ 5225 assert(vdef->version == version); 5226 } 5227 5228 /* 5229 * Load data from X86CPUDefinition into a X86CPU object. 5230 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 5231 */ 5232 static void x86_cpu_load_model(X86CPU *cpu, X86CPUModel *model) 5233 { 5234 const X86CPUDefinition *def = model->cpudef; 5235 CPUX86State *env = &cpu->env; 5236 FeatureWord w; 5237 5238 /*NOTE: any property set by this function should be returned by 5239 * x86_cpu_static_props(), so static expansion of 5240 * query-cpu-model-expansion is always complete. 5241 */ 5242 5243 /* CPU models only set _minimum_ values for level/xlevel: */ 5244 object_property_set_uint(OBJECT(cpu), "min-level", def->level, 5245 &error_abort); 5246 object_property_set_uint(OBJECT(cpu), "min-xlevel", def->xlevel, 5247 &error_abort); 5248 5249 object_property_set_int(OBJECT(cpu), "family", def->family, &error_abort); 5250 object_property_set_int(OBJECT(cpu), "model", def->model, &error_abort); 5251 object_property_set_int(OBJECT(cpu), "stepping", def->stepping, 5252 &error_abort); 5253 object_property_set_str(OBJECT(cpu), "model-id", def->model_id, 5254 &error_abort); 5255 for (w = 0; w < FEATURE_WORDS; w++) { 5256 env->features[w] = def->features[w]; 5257 } 5258 5259 /* legacy-cache defaults to 'off' if CPU model provides cache info */ 5260 cpu->legacy_cache = !def->cache_info; 5261 5262 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR; 5263 5264 /* sysenter isn't supported in compatibility mode on AMD, 5265 * syscall isn't supported in compatibility mode on Intel. 5266 * Normally we advertise the actual CPU vendor, but you can 5267 * override this using the 'vendor' property if you want to use 5268 * KVM's sysenter/syscall emulation in compatibility mode and 5269 * when doing cross vendor migration 5270 */ 5271 5272 /* 5273 * vendor property is set here but then overloaded with the 5274 * host cpu vendor for KVM and HVF. 5275 */ 5276 object_property_set_str(OBJECT(cpu), "vendor", def->vendor, &error_abort); 5277 5278 x86_cpu_apply_version_props(cpu, model); 5279 5280 /* 5281 * Properties in versioned CPU model are not user specified features. 5282 * We can simply clear env->user_features here since it will be filled later 5283 * in x86_cpu_expand_features() based on plus_features and minus_features. 5284 */ 5285 memset(&env->user_features, 0, sizeof(env->user_features)); 5286 } 5287 5288 static gchar *x86_gdb_arch_name(CPUState *cs) 5289 { 5290 #ifdef TARGET_X86_64 5291 return g_strdup("i386:x86-64"); 5292 #else 5293 return g_strdup("i386"); 5294 #endif 5295 } 5296 5297 static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data) 5298 { 5299 X86CPUModel *model = data; 5300 X86CPUClass *xcc = X86_CPU_CLASS(oc); 5301 CPUClass *cc = CPU_CLASS(oc); 5302 5303 xcc->model = model; 5304 xcc->migration_safe = true; 5305 cc->deprecation_note = model->cpudef->deprecation_note; 5306 } 5307 5308 static void x86_register_cpu_model_type(const char *name, X86CPUModel *model) 5309 { 5310 g_autofree char *typename = x86_cpu_type_name(name); 5311 TypeInfo ti = { 5312 .name = typename, 5313 .parent = TYPE_X86_CPU, 5314 .class_init = x86_cpu_cpudef_class_init, 5315 .class_data = model, 5316 }; 5317 5318 type_register(&ti); 5319 } 5320 5321 5322 /* 5323 * register builtin_x86_defs; 5324 * "max", "base" and subclasses ("host") are not registered here. 5325 * See x86_cpu_register_types for all model registrations. 5326 */ 5327 static void x86_register_cpudef_types(const X86CPUDefinition *def) 5328 { 5329 X86CPUModel *m; 5330 const X86CPUVersionDefinition *vdef; 5331 5332 /* AMD aliases are handled at runtime based on CPUID vendor, so 5333 * they shouldn't be set on the CPU model table. 5334 */ 5335 assert(!(def->features[FEAT_8000_0001_EDX] & CPUID_EXT2_AMD_ALIASES)); 5336 /* catch mistakes instead of silently truncating model_id when too long */ 5337 assert(def->model_id && strlen(def->model_id) <= 48); 5338 5339 /* Unversioned model: */ 5340 m = g_new0(X86CPUModel, 1); 5341 m->cpudef = def; 5342 m->version = CPU_VERSION_AUTO; 5343 m->is_alias = true; 5344 x86_register_cpu_model_type(def->name, m); 5345 5346 /* Versioned models: */ 5347 5348 for (vdef = x86_cpu_def_get_versions(def); vdef->version; vdef++) { 5349 X86CPUModel *m = g_new0(X86CPUModel, 1); 5350 g_autofree char *name = 5351 x86_cpu_versioned_model_name(def, vdef->version); 5352 m->cpudef = def; 5353 m->version = vdef->version; 5354 m->note = vdef->note; 5355 x86_register_cpu_model_type(name, m); 5356 5357 if (vdef->alias) { 5358 X86CPUModel *am = g_new0(X86CPUModel, 1); 5359 am->cpudef = def; 5360 am->version = vdef->version; 5361 am->is_alias = true; 5362 x86_register_cpu_model_type(vdef->alias, am); 5363 } 5364 } 5365 5366 } 5367 5368 uint32_t cpu_x86_virtual_addr_width(CPUX86State *env) 5369 { 5370 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57) { 5371 return 57; /* 57 bits virtual */ 5372 } else { 5373 return 48; /* 48 bits virtual */ 5374 } 5375 } 5376 5377 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, 5378 uint32_t *eax, uint32_t *ebx, 5379 uint32_t *ecx, uint32_t *edx) 5380 { 5381 X86CPU *cpu = env_archcpu(env); 5382 CPUState *cs = env_cpu(env); 5383 uint32_t die_offset; 5384 uint32_t limit; 5385 uint32_t signature[3]; 5386 X86CPUTopoInfo topo_info; 5387 5388 topo_info.dies_per_pkg = env->nr_dies; 5389 topo_info.cores_per_die = cs->nr_cores; 5390 topo_info.threads_per_core = cs->nr_threads; 5391 5392 /* Calculate & apply limits for different index ranges */ 5393 if (index >= 0xC0000000) { 5394 limit = env->cpuid_xlevel2; 5395 } else if (index >= 0x80000000) { 5396 limit = env->cpuid_xlevel; 5397 } else if (index >= 0x40000000) { 5398 limit = 0x40000001; 5399 } else { 5400 limit = env->cpuid_level; 5401 } 5402 5403 if (index > limit) { 5404 /* Intel documentation states that invalid EAX input will 5405 * return the same information as EAX=cpuid_level 5406 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID) 5407 */ 5408 index = env->cpuid_level; 5409 } 5410 5411 switch(index) { 5412 case 0: 5413 *eax = env->cpuid_level; 5414 *ebx = env->cpuid_vendor1; 5415 *edx = env->cpuid_vendor2; 5416 *ecx = env->cpuid_vendor3; 5417 break; 5418 case 1: 5419 *eax = env->cpuid_version; 5420 *ebx = (cpu->apic_id << 24) | 5421 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */ 5422 *ecx = env->features[FEAT_1_ECX]; 5423 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) { 5424 *ecx |= CPUID_EXT_OSXSAVE; 5425 } 5426 *edx = env->features[FEAT_1_EDX]; 5427 if (cs->nr_cores * cs->nr_threads > 1) { 5428 *ebx |= (cs->nr_cores * cs->nr_threads) << 16; 5429 *edx |= CPUID_HT; 5430 } 5431 if (!cpu->enable_pmu) { 5432 *ecx &= ~CPUID_EXT_PDCM; 5433 } 5434 break; 5435 case 2: 5436 /* cache info: needed for Pentium Pro compatibility */ 5437 if (cpu->cache_info_passthrough) { 5438 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 5439 break; 5440 } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { 5441 *eax = *ebx = *ecx = *edx = 0; 5442 break; 5443 } 5444 *eax = 1; /* Number of CPUID[EAX=2] calls required */ 5445 *ebx = 0; 5446 if (!cpu->enable_l3_cache) { 5447 *ecx = 0; 5448 } else { 5449 *ecx = cpuid2_cache_descriptor(env->cache_info_cpuid2.l3_cache); 5450 } 5451 *edx = (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1d_cache) << 16) | 5452 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1i_cache) << 8) | 5453 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l2_cache)); 5454 break; 5455 case 4: 5456 /* cache info: needed for Core compatibility */ 5457 if (cpu->cache_info_passthrough) { 5458 x86_cpu_get_cache_cpuid(index, count, eax, ebx, ecx, edx); 5459 /* 5460 * QEMU has its own number of cores/logical cpus, 5461 * set 24..14, 31..26 bit to configured values 5462 */ 5463 if (*eax & 31) { 5464 int host_vcpus_per_cache = 1 + ((*eax & 0x3FFC000) >> 14); 5465 int vcpus_per_socket = env->nr_dies * cs->nr_cores * 5466 cs->nr_threads; 5467 if (cs->nr_cores > 1) { 5468 *eax &= ~0xFC000000; 5469 *eax |= (pow2ceil(cs->nr_cores) - 1) << 26; 5470 } 5471 if (host_vcpus_per_cache > vcpus_per_socket) { 5472 *eax &= ~0x3FFC000; 5473 *eax |= (pow2ceil(vcpus_per_socket) - 1) << 14; 5474 } 5475 } 5476 } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { 5477 *eax = *ebx = *ecx = *edx = 0; 5478 } else { 5479 *eax = 0; 5480 switch (count) { 5481 case 0: /* L1 dcache info */ 5482 encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache, 5483 1, cs->nr_cores, 5484 eax, ebx, ecx, edx); 5485 break; 5486 case 1: /* L1 icache info */ 5487 encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache, 5488 1, cs->nr_cores, 5489 eax, ebx, ecx, edx); 5490 break; 5491 case 2: /* L2 cache info */ 5492 encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache, 5493 cs->nr_threads, cs->nr_cores, 5494 eax, ebx, ecx, edx); 5495 break; 5496 case 3: /* L3 cache info */ 5497 die_offset = apicid_die_offset(&topo_info); 5498 if (cpu->enable_l3_cache) { 5499 encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache, 5500 (1 << die_offset), cs->nr_cores, 5501 eax, ebx, ecx, edx); 5502 break; 5503 } 5504 /* fall through */ 5505 default: /* end of info */ 5506 *eax = *ebx = *ecx = *edx = 0; 5507 break; 5508 } 5509 } 5510 break; 5511 case 5: 5512 /* MONITOR/MWAIT Leaf */ 5513 *eax = cpu->mwait.eax; /* Smallest monitor-line size in bytes */ 5514 *ebx = cpu->mwait.ebx; /* Largest monitor-line size in bytes */ 5515 *ecx = cpu->mwait.ecx; /* flags */ 5516 *edx = cpu->mwait.edx; /* mwait substates */ 5517 break; 5518 case 6: 5519 /* Thermal and Power Leaf */ 5520 *eax = env->features[FEAT_6_EAX]; 5521 *ebx = 0; 5522 *ecx = 0; 5523 *edx = 0; 5524 break; 5525 case 7: 5526 /* Structured Extended Feature Flags Enumeration Leaf */ 5527 if (count == 0) { 5528 /* Maximum ECX value for sub-leaves */ 5529 *eax = env->cpuid_level_func7; 5530 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */ 5531 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */ 5532 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) { 5533 *ecx |= CPUID_7_0_ECX_OSPKE; 5534 } 5535 *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */ 5536 5537 /* 5538 * SGX cannot be emulated in software. If hardware does not 5539 * support enabling SGX and/or SGX flexible launch control, 5540 * then we need to update the VM's CPUID values accordingly. 5541 */ 5542 if ((*ebx & CPUID_7_0_EBX_SGX) && 5543 (!kvm_enabled() || 5544 !(kvm_arch_get_supported_cpuid(cs->kvm_state, 0x7, 0, R_EBX) & 5545 CPUID_7_0_EBX_SGX))) { 5546 *ebx &= ~CPUID_7_0_EBX_SGX; 5547 } 5548 5549 if ((*ecx & CPUID_7_0_ECX_SGX_LC) && 5550 (!(*ebx & CPUID_7_0_EBX_SGX) || !kvm_enabled() || 5551 !(kvm_arch_get_supported_cpuid(cs->kvm_state, 0x7, 0, R_ECX) & 5552 CPUID_7_0_ECX_SGX_LC))) { 5553 *ecx &= ~CPUID_7_0_ECX_SGX_LC; 5554 } 5555 } else if (count == 1) { 5556 *eax = env->features[FEAT_7_1_EAX]; 5557 *edx = env->features[FEAT_7_1_EDX]; 5558 *ebx = 0; 5559 *ecx = 0; 5560 } else { 5561 *eax = 0; 5562 *ebx = 0; 5563 *ecx = 0; 5564 *edx = 0; 5565 } 5566 break; 5567 case 9: 5568 /* Direct Cache Access Information Leaf */ 5569 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */ 5570 *ebx = 0; 5571 *ecx = 0; 5572 *edx = 0; 5573 break; 5574 case 0xA: 5575 /* Architectural Performance Monitoring Leaf */ 5576 if (accel_uses_host_cpuid() && cpu->enable_pmu) { 5577 x86_cpu_get_supported_cpuid(0xA, count, eax, ebx, ecx, edx); 5578 } else { 5579 *eax = 0; 5580 *ebx = 0; 5581 *ecx = 0; 5582 *edx = 0; 5583 } 5584 break; 5585 case 0xB: 5586 /* Extended Topology Enumeration Leaf */ 5587 if (!cpu->enable_cpuid_0xb) { 5588 *eax = *ebx = *ecx = *edx = 0; 5589 break; 5590 } 5591 5592 *ecx = count & 0xff; 5593 *edx = cpu->apic_id; 5594 5595 switch (count) { 5596 case 0: 5597 *eax = apicid_core_offset(&topo_info); 5598 *ebx = cs->nr_threads; 5599 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT; 5600 break; 5601 case 1: 5602 *eax = apicid_pkg_offset(&topo_info); 5603 *ebx = cs->nr_cores * cs->nr_threads; 5604 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE; 5605 break; 5606 default: 5607 *eax = 0; 5608 *ebx = 0; 5609 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID; 5610 } 5611 5612 assert(!(*eax & ~0x1f)); 5613 *ebx &= 0xffff; /* The count doesn't need to be reliable. */ 5614 break; 5615 case 0x1C: 5616 if (accel_uses_host_cpuid() && cpu->enable_pmu && 5617 (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) { 5618 x86_cpu_get_supported_cpuid(0x1C, 0, eax, ebx, ecx, edx); 5619 *edx = 0; 5620 } 5621 break; 5622 case 0x1F: 5623 /* V2 Extended Topology Enumeration Leaf */ 5624 if (env->nr_dies < 2) { 5625 *eax = *ebx = *ecx = *edx = 0; 5626 break; 5627 } 5628 5629 *ecx = count & 0xff; 5630 *edx = cpu->apic_id; 5631 switch (count) { 5632 case 0: 5633 *eax = apicid_core_offset(&topo_info); 5634 *ebx = cs->nr_threads; 5635 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT; 5636 break; 5637 case 1: 5638 *eax = apicid_die_offset(&topo_info); 5639 *ebx = cs->nr_cores * cs->nr_threads; 5640 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE; 5641 break; 5642 case 2: 5643 *eax = apicid_pkg_offset(&topo_info); 5644 *ebx = env->nr_dies * cs->nr_cores * cs->nr_threads; 5645 *ecx |= CPUID_TOPOLOGY_LEVEL_DIE; 5646 break; 5647 default: 5648 *eax = 0; 5649 *ebx = 0; 5650 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID; 5651 } 5652 assert(!(*eax & ~0x1f)); 5653 *ebx &= 0xffff; /* The count doesn't need to be reliable. */ 5654 break; 5655 case 0xD: { 5656 /* Processor Extended State */ 5657 *eax = 0; 5658 *ebx = 0; 5659 *ecx = 0; 5660 *edx = 0; 5661 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { 5662 break; 5663 } 5664 5665 if (count == 0) { 5666 *ecx = xsave_area_size(x86_cpu_xsave_xcr0_components(cpu), false); 5667 *eax = env->features[FEAT_XSAVE_XCR0_LO]; 5668 *edx = env->features[FEAT_XSAVE_XCR0_HI]; 5669 /* 5670 * The initial value of xcr0 and ebx == 0, On host without kvm 5671 * commit 412a3c41(e.g., CentOS 6), the ebx's value always == 0 5672 * even through guest update xcr0, this will crash some legacy guest 5673 * (e.g., CentOS 6), So set ebx == ecx to workaroud it. 5674 */ 5675 *ebx = kvm_enabled() ? *ecx : xsave_area_size(env->xcr0, false); 5676 } else if (count == 1) { 5677 uint64_t xstate = x86_cpu_xsave_xcr0_components(cpu) | 5678 x86_cpu_xsave_xss_components(cpu); 5679 5680 *eax = env->features[FEAT_XSAVE]; 5681 *ebx = xsave_area_size(xstate, true); 5682 *ecx = env->features[FEAT_XSAVE_XSS_LO]; 5683 *edx = env->features[FEAT_XSAVE_XSS_HI]; 5684 if (kvm_enabled() && cpu->enable_pmu && 5685 (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR) && 5686 (*eax & CPUID_XSAVE_XSAVES)) { 5687 *ecx |= XSTATE_ARCH_LBR_MASK; 5688 } else { 5689 *ecx &= ~XSTATE_ARCH_LBR_MASK; 5690 } 5691 } else if (count == 0xf && 5692 accel_uses_host_cpuid() && cpu->enable_pmu && 5693 (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) { 5694 x86_cpu_get_supported_cpuid(0xD, count, eax, ebx, ecx, edx); 5695 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) { 5696 const ExtSaveArea *esa = &x86_ext_save_areas[count]; 5697 5698 if (x86_cpu_xsave_xcr0_components(cpu) & (1ULL << count)) { 5699 *eax = esa->size; 5700 *ebx = esa->offset; 5701 *ecx = esa->ecx & 5702 (ESA_FEATURE_ALIGN64_MASK | ESA_FEATURE_XFD_MASK); 5703 } else if (x86_cpu_xsave_xss_components(cpu) & (1ULL << count)) { 5704 *eax = esa->size; 5705 *ebx = 0; 5706 *ecx = 1; 5707 } 5708 } 5709 break; 5710 } 5711 case 0x12: 5712 #ifndef CONFIG_USER_ONLY 5713 if (!kvm_enabled() || 5714 !(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX)) { 5715 *eax = *ebx = *ecx = *edx = 0; 5716 break; 5717 } 5718 5719 /* 5720 * SGX sub-leafs CPUID.0x12.{0x2..N} enumerate EPC sections. Retrieve 5721 * the EPC properties, e.g. confidentiality and integrity, from the 5722 * host's first EPC section, i.e. assume there is one EPC section or 5723 * that all EPC sections have the same security properties. 5724 */ 5725 if (count > 1) { 5726 uint64_t epc_addr, epc_size; 5727 5728 if (sgx_epc_get_section(count - 2, &epc_addr, &epc_size)) { 5729 *eax = *ebx = *ecx = *edx = 0; 5730 break; 5731 } 5732 host_cpuid(index, 2, eax, ebx, ecx, edx); 5733 *eax = (uint32_t)(epc_addr & 0xfffff000) | 0x1; 5734 *ebx = (uint32_t)(epc_addr >> 32); 5735 *ecx = (uint32_t)(epc_size & 0xfffff000) | (*ecx & 0xf); 5736 *edx = (uint32_t)(epc_size >> 32); 5737 break; 5738 } 5739 5740 /* 5741 * SGX sub-leafs CPUID.0x12.{0x0,0x1} are heavily dependent on hardware 5742 * and KVM, i.e. QEMU cannot emulate features to override what KVM 5743 * supports. Features can be further restricted by userspace, but not 5744 * made more permissive. 5745 */ 5746 x86_cpu_get_supported_cpuid(0x12, count, eax, ebx, ecx, edx); 5747 5748 if (count == 0) { 5749 *eax &= env->features[FEAT_SGX_12_0_EAX]; 5750 *ebx &= env->features[FEAT_SGX_12_0_EBX]; 5751 } else { 5752 *eax &= env->features[FEAT_SGX_12_1_EAX]; 5753 *ebx &= 0; /* ebx reserve */ 5754 *ecx &= env->features[FEAT_XSAVE_XCR0_LO]; 5755 *edx &= env->features[FEAT_XSAVE_XCR0_HI]; 5756 5757 /* FP and SSE are always allowed regardless of XSAVE/XCR0. */ 5758 *ecx |= XSTATE_FP_MASK | XSTATE_SSE_MASK; 5759 5760 /* Access to PROVISIONKEY requires additional credentials. */ 5761 if ((*eax & (1U << 4)) && 5762 !kvm_enable_sgx_provisioning(cs->kvm_state)) { 5763 *eax &= ~(1U << 4); 5764 } 5765 } 5766 #endif 5767 break; 5768 case 0x14: { 5769 /* Intel Processor Trace Enumeration */ 5770 *eax = 0; 5771 *ebx = 0; 5772 *ecx = 0; 5773 *edx = 0; 5774 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) || 5775 !kvm_enabled()) { 5776 break; 5777 } 5778 5779 if (count == 0) { 5780 *eax = INTEL_PT_MAX_SUBLEAF; 5781 *ebx = INTEL_PT_MINIMAL_EBX; 5782 *ecx = INTEL_PT_MINIMAL_ECX; 5783 if (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP) { 5784 *ecx |= CPUID_14_0_ECX_LIP; 5785 } 5786 } else if (count == 1) { 5787 *eax = INTEL_PT_MTC_BITMAP | INTEL_PT_ADDR_RANGES_NUM; 5788 *ebx = INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP; 5789 } 5790 break; 5791 } 5792 case 0x1D: { 5793 /* AMX TILE, for now hardcoded for Sapphire Rapids*/ 5794 *eax = 0; 5795 *ebx = 0; 5796 *ecx = 0; 5797 *edx = 0; 5798 if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) { 5799 break; 5800 } 5801 5802 if (count == 0) { 5803 /* Highest numbered palette subleaf */ 5804 *eax = INTEL_AMX_TILE_MAX_SUBLEAF; 5805 } else if (count == 1) { 5806 *eax = INTEL_AMX_TOTAL_TILE_BYTES | 5807 (INTEL_AMX_BYTES_PER_TILE << 16); 5808 *ebx = INTEL_AMX_BYTES_PER_ROW | (INTEL_AMX_TILE_MAX_NAMES << 16); 5809 *ecx = INTEL_AMX_TILE_MAX_ROWS; 5810 } 5811 break; 5812 } 5813 case 0x1E: { 5814 /* AMX TMUL, for now hardcoded for Sapphire Rapids */ 5815 *eax = 0; 5816 *ebx = 0; 5817 *ecx = 0; 5818 *edx = 0; 5819 if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) { 5820 break; 5821 } 5822 5823 if (count == 0) { 5824 /* Highest numbered palette subleaf */ 5825 *ebx = INTEL_AMX_TMUL_MAX_K | (INTEL_AMX_TMUL_MAX_N << 8); 5826 } 5827 break; 5828 } 5829 case 0x40000000: 5830 /* 5831 * CPUID code in kvm_arch_init_vcpu() ignores stuff 5832 * set here, but we restrict to TCG none the less. 5833 */ 5834 if (tcg_enabled() && cpu->expose_tcg) { 5835 memcpy(signature, "TCGTCGTCGTCG", 12); 5836 *eax = 0x40000001; 5837 *ebx = signature[0]; 5838 *ecx = signature[1]; 5839 *edx = signature[2]; 5840 } else { 5841 *eax = 0; 5842 *ebx = 0; 5843 *ecx = 0; 5844 *edx = 0; 5845 } 5846 break; 5847 case 0x40000001: 5848 *eax = 0; 5849 *ebx = 0; 5850 *ecx = 0; 5851 *edx = 0; 5852 break; 5853 case 0x80000000: 5854 *eax = env->cpuid_xlevel; 5855 *ebx = env->cpuid_vendor1; 5856 *edx = env->cpuid_vendor2; 5857 *ecx = env->cpuid_vendor3; 5858 break; 5859 case 0x80000001: 5860 *eax = env->cpuid_version; 5861 *ebx = 0; 5862 *ecx = env->features[FEAT_8000_0001_ECX]; 5863 *edx = env->features[FEAT_8000_0001_EDX]; 5864 5865 /* The Linux kernel checks for the CMPLegacy bit and 5866 * discards multiple thread information if it is set. 5867 * So don't set it here for Intel to make Linux guests happy. 5868 */ 5869 if (cs->nr_cores * cs->nr_threads > 1) { 5870 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 || 5871 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 || 5872 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) { 5873 *ecx |= 1 << 1; /* CmpLegacy bit */ 5874 } 5875 } 5876 break; 5877 case 0x80000002: 5878 case 0x80000003: 5879 case 0x80000004: 5880 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0]; 5881 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1]; 5882 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2]; 5883 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3]; 5884 break; 5885 case 0x80000005: 5886 /* cache info (L1 cache) */ 5887 if (cpu->cache_info_passthrough) { 5888 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 5889 break; 5890 } 5891 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | 5892 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES); 5893 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | 5894 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES); 5895 *ecx = encode_cache_cpuid80000005(env->cache_info_amd.l1d_cache); 5896 *edx = encode_cache_cpuid80000005(env->cache_info_amd.l1i_cache); 5897 break; 5898 case 0x80000006: 5899 /* cache info (L2 cache) */ 5900 if (cpu->cache_info_passthrough) { 5901 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 5902 break; 5903 } 5904 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | 5905 (L2_DTLB_2M_ENTRIES << 16) | 5906 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | 5907 (L2_ITLB_2M_ENTRIES); 5908 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | 5909 (L2_DTLB_4K_ENTRIES << 16) | 5910 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | 5911 (L2_ITLB_4K_ENTRIES); 5912 encode_cache_cpuid80000006(env->cache_info_amd.l2_cache, 5913 cpu->enable_l3_cache ? 5914 env->cache_info_amd.l3_cache : NULL, 5915 ecx, edx); 5916 break; 5917 case 0x80000007: 5918 *eax = 0; 5919 *ebx = 0; 5920 *ecx = 0; 5921 *edx = env->features[FEAT_8000_0007_EDX]; 5922 break; 5923 case 0x80000008: 5924 /* virtual & phys address size in low 2 bytes. */ 5925 *eax = cpu->phys_bits; 5926 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 5927 /* 64 bit processor */ 5928 *eax |= (cpu_x86_virtual_addr_width(env) << 8); 5929 } 5930 *ebx = env->features[FEAT_8000_0008_EBX]; 5931 if (cs->nr_cores * cs->nr_threads > 1) { 5932 /* 5933 * Bits 15:12 is "The number of bits in the initial 5934 * Core::X86::Apic::ApicId[ApicId] value that indicate 5935 * thread ID within a package". 5936 * Bits 7:0 is "The number of threads in the package is NC+1" 5937 */ 5938 *ecx = (apicid_pkg_offset(&topo_info) << 12) | 5939 ((cs->nr_cores * cs->nr_threads) - 1); 5940 } else { 5941 *ecx = 0; 5942 } 5943 *edx = 0; 5944 break; 5945 case 0x8000000A: 5946 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { 5947 *eax = 0x00000001; /* SVM Revision */ 5948 *ebx = 0x00000010; /* nr of ASIDs */ 5949 *ecx = 0; 5950 *edx = env->features[FEAT_SVM]; /* optional features */ 5951 } else { 5952 *eax = 0; 5953 *ebx = 0; 5954 *ecx = 0; 5955 *edx = 0; 5956 } 5957 break; 5958 case 0x8000001D: 5959 *eax = 0; 5960 if (cpu->cache_info_passthrough) { 5961 x86_cpu_get_cache_cpuid(index, count, eax, ebx, ecx, edx); 5962 break; 5963 } 5964 switch (count) { 5965 case 0: /* L1 dcache info */ 5966 encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache, 5967 &topo_info, eax, ebx, ecx, edx); 5968 break; 5969 case 1: /* L1 icache info */ 5970 encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache, 5971 &topo_info, eax, ebx, ecx, edx); 5972 break; 5973 case 2: /* L2 cache info */ 5974 encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache, 5975 &topo_info, eax, ebx, ecx, edx); 5976 break; 5977 case 3: /* L3 cache info */ 5978 encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache, 5979 &topo_info, eax, ebx, ecx, edx); 5980 break; 5981 default: /* end of info */ 5982 *eax = *ebx = *ecx = *edx = 0; 5983 break; 5984 } 5985 break; 5986 case 0x8000001E: 5987 if (cpu->core_id <= 255) { 5988 encode_topo_cpuid8000001e(cpu, &topo_info, eax, ebx, ecx, edx); 5989 } else { 5990 *eax = 0; 5991 *ebx = 0; 5992 *ecx = 0; 5993 *edx = 0; 5994 } 5995 break; 5996 case 0xC0000000: 5997 *eax = env->cpuid_xlevel2; 5998 *ebx = 0; 5999 *ecx = 0; 6000 *edx = 0; 6001 break; 6002 case 0xC0000001: 6003 /* Support for VIA CPU's CPUID instruction */ 6004 *eax = env->cpuid_version; 6005 *ebx = 0; 6006 *ecx = 0; 6007 *edx = env->features[FEAT_C000_0001_EDX]; 6008 break; 6009 case 0xC0000002: 6010 case 0xC0000003: 6011 case 0xC0000004: 6012 /* Reserved for the future, and now filled with zero */ 6013 *eax = 0; 6014 *ebx = 0; 6015 *ecx = 0; 6016 *edx = 0; 6017 break; 6018 case 0x8000001F: 6019 *eax = *ebx = *ecx = *edx = 0; 6020 if (sev_enabled()) { 6021 *eax = 0x2; 6022 *eax |= sev_es_enabled() ? 0x8 : 0; 6023 *ebx = sev_get_cbit_position() & 0x3f; /* EBX[5:0] */ 6024 *ebx |= (sev_get_reduced_phys_bits() & 0x3f) << 6; /* EBX[11:6] */ 6025 } 6026 break; 6027 default: 6028 /* reserved values: zero */ 6029 *eax = 0; 6030 *ebx = 0; 6031 *ecx = 0; 6032 *edx = 0; 6033 break; 6034 } 6035 } 6036 6037 static void x86_cpu_set_sgxlepubkeyhash(CPUX86State *env) 6038 { 6039 #ifndef CONFIG_USER_ONLY 6040 /* Those default values are defined in Skylake HW */ 6041 env->msr_ia32_sgxlepubkeyhash[0] = 0xa6053e051270b7acULL; 6042 env->msr_ia32_sgxlepubkeyhash[1] = 0x6cfbe8ba8b3b413dULL; 6043 env->msr_ia32_sgxlepubkeyhash[2] = 0xc4916d99f2b3735dULL; 6044 env->msr_ia32_sgxlepubkeyhash[3] = 0xd4f8c05909f9bb3bULL; 6045 #endif 6046 } 6047 6048 static void x86_cpu_reset_hold(Object *obj) 6049 { 6050 CPUState *s = CPU(obj); 6051 X86CPU *cpu = X86_CPU(s); 6052 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu); 6053 CPUX86State *env = &cpu->env; 6054 target_ulong cr4; 6055 uint64_t xcr0; 6056 int i; 6057 6058 if (xcc->parent_phases.hold) { 6059 xcc->parent_phases.hold(obj); 6060 } 6061 6062 memset(env, 0, offsetof(CPUX86State, end_reset_fields)); 6063 6064 env->old_exception = -1; 6065 6066 /* init to reset state */ 6067 env->int_ctl = 0; 6068 env->hflags2 |= HF2_GIF_MASK; 6069 env->hflags2 |= HF2_VGIF_MASK; 6070 env->hflags &= ~HF_GUEST_MASK; 6071 6072 cpu_x86_update_cr0(env, 0x60000010); 6073 env->a20_mask = ~0x0; 6074 env->smbase = 0x30000; 6075 env->msr_smi_count = 0; 6076 6077 env->idt.limit = 0xffff; 6078 env->gdt.limit = 0xffff; 6079 env->ldt.limit = 0xffff; 6080 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT); 6081 env->tr.limit = 0xffff; 6082 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT); 6083 6084 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff, 6085 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK | 6086 DESC_R_MASK | DESC_A_MASK); 6087 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff, 6088 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 6089 DESC_A_MASK); 6090 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff, 6091 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 6092 DESC_A_MASK); 6093 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff, 6094 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 6095 DESC_A_MASK); 6096 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff, 6097 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 6098 DESC_A_MASK); 6099 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff, 6100 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 6101 DESC_A_MASK); 6102 6103 env->eip = 0xfff0; 6104 env->regs[R_EDX] = env->cpuid_version; 6105 6106 env->eflags = 0x2; 6107 6108 /* FPU init */ 6109 for (i = 0; i < 8; i++) { 6110 env->fptags[i] = 1; 6111 } 6112 cpu_set_fpuc(env, 0x37f); 6113 6114 env->mxcsr = 0x1f80; 6115 /* All units are in INIT state. */ 6116 env->xstate_bv = 0; 6117 6118 env->pat = 0x0007040600070406ULL; 6119 6120 if (kvm_enabled()) { 6121 /* 6122 * KVM handles TSC = 0 specially and thinks we are hot-plugging 6123 * a new CPU, use 1 instead to force a reset. 6124 */ 6125 if (env->tsc != 0) { 6126 env->tsc = 1; 6127 } 6128 } else { 6129 env->tsc = 0; 6130 } 6131 6132 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT; 6133 if (env->features[FEAT_1_ECX] & CPUID_EXT_MONITOR) { 6134 env->msr_ia32_misc_enable |= MSR_IA32_MISC_ENABLE_MWAIT; 6135 } 6136 6137 memset(env->dr, 0, sizeof(env->dr)); 6138 env->dr[6] = DR6_FIXED_1; 6139 env->dr[7] = DR7_FIXED_1; 6140 cpu_breakpoint_remove_all(s, BP_CPU); 6141 cpu_watchpoint_remove_all(s, BP_CPU); 6142 6143 cr4 = 0; 6144 xcr0 = XSTATE_FP_MASK; 6145 6146 #ifdef CONFIG_USER_ONLY 6147 /* Enable all the features for user-mode. */ 6148 if (env->features[FEAT_1_EDX] & CPUID_SSE) { 6149 xcr0 |= XSTATE_SSE_MASK; 6150 } 6151 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 6152 const ExtSaveArea *esa = &x86_ext_save_areas[i]; 6153 if (!((1 << i) & CPUID_XSTATE_XCR0_MASK)) { 6154 continue; 6155 } 6156 if (env->features[esa->feature] & esa->bits) { 6157 xcr0 |= 1ull << i; 6158 } 6159 } 6160 6161 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) { 6162 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK; 6163 } 6164 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) { 6165 cr4 |= CR4_FSGSBASE_MASK; 6166 } 6167 #endif 6168 6169 env->xcr0 = xcr0; 6170 cpu_x86_update_cr4(env, cr4); 6171 6172 /* 6173 * SDM 11.11.5 requires: 6174 * - IA32_MTRR_DEF_TYPE MSR.E = 0 6175 * - IA32_MTRR_PHYSMASKn.V = 0 6176 * All other bits are undefined. For simplification, zero it all. 6177 */ 6178 env->mtrr_deftype = 0; 6179 memset(env->mtrr_var, 0, sizeof(env->mtrr_var)); 6180 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed)); 6181 6182 env->interrupt_injected = -1; 6183 env->exception_nr = -1; 6184 env->exception_pending = 0; 6185 env->exception_injected = 0; 6186 env->exception_has_payload = false; 6187 env->exception_payload = 0; 6188 env->nmi_injected = false; 6189 env->triple_fault_pending = false; 6190 #if !defined(CONFIG_USER_ONLY) 6191 /* We hard-wire the BSP to the first CPU. */ 6192 apic_designate_bsp(cpu->apic_state, s->cpu_index == 0); 6193 6194 s->halted = !cpu_is_bsp(cpu); 6195 6196 if (kvm_enabled()) { 6197 kvm_arch_reset_vcpu(cpu); 6198 } 6199 6200 x86_cpu_set_sgxlepubkeyhash(env); 6201 6202 env->amd_tsc_scale_msr = MSR_AMD64_TSC_RATIO_DEFAULT; 6203 6204 #endif 6205 } 6206 6207 void x86_cpu_after_reset(X86CPU *cpu) 6208 { 6209 #ifndef CONFIG_USER_ONLY 6210 if (kvm_enabled()) { 6211 kvm_arch_after_reset_vcpu(cpu); 6212 } 6213 6214 if (cpu->apic_state) { 6215 device_cold_reset(cpu->apic_state); 6216 } 6217 #endif 6218 } 6219 6220 static void mce_init(X86CPU *cpu) 6221 { 6222 CPUX86State *cenv = &cpu->env; 6223 unsigned int bank; 6224 6225 if (((cenv->cpuid_version >> 8) & 0xf) >= 6 6226 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) == 6227 (CPUID_MCE | CPUID_MCA)) { 6228 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF | 6229 (cpu->enable_lmce ? MCG_LMCE_P : 0); 6230 cenv->mcg_ctl = ~(uint64_t)0; 6231 for (bank = 0; bank < MCE_BANKS_DEF; bank++) { 6232 cenv->mce_banks[bank * 4] = ~(uint64_t)0; 6233 } 6234 } 6235 } 6236 6237 static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value) 6238 { 6239 if (*min < value) { 6240 *min = value; 6241 } 6242 } 6243 6244 /* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */ 6245 static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w) 6246 { 6247 CPUX86State *env = &cpu->env; 6248 FeatureWordInfo *fi = &feature_word_info[w]; 6249 uint32_t eax = fi->cpuid.eax; 6250 uint32_t region = eax & 0xF0000000; 6251 6252 assert(feature_word_info[w].type == CPUID_FEATURE_WORD); 6253 if (!env->features[w]) { 6254 return; 6255 } 6256 6257 switch (region) { 6258 case 0x00000000: 6259 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax); 6260 break; 6261 case 0x80000000: 6262 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax); 6263 break; 6264 case 0xC0000000: 6265 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax); 6266 break; 6267 } 6268 6269 if (eax == 7) { 6270 x86_cpu_adjust_level(cpu, &env->cpuid_min_level_func7, 6271 fi->cpuid.ecx); 6272 } 6273 } 6274 6275 /* Calculate XSAVE components based on the configured CPU feature flags */ 6276 static void x86_cpu_enable_xsave_components(X86CPU *cpu) 6277 { 6278 CPUX86State *env = &cpu->env; 6279 int i; 6280 uint64_t mask; 6281 static bool request_perm; 6282 6283 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { 6284 env->features[FEAT_XSAVE_XCR0_LO] = 0; 6285 env->features[FEAT_XSAVE_XCR0_HI] = 0; 6286 return; 6287 } 6288 6289 mask = 0; 6290 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 6291 const ExtSaveArea *esa = &x86_ext_save_areas[i]; 6292 if (env->features[esa->feature] & esa->bits) { 6293 mask |= (1ULL << i); 6294 } 6295 } 6296 6297 /* Only request permission for first vcpu */ 6298 if (kvm_enabled() && !request_perm) { 6299 kvm_request_xsave_components(cpu, mask); 6300 request_perm = true; 6301 } 6302 6303 env->features[FEAT_XSAVE_XCR0_LO] = mask & CPUID_XSTATE_XCR0_MASK; 6304 env->features[FEAT_XSAVE_XCR0_HI] = mask >> 32; 6305 env->features[FEAT_XSAVE_XSS_LO] = mask & CPUID_XSTATE_XSS_MASK; 6306 env->features[FEAT_XSAVE_XSS_HI] = mask >> 32; 6307 } 6308 6309 /***** Steps involved on loading and filtering CPUID data 6310 * 6311 * When initializing and realizing a CPU object, the steps 6312 * involved in setting up CPUID data are: 6313 * 6314 * 1) Loading CPU model definition (X86CPUDefinition). This is 6315 * implemented by x86_cpu_load_model() and should be completely 6316 * transparent, as it is done automatically by instance_init. 6317 * No code should need to look at X86CPUDefinition structs 6318 * outside instance_init. 6319 * 6320 * 2) CPU expansion. This is done by realize before CPUID 6321 * filtering, and will make sure host/accelerator data is 6322 * loaded for CPU models that depend on host capabilities 6323 * (e.g. "host"). Done by x86_cpu_expand_features(). 6324 * 6325 * 3) CPUID filtering. This initializes extra data related to 6326 * CPUID, and checks if the host supports all capabilities 6327 * required by the CPU. Runnability of a CPU model is 6328 * determined at this step. Done by x86_cpu_filter_features(). 6329 * 6330 * Some operations don't require all steps to be performed. 6331 * More precisely: 6332 * 6333 * - CPU instance creation (instance_init) will run only CPU 6334 * model loading. CPU expansion can't run at instance_init-time 6335 * because host/accelerator data may be not available yet. 6336 * - CPU realization will perform both CPU model expansion and CPUID 6337 * filtering, and return an error in case one of them fails. 6338 * - query-cpu-definitions needs to run all 3 steps. It needs 6339 * to run CPUID filtering, as the 'unavailable-features' 6340 * field is set based on the filtering results. 6341 * - The query-cpu-model-expansion QMP command only needs to run 6342 * CPU model loading and CPU expansion. It should not filter 6343 * any CPUID data based on host capabilities. 6344 */ 6345 6346 /* Expand CPU configuration data, based on configured features 6347 * and host/accelerator capabilities when appropriate. 6348 */ 6349 void x86_cpu_expand_features(X86CPU *cpu, Error **errp) 6350 { 6351 CPUX86State *env = &cpu->env; 6352 FeatureWord w; 6353 int i; 6354 GList *l; 6355 6356 for (l = plus_features; l; l = l->next) { 6357 const char *prop = l->data; 6358 if (!object_property_set_bool(OBJECT(cpu), prop, true, errp)) { 6359 return; 6360 } 6361 } 6362 6363 for (l = minus_features; l; l = l->next) { 6364 const char *prop = l->data; 6365 if (!object_property_set_bool(OBJECT(cpu), prop, false, errp)) { 6366 return; 6367 } 6368 } 6369 6370 /*TODO: Now cpu->max_features doesn't overwrite features 6371 * set using QOM properties, and we can convert 6372 * plus_features & minus_features to global properties 6373 * inside x86_cpu_parse_featurestr() too. 6374 */ 6375 if (cpu->max_features) { 6376 for (w = 0; w < FEATURE_WORDS; w++) { 6377 /* Override only features that weren't set explicitly 6378 * by the user. 6379 */ 6380 env->features[w] |= 6381 x86_cpu_get_supported_feature_word(w, cpu->migratable) & 6382 ~env->user_features[w] & 6383 ~feature_word_info[w].no_autoenable_flags; 6384 } 6385 } 6386 6387 for (i = 0; i < ARRAY_SIZE(feature_dependencies); i++) { 6388 FeatureDep *d = &feature_dependencies[i]; 6389 if (!(env->features[d->from.index] & d->from.mask)) { 6390 uint64_t unavailable_features = env->features[d->to.index] & d->to.mask; 6391 6392 /* Not an error unless the dependent feature was added explicitly. */ 6393 mark_unavailable_features(cpu, d->to.index, 6394 unavailable_features & env->user_features[d->to.index], 6395 "This feature depends on other features that were not requested"); 6396 6397 env->features[d->to.index] &= ~unavailable_features; 6398 } 6399 } 6400 6401 if (!kvm_enabled() || !cpu->expose_kvm) { 6402 env->features[FEAT_KVM] = 0; 6403 } 6404 6405 x86_cpu_enable_xsave_components(cpu); 6406 6407 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */ 6408 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX); 6409 if (cpu->full_cpuid_auto_level) { 6410 x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX); 6411 x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX); 6412 x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX); 6413 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX); 6414 x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EAX); 6415 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX); 6416 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX); 6417 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX); 6418 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0008_EBX); 6419 x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX); 6420 x86_cpu_adjust_feat_level(cpu, FEAT_SVM); 6421 x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE); 6422 6423 /* Intel Processor Trace requires CPUID[0x14] */ 6424 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT)) { 6425 if (cpu->intel_pt_auto_level) { 6426 x86_cpu_adjust_level(cpu, &cpu->env.cpuid_min_level, 0x14); 6427 } else if (cpu->env.cpuid_min_level < 0x14) { 6428 mark_unavailable_features(cpu, FEAT_7_0_EBX, 6429 CPUID_7_0_EBX_INTEL_PT, 6430 "Intel PT need CPUID leaf 0x14, please set by \"-cpu ...,intel-pt=on,min-level=0x14\""); 6431 } 6432 } 6433 6434 /* 6435 * Intel CPU topology with multi-dies support requires CPUID[0x1F]. 6436 * For AMD Rome/Milan, cpuid level is 0x10, and guest OS should detect 6437 * extended toplogy by leaf 0xB. Only adjust it for Intel CPU, unless 6438 * cpu->vendor_cpuid_only has been unset for compatibility with older 6439 * machine types. 6440 */ 6441 if ((env->nr_dies > 1) && 6442 (IS_INTEL_CPU(env) || !cpu->vendor_cpuid_only)) { 6443 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x1F); 6444 } 6445 6446 /* SVM requires CPUID[0x8000000A] */ 6447 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { 6448 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A); 6449 } 6450 6451 /* SEV requires CPUID[0x8000001F] */ 6452 if (sev_enabled()) { 6453 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F); 6454 } 6455 6456 /* SGX requires CPUID[0x12] for EPC enumeration */ 6457 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX) { 6458 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x12); 6459 } 6460 } 6461 6462 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */ 6463 if (env->cpuid_level_func7 == UINT32_MAX) { 6464 env->cpuid_level_func7 = env->cpuid_min_level_func7; 6465 } 6466 if (env->cpuid_level == UINT32_MAX) { 6467 env->cpuid_level = env->cpuid_min_level; 6468 } 6469 if (env->cpuid_xlevel == UINT32_MAX) { 6470 env->cpuid_xlevel = env->cpuid_min_xlevel; 6471 } 6472 if (env->cpuid_xlevel2 == UINT32_MAX) { 6473 env->cpuid_xlevel2 = env->cpuid_min_xlevel2; 6474 } 6475 6476 if (kvm_enabled()) { 6477 kvm_hyperv_expand_features(cpu, errp); 6478 } 6479 } 6480 6481 /* 6482 * Finishes initialization of CPUID data, filters CPU feature 6483 * words based on host availability of each feature. 6484 * 6485 * Returns: 0 if all flags are supported by the host, non-zero otherwise. 6486 */ 6487 static void x86_cpu_filter_features(X86CPU *cpu, bool verbose) 6488 { 6489 CPUX86State *env = &cpu->env; 6490 FeatureWord w; 6491 const char *prefix = NULL; 6492 6493 if (verbose) { 6494 prefix = accel_uses_host_cpuid() 6495 ? "host doesn't support requested feature" 6496 : "TCG doesn't support requested feature"; 6497 } 6498 6499 for (w = 0; w < FEATURE_WORDS; w++) { 6500 uint64_t host_feat = 6501 x86_cpu_get_supported_feature_word(w, false); 6502 uint64_t requested_features = env->features[w]; 6503 uint64_t unavailable_features = requested_features & ~host_feat; 6504 mark_unavailable_features(cpu, w, unavailable_features, prefix); 6505 } 6506 6507 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) && 6508 kvm_enabled()) { 6509 KVMState *s = CPU(cpu)->kvm_state; 6510 uint32_t eax_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EAX); 6511 uint32_t ebx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EBX); 6512 uint32_t ecx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_ECX); 6513 uint32_t eax_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EAX); 6514 uint32_t ebx_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EBX); 6515 6516 if (!eax_0 || 6517 ((ebx_0 & INTEL_PT_MINIMAL_EBX) != INTEL_PT_MINIMAL_EBX) || 6518 ((ecx_0 & INTEL_PT_MINIMAL_ECX) != INTEL_PT_MINIMAL_ECX) || 6519 ((eax_1 & INTEL_PT_MTC_BITMAP) != INTEL_PT_MTC_BITMAP) || 6520 ((eax_1 & INTEL_PT_ADDR_RANGES_NUM_MASK) < 6521 INTEL_PT_ADDR_RANGES_NUM) || 6522 ((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) != 6523 (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) || 6524 ((ecx_0 & CPUID_14_0_ECX_LIP) != 6525 (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP))) { 6526 /* 6527 * Processor Trace capabilities aren't configurable, so if the 6528 * host can't emulate the capabilities we report on 6529 * cpu_x86_cpuid(), intel-pt can't be enabled on the current host. 6530 */ 6531 mark_unavailable_features(cpu, FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT, prefix); 6532 } 6533 } 6534 } 6535 6536 static void x86_cpu_hyperv_realize(X86CPU *cpu) 6537 { 6538 size_t len; 6539 6540 /* Hyper-V vendor id */ 6541 if (!cpu->hyperv_vendor) { 6542 object_property_set_str(OBJECT(cpu), "hv-vendor-id", "Microsoft Hv", 6543 &error_abort); 6544 } 6545 len = strlen(cpu->hyperv_vendor); 6546 if (len > 12) { 6547 warn_report("hv-vendor-id truncated to 12 characters"); 6548 len = 12; 6549 } 6550 memset(cpu->hyperv_vendor_id, 0, 12); 6551 memcpy(cpu->hyperv_vendor_id, cpu->hyperv_vendor, len); 6552 6553 /* 'Hv#1' interface identification*/ 6554 cpu->hyperv_interface_id[0] = 0x31237648; 6555 cpu->hyperv_interface_id[1] = 0; 6556 cpu->hyperv_interface_id[2] = 0; 6557 cpu->hyperv_interface_id[3] = 0; 6558 6559 /* Hypervisor implementation limits */ 6560 cpu->hyperv_limits[0] = 64; 6561 cpu->hyperv_limits[1] = 0; 6562 cpu->hyperv_limits[2] = 0; 6563 } 6564 6565 static void x86_cpu_realizefn(DeviceState *dev, Error **errp) 6566 { 6567 CPUState *cs = CPU(dev); 6568 X86CPU *cpu = X86_CPU(dev); 6569 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev); 6570 CPUX86State *env = &cpu->env; 6571 Error *local_err = NULL; 6572 static bool ht_warned; 6573 unsigned requested_lbr_fmt; 6574 6575 /* Use pc-relative instructions in system-mode */ 6576 #ifndef CONFIG_USER_ONLY 6577 cs->tcg_cflags |= CF_PCREL; 6578 #endif 6579 6580 if (cpu->apic_id == UNASSIGNED_APIC_ID) { 6581 error_setg(errp, "apic-id property was not initialized properly"); 6582 return; 6583 } 6584 6585 /* 6586 * Process Hyper-V enlightenments. 6587 * Note: this currently has to happen before the expansion of CPU features. 6588 */ 6589 x86_cpu_hyperv_realize(cpu); 6590 6591 x86_cpu_expand_features(cpu, &local_err); 6592 if (local_err) { 6593 goto out; 6594 } 6595 6596 /* 6597 * Override env->features[FEAT_PERF_CAPABILITIES].LBR_FMT 6598 * with user-provided setting. 6599 */ 6600 if (cpu->lbr_fmt != ~PERF_CAP_LBR_FMT) { 6601 if ((cpu->lbr_fmt & PERF_CAP_LBR_FMT) != cpu->lbr_fmt) { 6602 error_setg(errp, "invalid lbr-fmt"); 6603 return; 6604 } 6605 env->features[FEAT_PERF_CAPABILITIES] &= ~PERF_CAP_LBR_FMT; 6606 env->features[FEAT_PERF_CAPABILITIES] |= cpu->lbr_fmt; 6607 } 6608 6609 /* 6610 * vPMU LBR is supported when 1) KVM is enabled 2) Option pmu=on and 6611 * 3)vPMU LBR format matches that of host setting. 6612 */ 6613 requested_lbr_fmt = 6614 env->features[FEAT_PERF_CAPABILITIES] & PERF_CAP_LBR_FMT; 6615 if (requested_lbr_fmt && kvm_enabled()) { 6616 uint64_t host_perf_cap = 6617 x86_cpu_get_supported_feature_word(FEAT_PERF_CAPABILITIES, false); 6618 unsigned host_lbr_fmt = host_perf_cap & PERF_CAP_LBR_FMT; 6619 6620 if (!cpu->enable_pmu) { 6621 error_setg(errp, "vPMU: LBR is unsupported without pmu=on"); 6622 return; 6623 } 6624 if (requested_lbr_fmt != host_lbr_fmt) { 6625 error_setg(errp, "vPMU: the lbr-fmt value (0x%x) does not match " 6626 "the host value (0x%x).", 6627 requested_lbr_fmt, host_lbr_fmt); 6628 return; 6629 } 6630 } 6631 6632 x86_cpu_filter_features(cpu, cpu->check_cpuid || cpu->enforce_cpuid); 6633 6634 if (cpu->enforce_cpuid && x86_cpu_have_filtered_features(cpu)) { 6635 error_setg(&local_err, 6636 accel_uses_host_cpuid() ? 6637 "Host doesn't support requested features" : 6638 "TCG doesn't support requested features"); 6639 goto out; 6640 } 6641 6642 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on 6643 * CPUID[1].EDX. 6644 */ 6645 if (IS_AMD_CPU(env)) { 6646 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES; 6647 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX] 6648 & CPUID_EXT2_AMD_ALIASES); 6649 } 6650 6651 x86_cpu_set_sgxlepubkeyhash(env); 6652 6653 /* 6654 * note: the call to the framework needs to happen after feature expansion, 6655 * but before the checks/modifications to ucode_rev, mwait, phys_bits. 6656 * These may be set by the accel-specific code, 6657 * and the results are subsequently checked / assumed in this function. 6658 */ 6659 cpu_exec_realizefn(cs, &local_err); 6660 if (local_err != NULL) { 6661 error_propagate(errp, local_err); 6662 return; 6663 } 6664 6665 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) { 6666 g_autofree char *name = x86_cpu_class_get_model_name(xcc); 6667 error_setg(&local_err, "CPU model '%s' requires KVM or HVF", name); 6668 goto out; 6669 } 6670 6671 if (cpu->ucode_rev == 0) { 6672 /* 6673 * The default is the same as KVM's. Note that this check 6674 * needs to happen after the evenual setting of ucode_rev in 6675 * accel-specific code in cpu_exec_realizefn. 6676 */ 6677 if (IS_AMD_CPU(env)) { 6678 cpu->ucode_rev = 0x01000065; 6679 } else { 6680 cpu->ucode_rev = 0x100000000ULL; 6681 } 6682 } 6683 6684 /* 6685 * mwait extended info: needed for Core compatibility 6686 * We always wake on interrupt even if host does not have the capability. 6687 * 6688 * requires the accel-specific code in cpu_exec_realizefn to 6689 * have already acquired the CPUID data into cpu->mwait. 6690 */ 6691 cpu->mwait.ecx |= CPUID_MWAIT_EMX | CPUID_MWAIT_IBE; 6692 6693 /* For 64bit systems think about the number of physical bits to present. 6694 * ideally this should be the same as the host; anything other than matching 6695 * the host can cause incorrect guest behaviour. 6696 * QEMU used to pick the magic value of 40 bits that corresponds to 6697 * consumer AMD devices but nothing else. 6698 * 6699 * Note that this code assumes features expansion has already been done 6700 * (as it checks for CPUID_EXT2_LM), and also assumes that potential 6701 * phys_bits adjustments to match the host have been already done in 6702 * accel-specific code in cpu_exec_realizefn. 6703 */ 6704 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 6705 if (cpu->phys_bits && 6706 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS || 6707 cpu->phys_bits < 32)) { 6708 error_setg(errp, "phys-bits should be between 32 and %u " 6709 " (but is %u)", 6710 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits); 6711 return; 6712 } 6713 /* 6714 * 0 means it was not explicitly set by the user (or by machine 6715 * compat_props or by the host code in host-cpu.c). 6716 * In this case, the default is the value used by TCG (40). 6717 */ 6718 if (cpu->phys_bits == 0) { 6719 cpu->phys_bits = TCG_PHYS_ADDR_BITS; 6720 } 6721 } else { 6722 /* For 32 bit systems don't use the user set value, but keep 6723 * phys_bits consistent with what we tell the guest. 6724 */ 6725 if (cpu->phys_bits != 0) { 6726 error_setg(errp, "phys-bits is not user-configurable in 32 bit"); 6727 return; 6728 } 6729 6730 if (env->features[FEAT_1_EDX] & CPUID_PSE36) { 6731 cpu->phys_bits = 36; 6732 } else { 6733 cpu->phys_bits = 32; 6734 } 6735 } 6736 6737 /* Cache information initialization */ 6738 if (!cpu->legacy_cache) { 6739 if (!xcc->model || !xcc->model->cpudef->cache_info) { 6740 g_autofree char *name = x86_cpu_class_get_model_name(xcc); 6741 error_setg(errp, 6742 "CPU model '%s' doesn't support legacy-cache=off", name); 6743 return; 6744 } 6745 env->cache_info_cpuid2 = env->cache_info_cpuid4 = env->cache_info_amd = 6746 *xcc->model->cpudef->cache_info; 6747 } else { 6748 /* Build legacy cache information */ 6749 env->cache_info_cpuid2.l1d_cache = &legacy_l1d_cache; 6750 env->cache_info_cpuid2.l1i_cache = &legacy_l1i_cache; 6751 env->cache_info_cpuid2.l2_cache = &legacy_l2_cache_cpuid2; 6752 env->cache_info_cpuid2.l3_cache = &legacy_l3_cache; 6753 6754 env->cache_info_cpuid4.l1d_cache = &legacy_l1d_cache; 6755 env->cache_info_cpuid4.l1i_cache = &legacy_l1i_cache; 6756 env->cache_info_cpuid4.l2_cache = &legacy_l2_cache; 6757 env->cache_info_cpuid4.l3_cache = &legacy_l3_cache; 6758 6759 env->cache_info_amd.l1d_cache = &legacy_l1d_cache_amd; 6760 env->cache_info_amd.l1i_cache = &legacy_l1i_cache_amd; 6761 env->cache_info_amd.l2_cache = &legacy_l2_cache_amd; 6762 env->cache_info_amd.l3_cache = &legacy_l3_cache; 6763 } 6764 6765 #ifndef CONFIG_USER_ONLY 6766 MachineState *ms = MACHINE(qdev_get_machine()); 6767 qemu_register_reset(x86_cpu_machine_reset_cb, cpu); 6768 6769 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || ms->smp.cpus > 1) { 6770 x86_cpu_apic_create(cpu, &local_err); 6771 if (local_err != NULL) { 6772 goto out; 6773 } 6774 } 6775 #endif 6776 6777 mce_init(cpu); 6778 6779 qemu_init_vcpu(cs); 6780 6781 /* 6782 * Most Intel and certain AMD CPUs support hyperthreading. Even though QEMU 6783 * fixes this issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX 6784 * based on inputs (sockets,cores,threads), it is still better to give 6785 * users a warning. 6786 * 6787 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise 6788 * cs->nr_threads hasn't be populated yet and the checking is incorrect. 6789 */ 6790 if (IS_AMD_CPU(env) && 6791 !(env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) && 6792 cs->nr_threads > 1 && !ht_warned) { 6793 warn_report("This family of AMD CPU doesn't support " 6794 "hyperthreading(%d)", 6795 cs->nr_threads); 6796 error_printf("Please configure -smp options properly" 6797 " or try enabling topoext feature.\n"); 6798 ht_warned = true; 6799 } 6800 6801 #ifndef CONFIG_USER_ONLY 6802 x86_cpu_apic_realize(cpu, &local_err); 6803 if (local_err != NULL) { 6804 goto out; 6805 } 6806 #endif /* !CONFIG_USER_ONLY */ 6807 cpu_reset(cs); 6808 6809 xcc->parent_realize(dev, &local_err); 6810 6811 out: 6812 if (local_err != NULL) { 6813 error_propagate(errp, local_err); 6814 return; 6815 } 6816 } 6817 6818 static void x86_cpu_unrealizefn(DeviceState *dev) 6819 { 6820 X86CPU *cpu = X86_CPU(dev); 6821 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev); 6822 6823 #ifndef CONFIG_USER_ONLY 6824 cpu_remove_sync(CPU(dev)); 6825 qemu_unregister_reset(x86_cpu_machine_reset_cb, dev); 6826 #endif 6827 6828 if (cpu->apic_state) { 6829 object_unparent(OBJECT(cpu->apic_state)); 6830 cpu->apic_state = NULL; 6831 } 6832 6833 xcc->parent_unrealize(dev); 6834 } 6835 6836 typedef struct BitProperty { 6837 FeatureWord w; 6838 uint64_t mask; 6839 } BitProperty; 6840 6841 static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name, 6842 void *opaque, Error **errp) 6843 { 6844 X86CPU *cpu = X86_CPU(obj); 6845 BitProperty *fp = opaque; 6846 uint64_t f = cpu->env.features[fp->w]; 6847 bool value = (f & fp->mask) == fp->mask; 6848 visit_type_bool(v, name, &value, errp); 6849 } 6850 6851 static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name, 6852 void *opaque, Error **errp) 6853 { 6854 DeviceState *dev = DEVICE(obj); 6855 X86CPU *cpu = X86_CPU(obj); 6856 BitProperty *fp = opaque; 6857 bool value; 6858 6859 if (dev->realized) { 6860 qdev_prop_set_after_realize(dev, name, errp); 6861 return; 6862 } 6863 6864 if (!visit_type_bool(v, name, &value, errp)) { 6865 return; 6866 } 6867 6868 if (value) { 6869 cpu->env.features[fp->w] |= fp->mask; 6870 } else { 6871 cpu->env.features[fp->w] &= ~fp->mask; 6872 } 6873 cpu->env.user_features[fp->w] |= fp->mask; 6874 } 6875 6876 /* Register a boolean property to get/set a single bit in a uint32_t field. 6877 * 6878 * The same property name can be registered multiple times to make it affect 6879 * multiple bits in the same FeatureWord. In that case, the getter will return 6880 * true only if all bits are set. 6881 */ 6882 static void x86_cpu_register_bit_prop(X86CPUClass *xcc, 6883 const char *prop_name, 6884 FeatureWord w, 6885 int bitnr) 6886 { 6887 ObjectClass *oc = OBJECT_CLASS(xcc); 6888 BitProperty *fp; 6889 ObjectProperty *op; 6890 uint64_t mask = (1ULL << bitnr); 6891 6892 op = object_class_property_find(oc, prop_name); 6893 if (op) { 6894 fp = op->opaque; 6895 assert(fp->w == w); 6896 fp->mask |= mask; 6897 } else { 6898 fp = g_new0(BitProperty, 1); 6899 fp->w = w; 6900 fp->mask = mask; 6901 object_class_property_add(oc, prop_name, "bool", 6902 x86_cpu_get_bit_prop, 6903 x86_cpu_set_bit_prop, 6904 NULL, fp); 6905 } 6906 } 6907 6908 static void x86_cpu_register_feature_bit_props(X86CPUClass *xcc, 6909 FeatureWord w, 6910 int bitnr) 6911 { 6912 FeatureWordInfo *fi = &feature_word_info[w]; 6913 const char *name = fi->feat_names[bitnr]; 6914 6915 if (!name) { 6916 return; 6917 } 6918 6919 /* Property names should use "-" instead of "_". 6920 * Old names containing underscores are registered as aliases 6921 * using object_property_add_alias() 6922 */ 6923 assert(!strchr(name, '_')); 6924 /* aliases don't use "|" delimiters anymore, they are registered 6925 * manually using object_property_add_alias() */ 6926 assert(!strchr(name, '|')); 6927 x86_cpu_register_bit_prop(xcc, name, w, bitnr); 6928 } 6929 6930 static void x86_cpu_post_initfn(Object *obj) 6931 { 6932 accel_cpu_instance_init(CPU(obj)); 6933 } 6934 6935 static void x86_cpu_initfn(Object *obj) 6936 { 6937 X86CPU *cpu = X86_CPU(obj); 6938 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj); 6939 CPUX86State *env = &cpu->env; 6940 6941 env->nr_dies = 1; 6942 cpu_set_cpustate_pointers(cpu); 6943 6944 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo", 6945 x86_cpu_get_feature_words, 6946 NULL, NULL, (void *)env->features); 6947 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo", 6948 x86_cpu_get_feature_words, 6949 NULL, NULL, (void *)cpu->filtered_features); 6950 6951 object_property_add_alias(obj, "sse3", obj, "pni"); 6952 object_property_add_alias(obj, "pclmuldq", obj, "pclmulqdq"); 6953 object_property_add_alias(obj, "sse4-1", obj, "sse4.1"); 6954 object_property_add_alias(obj, "sse4-2", obj, "sse4.2"); 6955 object_property_add_alias(obj, "xd", obj, "nx"); 6956 object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt"); 6957 object_property_add_alias(obj, "i64", obj, "lm"); 6958 6959 object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl"); 6960 object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust"); 6961 object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt"); 6962 object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm"); 6963 object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy"); 6964 object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr"); 6965 object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core"); 6966 object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb"); 6967 object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay"); 6968 object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu"); 6969 object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf"); 6970 object_property_add_alias(obj, "kvm_asyncpf_int", obj, "kvm-asyncpf-int"); 6971 object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time"); 6972 object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi"); 6973 object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt"); 6974 object_property_add_alias(obj, "kvm_poll_control", obj, "kvm-poll-control"); 6975 object_property_add_alias(obj, "svm_lock", obj, "svm-lock"); 6976 object_property_add_alias(obj, "nrip_save", obj, "nrip-save"); 6977 object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale"); 6978 object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean"); 6979 object_property_add_alias(obj, "pause_filter", obj, "pause-filter"); 6980 object_property_add_alias(obj, "sse4_1", obj, "sse4.1"); 6981 object_property_add_alias(obj, "sse4_2", obj, "sse4.2"); 6982 6983 object_property_add_alias(obj, "hv-apicv", obj, "hv-avic"); 6984 cpu->lbr_fmt = ~PERF_CAP_LBR_FMT; 6985 object_property_add_alias(obj, "lbr_fmt", obj, "lbr-fmt"); 6986 6987 if (xcc->model) { 6988 x86_cpu_load_model(cpu, xcc->model); 6989 } 6990 } 6991 6992 static int64_t x86_cpu_get_arch_id(CPUState *cs) 6993 { 6994 X86CPU *cpu = X86_CPU(cs); 6995 6996 return cpu->apic_id; 6997 } 6998 6999 #if !defined(CONFIG_USER_ONLY) 7000 static bool x86_cpu_get_paging_enabled(const CPUState *cs) 7001 { 7002 X86CPU *cpu = X86_CPU(cs); 7003 7004 return cpu->env.cr[0] & CR0_PG_MASK; 7005 } 7006 #endif /* !CONFIG_USER_ONLY */ 7007 7008 static void x86_cpu_set_pc(CPUState *cs, vaddr value) 7009 { 7010 X86CPU *cpu = X86_CPU(cs); 7011 7012 cpu->env.eip = value; 7013 } 7014 7015 static vaddr x86_cpu_get_pc(CPUState *cs) 7016 { 7017 X86CPU *cpu = X86_CPU(cs); 7018 7019 /* Match cpu_get_tb_cpu_state. */ 7020 return cpu->env.eip + cpu->env.segs[R_CS].base; 7021 } 7022 7023 int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request) 7024 { 7025 X86CPU *cpu = X86_CPU(cs); 7026 CPUX86State *env = &cpu->env; 7027 7028 #if !defined(CONFIG_USER_ONLY) 7029 if (interrupt_request & CPU_INTERRUPT_POLL) { 7030 return CPU_INTERRUPT_POLL; 7031 } 7032 #endif 7033 if (interrupt_request & CPU_INTERRUPT_SIPI) { 7034 return CPU_INTERRUPT_SIPI; 7035 } 7036 7037 if (env->hflags2 & HF2_GIF_MASK) { 7038 if ((interrupt_request & CPU_INTERRUPT_SMI) && 7039 !(env->hflags & HF_SMM_MASK)) { 7040 return CPU_INTERRUPT_SMI; 7041 } else if ((interrupt_request & CPU_INTERRUPT_NMI) && 7042 !(env->hflags2 & HF2_NMI_MASK)) { 7043 return CPU_INTERRUPT_NMI; 7044 } else if (interrupt_request & CPU_INTERRUPT_MCE) { 7045 return CPU_INTERRUPT_MCE; 7046 } else if ((interrupt_request & CPU_INTERRUPT_HARD) && 7047 (((env->hflags2 & HF2_VINTR_MASK) && 7048 (env->hflags2 & HF2_HIF_MASK)) || 7049 (!(env->hflags2 & HF2_VINTR_MASK) && 7050 (env->eflags & IF_MASK && 7051 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) { 7052 return CPU_INTERRUPT_HARD; 7053 #if !defined(CONFIG_USER_ONLY) 7054 } else if (env->hflags2 & HF2_VGIF_MASK) { 7055 if((interrupt_request & CPU_INTERRUPT_VIRQ) && 7056 (env->eflags & IF_MASK) && 7057 !(env->hflags & HF_INHIBIT_IRQ_MASK)) { 7058 return CPU_INTERRUPT_VIRQ; 7059 } 7060 #endif 7061 } 7062 } 7063 7064 return 0; 7065 } 7066 7067 static bool x86_cpu_has_work(CPUState *cs) 7068 { 7069 return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0; 7070 } 7071 7072 static void x86_disas_set_info(CPUState *cs, disassemble_info *info) 7073 { 7074 X86CPU *cpu = X86_CPU(cs); 7075 CPUX86State *env = &cpu->env; 7076 7077 info->mach = (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64 7078 : env->hflags & HF_CS32_MASK ? bfd_mach_i386_i386 7079 : bfd_mach_i386_i8086); 7080 7081 info->cap_arch = CS_ARCH_X86; 7082 info->cap_mode = (env->hflags & HF_CS64_MASK ? CS_MODE_64 7083 : env->hflags & HF_CS32_MASK ? CS_MODE_32 7084 : CS_MODE_16); 7085 info->cap_insn_unit = 1; 7086 info->cap_insn_split = 8; 7087 } 7088 7089 void x86_update_hflags(CPUX86State *env) 7090 { 7091 uint32_t hflags; 7092 #define HFLAG_COPY_MASK \ 7093 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \ 7094 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \ 7095 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \ 7096 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK) 7097 7098 hflags = env->hflags & HFLAG_COPY_MASK; 7099 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK; 7100 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT); 7101 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) & 7102 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK); 7103 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK)); 7104 7105 if (env->cr[4] & CR4_OSFXSR_MASK) { 7106 hflags |= HF_OSFXSR_MASK; 7107 } 7108 7109 if (env->efer & MSR_EFER_LMA) { 7110 hflags |= HF_LMA_MASK; 7111 } 7112 7113 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) { 7114 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; 7115 } else { 7116 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >> 7117 (DESC_B_SHIFT - HF_CS32_SHIFT); 7118 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >> 7119 (DESC_B_SHIFT - HF_SS32_SHIFT); 7120 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) || 7121 !(hflags & HF_CS32_MASK)) { 7122 hflags |= HF_ADDSEG_MASK; 7123 } else { 7124 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base | 7125 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT; 7126 } 7127 } 7128 env->hflags = hflags; 7129 } 7130 7131 static Property x86_cpu_properties[] = { 7132 #ifdef CONFIG_USER_ONLY 7133 /* apic_id = 0 by default for *-user, see commit 9886e834 */ 7134 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0), 7135 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0), 7136 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0), 7137 DEFINE_PROP_INT32("die-id", X86CPU, die_id, 0), 7138 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0), 7139 #else 7140 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID), 7141 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1), 7142 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1), 7143 DEFINE_PROP_INT32("die-id", X86CPU, die_id, -1), 7144 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1), 7145 #endif 7146 DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID), 7147 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false), 7148 DEFINE_PROP_UINT64_CHECKMASK("lbr-fmt", X86CPU, lbr_fmt, PERF_CAP_LBR_FMT), 7149 7150 DEFINE_PROP_UINT32("hv-spinlocks", X86CPU, hyperv_spinlock_attempts, 7151 HYPERV_SPINLOCK_NEVER_NOTIFY), 7152 DEFINE_PROP_BIT64("hv-relaxed", X86CPU, hyperv_features, 7153 HYPERV_FEAT_RELAXED, 0), 7154 DEFINE_PROP_BIT64("hv-vapic", X86CPU, hyperv_features, 7155 HYPERV_FEAT_VAPIC, 0), 7156 DEFINE_PROP_BIT64("hv-time", X86CPU, hyperv_features, 7157 HYPERV_FEAT_TIME, 0), 7158 DEFINE_PROP_BIT64("hv-crash", X86CPU, hyperv_features, 7159 HYPERV_FEAT_CRASH, 0), 7160 DEFINE_PROP_BIT64("hv-reset", X86CPU, hyperv_features, 7161 HYPERV_FEAT_RESET, 0), 7162 DEFINE_PROP_BIT64("hv-vpindex", X86CPU, hyperv_features, 7163 HYPERV_FEAT_VPINDEX, 0), 7164 DEFINE_PROP_BIT64("hv-runtime", X86CPU, hyperv_features, 7165 HYPERV_FEAT_RUNTIME, 0), 7166 DEFINE_PROP_BIT64("hv-synic", X86CPU, hyperv_features, 7167 HYPERV_FEAT_SYNIC, 0), 7168 DEFINE_PROP_BIT64("hv-stimer", X86CPU, hyperv_features, 7169 HYPERV_FEAT_STIMER, 0), 7170 DEFINE_PROP_BIT64("hv-frequencies", X86CPU, hyperv_features, 7171 HYPERV_FEAT_FREQUENCIES, 0), 7172 DEFINE_PROP_BIT64("hv-reenlightenment", X86CPU, hyperv_features, 7173 HYPERV_FEAT_REENLIGHTENMENT, 0), 7174 DEFINE_PROP_BIT64("hv-tlbflush", X86CPU, hyperv_features, 7175 HYPERV_FEAT_TLBFLUSH, 0), 7176 DEFINE_PROP_BIT64("hv-evmcs", X86CPU, hyperv_features, 7177 HYPERV_FEAT_EVMCS, 0), 7178 DEFINE_PROP_BIT64("hv-ipi", X86CPU, hyperv_features, 7179 HYPERV_FEAT_IPI, 0), 7180 DEFINE_PROP_BIT64("hv-stimer-direct", X86CPU, hyperv_features, 7181 HYPERV_FEAT_STIMER_DIRECT, 0), 7182 DEFINE_PROP_BIT64("hv-avic", X86CPU, hyperv_features, 7183 HYPERV_FEAT_AVIC, 0), 7184 DEFINE_PROP_BIT64("hv-emsr-bitmap", X86CPU, hyperv_features, 7185 HYPERV_FEAT_MSR_BITMAP, 0), 7186 DEFINE_PROP_BIT64("hv-xmm-input", X86CPU, hyperv_features, 7187 HYPERV_FEAT_XMM_INPUT, 0), 7188 DEFINE_PROP_BIT64("hv-tlbflush-ext", X86CPU, hyperv_features, 7189 HYPERV_FEAT_TLBFLUSH_EXT, 0), 7190 DEFINE_PROP_BIT64("hv-tlbflush-direct", X86CPU, hyperv_features, 7191 HYPERV_FEAT_TLBFLUSH_DIRECT, 0), 7192 DEFINE_PROP_ON_OFF_AUTO("hv-no-nonarch-coresharing", X86CPU, 7193 hyperv_no_nonarch_cs, ON_OFF_AUTO_OFF), 7194 DEFINE_PROP_BIT64("hv-syndbg", X86CPU, hyperv_features, 7195 HYPERV_FEAT_SYNDBG, 0), 7196 DEFINE_PROP_BOOL("hv-passthrough", X86CPU, hyperv_passthrough, false), 7197 DEFINE_PROP_BOOL("hv-enforce-cpuid", X86CPU, hyperv_enforce_cpuid, false), 7198 7199 /* WS2008R2 identify by default */ 7200 DEFINE_PROP_UINT32("hv-version-id-build", X86CPU, hyperv_ver_id_build, 7201 0x3839), 7202 DEFINE_PROP_UINT16("hv-version-id-major", X86CPU, hyperv_ver_id_major, 7203 0x000A), 7204 DEFINE_PROP_UINT16("hv-version-id-minor", X86CPU, hyperv_ver_id_minor, 7205 0x0000), 7206 DEFINE_PROP_UINT32("hv-version-id-spack", X86CPU, hyperv_ver_id_sp, 0), 7207 DEFINE_PROP_UINT8("hv-version-id-sbranch", X86CPU, hyperv_ver_id_sb, 0), 7208 DEFINE_PROP_UINT32("hv-version-id-snumber", X86CPU, hyperv_ver_id_sn, 0), 7209 7210 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true), 7211 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false), 7212 DEFINE_PROP_BOOL("x-force-features", X86CPU, force_features, false), 7213 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true), 7214 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0), 7215 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false), 7216 DEFINE_PROP_UINT8("host-phys-bits-limit", X86CPU, host_phys_bits_limit, 0), 7217 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true), 7218 DEFINE_PROP_UINT32("level-func7", X86CPU, env.cpuid_level_func7, 7219 UINT32_MAX), 7220 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX), 7221 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX), 7222 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX), 7223 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0), 7224 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0), 7225 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0), 7226 DEFINE_PROP_UINT64("ucode-rev", X86CPU, ucode_rev, 0), 7227 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true), 7228 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor), 7229 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true), 7230 DEFINE_PROP_BOOL("x-vendor-cpuid-only", X86CPU, vendor_cpuid_only, true), 7231 DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false), 7232 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true), 7233 DEFINE_PROP_BOOL("kvm-no-smi-migration", X86CPU, kvm_no_smi_migration, 7234 false), 7235 DEFINE_PROP_BOOL("kvm-pv-enforce-cpuid", X86CPU, kvm_pv_enforce_cpuid, 7236 false), 7237 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true), 7238 DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true), 7239 DEFINE_PROP_BOOL("x-migrate-smi-count", X86CPU, migrate_smi_count, 7240 true), 7241 /* 7242 * lecacy_cache defaults to true unless the CPU model provides its 7243 * own cache information (see x86_cpu_load_def()). 7244 */ 7245 DEFINE_PROP_BOOL("legacy-cache", X86CPU, legacy_cache, true), 7246 DEFINE_PROP_BOOL("xen-vapic", X86CPU, xen_vapic, false), 7247 7248 /* 7249 * From "Requirements for Implementing the Microsoft 7250 * Hypervisor Interface": 7251 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs 7252 * 7253 * "Starting with Windows Server 2012 and Windows 8, if 7254 * CPUID.40000005.EAX contains a value of -1, Windows assumes that 7255 * the hypervisor imposes no specific limit to the number of VPs. 7256 * In this case, Windows Server 2012 guest VMs may use more than 7257 * 64 VPs, up to the maximum supported number of processors applicable 7258 * to the specific Windows version being used." 7259 */ 7260 DEFINE_PROP_INT32("x-hv-max-vps", X86CPU, hv_max_vps, -1), 7261 DEFINE_PROP_BOOL("x-hv-synic-kvm-only", X86CPU, hyperv_synic_kvm_only, 7262 false), 7263 DEFINE_PROP_BOOL("x-intel-pt-auto-level", X86CPU, intel_pt_auto_level, 7264 true), 7265 DEFINE_PROP_END_OF_LIST() 7266 }; 7267 7268 #ifndef CONFIG_USER_ONLY 7269 #include "hw/core/sysemu-cpu-ops.h" 7270 7271 static const struct SysemuCPUOps i386_sysemu_ops = { 7272 .get_memory_mapping = x86_cpu_get_memory_mapping, 7273 .get_paging_enabled = x86_cpu_get_paging_enabled, 7274 .get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug, 7275 .asidx_from_attrs = x86_asidx_from_attrs, 7276 .get_crash_info = x86_cpu_get_crash_info, 7277 .write_elf32_note = x86_cpu_write_elf32_note, 7278 .write_elf64_note = x86_cpu_write_elf64_note, 7279 .write_elf32_qemunote = x86_cpu_write_elf32_qemunote, 7280 .write_elf64_qemunote = x86_cpu_write_elf64_qemunote, 7281 .legacy_vmsd = &vmstate_x86_cpu, 7282 }; 7283 #endif 7284 7285 static void x86_cpu_common_class_init(ObjectClass *oc, void *data) 7286 { 7287 X86CPUClass *xcc = X86_CPU_CLASS(oc); 7288 CPUClass *cc = CPU_CLASS(oc); 7289 DeviceClass *dc = DEVICE_CLASS(oc); 7290 ResettableClass *rc = RESETTABLE_CLASS(oc); 7291 FeatureWord w; 7292 7293 device_class_set_parent_realize(dc, x86_cpu_realizefn, 7294 &xcc->parent_realize); 7295 device_class_set_parent_unrealize(dc, x86_cpu_unrealizefn, 7296 &xcc->parent_unrealize); 7297 device_class_set_props(dc, x86_cpu_properties); 7298 7299 resettable_class_set_parent_phases(rc, NULL, x86_cpu_reset_hold, NULL, 7300 &xcc->parent_phases); 7301 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP; 7302 7303 cc->class_by_name = x86_cpu_class_by_name; 7304 cc->parse_features = x86_cpu_parse_featurestr; 7305 cc->has_work = x86_cpu_has_work; 7306 cc->dump_state = x86_cpu_dump_state; 7307 cc->set_pc = x86_cpu_set_pc; 7308 cc->get_pc = x86_cpu_get_pc; 7309 cc->gdb_read_register = x86_cpu_gdb_read_register; 7310 cc->gdb_write_register = x86_cpu_gdb_write_register; 7311 cc->get_arch_id = x86_cpu_get_arch_id; 7312 7313 #ifndef CONFIG_USER_ONLY 7314 cc->sysemu_ops = &i386_sysemu_ops; 7315 #endif /* !CONFIG_USER_ONLY */ 7316 7317 cc->gdb_arch_name = x86_gdb_arch_name; 7318 #ifdef TARGET_X86_64 7319 cc->gdb_core_xml_file = "i386-64bit.xml"; 7320 cc->gdb_num_core_regs = 66; 7321 #else 7322 cc->gdb_core_xml_file = "i386-32bit.xml"; 7323 cc->gdb_num_core_regs = 50; 7324 #endif 7325 cc->disas_set_info = x86_disas_set_info; 7326 7327 dc->user_creatable = true; 7328 7329 object_class_property_add(oc, "family", "int", 7330 x86_cpuid_version_get_family, 7331 x86_cpuid_version_set_family, NULL, NULL); 7332 object_class_property_add(oc, "model", "int", 7333 x86_cpuid_version_get_model, 7334 x86_cpuid_version_set_model, NULL, NULL); 7335 object_class_property_add(oc, "stepping", "int", 7336 x86_cpuid_version_get_stepping, 7337 x86_cpuid_version_set_stepping, NULL, NULL); 7338 object_class_property_add_str(oc, "vendor", 7339 x86_cpuid_get_vendor, 7340 x86_cpuid_set_vendor); 7341 object_class_property_add_str(oc, "model-id", 7342 x86_cpuid_get_model_id, 7343 x86_cpuid_set_model_id); 7344 object_class_property_add(oc, "tsc-frequency", "int", 7345 x86_cpuid_get_tsc_freq, 7346 x86_cpuid_set_tsc_freq, NULL, NULL); 7347 /* 7348 * The "unavailable-features" property has the same semantics as 7349 * CpuDefinitionInfo.unavailable-features on the "query-cpu-definitions" 7350 * QMP command: they list the features that would have prevented the 7351 * CPU from running if the "enforce" flag was set. 7352 */ 7353 object_class_property_add(oc, "unavailable-features", "strList", 7354 x86_cpu_get_unavailable_features, 7355 NULL, NULL, NULL); 7356 7357 #if !defined(CONFIG_USER_ONLY) 7358 object_class_property_add(oc, "crash-information", "GuestPanicInformation", 7359 x86_cpu_get_crash_info_qom, NULL, NULL, NULL); 7360 #endif 7361 7362 for (w = 0; w < FEATURE_WORDS; w++) { 7363 int bitnr; 7364 for (bitnr = 0; bitnr < 64; bitnr++) { 7365 x86_cpu_register_feature_bit_props(xcc, w, bitnr); 7366 } 7367 } 7368 } 7369 7370 static const TypeInfo x86_cpu_type_info = { 7371 .name = TYPE_X86_CPU, 7372 .parent = TYPE_CPU, 7373 .instance_size = sizeof(X86CPU), 7374 .instance_init = x86_cpu_initfn, 7375 .instance_post_init = x86_cpu_post_initfn, 7376 7377 .abstract = true, 7378 .class_size = sizeof(X86CPUClass), 7379 .class_init = x86_cpu_common_class_init, 7380 }; 7381 7382 /* "base" CPU model, used by query-cpu-model-expansion */ 7383 static void x86_cpu_base_class_init(ObjectClass *oc, void *data) 7384 { 7385 X86CPUClass *xcc = X86_CPU_CLASS(oc); 7386 7387 xcc->static_model = true; 7388 xcc->migration_safe = true; 7389 xcc->model_description = "base CPU model type with no features enabled"; 7390 xcc->ordering = 8; 7391 } 7392 7393 static const TypeInfo x86_base_cpu_type_info = { 7394 .name = X86_CPU_TYPE_NAME("base"), 7395 .parent = TYPE_X86_CPU, 7396 .class_init = x86_cpu_base_class_init, 7397 }; 7398 7399 static void x86_cpu_register_types(void) 7400 { 7401 int i; 7402 7403 type_register_static(&x86_cpu_type_info); 7404 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) { 7405 x86_register_cpudef_types(&builtin_x86_defs[i]); 7406 } 7407 type_register_static(&max_x86_cpu_type_info); 7408 type_register_static(&x86_base_cpu_type_info); 7409 } 7410 7411 type_init(x86_cpu_register_types) 7412