1 /* 2 * i386 CPUID, CPU class, definitions, models 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/units.h" 22 #include "qemu/cutils.h" 23 #include "qemu/qemu-print.h" 24 #include "qemu/hw-version.h" 25 #include "cpu.h" 26 #include "tcg/helper-tcg.h" 27 #include "sysemu/hvf.h" 28 #include "hvf/hvf-i386.h" 29 #include "kvm/kvm_i386.h" 30 #include "sev.h" 31 #include "qapi/error.h" 32 #include "qemu/error-report.h" 33 #include "qapi/qapi-visit-machine.h" 34 #include "qapi/qmp/qerror.h" 35 #include "standard-headers/asm-x86/kvm_para.h" 36 #include "hw/qdev-properties.h" 37 #include "hw/i386/topology.h" 38 #ifndef CONFIG_USER_ONLY 39 #include "sysemu/reset.h" 40 #include "qapi/qapi-commands-machine-target.h" 41 #include "exec/address-spaces.h" 42 #include "hw/boards.h" 43 #include "hw/i386/sgx-epc.h" 44 #endif 45 46 #include "disas/capstone.h" 47 #include "cpu-internal.h" 48 49 static void x86_cpu_realizefn(DeviceState *dev, Error **errp); 50 51 /* Helpers for building CPUID[2] descriptors: */ 52 53 struct CPUID2CacheDescriptorInfo { 54 enum CacheType type; 55 int level; 56 int size; 57 int line_size; 58 int associativity; 59 }; 60 61 /* 62 * Known CPUID 2 cache descriptors. 63 * From Intel SDM Volume 2A, CPUID instruction 64 */ 65 struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = { 66 [0x06] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 8 * KiB, 67 .associativity = 4, .line_size = 32, }, 68 [0x08] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 16 * KiB, 69 .associativity = 4, .line_size = 32, }, 70 [0x09] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB, 71 .associativity = 4, .line_size = 64, }, 72 [0x0A] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB, 73 .associativity = 2, .line_size = 32, }, 74 [0x0C] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 75 .associativity = 4, .line_size = 32, }, 76 [0x0D] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 77 .associativity = 4, .line_size = 64, }, 78 [0x0E] = { .level = 1, .type = DATA_CACHE, .size = 24 * KiB, 79 .associativity = 6, .line_size = 64, }, 80 [0x1D] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB, 81 .associativity = 2, .line_size = 64, }, 82 [0x21] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 83 .associativity = 8, .line_size = 64, }, 84 /* lines per sector is not supported cpuid2_cache_descriptor(), 85 * so descriptors 0x22, 0x23 are not included 86 */ 87 [0x24] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 88 .associativity = 16, .line_size = 64, }, 89 /* lines per sector is not supported cpuid2_cache_descriptor(), 90 * so descriptors 0x25, 0x20 are not included 91 */ 92 [0x2C] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB, 93 .associativity = 8, .line_size = 64, }, 94 [0x30] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB, 95 .associativity = 8, .line_size = 64, }, 96 [0x41] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB, 97 .associativity = 4, .line_size = 32, }, 98 [0x42] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 99 .associativity = 4, .line_size = 32, }, 100 [0x43] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 101 .associativity = 4, .line_size = 32, }, 102 [0x44] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 103 .associativity = 4, .line_size = 32, }, 104 [0x45] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 105 .associativity = 4, .line_size = 32, }, 106 [0x46] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 107 .associativity = 4, .line_size = 64, }, 108 [0x47] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 109 .associativity = 8, .line_size = 64, }, 110 [0x48] = { .level = 2, .type = UNIFIED_CACHE, .size = 3 * MiB, 111 .associativity = 12, .line_size = 64, }, 112 /* Descriptor 0x49 depends on CPU family/model, so it is not included */ 113 [0x4A] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB, 114 .associativity = 12, .line_size = 64, }, 115 [0x4B] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 116 .associativity = 16, .line_size = 64, }, 117 [0x4C] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB, 118 .associativity = 12, .line_size = 64, }, 119 [0x4D] = { .level = 3, .type = UNIFIED_CACHE, .size = 16 * MiB, 120 .associativity = 16, .line_size = 64, }, 121 [0x4E] = { .level = 2, .type = UNIFIED_CACHE, .size = 6 * MiB, 122 .associativity = 24, .line_size = 64, }, 123 [0x60] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 124 .associativity = 8, .line_size = 64, }, 125 [0x66] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB, 126 .associativity = 4, .line_size = 64, }, 127 [0x67] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 128 .associativity = 4, .line_size = 64, }, 129 [0x68] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB, 130 .associativity = 4, .line_size = 64, }, 131 [0x78] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 132 .associativity = 4, .line_size = 64, }, 133 /* lines per sector is not supported cpuid2_cache_descriptor(), 134 * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included. 135 */ 136 [0x7D] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 137 .associativity = 8, .line_size = 64, }, 138 [0x7F] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 139 .associativity = 2, .line_size = 64, }, 140 [0x80] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 141 .associativity = 8, .line_size = 64, }, 142 [0x82] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 143 .associativity = 8, .line_size = 32, }, 144 [0x83] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 145 .associativity = 8, .line_size = 32, }, 146 [0x84] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 147 .associativity = 8, .line_size = 32, }, 148 [0x85] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 149 .associativity = 8, .line_size = 32, }, 150 [0x86] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 151 .associativity = 4, .line_size = 64, }, 152 [0x87] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 153 .associativity = 8, .line_size = 64, }, 154 [0xD0] = { .level = 3, .type = UNIFIED_CACHE, .size = 512 * KiB, 155 .associativity = 4, .line_size = 64, }, 156 [0xD1] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB, 157 .associativity = 4, .line_size = 64, }, 158 [0xD2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 159 .associativity = 4, .line_size = 64, }, 160 [0xD6] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB, 161 .associativity = 8, .line_size = 64, }, 162 [0xD7] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 163 .associativity = 8, .line_size = 64, }, 164 [0xD8] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 165 .associativity = 8, .line_size = 64, }, 166 [0xDC] = { .level = 3, .type = UNIFIED_CACHE, .size = 1.5 * MiB, 167 .associativity = 12, .line_size = 64, }, 168 [0xDD] = { .level = 3, .type = UNIFIED_CACHE, .size = 3 * MiB, 169 .associativity = 12, .line_size = 64, }, 170 [0xDE] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB, 171 .associativity = 12, .line_size = 64, }, 172 [0xE2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 173 .associativity = 16, .line_size = 64, }, 174 [0xE3] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 175 .associativity = 16, .line_size = 64, }, 176 [0xE4] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 177 .associativity = 16, .line_size = 64, }, 178 [0xEA] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB, 179 .associativity = 24, .line_size = 64, }, 180 [0xEB] = { .level = 3, .type = UNIFIED_CACHE, .size = 18 * MiB, 181 .associativity = 24, .line_size = 64, }, 182 [0xEC] = { .level = 3, .type = UNIFIED_CACHE, .size = 24 * MiB, 183 .associativity = 24, .line_size = 64, }, 184 }; 185 186 /* 187 * "CPUID leaf 2 does not report cache descriptor information, 188 * use CPUID leaf 4 to query cache parameters" 189 */ 190 #define CACHE_DESCRIPTOR_UNAVAILABLE 0xFF 191 192 /* 193 * Return a CPUID 2 cache descriptor for a given cache. 194 * If no known descriptor is found, return CACHE_DESCRIPTOR_UNAVAILABLE 195 */ 196 static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache) 197 { 198 int i; 199 200 assert(cache->size > 0); 201 assert(cache->level > 0); 202 assert(cache->line_size > 0); 203 assert(cache->associativity > 0); 204 for (i = 0; i < ARRAY_SIZE(cpuid2_cache_descriptors); i++) { 205 struct CPUID2CacheDescriptorInfo *d = &cpuid2_cache_descriptors[i]; 206 if (d->level == cache->level && d->type == cache->type && 207 d->size == cache->size && d->line_size == cache->line_size && 208 d->associativity == cache->associativity) { 209 return i; 210 } 211 } 212 213 return CACHE_DESCRIPTOR_UNAVAILABLE; 214 } 215 216 /* CPUID Leaf 4 constants: */ 217 218 /* EAX: */ 219 #define CACHE_TYPE_D 1 220 #define CACHE_TYPE_I 2 221 #define CACHE_TYPE_UNIFIED 3 222 223 #define CACHE_LEVEL(l) (l << 5) 224 225 #define CACHE_SELF_INIT_LEVEL (1 << 8) 226 227 /* EDX: */ 228 #define CACHE_NO_INVD_SHARING (1 << 0) 229 #define CACHE_INCLUSIVE (1 << 1) 230 #define CACHE_COMPLEX_IDX (1 << 2) 231 232 /* Encode CacheType for CPUID[4].EAX */ 233 #define CACHE_TYPE(t) (((t) == DATA_CACHE) ? CACHE_TYPE_D : \ 234 ((t) == INSTRUCTION_CACHE) ? CACHE_TYPE_I : \ 235 ((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \ 236 0 /* Invalid value */) 237 238 static uint32_t max_thread_ids_for_cache(X86CPUTopoInfo *topo_info, 239 enum CPUTopoLevel share_level) 240 { 241 uint32_t num_ids = 0; 242 243 switch (share_level) { 244 case CPU_TOPO_LEVEL_CORE: 245 num_ids = 1 << apicid_core_offset(topo_info); 246 break; 247 case CPU_TOPO_LEVEL_DIE: 248 num_ids = 1 << apicid_die_offset(topo_info); 249 break; 250 case CPU_TOPO_LEVEL_PACKAGE: 251 num_ids = 1 << apicid_pkg_offset(topo_info); 252 break; 253 default: 254 /* 255 * Currently there is no use case for SMT and MODULE, so use 256 * assert directly to facilitate debugging. 257 */ 258 g_assert_not_reached(); 259 } 260 261 return num_ids - 1; 262 } 263 264 static uint32_t max_core_ids_in_package(X86CPUTopoInfo *topo_info) 265 { 266 uint32_t num_cores = 1 << (apicid_pkg_offset(topo_info) - 267 apicid_core_offset(topo_info)); 268 return num_cores - 1; 269 } 270 271 /* Encode cache info for CPUID[4] */ 272 static void encode_cache_cpuid4(CPUCacheInfo *cache, 273 X86CPUTopoInfo *topo_info, 274 uint32_t *eax, uint32_t *ebx, 275 uint32_t *ecx, uint32_t *edx) 276 { 277 assert(cache->size == cache->line_size * cache->associativity * 278 cache->partitions * cache->sets); 279 280 *eax = CACHE_TYPE(cache->type) | 281 CACHE_LEVEL(cache->level) | 282 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) | 283 (max_core_ids_in_package(topo_info) << 26) | 284 (max_thread_ids_for_cache(topo_info, cache->share_level) << 14); 285 286 assert(cache->line_size > 0); 287 assert(cache->partitions > 0); 288 assert(cache->associativity > 0); 289 /* We don't implement fully-associative caches */ 290 assert(cache->associativity < cache->sets); 291 *ebx = (cache->line_size - 1) | 292 ((cache->partitions - 1) << 12) | 293 ((cache->associativity - 1) << 22); 294 295 assert(cache->sets > 0); 296 *ecx = cache->sets - 1; 297 298 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) | 299 (cache->inclusive ? CACHE_INCLUSIVE : 0) | 300 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); 301 } 302 303 static uint32_t num_threads_by_topo_level(X86CPUTopoInfo *topo_info, 304 enum CPUTopoLevel topo_level) 305 { 306 switch (topo_level) { 307 case CPU_TOPO_LEVEL_SMT: 308 return 1; 309 case CPU_TOPO_LEVEL_CORE: 310 return topo_info->threads_per_core; 311 case CPU_TOPO_LEVEL_MODULE: 312 return topo_info->threads_per_core * topo_info->cores_per_module; 313 case CPU_TOPO_LEVEL_DIE: 314 return topo_info->threads_per_core * topo_info->cores_per_module * 315 topo_info->modules_per_die; 316 case CPU_TOPO_LEVEL_PACKAGE: 317 return topo_info->threads_per_core * topo_info->cores_per_module * 318 topo_info->modules_per_die * topo_info->dies_per_pkg; 319 default: 320 g_assert_not_reached(); 321 } 322 return 0; 323 } 324 325 static uint32_t apicid_offset_by_topo_level(X86CPUTopoInfo *topo_info, 326 enum CPUTopoLevel topo_level) 327 { 328 switch (topo_level) { 329 case CPU_TOPO_LEVEL_SMT: 330 return 0; 331 case CPU_TOPO_LEVEL_CORE: 332 return apicid_core_offset(topo_info); 333 case CPU_TOPO_LEVEL_MODULE: 334 return apicid_module_offset(topo_info); 335 case CPU_TOPO_LEVEL_DIE: 336 return apicid_die_offset(topo_info); 337 case CPU_TOPO_LEVEL_PACKAGE: 338 return apicid_pkg_offset(topo_info); 339 default: 340 g_assert_not_reached(); 341 } 342 return 0; 343 } 344 345 static uint32_t cpuid1f_topo_type(enum CPUTopoLevel topo_level) 346 { 347 switch (topo_level) { 348 case CPU_TOPO_LEVEL_INVALID: 349 return CPUID_1F_ECX_TOPO_LEVEL_INVALID; 350 case CPU_TOPO_LEVEL_SMT: 351 return CPUID_1F_ECX_TOPO_LEVEL_SMT; 352 case CPU_TOPO_LEVEL_CORE: 353 return CPUID_1F_ECX_TOPO_LEVEL_CORE; 354 case CPU_TOPO_LEVEL_MODULE: 355 return CPUID_1F_ECX_TOPO_LEVEL_MODULE; 356 case CPU_TOPO_LEVEL_DIE: 357 return CPUID_1F_ECX_TOPO_LEVEL_DIE; 358 default: 359 /* Other types are not supported in QEMU. */ 360 g_assert_not_reached(); 361 } 362 return 0; 363 } 364 365 static void encode_topo_cpuid1f(CPUX86State *env, uint32_t count, 366 X86CPUTopoInfo *topo_info, 367 uint32_t *eax, uint32_t *ebx, 368 uint32_t *ecx, uint32_t *edx) 369 { 370 X86CPU *cpu = env_archcpu(env); 371 unsigned long level, next_level; 372 uint32_t num_threads_next_level, offset_next_level; 373 374 assert(count + 1 < CPU_TOPO_LEVEL_MAX); 375 376 /* 377 * Find the No.(count + 1) topology level in avail_cpu_topo bitmap. 378 * The search starts from bit 1 (CPU_TOPO_LEVEL_INVALID + 1). 379 */ 380 level = CPU_TOPO_LEVEL_INVALID; 381 for (int i = 0; i <= count; i++) { 382 level = find_next_bit(env->avail_cpu_topo, 383 CPU_TOPO_LEVEL_PACKAGE, 384 level + 1); 385 386 /* 387 * CPUID[0x1f] doesn't explicitly encode the package level, 388 * and it just encodes the invalid level (all fields are 0) 389 * into the last subleaf of 0x1f. 390 */ 391 if (level == CPU_TOPO_LEVEL_PACKAGE) { 392 level = CPU_TOPO_LEVEL_INVALID; 393 break; 394 } 395 } 396 397 if (level == CPU_TOPO_LEVEL_INVALID) { 398 num_threads_next_level = 0; 399 offset_next_level = 0; 400 } else { 401 next_level = find_next_bit(env->avail_cpu_topo, 402 CPU_TOPO_LEVEL_PACKAGE, 403 level + 1); 404 num_threads_next_level = num_threads_by_topo_level(topo_info, 405 next_level); 406 offset_next_level = apicid_offset_by_topo_level(topo_info, 407 next_level); 408 } 409 410 *eax = offset_next_level; 411 /* The count (bits 15-00) doesn't need to be reliable. */ 412 *ebx = num_threads_next_level & 0xffff; 413 *ecx = (count & 0xff) | (cpuid1f_topo_type(level) << 8); 414 *edx = cpu->apic_id; 415 416 assert(!(*eax & ~0x1f)); 417 } 418 419 /* Encode cache info for CPUID[0x80000005].ECX or CPUID[0x80000005].EDX */ 420 static uint32_t encode_cache_cpuid80000005(CPUCacheInfo *cache) 421 { 422 assert(cache->size % 1024 == 0); 423 assert(cache->lines_per_tag > 0); 424 assert(cache->associativity > 0); 425 assert(cache->line_size > 0); 426 return ((cache->size / 1024) << 24) | (cache->associativity << 16) | 427 (cache->lines_per_tag << 8) | (cache->line_size); 428 } 429 430 #define ASSOC_FULL 0xFF 431 432 /* AMD associativity encoding used on CPUID Leaf 0x80000006: */ 433 #define AMD_ENC_ASSOC(a) (a <= 1 ? a : \ 434 a == 2 ? 0x2 : \ 435 a == 4 ? 0x4 : \ 436 a == 8 ? 0x6 : \ 437 a == 16 ? 0x8 : \ 438 a == 32 ? 0xA : \ 439 a == 48 ? 0xB : \ 440 a == 64 ? 0xC : \ 441 a == 96 ? 0xD : \ 442 a == 128 ? 0xE : \ 443 a == ASSOC_FULL ? 0xF : \ 444 0 /* invalid value */) 445 446 /* 447 * Encode cache info for CPUID[0x80000006].ECX and CPUID[0x80000006].EDX 448 * @l3 can be NULL. 449 */ 450 static void encode_cache_cpuid80000006(CPUCacheInfo *l2, 451 CPUCacheInfo *l3, 452 uint32_t *ecx, uint32_t *edx) 453 { 454 assert(l2->size % 1024 == 0); 455 assert(l2->associativity > 0); 456 assert(l2->lines_per_tag > 0); 457 assert(l2->line_size > 0); 458 *ecx = ((l2->size / 1024) << 16) | 459 (AMD_ENC_ASSOC(l2->associativity) << 12) | 460 (l2->lines_per_tag << 8) | (l2->line_size); 461 462 if (l3) { 463 assert(l3->size % (512 * 1024) == 0); 464 assert(l3->associativity > 0); 465 assert(l3->lines_per_tag > 0); 466 assert(l3->line_size > 0); 467 *edx = ((l3->size / (512 * 1024)) << 18) | 468 (AMD_ENC_ASSOC(l3->associativity) << 12) | 469 (l3->lines_per_tag << 8) | (l3->line_size); 470 } else { 471 *edx = 0; 472 } 473 } 474 475 /* Encode cache info for CPUID[8000001D] */ 476 static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, 477 X86CPUTopoInfo *topo_info, 478 uint32_t *eax, uint32_t *ebx, 479 uint32_t *ecx, uint32_t *edx) 480 { 481 assert(cache->size == cache->line_size * cache->associativity * 482 cache->partitions * cache->sets); 483 484 *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) | 485 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0); 486 *eax |= max_thread_ids_for_cache(topo_info, cache->share_level) << 14; 487 488 assert(cache->line_size > 0); 489 assert(cache->partitions > 0); 490 assert(cache->associativity > 0); 491 /* We don't implement fully-associative caches */ 492 assert(cache->associativity < cache->sets); 493 *ebx = (cache->line_size - 1) | 494 ((cache->partitions - 1) << 12) | 495 ((cache->associativity - 1) << 22); 496 497 assert(cache->sets > 0); 498 *ecx = cache->sets - 1; 499 500 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) | 501 (cache->inclusive ? CACHE_INCLUSIVE : 0) | 502 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); 503 } 504 505 /* Encode cache info for CPUID[8000001E] */ 506 static void encode_topo_cpuid8000001e(X86CPU *cpu, X86CPUTopoInfo *topo_info, 507 uint32_t *eax, uint32_t *ebx, 508 uint32_t *ecx, uint32_t *edx) 509 { 510 X86CPUTopoIDs topo_ids; 511 512 x86_topo_ids_from_apicid(cpu->apic_id, topo_info, &topo_ids); 513 514 *eax = cpu->apic_id; 515 516 /* 517 * CPUID_Fn8000001E_EBX [Core Identifiers] (CoreId) 518 * Read-only. Reset: 0000_XXXXh. 519 * See Core::X86::Cpuid::ExtApicId. 520 * Core::X86::Cpuid::CoreId_lthree[1:0]_core[3:0]_thread[1:0]; 521 * Bits Description 522 * 31:16 Reserved. 523 * 15:8 ThreadsPerCore: threads per core. Read-only. Reset: XXh. 524 * The number of threads per core is ThreadsPerCore+1. 525 * 7:0 CoreId: core ID. Read-only. Reset: XXh. 526 * 527 * NOTE: CoreId is already part of apic_id. Just use it. We can 528 * use all the 8 bits to represent the core_id here. 529 */ 530 *ebx = ((topo_info->threads_per_core - 1) << 8) | (topo_ids.core_id & 0xFF); 531 532 /* 533 * CPUID_Fn8000001E_ECX [Node Identifiers] (NodeId) 534 * Read-only. Reset: 0000_0XXXh. 535 * Core::X86::Cpuid::NodeId_lthree[1:0]_core[3:0]_thread[1:0]; 536 * Bits Description 537 * 31:11 Reserved. 538 * 10:8 NodesPerProcessor: Node per processor. Read-only. Reset: XXXb. 539 * ValidValues: 540 * Value Description 541 * 0h 1 node per processor. 542 * 7h-1h Reserved. 543 * 7:0 NodeId: Node ID. Read-only. Reset: XXh. 544 * 545 * NOTE: Hardware reserves 3 bits for number of nodes per processor. 546 * But users can create more nodes than the actual hardware can 547 * support. To genaralize we can use all the upper 8 bits for nodes. 548 * NodeId is combination of node and socket_id which is already decoded 549 * in apic_id. Just use it by shifting. 550 */ 551 if (cpu->legacy_multi_node) { 552 *ecx = ((topo_info->dies_per_pkg - 1) << 8) | 553 ((cpu->apic_id >> apicid_die_offset(topo_info)) & 0xFF); 554 } else { 555 *ecx = (cpu->apic_id >> apicid_pkg_offset(topo_info)) & 0xFF; 556 } 557 558 *edx = 0; 559 } 560 561 /* 562 * Definitions of the hardcoded cache entries we expose: 563 * These are legacy cache values. If there is a need to change any 564 * of these values please use builtin_x86_defs 565 */ 566 567 /* L1 data cache: */ 568 static CPUCacheInfo legacy_l1d_cache = { 569 .type = DATA_CACHE, 570 .level = 1, 571 .size = 32 * KiB, 572 .self_init = 1, 573 .line_size = 64, 574 .associativity = 8, 575 .sets = 64, 576 .partitions = 1, 577 .no_invd_sharing = true, 578 .share_level = CPU_TOPO_LEVEL_CORE, 579 }; 580 581 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ 582 static CPUCacheInfo legacy_l1d_cache_amd = { 583 .type = DATA_CACHE, 584 .level = 1, 585 .size = 64 * KiB, 586 .self_init = 1, 587 .line_size = 64, 588 .associativity = 2, 589 .sets = 512, 590 .partitions = 1, 591 .lines_per_tag = 1, 592 .no_invd_sharing = true, 593 .share_level = CPU_TOPO_LEVEL_CORE, 594 }; 595 596 /* L1 instruction cache: */ 597 static CPUCacheInfo legacy_l1i_cache = { 598 .type = INSTRUCTION_CACHE, 599 .level = 1, 600 .size = 32 * KiB, 601 .self_init = 1, 602 .line_size = 64, 603 .associativity = 8, 604 .sets = 64, 605 .partitions = 1, 606 .no_invd_sharing = true, 607 .share_level = CPU_TOPO_LEVEL_CORE, 608 }; 609 610 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ 611 static CPUCacheInfo legacy_l1i_cache_amd = { 612 .type = INSTRUCTION_CACHE, 613 .level = 1, 614 .size = 64 * KiB, 615 .self_init = 1, 616 .line_size = 64, 617 .associativity = 2, 618 .sets = 512, 619 .partitions = 1, 620 .lines_per_tag = 1, 621 .no_invd_sharing = true, 622 .share_level = CPU_TOPO_LEVEL_CORE, 623 }; 624 625 /* Level 2 unified cache: */ 626 static CPUCacheInfo legacy_l2_cache = { 627 .type = UNIFIED_CACHE, 628 .level = 2, 629 .size = 4 * MiB, 630 .self_init = 1, 631 .line_size = 64, 632 .associativity = 16, 633 .sets = 4096, 634 .partitions = 1, 635 .no_invd_sharing = true, 636 .share_level = CPU_TOPO_LEVEL_CORE, 637 }; 638 639 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */ 640 static CPUCacheInfo legacy_l2_cache_cpuid2 = { 641 .type = UNIFIED_CACHE, 642 .level = 2, 643 .size = 2 * MiB, 644 .line_size = 64, 645 .associativity = 8, 646 .share_level = CPU_TOPO_LEVEL_INVALID, 647 }; 648 649 650 /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */ 651 static CPUCacheInfo legacy_l2_cache_amd = { 652 .type = UNIFIED_CACHE, 653 .level = 2, 654 .size = 512 * KiB, 655 .line_size = 64, 656 .lines_per_tag = 1, 657 .associativity = 16, 658 .sets = 512, 659 .partitions = 1, 660 .share_level = CPU_TOPO_LEVEL_CORE, 661 }; 662 663 /* Level 3 unified cache: */ 664 static CPUCacheInfo legacy_l3_cache = { 665 .type = UNIFIED_CACHE, 666 .level = 3, 667 .size = 16 * MiB, 668 .line_size = 64, 669 .associativity = 16, 670 .sets = 16384, 671 .partitions = 1, 672 .lines_per_tag = 1, 673 .self_init = true, 674 .inclusive = true, 675 .complex_indexing = true, 676 .share_level = CPU_TOPO_LEVEL_DIE, 677 }; 678 679 /* TLB definitions: */ 680 681 #define L1_DTLB_2M_ASSOC 1 682 #define L1_DTLB_2M_ENTRIES 255 683 #define L1_DTLB_4K_ASSOC 1 684 #define L1_DTLB_4K_ENTRIES 255 685 686 #define L1_ITLB_2M_ASSOC 1 687 #define L1_ITLB_2M_ENTRIES 255 688 #define L1_ITLB_4K_ASSOC 1 689 #define L1_ITLB_4K_ENTRIES 255 690 691 #define L2_DTLB_2M_ASSOC 0 /* disabled */ 692 #define L2_DTLB_2M_ENTRIES 0 /* disabled */ 693 #define L2_DTLB_4K_ASSOC 4 694 #define L2_DTLB_4K_ENTRIES 512 695 696 #define L2_ITLB_2M_ASSOC 0 /* disabled */ 697 #define L2_ITLB_2M_ENTRIES 0 /* disabled */ 698 #define L2_ITLB_4K_ASSOC 4 699 #define L2_ITLB_4K_ENTRIES 512 700 701 /* CPUID Leaf 0x14 constants: */ 702 #define INTEL_PT_MAX_SUBLEAF 0x1 703 /* 704 * bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MATCH 705 * MSR can be accessed; 706 * bit[01]: Support Configurable PSB and Cycle-Accurate Mode; 707 * bit[02]: Support IP Filtering, TraceStop filtering, and preservation 708 * of Intel PT MSRs across warm reset; 709 * bit[03]: Support MTC timing packet and suppression of COFI-based packets; 710 */ 711 #define INTEL_PT_MINIMAL_EBX 0xf 712 /* 713 * bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 and 714 * IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be 715 * accessed; 716 * bit[01]: ToPA tables can hold any number of output entries, up to the 717 * maximum allowed by the MaskOrTableOffset field of 718 * IA32_RTIT_OUTPUT_MASK_PTRS; 719 * bit[02]: Support Single-Range Output scheme; 720 */ 721 #define INTEL_PT_MINIMAL_ECX 0x7 722 /* generated packets which contain IP payloads have LIP values */ 723 #define INTEL_PT_IP_LIP (1 << 31) 724 #define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */ 725 #define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3 726 #define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */ 727 #define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */ 728 #define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */ 729 730 /* CPUID Leaf 0x1D constants: */ 731 #define INTEL_AMX_TILE_MAX_SUBLEAF 0x1 732 #define INTEL_AMX_TOTAL_TILE_BYTES 0x2000 733 #define INTEL_AMX_BYTES_PER_TILE 0x400 734 #define INTEL_AMX_BYTES_PER_ROW 0x40 735 #define INTEL_AMX_TILE_MAX_NAMES 0x8 736 #define INTEL_AMX_TILE_MAX_ROWS 0x10 737 738 /* CPUID Leaf 0x1E constants: */ 739 #define INTEL_AMX_TMUL_MAX_K 0x10 740 #define INTEL_AMX_TMUL_MAX_N 0x40 741 742 void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1, 743 uint32_t vendor2, uint32_t vendor3) 744 { 745 int i; 746 for (i = 0; i < 4; i++) { 747 dst[i] = vendor1 >> (8 * i); 748 dst[i + 4] = vendor2 >> (8 * i); 749 dst[i + 8] = vendor3 >> (8 * i); 750 } 751 dst[CPUID_VENDOR_SZ] = '\0'; 752 } 753 754 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE) 755 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \ 756 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC) 757 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \ 758 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ 759 CPUID_PSE36 | CPUID_FXSR) 760 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE) 761 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \ 762 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \ 763 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \ 764 CPUID_PAE | CPUID_SEP | CPUID_APIC) 765 766 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \ 767 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \ 768 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ 769 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \ 770 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE) 771 /* partly implemented: 772 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */ 773 /* missing: 774 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */ 775 776 /* 777 * Kernel-only features that can be shown to usermode programs even if 778 * they aren't actually supported by TCG, because qemu-user only runs 779 * in CPL=3; remove them if they are ever implemented for system emulation. 780 */ 781 #if defined CONFIG_USER_ONLY 782 #define CPUID_EXT_KERNEL_FEATURES \ 783 (CPUID_EXT_PCID | CPUID_EXT_TSC_DEADLINE_TIMER) 784 #else 785 #define CPUID_EXT_KERNEL_FEATURES 0 786 #endif 787 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \ 788 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \ 789 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \ 790 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \ 791 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR | \ 792 CPUID_EXT_RDRAND | CPUID_EXT_AVX | CPUID_EXT_F16C | \ 793 CPUID_EXT_FMA | CPUID_EXT_X2APIC | CPUID_EXT_KERNEL_FEATURES) 794 /* missing: 795 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX, 796 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, 797 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA, 798 CPUID_EXT_TSC_DEADLINE_TIMER 799 */ 800 801 #ifdef TARGET_X86_64 802 #define TCG_EXT2_X86_64_FEATURES CPUID_EXT2_LM 803 #else 804 #define TCG_EXT2_X86_64_FEATURES 0 805 #endif 806 807 /* 808 * CPUID_*_KERNEL_FEATURES denotes bits and features that are not usable 809 * in usermode or by 32-bit programs. Those are added to supported 810 * TCG features unconditionally in user-mode emulation mode. This may 811 * indeed seem strange or incorrect, but it works because code running 812 * under usermode emulation cannot access them. 813 * 814 * Even for long mode, qemu-i386 is not running "a userspace program on a 815 * 32-bit CPU"; it's running "a userspace program with a 32-bit code segment" 816 * and therefore using the 32-bit ABI; the CPU itself might be 64-bit 817 * but again the difference is only visible in kernel mode. 818 */ 819 #if defined CONFIG_LINUX_USER 820 #define CPUID_EXT2_KERNEL_FEATURES (CPUID_EXT2_LM | CPUID_EXT2_FFXSR) 821 #elif defined CONFIG_USER_ONLY 822 /* FIXME: Long mode not yet supported for i386 bsd-user */ 823 #define CPUID_EXT2_KERNEL_FEATURES CPUID_EXT2_FFXSR 824 #else 825 #define CPUID_EXT2_KERNEL_FEATURES 0 826 #endif 827 828 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \ 829 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \ 830 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \ 831 CPUID_EXT2_SYSCALL | TCG_EXT2_X86_64_FEATURES | \ 832 CPUID_EXT2_KERNEL_FEATURES) 833 834 #if defined CONFIG_USER_ONLY 835 #define CPUID_EXT3_KERNEL_FEATURES CPUID_EXT3_OSVW 836 #else 837 #define CPUID_EXT3_KERNEL_FEATURES 0 838 #endif 839 840 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \ 841 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A | \ 842 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_KERNEL_FEATURES) 843 844 #define TCG_EXT4_FEATURES 0 845 846 #if defined CONFIG_USER_ONLY 847 #define CPUID_SVM_KERNEL_FEATURES (CPUID_SVM_NRIPSAVE | CPUID_SVM_VNMI) 848 #else 849 #define CPUID_SVM_KERNEL_FEATURES 0 850 #endif 851 #define TCG_SVM_FEATURES (CPUID_SVM_NPT | CPUID_SVM_VGIF | \ 852 CPUID_SVM_SVME_ADDR_CHK | CPUID_SVM_KERNEL_FEATURES) 853 854 #define TCG_KVM_FEATURES 0 855 856 #if defined CONFIG_USER_ONLY 857 #define CPUID_7_0_EBX_KERNEL_FEATURES CPUID_7_0_EBX_INVPCID 858 #else 859 #define CPUID_7_0_EBX_KERNEL_FEATURES 0 860 #endif 861 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \ 862 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \ 863 CPUID_7_0_EBX_CLFLUSHOPT | \ 864 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \ 865 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_RDSEED | \ 866 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_KERNEL_FEATURES) 867 /* missing: 868 CPUID_7_0_EBX_HLE 869 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM */ 870 871 #if !defined CONFIG_USER_ONLY || defined CONFIG_LINUX 872 #define TCG_7_0_ECX_RDPID CPUID_7_0_ECX_RDPID 873 #else 874 #define TCG_7_0_ECX_RDPID 0 875 #endif 876 #define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | \ 877 /* CPUID_7_0_ECX_OSPKE is dynamic */ \ 878 CPUID_7_0_ECX_LA57 | CPUID_7_0_ECX_PKS | CPUID_7_0_ECX_VAES | \ 879 TCG_7_0_ECX_RDPID) 880 881 #if defined CONFIG_USER_ONLY 882 #define CPUID_7_0_EDX_KERNEL_FEATURES (CPUID_7_0_EDX_SPEC_CTRL | \ 883 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD) 884 #else 885 #define CPUID_7_0_EDX_KERNEL_FEATURES 0 886 #endif 887 #define TCG_7_0_EDX_FEATURES (CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_KERNEL_FEATURES) 888 889 #define TCG_7_1_EAX_FEATURES (CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | \ 890 CPUID_7_1_EAX_FSRC | CPUID_7_1_EAX_CMPCCXADD) 891 #define TCG_7_1_EDX_FEATURES 0 892 #define TCG_7_2_EDX_FEATURES 0 893 #define TCG_APM_FEATURES 0 894 #define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT 895 #define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1) 896 /* missing: 897 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */ 898 #define TCG_14_0_ECX_FEATURES 0 899 #define TCG_SGX_12_0_EAX_FEATURES 0 900 #define TCG_SGX_12_0_EBX_FEATURES 0 901 #define TCG_SGX_12_1_EAX_FEATURES 0 902 903 #if defined CONFIG_USER_ONLY 904 #define CPUID_8000_0008_EBX_KERNEL_FEATURES (CPUID_8000_0008_EBX_IBPB | \ 905 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | \ 906 CPUID_8000_0008_EBX_STIBP_ALWAYS_ON | CPUID_8000_0008_EBX_AMD_SSBD | \ 907 CPUID_8000_0008_EBX_AMD_PSFD) 908 #else 909 #define CPUID_8000_0008_EBX_KERNEL_FEATURES 0 910 #endif 911 912 #define TCG_8000_0008_EBX (CPUID_8000_0008_EBX_XSAVEERPTR | \ 913 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_KERNEL_FEATURES) 914 915 FeatureWordInfo feature_word_info[FEATURE_WORDS] = { 916 [FEAT_1_EDX] = { 917 .type = CPUID_FEATURE_WORD, 918 .feat_names = { 919 "fpu", "vme", "de", "pse", 920 "tsc", "msr", "pae", "mce", 921 "cx8", "apic", NULL, "sep", 922 "mtrr", "pge", "mca", "cmov", 923 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */, 924 NULL, "ds" /* Intel dts */, "acpi", "mmx", 925 "fxsr", "sse", "sse2", "ss", 926 "ht" /* Intel htt */, "tm", "ia64", "pbe", 927 }, 928 .cpuid = {.eax = 1, .reg = R_EDX, }, 929 .tcg_features = TCG_FEATURES, 930 .no_autoenable_flags = CPUID_HT, 931 }, 932 [FEAT_1_ECX] = { 933 .type = CPUID_FEATURE_WORD, 934 .feat_names = { 935 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor", 936 "ds-cpl", "vmx", "smx", "est", 937 "tm2", "ssse3", "cid", NULL, 938 "fma", "cx16", "xtpr", "pdcm", 939 NULL, "pcid", "dca", "sse4.1", 940 "sse4.2", "x2apic", "movbe", "popcnt", 941 "tsc-deadline", "aes", "xsave", NULL /* osxsave */, 942 "avx", "f16c", "rdrand", "hypervisor", 943 }, 944 .cpuid = { .eax = 1, .reg = R_ECX, }, 945 .tcg_features = TCG_EXT_FEATURES, 946 }, 947 /* Feature names that are already defined on feature_name[] but 948 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their 949 * names on feat_names below. They are copied automatically 950 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD. 951 */ 952 [FEAT_8000_0001_EDX] = { 953 .type = CPUID_FEATURE_WORD, 954 .feat_names = { 955 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */, 956 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */, 957 NULL /* cx8 */, NULL /* apic */, NULL, "syscall", 958 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */, 959 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */, 960 "nx", NULL, "mmxext", NULL /* mmx */, 961 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp", 962 NULL, "lm", "3dnowext", "3dnow", 963 }, 964 .cpuid = { .eax = 0x80000001, .reg = R_EDX, }, 965 .tcg_features = TCG_EXT2_FEATURES, 966 }, 967 [FEAT_8000_0001_ECX] = { 968 .type = CPUID_FEATURE_WORD, 969 .feat_names = { 970 "lahf-lm", "cmp-legacy", "svm", "extapic", 971 "cr8legacy", "abm", "sse4a", "misalignsse", 972 "3dnowprefetch", "osvw", "ibs", "xop", 973 "skinit", "wdt", NULL, "lwp", 974 "fma4", "tce", NULL, "nodeid-msr", 975 NULL, "tbm", "topoext", "perfctr-core", 976 "perfctr-nb", NULL, NULL, NULL, 977 NULL, NULL, NULL, NULL, 978 }, 979 .cpuid = { .eax = 0x80000001, .reg = R_ECX, }, 980 .tcg_features = TCG_EXT3_FEATURES, 981 /* 982 * TOPOEXT is always allowed but can't be enabled blindly by 983 * "-cpu host", as it requires consistent cache topology info 984 * to be provided so it doesn't confuse guests. 985 */ 986 .no_autoenable_flags = CPUID_EXT3_TOPOEXT, 987 }, 988 [FEAT_C000_0001_EDX] = { 989 .type = CPUID_FEATURE_WORD, 990 .feat_names = { 991 NULL, NULL, "xstore", "xstore-en", 992 NULL, NULL, "xcrypt", "xcrypt-en", 993 "ace2", "ace2-en", "phe", "phe-en", 994 "pmm", "pmm-en", NULL, NULL, 995 NULL, NULL, NULL, NULL, 996 NULL, NULL, NULL, NULL, 997 NULL, NULL, NULL, NULL, 998 NULL, NULL, NULL, NULL, 999 }, 1000 .cpuid = { .eax = 0xC0000001, .reg = R_EDX, }, 1001 .tcg_features = TCG_EXT4_FEATURES, 1002 }, 1003 [FEAT_KVM] = { 1004 .type = CPUID_FEATURE_WORD, 1005 .feat_names = { 1006 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock", 1007 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt", 1008 NULL, "kvm-pv-tlb-flush", "kvm-asyncpf-vmexit", "kvm-pv-ipi", 1009 "kvm-poll-control", "kvm-pv-sched-yield", "kvm-asyncpf-int", "kvm-msi-ext-dest-id", 1010 NULL, NULL, NULL, NULL, 1011 NULL, NULL, NULL, NULL, 1012 "kvmclock-stable-bit", NULL, NULL, NULL, 1013 NULL, NULL, NULL, NULL, 1014 }, 1015 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EAX, }, 1016 .tcg_features = TCG_KVM_FEATURES, 1017 }, 1018 [FEAT_KVM_HINTS] = { 1019 .type = CPUID_FEATURE_WORD, 1020 .feat_names = { 1021 "kvm-hint-dedicated", NULL, NULL, NULL, 1022 NULL, NULL, NULL, NULL, 1023 NULL, NULL, NULL, NULL, 1024 NULL, NULL, NULL, NULL, 1025 NULL, NULL, NULL, NULL, 1026 NULL, NULL, NULL, NULL, 1027 NULL, NULL, NULL, NULL, 1028 NULL, NULL, NULL, NULL, 1029 }, 1030 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EDX, }, 1031 .tcg_features = TCG_KVM_FEATURES, 1032 /* 1033 * KVM hints aren't auto-enabled by -cpu host, they need to be 1034 * explicitly enabled in the command-line. 1035 */ 1036 .no_autoenable_flags = ~0U, 1037 }, 1038 [FEAT_SVM] = { 1039 .type = CPUID_FEATURE_WORD, 1040 .feat_names = { 1041 "npt", "lbrv", "svm-lock", "nrip-save", 1042 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists", 1043 NULL, NULL, "pause-filter", NULL, 1044 "pfthreshold", "avic", NULL, "v-vmsave-vmload", 1045 "vgif", NULL, NULL, NULL, 1046 NULL, NULL, NULL, NULL, 1047 NULL, "vnmi", NULL, NULL, 1048 "svme-addr-chk", NULL, NULL, NULL, 1049 }, 1050 .cpuid = { .eax = 0x8000000A, .reg = R_EDX, }, 1051 .tcg_features = TCG_SVM_FEATURES, 1052 }, 1053 [FEAT_7_0_EBX] = { 1054 .type = CPUID_FEATURE_WORD, 1055 .feat_names = { 1056 "fsgsbase", "tsc-adjust", "sgx", "bmi1", 1057 "hle", "avx2", NULL, "smep", 1058 "bmi2", "erms", "invpcid", "rtm", 1059 NULL, NULL, "mpx", NULL, 1060 "avx512f", "avx512dq", "rdseed", "adx", 1061 "smap", "avx512ifma", "pcommit", "clflushopt", 1062 "clwb", "intel-pt", "avx512pf", "avx512er", 1063 "avx512cd", "sha-ni", "avx512bw", "avx512vl", 1064 }, 1065 .cpuid = { 1066 .eax = 7, 1067 .needs_ecx = true, .ecx = 0, 1068 .reg = R_EBX, 1069 }, 1070 .tcg_features = TCG_7_0_EBX_FEATURES, 1071 }, 1072 [FEAT_7_0_ECX] = { 1073 .type = CPUID_FEATURE_WORD, 1074 .feat_names = { 1075 NULL, "avx512vbmi", "umip", "pku", 1076 NULL /* ospke */, "waitpkg", "avx512vbmi2", NULL, 1077 "gfni", "vaes", "vpclmulqdq", "avx512vnni", 1078 "avx512bitalg", NULL, "avx512-vpopcntdq", NULL, 1079 "la57", NULL, NULL, NULL, 1080 NULL, NULL, "rdpid", NULL, 1081 "bus-lock-detect", "cldemote", NULL, "movdiri", 1082 "movdir64b", NULL, "sgxlc", "pks", 1083 }, 1084 .cpuid = { 1085 .eax = 7, 1086 .needs_ecx = true, .ecx = 0, 1087 .reg = R_ECX, 1088 }, 1089 .tcg_features = TCG_7_0_ECX_FEATURES, 1090 }, 1091 [FEAT_7_0_EDX] = { 1092 .type = CPUID_FEATURE_WORD, 1093 .feat_names = { 1094 NULL, NULL, "avx512-4vnniw", "avx512-4fmaps", 1095 "fsrm", NULL, NULL, NULL, 1096 "avx512-vp2intersect", NULL, "md-clear", NULL, 1097 NULL, NULL, "serialize", NULL, 1098 "tsx-ldtrk", NULL, NULL /* pconfig */, "arch-lbr", 1099 NULL, NULL, "amx-bf16", "avx512-fp16", 1100 "amx-tile", "amx-int8", "spec-ctrl", "stibp", 1101 "flush-l1d", "arch-capabilities", "core-capability", "ssbd", 1102 }, 1103 .cpuid = { 1104 .eax = 7, 1105 .needs_ecx = true, .ecx = 0, 1106 .reg = R_EDX, 1107 }, 1108 .tcg_features = TCG_7_0_EDX_FEATURES, 1109 }, 1110 [FEAT_7_1_EAX] = { 1111 .type = CPUID_FEATURE_WORD, 1112 .feat_names = { 1113 NULL, NULL, NULL, NULL, 1114 "avx-vnni", "avx512-bf16", NULL, "cmpccxadd", 1115 NULL, NULL, "fzrm", "fsrs", 1116 "fsrc", NULL, NULL, NULL, 1117 NULL, "fred", "lkgs", "wrmsrns", 1118 NULL, "amx-fp16", NULL, "avx-ifma", 1119 NULL, NULL, "lam", NULL, 1120 NULL, NULL, NULL, NULL, 1121 }, 1122 .cpuid = { 1123 .eax = 7, 1124 .needs_ecx = true, .ecx = 1, 1125 .reg = R_EAX, 1126 }, 1127 .tcg_features = TCG_7_1_EAX_FEATURES, 1128 }, 1129 [FEAT_7_1_EDX] = { 1130 .type = CPUID_FEATURE_WORD, 1131 .feat_names = { 1132 NULL, NULL, NULL, NULL, 1133 "avx-vnni-int8", "avx-ne-convert", NULL, NULL, 1134 "amx-complex", NULL, NULL, NULL, 1135 NULL, NULL, "prefetchiti", NULL, 1136 NULL, NULL, NULL, NULL, 1137 NULL, NULL, NULL, NULL, 1138 NULL, NULL, NULL, NULL, 1139 NULL, NULL, NULL, NULL, 1140 }, 1141 .cpuid = { 1142 .eax = 7, 1143 .needs_ecx = true, .ecx = 1, 1144 .reg = R_EDX, 1145 }, 1146 .tcg_features = TCG_7_1_EDX_FEATURES, 1147 }, 1148 [FEAT_7_2_EDX] = { 1149 .type = CPUID_FEATURE_WORD, 1150 .feat_names = { 1151 NULL, NULL, NULL, NULL, 1152 NULL, "mcdt-no", NULL, NULL, 1153 NULL, NULL, NULL, NULL, 1154 NULL, NULL, NULL, NULL, 1155 NULL, NULL, NULL, NULL, 1156 NULL, NULL, NULL, NULL, 1157 NULL, NULL, NULL, NULL, 1158 NULL, NULL, NULL, NULL, 1159 }, 1160 .cpuid = { 1161 .eax = 7, 1162 .needs_ecx = true, .ecx = 2, 1163 .reg = R_EDX, 1164 }, 1165 .tcg_features = TCG_7_2_EDX_FEATURES, 1166 }, 1167 [FEAT_8000_0007_EDX] = { 1168 .type = CPUID_FEATURE_WORD, 1169 .feat_names = { 1170 NULL, NULL, NULL, NULL, 1171 NULL, NULL, NULL, NULL, 1172 "invtsc", NULL, NULL, NULL, 1173 NULL, NULL, NULL, NULL, 1174 NULL, NULL, NULL, NULL, 1175 NULL, NULL, NULL, NULL, 1176 NULL, NULL, NULL, NULL, 1177 NULL, NULL, NULL, NULL, 1178 }, 1179 .cpuid = { .eax = 0x80000007, .reg = R_EDX, }, 1180 .tcg_features = TCG_APM_FEATURES, 1181 .unmigratable_flags = CPUID_APM_INVTSC, 1182 }, 1183 [FEAT_8000_0008_EBX] = { 1184 .type = CPUID_FEATURE_WORD, 1185 .feat_names = { 1186 "clzero", NULL, "xsaveerptr", NULL, 1187 NULL, NULL, NULL, NULL, 1188 NULL, "wbnoinvd", NULL, NULL, 1189 "ibpb", NULL, "ibrs", "amd-stibp", 1190 NULL, "stibp-always-on", NULL, NULL, 1191 NULL, NULL, NULL, NULL, 1192 "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL, 1193 "amd-psfd", NULL, NULL, NULL, 1194 }, 1195 .cpuid = { .eax = 0x80000008, .reg = R_EBX, }, 1196 .tcg_features = TCG_8000_0008_EBX, 1197 .unmigratable_flags = 0, 1198 }, 1199 [FEAT_8000_0021_EAX] = { 1200 .type = CPUID_FEATURE_WORD, 1201 .feat_names = { 1202 "no-nested-data-bp", NULL, "lfence-always-serializing", NULL, 1203 NULL, NULL, "null-sel-clr-base", NULL, 1204 "auto-ibrs", NULL, NULL, NULL, 1205 NULL, NULL, NULL, NULL, 1206 NULL, NULL, NULL, NULL, 1207 NULL, NULL, NULL, NULL, 1208 NULL, NULL, NULL, NULL, 1209 NULL, NULL, NULL, NULL, 1210 }, 1211 .cpuid = { .eax = 0x80000021, .reg = R_EAX, }, 1212 .tcg_features = 0, 1213 .unmigratable_flags = 0, 1214 }, 1215 [FEAT_XSAVE] = { 1216 .type = CPUID_FEATURE_WORD, 1217 .feat_names = { 1218 "xsaveopt", "xsavec", "xgetbv1", "xsaves", 1219 "xfd", NULL, NULL, NULL, 1220 NULL, NULL, NULL, NULL, 1221 NULL, NULL, NULL, NULL, 1222 NULL, NULL, NULL, NULL, 1223 NULL, NULL, NULL, NULL, 1224 NULL, NULL, NULL, NULL, 1225 NULL, NULL, NULL, NULL, 1226 }, 1227 .cpuid = { 1228 .eax = 0xd, 1229 .needs_ecx = true, .ecx = 1, 1230 .reg = R_EAX, 1231 }, 1232 .tcg_features = TCG_XSAVE_FEATURES, 1233 }, 1234 [FEAT_XSAVE_XSS_LO] = { 1235 .type = CPUID_FEATURE_WORD, 1236 .feat_names = { 1237 NULL, NULL, NULL, NULL, 1238 NULL, NULL, NULL, NULL, 1239 NULL, NULL, NULL, NULL, 1240 NULL, NULL, NULL, NULL, 1241 NULL, NULL, NULL, NULL, 1242 NULL, NULL, NULL, NULL, 1243 NULL, NULL, NULL, NULL, 1244 NULL, NULL, NULL, NULL, 1245 }, 1246 .cpuid = { 1247 .eax = 0xD, 1248 .needs_ecx = true, 1249 .ecx = 1, 1250 .reg = R_ECX, 1251 }, 1252 }, 1253 [FEAT_XSAVE_XSS_HI] = { 1254 .type = CPUID_FEATURE_WORD, 1255 .cpuid = { 1256 .eax = 0xD, 1257 .needs_ecx = true, 1258 .ecx = 1, 1259 .reg = R_EDX 1260 }, 1261 }, 1262 [FEAT_6_EAX] = { 1263 .type = CPUID_FEATURE_WORD, 1264 .feat_names = { 1265 NULL, NULL, "arat", NULL, 1266 NULL, NULL, NULL, NULL, 1267 NULL, NULL, NULL, NULL, 1268 NULL, NULL, NULL, NULL, 1269 NULL, NULL, NULL, NULL, 1270 NULL, NULL, NULL, NULL, 1271 NULL, NULL, NULL, NULL, 1272 NULL, NULL, NULL, NULL, 1273 }, 1274 .cpuid = { .eax = 6, .reg = R_EAX, }, 1275 .tcg_features = TCG_6_EAX_FEATURES, 1276 }, 1277 [FEAT_XSAVE_XCR0_LO] = { 1278 .type = CPUID_FEATURE_WORD, 1279 .cpuid = { 1280 .eax = 0xD, 1281 .needs_ecx = true, .ecx = 0, 1282 .reg = R_EAX, 1283 }, 1284 .tcg_features = ~0U, 1285 .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK | 1286 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK | 1287 XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK | 1288 XSTATE_PKRU_MASK, 1289 }, 1290 [FEAT_XSAVE_XCR0_HI] = { 1291 .type = CPUID_FEATURE_WORD, 1292 .cpuid = { 1293 .eax = 0xD, 1294 .needs_ecx = true, .ecx = 0, 1295 .reg = R_EDX, 1296 }, 1297 .tcg_features = ~0U, 1298 }, 1299 /*Below are MSR exposed features*/ 1300 [FEAT_ARCH_CAPABILITIES] = { 1301 .type = MSR_FEATURE_WORD, 1302 .feat_names = { 1303 "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry", 1304 "ssb-no", "mds-no", "pschange-mc-no", "tsx-ctrl", 1305 "taa-no", NULL, NULL, NULL, 1306 NULL, "sbdr-ssdp-no", "fbsdp-no", "psdp-no", 1307 NULL, "fb-clear", NULL, NULL, 1308 NULL, NULL, NULL, NULL, 1309 "pbrsb-no", NULL, "gds-no", "rfds-no", 1310 "rfds-clear", NULL, NULL, NULL, 1311 }, 1312 .msr = { 1313 .index = MSR_IA32_ARCH_CAPABILITIES, 1314 }, 1315 /* 1316 * FEAT_ARCH_CAPABILITIES only affects a read-only MSR, which 1317 * cannot be read from user mode. Therefore, it has no impact 1318 > on any user-mode operation, and warnings about unsupported 1319 * features do not matter. 1320 */ 1321 .tcg_features = ~0U, 1322 }, 1323 [FEAT_CORE_CAPABILITY] = { 1324 .type = MSR_FEATURE_WORD, 1325 .feat_names = { 1326 NULL, NULL, NULL, NULL, 1327 NULL, "split-lock-detect", NULL, NULL, 1328 NULL, NULL, NULL, NULL, 1329 NULL, NULL, NULL, NULL, 1330 NULL, NULL, NULL, NULL, 1331 NULL, NULL, NULL, NULL, 1332 NULL, NULL, NULL, NULL, 1333 NULL, NULL, NULL, NULL, 1334 }, 1335 .msr = { 1336 .index = MSR_IA32_CORE_CAPABILITY, 1337 }, 1338 }, 1339 [FEAT_PERF_CAPABILITIES] = { 1340 .type = MSR_FEATURE_WORD, 1341 .feat_names = { 1342 NULL, NULL, NULL, NULL, 1343 NULL, NULL, NULL, NULL, 1344 NULL, NULL, NULL, NULL, 1345 NULL, "full-width-write", NULL, NULL, 1346 NULL, NULL, NULL, NULL, 1347 NULL, NULL, NULL, NULL, 1348 NULL, NULL, NULL, NULL, 1349 NULL, NULL, NULL, NULL, 1350 }, 1351 .msr = { 1352 .index = MSR_IA32_PERF_CAPABILITIES, 1353 }, 1354 }, 1355 1356 [FEAT_VMX_PROCBASED_CTLS] = { 1357 .type = MSR_FEATURE_WORD, 1358 .feat_names = { 1359 NULL, NULL, "vmx-vintr-pending", "vmx-tsc-offset", 1360 NULL, NULL, NULL, "vmx-hlt-exit", 1361 NULL, "vmx-invlpg-exit", "vmx-mwait-exit", "vmx-rdpmc-exit", 1362 "vmx-rdtsc-exit", NULL, NULL, "vmx-cr3-load-noexit", 1363 "vmx-cr3-store-noexit", NULL, NULL, "vmx-cr8-load-exit", 1364 "vmx-cr8-store-exit", "vmx-flexpriority", "vmx-vnmi-pending", "vmx-movdr-exit", 1365 "vmx-io-exit", "vmx-io-bitmap", NULL, "vmx-mtf", 1366 "vmx-msr-bitmap", "vmx-monitor-exit", "vmx-pause-exit", "vmx-secondary-ctls", 1367 }, 1368 .msr = { 1369 .index = MSR_IA32_VMX_TRUE_PROCBASED_CTLS, 1370 } 1371 }, 1372 1373 [FEAT_VMX_SECONDARY_CTLS] = { 1374 .type = MSR_FEATURE_WORD, 1375 .feat_names = { 1376 "vmx-apicv-xapic", "vmx-ept", "vmx-desc-exit", "vmx-rdtscp-exit", 1377 "vmx-apicv-x2apic", "vmx-vpid", "vmx-wbinvd-exit", "vmx-unrestricted-guest", 1378 "vmx-apicv-register", "vmx-apicv-vid", "vmx-ple", "vmx-rdrand-exit", 1379 "vmx-invpcid-exit", "vmx-vmfunc", "vmx-shadow-vmcs", "vmx-encls-exit", 1380 "vmx-rdseed-exit", "vmx-pml", NULL, NULL, 1381 "vmx-xsaves", NULL, NULL, NULL, 1382 NULL, "vmx-tsc-scaling", "vmx-enable-user-wait-pause", NULL, 1383 NULL, NULL, NULL, NULL, 1384 }, 1385 .msr = { 1386 .index = MSR_IA32_VMX_PROCBASED_CTLS2, 1387 } 1388 }, 1389 1390 [FEAT_VMX_PINBASED_CTLS] = { 1391 .type = MSR_FEATURE_WORD, 1392 .feat_names = { 1393 "vmx-intr-exit", NULL, NULL, "vmx-nmi-exit", 1394 NULL, "vmx-vnmi", "vmx-preemption-timer", "vmx-posted-intr", 1395 NULL, NULL, NULL, NULL, 1396 NULL, NULL, NULL, NULL, 1397 NULL, NULL, NULL, NULL, 1398 NULL, NULL, NULL, NULL, 1399 NULL, NULL, NULL, NULL, 1400 NULL, NULL, NULL, NULL, 1401 }, 1402 .msr = { 1403 .index = MSR_IA32_VMX_TRUE_PINBASED_CTLS, 1404 } 1405 }, 1406 1407 [FEAT_VMX_EXIT_CTLS] = { 1408 .type = MSR_FEATURE_WORD, 1409 /* 1410 * VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE is copied from 1411 * the LM CPUID bit. 1412 */ 1413 .feat_names = { 1414 NULL, NULL, "vmx-exit-nosave-debugctl", NULL, 1415 NULL, NULL, NULL, NULL, 1416 NULL, NULL /* vmx-exit-host-addr-space-size */, NULL, NULL, 1417 "vmx-exit-load-perf-global-ctrl", NULL, NULL, "vmx-exit-ack-intr", 1418 NULL, NULL, "vmx-exit-save-pat", "vmx-exit-load-pat", 1419 "vmx-exit-save-efer", "vmx-exit-load-efer", 1420 "vmx-exit-save-preemption-timer", "vmx-exit-clear-bndcfgs", 1421 NULL, "vmx-exit-clear-rtit-ctl", NULL, NULL, 1422 NULL, "vmx-exit-load-pkrs", NULL, NULL, 1423 }, 1424 .msr = { 1425 .index = MSR_IA32_VMX_TRUE_EXIT_CTLS, 1426 } 1427 }, 1428 1429 [FEAT_VMX_ENTRY_CTLS] = { 1430 .type = MSR_FEATURE_WORD, 1431 .feat_names = { 1432 NULL, NULL, "vmx-entry-noload-debugctl", NULL, 1433 NULL, NULL, NULL, NULL, 1434 NULL, "vmx-entry-ia32e-mode", NULL, NULL, 1435 NULL, "vmx-entry-load-perf-global-ctrl", "vmx-entry-load-pat", "vmx-entry-load-efer", 1436 "vmx-entry-load-bndcfgs", NULL, "vmx-entry-load-rtit-ctl", NULL, 1437 NULL, NULL, "vmx-entry-load-pkrs", NULL, 1438 NULL, NULL, NULL, NULL, 1439 NULL, NULL, NULL, NULL, 1440 }, 1441 .msr = { 1442 .index = MSR_IA32_VMX_TRUE_ENTRY_CTLS, 1443 } 1444 }, 1445 1446 [FEAT_VMX_MISC] = { 1447 .type = MSR_FEATURE_WORD, 1448 .feat_names = { 1449 NULL, NULL, NULL, NULL, 1450 NULL, "vmx-store-lma", "vmx-activity-hlt", "vmx-activity-shutdown", 1451 "vmx-activity-wait-sipi", NULL, NULL, NULL, 1452 NULL, NULL, NULL, NULL, 1453 NULL, NULL, NULL, NULL, 1454 NULL, NULL, NULL, NULL, 1455 NULL, NULL, NULL, NULL, 1456 NULL, "vmx-vmwrite-vmexit-fields", "vmx-zero-len-inject", NULL, 1457 }, 1458 .msr = { 1459 .index = MSR_IA32_VMX_MISC, 1460 } 1461 }, 1462 1463 [FEAT_VMX_EPT_VPID_CAPS] = { 1464 .type = MSR_FEATURE_WORD, 1465 .feat_names = { 1466 "vmx-ept-execonly", NULL, NULL, NULL, 1467 NULL, NULL, "vmx-page-walk-4", "vmx-page-walk-5", 1468 NULL, NULL, NULL, NULL, 1469 NULL, NULL, NULL, NULL, 1470 "vmx-ept-2mb", "vmx-ept-1gb", NULL, NULL, 1471 "vmx-invept", "vmx-eptad", "vmx-ept-advanced-exitinfo", NULL, 1472 NULL, "vmx-invept-single-context", "vmx-invept-all-context", NULL, 1473 NULL, NULL, NULL, NULL, 1474 "vmx-invvpid", NULL, NULL, NULL, 1475 NULL, NULL, NULL, NULL, 1476 "vmx-invvpid-single-addr", "vmx-invept-single-context", 1477 "vmx-invvpid-all-context", "vmx-invept-single-context-noglobals", 1478 NULL, NULL, NULL, NULL, 1479 NULL, NULL, NULL, NULL, 1480 NULL, NULL, NULL, NULL, 1481 NULL, NULL, NULL, NULL, 1482 NULL, NULL, NULL, NULL, 1483 }, 1484 .msr = { 1485 .index = MSR_IA32_VMX_EPT_VPID_CAP, 1486 } 1487 }, 1488 1489 [FEAT_VMX_BASIC] = { 1490 .type = MSR_FEATURE_WORD, 1491 .feat_names = { 1492 [54] = "vmx-ins-outs", 1493 [55] = "vmx-true-ctls", 1494 [56] = "vmx-any-errcode", 1495 }, 1496 .msr = { 1497 .index = MSR_IA32_VMX_BASIC, 1498 }, 1499 /* Just to be safe - we don't support setting the MSEG version field. */ 1500 .no_autoenable_flags = MSR_VMX_BASIC_DUAL_MONITOR, 1501 }, 1502 1503 [FEAT_VMX_VMFUNC] = { 1504 .type = MSR_FEATURE_WORD, 1505 .feat_names = { 1506 [0] = "vmx-eptp-switching", 1507 }, 1508 .msr = { 1509 .index = MSR_IA32_VMX_VMFUNC, 1510 } 1511 }, 1512 1513 [FEAT_14_0_ECX] = { 1514 .type = CPUID_FEATURE_WORD, 1515 .feat_names = { 1516 NULL, NULL, NULL, NULL, 1517 NULL, NULL, NULL, NULL, 1518 NULL, NULL, NULL, NULL, 1519 NULL, NULL, NULL, NULL, 1520 NULL, NULL, NULL, NULL, 1521 NULL, NULL, NULL, NULL, 1522 NULL, NULL, NULL, NULL, 1523 NULL, NULL, NULL, "intel-pt-lip", 1524 }, 1525 .cpuid = { 1526 .eax = 0x14, 1527 .needs_ecx = true, .ecx = 0, 1528 .reg = R_ECX, 1529 }, 1530 .tcg_features = TCG_14_0_ECX_FEATURES, 1531 }, 1532 1533 [FEAT_SGX_12_0_EAX] = { 1534 .type = CPUID_FEATURE_WORD, 1535 .feat_names = { 1536 "sgx1", "sgx2", NULL, NULL, 1537 NULL, NULL, NULL, NULL, 1538 NULL, NULL, NULL, "sgx-edeccssa", 1539 NULL, NULL, NULL, NULL, 1540 NULL, NULL, NULL, NULL, 1541 NULL, NULL, NULL, NULL, 1542 NULL, NULL, NULL, NULL, 1543 NULL, NULL, NULL, NULL, 1544 }, 1545 .cpuid = { 1546 .eax = 0x12, 1547 .needs_ecx = true, .ecx = 0, 1548 .reg = R_EAX, 1549 }, 1550 .tcg_features = TCG_SGX_12_0_EAX_FEATURES, 1551 }, 1552 1553 [FEAT_SGX_12_0_EBX] = { 1554 .type = CPUID_FEATURE_WORD, 1555 .feat_names = { 1556 "sgx-exinfo" , NULL, NULL, NULL, 1557 NULL, NULL, NULL, NULL, 1558 NULL, NULL, NULL, NULL, 1559 NULL, NULL, NULL, NULL, 1560 NULL, NULL, NULL, NULL, 1561 NULL, NULL, NULL, NULL, 1562 NULL, NULL, NULL, NULL, 1563 NULL, NULL, NULL, NULL, 1564 }, 1565 .cpuid = { 1566 .eax = 0x12, 1567 .needs_ecx = true, .ecx = 0, 1568 .reg = R_EBX, 1569 }, 1570 .tcg_features = TCG_SGX_12_0_EBX_FEATURES, 1571 }, 1572 1573 [FEAT_SGX_12_1_EAX] = { 1574 .type = CPUID_FEATURE_WORD, 1575 .feat_names = { 1576 NULL, "sgx-debug", "sgx-mode64", NULL, 1577 "sgx-provisionkey", "sgx-tokenkey", NULL, "sgx-kss", 1578 NULL, NULL, "sgx-aex-notify", NULL, 1579 NULL, NULL, NULL, NULL, 1580 NULL, NULL, NULL, NULL, 1581 NULL, NULL, NULL, NULL, 1582 NULL, NULL, NULL, NULL, 1583 NULL, NULL, NULL, NULL, 1584 }, 1585 .cpuid = { 1586 .eax = 0x12, 1587 .needs_ecx = true, .ecx = 1, 1588 .reg = R_EAX, 1589 }, 1590 .tcg_features = TCG_SGX_12_1_EAX_FEATURES, 1591 }, 1592 }; 1593 1594 typedef struct FeatureMask { 1595 FeatureWord index; 1596 uint64_t mask; 1597 } FeatureMask; 1598 1599 typedef struct FeatureDep { 1600 FeatureMask from, to; 1601 } FeatureDep; 1602 1603 static FeatureDep feature_dependencies[] = { 1604 { 1605 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_ARCH_CAPABILITIES }, 1606 .to = { FEAT_ARCH_CAPABILITIES, ~0ull }, 1607 }, 1608 { 1609 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_CORE_CAPABILITY }, 1610 .to = { FEAT_CORE_CAPABILITY, ~0ull }, 1611 }, 1612 { 1613 .from = { FEAT_1_ECX, CPUID_EXT_PDCM }, 1614 .to = { FEAT_PERF_CAPABILITIES, ~0ull }, 1615 }, 1616 { 1617 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1618 .to = { FEAT_VMX_PROCBASED_CTLS, ~0ull }, 1619 }, 1620 { 1621 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1622 .to = { FEAT_VMX_PINBASED_CTLS, ~0ull }, 1623 }, 1624 { 1625 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1626 .to = { FEAT_VMX_EXIT_CTLS, ~0ull }, 1627 }, 1628 { 1629 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1630 .to = { FEAT_VMX_ENTRY_CTLS, ~0ull }, 1631 }, 1632 { 1633 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1634 .to = { FEAT_VMX_MISC, ~0ull }, 1635 }, 1636 { 1637 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1638 .to = { FEAT_VMX_BASIC, ~0ull }, 1639 }, 1640 { 1641 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_LM }, 1642 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_IA32E_MODE }, 1643 }, 1644 { 1645 .from = { FEAT_VMX_PROCBASED_CTLS, VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS }, 1646 .to = { FEAT_VMX_SECONDARY_CTLS, ~0ull }, 1647 }, 1648 { 1649 .from = { FEAT_XSAVE, CPUID_XSAVE_XSAVES }, 1650 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_XSAVES }, 1651 }, 1652 { 1653 .from = { FEAT_1_ECX, CPUID_EXT_RDRAND }, 1654 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDRAND_EXITING }, 1655 }, 1656 { 1657 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INVPCID }, 1658 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_INVPCID }, 1659 }, 1660 { 1661 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_MPX }, 1662 .to = { FEAT_VMX_EXIT_CTLS, VMX_VM_EXIT_CLEAR_BNDCFGS }, 1663 }, 1664 { 1665 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_MPX }, 1666 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_LOAD_BNDCFGS }, 1667 }, 1668 { 1669 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_RDSEED }, 1670 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDSEED_EXITING }, 1671 }, 1672 { 1673 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT }, 1674 .to = { FEAT_14_0_ECX, ~0ull }, 1675 }, 1676 { 1677 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_RDTSCP }, 1678 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDTSCP }, 1679 }, 1680 { 1681 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT }, 1682 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull }, 1683 }, 1684 { 1685 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT }, 1686 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST }, 1687 }, 1688 { 1689 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VPID }, 1690 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull << 32 }, 1691 }, 1692 { 1693 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VMFUNC }, 1694 .to = { FEAT_VMX_VMFUNC, ~0ull }, 1695 }, 1696 { 1697 .from = { FEAT_8000_0001_ECX, CPUID_EXT3_SVM }, 1698 .to = { FEAT_SVM, ~0ull }, 1699 }, 1700 { 1701 .from = { FEAT_7_0_ECX, CPUID_7_0_ECX_WAITPKG }, 1702 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_USER_WAIT_PAUSE }, 1703 }, 1704 { 1705 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_LM }, 1706 .to = { FEAT_7_1_EAX, CPUID_7_1_EAX_FRED }, 1707 }, 1708 { 1709 .from = { FEAT_7_1_EAX, CPUID_7_1_EAX_LKGS }, 1710 .to = { FEAT_7_1_EAX, CPUID_7_1_EAX_FRED }, 1711 }, 1712 { 1713 .from = { FEAT_7_1_EAX, CPUID_7_1_EAX_WRMSRNS }, 1714 .to = { FEAT_7_1_EAX, CPUID_7_1_EAX_FRED }, 1715 }, 1716 }; 1717 1718 typedef struct X86RegisterInfo32 { 1719 /* Name of register */ 1720 const char *name; 1721 /* QAPI enum value register */ 1722 X86CPURegister32 qapi_enum; 1723 } X86RegisterInfo32; 1724 1725 #define REGISTER(reg) \ 1726 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg } 1727 static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = { 1728 REGISTER(EAX), 1729 REGISTER(ECX), 1730 REGISTER(EDX), 1731 REGISTER(EBX), 1732 REGISTER(ESP), 1733 REGISTER(EBP), 1734 REGISTER(ESI), 1735 REGISTER(EDI), 1736 }; 1737 #undef REGISTER 1738 1739 /* CPUID feature bits available in XSS */ 1740 #define CPUID_XSTATE_XSS_MASK (XSTATE_ARCH_LBR_MASK) 1741 1742 ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUNT] = { 1743 [XSTATE_FP_BIT] = { 1744 /* x87 FP state component is always enabled if XSAVE is supported */ 1745 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE, 1746 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader), 1747 }, 1748 [XSTATE_SSE_BIT] = { 1749 /* SSE state component is always enabled if XSAVE is supported */ 1750 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE, 1751 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader), 1752 }, 1753 [XSTATE_YMM_BIT] = 1754 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX, 1755 .size = sizeof(XSaveAVX) }, 1756 [XSTATE_BNDREGS_BIT] = 1757 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX, 1758 .size = sizeof(XSaveBNDREG) }, 1759 [XSTATE_BNDCSR_BIT] = 1760 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX, 1761 .size = sizeof(XSaveBNDCSR) }, 1762 [XSTATE_OPMASK_BIT] = 1763 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1764 .size = sizeof(XSaveOpmask) }, 1765 [XSTATE_ZMM_Hi256_BIT] = 1766 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1767 .size = sizeof(XSaveZMM_Hi256) }, 1768 [XSTATE_Hi16_ZMM_BIT] = 1769 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1770 .size = sizeof(XSaveHi16_ZMM) }, 1771 [XSTATE_PKRU_BIT] = 1772 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU, 1773 .size = sizeof(XSavePKRU) }, 1774 [XSTATE_ARCH_LBR_BIT] = { 1775 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_ARCH_LBR, 1776 .offset = 0 /*supervisor mode component, offset = 0 */, 1777 .size = sizeof(XSavesArchLBR) }, 1778 [XSTATE_XTILE_CFG_BIT] = { 1779 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_AMX_TILE, 1780 .size = sizeof(XSaveXTILECFG), 1781 }, 1782 [XSTATE_XTILE_DATA_BIT] = { 1783 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_AMX_TILE, 1784 .size = sizeof(XSaveXTILEDATA) 1785 }, 1786 }; 1787 1788 uint32_t xsave_area_size(uint64_t mask, bool compacted) 1789 { 1790 uint64_t ret = x86_ext_save_areas[0].size; 1791 const ExtSaveArea *esa; 1792 uint32_t offset = 0; 1793 int i; 1794 1795 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 1796 esa = &x86_ext_save_areas[i]; 1797 if ((mask >> i) & 1) { 1798 offset = compacted ? ret : esa->offset; 1799 ret = MAX(ret, offset + esa->size); 1800 } 1801 } 1802 return ret; 1803 } 1804 1805 static inline bool accel_uses_host_cpuid(void) 1806 { 1807 return kvm_enabled() || hvf_enabled(); 1808 } 1809 1810 static inline uint64_t x86_cpu_xsave_xcr0_components(X86CPU *cpu) 1811 { 1812 return ((uint64_t)cpu->env.features[FEAT_XSAVE_XCR0_HI]) << 32 | 1813 cpu->env.features[FEAT_XSAVE_XCR0_LO]; 1814 } 1815 1816 /* Return name of 32-bit register, from a R_* constant */ 1817 static const char *get_register_name_32(unsigned int reg) 1818 { 1819 if (reg >= CPU_NB_REGS32) { 1820 return NULL; 1821 } 1822 return x86_reg_info_32[reg].name; 1823 } 1824 1825 static inline uint64_t x86_cpu_xsave_xss_components(X86CPU *cpu) 1826 { 1827 return ((uint64_t)cpu->env.features[FEAT_XSAVE_XSS_HI]) << 32 | 1828 cpu->env.features[FEAT_XSAVE_XSS_LO]; 1829 } 1830 1831 /* 1832 * Returns the set of feature flags that are supported and migratable by 1833 * QEMU, for a given FeatureWord. 1834 */ 1835 static uint64_t x86_cpu_get_migratable_flags(FeatureWord w) 1836 { 1837 FeatureWordInfo *wi = &feature_word_info[w]; 1838 uint64_t r = 0; 1839 int i; 1840 1841 for (i = 0; i < 64; i++) { 1842 uint64_t f = 1ULL << i; 1843 1844 /* If the feature name is known, it is implicitly considered migratable, 1845 * unless it is explicitly set in unmigratable_flags */ 1846 if ((wi->migratable_flags & f) || 1847 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) { 1848 r |= f; 1849 } 1850 } 1851 return r; 1852 } 1853 1854 void host_cpuid(uint32_t function, uint32_t count, 1855 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) 1856 { 1857 uint32_t vec[4]; 1858 1859 #ifdef __x86_64__ 1860 asm volatile("cpuid" 1861 : "=a"(vec[0]), "=b"(vec[1]), 1862 "=c"(vec[2]), "=d"(vec[3]) 1863 : "0"(function), "c"(count) : "cc"); 1864 #elif defined(__i386__) 1865 asm volatile("pusha \n\t" 1866 "cpuid \n\t" 1867 "mov %%eax, 0(%2) \n\t" 1868 "mov %%ebx, 4(%2) \n\t" 1869 "mov %%ecx, 8(%2) \n\t" 1870 "mov %%edx, 12(%2) \n\t" 1871 "popa" 1872 : : "a"(function), "c"(count), "S"(vec) 1873 : "memory", "cc"); 1874 #else 1875 abort(); 1876 #endif 1877 1878 if (eax) 1879 *eax = vec[0]; 1880 if (ebx) 1881 *ebx = vec[1]; 1882 if (ecx) 1883 *ecx = vec[2]; 1884 if (edx) 1885 *edx = vec[3]; 1886 } 1887 1888 /* CPU class name definitions: */ 1889 1890 /* Return type name for a given CPU model name 1891 * Caller is responsible for freeing the returned string. 1892 */ 1893 static char *x86_cpu_type_name(const char *model_name) 1894 { 1895 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name); 1896 } 1897 1898 static ObjectClass *x86_cpu_class_by_name(const char *cpu_model) 1899 { 1900 g_autofree char *typename = x86_cpu_type_name(cpu_model); 1901 return object_class_by_name(typename); 1902 } 1903 1904 static char *x86_cpu_class_get_model_name(X86CPUClass *cc) 1905 { 1906 const char *class_name = object_class_get_name(OBJECT_CLASS(cc)); 1907 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX)); 1908 return cpu_model_from_type(class_name); 1909 } 1910 1911 typedef struct X86CPUVersionDefinition { 1912 X86CPUVersion version; 1913 const char *alias; 1914 const char *note; 1915 PropValue *props; 1916 const CPUCaches *const cache_info; 1917 } X86CPUVersionDefinition; 1918 1919 /* Base definition for a CPU model */ 1920 typedef struct X86CPUDefinition { 1921 const char *name; 1922 uint32_t level; 1923 uint32_t xlevel; 1924 /* vendor is zero-terminated, 12 character ASCII string */ 1925 char vendor[CPUID_VENDOR_SZ + 1]; 1926 int family; 1927 int model; 1928 int stepping; 1929 FeatureWordArray features; 1930 const char *model_id; 1931 const CPUCaches *const cache_info; 1932 /* 1933 * Definitions for alternative versions of CPU model. 1934 * List is terminated by item with version == 0. 1935 * If NULL, version 1 will be registered automatically. 1936 */ 1937 const X86CPUVersionDefinition *versions; 1938 const char *deprecation_note; 1939 } X86CPUDefinition; 1940 1941 /* Reference to a specific CPU model version */ 1942 struct X86CPUModel { 1943 /* Base CPU definition */ 1944 const X86CPUDefinition *cpudef; 1945 /* CPU model version */ 1946 X86CPUVersion version; 1947 const char *note; 1948 /* 1949 * If true, this is an alias CPU model. 1950 * This matters only for "-cpu help" and query-cpu-definitions 1951 */ 1952 bool is_alias; 1953 }; 1954 1955 /* Get full model name for CPU version */ 1956 static char *x86_cpu_versioned_model_name(const X86CPUDefinition *cpudef, 1957 X86CPUVersion version) 1958 { 1959 assert(version > 0); 1960 return g_strdup_printf("%s-v%d", cpudef->name, (int)version); 1961 } 1962 1963 static const X86CPUVersionDefinition * 1964 x86_cpu_def_get_versions(const X86CPUDefinition *def) 1965 { 1966 /* When X86CPUDefinition::versions is NULL, we register only v1 */ 1967 static const X86CPUVersionDefinition default_version_list[] = { 1968 { 1 }, 1969 { /* end of list */ } 1970 }; 1971 1972 return def->versions ?: default_version_list; 1973 } 1974 1975 static const CPUCaches epyc_cache_info = { 1976 .l1d_cache = &(CPUCacheInfo) { 1977 .type = DATA_CACHE, 1978 .level = 1, 1979 .size = 32 * KiB, 1980 .line_size = 64, 1981 .associativity = 8, 1982 .partitions = 1, 1983 .sets = 64, 1984 .lines_per_tag = 1, 1985 .self_init = 1, 1986 .no_invd_sharing = true, 1987 .share_level = CPU_TOPO_LEVEL_CORE, 1988 }, 1989 .l1i_cache = &(CPUCacheInfo) { 1990 .type = INSTRUCTION_CACHE, 1991 .level = 1, 1992 .size = 64 * KiB, 1993 .line_size = 64, 1994 .associativity = 4, 1995 .partitions = 1, 1996 .sets = 256, 1997 .lines_per_tag = 1, 1998 .self_init = 1, 1999 .no_invd_sharing = true, 2000 .share_level = CPU_TOPO_LEVEL_CORE, 2001 }, 2002 .l2_cache = &(CPUCacheInfo) { 2003 .type = UNIFIED_CACHE, 2004 .level = 2, 2005 .size = 512 * KiB, 2006 .line_size = 64, 2007 .associativity = 8, 2008 .partitions = 1, 2009 .sets = 1024, 2010 .lines_per_tag = 1, 2011 .share_level = CPU_TOPO_LEVEL_CORE, 2012 }, 2013 .l3_cache = &(CPUCacheInfo) { 2014 .type = UNIFIED_CACHE, 2015 .level = 3, 2016 .size = 8 * MiB, 2017 .line_size = 64, 2018 .associativity = 16, 2019 .partitions = 1, 2020 .sets = 8192, 2021 .lines_per_tag = 1, 2022 .self_init = true, 2023 .inclusive = true, 2024 .complex_indexing = true, 2025 .share_level = CPU_TOPO_LEVEL_DIE, 2026 }, 2027 }; 2028 2029 static CPUCaches epyc_v4_cache_info = { 2030 .l1d_cache = &(CPUCacheInfo) { 2031 .type = DATA_CACHE, 2032 .level = 1, 2033 .size = 32 * KiB, 2034 .line_size = 64, 2035 .associativity = 8, 2036 .partitions = 1, 2037 .sets = 64, 2038 .lines_per_tag = 1, 2039 .self_init = 1, 2040 .no_invd_sharing = true, 2041 .share_level = CPU_TOPO_LEVEL_CORE, 2042 }, 2043 .l1i_cache = &(CPUCacheInfo) { 2044 .type = INSTRUCTION_CACHE, 2045 .level = 1, 2046 .size = 64 * KiB, 2047 .line_size = 64, 2048 .associativity = 4, 2049 .partitions = 1, 2050 .sets = 256, 2051 .lines_per_tag = 1, 2052 .self_init = 1, 2053 .no_invd_sharing = true, 2054 .share_level = CPU_TOPO_LEVEL_CORE, 2055 }, 2056 .l2_cache = &(CPUCacheInfo) { 2057 .type = UNIFIED_CACHE, 2058 .level = 2, 2059 .size = 512 * KiB, 2060 .line_size = 64, 2061 .associativity = 8, 2062 .partitions = 1, 2063 .sets = 1024, 2064 .lines_per_tag = 1, 2065 .share_level = CPU_TOPO_LEVEL_CORE, 2066 }, 2067 .l3_cache = &(CPUCacheInfo) { 2068 .type = UNIFIED_CACHE, 2069 .level = 3, 2070 .size = 8 * MiB, 2071 .line_size = 64, 2072 .associativity = 16, 2073 .partitions = 1, 2074 .sets = 8192, 2075 .lines_per_tag = 1, 2076 .self_init = true, 2077 .inclusive = true, 2078 .complex_indexing = false, 2079 .share_level = CPU_TOPO_LEVEL_DIE, 2080 }, 2081 }; 2082 2083 static const CPUCaches epyc_rome_cache_info = { 2084 .l1d_cache = &(CPUCacheInfo) { 2085 .type = DATA_CACHE, 2086 .level = 1, 2087 .size = 32 * KiB, 2088 .line_size = 64, 2089 .associativity = 8, 2090 .partitions = 1, 2091 .sets = 64, 2092 .lines_per_tag = 1, 2093 .self_init = 1, 2094 .no_invd_sharing = true, 2095 .share_level = CPU_TOPO_LEVEL_CORE, 2096 }, 2097 .l1i_cache = &(CPUCacheInfo) { 2098 .type = INSTRUCTION_CACHE, 2099 .level = 1, 2100 .size = 32 * KiB, 2101 .line_size = 64, 2102 .associativity = 8, 2103 .partitions = 1, 2104 .sets = 64, 2105 .lines_per_tag = 1, 2106 .self_init = 1, 2107 .no_invd_sharing = true, 2108 .share_level = CPU_TOPO_LEVEL_CORE, 2109 }, 2110 .l2_cache = &(CPUCacheInfo) { 2111 .type = UNIFIED_CACHE, 2112 .level = 2, 2113 .size = 512 * KiB, 2114 .line_size = 64, 2115 .associativity = 8, 2116 .partitions = 1, 2117 .sets = 1024, 2118 .lines_per_tag = 1, 2119 .share_level = CPU_TOPO_LEVEL_CORE, 2120 }, 2121 .l3_cache = &(CPUCacheInfo) { 2122 .type = UNIFIED_CACHE, 2123 .level = 3, 2124 .size = 16 * MiB, 2125 .line_size = 64, 2126 .associativity = 16, 2127 .partitions = 1, 2128 .sets = 16384, 2129 .lines_per_tag = 1, 2130 .self_init = true, 2131 .inclusive = true, 2132 .complex_indexing = true, 2133 .share_level = CPU_TOPO_LEVEL_DIE, 2134 }, 2135 }; 2136 2137 static const CPUCaches epyc_rome_v3_cache_info = { 2138 .l1d_cache = &(CPUCacheInfo) { 2139 .type = DATA_CACHE, 2140 .level = 1, 2141 .size = 32 * KiB, 2142 .line_size = 64, 2143 .associativity = 8, 2144 .partitions = 1, 2145 .sets = 64, 2146 .lines_per_tag = 1, 2147 .self_init = 1, 2148 .no_invd_sharing = true, 2149 .share_level = CPU_TOPO_LEVEL_CORE, 2150 }, 2151 .l1i_cache = &(CPUCacheInfo) { 2152 .type = INSTRUCTION_CACHE, 2153 .level = 1, 2154 .size = 32 * KiB, 2155 .line_size = 64, 2156 .associativity = 8, 2157 .partitions = 1, 2158 .sets = 64, 2159 .lines_per_tag = 1, 2160 .self_init = 1, 2161 .no_invd_sharing = true, 2162 .share_level = CPU_TOPO_LEVEL_CORE, 2163 }, 2164 .l2_cache = &(CPUCacheInfo) { 2165 .type = UNIFIED_CACHE, 2166 .level = 2, 2167 .size = 512 * KiB, 2168 .line_size = 64, 2169 .associativity = 8, 2170 .partitions = 1, 2171 .sets = 1024, 2172 .lines_per_tag = 1, 2173 .share_level = CPU_TOPO_LEVEL_CORE, 2174 }, 2175 .l3_cache = &(CPUCacheInfo) { 2176 .type = UNIFIED_CACHE, 2177 .level = 3, 2178 .size = 16 * MiB, 2179 .line_size = 64, 2180 .associativity = 16, 2181 .partitions = 1, 2182 .sets = 16384, 2183 .lines_per_tag = 1, 2184 .self_init = true, 2185 .inclusive = true, 2186 .complex_indexing = false, 2187 .share_level = CPU_TOPO_LEVEL_DIE, 2188 }, 2189 }; 2190 2191 static const CPUCaches epyc_milan_cache_info = { 2192 .l1d_cache = &(CPUCacheInfo) { 2193 .type = DATA_CACHE, 2194 .level = 1, 2195 .size = 32 * KiB, 2196 .line_size = 64, 2197 .associativity = 8, 2198 .partitions = 1, 2199 .sets = 64, 2200 .lines_per_tag = 1, 2201 .self_init = 1, 2202 .no_invd_sharing = true, 2203 .share_level = CPU_TOPO_LEVEL_CORE, 2204 }, 2205 .l1i_cache = &(CPUCacheInfo) { 2206 .type = INSTRUCTION_CACHE, 2207 .level = 1, 2208 .size = 32 * KiB, 2209 .line_size = 64, 2210 .associativity = 8, 2211 .partitions = 1, 2212 .sets = 64, 2213 .lines_per_tag = 1, 2214 .self_init = 1, 2215 .no_invd_sharing = true, 2216 .share_level = CPU_TOPO_LEVEL_CORE, 2217 }, 2218 .l2_cache = &(CPUCacheInfo) { 2219 .type = UNIFIED_CACHE, 2220 .level = 2, 2221 .size = 512 * KiB, 2222 .line_size = 64, 2223 .associativity = 8, 2224 .partitions = 1, 2225 .sets = 1024, 2226 .lines_per_tag = 1, 2227 .share_level = CPU_TOPO_LEVEL_CORE, 2228 }, 2229 .l3_cache = &(CPUCacheInfo) { 2230 .type = UNIFIED_CACHE, 2231 .level = 3, 2232 .size = 32 * MiB, 2233 .line_size = 64, 2234 .associativity = 16, 2235 .partitions = 1, 2236 .sets = 32768, 2237 .lines_per_tag = 1, 2238 .self_init = true, 2239 .inclusive = true, 2240 .complex_indexing = true, 2241 .share_level = CPU_TOPO_LEVEL_DIE, 2242 }, 2243 }; 2244 2245 static const CPUCaches epyc_milan_v2_cache_info = { 2246 .l1d_cache = &(CPUCacheInfo) { 2247 .type = DATA_CACHE, 2248 .level = 1, 2249 .size = 32 * KiB, 2250 .line_size = 64, 2251 .associativity = 8, 2252 .partitions = 1, 2253 .sets = 64, 2254 .lines_per_tag = 1, 2255 .self_init = 1, 2256 .no_invd_sharing = true, 2257 .share_level = CPU_TOPO_LEVEL_CORE, 2258 }, 2259 .l1i_cache = &(CPUCacheInfo) { 2260 .type = INSTRUCTION_CACHE, 2261 .level = 1, 2262 .size = 32 * KiB, 2263 .line_size = 64, 2264 .associativity = 8, 2265 .partitions = 1, 2266 .sets = 64, 2267 .lines_per_tag = 1, 2268 .self_init = 1, 2269 .no_invd_sharing = true, 2270 .share_level = CPU_TOPO_LEVEL_CORE, 2271 }, 2272 .l2_cache = &(CPUCacheInfo) { 2273 .type = UNIFIED_CACHE, 2274 .level = 2, 2275 .size = 512 * KiB, 2276 .line_size = 64, 2277 .associativity = 8, 2278 .partitions = 1, 2279 .sets = 1024, 2280 .lines_per_tag = 1, 2281 .share_level = CPU_TOPO_LEVEL_CORE, 2282 }, 2283 .l3_cache = &(CPUCacheInfo) { 2284 .type = UNIFIED_CACHE, 2285 .level = 3, 2286 .size = 32 * MiB, 2287 .line_size = 64, 2288 .associativity = 16, 2289 .partitions = 1, 2290 .sets = 32768, 2291 .lines_per_tag = 1, 2292 .self_init = true, 2293 .inclusive = true, 2294 .complex_indexing = false, 2295 .share_level = CPU_TOPO_LEVEL_DIE, 2296 }, 2297 }; 2298 2299 static const CPUCaches epyc_genoa_cache_info = { 2300 .l1d_cache = &(CPUCacheInfo) { 2301 .type = DATA_CACHE, 2302 .level = 1, 2303 .size = 32 * KiB, 2304 .line_size = 64, 2305 .associativity = 8, 2306 .partitions = 1, 2307 .sets = 64, 2308 .lines_per_tag = 1, 2309 .self_init = 1, 2310 .no_invd_sharing = true, 2311 .share_level = CPU_TOPO_LEVEL_CORE, 2312 }, 2313 .l1i_cache = &(CPUCacheInfo) { 2314 .type = INSTRUCTION_CACHE, 2315 .level = 1, 2316 .size = 32 * KiB, 2317 .line_size = 64, 2318 .associativity = 8, 2319 .partitions = 1, 2320 .sets = 64, 2321 .lines_per_tag = 1, 2322 .self_init = 1, 2323 .no_invd_sharing = true, 2324 .share_level = CPU_TOPO_LEVEL_CORE, 2325 }, 2326 .l2_cache = &(CPUCacheInfo) { 2327 .type = UNIFIED_CACHE, 2328 .level = 2, 2329 .size = 1 * MiB, 2330 .line_size = 64, 2331 .associativity = 8, 2332 .partitions = 1, 2333 .sets = 2048, 2334 .lines_per_tag = 1, 2335 .share_level = CPU_TOPO_LEVEL_CORE, 2336 }, 2337 .l3_cache = &(CPUCacheInfo) { 2338 .type = UNIFIED_CACHE, 2339 .level = 3, 2340 .size = 32 * MiB, 2341 .line_size = 64, 2342 .associativity = 16, 2343 .partitions = 1, 2344 .sets = 32768, 2345 .lines_per_tag = 1, 2346 .self_init = true, 2347 .inclusive = true, 2348 .complex_indexing = false, 2349 .share_level = CPU_TOPO_LEVEL_DIE, 2350 }, 2351 }; 2352 2353 /* The following VMX features are not supported by KVM and are left out in the 2354 * CPU definitions: 2355 * 2356 * Dual-monitor support (all processors) 2357 * Entry to SMM 2358 * Deactivate dual-monitor treatment 2359 * Number of CR3-target values 2360 * Shutdown activity state 2361 * Wait-for-SIPI activity state 2362 * PAUSE-loop exiting (Westmere and newer) 2363 * EPT-violation #VE (Broadwell and newer) 2364 * Inject event with insn length=0 (Skylake and newer) 2365 * Conceal non-root operation from PT 2366 * Conceal VM exits from PT 2367 * Conceal VM entries from PT 2368 * Enable ENCLS exiting 2369 * Mode-based execute control (XS/XU) 2370 * TSC scaling (Skylake Server and newer) 2371 * GPA translation for PT (IceLake and newer) 2372 * User wait and pause 2373 * ENCLV exiting 2374 * Load IA32_RTIT_CTL 2375 * Clear IA32_RTIT_CTL 2376 * Advanced VM-exit information for EPT violations 2377 * Sub-page write permissions 2378 * PT in VMX operation 2379 */ 2380 2381 static const X86CPUDefinition builtin_x86_defs[] = { 2382 { 2383 .name = "qemu64", 2384 .level = 0xd, 2385 .vendor = CPUID_VENDOR_AMD, 2386 .family = 15, 2387 .model = 107, 2388 .stepping = 1, 2389 .features[FEAT_1_EDX] = 2390 PPRO_FEATURES | 2391 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2392 CPUID_PSE36, 2393 .features[FEAT_1_ECX] = 2394 CPUID_EXT_SSE3 | CPUID_EXT_CX16, 2395 .features[FEAT_8000_0001_EDX] = 2396 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2397 .features[FEAT_8000_0001_ECX] = 2398 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM, 2399 .xlevel = 0x8000000A, 2400 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 2401 }, 2402 { 2403 .name = "phenom", 2404 .level = 5, 2405 .vendor = CPUID_VENDOR_AMD, 2406 .family = 16, 2407 .model = 2, 2408 .stepping = 3, 2409 /* Missing: CPUID_HT */ 2410 .features[FEAT_1_EDX] = 2411 PPRO_FEATURES | 2412 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2413 CPUID_PSE36 | CPUID_VME, 2414 .features[FEAT_1_ECX] = 2415 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 | 2416 CPUID_EXT_POPCNT, 2417 .features[FEAT_8000_0001_EDX] = 2418 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | 2419 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT | 2420 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP, 2421 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, 2422 CPUID_EXT3_CR8LEG, 2423 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, 2424 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */ 2425 .features[FEAT_8000_0001_ECX] = 2426 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | 2427 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A, 2428 /* Missing: CPUID_SVM_LBRV */ 2429 .features[FEAT_SVM] = 2430 CPUID_SVM_NPT, 2431 .xlevel = 0x8000001A, 2432 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor" 2433 }, 2434 { 2435 .name = "core2duo", 2436 .level = 10, 2437 .vendor = CPUID_VENDOR_INTEL, 2438 .family = 6, 2439 .model = 15, 2440 .stepping = 11, 2441 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2442 .features[FEAT_1_EDX] = 2443 PPRO_FEATURES | 2444 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2445 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS, 2446 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST, 2447 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */ 2448 .features[FEAT_1_ECX] = 2449 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | 2450 CPUID_EXT_CX16, 2451 .features[FEAT_8000_0001_EDX] = 2452 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2453 .features[FEAT_8000_0001_ECX] = 2454 CPUID_EXT3_LAHF_LM, 2455 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2456 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2457 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2458 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2459 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2460 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2461 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2462 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2463 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2464 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2465 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2466 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2467 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2468 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2469 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2470 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2471 .features[FEAT_VMX_SECONDARY_CTLS] = 2472 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES, 2473 .xlevel = 0x80000008, 2474 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz", 2475 }, 2476 { 2477 .name = "kvm64", 2478 .level = 0xd, 2479 .vendor = CPUID_VENDOR_INTEL, 2480 .family = 15, 2481 .model = 6, 2482 .stepping = 1, 2483 /* Missing: CPUID_HT */ 2484 .features[FEAT_1_EDX] = 2485 PPRO_FEATURES | CPUID_VME | 2486 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2487 CPUID_PSE36, 2488 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */ 2489 .features[FEAT_1_ECX] = 2490 CPUID_EXT_SSE3 | CPUID_EXT_CX16, 2491 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */ 2492 .features[FEAT_8000_0001_EDX] = 2493 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2494 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, 2495 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A, 2496 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, 2497 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */ 2498 .features[FEAT_8000_0001_ECX] = 2499 0, 2500 /* VMX features from Cedar Mill/Prescott */ 2501 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2502 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2503 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2504 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2505 VMX_PIN_BASED_NMI_EXITING, 2506 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2507 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2508 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2509 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2510 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2511 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2512 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2513 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING, 2514 .xlevel = 0x80000008, 2515 .model_id = "Common KVM processor" 2516 }, 2517 { 2518 .name = "qemu32", 2519 .level = 4, 2520 .vendor = CPUID_VENDOR_INTEL, 2521 .family = 6, 2522 .model = 6, 2523 .stepping = 3, 2524 .features[FEAT_1_EDX] = 2525 PPRO_FEATURES, 2526 .features[FEAT_1_ECX] = 2527 CPUID_EXT_SSE3, 2528 .xlevel = 0x80000004, 2529 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 2530 }, 2531 { 2532 .name = "kvm32", 2533 .level = 5, 2534 .vendor = CPUID_VENDOR_INTEL, 2535 .family = 15, 2536 .model = 6, 2537 .stepping = 1, 2538 .features[FEAT_1_EDX] = 2539 PPRO_FEATURES | CPUID_VME | 2540 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36, 2541 .features[FEAT_1_ECX] = 2542 CPUID_EXT_SSE3, 2543 .features[FEAT_8000_0001_ECX] = 2544 0, 2545 /* VMX features from Yonah */ 2546 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2547 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2548 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2549 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2550 VMX_PIN_BASED_NMI_EXITING, 2551 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2552 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2553 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2554 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2555 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 2556 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 2557 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS, 2558 .xlevel = 0x80000008, 2559 .model_id = "Common 32-bit KVM processor" 2560 }, 2561 { 2562 .name = "coreduo", 2563 .level = 10, 2564 .vendor = CPUID_VENDOR_INTEL, 2565 .family = 6, 2566 .model = 14, 2567 .stepping = 8, 2568 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2569 .features[FEAT_1_EDX] = 2570 PPRO_FEATURES | CPUID_VME | 2571 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI | 2572 CPUID_SS, 2573 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR, 2574 * CPUID_EXT_PDCM, CPUID_EXT_VMX */ 2575 .features[FEAT_1_ECX] = 2576 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR, 2577 .features[FEAT_8000_0001_EDX] = 2578 CPUID_EXT2_NX, 2579 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2580 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2581 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2582 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2583 VMX_PIN_BASED_NMI_EXITING, 2584 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2585 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2586 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2587 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2588 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 2589 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 2590 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS, 2591 .xlevel = 0x80000008, 2592 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz", 2593 }, 2594 { 2595 .name = "486", 2596 .level = 1, 2597 .vendor = CPUID_VENDOR_INTEL, 2598 .family = 4, 2599 .model = 8, 2600 .stepping = 0, 2601 .features[FEAT_1_EDX] = 2602 I486_FEATURES, 2603 .xlevel = 0, 2604 .model_id = "", 2605 }, 2606 { 2607 .name = "pentium", 2608 .level = 1, 2609 .vendor = CPUID_VENDOR_INTEL, 2610 .family = 5, 2611 .model = 4, 2612 .stepping = 3, 2613 .features[FEAT_1_EDX] = 2614 PENTIUM_FEATURES, 2615 .xlevel = 0, 2616 .model_id = "", 2617 }, 2618 { 2619 .name = "pentium2", 2620 .level = 2, 2621 .vendor = CPUID_VENDOR_INTEL, 2622 .family = 6, 2623 .model = 5, 2624 .stepping = 2, 2625 .features[FEAT_1_EDX] = 2626 PENTIUM2_FEATURES, 2627 .xlevel = 0, 2628 .model_id = "", 2629 }, 2630 { 2631 .name = "pentium3", 2632 .level = 3, 2633 .vendor = CPUID_VENDOR_INTEL, 2634 .family = 6, 2635 .model = 7, 2636 .stepping = 3, 2637 .features[FEAT_1_EDX] = 2638 PENTIUM3_FEATURES, 2639 .xlevel = 0, 2640 .model_id = "", 2641 }, 2642 { 2643 .name = "athlon", 2644 .level = 2, 2645 .vendor = CPUID_VENDOR_AMD, 2646 .family = 6, 2647 .model = 2, 2648 .stepping = 3, 2649 .features[FEAT_1_EDX] = 2650 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR | 2651 CPUID_MCA, 2652 .features[FEAT_8000_0001_EDX] = 2653 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT, 2654 .xlevel = 0x80000008, 2655 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 2656 }, 2657 { 2658 .name = "n270", 2659 .level = 10, 2660 .vendor = CPUID_VENDOR_INTEL, 2661 .family = 6, 2662 .model = 28, 2663 .stepping = 2, 2664 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2665 .features[FEAT_1_EDX] = 2666 PPRO_FEATURES | 2667 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | 2668 CPUID_ACPI | CPUID_SS, 2669 /* Some CPUs got no CPUID_SEP */ 2670 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2, 2671 * CPUID_EXT_XTPR */ 2672 .features[FEAT_1_ECX] = 2673 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | 2674 CPUID_EXT_MOVBE, 2675 .features[FEAT_8000_0001_EDX] = 2676 CPUID_EXT2_NX, 2677 .features[FEAT_8000_0001_ECX] = 2678 CPUID_EXT3_LAHF_LM, 2679 .xlevel = 0x80000008, 2680 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz", 2681 }, 2682 { 2683 .name = "Conroe", 2684 .level = 10, 2685 .vendor = CPUID_VENDOR_INTEL, 2686 .family = 6, 2687 .model = 15, 2688 .stepping = 3, 2689 .features[FEAT_1_EDX] = 2690 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2691 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2692 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2693 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2694 CPUID_DE | CPUID_FP87, 2695 .features[FEAT_1_ECX] = 2696 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, 2697 .features[FEAT_8000_0001_EDX] = 2698 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 2699 .features[FEAT_8000_0001_ECX] = 2700 CPUID_EXT3_LAHF_LM, 2701 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2702 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2703 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2704 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2705 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2706 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2707 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2708 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2709 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2710 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2711 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2712 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2713 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2714 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2715 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2716 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2717 .features[FEAT_VMX_SECONDARY_CTLS] = 2718 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES, 2719 .xlevel = 0x80000008, 2720 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)", 2721 }, 2722 { 2723 .name = "Penryn", 2724 .level = 10, 2725 .vendor = CPUID_VENDOR_INTEL, 2726 .family = 6, 2727 .model = 23, 2728 .stepping = 3, 2729 .features[FEAT_1_EDX] = 2730 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2731 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2732 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2733 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2734 CPUID_DE | CPUID_FP87, 2735 .features[FEAT_1_ECX] = 2736 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2737 CPUID_EXT_SSE3, 2738 .features[FEAT_8000_0001_EDX] = 2739 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 2740 .features[FEAT_8000_0001_ECX] = 2741 CPUID_EXT3_LAHF_LM, 2742 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2743 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2744 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, 2745 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT | 2746 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL, 2747 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2748 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2749 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2750 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2751 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2752 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2753 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2754 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2755 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2756 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2757 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2758 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2759 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2760 .features[FEAT_VMX_SECONDARY_CTLS] = 2761 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2762 VMX_SECONDARY_EXEC_WBINVD_EXITING, 2763 .xlevel = 0x80000008, 2764 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)", 2765 }, 2766 { 2767 .name = "Nehalem", 2768 .level = 11, 2769 .vendor = CPUID_VENDOR_INTEL, 2770 .family = 6, 2771 .model = 26, 2772 .stepping = 3, 2773 .features[FEAT_1_EDX] = 2774 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2775 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2776 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2777 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2778 CPUID_DE | CPUID_FP87, 2779 .features[FEAT_1_ECX] = 2780 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 2781 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, 2782 .features[FEAT_8000_0001_EDX] = 2783 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2784 .features[FEAT_8000_0001_ECX] = 2785 CPUID_EXT3_LAHF_LM, 2786 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2787 MSR_VMX_BASIC_TRUE_CTLS, 2788 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2789 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2790 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2791 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2792 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2793 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2794 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2795 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2796 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2797 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2798 .features[FEAT_VMX_EXIT_CTLS] = 2799 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2800 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2801 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2802 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2803 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2804 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2805 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2806 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2807 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2808 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2809 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2810 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2811 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2812 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2813 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2814 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2815 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2816 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2817 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2818 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2819 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2820 .features[FEAT_VMX_SECONDARY_CTLS] = 2821 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2822 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2823 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2824 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2825 VMX_SECONDARY_EXEC_ENABLE_VPID, 2826 .xlevel = 0x80000008, 2827 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)", 2828 .versions = (X86CPUVersionDefinition[]) { 2829 { .version = 1 }, 2830 { 2831 .version = 2, 2832 .alias = "Nehalem-IBRS", 2833 .props = (PropValue[]) { 2834 { "spec-ctrl", "on" }, 2835 { "model-id", 2836 "Intel Core i7 9xx (Nehalem Core i7, IBRS update)" }, 2837 { /* end of list */ } 2838 } 2839 }, 2840 { /* end of list */ } 2841 } 2842 }, 2843 { 2844 .name = "Westmere", 2845 .level = 11, 2846 .vendor = CPUID_VENDOR_INTEL, 2847 .family = 6, 2848 .model = 44, 2849 .stepping = 1, 2850 .features[FEAT_1_EDX] = 2851 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2852 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2853 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2854 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2855 CPUID_DE | CPUID_FP87, 2856 .features[FEAT_1_ECX] = 2857 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | 2858 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2859 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 2860 .features[FEAT_8000_0001_EDX] = 2861 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2862 .features[FEAT_8000_0001_ECX] = 2863 CPUID_EXT3_LAHF_LM, 2864 .features[FEAT_6_EAX] = 2865 CPUID_6_EAX_ARAT, 2866 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2867 MSR_VMX_BASIC_TRUE_CTLS, 2868 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2869 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2870 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2871 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2872 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2873 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2874 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2875 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2876 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2877 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2878 .features[FEAT_VMX_EXIT_CTLS] = 2879 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2880 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2881 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2882 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2883 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2884 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2885 MSR_VMX_MISC_STORE_LMA, 2886 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2887 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2888 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2889 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2890 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2891 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2892 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2893 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2894 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2895 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2896 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2897 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2898 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2899 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2900 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2901 .features[FEAT_VMX_SECONDARY_CTLS] = 2902 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2903 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2904 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2905 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2906 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST, 2907 .xlevel = 0x80000008, 2908 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)", 2909 .versions = (X86CPUVersionDefinition[]) { 2910 { .version = 1 }, 2911 { 2912 .version = 2, 2913 .alias = "Westmere-IBRS", 2914 .props = (PropValue[]) { 2915 { "spec-ctrl", "on" }, 2916 { "model-id", 2917 "Westmere E56xx/L56xx/X56xx (IBRS update)" }, 2918 { /* end of list */ } 2919 } 2920 }, 2921 { /* end of list */ } 2922 } 2923 }, 2924 { 2925 .name = "SandyBridge", 2926 .level = 0xd, 2927 .vendor = CPUID_VENDOR_INTEL, 2928 .family = 6, 2929 .model = 42, 2930 .stepping = 1, 2931 .features[FEAT_1_EDX] = 2932 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2933 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2934 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2935 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2936 CPUID_DE | CPUID_FP87, 2937 .features[FEAT_1_ECX] = 2938 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2939 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | 2940 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 2941 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 2942 CPUID_EXT_SSE3, 2943 .features[FEAT_8000_0001_EDX] = 2944 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 2945 CPUID_EXT2_SYSCALL, 2946 .features[FEAT_8000_0001_ECX] = 2947 CPUID_EXT3_LAHF_LM, 2948 .features[FEAT_XSAVE] = 2949 CPUID_XSAVE_XSAVEOPT, 2950 .features[FEAT_6_EAX] = 2951 CPUID_6_EAX_ARAT, 2952 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2953 MSR_VMX_BASIC_TRUE_CTLS, 2954 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2955 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2956 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2957 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2958 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2959 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2960 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2961 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2962 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2963 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2964 .features[FEAT_VMX_EXIT_CTLS] = 2965 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2966 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2967 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2968 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2969 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2970 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2971 MSR_VMX_MISC_STORE_LMA, 2972 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2973 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2974 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2975 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2976 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2977 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2978 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2979 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2980 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2981 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2982 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2983 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2984 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2985 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2986 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2987 .features[FEAT_VMX_SECONDARY_CTLS] = 2988 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2989 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2990 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2991 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2992 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST, 2993 .xlevel = 0x80000008, 2994 .model_id = "Intel Xeon E312xx (Sandy Bridge)", 2995 .versions = (X86CPUVersionDefinition[]) { 2996 { .version = 1 }, 2997 { 2998 .version = 2, 2999 .alias = "SandyBridge-IBRS", 3000 .props = (PropValue[]) { 3001 { "spec-ctrl", "on" }, 3002 { "model-id", 3003 "Intel Xeon E312xx (Sandy Bridge, IBRS update)" }, 3004 { /* end of list */ } 3005 } 3006 }, 3007 { /* end of list */ } 3008 } 3009 }, 3010 { 3011 .name = "IvyBridge", 3012 .level = 0xd, 3013 .vendor = CPUID_VENDOR_INTEL, 3014 .family = 6, 3015 .model = 58, 3016 .stepping = 9, 3017 .features[FEAT_1_EDX] = 3018 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3019 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3020 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3021 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3022 CPUID_DE | CPUID_FP87, 3023 .features[FEAT_1_ECX] = 3024 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3025 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | 3026 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 3027 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 3028 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3029 .features[FEAT_7_0_EBX] = 3030 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | 3031 CPUID_7_0_EBX_ERMS, 3032 .features[FEAT_8000_0001_EDX] = 3033 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3034 CPUID_EXT2_SYSCALL, 3035 .features[FEAT_8000_0001_ECX] = 3036 CPUID_EXT3_LAHF_LM, 3037 .features[FEAT_XSAVE] = 3038 CPUID_XSAVE_XSAVEOPT, 3039 .features[FEAT_6_EAX] = 3040 CPUID_6_EAX_ARAT, 3041 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3042 MSR_VMX_BASIC_TRUE_CTLS, 3043 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3044 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3045 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3046 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3047 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3048 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3049 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3050 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3051 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3052 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 3053 .features[FEAT_VMX_EXIT_CTLS] = 3054 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3055 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3056 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3057 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3058 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3059 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3060 MSR_VMX_MISC_STORE_LMA, 3061 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3062 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3063 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3064 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3065 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3066 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3067 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3068 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3069 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3070 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3071 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3072 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3073 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3074 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3075 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3076 .features[FEAT_VMX_SECONDARY_CTLS] = 3077 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3078 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3079 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3080 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3081 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3082 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3083 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3084 VMX_SECONDARY_EXEC_RDRAND_EXITING, 3085 .xlevel = 0x80000008, 3086 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)", 3087 .versions = (X86CPUVersionDefinition[]) { 3088 { .version = 1 }, 3089 { 3090 .version = 2, 3091 .alias = "IvyBridge-IBRS", 3092 .props = (PropValue[]) { 3093 { "spec-ctrl", "on" }, 3094 { "model-id", 3095 "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)" }, 3096 { /* end of list */ } 3097 } 3098 }, 3099 { /* end of list */ } 3100 } 3101 }, 3102 { 3103 .name = "Haswell", 3104 .level = 0xd, 3105 .vendor = CPUID_VENDOR_INTEL, 3106 .family = 6, 3107 .model = 60, 3108 .stepping = 4, 3109 .features[FEAT_1_EDX] = 3110 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3111 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3112 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3113 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3114 CPUID_DE | CPUID_FP87, 3115 .features[FEAT_1_ECX] = 3116 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3117 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3118 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3119 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3120 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3121 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3122 .features[FEAT_8000_0001_EDX] = 3123 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3124 CPUID_EXT2_SYSCALL, 3125 .features[FEAT_8000_0001_ECX] = 3126 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM, 3127 .features[FEAT_7_0_EBX] = 3128 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3129 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3130 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3131 CPUID_7_0_EBX_RTM, 3132 .features[FEAT_XSAVE] = 3133 CPUID_XSAVE_XSAVEOPT, 3134 .features[FEAT_6_EAX] = 3135 CPUID_6_EAX_ARAT, 3136 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3137 MSR_VMX_BASIC_TRUE_CTLS, 3138 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3139 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3140 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3141 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3142 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3143 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3144 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3145 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3146 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3147 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3148 .features[FEAT_VMX_EXIT_CTLS] = 3149 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3150 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3151 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3152 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3153 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3154 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3155 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3156 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3157 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3158 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3159 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3160 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3161 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3162 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3163 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3164 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3165 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3166 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3167 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3168 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3169 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3170 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3171 .features[FEAT_VMX_SECONDARY_CTLS] = 3172 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3173 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3174 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3175 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3176 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3177 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3178 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3179 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3180 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS, 3181 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3182 .xlevel = 0x80000008, 3183 .model_id = "Intel Core Processor (Haswell)", 3184 .versions = (X86CPUVersionDefinition[]) { 3185 { .version = 1 }, 3186 { 3187 .version = 2, 3188 .alias = "Haswell-noTSX", 3189 .props = (PropValue[]) { 3190 { "hle", "off" }, 3191 { "rtm", "off" }, 3192 { "stepping", "1" }, 3193 { "model-id", "Intel Core Processor (Haswell, no TSX)", }, 3194 { /* end of list */ } 3195 }, 3196 }, 3197 { 3198 .version = 3, 3199 .alias = "Haswell-IBRS", 3200 .props = (PropValue[]) { 3201 /* Restore TSX features removed by -v2 above */ 3202 { "hle", "on" }, 3203 { "rtm", "on" }, 3204 /* 3205 * Haswell and Haswell-IBRS had stepping=4 in 3206 * QEMU 4.0 and older 3207 */ 3208 { "stepping", "4" }, 3209 { "spec-ctrl", "on" }, 3210 { "model-id", 3211 "Intel Core Processor (Haswell, IBRS)" }, 3212 { /* end of list */ } 3213 } 3214 }, 3215 { 3216 .version = 4, 3217 .alias = "Haswell-noTSX-IBRS", 3218 .props = (PropValue[]) { 3219 { "hle", "off" }, 3220 { "rtm", "off" }, 3221 /* spec-ctrl was already enabled by -v3 above */ 3222 { "stepping", "1" }, 3223 { "model-id", 3224 "Intel Core Processor (Haswell, no TSX, IBRS)" }, 3225 { /* end of list */ } 3226 } 3227 }, 3228 { /* end of list */ } 3229 } 3230 }, 3231 { 3232 .name = "Broadwell", 3233 .level = 0xd, 3234 .vendor = CPUID_VENDOR_INTEL, 3235 .family = 6, 3236 .model = 61, 3237 .stepping = 2, 3238 .features[FEAT_1_EDX] = 3239 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3240 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3241 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3242 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3243 CPUID_DE | CPUID_FP87, 3244 .features[FEAT_1_ECX] = 3245 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3246 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3247 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3248 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3249 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3250 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3251 .features[FEAT_8000_0001_EDX] = 3252 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3253 CPUID_EXT2_SYSCALL, 3254 .features[FEAT_8000_0001_ECX] = 3255 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3256 .features[FEAT_7_0_EBX] = 3257 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3258 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3259 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3260 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3261 CPUID_7_0_EBX_SMAP, 3262 .features[FEAT_XSAVE] = 3263 CPUID_XSAVE_XSAVEOPT, 3264 .features[FEAT_6_EAX] = 3265 CPUID_6_EAX_ARAT, 3266 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3267 MSR_VMX_BASIC_TRUE_CTLS, 3268 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3269 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3270 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3271 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3272 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3273 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3274 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3275 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3276 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3277 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3278 .features[FEAT_VMX_EXIT_CTLS] = 3279 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3280 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3281 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3282 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3283 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3284 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3285 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3286 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3287 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3288 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3289 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3290 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3291 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3292 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3293 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3294 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3295 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3296 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3297 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3298 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3299 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3300 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3301 .features[FEAT_VMX_SECONDARY_CTLS] = 3302 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3303 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3304 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3305 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3306 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3307 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3308 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3309 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3310 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3311 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3312 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3313 .xlevel = 0x80000008, 3314 .model_id = "Intel Core Processor (Broadwell)", 3315 .versions = (X86CPUVersionDefinition[]) { 3316 { .version = 1 }, 3317 { 3318 .version = 2, 3319 .alias = "Broadwell-noTSX", 3320 .props = (PropValue[]) { 3321 { "hle", "off" }, 3322 { "rtm", "off" }, 3323 { "model-id", "Intel Core Processor (Broadwell, no TSX)", }, 3324 { /* end of list */ } 3325 }, 3326 }, 3327 { 3328 .version = 3, 3329 .alias = "Broadwell-IBRS", 3330 .props = (PropValue[]) { 3331 /* Restore TSX features removed by -v2 above */ 3332 { "hle", "on" }, 3333 { "rtm", "on" }, 3334 { "spec-ctrl", "on" }, 3335 { "model-id", 3336 "Intel Core Processor (Broadwell, IBRS)" }, 3337 { /* end of list */ } 3338 } 3339 }, 3340 { 3341 .version = 4, 3342 .alias = "Broadwell-noTSX-IBRS", 3343 .props = (PropValue[]) { 3344 { "hle", "off" }, 3345 { "rtm", "off" }, 3346 /* spec-ctrl was already enabled by -v3 above */ 3347 { "model-id", 3348 "Intel Core Processor (Broadwell, no TSX, IBRS)" }, 3349 { /* end of list */ } 3350 } 3351 }, 3352 { /* end of list */ } 3353 } 3354 }, 3355 { 3356 .name = "Skylake-Client", 3357 .level = 0xd, 3358 .vendor = CPUID_VENDOR_INTEL, 3359 .family = 6, 3360 .model = 94, 3361 .stepping = 3, 3362 .features[FEAT_1_EDX] = 3363 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3364 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3365 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3366 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3367 CPUID_DE | CPUID_FP87, 3368 .features[FEAT_1_ECX] = 3369 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3370 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3371 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3372 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3373 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3374 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3375 .features[FEAT_8000_0001_EDX] = 3376 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3377 CPUID_EXT2_SYSCALL, 3378 .features[FEAT_8000_0001_ECX] = 3379 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3380 .features[FEAT_7_0_EBX] = 3381 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3382 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3383 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3384 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3385 CPUID_7_0_EBX_SMAP, 3386 /* XSAVES is added in version 4 */ 3387 .features[FEAT_XSAVE] = 3388 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3389 CPUID_XSAVE_XGETBV1, 3390 .features[FEAT_6_EAX] = 3391 CPUID_6_EAX_ARAT, 3392 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3393 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3394 MSR_VMX_BASIC_TRUE_CTLS, 3395 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3396 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3397 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3398 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3399 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3400 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3401 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3402 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3403 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3404 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3405 .features[FEAT_VMX_EXIT_CTLS] = 3406 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3407 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3408 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3409 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3410 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3411 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3412 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3413 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3414 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3415 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 3416 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3417 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3418 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3419 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3420 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3421 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3422 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3423 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3424 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3425 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3426 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3427 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3428 .features[FEAT_VMX_SECONDARY_CTLS] = 3429 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3430 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3431 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3432 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3433 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3434 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3435 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3436 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3437 .xlevel = 0x80000008, 3438 .model_id = "Intel Core Processor (Skylake)", 3439 .versions = (X86CPUVersionDefinition[]) { 3440 { .version = 1 }, 3441 { 3442 .version = 2, 3443 .alias = "Skylake-Client-IBRS", 3444 .props = (PropValue[]) { 3445 { "spec-ctrl", "on" }, 3446 { "model-id", 3447 "Intel Core Processor (Skylake, IBRS)" }, 3448 { /* end of list */ } 3449 } 3450 }, 3451 { 3452 .version = 3, 3453 .alias = "Skylake-Client-noTSX-IBRS", 3454 .props = (PropValue[]) { 3455 { "hle", "off" }, 3456 { "rtm", "off" }, 3457 { "model-id", 3458 "Intel Core Processor (Skylake, IBRS, no TSX)" }, 3459 { /* end of list */ } 3460 } 3461 }, 3462 { 3463 .version = 4, 3464 .note = "IBRS, XSAVES, no TSX", 3465 .props = (PropValue[]) { 3466 { "xsaves", "on" }, 3467 { "vmx-xsaves", "on" }, 3468 { /* end of list */ } 3469 } 3470 }, 3471 { /* end of list */ } 3472 } 3473 }, 3474 { 3475 .name = "Skylake-Server", 3476 .level = 0xd, 3477 .vendor = CPUID_VENDOR_INTEL, 3478 .family = 6, 3479 .model = 85, 3480 .stepping = 4, 3481 .features[FEAT_1_EDX] = 3482 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3483 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3484 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3485 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3486 CPUID_DE | CPUID_FP87, 3487 .features[FEAT_1_ECX] = 3488 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3489 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3490 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3491 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3492 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3493 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3494 .features[FEAT_8000_0001_EDX] = 3495 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3496 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3497 .features[FEAT_8000_0001_ECX] = 3498 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3499 .features[FEAT_7_0_EBX] = 3500 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3501 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3502 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3503 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3504 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3505 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3506 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3507 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3508 .features[FEAT_7_0_ECX] = 3509 CPUID_7_0_ECX_PKU, 3510 /* XSAVES is added in version 5 */ 3511 .features[FEAT_XSAVE] = 3512 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3513 CPUID_XSAVE_XGETBV1, 3514 .features[FEAT_6_EAX] = 3515 CPUID_6_EAX_ARAT, 3516 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3517 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3518 MSR_VMX_BASIC_TRUE_CTLS, 3519 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3520 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3521 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3522 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3523 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3524 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3525 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3526 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3527 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3528 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3529 .features[FEAT_VMX_EXIT_CTLS] = 3530 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3531 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3532 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3533 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3534 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3535 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3536 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3537 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3538 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3539 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3540 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3541 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3542 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3543 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3544 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3545 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3546 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3547 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3548 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3549 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3550 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3551 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3552 .features[FEAT_VMX_SECONDARY_CTLS] = 3553 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3554 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3555 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3556 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3557 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3558 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3559 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3560 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3561 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3562 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3563 .xlevel = 0x80000008, 3564 .model_id = "Intel Xeon Processor (Skylake)", 3565 .versions = (X86CPUVersionDefinition[]) { 3566 { .version = 1 }, 3567 { 3568 .version = 2, 3569 .alias = "Skylake-Server-IBRS", 3570 .props = (PropValue[]) { 3571 /* clflushopt was not added to Skylake-Server-IBRS */ 3572 /* TODO: add -v3 including clflushopt */ 3573 { "clflushopt", "off" }, 3574 { "spec-ctrl", "on" }, 3575 { "model-id", 3576 "Intel Xeon Processor (Skylake, IBRS)" }, 3577 { /* end of list */ } 3578 } 3579 }, 3580 { 3581 .version = 3, 3582 .alias = "Skylake-Server-noTSX-IBRS", 3583 .props = (PropValue[]) { 3584 { "hle", "off" }, 3585 { "rtm", "off" }, 3586 { "model-id", 3587 "Intel Xeon Processor (Skylake, IBRS, no TSX)" }, 3588 { /* end of list */ } 3589 } 3590 }, 3591 { 3592 .version = 4, 3593 .props = (PropValue[]) { 3594 { "vmx-eptp-switching", "on" }, 3595 { /* end of list */ } 3596 } 3597 }, 3598 { 3599 .version = 5, 3600 .note = "IBRS, XSAVES, EPT switching, no TSX", 3601 .props = (PropValue[]) { 3602 { "xsaves", "on" }, 3603 { "vmx-xsaves", "on" }, 3604 { /* end of list */ } 3605 } 3606 }, 3607 { /* end of list */ } 3608 } 3609 }, 3610 { 3611 .name = "Cascadelake-Server", 3612 .level = 0xd, 3613 .vendor = CPUID_VENDOR_INTEL, 3614 .family = 6, 3615 .model = 85, 3616 .stepping = 6, 3617 .features[FEAT_1_EDX] = 3618 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3619 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3620 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3621 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3622 CPUID_DE | CPUID_FP87, 3623 .features[FEAT_1_ECX] = 3624 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3625 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3626 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3627 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3628 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3629 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3630 .features[FEAT_8000_0001_EDX] = 3631 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3632 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3633 .features[FEAT_8000_0001_ECX] = 3634 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3635 .features[FEAT_7_0_EBX] = 3636 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3637 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3638 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3639 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3640 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3641 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3642 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3643 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3644 .features[FEAT_7_0_ECX] = 3645 CPUID_7_0_ECX_PKU | 3646 CPUID_7_0_ECX_AVX512VNNI, 3647 .features[FEAT_7_0_EDX] = 3648 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 3649 /* XSAVES is added in version 5 */ 3650 .features[FEAT_XSAVE] = 3651 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3652 CPUID_XSAVE_XGETBV1, 3653 .features[FEAT_6_EAX] = 3654 CPUID_6_EAX_ARAT, 3655 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3656 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3657 MSR_VMX_BASIC_TRUE_CTLS, 3658 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3659 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3660 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3661 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3662 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3663 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3664 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3665 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3666 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3667 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3668 .features[FEAT_VMX_EXIT_CTLS] = 3669 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3670 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3671 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3672 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3673 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3674 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3675 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3676 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3677 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3678 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3679 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3680 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3681 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3682 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3683 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3684 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3685 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3686 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3687 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3688 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3689 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3690 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3691 .features[FEAT_VMX_SECONDARY_CTLS] = 3692 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3693 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3694 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3695 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3696 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3697 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3698 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3699 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3700 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3701 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3702 .xlevel = 0x80000008, 3703 .model_id = "Intel Xeon Processor (Cascadelake)", 3704 .versions = (X86CPUVersionDefinition[]) { 3705 { .version = 1 }, 3706 { .version = 2, 3707 .note = "ARCH_CAPABILITIES", 3708 .props = (PropValue[]) { 3709 { "arch-capabilities", "on" }, 3710 { "rdctl-no", "on" }, 3711 { "ibrs-all", "on" }, 3712 { "skip-l1dfl-vmentry", "on" }, 3713 { "mds-no", "on" }, 3714 { /* end of list */ } 3715 }, 3716 }, 3717 { .version = 3, 3718 .alias = "Cascadelake-Server-noTSX", 3719 .note = "ARCH_CAPABILITIES, no TSX", 3720 .props = (PropValue[]) { 3721 { "hle", "off" }, 3722 { "rtm", "off" }, 3723 { /* end of list */ } 3724 }, 3725 }, 3726 { .version = 4, 3727 .note = "ARCH_CAPABILITIES, no TSX", 3728 .props = (PropValue[]) { 3729 { "vmx-eptp-switching", "on" }, 3730 { /* end of list */ } 3731 }, 3732 }, 3733 { .version = 5, 3734 .note = "ARCH_CAPABILITIES, EPT switching, XSAVES, no TSX", 3735 .props = (PropValue[]) { 3736 { "xsaves", "on" }, 3737 { "vmx-xsaves", "on" }, 3738 { /* end of list */ } 3739 }, 3740 }, 3741 { /* end of list */ } 3742 } 3743 }, 3744 { 3745 .name = "Cooperlake", 3746 .level = 0xd, 3747 .vendor = CPUID_VENDOR_INTEL, 3748 .family = 6, 3749 .model = 85, 3750 .stepping = 10, 3751 .features[FEAT_1_EDX] = 3752 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3753 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3754 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3755 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3756 CPUID_DE | CPUID_FP87, 3757 .features[FEAT_1_ECX] = 3758 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3759 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3760 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3761 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3762 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3763 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3764 .features[FEAT_8000_0001_EDX] = 3765 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3766 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3767 .features[FEAT_8000_0001_ECX] = 3768 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3769 .features[FEAT_7_0_EBX] = 3770 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3771 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3772 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3773 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3774 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3775 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3776 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3777 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3778 .features[FEAT_7_0_ECX] = 3779 CPUID_7_0_ECX_PKU | 3780 CPUID_7_0_ECX_AVX512VNNI, 3781 .features[FEAT_7_0_EDX] = 3782 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_STIBP | 3783 CPUID_7_0_EDX_SPEC_CTRL_SSBD | CPUID_7_0_EDX_ARCH_CAPABILITIES, 3784 .features[FEAT_ARCH_CAPABILITIES] = 3785 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 3786 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 3787 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO, 3788 .features[FEAT_7_1_EAX] = 3789 CPUID_7_1_EAX_AVX512_BF16, 3790 /* XSAVES is added in version 2 */ 3791 .features[FEAT_XSAVE] = 3792 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3793 CPUID_XSAVE_XGETBV1, 3794 .features[FEAT_6_EAX] = 3795 CPUID_6_EAX_ARAT, 3796 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3797 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3798 MSR_VMX_BASIC_TRUE_CTLS, 3799 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3800 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3801 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3802 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3803 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3804 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3805 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3806 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3807 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3808 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3809 .features[FEAT_VMX_EXIT_CTLS] = 3810 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3811 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3812 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3813 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3814 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3815 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3816 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3817 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3818 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3819 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3820 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3821 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3822 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3823 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3824 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3825 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3826 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3827 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3828 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3829 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3830 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3831 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3832 .features[FEAT_VMX_SECONDARY_CTLS] = 3833 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3834 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3835 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3836 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3837 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3838 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3839 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3840 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3841 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3842 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3843 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3844 .xlevel = 0x80000008, 3845 .model_id = "Intel Xeon Processor (Cooperlake)", 3846 .versions = (X86CPUVersionDefinition[]) { 3847 { .version = 1 }, 3848 { .version = 2, 3849 .note = "XSAVES", 3850 .props = (PropValue[]) { 3851 { "xsaves", "on" }, 3852 { "vmx-xsaves", "on" }, 3853 { /* end of list */ } 3854 }, 3855 }, 3856 { /* end of list */ } 3857 } 3858 }, 3859 { 3860 .name = "Icelake-Server", 3861 .level = 0xd, 3862 .vendor = CPUID_VENDOR_INTEL, 3863 .family = 6, 3864 .model = 134, 3865 .stepping = 0, 3866 .features[FEAT_1_EDX] = 3867 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3868 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3869 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3870 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3871 CPUID_DE | CPUID_FP87, 3872 .features[FEAT_1_ECX] = 3873 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3874 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3875 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3876 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3877 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3878 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3879 .features[FEAT_8000_0001_EDX] = 3880 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3881 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3882 .features[FEAT_8000_0001_ECX] = 3883 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3884 .features[FEAT_8000_0008_EBX] = 3885 CPUID_8000_0008_EBX_WBNOINVD, 3886 .features[FEAT_7_0_EBX] = 3887 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3888 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3889 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3890 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3891 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3892 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3893 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3894 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3895 .features[FEAT_7_0_ECX] = 3896 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 3897 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 3898 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 3899 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 3900 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57, 3901 .features[FEAT_7_0_EDX] = 3902 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 3903 /* XSAVES is added in version 5 */ 3904 .features[FEAT_XSAVE] = 3905 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3906 CPUID_XSAVE_XGETBV1, 3907 .features[FEAT_6_EAX] = 3908 CPUID_6_EAX_ARAT, 3909 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3910 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3911 MSR_VMX_BASIC_TRUE_CTLS, 3912 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3913 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3914 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3915 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3916 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3917 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3918 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3919 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3920 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3921 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3922 .features[FEAT_VMX_EXIT_CTLS] = 3923 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3924 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3925 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3926 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3927 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3928 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3929 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3930 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3931 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3932 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3933 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3934 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3935 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3936 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3937 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3938 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3939 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3940 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3941 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3942 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3943 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3944 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3945 .features[FEAT_VMX_SECONDARY_CTLS] = 3946 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3947 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3948 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3949 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3950 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3951 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3952 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3953 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3954 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS, 3955 .xlevel = 0x80000008, 3956 .model_id = "Intel Xeon Processor (Icelake)", 3957 .versions = (X86CPUVersionDefinition[]) { 3958 { .version = 1 }, 3959 { 3960 .version = 2, 3961 .note = "no TSX", 3962 .alias = "Icelake-Server-noTSX", 3963 .props = (PropValue[]) { 3964 { "hle", "off" }, 3965 { "rtm", "off" }, 3966 { /* end of list */ } 3967 }, 3968 }, 3969 { 3970 .version = 3, 3971 .props = (PropValue[]) { 3972 { "arch-capabilities", "on" }, 3973 { "rdctl-no", "on" }, 3974 { "ibrs-all", "on" }, 3975 { "skip-l1dfl-vmentry", "on" }, 3976 { "mds-no", "on" }, 3977 { "pschange-mc-no", "on" }, 3978 { "taa-no", "on" }, 3979 { /* end of list */ } 3980 }, 3981 }, 3982 { 3983 .version = 4, 3984 .props = (PropValue[]) { 3985 { "sha-ni", "on" }, 3986 { "avx512ifma", "on" }, 3987 { "rdpid", "on" }, 3988 { "fsrm", "on" }, 3989 { "vmx-rdseed-exit", "on" }, 3990 { "vmx-pml", "on" }, 3991 { "vmx-eptp-switching", "on" }, 3992 { "model", "106" }, 3993 { /* end of list */ } 3994 }, 3995 }, 3996 { 3997 .version = 5, 3998 .note = "XSAVES", 3999 .props = (PropValue[]) { 4000 { "xsaves", "on" }, 4001 { "vmx-xsaves", "on" }, 4002 { /* end of list */ } 4003 }, 4004 }, 4005 { 4006 .version = 6, 4007 .note = "5-level EPT", 4008 .props = (PropValue[]) { 4009 { "vmx-page-walk-5", "on" }, 4010 { /* end of list */ } 4011 }, 4012 }, 4013 { 4014 .version = 7, 4015 .note = "TSX, taa-no", 4016 .props = (PropValue[]) { 4017 /* Restore TSX features removed by -v2 above */ 4018 { "hle", "on" }, 4019 { "rtm", "on" }, 4020 { /* end of list */ } 4021 }, 4022 }, 4023 { /* end of list */ } 4024 } 4025 }, 4026 { 4027 .name = "SapphireRapids", 4028 .level = 0x20, 4029 .vendor = CPUID_VENDOR_INTEL, 4030 .family = 6, 4031 .model = 143, 4032 .stepping = 4, 4033 /* 4034 * please keep the ascending order so that we can have a clear view of 4035 * bit position of each feature. 4036 */ 4037 .features[FEAT_1_EDX] = 4038 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4039 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4040 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4041 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4042 CPUID_SSE | CPUID_SSE2, 4043 .features[FEAT_1_ECX] = 4044 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 4045 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 4046 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4047 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 4048 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4049 .features[FEAT_8000_0001_EDX] = 4050 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4051 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4052 .features[FEAT_8000_0001_ECX] = 4053 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 4054 .features[FEAT_8000_0008_EBX] = 4055 CPUID_8000_0008_EBX_WBNOINVD, 4056 .features[FEAT_7_0_EBX] = 4057 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_HLE | 4058 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | 4059 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RTM | 4060 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 4061 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | 4062 CPUID_7_0_EBX_AVX512IFMA | CPUID_7_0_EBX_CLFLUSHOPT | 4063 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | 4064 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, 4065 .features[FEAT_7_0_ECX] = 4066 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 4067 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 4068 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4069 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 4070 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | 4071 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT, 4072 .features[FEAT_7_0_EDX] = 4073 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 4074 CPUID_7_0_EDX_TSX_LDTRK | CPUID_7_0_EDX_AMX_BF16 | 4075 CPUID_7_0_EDX_AVX512_FP16 | CPUID_7_0_EDX_AMX_TILE | 4076 CPUID_7_0_EDX_AMX_INT8 | CPUID_7_0_EDX_SPEC_CTRL | 4077 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4078 .features[FEAT_ARCH_CAPABILITIES] = 4079 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 4080 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 4081 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO, 4082 .features[FEAT_XSAVE] = 4083 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4084 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES | CPUID_D_1_EAX_XFD, 4085 .features[FEAT_6_EAX] = 4086 CPUID_6_EAX_ARAT, 4087 .features[FEAT_7_1_EAX] = 4088 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_AVX512_BF16 | 4089 CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC, 4090 .features[FEAT_VMX_BASIC] = 4091 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 4092 .features[FEAT_VMX_ENTRY_CTLS] = 4093 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 4094 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 4095 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 4096 .features[FEAT_VMX_EPT_VPID_CAPS] = 4097 MSR_VMX_EPT_EXECONLY | 4098 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_PAGE_WALK_LENGTH_5 | 4099 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 4100 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 4101 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4102 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4103 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 4104 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4105 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 4106 .features[FEAT_VMX_EXIT_CTLS] = 4107 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4108 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4109 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 4110 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4111 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4112 .features[FEAT_VMX_MISC] = 4113 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 4114 MSR_VMX_MISC_VMWRITE_VMEXIT, 4115 .features[FEAT_VMX_PINBASED_CTLS] = 4116 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 4117 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 4118 VMX_PIN_BASED_POSTED_INTR, 4119 .features[FEAT_VMX_PROCBASED_CTLS] = 4120 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4121 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4122 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4123 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4124 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4125 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4126 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 4127 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 4128 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4129 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 4130 VMX_CPU_BASED_PAUSE_EXITING | 4131 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4132 .features[FEAT_VMX_SECONDARY_CTLS] = 4133 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4134 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 4135 VMX_SECONDARY_EXEC_RDTSCP | 4136 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4137 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 4138 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4139 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4140 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4141 VMX_SECONDARY_EXEC_RDRAND_EXITING | 4142 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4143 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4144 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 4145 VMX_SECONDARY_EXEC_XSAVES, 4146 .features[FEAT_VMX_VMFUNC] = 4147 MSR_VMX_VMFUNC_EPT_SWITCHING, 4148 .xlevel = 0x80000008, 4149 .model_id = "Intel Xeon Processor (SapphireRapids)", 4150 .versions = (X86CPUVersionDefinition[]) { 4151 { .version = 1 }, 4152 { 4153 .version = 2, 4154 .props = (PropValue[]) { 4155 { "sbdr-ssdp-no", "on" }, 4156 { "fbsdp-no", "on" }, 4157 { "psdp-no", "on" }, 4158 { /* end of list */ } 4159 } 4160 }, 4161 { 4162 .version = 3, 4163 .props = (PropValue[]) { 4164 { "ss", "on" }, 4165 { "tsc-adjust", "on" }, 4166 { "cldemote", "on" }, 4167 { "movdiri", "on" }, 4168 { "movdir64b", "on" }, 4169 { /* end of list */ } 4170 } 4171 }, 4172 { /* end of list */ } 4173 } 4174 }, 4175 { 4176 .name = "GraniteRapids", 4177 .level = 0x20, 4178 .vendor = CPUID_VENDOR_INTEL, 4179 .family = 6, 4180 .model = 173, 4181 .stepping = 0, 4182 /* 4183 * please keep the ascending order so that we can have a clear view of 4184 * bit position of each feature. 4185 */ 4186 .features[FEAT_1_EDX] = 4187 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4188 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4189 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4190 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4191 CPUID_SSE | CPUID_SSE2, 4192 .features[FEAT_1_ECX] = 4193 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 4194 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 4195 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4196 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 4197 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4198 .features[FEAT_8000_0001_EDX] = 4199 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4200 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4201 .features[FEAT_8000_0001_ECX] = 4202 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 4203 .features[FEAT_8000_0008_EBX] = 4204 CPUID_8000_0008_EBX_WBNOINVD, 4205 .features[FEAT_7_0_EBX] = 4206 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_HLE | 4207 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | 4208 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RTM | 4209 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 4210 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | 4211 CPUID_7_0_EBX_AVX512IFMA | CPUID_7_0_EBX_CLFLUSHOPT | 4212 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | 4213 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, 4214 .features[FEAT_7_0_ECX] = 4215 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 4216 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 4217 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4218 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 4219 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | 4220 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT, 4221 .features[FEAT_7_0_EDX] = 4222 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 4223 CPUID_7_0_EDX_TSX_LDTRK | CPUID_7_0_EDX_AMX_BF16 | 4224 CPUID_7_0_EDX_AVX512_FP16 | CPUID_7_0_EDX_AMX_TILE | 4225 CPUID_7_0_EDX_AMX_INT8 | CPUID_7_0_EDX_SPEC_CTRL | 4226 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4227 .features[FEAT_ARCH_CAPABILITIES] = 4228 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 4229 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 4230 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO | 4231 MSR_ARCH_CAP_SBDR_SSDP_NO | MSR_ARCH_CAP_FBSDP_NO | 4232 MSR_ARCH_CAP_PSDP_NO | MSR_ARCH_CAP_PBRSB_NO, 4233 .features[FEAT_XSAVE] = 4234 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4235 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES | CPUID_D_1_EAX_XFD, 4236 .features[FEAT_6_EAX] = 4237 CPUID_6_EAX_ARAT, 4238 .features[FEAT_7_1_EAX] = 4239 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_AVX512_BF16 | 4240 CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC | 4241 CPUID_7_1_EAX_AMX_FP16, 4242 .features[FEAT_7_1_EDX] = 4243 CPUID_7_1_EDX_PREFETCHITI, 4244 .features[FEAT_7_2_EDX] = 4245 CPUID_7_2_EDX_MCDT_NO, 4246 .features[FEAT_VMX_BASIC] = 4247 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 4248 .features[FEAT_VMX_ENTRY_CTLS] = 4249 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 4250 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 4251 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 4252 .features[FEAT_VMX_EPT_VPID_CAPS] = 4253 MSR_VMX_EPT_EXECONLY | 4254 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_PAGE_WALK_LENGTH_5 | 4255 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 4256 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 4257 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4258 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4259 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 4260 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4261 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 4262 .features[FEAT_VMX_EXIT_CTLS] = 4263 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4264 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4265 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 4266 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4267 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4268 .features[FEAT_VMX_MISC] = 4269 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 4270 MSR_VMX_MISC_VMWRITE_VMEXIT, 4271 .features[FEAT_VMX_PINBASED_CTLS] = 4272 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 4273 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 4274 VMX_PIN_BASED_POSTED_INTR, 4275 .features[FEAT_VMX_PROCBASED_CTLS] = 4276 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4277 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4278 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4279 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4280 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4281 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4282 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 4283 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 4284 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4285 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 4286 VMX_CPU_BASED_PAUSE_EXITING | 4287 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4288 .features[FEAT_VMX_SECONDARY_CTLS] = 4289 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4290 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 4291 VMX_SECONDARY_EXEC_RDTSCP | 4292 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4293 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 4294 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4295 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4296 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4297 VMX_SECONDARY_EXEC_RDRAND_EXITING | 4298 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4299 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4300 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 4301 VMX_SECONDARY_EXEC_XSAVES, 4302 .features[FEAT_VMX_VMFUNC] = 4303 MSR_VMX_VMFUNC_EPT_SWITCHING, 4304 .xlevel = 0x80000008, 4305 .model_id = "Intel Xeon Processor (GraniteRapids)", 4306 .versions = (X86CPUVersionDefinition[]) { 4307 { .version = 1 }, 4308 { /* end of list */ }, 4309 }, 4310 }, 4311 { 4312 .name = "SierraForest", 4313 .level = 0x23, 4314 .vendor = CPUID_VENDOR_INTEL, 4315 .family = 6, 4316 .model = 175, 4317 .stepping = 0, 4318 /* 4319 * please keep the ascending order so that we can have a clear view of 4320 * bit position of each feature. 4321 */ 4322 .features[FEAT_1_EDX] = 4323 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4324 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4325 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4326 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4327 CPUID_SSE | CPUID_SSE2, 4328 .features[FEAT_1_ECX] = 4329 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 4330 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 4331 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4332 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 4333 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4334 .features[FEAT_8000_0001_EDX] = 4335 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4336 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4337 .features[FEAT_8000_0001_ECX] = 4338 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 4339 .features[FEAT_8000_0008_EBX] = 4340 CPUID_8000_0008_EBX_WBNOINVD, 4341 .features[FEAT_7_0_EBX] = 4342 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4343 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 4344 CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 4345 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB | 4346 CPUID_7_0_EBX_SHA_NI, 4347 .features[FEAT_7_0_ECX] = 4348 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_GFNI | 4349 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4350 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT, 4351 .features[FEAT_7_0_EDX] = 4352 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 4353 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES | 4354 CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4355 .features[FEAT_ARCH_CAPABILITIES] = 4356 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 4357 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 4358 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_SBDR_SSDP_NO | 4359 MSR_ARCH_CAP_FBSDP_NO | MSR_ARCH_CAP_PSDP_NO | 4360 MSR_ARCH_CAP_PBRSB_NO, 4361 .features[FEAT_XSAVE] = 4362 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4363 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 4364 .features[FEAT_6_EAX] = 4365 CPUID_6_EAX_ARAT, 4366 .features[FEAT_7_1_EAX] = 4367 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_CMPCCXADD | 4368 CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_AVX_IFMA, 4369 .features[FEAT_7_1_EDX] = 4370 CPUID_7_1_EDX_AVX_VNNI_INT8 | CPUID_7_1_EDX_AVX_NE_CONVERT, 4371 .features[FEAT_7_2_EDX] = 4372 CPUID_7_2_EDX_MCDT_NO, 4373 .features[FEAT_VMX_BASIC] = 4374 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 4375 .features[FEAT_VMX_ENTRY_CTLS] = 4376 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 4377 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 4378 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 4379 .features[FEAT_VMX_EPT_VPID_CAPS] = 4380 MSR_VMX_EPT_EXECONLY | MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | 4381 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 4382 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 4383 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4384 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4385 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 4386 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4387 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 4388 .features[FEAT_VMX_EXIT_CTLS] = 4389 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4390 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4391 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 4392 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4393 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4394 .features[FEAT_VMX_MISC] = 4395 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 4396 MSR_VMX_MISC_VMWRITE_VMEXIT, 4397 .features[FEAT_VMX_PINBASED_CTLS] = 4398 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 4399 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 4400 VMX_PIN_BASED_POSTED_INTR, 4401 .features[FEAT_VMX_PROCBASED_CTLS] = 4402 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4403 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4404 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4405 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4406 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4407 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4408 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 4409 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 4410 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4411 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 4412 VMX_CPU_BASED_PAUSE_EXITING | 4413 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4414 .features[FEAT_VMX_SECONDARY_CTLS] = 4415 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4416 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 4417 VMX_SECONDARY_EXEC_RDTSCP | 4418 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4419 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 4420 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4421 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4422 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4423 VMX_SECONDARY_EXEC_RDRAND_EXITING | 4424 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4425 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4426 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 4427 VMX_SECONDARY_EXEC_XSAVES, 4428 .features[FEAT_VMX_VMFUNC] = 4429 MSR_VMX_VMFUNC_EPT_SWITCHING, 4430 .xlevel = 0x80000008, 4431 .model_id = "Intel Xeon Processor (SierraForest)", 4432 .versions = (X86CPUVersionDefinition[]) { 4433 { .version = 1 }, 4434 { /* end of list */ }, 4435 }, 4436 }, 4437 { 4438 .name = "Denverton", 4439 .level = 21, 4440 .vendor = CPUID_VENDOR_INTEL, 4441 .family = 6, 4442 .model = 95, 4443 .stepping = 1, 4444 .features[FEAT_1_EDX] = 4445 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4446 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4447 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4448 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4449 CPUID_SSE | CPUID_SSE2, 4450 .features[FEAT_1_ECX] = 4451 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR | 4452 CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_SSE41 | 4453 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4454 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | 4455 CPUID_EXT_AES | CPUID_EXT_XSAVE | CPUID_EXT_RDRAND, 4456 .features[FEAT_8000_0001_EDX] = 4457 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4458 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4459 .features[FEAT_8000_0001_ECX] = 4460 CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 4461 .features[FEAT_7_0_EBX] = 4462 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_ERMS | 4463 CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_SMAP | 4464 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_SHA_NI, 4465 .features[FEAT_7_0_EDX] = 4466 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES | 4467 CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4468 /* XSAVES is added in version 3 */ 4469 .features[FEAT_XSAVE] = 4470 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | CPUID_XSAVE_XGETBV1, 4471 .features[FEAT_6_EAX] = 4472 CPUID_6_EAX_ARAT, 4473 .features[FEAT_ARCH_CAPABILITIES] = 4474 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY, 4475 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 4476 MSR_VMX_BASIC_TRUE_CTLS, 4477 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 4478 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 4479 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 4480 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 4481 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 4482 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 4483 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4484 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4485 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4486 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 4487 .features[FEAT_VMX_EXIT_CTLS] = 4488 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4489 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4490 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 4491 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4492 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4493 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 4494 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 4495 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 4496 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 4497 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 4498 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4499 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4500 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4501 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4502 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4503 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 4504 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 4505 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 4506 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 4507 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4508 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4509 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4510 .features[FEAT_VMX_SECONDARY_CTLS] = 4511 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4512 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 4513 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 4514 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4515 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4516 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4517 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4518 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4519 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4520 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 4521 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 4522 .xlevel = 0x80000008, 4523 .model_id = "Intel Atom Processor (Denverton)", 4524 .versions = (X86CPUVersionDefinition[]) { 4525 { .version = 1 }, 4526 { 4527 .version = 2, 4528 .note = "no MPX, no MONITOR", 4529 .props = (PropValue[]) { 4530 { "monitor", "off" }, 4531 { "mpx", "off" }, 4532 { /* end of list */ }, 4533 }, 4534 }, 4535 { 4536 .version = 3, 4537 .note = "XSAVES, no MPX, no MONITOR", 4538 .props = (PropValue[]) { 4539 { "xsaves", "on" }, 4540 { "vmx-xsaves", "on" }, 4541 { /* end of list */ }, 4542 }, 4543 }, 4544 { /* end of list */ }, 4545 }, 4546 }, 4547 { 4548 .name = "Snowridge", 4549 .level = 27, 4550 .vendor = CPUID_VENDOR_INTEL, 4551 .family = 6, 4552 .model = 134, 4553 .stepping = 1, 4554 .features[FEAT_1_EDX] = 4555 /* missing: CPUID_PN CPUID_IA64 */ 4556 /* missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 4557 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | 4558 CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_MCE | 4559 CPUID_CX8 | CPUID_APIC | CPUID_SEP | 4560 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4561 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | 4562 CPUID_MMX | 4563 CPUID_FXSR | CPUID_SSE | CPUID_SSE2, 4564 .features[FEAT_1_ECX] = 4565 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR | 4566 CPUID_EXT_SSSE3 | 4567 CPUID_EXT_CX16 | 4568 CPUID_EXT_SSE41 | 4569 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4570 CPUID_EXT_POPCNT | 4571 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | CPUID_EXT_XSAVE | 4572 CPUID_EXT_RDRAND, 4573 .features[FEAT_8000_0001_EDX] = 4574 CPUID_EXT2_SYSCALL | 4575 CPUID_EXT2_NX | 4576 CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 4577 CPUID_EXT2_LM, 4578 .features[FEAT_8000_0001_ECX] = 4579 CPUID_EXT3_LAHF_LM | 4580 CPUID_EXT3_3DNOWPREFETCH, 4581 .features[FEAT_7_0_EBX] = 4582 CPUID_7_0_EBX_FSGSBASE | 4583 CPUID_7_0_EBX_SMEP | 4584 CPUID_7_0_EBX_ERMS | 4585 CPUID_7_0_EBX_MPX | /* missing bits 13, 15 */ 4586 CPUID_7_0_EBX_RDSEED | 4587 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 4588 CPUID_7_0_EBX_CLWB | 4589 CPUID_7_0_EBX_SHA_NI, 4590 .features[FEAT_7_0_ECX] = 4591 CPUID_7_0_ECX_UMIP | 4592 /* missing bit 5 */ 4593 CPUID_7_0_ECX_GFNI | 4594 CPUID_7_0_ECX_MOVDIRI | CPUID_7_0_ECX_CLDEMOTE | 4595 CPUID_7_0_ECX_MOVDIR64B, 4596 .features[FEAT_7_0_EDX] = 4597 CPUID_7_0_EDX_SPEC_CTRL | 4598 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD | 4599 CPUID_7_0_EDX_CORE_CAPABILITY, 4600 .features[FEAT_CORE_CAPABILITY] = 4601 MSR_CORE_CAP_SPLIT_LOCK_DETECT, 4602 /* XSAVES is added in version 3 */ 4603 .features[FEAT_XSAVE] = 4604 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4605 CPUID_XSAVE_XGETBV1, 4606 .features[FEAT_6_EAX] = 4607 CPUID_6_EAX_ARAT, 4608 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 4609 MSR_VMX_BASIC_TRUE_CTLS, 4610 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 4611 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 4612 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 4613 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 4614 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 4615 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 4616 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4617 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4618 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4619 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 4620 .features[FEAT_VMX_EXIT_CTLS] = 4621 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4622 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4623 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 4624 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4625 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4626 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 4627 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 4628 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 4629 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 4630 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 4631 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4632 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4633 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4634 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4635 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4636 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 4637 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 4638 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 4639 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 4640 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4641 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4642 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4643 .features[FEAT_VMX_SECONDARY_CTLS] = 4644 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4645 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 4646 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 4647 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4648 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4649 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4650 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4651 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4652 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4653 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 4654 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 4655 .xlevel = 0x80000008, 4656 .model_id = "Intel Atom Processor (SnowRidge)", 4657 .versions = (X86CPUVersionDefinition[]) { 4658 { .version = 1 }, 4659 { 4660 .version = 2, 4661 .props = (PropValue[]) { 4662 { "mpx", "off" }, 4663 { "model-id", "Intel Atom Processor (Snowridge, no MPX)" }, 4664 { /* end of list */ }, 4665 }, 4666 }, 4667 { 4668 .version = 3, 4669 .note = "XSAVES, no MPX", 4670 .props = (PropValue[]) { 4671 { "xsaves", "on" }, 4672 { "vmx-xsaves", "on" }, 4673 { /* end of list */ }, 4674 }, 4675 }, 4676 { 4677 .version = 4, 4678 .note = "no split lock detect, no core-capability", 4679 .props = (PropValue[]) { 4680 { "split-lock-detect", "off" }, 4681 { "core-capability", "off" }, 4682 { /* end of list */ }, 4683 }, 4684 }, 4685 { /* end of list */ }, 4686 }, 4687 }, 4688 { 4689 .name = "KnightsMill", 4690 .level = 0xd, 4691 .vendor = CPUID_VENDOR_INTEL, 4692 .family = 6, 4693 .model = 133, 4694 .stepping = 0, 4695 .features[FEAT_1_EDX] = 4696 CPUID_VME | CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | 4697 CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | 4698 CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | 4699 CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | 4700 CPUID_PSE | CPUID_DE | CPUID_FP87, 4701 .features[FEAT_1_ECX] = 4702 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 4703 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 4704 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 4705 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 4706 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 4707 CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4708 .features[FEAT_8000_0001_EDX] = 4709 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 4710 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 4711 .features[FEAT_8000_0001_ECX] = 4712 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 4713 .features[FEAT_7_0_EBX] = 4714 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4715 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 4716 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_AVX512F | 4717 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_AVX512PF | 4718 CPUID_7_0_EBX_AVX512ER, 4719 .features[FEAT_7_0_ECX] = 4720 CPUID_7_0_ECX_AVX512_VPOPCNTDQ, 4721 .features[FEAT_7_0_EDX] = 4722 CPUID_7_0_EDX_AVX512_4VNNIW | CPUID_7_0_EDX_AVX512_4FMAPS, 4723 .features[FEAT_XSAVE] = 4724 CPUID_XSAVE_XSAVEOPT, 4725 .features[FEAT_6_EAX] = 4726 CPUID_6_EAX_ARAT, 4727 .xlevel = 0x80000008, 4728 .model_id = "Intel Xeon Phi Processor (Knights Mill)", 4729 }, 4730 { 4731 .name = "Opteron_G1", 4732 .level = 5, 4733 .vendor = CPUID_VENDOR_AMD, 4734 .family = 15, 4735 .model = 6, 4736 .stepping = 1, 4737 .features[FEAT_1_EDX] = 4738 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4739 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4740 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4741 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4742 CPUID_DE | CPUID_FP87, 4743 .features[FEAT_1_ECX] = 4744 CPUID_EXT_SSE3, 4745 .features[FEAT_8000_0001_EDX] = 4746 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 4747 .xlevel = 0x80000008, 4748 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)", 4749 }, 4750 { 4751 .name = "Opteron_G2", 4752 .level = 5, 4753 .vendor = CPUID_VENDOR_AMD, 4754 .family = 15, 4755 .model = 6, 4756 .stepping = 1, 4757 .features[FEAT_1_EDX] = 4758 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4759 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4760 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4761 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4762 CPUID_DE | CPUID_FP87, 4763 .features[FEAT_1_ECX] = 4764 CPUID_EXT_CX16 | CPUID_EXT_SSE3, 4765 .features[FEAT_8000_0001_EDX] = 4766 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 4767 .features[FEAT_8000_0001_ECX] = 4768 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, 4769 .xlevel = 0x80000008, 4770 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)", 4771 }, 4772 { 4773 .name = "Opteron_G3", 4774 .level = 5, 4775 .vendor = CPUID_VENDOR_AMD, 4776 .family = 16, 4777 .model = 2, 4778 .stepping = 3, 4779 .features[FEAT_1_EDX] = 4780 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4781 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4782 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4783 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4784 CPUID_DE | CPUID_FP87, 4785 .features[FEAT_1_ECX] = 4786 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR | 4787 CPUID_EXT_SSE3, 4788 .features[FEAT_8000_0001_EDX] = 4789 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL | 4790 CPUID_EXT2_RDTSCP, 4791 .features[FEAT_8000_0001_ECX] = 4792 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | 4793 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, 4794 .xlevel = 0x80000008, 4795 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)", 4796 }, 4797 { 4798 .name = "Opteron_G4", 4799 .level = 0xd, 4800 .vendor = CPUID_VENDOR_AMD, 4801 .family = 21, 4802 .model = 1, 4803 .stepping = 2, 4804 .features[FEAT_1_EDX] = 4805 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4806 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4807 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4808 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4809 CPUID_DE | CPUID_FP87, 4810 .features[FEAT_1_ECX] = 4811 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 4812 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 4813 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 4814 CPUID_EXT_SSE3, 4815 .features[FEAT_8000_0001_EDX] = 4816 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX | 4817 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP, 4818 .features[FEAT_8000_0001_ECX] = 4819 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP | 4820 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | 4821 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | 4822 CPUID_EXT3_LAHF_LM, 4823 .features[FEAT_SVM] = 4824 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 4825 /* no xsaveopt! */ 4826 .xlevel = 0x8000001A, 4827 .model_id = "AMD Opteron 62xx class CPU", 4828 }, 4829 { 4830 .name = "Opteron_G5", 4831 .level = 0xd, 4832 .vendor = CPUID_VENDOR_AMD, 4833 .family = 21, 4834 .model = 2, 4835 .stepping = 0, 4836 .features[FEAT_1_EDX] = 4837 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4838 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4839 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4840 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4841 CPUID_DE | CPUID_FP87, 4842 .features[FEAT_1_ECX] = 4843 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE | 4844 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | 4845 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA | 4846 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 4847 .features[FEAT_8000_0001_EDX] = 4848 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX | 4849 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP, 4850 .features[FEAT_8000_0001_ECX] = 4851 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP | 4852 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | 4853 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | 4854 CPUID_EXT3_LAHF_LM, 4855 .features[FEAT_SVM] = 4856 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 4857 /* no xsaveopt! */ 4858 .xlevel = 0x8000001A, 4859 .model_id = "AMD Opteron 63xx class CPU", 4860 }, 4861 { 4862 .name = "EPYC", 4863 .level = 0xd, 4864 .vendor = CPUID_VENDOR_AMD, 4865 .family = 23, 4866 .model = 1, 4867 .stepping = 2, 4868 .features[FEAT_1_EDX] = 4869 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 4870 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 4871 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 4872 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 4873 CPUID_VME | CPUID_FP87, 4874 .features[FEAT_1_ECX] = 4875 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 4876 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 4877 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 4878 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 4879 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 4880 .features[FEAT_8000_0001_EDX] = 4881 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 4882 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 4883 CPUID_EXT2_SYSCALL, 4884 .features[FEAT_8000_0001_ECX] = 4885 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 4886 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 4887 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 4888 CPUID_EXT3_TOPOEXT, 4889 .features[FEAT_7_0_EBX] = 4890 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4891 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 4892 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 4893 CPUID_7_0_EBX_SHA_NI, 4894 .features[FEAT_XSAVE] = 4895 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4896 CPUID_XSAVE_XGETBV1, 4897 .features[FEAT_6_EAX] = 4898 CPUID_6_EAX_ARAT, 4899 .features[FEAT_SVM] = 4900 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 4901 .xlevel = 0x8000001E, 4902 .model_id = "AMD EPYC Processor", 4903 .cache_info = &epyc_cache_info, 4904 .versions = (X86CPUVersionDefinition[]) { 4905 { .version = 1 }, 4906 { 4907 .version = 2, 4908 .alias = "EPYC-IBPB", 4909 .props = (PropValue[]) { 4910 { "ibpb", "on" }, 4911 { "model-id", 4912 "AMD EPYC Processor (with IBPB)" }, 4913 { /* end of list */ } 4914 } 4915 }, 4916 { 4917 .version = 3, 4918 .props = (PropValue[]) { 4919 { "ibpb", "on" }, 4920 { "perfctr-core", "on" }, 4921 { "clzero", "on" }, 4922 { "xsaveerptr", "on" }, 4923 { "xsaves", "on" }, 4924 { "model-id", 4925 "AMD EPYC Processor" }, 4926 { /* end of list */ } 4927 } 4928 }, 4929 { 4930 .version = 4, 4931 .props = (PropValue[]) { 4932 { "model-id", 4933 "AMD EPYC-v4 Processor" }, 4934 { /* end of list */ } 4935 }, 4936 .cache_info = &epyc_v4_cache_info 4937 }, 4938 { /* end of list */ } 4939 } 4940 }, 4941 { 4942 .name = "Dhyana", 4943 .level = 0xd, 4944 .vendor = CPUID_VENDOR_HYGON, 4945 .family = 24, 4946 .model = 0, 4947 .stepping = 1, 4948 .features[FEAT_1_EDX] = 4949 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 4950 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 4951 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 4952 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 4953 CPUID_VME | CPUID_FP87, 4954 .features[FEAT_1_ECX] = 4955 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 4956 CPUID_EXT_XSAVE | CPUID_EXT_POPCNT | 4957 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 4958 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 4959 CPUID_EXT_MONITOR | CPUID_EXT_SSE3, 4960 .features[FEAT_8000_0001_EDX] = 4961 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 4962 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 4963 CPUID_EXT2_SYSCALL, 4964 .features[FEAT_8000_0001_ECX] = 4965 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 4966 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 4967 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 4968 CPUID_EXT3_TOPOEXT, 4969 .features[FEAT_8000_0008_EBX] = 4970 CPUID_8000_0008_EBX_IBPB, 4971 .features[FEAT_7_0_EBX] = 4972 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4973 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 4974 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT, 4975 /* XSAVES is added in version 2 */ 4976 .features[FEAT_XSAVE] = 4977 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4978 CPUID_XSAVE_XGETBV1, 4979 .features[FEAT_6_EAX] = 4980 CPUID_6_EAX_ARAT, 4981 .features[FEAT_SVM] = 4982 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 4983 .xlevel = 0x8000001E, 4984 .model_id = "Hygon Dhyana Processor", 4985 .cache_info = &epyc_cache_info, 4986 .versions = (X86CPUVersionDefinition[]) { 4987 { .version = 1 }, 4988 { .version = 2, 4989 .note = "XSAVES", 4990 .props = (PropValue[]) { 4991 { "xsaves", "on" }, 4992 { /* end of list */ } 4993 }, 4994 }, 4995 { /* end of list */ } 4996 } 4997 }, 4998 { 4999 .name = "EPYC-Rome", 5000 .level = 0xd, 5001 .vendor = CPUID_VENDOR_AMD, 5002 .family = 23, 5003 .model = 49, 5004 .stepping = 0, 5005 .features[FEAT_1_EDX] = 5006 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 5007 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 5008 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 5009 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 5010 CPUID_VME | CPUID_FP87, 5011 .features[FEAT_1_ECX] = 5012 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5013 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 5014 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5015 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 5016 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 5017 .features[FEAT_8000_0001_EDX] = 5018 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5019 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5020 CPUID_EXT2_SYSCALL, 5021 .features[FEAT_8000_0001_ECX] = 5022 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5023 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5024 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5025 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 5026 .features[FEAT_8000_0008_EBX] = 5027 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 5028 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 5029 CPUID_8000_0008_EBX_STIBP, 5030 .features[FEAT_7_0_EBX] = 5031 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5032 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 5033 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 5034 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB, 5035 .features[FEAT_7_0_ECX] = 5036 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID, 5037 .features[FEAT_XSAVE] = 5038 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5039 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 5040 .features[FEAT_6_EAX] = 5041 CPUID_6_EAX_ARAT, 5042 .features[FEAT_SVM] = 5043 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 5044 .xlevel = 0x8000001E, 5045 .model_id = "AMD EPYC-Rome Processor", 5046 .cache_info = &epyc_rome_cache_info, 5047 .versions = (X86CPUVersionDefinition[]) { 5048 { .version = 1 }, 5049 { 5050 .version = 2, 5051 .props = (PropValue[]) { 5052 { "ibrs", "on" }, 5053 { "amd-ssbd", "on" }, 5054 { /* end of list */ } 5055 } 5056 }, 5057 { 5058 .version = 3, 5059 .props = (PropValue[]) { 5060 { "model-id", 5061 "AMD EPYC-Rome-v3 Processor" }, 5062 { /* end of list */ } 5063 }, 5064 .cache_info = &epyc_rome_v3_cache_info 5065 }, 5066 { 5067 .version = 4, 5068 .props = (PropValue[]) { 5069 /* Erratum 1386 */ 5070 { "model-id", 5071 "AMD EPYC-Rome-v4 Processor (no XSAVES)" }, 5072 { "xsaves", "off" }, 5073 { /* end of list */ } 5074 }, 5075 }, 5076 { /* end of list */ } 5077 } 5078 }, 5079 { 5080 .name = "EPYC-Milan", 5081 .level = 0xd, 5082 .vendor = CPUID_VENDOR_AMD, 5083 .family = 25, 5084 .model = 1, 5085 .stepping = 1, 5086 .features[FEAT_1_EDX] = 5087 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 5088 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 5089 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 5090 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 5091 CPUID_VME | CPUID_FP87, 5092 .features[FEAT_1_ECX] = 5093 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5094 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 5095 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5096 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 5097 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 5098 CPUID_EXT_PCID, 5099 .features[FEAT_8000_0001_EDX] = 5100 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5101 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5102 CPUID_EXT2_SYSCALL, 5103 .features[FEAT_8000_0001_ECX] = 5104 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5105 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5106 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5107 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 5108 .features[FEAT_8000_0008_EBX] = 5109 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 5110 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 5111 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | 5112 CPUID_8000_0008_EBX_AMD_SSBD, 5113 .features[FEAT_7_0_EBX] = 5114 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5115 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 5116 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 5117 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_ERMS | 5118 CPUID_7_0_EBX_INVPCID, 5119 .features[FEAT_7_0_ECX] = 5120 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_PKU, 5121 .features[FEAT_7_0_EDX] = 5122 CPUID_7_0_EDX_FSRM, 5123 .features[FEAT_XSAVE] = 5124 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5125 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 5126 .features[FEAT_6_EAX] = 5127 CPUID_6_EAX_ARAT, 5128 .features[FEAT_SVM] = 5129 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE | CPUID_SVM_SVME_ADDR_CHK, 5130 .xlevel = 0x8000001E, 5131 .model_id = "AMD EPYC-Milan Processor", 5132 .cache_info = &epyc_milan_cache_info, 5133 .versions = (X86CPUVersionDefinition[]) { 5134 { .version = 1 }, 5135 { 5136 .version = 2, 5137 .props = (PropValue[]) { 5138 { "model-id", 5139 "AMD EPYC-Milan-v2 Processor" }, 5140 { "vaes", "on" }, 5141 { "vpclmulqdq", "on" }, 5142 { "stibp-always-on", "on" }, 5143 { "amd-psfd", "on" }, 5144 { "no-nested-data-bp", "on" }, 5145 { "lfence-always-serializing", "on" }, 5146 { "null-sel-clr-base", "on" }, 5147 { /* end of list */ } 5148 }, 5149 .cache_info = &epyc_milan_v2_cache_info 5150 }, 5151 { /* end of list */ } 5152 } 5153 }, 5154 { 5155 .name = "EPYC-Genoa", 5156 .level = 0xd, 5157 .vendor = CPUID_VENDOR_AMD, 5158 .family = 25, 5159 .model = 17, 5160 .stepping = 0, 5161 .features[FEAT_1_EDX] = 5162 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 5163 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 5164 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 5165 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 5166 CPUID_VME | CPUID_FP87, 5167 .features[FEAT_1_ECX] = 5168 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5169 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 5170 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5171 CPUID_EXT_PCID | CPUID_EXT_CX16 | CPUID_EXT_FMA | 5172 CPUID_EXT_SSSE3 | CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | 5173 CPUID_EXT_SSE3, 5174 .features[FEAT_8000_0001_EDX] = 5175 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5176 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5177 CPUID_EXT2_SYSCALL, 5178 .features[FEAT_8000_0001_ECX] = 5179 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5180 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5181 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5182 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 5183 .features[FEAT_8000_0008_EBX] = 5184 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 5185 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 5186 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | 5187 CPUID_8000_0008_EBX_STIBP_ALWAYS_ON | 5188 CPUID_8000_0008_EBX_AMD_SSBD | CPUID_8000_0008_EBX_AMD_PSFD, 5189 .features[FEAT_8000_0021_EAX] = 5190 CPUID_8000_0021_EAX_No_NESTED_DATA_BP | 5191 CPUID_8000_0021_EAX_LFENCE_ALWAYS_SERIALIZING | 5192 CPUID_8000_0021_EAX_NULL_SEL_CLR_BASE | 5193 CPUID_8000_0021_EAX_AUTO_IBRS, 5194 .features[FEAT_7_0_EBX] = 5195 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5196 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 5197 CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_AVX512F | 5198 CPUID_7_0_EBX_AVX512DQ | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 5199 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_AVX512IFMA | 5200 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB | 5201 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | 5202 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, 5203 .features[FEAT_7_0_ECX] = 5204 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 5205 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 5206 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 5207 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 5208 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | 5209 CPUID_7_0_ECX_RDPID, 5210 .features[FEAT_7_0_EDX] = 5211 CPUID_7_0_EDX_FSRM, 5212 .features[FEAT_7_1_EAX] = 5213 CPUID_7_1_EAX_AVX512_BF16, 5214 .features[FEAT_XSAVE] = 5215 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5216 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 5217 .features[FEAT_6_EAX] = 5218 CPUID_6_EAX_ARAT, 5219 .features[FEAT_SVM] = 5220 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE | CPUID_SVM_VNMI | 5221 CPUID_SVM_SVME_ADDR_CHK, 5222 .xlevel = 0x80000022, 5223 .model_id = "AMD EPYC-Genoa Processor", 5224 .cache_info = &epyc_genoa_cache_info, 5225 }, 5226 }; 5227 5228 /* 5229 * We resolve CPU model aliases using -v1 when using "-machine 5230 * none", but this is just for compatibility while libvirt isn't 5231 * adapted to resolve CPU model versions before creating VMs. 5232 * See "Runnability guarantee of CPU models" at 5233 * docs/about/deprecated.rst. 5234 */ 5235 X86CPUVersion default_cpu_version = 1; 5236 5237 void x86_cpu_set_default_version(X86CPUVersion version) 5238 { 5239 /* Translating CPU_VERSION_AUTO to CPU_VERSION_AUTO doesn't make sense */ 5240 assert(version != CPU_VERSION_AUTO); 5241 default_cpu_version = version; 5242 } 5243 5244 static X86CPUVersion x86_cpu_model_last_version(const X86CPUModel *model) 5245 { 5246 int v = 0; 5247 const X86CPUVersionDefinition *vdef = 5248 x86_cpu_def_get_versions(model->cpudef); 5249 while (vdef->version) { 5250 v = vdef->version; 5251 vdef++; 5252 } 5253 return v; 5254 } 5255 5256 /* Return the actual version being used for a specific CPU model */ 5257 static X86CPUVersion x86_cpu_model_resolve_version(const X86CPUModel *model) 5258 { 5259 X86CPUVersion v = model->version; 5260 if (v == CPU_VERSION_AUTO) { 5261 v = default_cpu_version; 5262 } 5263 if (v == CPU_VERSION_LATEST) { 5264 return x86_cpu_model_last_version(model); 5265 } 5266 return v; 5267 } 5268 5269 static Property max_x86_cpu_properties[] = { 5270 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true), 5271 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false), 5272 DEFINE_PROP_END_OF_LIST() 5273 }; 5274 5275 static void max_x86_cpu_realize(DeviceState *dev, Error **errp) 5276 { 5277 Object *obj = OBJECT(dev); 5278 5279 if (!object_property_get_int(obj, "family", &error_abort)) { 5280 if (X86_CPU(obj)->env.features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 5281 object_property_set_int(obj, "family", 15, &error_abort); 5282 object_property_set_int(obj, "model", 107, &error_abort); 5283 object_property_set_int(obj, "stepping", 1, &error_abort); 5284 } else { 5285 object_property_set_int(obj, "family", 6, &error_abort); 5286 object_property_set_int(obj, "model", 6, &error_abort); 5287 object_property_set_int(obj, "stepping", 3, &error_abort); 5288 } 5289 } 5290 5291 x86_cpu_realizefn(dev, errp); 5292 } 5293 5294 static void max_x86_cpu_class_init(ObjectClass *oc, void *data) 5295 { 5296 DeviceClass *dc = DEVICE_CLASS(oc); 5297 X86CPUClass *xcc = X86_CPU_CLASS(oc); 5298 5299 xcc->ordering = 9; 5300 5301 xcc->model_description = 5302 "Enables all features supported by the accelerator in the current host"; 5303 5304 device_class_set_props(dc, max_x86_cpu_properties); 5305 dc->realize = max_x86_cpu_realize; 5306 } 5307 5308 static void max_x86_cpu_initfn(Object *obj) 5309 { 5310 X86CPU *cpu = X86_CPU(obj); 5311 5312 /* We can't fill the features array here because we don't know yet if 5313 * "migratable" is true or false. 5314 */ 5315 cpu->max_features = true; 5316 object_property_set_bool(OBJECT(cpu), "pmu", true, &error_abort); 5317 5318 /* 5319 * these defaults are used for TCG and all other accelerators 5320 * besides KVM and HVF, which overwrite these values 5321 */ 5322 object_property_set_str(OBJECT(cpu), "vendor", CPUID_VENDOR_AMD, 5323 &error_abort); 5324 object_property_set_str(OBJECT(cpu), "model-id", 5325 "QEMU TCG CPU version " QEMU_HW_VERSION, 5326 &error_abort); 5327 } 5328 5329 static const TypeInfo max_x86_cpu_type_info = { 5330 .name = X86_CPU_TYPE_NAME("max"), 5331 .parent = TYPE_X86_CPU, 5332 .instance_init = max_x86_cpu_initfn, 5333 .class_init = max_x86_cpu_class_init, 5334 }; 5335 5336 static char *feature_word_description(FeatureWordInfo *f, uint32_t bit) 5337 { 5338 assert(f->type == CPUID_FEATURE_WORD || f->type == MSR_FEATURE_WORD); 5339 5340 switch (f->type) { 5341 case CPUID_FEATURE_WORD: 5342 { 5343 const char *reg = get_register_name_32(f->cpuid.reg); 5344 assert(reg); 5345 return g_strdup_printf("CPUID.%02XH:%s", 5346 f->cpuid.eax, reg); 5347 } 5348 case MSR_FEATURE_WORD: 5349 return g_strdup_printf("MSR(%02XH)", 5350 f->msr.index); 5351 } 5352 5353 return NULL; 5354 } 5355 5356 static bool x86_cpu_have_filtered_features(X86CPU *cpu) 5357 { 5358 FeatureWord w; 5359 5360 for (w = 0; w < FEATURE_WORDS; w++) { 5361 if (cpu->filtered_features[w]) { 5362 return true; 5363 } 5364 } 5365 5366 return false; 5367 } 5368 5369 static void mark_unavailable_features(X86CPU *cpu, FeatureWord w, uint64_t mask, 5370 const char *verbose_prefix) 5371 { 5372 CPUX86State *env = &cpu->env; 5373 FeatureWordInfo *f = &feature_word_info[w]; 5374 int i; 5375 5376 if (!cpu->force_features) { 5377 env->features[w] &= ~mask; 5378 } 5379 cpu->filtered_features[w] |= mask; 5380 5381 if (!verbose_prefix) { 5382 return; 5383 } 5384 5385 for (i = 0; i < 64; ++i) { 5386 if ((1ULL << i) & mask) { 5387 g_autofree char *feat_word_str = feature_word_description(f, i); 5388 warn_report("%s: %s%s%s [bit %d]", 5389 verbose_prefix, 5390 feat_word_str, 5391 f->feat_names[i] ? "." : "", 5392 f->feat_names[i] ? f->feat_names[i] : "", i); 5393 } 5394 } 5395 } 5396 5397 static void x86_cpuid_version_get_family(Object *obj, Visitor *v, 5398 const char *name, void *opaque, 5399 Error **errp) 5400 { 5401 X86CPU *cpu = X86_CPU(obj); 5402 CPUX86State *env = &cpu->env; 5403 int64_t value; 5404 5405 value = (env->cpuid_version >> 8) & 0xf; 5406 if (value == 0xf) { 5407 value += (env->cpuid_version >> 20) & 0xff; 5408 } 5409 visit_type_int(v, name, &value, errp); 5410 } 5411 5412 static void x86_cpuid_version_set_family(Object *obj, Visitor *v, 5413 const char *name, void *opaque, 5414 Error **errp) 5415 { 5416 X86CPU *cpu = X86_CPU(obj); 5417 CPUX86State *env = &cpu->env; 5418 const int64_t min = 0; 5419 const int64_t max = 0xff + 0xf; 5420 int64_t value; 5421 5422 if (!visit_type_int(v, name, &value, errp)) { 5423 return; 5424 } 5425 if (value < min || value > max) { 5426 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", 5427 name ? name : "null", value, min, max); 5428 return; 5429 } 5430 5431 env->cpuid_version &= ~0xff00f00; 5432 if (value > 0x0f) { 5433 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20); 5434 } else { 5435 env->cpuid_version |= value << 8; 5436 } 5437 } 5438 5439 static void x86_cpuid_version_get_model(Object *obj, Visitor *v, 5440 const char *name, void *opaque, 5441 Error **errp) 5442 { 5443 X86CPU *cpu = X86_CPU(obj); 5444 CPUX86State *env = &cpu->env; 5445 int64_t value; 5446 5447 value = (env->cpuid_version >> 4) & 0xf; 5448 value |= ((env->cpuid_version >> 16) & 0xf) << 4; 5449 visit_type_int(v, name, &value, errp); 5450 } 5451 5452 static void x86_cpuid_version_set_model(Object *obj, Visitor *v, 5453 const char *name, void *opaque, 5454 Error **errp) 5455 { 5456 X86CPU *cpu = X86_CPU(obj); 5457 CPUX86State *env = &cpu->env; 5458 const int64_t min = 0; 5459 const int64_t max = 0xff; 5460 int64_t value; 5461 5462 if (!visit_type_int(v, name, &value, errp)) { 5463 return; 5464 } 5465 if (value < min || value > max) { 5466 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", 5467 name ? name : "null", value, min, max); 5468 return; 5469 } 5470 5471 env->cpuid_version &= ~0xf00f0; 5472 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16); 5473 } 5474 5475 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v, 5476 const char *name, void *opaque, 5477 Error **errp) 5478 { 5479 X86CPU *cpu = X86_CPU(obj); 5480 CPUX86State *env = &cpu->env; 5481 int64_t value; 5482 5483 value = env->cpuid_version & 0xf; 5484 visit_type_int(v, name, &value, errp); 5485 } 5486 5487 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v, 5488 const char *name, void *opaque, 5489 Error **errp) 5490 { 5491 X86CPU *cpu = X86_CPU(obj); 5492 CPUX86State *env = &cpu->env; 5493 const int64_t min = 0; 5494 const int64_t max = 0xf; 5495 int64_t value; 5496 5497 if (!visit_type_int(v, name, &value, errp)) { 5498 return; 5499 } 5500 if (value < min || value > max) { 5501 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", 5502 name ? name : "null", value, min, max); 5503 return; 5504 } 5505 5506 env->cpuid_version &= ~0xf; 5507 env->cpuid_version |= value & 0xf; 5508 } 5509 5510 static char *x86_cpuid_get_vendor(Object *obj, Error **errp) 5511 { 5512 X86CPU *cpu = X86_CPU(obj); 5513 CPUX86State *env = &cpu->env; 5514 char *value; 5515 5516 value = g_malloc(CPUID_VENDOR_SZ + 1); 5517 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2, 5518 env->cpuid_vendor3); 5519 return value; 5520 } 5521 5522 static void x86_cpuid_set_vendor(Object *obj, const char *value, 5523 Error **errp) 5524 { 5525 X86CPU *cpu = X86_CPU(obj); 5526 CPUX86State *env = &cpu->env; 5527 int i; 5528 5529 if (strlen(value) != CPUID_VENDOR_SZ) { 5530 error_setg(errp, "value of property 'vendor' must consist of" 5531 " exactly " stringify(CPUID_VENDOR_SZ) " characters"); 5532 return; 5533 } 5534 5535 env->cpuid_vendor1 = 0; 5536 env->cpuid_vendor2 = 0; 5537 env->cpuid_vendor3 = 0; 5538 for (i = 0; i < 4; i++) { 5539 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i); 5540 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i); 5541 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i); 5542 } 5543 } 5544 5545 static char *x86_cpuid_get_model_id(Object *obj, Error **errp) 5546 { 5547 X86CPU *cpu = X86_CPU(obj); 5548 CPUX86State *env = &cpu->env; 5549 char *value; 5550 int i; 5551 5552 value = g_malloc(48 + 1); 5553 for (i = 0; i < 48; i++) { 5554 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3)); 5555 } 5556 value[48] = '\0'; 5557 return value; 5558 } 5559 5560 static void x86_cpuid_set_model_id(Object *obj, const char *model_id, 5561 Error **errp) 5562 { 5563 X86CPU *cpu = X86_CPU(obj); 5564 CPUX86State *env = &cpu->env; 5565 int c, len, i; 5566 5567 if (model_id == NULL) { 5568 model_id = ""; 5569 } 5570 len = strlen(model_id); 5571 memset(env->cpuid_model, 0, 48); 5572 for (i = 0; i < 48; i++) { 5573 if (i >= len) { 5574 c = '\0'; 5575 } else { 5576 c = (uint8_t)model_id[i]; 5577 } 5578 env->cpuid_model[i >> 2] |= c << (8 * (i & 3)); 5579 } 5580 } 5581 5582 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name, 5583 void *opaque, Error **errp) 5584 { 5585 X86CPU *cpu = X86_CPU(obj); 5586 int64_t value; 5587 5588 value = cpu->env.tsc_khz * 1000; 5589 visit_type_int(v, name, &value, errp); 5590 } 5591 5592 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name, 5593 void *opaque, Error **errp) 5594 { 5595 X86CPU *cpu = X86_CPU(obj); 5596 const int64_t min = 0; 5597 const int64_t max = INT64_MAX; 5598 int64_t value; 5599 5600 if (!visit_type_int(v, name, &value, errp)) { 5601 return; 5602 } 5603 if (value < min || value > max) { 5604 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", 5605 name ? name : "null", value, min, max); 5606 return; 5607 } 5608 5609 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000; 5610 } 5611 5612 /* Generic getter for "feature-words" and "filtered-features" properties */ 5613 static void x86_cpu_get_feature_words(Object *obj, Visitor *v, 5614 const char *name, void *opaque, 5615 Error **errp) 5616 { 5617 uint64_t *array = (uint64_t *)opaque; 5618 FeatureWord w; 5619 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { }; 5620 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { }; 5621 X86CPUFeatureWordInfoList *list = NULL; 5622 5623 for (w = 0; w < FEATURE_WORDS; w++) { 5624 FeatureWordInfo *wi = &feature_word_info[w]; 5625 /* 5626 * We didn't have MSR features when "feature-words" was 5627 * introduced. Therefore skipped other type entries. 5628 */ 5629 if (wi->type != CPUID_FEATURE_WORD) { 5630 continue; 5631 } 5632 X86CPUFeatureWordInfo *qwi = &word_infos[w]; 5633 qwi->cpuid_input_eax = wi->cpuid.eax; 5634 qwi->has_cpuid_input_ecx = wi->cpuid.needs_ecx; 5635 qwi->cpuid_input_ecx = wi->cpuid.ecx; 5636 qwi->cpuid_register = x86_reg_info_32[wi->cpuid.reg].qapi_enum; 5637 qwi->features = array[w]; 5638 5639 /* List will be in reverse order, but order shouldn't matter */ 5640 list_entries[w].next = list; 5641 list_entries[w].value = &word_infos[w]; 5642 list = &list_entries[w]; 5643 } 5644 5645 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp); 5646 } 5647 5648 /* Convert all '_' in a feature string option name to '-', to make feature 5649 * name conform to QOM property naming rule, which uses '-' instead of '_'. 5650 */ 5651 static inline void feat2prop(char *s) 5652 { 5653 while ((s = strchr(s, '_'))) { 5654 *s = '-'; 5655 } 5656 } 5657 5658 /* Return the feature property name for a feature flag bit */ 5659 static const char *x86_cpu_feature_name(FeatureWord w, int bitnr) 5660 { 5661 const char *name; 5662 /* XSAVE components are automatically enabled by other features, 5663 * so return the original feature name instead 5664 */ 5665 if (w == FEAT_XSAVE_XCR0_LO || w == FEAT_XSAVE_XCR0_HI) { 5666 int comp = (w == FEAT_XSAVE_XCR0_HI) ? bitnr + 32 : bitnr; 5667 5668 if (comp < ARRAY_SIZE(x86_ext_save_areas) && 5669 x86_ext_save_areas[comp].bits) { 5670 w = x86_ext_save_areas[comp].feature; 5671 bitnr = ctz32(x86_ext_save_areas[comp].bits); 5672 } 5673 } 5674 5675 assert(bitnr < 64); 5676 assert(w < FEATURE_WORDS); 5677 name = feature_word_info[w].feat_names[bitnr]; 5678 assert(bitnr < 32 || !(name && feature_word_info[w].type == CPUID_FEATURE_WORD)); 5679 return name; 5680 } 5681 5682 /* Compatibility hack to maintain legacy +-feat semantic, 5683 * where +-feat overwrites any feature set by 5684 * feat=on|feat even if the later is parsed after +-feat 5685 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled) 5686 */ 5687 static GList *plus_features, *minus_features; 5688 5689 static gint compare_string(gconstpointer a, gconstpointer b) 5690 { 5691 return g_strcmp0(a, b); 5692 } 5693 5694 /* Parse "+feature,-feature,feature=foo" CPU feature string 5695 */ 5696 static void x86_cpu_parse_featurestr(const char *typename, char *features, 5697 Error **errp) 5698 { 5699 char *featurestr; /* Single 'key=value" string being parsed */ 5700 static bool cpu_globals_initialized; 5701 bool ambiguous = false; 5702 5703 if (cpu_globals_initialized) { 5704 return; 5705 } 5706 cpu_globals_initialized = true; 5707 5708 if (!features) { 5709 return; 5710 } 5711 5712 for (featurestr = strtok(features, ","); 5713 featurestr; 5714 featurestr = strtok(NULL, ",")) { 5715 const char *name; 5716 const char *val = NULL; 5717 char *eq = NULL; 5718 char num[32]; 5719 GlobalProperty *prop; 5720 5721 /* Compatibility syntax: */ 5722 if (featurestr[0] == '+') { 5723 plus_features = g_list_append(plus_features, 5724 g_strdup(featurestr + 1)); 5725 continue; 5726 } else if (featurestr[0] == '-') { 5727 minus_features = g_list_append(minus_features, 5728 g_strdup(featurestr + 1)); 5729 continue; 5730 } 5731 5732 eq = strchr(featurestr, '='); 5733 if (eq) { 5734 *eq++ = 0; 5735 val = eq; 5736 } else { 5737 val = "on"; 5738 } 5739 5740 feat2prop(featurestr); 5741 name = featurestr; 5742 5743 if (g_list_find_custom(plus_features, name, compare_string)) { 5744 warn_report("Ambiguous CPU model string. " 5745 "Don't mix both \"+%s\" and \"%s=%s\"", 5746 name, name, val); 5747 ambiguous = true; 5748 } 5749 if (g_list_find_custom(minus_features, name, compare_string)) { 5750 warn_report("Ambiguous CPU model string. " 5751 "Don't mix both \"-%s\" and \"%s=%s\"", 5752 name, name, val); 5753 ambiguous = true; 5754 } 5755 5756 /* Special case: */ 5757 if (!strcmp(name, "tsc-freq")) { 5758 int ret; 5759 uint64_t tsc_freq; 5760 5761 ret = qemu_strtosz_metric(val, NULL, &tsc_freq); 5762 if (ret < 0 || tsc_freq > INT64_MAX) { 5763 error_setg(errp, "bad numerical value %s", val); 5764 return; 5765 } 5766 snprintf(num, sizeof(num), "%" PRId64, tsc_freq); 5767 val = num; 5768 name = "tsc-frequency"; 5769 } 5770 5771 prop = g_new0(typeof(*prop), 1); 5772 prop->driver = typename; 5773 prop->property = g_strdup(name); 5774 prop->value = g_strdup(val); 5775 qdev_prop_register_global(prop); 5776 } 5777 5778 if (ambiguous) { 5779 warn_report("Compatibility of ambiguous CPU model " 5780 "strings won't be kept on future QEMU versions"); 5781 } 5782 } 5783 5784 static void x86_cpu_filter_features(X86CPU *cpu, bool verbose); 5785 5786 /* Build a list with the name of all features on a feature word array */ 5787 static void x86_cpu_list_feature_names(FeatureWordArray features, 5788 strList **list) 5789 { 5790 strList **tail = list; 5791 FeatureWord w; 5792 5793 for (w = 0; w < FEATURE_WORDS; w++) { 5794 uint64_t filtered = features[w]; 5795 int i; 5796 for (i = 0; i < 64; i++) { 5797 if (filtered & (1ULL << i)) { 5798 QAPI_LIST_APPEND(tail, g_strdup(x86_cpu_feature_name(w, i))); 5799 } 5800 } 5801 } 5802 } 5803 5804 static void x86_cpu_get_unavailable_features(Object *obj, Visitor *v, 5805 const char *name, void *opaque, 5806 Error **errp) 5807 { 5808 X86CPU *xc = X86_CPU(obj); 5809 strList *result = NULL; 5810 5811 x86_cpu_list_feature_names(xc->filtered_features, &result); 5812 visit_type_strList(v, "unavailable-features", &result, errp); 5813 } 5814 5815 /* Print all cpuid feature names in featureset 5816 */ 5817 static void listflags(GList *features) 5818 { 5819 size_t len = 0; 5820 GList *tmp; 5821 5822 for (tmp = features; tmp; tmp = tmp->next) { 5823 const char *name = tmp->data; 5824 if ((len + strlen(name) + 1) >= 75) { 5825 qemu_printf("\n"); 5826 len = 0; 5827 } 5828 qemu_printf("%s%s", len == 0 ? " " : " ", name); 5829 len += strlen(name) + 1; 5830 } 5831 qemu_printf("\n"); 5832 } 5833 5834 /* Sort alphabetically by type name, respecting X86CPUClass::ordering. */ 5835 static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b) 5836 { 5837 ObjectClass *class_a = (ObjectClass *)a; 5838 ObjectClass *class_b = (ObjectClass *)b; 5839 X86CPUClass *cc_a = X86_CPU_CLASS(class_a); 5840 X86CPUClass *cc_b = X86_CPU_CLASS(class_b); 5841 int ret; 5842 5843 if (cc_a->ordering != cc_b->ordering) { 5844 ret = cc_a->ordering - cc_b->ordering; 5845 } else { 5846 g_autofree char *name_a = x86_cpu_class_get_model_name(cc_a); 5847 g_autofree char *name_b = x86_cpu_class_get_model_name(cc_b); 5848 ret = strcmp(name_a, name_b); 5849 } 5850 return ret; 5851 } 5852 5853 static GSList *get_sorted_cpu_model_list(void) 5854 { 5855 GSList *list = object_class_get_list(TYPE_X86_CPU, false); 5856 list = g_slist_sort(list, x86_cpu_list_compare); 5857 return list; 5858 } 5859 5860 static char *x86_cpu_class_get_model_id(X86CPUClass *xc) 5861 { 5862 Object *obj = object_new_with_class(OBJECT_CLASS(xc)); 5863 char *r = object_property_get_str(obj, "model-id", &error_abort); 5864 object_unref(obj); 5865 return r; 5866 } 5867 5868 static char *x86_cpu_class_get_alias_of(X86CPUClass *cc) 5869 { 5870 X86CPUVersion version; 5871 5872 if (!cc->model || !cc->model->is_alias) { 5873 return NULL; 5874 } 5875 version = x86_cpu_model_resolve_version(cc->model); 5876 if (version <= 0) { 5877 return NULL; 5878 } 5879 return x86_cpu_versioned_model_name(cc->model->cpudef, version); 5880 } 5881 5882 static void x86_cpu_list_entry(gpointer data, gpointer user_data) 5883 { 5884 ObjectClass *oc = data; 5885 X86CPUClass *cc = X86_CPU_CLASS(oc); 5886 g_autofree char *name = x86_cpu_class_get_model_name(cc); 5887 g_autofree char *desc = g_strdup(cc->model_description); 5888 g_autofree char *alias_of = x86_cpu_class_get_alias_of(cc); 5889 g_autofree char *model_id = x86_cpu_class_get_model_id(cc); 5890 5891 if (!desc && alias_of) { 5892 if (cc->model && cc->model->version == CPU_VERSION_AUTO) { 5893 desc = g_strdup("(alias configured by machine type)"); 5894 } else { 5895 desc = g_strdup_printf("(alias of %s)", alias_of); 5896 } 5897 } 5898 if (!desc && cc->model && cc->model->note) { 5899 desc = g_strdup_printf("%s [%s]", model_id, cc->model->note); 5900 } 5901 if (!desc) { 5902 desc = g_strdup_printf("%s", model_id); 5903 } 5904 5905 if (cc->model && cc->model->cpudef->deprecation_note) { 5906 g_autofree char *olddesc = desc; 5907 desc = g_strdup_printf("%s (deprecated)", olddesc); 5908 } 5909 5910 qemu_printf(" %-20s %s\n", name, desc); 5911 } 5912 5913 /* list available CPU models and flags */ 5914 void x86_cpu_list(void) 5915 { 5916 int i, j; 5917 GSList *list; 5918 GList *names = NULL; 5919 5920 qemu_printf("Available CPUs:\n"); 5921 list = get_sorted_cpu_model_list(); 5922 g_slist_foreach(list, x86_cpu_list_entry, NULL); 5923 g_slist_free(list); 5924 5925 names = NULL; 5926 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) { 5927 FeatureWordInfo *fw = &feature_word_info[i]; 5928 for (j = 0; j < 64; j++) { 5929 if (fw->feat_names[j]) { 5930 names = g_list_append(names, (gpointer)fw->feat_names[j]); 5931 } 5932 } 5933 } 5934 5935 names = g_list_sort(names, (GCompareFunc)strcmp); 5936 5937 qemu_printf("\nRecognized CPUID flags:\n"); 5938 listflags(names); 5939 qemu_printf("\n"); 5940 g_list_free(names); 5941 } 5942 5943 #ifndef CONFIG_USER_ONLY 5944 5945 /* Check for missing features that may prevent the CPU class from 5946 * running using the current machine and accelerator. 5947 */ 5948 static void x86_cpu_class_check_missing_features(X86CPUClass *xcc, 5949 strList **list) 5950 { 5951 strList **tail = list; 5952 X86CPU *xc; 5953 Error *err = NULL; 5954 5955 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) { 5956 QAPI_LIST_APPEND(tail, g_strdup("kvm")); 5957 return; 5958 } 5959 5960 xc = X86_CPU(object_new_with_class(OBJECT_CLASS(xcc))); 5961 5962 x86_cpu_expand_features(xc, &err); 5963 if (err) { 5964 /* Errors at x86_cpu_expand_features should never happen, 5965 * but in case it does, just report the model as not 5966 * runnable at all using the "type" property. 5967 */ 5968 QAPI_LIST_APPEND(tail, g_strdup("type")); 5969 error_free(err); 5970 } 5971 5972 x86_cpu_filter_features(xc, false); 5973 5974 x86_cpu_list_feature_names(xc->filtered_features, tail); 5975 5976 object_unref(OBJECT(xc)); 5977 } 5978 5979 static void x86_cpu_definition_entry(gpointer data, gpointer user_data) 5980 { 5981 ObjectClass *oc = data; 5982 X86CPUClass *cc = X86_CPU_CLASS(oc); 5983 CpuDefinitionInfoList **cpu_list = user_data; 5984 CpuDefinitionInfo *info; 5985 5986 info = g_malloc0(sizeof(*info)); 5987 info->name = x86_cpu_class_get_model_name(cc); 5988 x86_cpu_class_check_missing_features(cc, &info->unavailable_features); 5989 info->has_unavailable_features = true; 5990 info->q_typename = g_strdup(object_class_get_name(oc)); 5991 info->migration_safe = cc->migration_safe; 5992 info->has_migration_safe = true; 5993 info->q_static = cc->static_model; 5994 if (cc->model && cc->model->cpudef->deprecation_note) { 5995 info->deprecated = true; 5996 } else { 5997 info->deprecated = false; 5998 } 5999 /* 6000 * Old machine types won't report aliases, so that alias translation 6001 * doesn't break compatibility with previous QEMU versions. 6002 */ 6003 if (default_cpu_version != CPU_VERSION_LEGACY) { 6004 info->alias_of = x86_cpu_class_get_alias_of(cc); 6005 } 6006 6007 QAPI_LIST_PREPEND(*cpu_list, info); 6008 } 6009 6010 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) 6011 { 6012 CpuDefinitionInfoList *cpu_list = NULL; 6013 GSList *list = get_sorted_cpu_model_list(); 6014 g_slist_foreach(list, x86_cpu_definition_entry, &cpu_list); 6015 g_slist_free(list); 6016 return cpu_list; 6017 } 6018 6019 #endif /* !CONFIG_USER_ONLY */ 6020 6021 uint64_t x86_cpu_get_supported_feature_word(FeatureWord w, 6022 bool migratable_only) 6023 { 6024 FeatureWordInfo *wi = &feature_word_info[w]; 6025 uint64_t r = 0; 6026 6027 if (kvm_enabled()) { 6028 switch (wi->type) { 6029 case CPUID_FEATURE_WORD: 6030 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid.eax, 6031 wi->cpuid.ecx, 6032 wi->cpuid.reg); 6033 break; 6034 case MSR_FEATURE_WORD: 6035 r = kvm_arch_get_supported_msr_feature(kvm_state, 6036 wi->msr.index); 6037 break; 6038 } 6039 } else if (hvf_enabled()) { 6040 if (wi->type != CPUID_FEATURE_WORD) { 6041 return 0; 6042 } 6043 r = hvf_get_supported_cpuid(wi->cpuid.eax, 6044 wi->cpuid.ecx, 6045 wi->cpuid.reg); 6046 } else if (tcg_enabled()) { 6047 r = wi->tcg_features; 6048 } else { 6049 return ~0; 6050 } 6051 #ifndef TARGET_X86_64 6052 if (w == FEAT_8000_0001_EDX) { 6053 /* 6054 * 32-bit TCG can emulate 64-bit compatibility mode. If there is no 6055 * way for userspace to get out of its 32-bit jail, we can leave 6056 * the LM bit set. 6057 */ 6058 uint32_t unavail = tcg_enabled() 6059 ? CPUID_EXT2_LM & ~CPUID_EXT2_KERNEL_FEATURES 6060 : CPUID_EXT2_LM; 6061 r &= ~unavail; 6062 } 6063 #endif 6064 if (migratable_only) { 6065 r &= x86_cpu_get_migratable_flags(w); 6066 } 6067 return r; 6068 } 6069 6070 static void x86_cpu_get_supported_cpuid(uint32_t func, uint32_t index, 6071 uint32_t *eax, uint32_t *ebx, 6072 uint32_t *ecx, uint32_t *edx) 6073 { 6074 if (kvm_enabled()) { 6075 *eax = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EAX); 6076 *ebx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EBX); 6077 *ecx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_ECX); 6078 *edx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EDX); 6079 } else if (hvf_enabled()) { 6080 *eax = hvf_get_supported_cpuid(func, index, R_EAX); 6081 *ebx = hvf_get_supported_cpuid(func, index, R_EBX); 6082 *ecx = hvf_get_supported_cpuid(func, index, R_ECX); 6083 *edx = hvf_get_supported_cpuid(func, index, R_EDX); 6084 } else { 6085 *eax = 0; 6086 *ebx = 0; 6087 *ecx = 0; 6088 *edx = 0; 6089 } 6090 } 6091 6092 static void x86_cpu_get_cache_cpuid(uint32_t func, uint32_t index, 6093 uint32_t *eax, uint32_t *ebx, 6094 uint32_t *ecx, uint32_t *edx) 6095 { 6096 uint32_t level, unused; 6097 6098 /* Only return valid host leaves. */ 6099 switch (func) { 6100 case 2: 6101 case 4: 6102 host_cpuid(0, 0, &level, &unused, &unused, &unused); 6103 break; 6104 case 0x80000005: 6105 case 0x80000006: 6106 case 0x8000001d: 6107 host_cpuid(0x80000000, 0, &level, &unused, &unused, &unused); 6108 break; 6109 default: 6110 return; 6111 } 6112 6113 if (func > level) { 6114 *eax = 0; 6115 *ebx = 0; 6116 *ecx = 0; 6117 *edx = 0; 6118 } else { 6119 host_cpuid(func, index, eax, ebx, ecx, edx); 6120 } 6121 } 6122 6123 /* 6124 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 6125 */ 6126 void x86_cpu_apply_props(X86CPU *cpu, PropValue *props) 6127 { 6128 PropValue *pv; 6129 for (pv = props; pv->prop; pv++) { 6130 if (!pv->value) { 6131 continue; 6132 } 6133 object_property_parse(OBJECT(cpu), pv->prop, pv->value, 6134 &error_abort); 6135 } 6136 } 6137 6138 /* 6139 * Apply properties for the CPU model version specified in model. 6140 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 6141 */ 6142 6143 static void x86_cpu_apply_version_props(X86CPU *cpu, X86CPUModel *model) 6144 { 6145 const X86CPUVersionDefinition *vdef; 6146 X86CPUVersion version = x86_cpu_model_resolve_version(model); 6147 6148 if (version == CPU_VERSION_LEGACY) { 6149 return; 6150 } 6151 6152 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) { 6153 PropValue *p; 6154 6155 for (p = vdef->props; p && p->prop; p++) { 6156 object_property_parse(OBJECT(cpu), p->prop, p->value, 6157 &error_abort); 6158 } 6159 6160 if (vdef->version == version) { 6161 break; 6162 } 6163 } 6164 6165 /* 6166 * If we reached the end of the list, version number was invalid 6167 */ 6168 assert(vdef->version == version); 6169 } 6170 6171 static const CPUCaches *x86_cpu_get_versioned_cache_info(X86CPU *cpu, 6172 X86CPUModel *model) 6173 { 6174 const X86CPUVersionDefinition *vdef; 6175 X86CPUVersion version = x86_cpu_model_resolve_version(model); 6176 const CPUCaches *cache_info = model->cpudef->cache_info; 6177 6178 if (version == CPU_VERSION_LEGACY) { 6179 return cache_info; 6180 } 6181 6182 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) { 6183 if (vdef->cache_info) { 6184 cache_info = vdef->cache_info; 6185 } 6186 6187 if (vdef->version == version) { 6188 break; 6189 } 6190 } 6191 6192 assert(vdef->version == version); 6193 return cache_info; 6194 } 6195 6196 /* 6197 * Load data from X86CPUDefinition into a X86CPU object. 6198 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 6199 */ 6200 static void x86_cpu_load_model(X86CPU *cpu, X86CPUModel *model) 6201 { 6202 const X86CPUDefinition *def = model->cpudef; 6203 CPUX86State *env = &cpu->env; 6204 FeatureWord w; 6205 6206 /*NOTE: any property set by this function should be returned by 6207 * x86_cpu_static_props(), so static expansion of 6208 * query-cpu-model-expansion is always complete. 6209 */ 6210 6211 /* CPU models only set _minimum_ values for level/xlevel: */ 6212 object_property_set_uint(OBJECT(cpu), "min-level", def->level, 6213 &error_abort); 6214 object_property_set_uint(OBJECT(cpu), "min-xlevel", def->xlevel, 6215 &error_abort); 6216 6217 object_property_set_int(OBJECT(cpu), "family", def->family, &error_abort); 6218 object_property_set_int(OBJECT(cpu), "model", def->model, &error_abort); 6219 object_property_set_int(OBJECT(cpu), "stepping", def->stepping, 6220 &error_abort); 6221 object_property_set_str(OBJECT(cpu), "model-id", def->model_id, 6222 &error_abort); 6223 for (w = 0; w < FEATURE_WORDS; w++) { 6224 env->features[w] = def->features[w]; 6225 } 6226 6227 /* legacy-cache defaults to 'off' if CPU model provides cache info */ 6228 cpu->legacy_cache = !x86_cpu_get_versioned_cache_info(cpu, model); 6229 6230 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR; 6231 6232 /* sysenter isn't supported in compatibility mode on AMD, 6233 * syscall isn't supported in compatibility mode on Intel. 6234 * Normally we advertise the actual CPU vendor, but you can 6235 * override this using the 'vendor' property if you want to use 6236 * KVM's sysenter/syscall emulation in compatibility mode and 6237 * when doing cross vendor migration 6238 */ 6239 6240 /* 6241 * vendor property is set here but then overloaded with the 6242 * host cpu vendor for KVM and HVF. 6243 */ 6244 object_property_set_str(OBJECT(cpu), "vendor", def->vendor, &error_abort); 6245 6246 x86_cpu_apply_version_props(cpu, model); 6247 6248 /* 6249 * Properties in versioned CPU model are not user specified features. 6250 * We can simply clear env->user_features here since it will be filled later 6251 * in x86_cpu_expand_features() based on plus_features and minus_features. 6252 */ 6253 memset(&env->user_features, 0, sizeof(env->user_features)); 6254 } 6255 6256 static const gchar *x86_gdb_arch_name(CPUState *cs) 6257 { 6258 #ifdef TARGET_X86_64 6259 return "i386:x86-64"; 6260 #else 6261 return "i386"; 6262 #endif 6263 } 6264 6265 static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data) 6266 { 6267 X86CPUModel *model = data; 6268 X86CPUClass *xcc = X86_CPU_CLASS(oc); 6269 CPUClass *cc = CPU_CLASS(oc); 6270 6271 xcc->model = model; 6272 xcc->migration_safe = true; 6273 cc->deprecation_note = model->cpudef->deprecation_note; 6274 } 6275 6276 static void x86_register_cpu_model_type(const char *name, X86CPUModel *model) 6277 { 6278 g_autofree char *typename = x86_cpu_type_name(name); 6279 TypeInfo ti = { 6280 .name = typename, 6281 .parent = TYPE_X86_CPU, 6282 .class_init = x86_cpu_cpudef_class_init, 6283 .class_data = model, 6284 }; 6285 6286 type_register(&ti); 6287 } 6288 6289 6290 /* 6291 * register builtin_x86_defs; 6292 * "max", "base" and subclasses ("host") are not registered here. 6293 * See x86_cpu_register_types for all model registrations. 6294 */ 6295 static void x86_register_cpudef_types(const X86CPUDefinition *def) 6296 { 6297 X86CPUModel *m; 6298 const X86CPUVersionDefinition *vdef; 6299 6300 /* AMD aliases are handled at runtime based on CPUID vendor, so 6301 * they shouldn't be set on the CPU model table. 6302 */ 6303 assert(!(def->features[FEAT_8000_0001_EDX] & CPUID_EXT2_AMD_ALIASES)); 6304 /* catch mistakes instead of silently truncating model_id when too long */ 6305 assert(def->model_id && strlen(def->model_id) <= 48); 6306 6307 /* Unversioned model: */ 6308 m = g_new0(X86CPUModel, 1); 6309 m->cpudef = def; 6310 m->version = CPU_VERSION_AUTO; 6311 m->is_alias = true; 6312 x86_register_cpu_model_type(def->name, m); 6313 6314 /* Versioned models: */ 6315 6316 for (vdef = x86_cpu_def_get_versions(def); vdef->version; vdef++) { 6317 g_autofree char *name = 6318 x86_cpu_versioned_model_name(def, vdef->version); 6319 6320 m = g_new0(X86CPUModel, 1); 6321 m->cpudef = def; 6322 m->version = vdef->version; 6323 m->note = vdef->note; 6324 x86_register_cpu_model_type(name, m); 6325 6326 if (vdef->alias) { 6327 X86CPUModel *am = g_new0(X86CPUModel, 1); 6328 am->cpudef = def; 6329 am->version = vdef->version; 6330 am->is_alias = true; 6331 x86_register_cpu_model_type(vdef->alias, am); 6332 } 6333 } 6334 6335 } 6336 6337 uint32_t cpu_x86_virtual_addr_width(CPUX86State *env) 6338 { 6339 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57) { 6340 return 57; /* 57 bits virtual */ 6341 } else { 6342 return 48; /* 48 bits virtual */ 6343 } 6344 } 6345 6346 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, 6347 uint32_t *eax, uint32_t *ebx, 6348 uint32_t *ecx, uint32_t *edx) 6349 { 6350 X86CPU *cpu = env_archcpu(env); 6351 CPUState *cs = env_cpu(env); 6352 uint32_t limit; 6353 uint32_t signature[3]; 6354 X86CPUTopoInfo topo_info; 6355 uint32_t cores_per_pkg; 6356 uint32_t threads_per_pkg; 6357 6358 topo_info.dies_per_pkg = env->nr_dies; 6359 topo_info.modules_per_die = env->nr_modules; 6360 topo_info.cores_per_module = cs->nr_cores / env->nr_dies / env->nr_modules; 6361 topo_info.threads_per_core = cs->nr_threads; 6362 6363 cores_per_pkg = topo_info.cores_per_module * topo_info.modules_per_die * 6364 topo_info.dies_per_pkg; 6365 threads_per_pkg = cores_per_pkg * topo_info.threads_per_core; 6366 6367 /* Calculate & apply limits for different index ranges */ 6368 if (index >= 0xC0000000) { 6369 limit = env->cpuid_xlevel2; 6370 } else if (index >= 0x80000000) { 6371 limit = env->cpuid_xlevel; 6372 } else if (index >= 0x40000000) { 6373 limit = 0x40000001; 6374 } else { 6375 limit = env->cpuid_level; 6376 } 6377 6378 if (index > limit) { 6379 /* Intel documentation states that invalid EAX input will 6380 * return the same information as EAX=cpuid_level 6381 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID) 6382 */ 6383 index = env->cpuid_level; 6384 } 6385 6386 switch(index) { 6387 case 0: 6388 *eax = env->cpuid_level; 6389 *ebx = env->cpuid_vendor1; 6390 *edx = env->cpuid_vendor2; 6391 *ecx = env->cpuid_vendor3; 6392 break; 6393 case 1: 6394 *eax = env->cpuid_version; 6395 *ebx = (cpu->apic_id << 24) | 6396 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */ 6397 *ecx = env->features[FEAT_1_ECX]; 6398 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) { 6399 *ecx |= CPUID_EXT_OSXSAVE; 6400 } 6401 *edx = env->features[FEAT_1_EDX]; 6402 if (threads_per_pkg > 1) { 6403 *ebx |= threads_per_pkg << 16; 6404 *edx |= CPUID_HT; 6405 } 6406 if (!cpu->enable_pmu) { 6407 *ecx &= ~CPUID_EXT_PDCM; 6408 } 6409 break; 6410 case 2: 6411 /* cache info: needed for Pentium Pro compatibility */ 6412 if (cpu->cache_info_passthrough) { 6413 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 6414 break; 6415 } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { 6416 *eax = *ebx = *ecx = *edx = 0; 6417 break; 6418 } 6419 *eax = 1; /* Number of CPUID[EAX=2] calls required */ 6420 *ebx = 0; 6421 if (!cpu->enable_l3_cache) { 6422 *ecx = 0; 6423 } else { 6424 *ecx = cpuid2_cache_descriptor(env->cache_info_cpuid2.l3_cache); 6425 } 6426 *edx = (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1d_cache) << 16) | 6427 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1i_cache) << 8) | 6428 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l2_cache)); 6429 break; 6430 case 4: 6431 /* cache info: needed for Core compatibility */ 6432 if (cpu->cache_info_passthrough) { 6433 x86_cpu_get_cache_cpuid(index, count, eax, ebx, ecx, edx); 6434 /* 6435 * QEMU has its own number of cores/logical cpus, 6436 * set 24..14, 31..26 bit to configured values 6437 */ 6438 if (*eax & 31) { 6439 int host_vcpus_per_cache = 1 + ((*eax & 0x3FFC000) >> 14); 6440 6441 if (cores_per_pkg > 1) { 6442 *eax &= ~0xFC000000; 6443 *eax |= max_core_ids_in_package(&topo_info) << 26; 6444 } 6445 if (host_vcpus_per_cache > threads_per_pkg) { 6446 *eax &= ~0x3FFC000; 6447 6448 /* Share the cache at package level. */ 6449 *eax |= max_thread_ids_for_cache(&topo_info, 6450 CPU_TOPO_LEVEL_PACKAGE) << 14; 6451 } 6452 } 6453 } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { 6454 *eax = *ebx = *ecx = *edx = 0; 6455 } else { 6456 *eax = 0; 6457 6458 switch (count) { 6459 case 0: /* L1 dcache info */ 6460 encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache, 6461 &topo_info, 6462 eax, ebx, ecx, edx); 6463 if (!cpu->l1_cache_per_core) { 6464 *eax &= ~MAKE_64BIT_MASK(14, 12); 6465 } 6466 break; 6467 case 1: /* L1 icache info */ 6468 encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache, 6469 &topo_info, 6470 eax, ebx, ecx, edx); 6471 if (!cpu->l1_cache_per_core) { 6472 *eax &= ~MAKE_64BIT_MASK(14, 12); 6473 } 6474 break; 6475 case 2: /* L2 cache info */ 6476 encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache, 6477 &topo_info, 6478 eax, ebx, ecx, edx); 6479 break; 6480 case 3: /* L3 cache info */ 6481 if (cpu->enable_l3_cache) { 6482 encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache, 6483 &topo_info, 6484 eax, ebx, ecx, edx); 6485 break; 6486 } 6487 /* fall through */ 6488 default: /* end of info */ 6489 *eax = *ebx = *ecx = *edx = 0; 6490 break; 6491 } 6492 } 6493 break; 6494 case 5: 6495 /* MONITOR/MWAIT Leaf */ 6496 *eax = cpu->mwait.eax; /* Smallest monitor-line size in bytes */ 6497 *ebx = cpu->mwait.ebx; /* Largest monitor-line size in bytes */ 6498 *ecx = cpu->mwait.ecx; /* flags */ 6499 *edx = cpu->mwait.edx; /* mwait substates */ 6500 break; 6501 case 6: 6502 /* Thermal and Power Leaf */ 6503 *eax = env->features[FEAT_6_EAX]; 6504 *ebx = 0; 6505 *ecx = 0; 6506 *edx = 0; 6507 break; 6508 case 7: 6509 /* Structured Extended Feature Flags Enumeration Leaf */ 6510 if (count == 0) { 6511 uint32_t eax_0_unused, ebx_0, ecx_0, edx_0_unused; 6512 6513 /* Maximum ECX value for sub-leaves */ 6514 *eax = env->cpuid_level_func7; 6515 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */ 6516 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */ 6517 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) { 6518 *ecx |= CPUID_7_0_ECX_OSPKE; 6519 } 6520 *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */ 6521 6522 /* 6523 * SGX cannot be emulated in software. If hardware does not 6524 * support enabling SGX and/or SGX flexible launch control, 6525 * then we need to update the VM's CPUID values accordingly. 6526 */ 6527 x86_cpu_get_supported_cpuid(0x7, 0, 6528 &eax_0_unused, &ebx_0, 6529 &ecx_0, &edx_0_unused); 6530 if ((*ebx & CPUID_7_0_EBX_SGX) && !(ebx_0 & CPUID_7_0_EBX_SGX)) { 6531 *ebx &= ~CPUID_7_0_EBX_SGX; 6532 } 6533 6534 if ((*ecx & CPUID_7_0_ECX_SGX_LC) 6535 && (!(*ebx & CPUID_7_0_EBX_SGX) || !(ecx_0 & CPUID_7_0_ECX_SGX_LC))) { 6536 *ecx &= ~CPUID_7_0_ECX_SGX_LC; 6537 } 6538 } else if (count == 1) { 6539 *eax = env->features[FEAT_7_1_EAX]; 6540 *edx = env->features[FEAT_7_1_EDX]; 6541 *ebx = 0; 6542 *ecx = 0; 6543 } else if (count == 2) { 6544 *edx = env->features[FEAT_7_2_EDX]; 6545 *eax = 0; 6546 *ebx = 0; 6547 *ecx = 0; 6548 } else { 6549 *eax = 0; 6550 *ebx = 0; 6551 *ecx = 0; 6552 *edx = 0; 6553 } 6554 break; 6555 case 9: 6556 /* Direct Cache Access Information Leaf */ 6557 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */ 6558 *ebx = 0; 6559 *ecx = 0; 6560 *edx = 0; 6561 break; 6562 case 0xA: 6563 /* Architectural Performance Monitoring Leaf */ 6564 if (cpu->enable_pmu) { 6565 x86_cpu_get_supported_cpuid(0xA, count, eax, ebx, ecx, edx); 6566 } else { 6567 *eax = 0; 6568 *ebx = 0; 6569 *ecx = 0; 6570 *edx = 0; 6571 } 6572 break; 6573 case 0xB: 6574 /* Extended Topology Enumeration Leaf */ 6575 if (!cpu->enable_cpuid_0xb) { 6576 *eax = *ebx = *ecx = *edx = 0; 6577 break; 6578 } 6579 6580 *ecx = count & 0xff; 6581 *edx = cpu->apic_id; 6582 6583 switch (count) { 6584 case 0: 6585 *eax = apicid_core_offset(&topo_info); 6586 *ebx = topo_info.threads_per_core; 6587 *ecx |= CPUID_B_ECX_TOPO_LEVEL_SMT << 8; 6588 break; 6589 case 1: 6590 *eax = apicid_pkg_offset(&topo_info); 6591 *ebx = threads_per_pkg; 6592 *ecx |= CPUID_B_ECX_TOPO_LEVEL_CORE << 8; 6593 break; 6594 default: 6595 *eax = 0; 6596 *ebx = 0; 6597 *ecx |= CPUID_B_ECX_TOPO_LEVEL_INVALID << 8; 6598 } 6599 6600 assert(!(*eax & ~0x1f)); 6601 *ebx &= 0xffff; /* The count doesn't need to be reliable. */ 6602 break; 6603 case 0x1C: 6604 if (cpu->enable_pmu && (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) { 6605 x86_cpu_get_supported_cpuid(0x1C, 0, eax, ebx, ecx, edx); 6606 *edx = 0; 6607 } 6608 break; 6609 case 0x1F: 6610 /* V2 Extended Topology Enumeration Leaf */ 6611 if (!x86_has_extended_topo(env->avail_cpu_topo)) { 6612 *eax = *ebx = *ecx = *edx = 0; 6613 break; 6614 } 6615 6616 encode_topo_cpuid1f(env, count, &topo_info, eax, ebx, ecx, edx); 6617 break; 6618 case 0xD: { 6619 /* Processor Extended State */ 6620 *eax = 0; 6621 *ebx = 0; 6622 *ecx = 0; 6623 *edx = 0; 6624 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { 6625 break; 6626 } 6627 6628 if (count == 0) { 6629 *ecx = xsave_area_size(x86_cpu_xsave_xcr0_components(cpu), false); 6630 *eax = env->features[FEAT_XSAVE_XCR0_LO]; 6631 *edx = env->features[FEAT_XSAVE_XCR0_HI]; 6632 /* 6633 * The initial value of xcr0 and ebx == 0, On host without kvm 6634 * commit 412a3c41(e.g., CentOS 6), the ebx's value always == 0 6635 * even through guest update xcr0, this will crash some legacy guest 6636 * (e.g., CentOS 6), So set ebx == ecx to workaround it. 6637 */ 6638 *ebx = kvm_enabled() ? *ecx : xsave_area_size(env->xcr0, false); 6639 } else if (count == 1) { 6640 uint64_t xstate = x86_cpu_xsave_xcr0_components(cpu) | 6641 x86_cpu_xsave_xss_components(cpu); 6642 6643 *eax = env->features[FEAT_XSAVE]; 6644 *ebx = xsave_area_size(xstate, true); 6645 *ecx = env->features[FEAT_XSAVE_XSS_LO]; 6646 *edx = env->features[FEAT_XSAVE_XSS_HI]; 6647 if (kvm_enabled() && cpu->enable_pmu && 6648 (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR) && 6649 (*eax & CPUID_XSAVE_XSAVES)) { 6650 *ecx |= XSTATE_ARCH_LBR_MASK; 6651 } else { 6652 *ecx &= ~XSTATE_ARCH_LBR_MASK; 6653 } 6654 } else if (count == 0xf && cpu->enable_pmu 6655 && (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) { 6656 x86_cpu_get_supported_cpuid(0xD, count, eax, ebx, ecx, edx); 6657 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) { 6658 const ExtSaveArea *esa = &x86_ext_save_areas[count]; 6659 6660 if (x86_cpu_xsave_xcr0_components(cpu) & (1ULL << count)) { 6661 *eax = esa->size; 6662 *ebx = esa->offset; 6663 *ecx = esa->ecx & 6664 (ESA_FEATURE_ALIGN64_MASK | ESA_FEATURE_XFD_MASK); 6665 } else if (x86_cpu_xsave_xss_components(cpu) & (1ULL << count)) { 6666 *eax = esa->size; 6667 *ebx = 0; 6668 *ecx = 1; 6669 } 6670 } 6671 break; 6672 } 6673 case 0x12: 6674 #ifndef CONFIG_USER_ONLY 6675 if (!kvm_enabled() || 6676 !(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX)) { 6677 *eax = *ebx = *ecx = *edx = 0; 6678 break; 6679 } 6680 6681 /* 6682 * SGX sub-leafs CPUID.0x12.{0x2..N} enumerate EPC sections. Retrieve 6683 * the EPC properties, e.g. confidentiality and integrity, from the 6684 * host's first EPC section, i.e. assume there is one EPC section or 6685 * that all EPC sections have the same security properties. 6686 */ 6687 if (count > 1) { 6688 uint64_t epc_addr, epc_size; 6689 6690 if (sgx_epc_get_section(count - 2, &epc_addr, &epc_size)) { 6691 *eax = *ebx = *ecx = *edx = 0; 6692 break; 6693 } 6694 host_cpuid(index, 2, eax, ebx, ecx, edx); 6695 *eax = (uint32_t)(epc_addr & 0xfffff000) | 0x1; 6696 *ebx = (uint32_t)(epc_addr >> 32); 6697 *ecx = (uint32_t)(epc_size & 0xfffff000) | (*ecx & 0xf); 6698 *edx = (uint32_t)(epc_size >> 32); 6699 break; 6700 } 6701 6702 /* 6703 * SGX sub-leafs CPUID.0x12.{0x0,0x1} are heavily dependent on hardware 6704 * and KVM, i.e. QEMU cannot emulate features to override what KVM 6705 * supports. Features can be further restricted by userspace, but not 6706 * made more permissive. 6707 */ 6708 x86_cpu_get_supported_cpuid(0x12, count, eax, ebx, ecx, edx); 6709 6710 if (count == 0) { 6711 *eax &= env->features[FEAT_SGX_12_0_EAX]; 6712 *ebx &= env->features[FEAT_SGX_12_0_EBX]; 6713 } else { 6714 *eax &= env->features[FEAT_SGX_12_1_EAX]; 6715 *ebx &= 0; /* ebx reserve */ 6716 *ecx &= env->features[FEAT_XSAVE_XCR0_LO]; 6717 *edx &= env->features[FEAT_XSAVE_XCR0_HI]; 6718 6719 /* FP and SSE are always allowed regardless of XSAVE/XCR0. */ 6720 *ecx |= XSTATE_FP_MASK | XSTATE_SSE_MASK; 6721 6722 /* Access to PROVISIONKEY requires additional credentials. */ 6723 if ((*eax & (1U << 4)) && 6724 !kvm_enable_sgx_provisioning(cs->kvm_state)) { 6725 *eax &= ~(1U << 4); 6726 } 6727 } 6728 #endif 6729 break; 6730 case 0x14: { 6731 /* Intel Processor Trace Enumeration */ 6732 *eax = 0; 6733 *ebx = 0; 6734 *ecx = 0; 6735 *edx = 0; 6736 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) || 6737 !kvm_enabled()) { 6738 break; 6739 } 6740 6741 /* 6742 * If these are changed, they should stay in sync with 6743 * x86_cpu_filter_features(). 6744 */ 6745 if (count == 0) { 6746 *eax = INTEL_PT_MAX_SUBLEAF; 6747 *ebx = INTEL_PT_MINIMAL_EBX; 6748 *ecx = INTEL_PT_MINIMAL_ECX; 6749 if (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP) { 6750 *ecx |= CPUID_14_0_ECX_LIP; 6751 } 6752 } else if (count == 1) { 6753 *eax = INTEL_PT_MTC_BITMAP | INTEL_PT_ADDR_RANGES_NUM; 6754 *ebx = INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP; 6755 } 6756 break; 6757 } 6758 case 0x1D: { 6759 /* AMX TILE, for now hardcoded for Sapphire Rapids*/ 6760 *eax = 0; 6761 *ebx = 0; 6762 *ecx = 0; 6763 *edx = 0; 6764 if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) { 6765 break; 6766 } 6767 6768 if (count == 0) { 6769 /* Highest numbered palette subleaf */ 6770 *eax = INTEL_AMX_TILE_MAX_SUBLEAF; 6771 } else if (count == 1) { 6772 *eax = INTEL_AMX_TOTAL_TILE_BYTES | 6773 (INTEL_AMX_BYTES_PER_TILE << 16); 6774 *ebx = INTEL_AMX_BYTES_PER_ROW | (INTEL_AMX_TILE_MAX_NAMES << 16); 6775 *ecx = INTEL_AMX_TILE_MAX_ROWS; 6776 } 6777 break; 6778 } 6779 case 0x1E: { 6780 /* AMX TMUL, for now hardcoded for Sapphire Rapids */ 6781 *eax = 0; 6782 *ebx = 0; 6783 *ecx = 0; 6784 *edx = 0; 6785 if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) { 6786 break; 6787 } 6788 6789 if (count == 0) { 6790 /* Highest numbered palette subleaf */ 6791 *ebx = INTEL_AMX_TMUL_MAX_K | (INTEL_AMX_TMUL_MAX_N << 8); 6792 } 6793 break; 6794 } 6795 case 0x40000000: 6796 /* 6797 * CPUID code in kvm_arch_init_vcpu() ignores stuff 6798 * set here, but we restrict to TCG none the less. 6799 */ 6800 if (tcg_enabled() && cpu->expose_tcg) { 6801 memcpy(signature, "TCGTCGTCGTCG", 12); 6802 *eax = 0x40000001; 6803 *ebx = signature[0]; 6804 *ecx = signature[1]; 6805 *edx = signature[2]; 6806 } else { 6807 *eax = 0; 6808 *ebx = 0; 6809 *ecx = 0; 6810 *edx = 0; 6811 } 6812 break; 6813 case 0x40000001: 6814 *eax = 0; 6815 *ebx = 0; 6816 *ecx = 0; 6817 *edx = 0; 6818 break; 6819 case 0x80000000: 6820 *eax = env->cpuid_xlevel; 6821 *ebx = env->cpuid_vendor1; 6822 *edx = env->cpuid_vendor2; 6823 *ecx = env->cpuid_vendor3; 6824 break; 6825 case 0x80000001: 6826 *eax = env->cpuid_version; 6827 *ebx = 0; 6828 *ecx = env->features[FEAT_8000_0001_ECX]; 6829 *edx = env->features[FEAT_8000_0001_EDX]; 6830 6831 /* The Linux kernel checks for the CMPLegacy bit and 6832 * discards multiple thread information if it is set. 6833 * So don't set it here for Intel to make Linux guests happy. 6834 */ 6835 if (threads_per_pkg > 1) { 6836 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 || 6837 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 || 6838 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) { 6839 *ecx |= 1 << 1; /* CmpLegacy bit */ 6840 } 6841 } 6842 if (tcg_enabled() && env->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && 6843 !(env->hflags & HF_LMA_MASK)) { 6844 *edx &= ~CPUID_EXT2_SYSCALL; 6845 } 6846 break; 6847 case 0x80000002: 6848 case 0x80000003: 6849 case 0x80000004: 6850 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0]; 6851 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1]; 6852 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2]; 6853 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3]; 6854 break; 6855 case 0x80000005: 6856 /* cache info (L1 cache) */ 6857 if (cpu->cache_info_passthrough) { 6858 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 6859 break; 6860 } 6861 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | 6862 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES); 6863 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | 6864 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES); 6865 *ecx = encode_cache_cpuid80000005(env->cache_info_amd.l1d_cache); 6866 *edx = encode_cache_cpuid80000005(env->cache_info_amd.l1i_cache); 6867 break; 6868 case 0x80000006: 6869 /* cache info (L2 cache) */ 6870 if (cpu->cache_info_passthrough) { 6871 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 6872 break; 6873 } 6874 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | 6875 (L2_DTLB_2M_ENTRIES << 16) | 6876 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | 6877 (L2_ITLB_2M_ENTRIES); 6878 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | 6879 (L2_DTLB_4K_ENTRIES << 16) | 6880 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | 6881 (L2_ITLB_4K_ENTRIES); 6882 encode_cache_cpuid80000006(env->cache_info_amd.l2_cache, 6883 cpu->enable_l3_cache ? 6884 env->cache_info_amd.l3_cache : NULL, 6885 ecx, edx); 6886 break; 6887 case 0x80000007: 6888 *eax = 0; 6889 *ebx = 0; 6890 *ecx = 0; 6891 *edx = env->features[FEAT_8000_0007_EDX]; 6892 break; 6893 case 0x80000008: 6894 /* virtual & phys address size in low 2 bytes. */ 6895 *eax = cpu->phys_bits; 6896 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 6897 /* 64 bit processor */ 6898 *eax |= (cpu_x86_virtual_addr_width(env) << 8); 6899 *eax |= (cpu->guest_phys_bits << 16); 6900 } 6901 *ebx = env->features[FEAT_8000_0008_EBX]; 6902 if (threads_per_pkg > 1) { 6903 /* 6904 * Bits 15:12 is "The number of bits in the initial 6905 * Core::X86::Apic::ApicId[ApicId] value that indicate 6906 * thread ID within a package". 6907 * Bits 7:0 is "The number of threads in the package is NC+1" 6908 */ 6909 *ecx = (apicid_pkg_offset(&topo_info) << 12) | 6910 (threads_per_pkg - 1); 6911 } else { 6912 *ecx = 0; 6913 } 6914 *edx = 0; 6915 break; 6916 case 0x8000000A: 6917 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { 6918 *eax = 0x00000001; /* SVM Revision */ 6919 *ebx = 0x00000010; /* nr of ASIDs */ 6920 *ecx = 0; 6921 *edx = env->features[FEAT_SVM]; /* optional features */ 6922 } else { 6923 *eax = 0; 6924 *ebx = 0; 6925 *ecx = 0; 6926 *edx = 0; 6927 } 6928 break; 6929 case 0x8000001D: 6930 *eax = 0; 6931 if (cpu->cache_info_passthrough) { 6932 x86_cpu_get_cache_cpuid(index, count, eax, ebx, ecx, edx); 6933 break; 6934 } 6935 switch (count) { 6936 case 0: /* L1 dcache info */ 6937 encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache, 6938 &topo_info, eax, ebx, ecx, edx); 6939 break; 6940 case 1: /* L1 icache info */ 6941 encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache, 6942 &topo_info, eax, ebx, ecx, edx); 6943 break; 6944 case 2: /* L2 cache info */ 6945 encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache, 6946 &topo_info, eax, ebx, ecx, edx); 6947 break; 6948 case 3: /* L3 cache info */ 6949 encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache, 6950 &topo_info, eax, ebx, ecx, edx); 6951 break; 6952 default: /* end of info */ 6953 *eax = *ebx = *ecx = *edx = 0; 6954 break; 6955 } 6956 break; 6957 case 0x8000001E: 6958 if (cpu->core_id <= 255) { 6959 encode_topo_cpuid8000001e(cpu, &topo_info, eax, ebx, ecx, edx); 6960 } else { 6961 *eax = 0; 6962 *ebx = 0; 6963 *ecx = 0; 6964 *edx = 0; 6965 } 6966 break; 6967 case 0xC0000000: 6968 *eax = env->cpuid_xlevel2; 6969 *ebx = 0; 6970 *ecx = 0; 6971 *edx = 0; 6972 break; 6973 case 0xC0000001: 6974 /* Support for VIA CPU's CPUID instruction */ 6975 *eax = env->cpuid_version; 6976 *ebx = 0; 6977 *ecx = 0; 6978 *edx = env->features[FEAT_C000_0001_EDX]; 6979 break; 6980 case 0xC0000002: 6981 case 0xC0000003: 6982 case 0xC0000004: 6983 /* Reserved for the future, and now filled with zero */ 6984 *eax = 0; 6985 *ebx = 0; 6986 *ecx = 0; 6987 *edx = 0; 6988 break; 6989 case 0x8000001F: 6990 *eax = *ebx = *ecx = *edx = 0; 6991 if (sev_enabled()) { 6992 *eax = 0x2; 6993 *eax |= sev_es_enabled() ? 0x8 : 0; 6994 *eax |= sev_snp_enabled() ? 0x10 : 0; 6995 *ebx = sev_get_cbit_position() & 0x3f; /* EBX[5:0] */ 6996 *ebx |= (sev_get_reduced_phys_bits() & 0x3f) << 6; /* EBX[11:6] */ 6997 } 6998 break; 6999 case 0x80000021: 7000 *eax = env->features[FEAT_8000_0021_EAX]; 7001 *ebx = *ecx = *edx = 0; 7002 break; 7003 default: 7004 /* reserved values: zero */ 7005 *eax = 0; 7006 *ebx = 0; 7007 *ecx = 0; 7008 *edx = 0; 7009 break; 7010 } 7011 } 7012 7013 static void x86_cpu_set_sgxlepubkeyhash(CPUX86State *env) 7014 { 7015 #ifndef CONFIG_USER_ONLY 7016 /* Those default values are defined in Skylake HW */ 7017 env->msr_ia32_sgxlepubkeyhash[0] = 0xa6053e051270b7acULL; 7018 env->msr_ia32_sgxlepubkeyhash[1] = 0x6cfbe8ba8b3b413dULL; 7019 env->msr_ia32_sgxlepubkeyhash[2] = 0xc4916d99f2b3735dULL; 7020 env->msr_ia32_sgxlepubkeyhash[3] = 0xd4f8c05909f9bb3bULL; 7021 #endif 7022 } 7023 7024 static void x86_cpu_reset_hold(Object *obj, ResetType type) 7025 { 7026 CPUState *cs = CPU(obj); 7027 X86CPU *cpu = X86_CPU(cs); 7028 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj); 7029 CPUX86State *env = &cpu->env; 7030 target_ulong cr4; 7031 uint64_t xcr0; 7032 int i; 7033 7034 if (xcc->parent_phases.hold) { 7035 xcc->parent_phases.hold(obj, type); 7036 } 7037 7038 memset(env, 0, offsetof(CPUX86State, end_reset_fields)); 7039 7040 env->old_exception = -1; 7041 7042 /* init to reset state */ 7043 env->int_ctl = 0; 7044 env->hflags2 |= HF2_GIF_MASK; 7045 env->hflags2 |= HF2_VGIF_MASK; 7046 env->hflags &= ~HF_GUEST_MASK; 7047 7048 cpu_x86_update_cr0(env, 0x60000010); 7049 env->a20_mask = ~0x0; 7050 env->smbase = 0x30000; 7051 env->msr_smi_count = 0; 7052 7053 env->idt.limit = 0xffff; 7054 env->gdt.limit = 0xffff; 7055 env->ldt.limit = 0xffff; 7056 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT); 7057 env->tr.limit = 0xffff; 7058 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT); 7059 7060 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff, 7061 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK | 7062 DESC_R_MASK | DESC_A_MASK); 7063 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff, 7064 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7065 DESC_A_MASK); 7066 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff, 7067 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7068 DESC_A_MASK); 7069 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff, 7070 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7071 DESC_A_MASK); 7072 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff, 7073 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7074 DESC_A_MASK); 7075 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff, 7076 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 7077 DESC_A_MASK); 7078 7079 env->eip = 0xfff0; 7080 env->regs[R_EDX] = env->cpuid_version; 7081 7082 env->eflags = 0x2; 7083 7084 /* FPU init */ 7085 for (i = 0; i < 8; i++) { 7086 env->fptags[i] = 1; 7087 } 7088 cpu_set_fpuc(env, 0x37f); 7089 7090 env->mxcsr = 0x1f80; 7091 /* All units are in INIT state. */ 7092 env->xstate_bv = 0; 7093 7094 env->pat = 0x0007040600070406ULL; 7095 7096 if (kvm_enabled()) { 7097 /* 7098 * KVM handles TSC = 0 specially and thinks we are hot-plugging 7099 * a new CPU, use 1 instead to force a reset. 7100 */ 7101 if (env->tsc != 0) { 7102 env->tsc = 1; 7103 } 7104 } else { 7105 env->tsc = 0; 7106 } 7107 7108 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT; 7109 if (env->features[FEAT_1_ECX] & CPUID_EXT_MONITOR) { 7110 env->msr_ia32_misc_enable |= MSR_IA32_MISC_ENABLE_MWAIT; 7111 } 7112 7113 memset(env->dr, 0, sizeof(env->dr)); 7114 env->dr[6] = DR6_FIXED_1; 7115 env->dr[7] = DR7_FIXED_1; 7116 cpu_breakpoint_remove_all(cs, BP_CPU); 7117 cpu_watchpoint_remove_all(cs, BP_CPU); 7118 7119 cr4 = 0; 7120 xcr0 = XSTATE_FP_MASK; 7121 7122 #ifdef CONFIG_USER_ONLY 7123 /* Enable all the features for user-mode. */ 7124 if (env->features[FEAT_1_EDX] & CPUID_SSE) { 7125 xcr0 |= XSTATE_SSE_MASK; 7126 } 7127 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 7128 const ExtSaveArea *esa = &x86_ext_save_areas[i]; 7129 if (!((1 << i) & CPUID_XSTATE_XCR0_MASK)) { 7130 continue; 7131 } 7132 if (env->features[esa->feature] & esa->bits) { 7133 xcr0 |= 1ull << i; 7134 } 7135 } 7136 7137 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) { 7138 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK; 7139 } 7140 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) { 7141 cr4 |= CR4_FSGSBASE_MASK; 7142 } 7143 #endif 7144 7145 env->xcr0 = xcr0; 7146 cpu_x86_update_cr4(env, cr4); 7147 7148 /* 7149 * SDM 11.11.5 requires: 7150 * - IA32_MTRR_DEF_TYPE MSR.E = 0 7151 * - IA32_MTRR_PHYSMASKn.V = 0 7152 * All other bits are undefined. For simplification, zero it all. 7153 */ 7154 env->mtrr_deftype = 0; 7155 memset(env->mtrr_var, 0, sizeof(env->mtrr_var)); 7156 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed)); 7157 7158 env->interrupt_injected = -1; 7159 env->exception_nr = -1; 7160 env->exception_pending = 0; 7161 env->exception_injected = 0; 7162 env->exception_has_payload = false; 7163 env->exception_payload = 0; 7164 env->nmi_injected = false; 7165 env->triple_fault_pending = false; 7166 #if !defined(CONFIG_USER_ONLY) 7167 /* We hard-wire the BSP to the first CPU. */ 7168 apic_designate_bsp(cpu->apic_state, cs->cpu_index == 0); 7169 7170 cs->halted = !cpu_is_bsp(cpu); 7171 7172 if (kvm_enabled()) { 7173 kvm_arch_reset_vcpu(cpu); 7174 } 7175 7176 x86_cpu_set_sgxlepubkeyhash(env); 7177 7178 env->amd_tsc_scale_msr = MSR_AMD64_TSC_RATIO_DEFAULT; 7179 7180 #endif 7181 } 7182 7183 void x86_cpu_after_reset(X86CPU *cpu) 7184 { 7185 #ifndef CONFIG_USER_ONLY 7186 if (kvm_enabled()) { 7187 kvm_arch_after_reset_vcpu(cpu); 7188 } 7189 7190 if (cpu->apic_state) { 7191 device_cold_reset(cpu->apic_state); 7192 } 7193 #endif 7194 } 7195 7196 static void mce_init(X86CPU *cpu) 7197 { 7198 CPUX86State *cenv = &cpu->env; 7199 unsigned int bank; 7200 7201 if (((cenv->cpuid_version >> 8) & 0xf) >= 6 7202 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) == 7203 (CPUID_MCE | CPUID_MCA)) { 7204 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF | 7205 (cpu->enable_lmce ? MCG_LMCE_P : 0); 7206 cenv->mcg_ctl = ~(uint64_t)0; 7207 for (bank = 0; bank < MCE_BANKS_DEF; bank++) { 7208 cenv->mce_banks[bank * 4] = ~(uint64_t)0; 7209 } 7210 } 7211 } 7212 7213 static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value) 7214 { 7215 if (*min < value) { 7216 *min = value; 7217 } 7218 } 7219 7220 /* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */ 7221 static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w) 7222 { 7223 CPUX86State *env = &cpu->env; 7224 FeatureWordInfo *fi = &feature_word_info[w]; 7225 uint32_t eax = fi->cpuid.eax; 7226 uint32_t region = eax & 0xF0000000; 7227 7228 assert(feature_word_info[w].type == CPUID_FEATURE_WORD); 7229 if (!env->features[w]) { 7230 return; 7231 } 7232 7233 switch (region) { 7234 case 0x00000000: 7235 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax); 7236 break; 7237 case 0x80000000: 7238 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax); 7239 break; 7240 case 0xC0000000: 7241 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax); 7242 break; 7243 } 7244 7245 if (eax == 7) { 7246 x86_cpu_adjust_level(cpu, &env->cpuid_min_level_func7, 7247 fi->cpuid.ecx); 7248 } 7249 } 7250 7251 /* Calculate XSAVE components based on the configured CPU feature flags */ 7252 static void x86_cpu_enable_xsave_components(X86CPU *cpu) 7253 { 7254 CPUX86State *env = &cpu->env; 7255 int i; 7256 uint64_t mask; 7257 static bool request_perm; 7258 7259 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { 7260 env->features[FEAT_XSAVE_XCR0_LO] = 0; 7261 env->features[FEAT_XSAVE_XCR0_HI] = 0; 7262 env->features[FEAT_XSAVE_XSS_LO] = 0; 7263 env->features[FEAT_XSAVE_XSS_HI] = 0; 7264 return; 7265 } 7266 7267 mask = 0; 7268 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 7269 const ExtSaveArea *esa = &x86_ext_save_areas[i]; 7270 if (env->features[esa->feature] & esa->bits) { 7271 mask |= (1ULL << i); 7272 } 7273 } 7274 7275 /* Only request permission for first vcpu */ 7276 if (kvm_enabled() && !request_perm) { 7277 kvm_request_xsave_components(cpu, mask); 7278 request_perm = true; 7279 } 7280 7281 env->features[FEAT_XSAVE_XCR0_LO] = mask & CPUID_XSTATE_XCR0_MASK; 7282 env->features[FEAT_XSAVE_XCR0_HI] = (mask & CPUID_XSTATE_XCR0_MASK) >> 32; 7283 env->features[FEAT_XSAVE_XSS_LO] = mask & CPUID_XSTATE_XSS_MASK; 7284 env->features[FEAT_XSAVE_XSS_HI] = (mask & CPUID_XSTATE_XSS_MASK) >> 32; 7285 } 7286 7287 /***** Steps involved on loading and filtering CPUID data 7288 * 7289 * When initializing and realizing a CPU object, the steps 7290 * involved in setting up CPUID data are: 7291 * 7292 * 1) Loading CPU model definition (X86CPUDefinition). This is 7293 * implemented by x86_cpu_load_model() and should be completely 7294 * transparent, as it is done automatically by instance_init. 7295 * No code should need to look at X86CPUDefinition structs 7296 * outside instance_init. 7297 * 7298 * 2) CPU expansion. This is done by realize before CPUID 7299 * filtering, and will make sure host/accelerator data is 7300 * loaded for CPU models that depend on host capabilities 7301 * (e.g. "host"). Done by x86_cpu_expand_features(). 7302 * 7303 * 3) CPUID filtering. This initializes extra data related to 7304 * CPUID, and checks if the host supports all capabilities 7305 * required by the CPU. Runnability of a CPU model is 7306 * determined at this step. Done by x86_cpu_filter_features(). 7307 * 7308 * Some operations don't require all steps to be performed. 7309 * More precisely: 7310 * 7311 * - CPU instance creation (instance_init) will run only CPU 7312 * model loading. CPU expansion can't run at instance_init-time 7313 * because host/accelerator data may be not available yet. 7314 * - CPU realization will perform both CPU model expansion and CPUID 7315 * filtering, and return an error in case one of them fails. 7316 * - query-cpu-definitions needs to run all 3 steps. It needs 7317 * to run CPUID filtering, as the 'unavailable-features' 7318 * field is set based on the filtering results. 7319 * - The query-cpu-model-expansion QMP command only needs to run 7320 * CPU model loading and CPU expansion. It should not filter 7321 * any CPUID data based on host capabilities. 7322 */ 7323 7324 /* Expand CPU configuration data, based on configured features 7325 * and host/accelerator capabilities when appropriate. 7326 */ 7327 void x86_cpu_expand_features(X86CPU *cpu, Error **errp) 7328 { 7329 CPUX86State *env = &cpu->env; 7330 FeatureWord w; 7331 int i; 7332 GList *l; 7333 7334 for (l = plus_features; l; l = l->next) { 7335 const char *prop = l->data; 7336 if (!object_property_set_bool(OBJECT(cpu), prop, true, errp)) { 7337 return; 7338 } 7339 } 7340 7341 for (l = minus_features; l; l = l->next) { 7342 const char *prop = l->data; 7343 if (!object_property_set_bool(OBJECT(cpu), prop, false, errp)) { 7344 return; 7345 } 7346 } 7347 7348 /*TODO: Now cpu->max_features doesn't overwrite features 7349 * set using QOM properties, and we can convert 7350 * plus_features & minus_features to global properties 7351 * inside x86_cpu_parse_featurestr() too. 7352 */ 7353 if (cpu->max_features) { 7354 for (w = 0; w < FEATURE_WORDS; w++) { 7355 /* Override only features that weren't set explicitly 7356 * by the user. 7357 */ 7358 env->features[w] |= 7359 x86_cpu_get_supported_feature_word(w, cpu->migratable) & 7360 ~env->user_features[w] & 7361 ~feature_word_info[w].no_autoenable_flags; 7362 } 7363 } 7364 7365 for (i = 0; i < ARRAY_SIZE(feature_dependencies); i++) { 7366 FeatureDep *d = &feature_dependencies[i]; 7367 if (!(env->features[d->from.index] & d->from.mask)) { 7368 uint64_t unavailable_features = env->features[d->to.index] & d->to.mask; 7369 7370 /* Not an error unless the dependent feature was added explicitly. */ 7371 mark_unavailable_features(cpu, d->to.index, 7372 unavailable_features & env->user_features[d->to.index], 7373 "This feature depends on other features that were not requested"); 7374 7375 env->features[d->to.index] &= ~unavailable_features; 7376 } 7377 } 7378 7379 if (!kvm_enabled() || !cpu->expose_kvm) { 7380 env->features[FEAT_KVM] = 0; 7381 } 7382 7383 x86_cpu_enable_xsave_components(cpu); 7384 7385 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */ 7386 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX); 7387 if (cpu->full_cpuid_auto_level) { 7388 x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX); 7389 x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX); 7390 x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX); 7391 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX); 7392 x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EAX); 7393 x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EDX); 7394 x86_cpu_adjust_feat_level(cpu, FEAT_7_2_EDX); 7395 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX); 7396 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX); 7397 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX); 7398 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0008_EBX); 7399 x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX); 7400 x86_cpu_adjust_feat_level(cpu, FEAT_SVM); 7401 x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE); 7402 7403 /* Intel Processor Trace requires CPUID[0x14] */ 7404 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT)) { 7405 if (cpu->intel_pt_auto_level) { 7406 x86_cpu_adjust_level(cpu, &cpu->env.cpuid_min_level, 0x14); 7407 } else if (cpu->env.cpuid_min_level < 0x14) { 7408 mark_unavailable_features(cpu, FEAT_7_0_EBX, 7409 CPUID_7_0_EBX_INTEL_PT, 7410 "Intel PT need CPUID leaf 0x14, please set by \"-cpu ...,intel-pt=on,min-level=0x14\""); 7411 } 7412 } 7413 7414 /* 7415 * Intel CPU topology with multi-dies support requires CPUID[0x1F]. 7416 * For AMD Rome/Milan, cpuid level is 0x10, and guest OS should detect 7417 * extended toplogy by leaf 0xB. Only adjust it for Intel CPU, unless 7418 * cpu->vendor_cpuid_only has been unset for compatibility with older 7419 * machine types. 7420 */ 7421 if (x86_has_extended_topo(env->avail_cpu_topo) && 7422 (IS_INTEL_CPU(env) || !cpu->vendor_cpuid_only)) { 7423 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x1F); 7424 } 7425 7426 /* SVM requires CPUID[0x8000000A] */ 7427 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { 7428 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A); 7429 } 7430 7431 /* SEV requires CPUID[0x8000001F] */ 7432 if (sev_enabled()) { 7433 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F); 7434 } 7435 7436 if (env->features[FEAT_8000_0021_EAX]) { 7437 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x80000021); 7438 } 7439 7440 /* SGX requires CPUID[0x12] for EPC enumeration */ 7441 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX) { 7442 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x12); 7443 } 7444 } 7445 7446 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */ 7447 if (env->cpuid_level_func7 == UINT32_MAX) { 7448 env->cpuid_level_func7 = env->cpuid_min_level_func7; 7449 } 7450 if (env->cpuid_level == UINT32_MAX) { 7451 env->cpuid_level = env->cpuid_min_level; 7452 } 7453 if (env->cpuid_xlevel == UINT32_MAX) { 7454 env->cpuid_xlevel = env->cpuid_min_xlevel; 7455 } 7456 if (env->cpuid_xlevel2 == UINT32_MAX) { 7457 env->cpuid_xlevel2 = env->cpuid_min_xlevel2; 7458 } 7459 7460 if (kvm_enabled() && !kvm_hyperv_expand_features(cpu, errp)) { 7461 return; 7462 } 7463 } 7464 7465 /* 7466 * Finishes initialization of CPUID data, filters CPU feature 7467 * words based on host availability of each feature. 7468 * 7469 * Returns: 0 if all flags are supported by the host, non-zero otherwise. 7470 */ 7471 static void x86_cpu_filter_features(X86CPU *cpu, bool verbose) 7472 { 7473 CPUX86State *env = &cpu->env; 7474 FeatureWord w; 7475 const char *prefix = NULL; 7476 7477 if (verbose) { 7478 prefix = accel_uses_host_cpuid() 7479 ? "host doesn't support requested feature" 7480 : "TCG doesn't support requested feature"; 7481 } 7482 7483 for (w = 0; w < FEATURE_WORDS; w++) { 7484 uint64_t host_feat = 7485 x86_cpu_get_supported_feature_word(w, false); 7486 uint64_t requested_features = env->features[w]; 7487 uint64_t unavailable_features = requested_features & ~host_feat; 7488 mark_unavailable_features(cpu, w, unavailable_features, prefix); 7489 } 7490 7491 /* 7492 * Check that KVM actually allows the processor tracing features that 7493 * are advertised by cpu_x86_cpuid(). Keep these two in sync. 7494 */ 7495 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) && 7496 kvm_enabled()) { 7497 uint32_t eax_0, ebx_0, ecx_0, edx_0_unused; 7498 uint32_t eax_1, ebx_1, ecx_1_unused, edx_1_unused; 7499 7500 x86_cpu_get_supported_cpuid(0x14, 0, 7501 &eax_0, &ebx_0, &ecx_0, &edx_0_unused); 7502 x86_cpu_get_supported_cpuid(0x14, 1, 7503 &eax_1, &ebx_1, &ecx_1_unused, &edx_1_unused); 7504 7505 if (!eax_0 || 7506 ((ebx_0 & INTEL_PT_MINIMAL_EBX) != INTEL_PT_MINIMAL_EBX) || 7507 ((ecx_0 & INTEL_PT_MINIMAL_ECX) != INTEL_PT_MINIMAL_ECX) || 7508 ((eax_1 & INTEL_PT_MTC_BITMAP) != INTEL_PT_MTC_BITMAP) || 7509 ((eax_1 & INTEL_PT_ADDR_RANGES_NUM_MASK) < 7510 INTEL_PT_ADDR_RANGES_NUM) || 7511 ((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) != 7512 (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) || 7513 ((ecx_0 & CPUID_14_0_ECX_LIP) != 7514 (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP))) { 7515 /* 7516 * Processor Trace capabilities aren't configurable, so if the 7517 * host can't emulate the capabilities we report on 7518 * cpu_x86_cpuid(), intel-pt can't be enabled on the current host. 7519 */ 7520 mark_unavailable_features(cpu, FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT, prefix); 7521 } 7522 } 7523 } 7524 7525 static void x86_cpu_hyperv_realize(X86CPU *cpu) 7526 { 7527 size_t len; 7528 7529 /* Hyper-V vendor id */ 7530 if (!cpu->hyperv_vendor) { 7531 object_property_set_str(OBJECT(cpu), "hv-vendor-id", "Microsoft Hv", 7532 &error_abort); 7533 } 7534 len = strlen(cpu->hyperv_vendor); 7535 if (len > 12) { 7536 warn_report("hv-vendor-id truncated to 12 characters"); 7537 len = 12; 7538 } 7539 memset(cpu->hyperv_vendor_id, 0, 12); 7540 memcpy(cpu->hyperv_vendor_id, cpu->hyperv_vendor, len); 7541 7542 /* 'Hv#1' interface identification*/ 7543 cpu->hyperv_interface_id[0] = 0x31237648; 7544 cpu->hyperv_interface_id[1] = 0; 7545 cpu->hyperv_interface_id[2] = 0; 7546 cpu->hyperv_interface_id[3] = 0; 7547 7548 /* Hypervisor implementation limits */ 7549 cpu->hyperv_limits[0] = 64; 7550 cpu->hyperv_limits[1] = 0; 7551 cpu->hyperv_limits[2] = 0; 7552 } 7553 7554 static void x86_cpu_realizefn(DeviceState *dev, Error **errp) 7555 { 7556 CPUState *cs = CPU(dev); 7557 X86CPU *cpu = X86_CPU(dev); 7558 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev); 7559 CPUX86State *env = &cpu->env; 7560 Error *local_err = NULL; 7561 unsigned requested_lbr_fmt; 7562 7563 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) 7564 /* Use pc-relative instructions in system-mode */ 7565 tcg_cflags_set(cs, CF_PCREL); 7566 #endif 7567 7568 if (cpu->apic_id == UNASSIGNED_APIC_ID) { 7569 error_setg(errp, "apic-id property was not initialized properly"); 7570 return; 7571 } 7572 7573 /* 7574 * Process Hyper-V enlightenments. 7575 * Note: this currently has to happen before the expansion of CPU features. 7576 */ 7577 x86_cpu_hyperv_realize(cpu); 7578 7579 x86_cpu_expand_features(cpu, &local_err); 7580 if (local_err) { 7581 goto out; 7582 } 7583 7584 /* 7585 * Override env->features[FEAT_PERF_CAPABILITIES].LBR_FMT 7586 * with user-provided setting. 7587 */ 7588 if (cpu->lbr_fmt != ~PERF_CAP_LBR_FMT) { 7589 if ((cpu->lbr_fmt & PERF_CAP_LBR_FMT) != cpu->lbr_fmt) { 7590 error_setg(errp, "invalid lbr-fmt"); 7591 return; 7592 } 7593 env->features[FEAT_PERF_CAPABILITIES] &= ~PERF_CAP_LBR_FMT; 7594 env->features[FEAT_PERF_CAPABILITIES] |= cpu->lbr_fmt; 7595 } 7596 7597 /* 7598 * vPMU LBR is supported when 1) KVM is enabled 2) Option pmu=on and 7599 * 3)vPMU LBR format matches that of host setting. 7600 */ 7601 requested_lbr_fmt = 7602 env->features[FEAT_PERF_CAPABILITIES] & PERF_CAP_LBR_FMT; 7603 if (requested_lbr_fmt && kvm_enabled()) { 7604 uint64_t host_perf_cap = 7605 x86_cpu_get_supported_feature_word(FEAT_PERF_CAPABILITIES, false); 7606 unsigned host_lbr_fmt = host_perf_cap & PERF_CAP_LBR_FMT; 7607 7608 if (!cpu->enable_pmu) { 7609 error_setg(errp, "vPMU: LBR is unsupported without pmu=on"); 7610 return; 7611 } 7612 if (requested_lbr_fmt != host_lbr_fmt) { 7613 error_setg(errp, "vPMU: the lbr-fmt value (0x%x) does not match " 7614 "the host value (0x%x).", 7615 requested_lbr_fmt, host_lbr_fmt); 7616 return; 7617 } 7618 } 7619 7620 x86_cpu_filter_features(cpu, cpu->check_cpuid || cpu->enforce_cpuid); 7621 7622 if (cpu->enforce_cpuid && x86_cpu_have_filtered_features(cpu)) { 7623 error_setg(&local_err, 7624 accel_uses_host_cpuid() ? 7625 "Host doesn't support requested features" : 7626 "TCG doesn't support requested features"); 7627 goto out; 7628 } 7629 7630 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on 7631 * CPUID[1].EDX. 7632 */ 7633 if (IS_AMD_CPU(env)) { 7634 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES; 7635 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX] 7636 & CPUID_EXT2_AMD_ALIASES); 7637 } 7638 7639 x86_cpu_set_sgxlepubkeyhash(env); 7640 7641 /* 7642 * note: the call to the framework needs to happen after feature expansion, 7643 * but before the checks/modifications to ucode_rev, mwait, phys_bits. 7644 * These may be set by the accel-specific code, 7645 * and the results are subsequently checked / assumed in this function. 7646 */ 7647 cpu_exec_realizefn(cs, &local_err); 7648 if (local_err != NULL) { 7649 error_propagate(errp, local_err); 7650 return; 7651 } 7652 7653 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) { 7654 g_autofree char *name = x86_cpu_class_get_model_name(xcc); 7655 error_setg(&local_err, "CPU model '%s' requires KVM or HVF", name); 7656 goto out; 7657 } 7658 7659 if (cpu->guest_phys_bits == -1) { 7660 /* 7661 * If it was not set by the user, or by the accelerator via 7662 * cpu_exec_realizefn, clear. 7663 */ 7664 cpu->guest_phys_bits = 0; 7665 } 7666 7667 if (cpu->ucode_rev == 0) { 7668 /* 7669 * The default is the same as KVM's. Note that this check 7670 * needs to happen after the evenual setting of ucode_rev in 7671 * accel-specific code in cpu_exec_realizefn. 7672 */ 7673 if (IS_AMD_CPU(env)) { 7674 cpu->ucode_rev = 0x01000065; 7675 } else { 7676 cpu->ucode_rev = 0x100000000ULL; 7677 } 7678 } 7679 7680 /* 7681 * mwait extended info: needed for Core compatibility 7682 * We always wake on interrupt even if host does not have the capability. 7683 * 7684 * requires the accel-specific code in cpu_exec_realizefn to 7685 * have already acquired the CPUID data into cpu->mwait. 7686 */ 7687 cpu->mwait.ecx |= CPUID_MWAIT_EMX | CPUID_MWAIT_IBE; 7688 7689 /* For 64bit systems think about the number of physical bits to present. 7690 * ideally this should be the same as the host; anything other than matching 7691 * the host can cause incorrect guest behaviour. 7692 * QEMU used to pick the magic value of 40 bits that corresponds to 7693 * consumer AMD devices but nothing else. 7694 * 7695 * Note that this code assumes features expansion has already been done 7696 * (as it checks for CPUID_EXT2_LM), and also assumes that potential 7697 * phys_bits adjustments to match the host have been already done in 7698 * accel-specific code in cpu_exec_realizefn. 7699 */ 7700 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 7701 if (cpu->phys_bits && 7702 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS || 7703 cpu->phys_bits < 32)) { 7704 error_setg(errp, "phys-bits should be between 32 and %u " 7705 " (but is %u)", 7706 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits); 7707 return; 7708 } 7709 /* 7710 * 0 means it was not explicitly set by the user (or by machine 7711 * compat_props or by the host code in host-cpu.c). 7712 * In this case, the default is the value used by TCG (40). 7713 */ 7714 if (cpu->phys_bits == 0) { 7715 cpu->phys_bits = TCG_PHYS_ADDR_BITS; 7716 } 7717 if (cpu->guest_phys_bits && 7718 (cpu->guest_phys_bits > cpu->phys_bits || 7719 cpu->guest_phys_bits < 32)) { 7720 error_setg(errp, "guest-phys-bits should be between 32 and %u " 7721 " (but is %u)", 7722 cpu->phys_bits, cpu->guest_phys_bits); 7723 return; 7724 } 7725 } else { 7726 /* For 32 bit systems don't use the user set value, but keep 7727 * phys_bits consistent with what we tell the guest. 7728 */ 7729 if (cpu->phys_bits != 0) { 7730 error_setg(errp, "phys-bits is not user-configurable in 32 bit"); 7731 return; 7732 } 7733 if (cpu->guest_phys_bits != 0) { 7734 error_setg(errp, "guest-phys-bits is not user-configurable in 32 bit"); 7735 return; 7736 } 7737 7738 if (env->features[FEAT_1_EDX] & (CPUID_PSE36 | CPUID_PAE)) { 7739 cpu->phys_bits = 36; 7740 } else { 7741 cpu->phys_bits = 32; 7742 } 7743 } 7744 7745 /* Cache information initialization */ 7746 if (!cpu->legacy_cache) { 7747 const CPUCaches *cache_info = 7748 x86_cpu_get_versioned_cache_info(cpu, xcc->model); 7749 7750 if (!xcc->model || !cache_info) { 7751 g_autofree char *name = x86_cpu_class_get_model_name(xcc); 7752 error_setg(errp, 7753 "CPU model '%s' doesn't support legacy-cache=off", name); 7754 return; 7755 } 7756 env->cache_info_cpuid2 = env->cache_info_cpuid4 = env->cache_info_amd = 7757 *cache_info; 7758 } else { 7759 /* Build legacy cache information */ 7760 env->cache_info_cpuid2.l1d_cache = &legacy_l1d_cache; 7761 env->cache_info_cpuid2.l1i_cache = &legacy_l1i_cache; 7762 env->cache_info_cpuid2.l2_cache = &legacy_l2_cache_cpuid2; 7763 env->cache_info_cpuid2.l3_cache = &legacy_l3_cache; 7764 7765 env->cache_info_cpuid4.l1d_cache = &legacy_l1d_cache; 7766 env->cache_info_cpuid4.l1i_cache = &legacy_l1i_cache; 7767 env->cache_info_cpuid4.l2_cache = &legacy_l2_cache; 7768 env->cache_info_cpuid4.l3_cache = &legacy_l3_cache; 7769 7770 env->cache_info_amd.l1d_cache = &legacy_l1d_cache_amd; 7771 env->cache_info_amd.l1i_cache = &legacy_l1i_cache_amd; 7772 env->cache_info_amd.l2_cache = &legacy_l2_cache_amd; 7773 env->cache_info_amd.l3_cache = &legacy_l3_cache; 7774 } 7775 7776 #ifndef CONFIG_USER_ONLY 7777 MachineState *ms = MACHINE(qdev_get_machine()); 7778 qemu_register_reset(x86_cpu_machine_reset_cb, cpu); 7779 7780 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || ms->smp.cpus > 1) { 7781 x86_cpu_apic_create(cpu, &local_err); 7782 if (local_err != NULL) { 7783 goto out; 7784 } 7785 } 7786 #endif 7787 7788 mce_init(cpu); 7789 7790 qemu_init_vcpu(cs); 7791 7792 /* 7793 * Most Intel and certain AMD CPUs support hyperthreading. Even though QEMU 7794 * fixes this issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX 7795 * based on inputs (sockets,cores,threads), it is still better to give 7796 * users a warning. 7797 * 7798 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise 7799 * cs->nr_threads hasn't be populated yet and the checking is incorrect. 7800 */ 7801 if (IS_AMD_CPU(env) && 7802 !(env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) && 7803 cs->nr_threads > 1) { 7804 warn_report_once("This family of AMD CPU doesn't support " 7805 "hyperthreading(%d). Please configure -smp " 7806 "options properly or try enabling topoext " 7807 "feature.", cs->nr_threads); 7808 } 7809 7810 #ifndef CONFIG_USER_ONLY 7811 x86_cpu_apic_realize(cpu, &local_err); 7812 if (local_err != NULL) { 7813 goto out; 7814 } 7815 #endif /* !CONFIG_USER_ONLY */ 7816 cpu_reset(cs); 7817 7818 xcc->parent_realize(dev, &local_err); 7819 7820 out: 7821 if (local_err != NULL) { 7822 error_propagate(errp, local_err); 7823 return; 7824 } 7825 } 7826 7827 static void x86_cpu_unrealizefn(DeviceState *dev) 7828 { 7829 X86CPU *cpu = X86_CPU(dev); 7830 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev); 7831 7832 #ifndef CONFIG_USER_ONLY 7833 cpu_remove_sync(CPU(dev)); 7834 qemu_unregister_reset(x86_cpu_machine_reset_cb, dev); 7835 #endif 7836 7837 if (cpu->apic_state) { 7838 object_unparent(OBJECT(cpu->apic_state)); 7839 cpu->apic_state = NULL; 7840 } 7841 7842 xcc->parent_unrealize(dev); 7843 } 7844 7845 typedef struct BitProperty { 7846 FeatureWord w; 7847 uint64_t mask; 7848 } BitProperty; 7849 7850 static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name, 7851 void *opaque, Error **errp) 7852 { 7853 X86CPU *cpu = X86_CPU(obj); 7854 BitProperty *fp = opaque; 7855 uint64_t f = cpu->env.features[fp->w]; 7856 bool value = (f & fp->mask) == fp->mask; 7857 visit_type_bool(v, name, &value, errp); 7858 } 7859 7860 static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name, 7861 void *opaque, Error **errp) 7862 { 7863 DeviceState *dev = DEVICE(obj); 7864 X86CPU *cpu = X86_CPU(obj); 7865 BitProperty *fp = opaque; 7866 bool value; 7867 7868 if (dev->realized) { 7869 qdev_prop_set_after_realize(dev, name, errp); 7870 return; 7871 } 7872 7873 if (!visit_type_bool(v, name, &value, errp)) { 7874 return; 7875 } 7876 7877 if (value) { 7878 cpu->env.features[fp->w] |= fp->mask; 7879 } else { 7880 cpu->env.features[fp->w] &= ~fp->mask; 7881 } 7882 cpu->env.user_features[fp->w] |= fp->mask; 7883 } 7884 7885 /* Register a boolean property to get/set a single bit in a uint32_t field. 7886 * 7887 * The same property name can be registered multiple times to make it affect 7888 * multiple bits in the same FeatureWord. In that case, the getter will return 7889 * true only if all bits are set. 7890 */ 7891 static void x86_cpu_register_bit_prop(X86CPUClass *xcc, 7892 const char *prop_name, 7893 FeatureWord w, 7894 int bitnr) 7895 { 7896 ObjectClass *oc = OBJECT_CLASS(xcc); 7897 BitProperty *fp; 7898 ObjectProperty *op; 7899 uint64_t mask = (1ULL << bitnr); 7900 7901 op = object_class_property_find(oc, prop_name); 7902 if (op) { 7903 fp = op->opaque; 7904 assert(fp->w == w); 7905 fp->mask |= mask; 7906 } else { 7907 fp = g_new0(BitProperty, 1); 7908 fp->w = w; 7909 fp->mask = mask; 7910 object_class_property_add(oc, prop_name, "bool", 7911 x86_cpu_get_bit_prop, 7912 x86_cpu_set_bit_prop, 7913 NULL, fp); 7914 } 7915 } 7916 7917 static void x86_cpu_register_feature_bit_props(X86CPUClass *xcc, 7918 FeatureWord w, 7919 int bitnr) 7920 { 7921 FeatureWordInfo *fi = &feature_word_info[w]; 7922 const char *name = fi->feat_names[bitnr]; 7923 7924 if (!name) { 7925 return; 7926 } 7927 7928 /* Property names should use "-" instead of "_". 7929 * Old names containing underscores are registered as aliases 7930 * using object_property_add_alias() 7931 */ 7932 assert(!strchr(name, '_')); 7933 /* aliases don't use "|" delimiters anymore, they are registered 7934 * manually using object_property_add_alias() */ 7935 assert(!strchr(name, '|')); 7936 x86_cpu_register_bit_prop(xcc, name, w, bitnr); 7937 } 7938 7939 static void x86_cpu_post_initfn(Object *obj) 7940 { 7941 accel_cpu_instance_init(CPU(obj)); 7942 } 7943 7944 static void x86_cpu_init_default_topo(X86CPU *cpu) 7945 { 7946 CPUX86State *env = &cpu->env; 7947 7948 env->nr_modules = 1; 7949 env->nr_dies = 1; 7950 7951 /* SMT, core and package levels are set by default. */ 7952 set_bit(CPU_TOPO_LEVEL_SMT, env->avail_cpu_topo); 7953 set_bit(CPU_TOPO_LEVEL_CORE, env->avail_cpu_topo); 7954 set_bit(CPU_TOPO_LEVEL_PACKAGE, env->avail_cpu_topo); 7955 } 7956 7957 static void x86_cpu_initfn(Object *obj) 7958 { 7959 X86CPU *cpu = X86_CPU(obj); 7960 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj); 7961 CPUX86State *env = &cpu->env; 7962 7963 x86_cpu_init_default_topo(cpu); 7964 7965 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo", 7966 x86_cpu_get_feature_words, 7967 NULL, NULL, (void *)env->features); 7968 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo", 7969 x86_cpu_get_feature_words, 7970 NULL, NULL, (void *)cpu->filtered_features); 7971 7972 object_property_add_alias(obj, "sse3", obj, "pni"); 7973 object_property_add_alias(obj, "pclmuldq", obj, "pclmulqdq"); 7974 object_property_add_alias(obj, "sse4-1", obj, "sse4.1"); 7975 object_property_add_alias(obj, "sse4-2", obj, "sse4.2"); 7976 object_property_add_alias(obj, "xd", obj, "nx"); 7977 object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt"); 7978 object_property_add_alias(obj, "i64", obj, "lm"); 7979 7980 object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl"); 7981 object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust"); 7982 object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt"); 7983 object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm"); 7984 object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy"); 7985 object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr"); 7986 object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core"); 7987 object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb"); 7988 object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay"); 7989 object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu"); 7990 object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf"); 7991 object_property_add_alias(obj, "kvm_asyncpf_int", obj, "kvm-asyncpf-int"); 7992 object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time"); 7993 object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi"); 7994 object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt"); 7995 object_property_add_alias(obj, "kvm_poll_control", obj, "kvm-poll-control"); 7996 object_property_add_alias(obj, "svm_lock", obj, "svm-lock"); 7997 object_property_add_alias(obj, "nrip_save", obj, "nrip-save"); 7998 object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale"); 7999 object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean"); 8000 object_property_add_alias(obj, "pause_filter", obj, "pause-filter"); 8001 object_property_add_alias(obj, "sse4_1", obj, "sse4.1"); 8002 object_property_add_alias(obj, "sse4_2", obj, "sse4.2"); 8003 8004 object_property_add_alias(obj, "hv-apicv", obj, "hv-avic"); 8005 cpu->lbr_fmt = ~PERF_CAP_LBR_FMT; 8006 object_property_add_alias(obj, "lbr_fmt", obj, "lbr-fmt"); 8007 8008 if (xcc->model) { 8009 x86_cpu_load_model(cpu, xcc->model); 8010 } 8011 } 8012 8013 static int64_t x86_cpu_get_arch_id(CPUState *cs) 8014 { 8015 X86CPU *cpu = X86_CPU(cs); 8016 8017 return cpu->apic_id; 8018 } 8019 8020 #if !defined(CONFIG_USER_ONLY) 8021 static bool x86_cpu_get_paging_enabled(const CPUState *cs) 8022 { 8023 X86CPU *cpu = X86_CPU(cs); 8024 8025 return cpu->env.cr[0] & CR0_PG_MASK; 8026 } 8027 #endif /* !CONFIG_USER_ONLY */ 8028 8029 static void x86_cpu_set_pc(CPUState *cs, vaddr value) 8030 { 8031 X86CPU *cpu = X86_CPU(cs); 8032 8033 cpu->env.eip = value; 8034 } 8035 8036 static vaddr x86_cpu_get_pc(CPUState *cs) 8037 { 8038 X86CPU *cpu = X86_CPU(cs); 8039 8040 /* Match cpu_get_tb_cpu_state. */ 8041 return cpu->env.eip + cpu->env.segs[R_CS].base; 8042 } 8043 8044 int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request) 8045 { 8046 X86CPU *cpu = X86_CPU(cs); 8047 CPUX86State *env = &cpu->env; 8048 8049 #if !defined(CONFIG_USER_ONLY) 8050 if (interrupt_request & CPU_INTERRUPT_POLL) { 8051 return CPU_INTERRUPT_POLL; 8052 } 8053 #endif 8054 if (interrupt_request & CPU_INTERRUPT_SIPI) { 8055 return CPU_INTERRUPT_SIPI; 8056 } 8057 8058 if (env->hflags2 & HF2_GIF_MASK) { 8059 if ((interrupt_request & CPU_INTERRUPT_SMI) && 8060 !(env->hflags & HF_SMM_MASK)) { 8061 return CPU_INTERRUPT_SMI; 8062 } else if ((interrupt_request & CPU_INTERRUPT_NMI) && 8063 !(env->hflags2 & HF2_NMI_MASK)) { 8064 return CPU_INTERRUPT_NMI; 8065 } else if (interrupt_request & CPU_INTERRUPT_MCE) { 8066 return CPU_INTERRUPT_MCE; 8067 } else if ((interrupt_request & CPU_INTERRUPT_HARD) && 8068 (((env->hflags2 & HF2_VINTR_MASK) && 8069 (env->hflags2 & HF2_HIF_MASK)) || 8070 (!(env->hflags2 & HF2_VINTR_MASK) && 8071 (env->eflags & IF_MASK && 8072 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) { 8073 return CPU_INTERRUPT_HARD; 8074 #if !defined(CONFIG_USER_ONLY) 8075 } else if (env->hflags2 & HF2_VGIF_MASK) { 8076 if((interrupt_request & CPU_INTERRUPT_VIRQ) && 8077 (env->eflags & IF_MASK) && 8078 !(env->hflags & HF_INHIBIT_IRQ_MASK)) { 8079 return CPU_INTERRUPT_VIRQ; 8080 } 8081 #endif 8082 } 8083 } 8084 8085 return 0; 8086 } 8087 8088 static bool x86_cpu_has_work(CPUState *cs) 8089 { 8090 return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0; 8091 } 8092 8093 static int x86_cpu_mmu_index(CPUState *cs, bool ifetch) 8094 { 8095 CPUX86State *env = cpu_env(cs); 8096 int mmu_index_32 = (env->hflags & HF_CS64_MASK) ? 0 : 1; 8097 int mmu_index_base = 8098 (env->hflags & HF_CPL_MASK) == 3 ? MMU_USER64_IDX : 8099 !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP64_IDX : 8100 (env->eflags & AC_MASK) ? MMU_KNOSMAP64_IDX : MMU_KSMAP64_IDX; 8101 8102 return mmu_index_base + mmu_index_32; 8103 } 8104 8105 static void x86_disas_set_info(CPUState *cs, disassemble_info *info) 8106 { 8107 X86CPU *cpu = X86_CPU(cs); 8108 CPUX86State *env = &cpu->env; 8109 8110 info->mach = (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64 8111 : env->hflags & HF_CS32_MASK ? bfd_mach_i386_i386 8112 : bfd_mach_i386_i8086); 8113 8114 info->cap_arch = CS_ARCH_X86; 8115 info->cap_mode = (env->hflags & HF_CS64_MASK ? CS_MODE_64 8116 : env->hflags & HF_CS32_MASK ? CS_MODE_32 8117 : CS_MODE_16); 8118 info->cap_insn_unit = 1; 8119 info->cap_insn_split = 8; 8120 } 8121 8122 void x86_update_hflags(CPUX86State *env) 8123 { 8124 uint32_t hflags; 8125 #define HFLAG_COPY_MASK \ 8126 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \ 8127 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \ 8128 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \ 8129 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK) 8130 8131 hflags = env->hflags & HFLAG_COPY_MASK; 8132 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK; 8133 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT); 8134 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) & 8135 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK); 8136 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK)); 8137 8138 if (env->cr[4] & CR4_OSFXSR_MASK) { 8139 hflags |= HF_OSFXSR_MASK; 8140 } 8141 8142 if (env->efer & MSR_EFER_LMA) { 8143 hflags |= HF_LMA_MASK; 8144 } 8145 8146 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) { 8147 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; 8148 } else { 8149 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >> 8150 (DESC_B_SHIFT - HF_CS32_SHIFT); 8151 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >> 8152 (DESC_B_SHIFT - HF_SS32_SHIFT); 8153 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) || 8154 !(hflags & HF_CS32_MASK)) { 8155 hflags |= HF_ADDSEG_MASK; 8156 } else { 8157 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base | 8158 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT; 8159 } 8160 } 8161 env->hflags = hflags; 8162 } 8163 8164 static Property x86_cpu_properties[] = { 8165 #ifdef CONFIG_USER_ONLY 8166 /* apic_id = 0 by default for *-user, see commit 9886e834 */ 8167 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0), 8168 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0), 8169 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0), 8170 DEFINE_PROP_INT32("module-id", X86CPU, module_id, 0), 8171 DEFINE_PROP_INT32("die-id", X86CPU, die_id, 0), 8172 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0), 8173 #else 8174 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID), 8175 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1), 8176 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1), 8177 DEFINE_PROP_INT32("module-id", X86CPU, module_id, -1), 8178 DEFINE_PROP_INT32("die-id", X86CPU, die_id, -1), 8179 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1), 8180 #endif 8181 DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID), 8182 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false), 8183 DEFINE_PROP_UINT64_CHECKMASK("lbr-fmt", X86CPU, lbr_fmt, PERF_CAP_LBR_FMT), 8184 8185 DEFINE_PROP_UINT32("hv-spinlocks", X86CPU, hyperv_spinlock_attempts, 8186 HYPERV_SPINLOCK_NEVER_NOTIFY), 8187 DEFINE_PROP_BIT64("hv-relaxed", X86CPU, hyperv_features, 8188 HYPERV_FEAT_RELAXED, 0), 8189 DEFINE_PROP_BIT64("hv-vapic", X86CPU, hyperv_features, 8190 HYPERV_FEAT_VAPIC, 0), 8191 DEFINE_PROP_BIT64("hv-time", X86CPU, hyperv_features, 8192 HYPERV_FEAT_TIME, 0), 8193 DEFINE_PROP_BIT64("hv-crash", X86CPU, hyperv_features, 8194 HYPERV_FEAT_CRASH, 0), 8195 DEFINE_PROP_BIT64("hv-reset", X86CPU, hyperv_features, 8196 HYPERV_FEAT_RESET, 0), 8197 DEFINE_PROP_BIT64("hv-vpindex", X86CPU, hyperv_features, 8198 HYPERV_FEAT_VPINDEX, 0), 8199 DEFINE_PROP_BIT64("hv-runtime", X86CPU, hyperv_features, 8200 HYPERV_FEAT_RUNTIME, 0), 8201 DEFINE_PROP_BIT64("hv-synic", X86CPU, hyperv_features, 8202 HYPERV_FEAT_SYNIC, 0), 8203 DEFINE_PROP_BIT64("hv-stimer", X86CPU, hyperv_features, 8204 HYPERV_FEAT_STIMER, 0), 8205 DEFINE_PROP_BIT64("hv-frequencies", X86CPU, hyperv_features, 8206 HYPERV_FEAT_FREQUENCIES, 0), 8207 DEFINE_PROP_BIT64("hv-reenlightenment", X86CPU, hyperv_features, 8208 HYPERV_FEAT_REENLIGHTENMENT, 0), 8209 DEFINE_PROP_BIT64("hv-tlbflush", X86CPU, hyperv_features, 8210 HYPERV_FEAT_TLBFLUSH, 0), 8211 DEFINE_PROP_BIT64("hv-evmcs", X86CPU, hyperv_features, 8212 HYPERV_FEAT_EVMCS, 0), 8213 DEFINE_PROP_BIT64("hv-ipi", X86CPU, hyperv_features, 8214 HYPERV_FEAT_IPI, 0), 8215 DEFINE_PROP_BIT64("hv-stimer-direct", X86CPU, hyperv_features, 8216 HYPERV_FEAT_STIMER_DIRECT, 0), 8217 DEFINE_PROP_BIT64("hv-avic", X86CPU, hyperv_features, 8218 HYPERV_FEAT_AVIC, 0), 8219 DEFINE_PROP_BIT64("hv-emsr-bitmap", X86CPU, hyperv_features, 8220 HYPERV_FEAT_MSR_BITMAP, 0), 8221 DEFINE_PROP_BIT64("hv-xmm-input", X86CPU, hyperv_features, 8222 HYPERV_FEAT_XMM_INPUT, 0), 8223 DEFINE_PROP_BIT64("hv-tlbflush-ext", X86CPU, hyperv_features, 8224 HYPERV_FEAT_TLBFLUSH_EXT, 0), 8225 DEFINE_PROP_BIT64("hv-tlbflush-direct", X86CPU, hyperv_features, 8226 HYPERV_FEAT_TLBFLUSH_DIRECT, 0), 8227 DEFINE_PROP_ON_OFF_AUTO("hv-no-nonarch-coresharing", X86CPU, 8228 hyperv_no_nonarch_cs, ON_OFF_AUTO_OFF), 8229 DEFINE_PROP_BIT64("hv-syndbg", X86CPU, hyperv_features, 8230 HYPERV_FEAT_SYNDBG, 0), 8231 DEFINE_PROP_BOOL("hv-passthrough", X86CPU, hyperv_passthrough, false), 8232 DEFINE_PROP_BOOL("hv-enforce-cpuid", X86CPU, hyperv_enforce_cpuid, false), 8233 8234 /* WS2008R2 identify by default */ 8235 DEFINE_PROP_UINT32("hv-version-id-build", X86CPU, hyperv_ver_id_build, 8236 0x3839), 8237 DEFINE_PROP_UINT16("hv-version-id-major", X86CPU, hyperv_ver_id_major, 8238 0x000A), 8239 DEFINE_PROP_UINT16("hv-version-id-minor", X86CPU, hyperv_ver_id_minor, 8240 0x0000), 8241 DEFINE_PROP_UINT32("hv-version-id-spack", X86CPU, hyperv_ver_id_sp, 0), 8242 DEFINE_PROP_UINT8("hv-version-id-sbranch", X86CPU, hyperv_ver_id_sb, 0), 8243 DEFINE_PROP_UINT32("hv-version-id-snumber", X86CPU, hyperv_ver_id_sn, 0), 8244 8245 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true), 8246 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false), 8247 DEFINE_PROP_BOOL("x-force-features", X86CPU, force_features, false), 8248 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true), 8249 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0), 8250 DEFINE_PROP_UINT32("guest-phys-bits", X86CPU, guest_phys_bits, -1), 8251 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false), 8252 DEFINE_PROP_UINT8("host-phys-bits-limit", X86CPU, host_phys_bits_limit, 0), 8253 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true), 8254 DEFINE_PROP_UINT32("level-func7", X86CPU, env.cpuid_level_func7, 8255 UINT32_MAX), 8256 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX), 8257 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX), 8258 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX), 8259 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0), 8260 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0), 8261 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0), 8262 DEFINE_PROP_UINT64("ucode-rev", X86CPU, ucode_rev, 0), 8263 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true), 8264 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor), 8265 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true), 8266 DEFINE_PROP_BOOL("x-vendor-cpuid-only", X86CPU, vendor_cpuid_only, true), 8267 DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false), 8268 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true), 8269 DEFINE_PROP_BOOL("kvm-no-smi-migration", X86CPU, kvm_no_smi_migration, 8270 false), 8271 DEFINE_PROP_BOOL("kvm-pv-enforce-cpuid", X86CPU, kvm_pv_enforce_cpuid, 8272 false), 8273 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true), 8274 DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true), 8275 DEFINE_PROP_BOOL("x-migrate-smi-count", X86CPU, migrate_smi_count, 8276 true), 8277 /* 8278 * lecacy_cache defaults to true unless the CPU model provides its 8279 * own cache information (see x86_cpu_load_def()). 8280 */ 8281 DEFINE_PROP_BOOL("legacy-cache", X86CPU, legacy_cache, true), 8282 DEFINE_PROP_BOOL("legacy-multi-node", X86CPU, legacy_multi_node, false), 8283 DEFINE_PROP_BOOL("xen-vapic", X86CPU, xen_vapic, false), 8284 8285 /* 8286 * From "Requirements for Implementing the Microsoft 8287 * Hypervisor Interface": 8288 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs 8289 * 8290 * "Starting with Windows Server 2012 and Windows 8, if 8291 * CPUID.40000005.EAX contains a value of -1, Windows assumes that 8292 * the hypervisor imposes no specific limit to the number of VPs. 8293 * In this case, Windows Server 2012 guest VMs may use more than 8294 * 64 VPs, up to the maximum supported number of processors applicable 8295 * to the specific Windows version being used." 8296 */ 8297 DEFINE_PROP_INT32("x-hv-max-vps", X86CPU, hv_max_vps, -1), 8298 DEFINE_PROP_BOOL("x-hv-synic-kvm-only", X86CPU, hyperv_synic_kvm_only, 8299 false), 8300 DEFINE_PROP_BOOL("x-intel-pt-auto-level", X86CPU, intel_pt_auto_level, 8301 true), 8302 DEFINE_PROP_BOOL("x-l1-cache-per-thread", X86CPU, l1_cache_per_core, true), 8303 DEFINE_PROP_END_OF_LIST() 8304 }; 8305 8306 #ifndef CONFIG_USER_ONLY 8307 #include "hw/core/sysemu-cpu-ops.h" 8308 8309 static const struct SysemuCPUOps i386_sysemu_ops = { 8310 .get_memory_mapping = x86_cpu_get_memory_mapping, 8311 .get_paging_enabled = x86_cpu_get_paging_enabled, 8312 .get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug, 8313 .asidx_from_attrs = x86_asidx_from_attrs, 8314 .get_crash_info = x86_cpu_get_crash_info, 8315 .write_elf32_note = x86_cpu_write_elf32_note, 8316 .write_elf64_note = x86_cpu_write_elf64_note, 8317 .write_elf32_qemunote = x86_cpu_write_elf32_qemunote, 8318 .write_elf64_qemunote = x86_cpu_write_elf64_qemunote, 8319 .legacy_vmsd = &vmstate_x86_cpu, 8320 }; 8321 #endif 8322 8323 static void x86_cpu_common_class_init(ObjectClass *oc, void *data) 8324 { 8325 X86CPUClass *xcc = X86_CPU_CLASS(oc); 8326 CPUClass *cc = CPU_CLASS(oc); 8327 DeviceClass *dc = DEVICE_CLASS(oc); 8328 ResettableClass *rc = RESETTABLE_CLASS(oc); 8329 FeatureWord w; 8330 8331 device_class_set_parent_realize(dc, x86_cpu_realizefn, 8332 &xcc->parent_realize); 8333 device_class_set_parent_unrealize(dc, x86_cpu_unrealizefn, 8334 &xcc->parent_unrealize); 8335 device_class_set_props(dc, x86_cpu_properties); 8336 8337 resettable_class_set_parent_phases(rc, NULL, x86_cpu_reset_hold, NULL, 8338 &xcc->parent_phases); 8339 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP; 8340 8341 cc->class_by_name = x86_cpu_class_by_name; 8342 cc->parse_features = x86_cpu_parse_featurestr; 8343 cc->has_work = x86_cpu_has_work; 8344 cc->mmu_index = x86_cpu_mmu_index; 8345 cc->dump_state = x86_cpu_dump_state; 8346 cc->set_pc = x86_cpu_set_pc; 8347 cc->get_pc = x86_cpu_get_pc; 8348 cc->gdb_read_register = x86_cpu_gdb_read_register; 8349 cc->gdb_write_register = x86_cpu_gdb_write_register; 8350 cc->get_arch_id = x86_cpu_get_arch_id; 8351 8352 #ifndef CONFIG_USER_ONLY 8353 cc->sysemu_ops = &i386_sysemu_ops; 8354 #endif /* !CONFIG_USER_ONLY */ 8355 8356 cc->gdb_arch_name = x86_gdb_arch_name; 8357 #ifdef TARGET_X86_64 8358 cc->gdb_core_xml_file = "i386-64bit.xml"; 8359 #else 8360 cc->gdb_core_xml_file = "i386-32bit.xml"; 8361 #endif 8362 cc->disas_set_info = x86_disas_set_info; 8363 8364 dc->user_creatable = true; 8365 8366 object_class_property_add(oc, "family", "int", 8367 x86_cpuid_version_get_family, 8368 x86_cpuid_version_set_family, NULL, NULL); 8369 object_class_property_add(oc, "model", "int", 8370 x86_cpuid_version_get_model, 8371 x86_cpuid_version_set_model, NULL, NULL); 8372 object_class_property_add(oc, "stepping", "int", 8373 x86_cpuid_version_get_stepping, 8374 x86_cpuid_version_set_stepping, NULL, NULL); 8375 object_class_property_add_str(oc, "vendor", 8376 x86_cpuid_get_vendor, 8377 x86_cpuid_set_vendor); 8378 object_class_property_add_str(oc, "model-id", 8379 x86_cpuid_get_model_id, 8380 x86_cpuid_set_model_id); 8381 object_class_property_add(oc, "tsc-frequency", "int", 8382 x86_cpuid_get_tsc_freq, 8383 x86_cpuid_set_tsc_freq, NULL, NULL); 8384 /* 8385 * The "unavailable-features" property has the same semantics as 8386 * CpuDefinitionInfo.unavailable-features on the "query-cpu-definitions" 8387 * QMP command: they list the features that would have prevented the 8388 * CPU from running if the "enforce" flag was set. 8389 */ 8390 object_class_property_add(oc, "unavailable-features", "strList", 8391 x86_cpu_get_unavailable_features, 8392 NULL, NULL, NULL); 8393 8394 #if !defined(CONFIG_USER_ONLY) 8395 object_class_property_add(oc, "crash-information", "GuestPanicInformation", 8396 x86_cpu_get_crash_info_qom, NULL, NULL, NULL); 8397 #endif 8398 8399 for (w = 0; w < FEATURE_WORDS; w++) { 8400 int bitnr; 8401 for (bitnr = 0; bitnr < 64; bitnr++) { 8402 x86_cpu_register_feature_bit_props(xcc, w, bitnr); 8403 } 8404 } 8405 } 8406 8407 static const TypeInfo x86_cpu_type_info = { 8408 .name = TYPE_X86_CPU, 8409 .parent = TYPE_CPU, 8410 .instance_size = sizeof(X86CPU), 8411 .instance_align = __alignof(X86CPU), 8412 .instance_init = x86_cpu_initfn, 8413 .instance_post_init = x86_cpu_post_initfn, 8414 8415 .abstract = true, 8416 .class_size = sizeof(X86CPUClass), 8417 .class_init = x86_cpu_common_class_init, 8418 }; 8419 8420 /* "base" CPU model, used by query-cpu-model-expansion */ 8421 static void x86_cpu_base_class_init(ObjectClass *oc, void *data) 8422 { 8423 X86CPUClass *xcc = X86_CPU_CLASS(oc); 8424 8425 xcc->static_model = true; 8426 xcc->migration_safe = true; 8427 xcc->model_description = "base CPU model type with no features enabled"; 8428 xcc->ordering = 8; 8429 } 8430 8431 static const TypeInfo x86_base_cpu_type_info = { 8432 .name = X86_CPU_TYPE_NAME("base"), 8433 .parent = TYPE_X86_CPU, 8434 .class_init = x86_cpu_base_class_init, 8435 }; 8436 8437 static void x86_cpu_register_types(void) 8438 { 8439 int i; 8440 8441 type_register_static(&x86_cpu_type_info); 8442 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) { 8443 x86_register_cpudef_types(&builtin_x86_defs[i]); 8444 } 8445 type_register_static(&max_x86_cpu_type_info); 8446 type_register_static(&x86_base_cpu_type_info); 8447 } 8448 8449 type_init(x86_cpu_register_types) 8450