1 /* 2 * i386 CPUID, CPU class, definitions, models 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/units.h" 22 #include "qemu/cutils.h" 23 #include "qemu/qemu-print.h" 24 #include "qemu/hw-version.h" 25 #include "cpu.h" 26 #include "tcg/helper-tcg.h" 27 #include "exec/translation-block.h" 28 #include "system/hvf.h" 29 #include "hvf/hvf-i386.h" 30 #include "kvm/kvm_i386.h" 31 #include "sev.h" 32 #include "qapi/error.h" 33 #include "qemu/error-report.h" 34 #include "qapi/qapi-visit-machine.h" 35 #include "standard-headers/asm-x86/kvm_para.h" 36 #include "hw/qdev-properties.h" 37 #include "hw/i386/topology.h" 38 #include "exec/watchpoint.h" 39 #ifndef CONFIG_USER_ONLY 40 #include "confidential-guest.h" 41 #include "system/reset.h" 42 #include "qapi/qapi-commands-machine.h" 43 #include "system/address-spaces.h" 44 #include "hw/boards.h" 45 #include "hw/i386/sgx-epc.h" 46 #endif 47 #include "system/qtest.h" 48 #include "tcg/tcg-cpu.h" 49 50 #include "disas/capstone.h" 51 #include "cpu-internal.h" 52 53 static void x86_cpu_realizefn(DeviceState *dev, Error **errp); 54 static void x86_cpu_get_supported_cpuid(uint32_t func, uint32_t index, 55 uint32_t *eax, uint32_t *ebx, 56 uint32_t *ecx, uint32_t *edx); 57 58 /* Helpers for building CPUID[2] descriptors: */ 59 60 struct CPUID2CacheDescriptorInfo { 61 enum CacheType type; 62 int level; 63 int size; 64 int line_size; 65 int associativity; 66 }; 67 68 /* 69 * Known CPUID 2 cache descriptors. 70 * From Intel SDM Volume 2A, CPUID instruction 71 */ 72 struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = { 73 [0x06] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 8 * KiB, 74 .associativity = 4, .line_size = 32, }, 75 [0x08] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 16 * KiB, 76 .associativity = 4, .line_size = 32, }, 77 [0x09] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB, 78 .associativity = 4, .line_size = 64, }, 79 [0x0A] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB, 80 .associativity = 2, .line_size = 32, }, 81 [0x0C] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 82 .associativity = 4, .line_size = 32, }, 83 [0x0D] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 84 .associativity = 4, .line_size = 64, }, 85 [0x0E] = { .level = 1, .type = DATA_CACHE, .size = 24 * KiB, 86 .associativity = 6, .line_size = 64, }, 87 [0x1D] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB, 88 .associativity = 2, .line_size = 64, }, 89 [0x21] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 90 .associativity = 8, .line_size = 64, }, 91 /* lines per sector is not supported cpuid2_cache_descriptor(), 92 * so descriptors 0x22, 0x23 are not included 93 */ 94 [0x24] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 95 .associativity = 16, .line_size = 64, }, 96 /* lines per sector is not supported cpuid2_cache_descriptor(), 97 * so descriptors 0x25, 0x20 are not included 98 */ 99 [0x2C] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB, 100 .associativity = 8, .line_size = 64, }, 101 [0x30] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB, 102 .associativity = 8, .line_size = 64, }, 103 [0x41] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB, 104 .associativity = 4, .line_size = 32, }, 105 [0x42] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 106 .associativity = 4, .line_size = 32, }, 107 [0x43] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 108 .associativity = 4, .line_size = 32, }, 109 [0x44] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 110 .associativity = 4, .line_size = 32, }, 111 [0x45] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 112 .associativity = 4, .line_size = 32, }, 113 [0x46] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 114 .associativity = 4, .line_size = 64, }, 115 [0x47] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 116 .associativity = 8, .line_size = 64, }, 117 [0x48] = { .level = 2, .type = UNIFIED_CACHE, .size = 3 * MiB, 118 .associativity = 12, .line_size = 64, }, 119 /* Descriptor 0x49 depends on CPU family/model, so it is not included */ 120 [0x4A] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB, 121 .associativity = 12, .line_size = 64, }, 122 [0x4B] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 123 .associativity = 16, .line_size = 64, }, 124 [0x4C] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB, 125 .associativity = 12, .line_size = 64, }, 126 [0x4D] = { .level = 3, .type = UNIFIED_CACHE, .size = 16 * MiB, 127 .associativity = 16, .line_size = 64, }, 128 [0x4E] = { .level = 2, .type = UNIFIED_CACHE, .size = 6 * MiB, 129 .associativity = 24, .line_size = 64, }, 130 [0x60] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 131 .associativity = 8, .line_size = 64, }, 132 [0x66] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB, 133 .associativity = 4, .line_size = 64, }, 134 [0x67] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 135 .associativity = 4, .line_size = 64, }, 136 [0x68] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB, 137 .associativity = 4, .line_size = 64, }, 138 [0x78] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 139 .associativity = 4, .line_size = 64, }, 140 /* lines per sector is not supported cpuid2_cache_descriptor(), 141 * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included. 142 */ 143 [0x7D] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 144 .associativity = 8, .line_size = 64, }, 145 [0x7F] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 146 .associativity = 2, .line_size = 64, }, 147 [0x80] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 148 .associativity = 8, .line_size = 64, }, 149 [0x82] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 150 .associativity = 8, .line_size = 32, }, 151 [0x83] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 152 .associativity = 8, .line_size = 32, }, 153 [0x84] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 154 .associativity = 8, .line_size = 32, }, 155 [0x85] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 156 .associativity = 8, .line_size = 32, }, 157 [0x86] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 158 .associativity = 4, .line_size = 64, }, 159 [0x87] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 160 .associativity = 8, .line_size = 64, }, 161 [0xD0] = { .level = 3, .type = UNIFIED_CACHE, .size = 512 * KiB, 162 .associativity = 4, .line_size = 64, }, 163 [0xD1] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB, 164 .associativity = 4, .line_size = 64, }, 165 [0xD2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 166 .associativity = 4, .line_size = 64, }, 167 [0xD6] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB, 168 .associativity = 8, .line_size = 64, }, 169 [0xD7] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 170 .associativity = 8, .line_size = 64, }, 171 [0xD8] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 172 .associativity = 8, .line_size = 64, }, 173 [0xDC] = { .level = 3, .type = UNIFIED_CACHE, .size = 1.5 * MiB, 174 .associativity = 12, .line_size = 64, }, 175 [0xDD] = { .level = 3, .type = UNIFIED_CACHE, .size = 3 * MiB, 176 .associativity = 12, .line_size = 64, }, 177 [0xDE] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB, 178 .associativity = 12, .line_size = 64, }, 179 [0xE2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 180 .associativity = 16, .line_size = 64, }, 181 [0xE3] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 182 .associativity = 16, .line_size = 64, }, 183 [0xE4] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 184 .associativity = 16, .line_size = 64, }, 185 [0xEA] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB, 186 .associativity = 24, .line_size = 64, }, 187 [0xEB] = { .level = 3, .type = UNIFIED_CACHE, .size = 18 * MiB, 188 .associativity = 24, .line_size = 64, }, 189 [0xEC] = { .level = 3, .type = UNIFIED_CACHE, .size = 24 * MiB, 190 .associativity = 24, .line_size = 64, }, 191 }; 192 193 /* 194 * "CPUID leaf 2 does not report cache descriptor information, 195 * use CPUID leaf 4 to query cache parameters" 196 */ 197 #define CACHE_DESCRIPTOR_UNAVAILABLE 0xFF 198 199 /* 200 * Return a CPUID 2 cache descriptor for a given cache. 201 * If no known descriptor is found, return CACHE_DESCRIPTOR_UNAVAILABLE 202 */ 203 static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache) 204 { 205 int i; 206 207 assert(cache->size > 0); 208 assert(cache->level > 0); 209 assert(cache->line_size > 0); 210 assert(cache->associativity > 0); 211 for (i = 0; i < ARRAY_SIZE(cpuid2_cache_descriptors); i++) { 212 struct CPUID2CacheDescriptorInfo *d = &cpuid2_cache_descriptors[i]; 213 if (d->level == cache->level && d->type == cache->type && 214 d->size == cache->size && d->line_size == cache->line_size && 215 d->associativity == cache->associativity) { 216 return i; 217 } 218 } 219 220 return CACHE_DESCRIPTOR_UNAVAILABLE; 221 } 222 223 /* CPUID Leaf 4 constants: */ 224 225 /* EAX: */ 226 #define CACHE_TYPE_D 1 227 #define CACHE_TYPE_I 2 228 #define CACHE_TYPE_UNIFIED 3 229 230 #define CACHE_LEVEL(l) (l << 5) 231 232 #define CACHE_SELF_INIT_LEVEL (1 << 8) 233 234 /* EDX: */ 235 #define CACHE_NO_INVD_SHARING (1 << 0) 236 #define CACHE_INCLUSIVE (1 << 1) 237 #define CACHE_COMPLEX_IDX (1 << 2) 238 239 /* Encode CacheType for CPUID[4].EAX */ 240 #define CACHE_TYPE(t) (((t) == DATA_CACHE) ? CACHE_TYPE_D : \ 241 ((t) == INSTRUCTION_CACHE) ? CACHE_TYPE_I : \ 242 ((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \ 243 0 /* Invalid value */) 244 245 static uint32_t max_thread_ids_for_cache(X86CPUTopoInfo *topo_info, 246 enum CpuTopologyLevel share_level) 247 { 248 uint32_t num_ids = 0; 249 250 switch (share_level) { 251 case CPU_TOPOLOGY_LEVEL_CORE: 252 num_ids = 1 << apicid_core_offset(topo_info); 253 break; 254 case CPU_TOPOLOGY_LEVEL_MODULE: 255 num_ids = 1 << apicid_module_offset(topo_info); 256 break; 257 case CPU_TOPOLOGY_LEVEL_DIE: 258 num_ids = 1 << apicid_die_offset(topo_info); 259 break; 260 case CPU_TOPOLOGY_LEVEL_SOCKET: 261 num_ids = 1 << apicid_pkg_offset(topo_info); 262 break; 263 default: 264 /* 265 * Currently there is no use case for THREAD, so use 266 * assert directly to facilitate debugging. 267 */ 268 g_assert_not_reached(); 269 } 270 271 return num_ids - 1; 272 } 273 274 static uint32_t max_core_ids_in_package(X86CPUTopoInfo *topo_info) 275 { 276 uint32_t num_cores = 1 << (apicid_pkg_offset(topo_info) - 277 apicid_core_offset(topo_info)); 278 return num_cores - 1; 279 } 280 281 /* Encode cache info for CPUID[4] */ 282 static void encode_cache_cpuid4(CPUCacheInfo *cache, 283 X86CPUTopoInfo *topo_info, 284 uint32_t *eax, uint32_t *ebx, 285 uint32_t *ecx, uint32_t *edx) 286 { 287 assert(cache->size == cache->line_size * cache->associativity * 288 cache->partitions * cache->sets); 289 290 *eax = CACHE_TYPE(cache->type) | 291 CACHE_LEVEL(cache->level) | 292 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) | 293 (max_core_ids_in_package(topo_info) << 26) | 294 (max_thread_ids_for_cache(topo_info, cache->share_level) << 14); 295 296 assert(cache->line_size > 0); 297 assert(cache->partitions > 0); 298 assert(cache->associativity > 0); 299 /* We don't implement fully-associative caches */ 300 assert(cache->associativity < cache->sets); 301 *ebx = (cache->line_size - 1) | 302 ((cache->partitions - 1) << 12) | 303 ((cache->associativity - 1) << 22); 304 305 assert(cache->sets > 0); 306 *ecx = cache->sets - 1; 307 308 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) | 309 (cache->inclusive ? CACHE_INCLUSIVE : 0) | 310 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); 311 } 312 313 static uint32_t num_threads_by_topo_level(X86CPUTopoInfo *topo_info, 314 enum CpuTopologyLevel topo_level) 315 { 316 switch (topo_level) { 317 case CPU_TOPOLOGY_LEVEL_THREAD: 318 return 1; 319 case CPU_TOPOLOGY_LEVEL_CORE: 320 return topo_info->threads_per_core; 321 case CPU_TOPOLOGY_LEVEL_MODULE: 322 return x86_threads_per_module(topo_info); 323 case CPU_TOPOLOGY_LEVEL_DIE: 324 return x86_threads_per_die(topo_info); 325 case CPU_TOPOLOGY_LEVEL_SOCKET: 326 return x86_threads_per_pkg(topo_info); 327 default: 328 g_assert_not_reached(); 329 } 330 return 0; 331 } 332 333 static uint32_t apicid_offset_by_topo_level(X86CPUTopoInfo *topo_info, 334 enum CpuTopologyLevel topo_level) 335 { 336 switch (topo_level) { 337 case CPU_TOPOLOGY_LEVEL_THREAD: 338 return 0; 339 case CPU_TOPOLOGY_LEVEL_CORE: 340 return apicid_core_offset(topo_info); 341 case CPU_TOPOLOGY_LEVEL_MODULE: 342 return apicid_module_offset(topo_info); 343 case CPU_TOPOLOGY_LEVEL_DIE: 344 return apicid_die_offset(topo_info); 345 case CPU_TOPOLOGY_LEVEL_SOCKET: 346 return apicid_pkg_offset(topo_info); 347 default: 348 g_assert_not_reached(); 349 } 350 return 0; 351 } 352 353 static uint32_t cpuid1f_topo_type(enum CpuTopologyLevel topo_level) 354 { 355 switch (topo_level) { 356 case CPU_TOPOLOGY_LEVEL_INVALID: 357 return CPUID_1F_ECX_TOPO_LEVEL_INVALID; 358 case CPU_TOPOLOGY_LEVEL_THREAD: 359 return CPUID_1F_ECX_TOPO_LEVEL_SMT; 360 case CPU_TOPOLOGY_LEVEL_CORE: 361 return CPUID_1F_ECX_TOPO_LEVEL_CORE; 362 case CPU_TOPOLOGY_LEVEL_MODULE: 363 return CPUID_1F_ECX_TOPO_LEVEL_MODULE; 364 case CPU_TOPOLOGY_LEVEL_DIE: 365 return CPUID_1F_ECX_TOPO_LEVEL_DIE; 366 default: 367 /* Other types are not supported in QEMU. */ 368 g_assert_not_reached(); 369 } 370 return 0; 371 } 372 373 static void encode_topo_cpuid1f(CPUX86State *env, uint32_t count, 374 X86CPUTopoInfo *topo_info, 375 uint32_t *eax, uint32_t *ebx, 376 uint32_t *ecx, uint32_t *edx) 377 { 378 X86CPU *cpu = env_archcpu(env); 379 unsigned long level, base_level, next_level; 380 uint32_t num_threads_next_level, offset_next_level; 381 382 assert(count <= CPU_TOPOLOGY_LEVEL_SOCKET); 383 384 /* 385 * Find the No.(count + 1) topology level in avail_cpu_topo bitmap. 386 * The search starts from bit 0 (CPU_TOPOLOGY_LEVEL_THREAD). 387 */ 388 level = CPU_TOPOLOGY_LEVEL_THREAD; 389 base_level = level; 390 for (int i = 0; i <= count; i++) { 391 level = find_next_bit(env->avail_cpu_topo, 392 CPU_TOPOLOGY_LEVEL_SOCKET, 393 base_level); 394 395 /* 396 * CPUID[0x1f] doesn't explicitly encode the package level, 397 * and it just encodes the invalid level (all fields are 0) 398 * into the last subleaf of 0x1f. 399 */ 400 if (level == CPU_TOPOLOGY_LEVEL_SOCKET) { 401 level = CPU_TOPOLOGY_LEVEL_INVALID; 402 break; 403 } 404 /* Search the next level. */ 405 base_level = level + 1; 406 } 407 408 if (level == CPU_TOPOLOGY_LEVEL_INVALID) { 409 num_threads_next_level = 0; 410 offset_next_level = 0; 411 } else { 412 next_level = find_next_bit(env->avail_cpu_topo, 413 CPU_TOPOLOGY_LEVEL_SOCKET, 414 level + 1); 415 num_threads_next_level = num_threads_by_topo_level(topo_info, 416 next_level); 417 offset_next_level = apicid_offset_by_topo_level(topo_info, 418 next_level); 419 } 420 421 *eax = offset_next_level; 422 /* The count (bits 15-00) doesn't need to be reliable. */ 423 *ebx = num_threads_next_level & 0xffff; 424 *ecx = (count & 0xff) | (cpuid1f_topo_type(level) << 8); 425 *edx = cpu->apic_id; 426 427 assert(!(*eax & ~0x1f)); 428 } 429 430 /* Encode cache info for CPUID[0x80000005].ECX or CPUID[0x80000005].EDX */ 431 static uint32_t encode_cache_cpuid80000005(CPUCacheInfo *cache) 432 { 433 assert(cache->size % 1024 == 0); 434 assert(cache->lines_per_tag > 0); 435 assert(cache->associativity > 0); 436 assert(cache->line_size > 0); 437 return ((cache->size / 1024) << 24) | (cache->associativity << 16) | 438 (cache->lines_per_tag << 8) | (cache->line_size); 439 } 440 441 #define ASSOC_FULL 0xFF 442 443 /* AMD associativity encoding used on CPUID Leaf 0x80000006: */ 444 #define AMD_ENC_ASSOC(a) (a <= 1 ? a : \ 445 a == 2 ? 0x2 : \ 446 a == 4 ? 0x4 : \ 447 a == 8 ? 0x6 : \ 448 a == 16 ? 0x8 : \ 449 a == 32 ? 0xA : \ 450 a == 48 ? 0xB : \ 451 a == 64 ? 0xC : \ 452 a == 96 ? 0xD : \ 453 a == 128 ? 0xE : \ 454 a == ASSOC_FULL ? 0xF : \ 455 0 /* invalid value */) 456 457 /* 458 * Encode cache info for CPUID[0x80000006].ECX and CPUID[0x80000006].EDX 459 * @l3 can be NULL. 460 */ 461 static void encode_cache_cpuid80000006(CPUCacheInfo *l2, 462 CPUCacheInfo *l3, 463 uint32_t *ecx, uint32_t *edx) 464 { 465 assert(l2->size % 1024 == 0); 466 assert(l2->associativity > 0); 467 assert(l2->lines_per_tag > 0); 468 assert(l2->line_size > 0); 469 *ecx = ((l2->size / 1024) << 16) | 470 (AMD_ENC_ASSOC(l2->associativity) << 12) | 471 (l2->lines_per_tag << 8) | (l2->line_size); 472 473 if (l3) { 474 assert(l3->size % (512 * 1024) == 0); 475 assert(l3->associativity > 0); 476 assert(l3->lines_per_tag > 0); 477 assert(l3->line_size > 0); 478 *edx = ((l3->size / (512 * 1024)) << 18) | 479 (AMD_ENC_ASSOC(l3->associativity) << 12) | 480 (l3->lines_per_tag << 8) | (l3->line_size); 481 } else { 482 *edx = 0; 483 } 484 } 485 486 /* Encode cache info for CPUID[8000001D] */ 487 static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, 488 X86CPUTopoInfo *topo_info, 489 uint32_t *eax, uint32_t *ebx, 490 uint32_t *ecx, uint32_t *edx) 491 { 492 assert(cache->size == cache->line_size * cache->associativity * 493 cache->partitions * cache->sets); 494 495 *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) | 496 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0); 497 *eax |= max_thread_ids_for_cache(topo_info, cache->share_level) << 14; 498 499 assert(cache->line_size > 0); 500 assert(cache->partitions > 0); 501 assert(cache->associativity > 0); 502 /* We don't implement fully-associative caches */ 503 assert(cache->associativity < cache->sets); 504 *ebx = (cache->line_size - 1) | 505 ((cache->partitions - 1) << 12) | 506 ((cache->associativity - 1) << 22); 507 508 assert(cache->sets > 0); 509 *ecx = cache->sets - 1; 510 511 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) | 512 (cache->inclusive ? CACHE_INCLUSIVE : 0) | 513 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); 514 } 515 516 /* Encode cache info for CPUID[8000001E] */ 517 static void encode_topo_cpuid8000001e(X86CPU *cpu, X86CPUTopoInfo *topo_info, 518 uint32_t *eax, uint32_t *ebx, 519 uint32_t *ecx, uint32_t *edx) 520 { 521 X86CPUTopoIDs topo_ids; 522 523 x86_topo_ids_from_apicid(cpu->apic_id, topo_info, &topo_ids); 524 525 *eax = cpu->apic_id; 526 527 /* 528 * CPUID_Fn8000001E_EBX [Core Identifiers] (CoreId) 529 * Read-only. Reset: 0000_XXXXh. 530 * See Core::X86::Cpuid::ExtApicId. 531 * Core::X86::Cpuid::CoreId_lthree[1:0]_core[3:0]_thread[1:0]; 532 * Bits Description 533 * 31:16 Reserved. 534 * 15:8 ThreadsPerCore: threads per core. Read-only. Reset: XXh. 535 * The number of threads per core is ThreadsPerCore+1. 536 * 7:0 CoreId: core ID. Read-only. Reset: XXh. 537 * 538 * NOTE: CoreId is already part of apic_id. Just use it. We can 539 * use all the 8 bits to represent the core_id here. 540 */ 541 *ebx = ((topo_info->threads_per_core - 1) << 8) | (topo_ids.core_id & 0xFF); 542 543 /* 544 * CPUID_Fn8000001E_ECX [Node Identifiers] (NodeId) 545 * Read-only. Reset: 0000_0XXXh. 546 * Core::X86::Cpuid::NodeId_lthree[1:0]_core[3:0]_thread[1:0]; 547 * Bits Description 548 * 31:11 Reserved. 549 * 10:8 NodesPerProcessor: Node per processor. Read-only. Reset: XXXb. 550 * ValidValues: 551 * Value Description 552 * 0h 1 node per processor. 553 * 7h-1h Reserved. 554 * 7:0 NodeId: Node ID. Read-only. Reset: XXh. 555 * 556 * NOTE: Hardware reserves 3 bits for number of nodes per processor. 557 * But users can create more nodes than the actual hardware can 558 * support. To genaralize we can use all the upper 8 bits for nodes. 559 * NodeId is combination of node and socket_id which is already decoded 560 * in apic_id. Just use it by shifting. 561 */ 562 if (cpu->legacy_multi_node) { 563 *ecx = ((topo_info->dies_per_pkg - 1) << 8) | 564 ((cpu->apic_id >> apicid_die_offset(topo_info)) & 0xFF); 565 } else { 566 *ecx = (cpu->apic_id >> apicid_pkg_offset(topo_info)) & 0xFF; 567 } 568 569 *edx = 0; 570 } 571 572 /* 573 * Definitions of the hardcoded cache entries we expose: 574 * These are legacy cache values. If there is a need to change any 575 * of these values please use builtin_x86_defs 576 */ 577 578 /* L1 data cache: */ 579 static CPUCacheInfo legacy_l1d_cache = { 580 .type = DATA_CACHE, 581 .level = 1, 582 .size = 32 * KiB, 583 .self_init = 1, 584 .line_size = 64, 585 .associativity = 8, 586 .sets = 64, 587 .partitions = 1, 588 .no_invd_sharing = true, 589 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 590 }; 591 592 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ 593 static CPUCacheInfo legacy_l1d_cache_amd = { 594 .type = DATA_CACHE, 595 .level = 1, 596 .size = 64 * KiB, 597 .self_init = 1, 598 .line_size = 64, 599 .associativity = 2, 600 .sets = 512, 601 .partitions = 1, 602 .lines_per_tag = 1, 603 .no_invd_sharing = true, 604 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 605 }; 606 607 /* L1 instruction cache: */ 608 static CPUCacheInfo legacy_l1i_cache = { 609 .type = INSTRUCTION_CACHE, 610 .level = 1, 611 .size = 32 * KiB, 612 .self_init = 1, 613 .line_size = 64, 614 .associativity = 8, 615 .sets = 64, 616 .partitions = 1, 617 .no_invd_sharing = true, 618 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 619 }; 620 621 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ 622 static CPUCacheInfo legacy_l1i_cache_amd = { 623 .type = INSTRUCTION_CACHE, 624 .level = 1, 625 .size = 64 * KiB, 626 .self_init = 1, 627 .line_size = 64, 628 .associativity = 2, 629 .sets = 512, 630 .partitions = 1, 631 .lines_per_tag = 1, 632 .no_invd_sharing = true, 633 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 634 }; 635 636 /* Level 2 unified cache: */ 637 static CPUCacheInfo legacy_l2_cache = { 638 .type = UNIFIED_CACHE, 639 .level = 2, 640 .size = 4 * MiB, 641 .self_init = 1, 642 .line_size = 64, 643 .associativity = 16, 644 .sets = 4096, 645 .partitions = 1, 646 .no_invd_sharing = true, 647 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 648 }; 649 650 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */ 651 static CPUCacheInfo legacy_l2_cache_cpuid2 = { 652 .type = UNIFIED_CACHE, 653 .level = 2, 654 .size = 2 * MiB, 655 .line_size = 64, 656 .associativity = 8, 657 .share_level = CPU_TOPOLOGY_LEVEL_INVALID, 658 }; 659 660 661 /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */ 662 static CPUCacheInfo legacy_l2_cache_amd = { 663 .type = UNIFIED_CACHE, 664 .level = 2, 665 .size = 512 * KiB, 666 .line_size = 64, 667 .lines_per_tag = 1, 668 .associativity = 16, 669 .sets = 512, 670 .partitions = 1, 671 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 672 }; 673 674 /* Level 3 unified cache: */ 675 static CPUCacheInfo legacy_l3_cache = { 676 .type = UNIFIED_CACHE, 677 .level = 3, 678 .size = 16 * MiB, 679 .line_size = 64, 680 .associativity = 16, 681 .sets = 16384, 682 .partitions = 1, 683 .lines_per_tag = 1, 684 .self_init = true, 685 .inclusive = true, 686 .complex_indexing = true, 687 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 688 }; 689 690 /* TLB definitions: */ 691 692 #define L1_DTLB_2M_ASSOC 1 693 #define L1_DTLB_2M_ENTRIES 255 694 #define L1_DTLB_4K_ASSOC 1 695 #define L1_DTLB_4K_ENTRIES 255 696 697 #define L1_ITLB_2M_ASSOC 1 698 #define L1_ITLB_2M_ENTRIES 255 699 #define L1_ITLB_4K_ASSOC 1 700 #define L1_ITLB_4K_ENTRIES 255 701 702 #define L2_DTLB_2M_ASSOC 0 /* disabled */ 703 #define L2_DTLB_2M_ENTRIES 0 /* disabled */ 704 #define L2_DTLB_4K_ASSOC 4 705 #define L2_DTLB_4K_ENTRIES 512 706 707 #define L2_ITLB_2M_ASSOC 0 /* disabled */ 708 #define L2_ITLB_2M_ENTRIES 0 /* disabled */ 709 #define L2_ITLB_4K_ASSOC 4 710 #define L2_ITLB_4K_ENTRIES 512 711 712 /* CPUID Leaf 0x14 constants: */ 713 #define INTEL_PT_MAX_SUBLEAF 0x1 714 /* 715 * bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MATCH 716 * MSR can be accessed; 717 * bit[01]: Support Configurable PSB and Cycle-Accurate Mode; 718 * bit[02]: Support IP Filtering, TraceStop filtering, and preservation 719 * of Intel PT MSRs across warm reset; 720 * bit[03]: Support MTC timing packet and suppression of COFI-based packets; 721 */ 722 #define INTEL_PT_MINIMAL_EBX 0xf 723 /* 724 * bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 and 725 * IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be 726 * accessed; 727 * bit[01]: ToPA tables can hold any number of output entries, up to the 728 * maximum allowed by the MaskOrTableOffset field of 729 * IA32_RTIT_OUTPUT_MASK_PTRS; 730 * bit[02]: Support Single-Range Output scheme; 731 */ 732 #define INTEL_PT_MINIMAL_ECX 0x7 733 /* generated packets which contain IP payloads have LIP values */ 734 #define INTEL_PT_IP_LIP (1 << 31) 735 #define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */ 736 #define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3 737 #define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */ 738 #define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */ 739 #define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */ 740 741 /* CPUID Leaf 0x1D constants: */ 742 #define INTEL_AMX_TILE_MAX_SUBLEAF 0x1 743 #define INTEL_AMX_TOTAL_TILE_BYTES 0x2000 744 #define INTEL_AMX_BYTES_PER_TILE 0x400 745 #define INTEL_AMX_BYTES_PER_ROW 0x40 746 #define INTEL_AMX_TILE_MAX_NAMES 0x8 747 #define INTEL_AMX_TILE_MAX_ROWS 0x10 748 749 /* CPUID Leaf 0x1E constants: */ 750 #define INTEL_AMX_TMUL_MAX_K 0x10 751 #define INTEL_AMX_TMUL_MAX_N 0x40 752 753 void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1, 754 uint32_t vendor2, uint32_t vendor3) 755 { 756 int i; 757 for (i = 0; i < 4; i++) { 758 dst[i] = vendor1 >> (8 * i); 759 dst[i + 4] = vendor2 >> (8 * i); 760 dst[i + 8] = vendor3 >> (8 * i); 761 } 762 dst[CPUID_VENDOR_SZ] = '\0'; 763 } 764 765 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE) 766 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \ 767 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC) 768 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \ 769 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ 770 CPUID_PSE36 | CPUID_FXSR) 771 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE) 772 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \ 773 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \ 774 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \ 775 CPUID_PAE | CPUID_SEP | CPUID_APIC) 776 777 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \ 778 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \ 779 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ 780 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \ 781 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE | \ 782 CPUID_HT) 783 /* partly implemented: 784 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */ 785 /* missing: 786 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_TM, CPUID_PBE */ 787 788 /* 789 * Kernel-only features that can be shown to usermode programs even if 790 * they aren't actually supported by TCG, because qemu-user only runs 791 * in CPL=3; remove them if they are ever implemented for system emulation. 792 */ 793 #if defined CONFIG_USER_ONLY 794 #define CPUID_EXT_KERNEL_FEATURES \ 795 (CPUID_EXT_PCID | CPUID_EXT_TSC_DEADLINE_TIMER) 796 #else 797 #define CPUID_EXT_KERNEL_FEATURES 0 798 #endif 799 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \ 800 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \ 801 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \ 802 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \ 803 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR | \ 804 CPUID_EXT_RDRAND | CPUID_EXT_AVX | CPUID_EXT_F16C | \ 805 CPUID_EXT_FMA | CPUID_EXT_X2APIC | CPUID_EXT_KERNEL_FEATURES) 806 /* missing: 807 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX, 808 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, 809 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA, 810 CPUID_EXT_TSC_DEADLINE_TIMER 811 */ 812 813 #ifdef TARGET_X86_64 814 #define TCG_EXT2_X86_64_FEATURES CPUID_EXT2_LM 815 #else 816 #define TCG_EXT2_X86_64_FEATURES 0 817 #endif 818 819 /* 820 * CPUID_*_KERNEL_FEATURES denotes bits and features that are not usable 821 * in usermode or by 32-bit programs. Those are added to supported 822 * TCG features unconditionally in user-mode emulation mode. This may 823 * indeed seem strange or incorrect, but it works because code running 824 * under usermode emulation cannot access them. 825 * 826 * Even for long mode, qemu-i386 is not running "a userspace program on a 827 * 32-bit CPU"; it's running "a userspace program with a 32-bit code segment" 828 * and therefore using the 32-bit ABI; the CPU itself might be 64-bit 829 * but again the difference is only visible in kernel mode. 830 */ 831 #if defined CONFIG_LINUX_USER 832 #define CPUID_EXT2_KERNEL_FEATURES (CPUID_EXT2_LM | CPUID_EXT2_FFXSR) 833 #elif defined CONFIG_USER_ONLY 834 /* FIXME: Long mode not yet supported for i386 bsd-user */ 835 #define CPUID_EXT2_KERNEL_FEATURES CPUID_EXT2_FFXSR 836 #else 837 #define CPUID_EXT2_KERNEL_FEATURES 0 838 #endif 839 840 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \ 841 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \ 842 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \ 843 CPUID_EXT2_SYSCALL | TCG_EXT2_X86_64_FEATURES | \ 844 CPUID_EXT2_KERNEL_FEATURES) 845 846 #if defined CONFIG_USER_ONLY 847 #define CPUID_EXT3_KERNEL_FEATURES CPUID_EXT3_OSVW 848 #else 849 #define CPUID_EXT3_KERNEL_FEATURES 0 850 #endif 851 852 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \ 853 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A | \ 854 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_KERNEL_FEATURES | \ 855 CPUID_EXT3_CMP_LEG) 856 857 #define TCG_EXT4_FEATURES 0 858 859 #if defined CONFIG_USER_ONLY 860 #define CPUID_SVM_KERNEL_FEATURES (CPUID_SVM_NRIPSAVE | CPUID_SVM_VNMI) 861 #else 862 #define CPUID_SVM_KERNEL_FEATURES 0 863 #endif 864 #define TCG_SVM_FEATURES (CPUID_SVM_NPT | CPUID_SVM_VGIF | \ 865 CPUID_SVM_SVME_ADDR_CHK | CPUID_SVM_KERNEL_FEATURES) 866 867 #define TCG_KVM_FEATURES 0 868 869 #if defined CONFIG_USER_ONLY 870 #define CPUID_7_0_EBX_KERNEL_FEATURES CPUID_7_0_EBX_INVPCID 871 #else 872 #define CPUID_7_0_EBX_KERNEL_FEATURES 0 873 #endif 874 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \ 875 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \ 876 CPUID_7_0_EBX_CLFLUSHOPT | \ 877 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \ 878 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_RDSEED | \ 879 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_KERNEL_FEATURES) 880 /* missing: 881 CPUID_7_0_EBX_HLE 882 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM */ 883 884 #if !defined CONFIG_USER_ONLY || defined CONFIG_LINUX 885 #define TCG_7_0_ECX_RDPID CPUID_7_0_ECX_RDPID 886 #else 887 #define TCG_7_0_ECX_RDPID 0 888 #endif 889 #define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | \ 890 /* CPUID_7_0_ECX_OSPKE is dynamic */ \ 891 CPUID_7_0_ECX_LA57 | CPUID_7_0_ECX_PKS | CPUID_7_0_ECX_VAES | \ 892 TCG_7_0_ECX_RDPID) 893 894 #if defined CONFIG_USER_ONLY 895 #define CPUID_7_0_EDX_KERNEL_FEATURES (CPUID_7_0_EDX_SPEC_CTRL | \ 896 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD) 897 #else 898 #define CPUID_7_0_EDX_KERNEL_FEATURES 0 899 #endif 900 #define TCG_7_0_EDX_FEATURES (CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_KERNEL_FEATURES) 901 902 #define TCG_7_1_EAX_FEATURES (CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | \ 903 CPUID_7_1_EAX_FSRC | CPUID_7_1_EAX_CMPCCXADD) 904 #define TCG_7_1_ECX_FEATURES 0 905 #define TCG_7_1_EDX_FEATURES 0 906 #define TCG_7_2_EDX_FEATURES 0 907 #define TCG_APM_FEATURES 0 908 #define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT 909 #define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1) 910 /* missing: 911 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */ 912 #define TCG_14_0_ECX_FEATURES 0 913 #define TCG_SGX_12_0_EAX_FEATURES 0 914 #define TCG_SGX_12_0_EBX_FEATURES 0 915 #define TCG_SGX_12_1_EAX_FEATURES 0 916 #define TCG_24_0_EBX_FEATURES 0 917 918 #if defined CONFIG_USER_ONLY 919 #define CPUID_8000_0008_EBX_KERNEL_FEATURES (CPUID_8000_0008_EBX_IBPB | \ 920 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | \ 921 CPUID_8000_0008_EBX_STIBP_ALWAYS_ON | CPUID_8000_0008_EBX_AMD_SSBD | \ 922 CPUID_8000_0008_EBX_AMD_PSFD) 923 #else 924 #define CPUID_8000_0008_EBX_KERNEL_FEATURES 0 925 #endif 926 927 #define TCG_8000_0008_EBX (CPUID_8000_0008_EBX_XSAVEERPTR | \ 928 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_KERNEL_FEATURES) 929 930 #if defined CONFIG_USER_ONLY 931 #define CPUID_8000_0021_EAX_KERNEL_FEATURES CPUID_8000_0021_EAX_AUTO_IBRS 932 #else 933 #define CPUID_8000_0021_EAX_KERNEL_FEATURES 0 934 #endif 935 936 #define TCG_8000_0021_EAX_FEATURES ( \ 937 CPUID_8000_0021_EAX_NO_NESTED_DATA_BP | \ 938 CPUID_8000_0021_EAX_NULL_SEL_CLR_BASE | \ 939 CPUID_8000_0021_EAX_KERNEL_FEATURES) 940 941 FeatureWordInfo feature_word_info[FEATURE_WORDS] = { 942 [FEAT_1_EDX] = { 943 .type = CPUID_FEATURE_WORD, 944 .feat_names = { 945 "fpu", "vme", "de", "pse", 946 "tsc", "msr", "pae", "mce", 947 "cx8", "apic", NULL, "sep", 948 "mtrr", "pge", "mca", "cmov", 949 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */, 950 NULL, "ds" /* Intel dts */, "acpi", "mmx", 951 "fxsr", "sse", "sse2", "ss", 952 "ht" /* Intel htt */, "tm", "ia64", "pbe", 953 }, 954 .cpuid = {.eax = 1, .reg = R_EDX, }, 955 .tcg_features = TCG_FEATURES, 956 .no_autoenable_flags = CPUID_HT, 957 }, 958 [FEAT_1_ECX] = { 959 .type = CPUID_FEATURE_WORD, 960 .feat_names = { 961 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor", 962 "ds-cpl", "vmx", "smx", "est", 963 "tm2", "ssse3", "cid", NULL, 964 "fma", "cx16", "xtpr", "pdcm", 965 NULL, "pcid", "dca", "sse4.1", 966 "sse4.2", "x2apic", "movbe", "popcnt", 967 "tsc-deadline", "aes", "xsave", NULL /* osxsave */, 968 "avx", "f16c", "rdrand", "hypervisor", 969 }, 970 .cpuid = { .eax = 1, .reg = R_ECX, }, 971 .tcg_features = TCG_EXT_FEATURES, 972 }, 973 /* Feature names that are already defined on feature_name[] but 974 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their 975 * names on feat_names below. They are copied automatically 976 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD. 977 */ 978 [FEAT_8000_0001_EDX] = { 979 .type = CPUID_FEATURE_WORD, 980 .feat_names = { 981 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */, 982 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */, 983 NULL /* cx8 */, NULL /* apic */, NULL, "syscall", 984 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */, 985 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */, 986 "nx", NULL, "mmxext", NULL /* mmx */, 987 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp", 988 NULL, "lm", "3dnowext", "3dnow", 989 }, 990 .cpuid = { .eax = 0x80000001, .reg = R_EDX, }, 991 .tcg_features = TCG_EXT2_FEATURES, 992 }, 993 [FEAT_8000_0001_ECX] = { 994 .type = CPUID_FEATURE_WORD, 995 .feat_names = { 996 "lahf-lm", "cmp-legacy", "svm", "extapic", 997 "cr8legacy", "abm", "sse4a", "misalignsse", 998 "3dnowprefetch", "osvw", "ibs", "xop", 999 "skinit", "wdt", NULL, "lwp", 1000 "fma4", "tce", NULL, "nodeid-msr", 1001 NULL, "tbm", "topoext", "perfctr-core", 1002 "perfctr-nb", NULL, NULL, NULL, 1003 NULL, NULL, NULL, NULL, 1004 }, 1005 .cpuid = { .eax = 0x80000001, .reg = R_ECX, }, 1006 .tcg_features = TCG_EXT3_FEATURES, 1007 /* 1008 * TOPOEXT is always allowed but can't be enabled blindly by 1009 * "-cpu host", as it requires consistent cache topology info 1010 * to be provided so it doesn't confuse guests. 1011 */ 1012 .no_autoenable_flags = CPUID_EXT3_TOPOEXT, 1013 }, 1014 [FEAT_C000_0001_EDX] = { 1015 .type = CPUID_FEATURE_WORD, 1016 .feat_names = { 1017 NULL, NULL, "xstore", "xstore-en", 1018 NULL, NULL, "xcrypt", "xcrypt-en", 1019 "ace2", "ace2-en", "phe", "phe-en", 1020 "pmm", "pmm-en", NULL, NULL, 1021 NULL, NULL, NULL, NULL, 1022 NULL, NULL, NULL, NULL, 1023 NULL, NULL, NULL, NULL, 1024 NULL, NULL, NULL, NULL, 1025 }, 1026 .cpuid = { .eax = 0xC0000001, .reg = R_EDX, }, 1027 .tcg_features = TCG_EXT4_FEATURES, 1028 }, 1029 [FEAT_KVM] = { 1030 .type = CPUID_FEATURE_WORD, 1031 .feat_names = { 1032 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock", 1033 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt", 1034 NULL, "kvm-pv-tlb-flush", "kvm-asyncpf-vmexit", "kvm-pv-ipi", 1035 "kvm-poll-control", "kvm-pv-sched-yield", "kvm-asyncpf-int", "kvm-msi-ext-dest-id", 1036 NULL, NULL, NULL, NULL, 1037 NULL, NULL, NULL, NULL, 1038 "kvmclock-stable-bit", NULL, NULL, NULL, 1039 NULL, NULL, NULL, NULL, 1040 }, 1041 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EAX, }, 1042 .tcg_features = TCG_KVM_FEATURES, 1043 }, 1044 [FEAT_KVM_HINTS] = { 1045 .type = CPUID_FEATURE_WORD, 1046 .feat_names = { 1047 "kvm-hint-dedicated", NULL, NULL, NULL, 1048 NULL, NULL, NULL, NULL, 1049 NULL, NULL, NULL, NULL, 1050 NULL, NULL, NULL, NULL, 1051 NULL, NULL, NULL, NULL, 1052 NULL, NULL, NULL, NULL, 1053 NULL, NULL, NULL, NULL, 1054 NULL, NULL, NULL, NULL, 1055 }, 1056 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EDX, }, 1057 .tcg_features = TCG_KVM_FEATURES, 1058 /* 1059 * KVM hints aren't auto-enabled by -cpu host, they need to be 1060 * explicitly enabled in the command-line. 1061 */ 1062 .no_autoenable_flags = ~0U, 1063 }, 1064 [FEAT_SVM] = { 1065 .type = CPUID_FEATURE_WORD, 1066 .feat_names = { 1067 "npt", "lbrv", "svm-lock", "nrip-save", 1068 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists", 1069 NULL, NULL, "pause-filter", NULL, 1070 "pfthreshold", "avic", NULL, "v-vmsave-vmload", 1071 "vgif", NULL, NULL, NULL, 1072 NULL, NULL, NULL, NULL, 1073 NULL, "vnmi", NULL, NULL, 1074 "svme-addr-chk", NULL, NULL, NULL, 1075 }, 1076 .cpuid = { .eax = 0x8000000A, .reg = R_EDX, }, 1077 .tcg_features = TCG_SVM_FEATURES, 1078 }, 1079 [FEAT_7_0_EBX] = { 1080 .type = CPUID_FEATURE_WORD, 1081 .feat_names = { 1082 "fsgsbase", "tsc-adjust", "sgx", "bmi1", 1083 "hle", "avx2", "fdp-excptn-only", "smep", 1084 "bmi2", "erms", "invpcid", "rtm", 1085 NULL, "zero-fcs-fds", "mpx", NULL, 1086 "avx512f", "avx512dq", "rdseed", "adx", 1087 "smap", "avx512ifma", "pcommit", "clflushopt", 1088 "clwb", "intel-pt", "avx512pf", "avx512er", 1089 "avx512cd", "sha-ni", "avx512bw", "avx512vl", 1090 }, 1091 .cpuid = { 1092 .eax = 7, 1093 .needs_ecx = true, .ecx = 0, 1094 .reg = R_EBX, 1095 }, 1096 .tcg_features = TCG_7_0_EBX_FEATURES, 1097 }, 1098 [FEAT_7_0_ECX] = { 1099 .type = CPUID_FEATURE_WORD, 1100 .feat_names = { 1101 NULL, "avx512vbmi", "umip", "pku", 1102 NULL /* ospke */, "waitpkg", "avx512vbmi2", NULL, 1103 "gfni", "vaes", "vpclmulqdq", "avx512vnni", 1104 "avx512bitalg", NULL, "avx512-vpopcntdq", NULL, 1105 "la57", NULL, NULL, NULL, 1106 NULL, NULL, "rdpid", NULL, 1107 "bus-lock-detect", "cldemote", NULL, "movdiri", 1108 "movdir64b", NULL, "sgxlc", "pks", 1109 }, 1110 .cpuid = { 1111 .eax = 7, 1112 .needs_ecx = true, .ecx = 0, 1113 .reg = R_ECX, 1114 }, 1115 .tcg_features = TCG_7_0_ECX_FEATURES, 1116 }, 1117 [FEAT_7_0_EDX] = { 1118 .type = CPUID_FEATURE_WORD, 1119 .feat_names = { 1120 NULL, NULL, "avx512-4vnniw", "avx512-4fmaps", 1121 "fsrm", NULL, NULL, NULL, 1122 "avx512-vp2intersect", NULL, "md-clear", NULL, 1123 NULL, NULL, "serialize", NULL, 1124 "tsx-ldtrk", NULL, NULL /* pconfig */, "arch-lbr", 1125 NULL, NULL, "amx-bf16", "avx512-fp16", 1126 "amx-tile", "amx-int8", "spec-ctrl", "stibp", 1127 "flush-l1d", "arch-capabilities", "core-capability", "ssbd", 1128 }, 1129 .cpuid = { 1130 .eax = 7, 1131 .needs_ecx = true, .ecx = 0, 1132 .reg = R_EDX, 1133 }, 1134 .tcg_features = TCG_7_0_EDX_FEATURES, 1135 }, 1136 [FEAT_7_1_EAX] = { 1137 .type = CPUID_FEATURE_WORD, 1138 .feat_names = { 1139 "sha512", "sm3", "sm4", NULL, 1140 "avx-vnni", "avx512-bf16", NULL, "cmpccxadd", 1141 NULL, NULL, "fzrm", "fsrs", 1142 "fsrc", NULL, NULL, NULL, 1143 NULL, "fred", "lkgs", "wrmsrns", 1144 NULL, "amx-fp16", NULL, "avx-ifma", 1145 NULL, NULL, "lam", NULL, 1146 NULL, NULL, NULL, NULL, 1147 }, 1148 .cpuid = { 1149 .eax = 7, 1150 .needs_ecx = true, .ecx = 1, 1151 .reg = R_EAX, 1152 }, 1153 .tcg_features = TCG_7_1_EAX_FEATURES, 1154 }, 1155 [FEAT_7_1_ECX] = { 1156 .type = CPUID_FEATURE_WORD, 1157 .feat_names = { 1158 NULL, NULL, NULL, NULL, 1159 NULL, "msr-imm", NULL, NULL, 1160 NULL, NULL, NULL, NULL, 1161 NULL, NULL, NULL, NULL, 1162 NULL, NULL, NULL, NULL, 1163 NULL, NULL, NULL, NULL, 1164 NULL, NULL, NULL, NULL, 1165 NULL, NULL, NULL, NULL, 1166 }, 1167 .cpuid = { 1168 .eax = 7, 1169 .needs_ecx = true, .ecx = 1, 1170 .reg = R_ECX, 1171 }, 1172 .tcg_features = TCG_7_1_ECX_FEATURES, 1173 }, 1174 [FEAT_7_1_EDX] = { 1175 .type = CPUID_FEATURE_WORD, 1176 .feat_names = { 1177 NULL, NULL, NULL, NULL, 1178 "avx-vnni-int8", "avx-ne-convert", NULL, NULL, 1179 "amx-complex", NULL, "avx-vnni-int16", NULL, 1180 NULL, NULL, "prefetchiti", NULL, 1181 NULL, NULL, NULL, "avx10", 1182 NULL, NULL, NULL, NULL, 1183 NULL, NULL, NULL, NULL, 1184 NULL, NULL, NULL, NULL, 1185 }, 1186 .cpuid = { 1187 .eax = 7, 1188 .needs_ecx = true, .ecx = 1, 1189 .reg = R_EDX, 1190 }, 1191 .tcg_features = TCG_7_1_EDX_FEATURES, 1192 }, 1193 [FEAT_7_2_EDX] = { 1194 .type = CPUID_FEATURE_WORD, 1195 .feat_names = { 1196 "intel-psfd", "ipred-ctrl", "rrsba-ctrl", "ddpd-u", 1197 "bhi-ctrl", "mcdt-no", NULL, NULL, 1198 NULL, NULL, NULL, NULL, 1199 NULL, NULL, NULL, NULL, 1200 NULL, NULL, NULL, NULL, 1201 NULL, NULL, NULL, NULL, 1202 NULL, NULL, NULL, NULL, 1203 NULL, NULL, NULL, NULL, 1204 }, 1205 .cpuid = { 1206 .eax = 7, 1207 .needs_ecx = true, .ecx = 2, 1208 .reg = R_EDX, 1209 }, 1210 .tcg_features = TCG_7_2_EDX_FEATURES, 1211 }, 1212 [FEAT_24_0_EBX] = { 1213 .type = CPUID_FEATURE_WORD, 1214 .feat_names = { 1215 [16] = "avx10-128", 1216 [17] = "avx10-256", 1217 [18] = "avx10-512", 1218 }, 1219 .cpuid = { 1220 .eax = 0x24, 1221 .needs_ecx = true, .ecx = 0, 1222 .reg = R_EBX, 1223 }, 1224 .tcg_features = TCG_24_0_EBX_FEATURES, 1225 }, 1226 [FEAT_8000_0007_EDX] = { 1227 .type = CPUID_FEATURE_WORD, 1228 .feat_names = { 1229 NULL, NULL, NULL, NULL, 1230 NULL, NULL, NULL, NULL, 1231 "invtsc", NULL, NULL, NULL, 1232 NULL, NULL, NULL, NULL, 1233 NULL, NULL, NULL, NULL, 1234 NULL, NULL, NULL, NULL, 1235 NULL, NULL, NULL, NULL, 1236 NULL, NULL, NULL, NULL, 1237 }, 1238 .cpuid = { .eax = 0x80000007, .reg = R_EDX, }, 1239 .tcg_features = TCG_APM_FEATURES, 1240 .unmigratable_flags = CPUID_APM_INVTSC, 1241 }, 1242 [FEAT_8000_0007_EBX] = { 1243 .type = CPUID_FEATURE_WORD, 1244 .feat_names = { 1245 "overflow-recov", "succor", NULL, NULL, 1246 NULL, NULL, NULL, NULL, 1247 NULL, NULL, NULL, NULL, 1248 NULL, NULL, NULL, NULL, 1249 NULL, NULL, NULL, NULL, 1250 NULL, NULL, NULL, NULL, 1251 NULL, NULL, NULL, NULL, 1252 NULL, NULL, NULL, NULL, 1253 }, 1254 .cpuid = { .eax = 0x80000007, .reg = R_EBX, }, 1255 .tcg_features = 0, 1256 .unmigratable_flags = 0, 1257 }, 1258 [FEAT_8000_0008_EBX] = { 1259 .type = CPUID_FEATURE_WORD, 1260 .feat_names = { 1261 "clzero", NULL, "xsaveerptr", NULL, 1262 NULL, NULL, NULL, NULL, 1263 NULL, "wbnoinvd", NULL, NULL, 1264 "ibpb", NULL, "ibrs", "amd-stibp", 1265 NULL, "stibp-always-on", NULL, NULL, 1266 NULL, NULL, NULL, NULL, 1267 "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL, 1268 "amd-psfd", NULL, NULL, NULL, 1269 }, 1270 .cpuid = { .eax = 0x80000008, .reg = R_EBX, }, 1271 .tcg_features = TCG_8000_0008_EBX, 1272 .unmigratable_flags = 0, 1273 }, 1274 [FEAT_8000_0021_EAX] = { 1275 .type = CPUID_FEATURE_WORD, 1276 .feat_names = { 1277 "no-nested-data-bp", "fs-gs-base-ns", "lfence-always-serializing", NULL, 1278 NULL, NULL, "null-sel-clr-base", NULL, 1279 "auto-ibrs", NULL, NULL, NULL, 1280 NULL, NULL, NULL, NULL, 1281 NULL, NULL, NULL, NULL, 1282 "prefetchi", NULL, NULL, NULL, 1283 "eraps", NULL, NULL, "sbpb", 1284 "ibpb-brtype", "srso-no", "srso-user-kernel-no", NULL, 1285 }, 1286 .cpuid = { .eax = 0x80000021, .reg = R_EAX, }, 1287 .tcg_features = TCG_8000_0021_EAX_FEATURES, 1288 .unmigratable_flags = 0, 1289 }, 1290 [FEAT_8000_0021_EBX] = { 1291 .type = CPUID_FEATURE_WORD, 1292 .cpuid = { .eax = 0x80000021, .reg = R_EBX, }, 1293 .tcg_features = 0, 1294 .unmigratable_flags = 0, 1295 }, 1296 [FEAT_8000_0022_EAX] = { 1297 .type = CPUID_FEATURE_WORD, 1298 .feat_names = { 1299 "perfmon-v2", NULL, NULL, NULL, 1300 NULL, NULL, NULL, NULL, 1301 NULL, NULL, NULL, NULL, 1302 NULL, NULL, NULL, NULL, 1303 NULL, NULL, NULL, NULL, 1304 NULL, NULL, NULL, NULL, 1305 NULL, NULL, NULL, NULL, 1306 NULL, NULL, NULL, NULL, 1307 }, 1308 .cpuid = { .eax = 0x80000022, .reg = R_EAX, }, 1309 .tcg_features = 0, 1310 .unmigratable_flags = 0, 1311 }, 1312 [FEAT_XSAVE] = { 1313 .type = CPUID_FEATURE_WORD, 1314 .feat_names = { 1315 "xsaveopt", "xsavec", "xgetbv1", "xsaves", 1316 "xfd", NULL, NULL, NULL, 1317 NULL, NULL, NULL, NULL, 1318 NULL, NULL, NULL, NULL, 1319 NULL, NULL, NULL, NULL, 1320 NULL, NULL, NULL, NULL, 1321 NULL, NULL, NULL, NULL, 1322 NULL, NULL, NULL, NULL, 1323 }, 1324 .cpuid = { 1325 .eax = 0xd, 1326 .needs_ecx = true, .ecx = 1, 1327 .reg = R_EAX, 1328 }, 1329 .tcg_features = TCG_XSAVE_FEATURES, 1330 }, 1331 [FEAT_XSAVE_XSS_LO] = { 1332 .type = CPUID_FEATURE_WORD, 1333 .feat_names = { 1334 NULL, NULL, NULL, NULL, 1335 NULL, NULL, NULL, NULL, 1336 NULL, NULL, NULL, NULL, 1337 NULL, NULL, NULL, NULL, 1338 NULL, NULL, NULL, NULL, 1339 NULL, NULL, NULL, NULL, 1340 NULL, NULL, NULL, NULL, 1341 NULL, NULL, NULL, NULL, 1342 }, 1343 .cpuid = { 1344 .eax = 0xD, 1345 .needs_ecx = true, 1346 .ecx = 1, 1347 .reg = R_ECX, 1348 }, 1349 }, 1350 [FEAT_XSAVE_XSS_HI] = { 1351 .type = CPUID_FEATURE_WORD, 1352 .cpuid = { 1353 .eax = 0xD, 1354 .needs_ecx = true, 1355 .ecx = 1, 1356 .reg = R_EDX 1357 }, 1358 }, 1359 [FEAT_6_EAX] = { 1360 .type = CPUID_FEATURE_WORD, 1361 .feat_names = { 1362 NULL, NULL, "arat", NULL, 1363 NULL, NULL, NULL, NULL, 1364 NULL, NULL, NULL, NULL, 1365 NULL, NULL, NULL, NULL, 1366 NULL, NULL, NULL, NULL, 1367 NULL, NULL, NULL, NULL, 1368 NULL, NULL, NULL, NULL, 1369 NULL, NULL, NULL, NULL, 1370 }, 1371 .cpuid = { .eax = 6, .reg = R_EAX, }, 1372 .tcg_features = TCG_6_EAX_FEATURES, 1373 }, 1374 [FEAT_XSAVE_XCR0_LO] = { 1375 .type = CPUID_FEATURE_WORD, 1376 .cpuid = { 1377 .eax = 0xD, 1378 .needs_ecx = true, .ecx = 0, 1379 .reg = R_EAX, 1380 }, 1381 .tcg_features = XSTATE_FP_MASK | XSTATE_SSE_MASK | 1382 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK | 1383 XSTATE_PKRU_MASK, 1384 .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK | 1385 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK | 1386 XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK | 1387 XSTATE_PKRU_MASK, 1388 }, 1389 [FEAT_XSAVE_XCR0_HI] = { 1390 .type = CPUID_FEATURE_WORD, 1391 .cpuid = { 1392 .eax = 0xD, 1393 .needs_ecx = true, .ecx = 0, 1394 .reg = R_EDX, 1395 }, 1396 .tcg_features = 0U, 1397 }, 1398 /*Below are MSR exposed features*/ 1399 [FEAT_ARCH_CAPABILITIES] = { 1400 .type = MSR_FEATURE_WORD, 1401 .feat_names = { 1402 "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry", 1403 "ssb-no", "mds-no", "pschange-mc-no", "tsx-ctrl", 1404 "taa-no", NULL, NULL, NULL, 1405 NULL, "sbdr-ssdp-no", "fbsdp-no", "psdp-no", 1406 NULL, "fb-clear", NULL, NULL, 1407 "bhi-no", NULL, NULL, NULL, 1408 "pbrsb-no", NULL, "gds-no", "rfds-no", 1409 "rfds-clear", NULL, NULL, NULL, 1410 NULL, NULL, NULL, NULL, 1411 NULL, NULL, NULL, NULL, 1412 NULL, NULL, NULL, NULL, 1413 NULL, NULL, NULL, NULL, 1414 NULL, NULL, NULL, NULL, 1415 NULL, NULL, NULL, NULL, 1416 NULL, NULL, NULL, NULL, 1417 NULL, NULL, "its-no", NULL, 1418 }, 1419 .msr = { 1420 .index = MSR_IA32_ARCH_CAPABILITIES, 1421 }, 1422 /* 1423 * FEAT_ARCH_CAPABILITIES only affects a read-only MSR, which 1424 * cannot be read from user mode. Therefore, it has no impact 1425 > on any user-mode operation, and warnings about unsupported 1426 * features do not matter. 1427 */ 1428 .tcg_features = ~0U, 1429 }, 1430 [FEAT_CORE_CAPABILITY] = { 1431 .type = MSR_FEATURE_WORD, 1432 .feat_names = { 1433 NULL, NULL, NULL, NULL, 1434 NULL, "split-lock-detect", NULL, NULL, 1435 NULL, NULL, NULL, NULL, 1436 NULL, NULL, NULL, NULL, 1437 NULL, NULL, NULL, NULL, 1438 NULL, NULL, NULL, NULL, 1439 NULL, NULL, NULL, NULL, 1440 NULL, NULL, NULL, NULL, 1441 }, 1442 .msr = { 1443 .index = MSR_IA32_CORE_CAPABILITY, 1444 }, 1445 }, 1446 [FEAT_PERF_CAPABILITIES] = { 1447 .type = MSR_FEATURE_WORD, 1448 .feat_names = { 1449 NULL, NULL, NULL, NULL, 1450 NULL, NULL, NULL, NULL, 1451 NULL, NULL, NULL, NULL, 1452 NULL, "full-width-write", NULL, NULL, 1453 NULL, NULL, NULL, NULL, 1454 NULL, NULL, NULL, NULL, 1455 NULL, NULL, NULL, NULL, 1456 NULL, NULL, NULL, NULL, 1457 }, 1458 .msr = { 1459 .index = MSR_IA32_PERF_CAPABILITIES, 1460 }, 1461 }, 1462 1463 [FEAT_VMX_PROCBASED_CTLS] = { 1464 .type = MSR_FEATURE_WORD, 1465 .feat_names = { 1466 NULL, NULL, "vmx-vintr-pending", "vmx-tsc-offset", 1467 NULL, NULL, NULL, "vmx-hlt-exit", 1468 NULL, "vmx-invlpg-exit", "vmx-mwait-exit", "vmx-rdpmc-exit", 1469 "vmx-rdtsc-exit", NULL, NULL, "vmx-cr3-load-noexit", 1470 "vmx-cr3-store-noexit", NULL, NULL, "vmx-cr8-load-exit", 1471 "vmx-cr8-store-exit", "vmx-flexpriority", "vmx-vnmi-pending", "vmx-movdr-exit", 1472 "vmx-io-exit", "vmx-io-bitmap", NULL, "vmx-mtf", 1473 "vmx-msr-bitmap", "vmx-monitor-exit", "vmx-pause-exit", "vmx-secondary-ctls", 1474 }, 1475 .msr = { 1476 .index = MSR_IA32_VMX_TRUE_PROCBASED_CTLS, 1477 } 1478 }, 1479 1480 [FEAT_VMX_SECONDARY_CTLS] = { 1481 .type = MSR_FEATURE_WORD, 1482 .feat_names = { 1483 "vmx-apicv-xapic", "vmx-ept", "vmx-desc-exit", "vmx-rdtscp-exit", 1484 "vmx-apicv-x2apic", "vmx-vpid", "vmx-wbinvd-exit", "vmx-unrestricted-guest", 1485 "vmx-apicv-register", "vmx-apicv-vid", "vmx-ple", "vmx-rdrand-exit", 1486 "vmx-invpcid-exit", "vmx-vmfunc", "vmx-shadow-vmcs", "vmx-encls-exit", 1487 "vmx-rdseed-exit", "vmx-pml", NULL, NULL, 1488 "vmx-xsaves", NULL, NULL, NULL, 1489 NULL, "vmx-tsc-scaling", "vmx-enable-user-wait-pause", NULL, 1490 NULL, NULL, NULL, NULL, 1491 }, 1492 .msr = { 1493 .index = MSR_IA32_VMX_PROCBASED_CTLS2, 1494 } 1495 }, 1496 1497 [FEAT_VMX_PINBASED_CTLS] = { 1498 .type = MSR_FEATURE_WORD, 1499 .feat_names = { 1500 "vmx-intr-exit", NULL, NULL, "vmx-nmi-exit", 1501 NULL, "vmx-vnmi", "vmx-preemption-timer", "vmx-posted-intr", 1502 NULL, NULL, NULL, NULL, 1503 NULL, NULL, NULL, NULL, 1504 NULL, NULL, NULL, NULL, 1505 NULL, NULL, NULL, NULL, 1506 NULL, NULL, NULL, NULL, 1507 NULL, NULL, NULL, NULL, 1508 }, 1509 .msr = { 1510 .index = MSR_IA32_VMX_TRUE_PINBASED_CTLS, 1511 } 1512 }, 1513 1514 [FEAT_VMX_EXIT_CTLS] = { 1515 .type = MSR_FEATURE_WORD, 1516 /* 1517 * VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE is copied from 1518 * the LM CPUID bit. 1519 */ 1520 .feat_names = { 1521 NULL, NULL, "vmx-exit-nosave-debugctl", NULL, 1522 NULL, NULL, NULL, NULL, 1523 NULL, NULL /* vmx-exit-host-addr-space-size */, NULL, NULL, 1524 "vmx-exit-load-perf-global-ctrl", NULL, NULL, "vmx-exit-ack-intr", 1525 NULL, NULL, "vmx-exit-save-pat", "vmx-exit-load-pat", 1526 "vmx-exit-save-efer", "vmx-exit-load-efer", 1527 "vmx-exit-save-preemption-timer", "vmx-exit-clear-bndcfgs", 1528 NULL, "vmx-exit-clear-rtit-ctl", NULL, NULL, 1529 NULL, "vmx-exit-load-pkrs", NULL, "vmx-exit-secondary-ctls", 1530 }, 1531 .msr = { 1532 .index = MSR_IA32_VMX_TRUE_EXIT_CTLS, 1533 } 1534 }, 1535 1536 [FEAT_VMX_ENTRY_CTLS] = { 1537 .type = MSR_FEATURE_WORD, 1538 .feat_names = { 1539 NULL, NULL, "vmx-entry-noload-debugctl", NULL, 1540 NULL, NULL, NULL, NULL, 1541 NULL, "vmx-entry-ia32e-mode", NULL, NULL, 1542 NULL, "vmx-entry-load-perf-global-ctrl", "vmx-entry-load-pat", "vmx-entry-load-efer", 1543 "vmx-entry-load-bndcfgs", NULL, "vmx-entry-load-rtit-ctl", NULL, 1544 NULL, NULL, "vmx-entry-load-pkrs", "vmx-entry-load-fred", 1545 NULL, NULL, NULL, NULL, 1546 NULL, NULL, NULL, NULL, 1547 }, 1548 .msr = { 1549 .index = MSR_IA32_VMX_TRUE_ENTRY_CTLS, 1550 } 1551 }, 1552 1553 [FEAT_VMX_MISC] = { 1554 .type = MSR_FEATURE_WORD, 1555 .feat_names = { 1556 NULL, NULL, NULL, NULL, 1557 NULL, "vmx-store-lma", "vmx-activity-hlt", "vmx-activity-shutdown", 1558 "vmx-activity-wait-sipi", NULL, NULL, NULL, 1559 NULL, NULL, NULL, NULL, 1560 NULL, NULL, NULL, NULL, 1561 NULL, NULL, NULL, NULL, 1562 NULL, NULL, NULL, NULL, 1563 NULL, "vmx-vmwrite-vmexit-fields", "vmx-zero-len-inject", NULL, 1564 }, 1565 .msr = { 1566 .index = MSR_IA32_VMX_MISC, 1567 } 1568 }, 1569 1570 [FEAT_VMX_EPT_VPID_CAPS] = { 1571 .type = MSR_FEATURE_WORD, 1572 .feat_names = { 1573 "vmx-ept-execonly", NULL, NULL, NULL, 1574 NULL, NULL, "vmx-page-walk-4", "vmx-page-walk-5", 1575 NULL, NULL, NULL, NULL, 1576 NULL, NULL, NULL, NULL, 1577 "vmx-ept-2mb", "vmx-ept-1gb", NULL, NULL, 1578 "vmx-invept", "vmx-eptad", "vmx-ept-advanced-exitinfo", NULL, 1579 NULL, "vmx-invept-single-context", "vmx-invept-all-context", NULL, 1580 NULL, NULL, NULL, NULL, 1581 "vmx-invvpid", NULL, NULL, NULL, 1582 NULL, NULL, NULL, NULL, 1583 "vmx-invvpid-single-addr", "vmx-invept-single-context", 1584 "vmx-invvpid-all-context", "vmx-invept-single-context-noglobals", 1585 NULL, NULL, NULL, NULL, 1586 NULL, NULL, NULL, NULL, 1587 NULL, NULL, NULL, NULL, 1588 NULL, NULL, NULL, NULL, 1589 NULL, NULL, NULL, NULL, 1590 }, 1591 .msr = { 1592 .index = MSR_IA32_VMX_EPT_VPID_CAP, 1593 } 1594 }, 1595 1596 [FEAT_VMX_BASIC] = { 1597 .type = MSR_FEATURE_WORD, 1598 .feat_names = { 1599 [54] = "vmx-ins-outs", 1600 [55] = "vmx-true-ctls", 1601 [56] = "vmx-any-errcode", 1602 [58] = "vmx-nested-exception", 1603 }, 1604 .msr = { 1605 .index = MSR_IA32_VMX_BASIC, 1606 }, 1607 /* Just to be safe - we don't support setting the MSEG version field. */ 1608 .no_autoenable_flags = MSR_VMX_BASIC_DUAL_MONITOR, 1609 }, 1610 1611 [FEAT_VMX_VMFUNC] = { 1612 .type = MSR_FEATURE_WORD, 1613 .feat_names = { 1614 [0] = "vmx-eptp-switching", 1615 }, 1616 .msr = { 1617 .index = MSR_IA32_VMX_VMFUNC, 1618 } 1619 }, 1620 1621 [FEAT_14_0_ECX] = { 1622 .type = CPUID_FEATURE_WORD, 1623 .feat_names = { 1624 NULL, NULL, NULL, NULL, 1625 NULL, NULL, NULL, NULL, 1626 NULL, NULL, NULL, NULL, 1627 NULL, NULL, NULL, NULL, 1628 NULL, NULL, NULL, NULL, 1629 NULL, NULL, NULL, NULL, 1630 NULL, NULL, NULL, NULL, 1631 NULL, NULL, NULL, "intel-pt-lip", 1632 }, 1633 .cpuid = { 1634 .eax = 0x14, 1635 .needs_ecx = true, .ecx = 0, 1636 .reg = R_ECX, 1637 }, 1638 .tcg_features = TCG_14_0_ECX_FEATURES, 1639 }, 1640 1641 [FEAT_SGX_12_0_EAX] = { 1642 .type = CPUID_FEATURE_WORD, 1643 .feat_names = { 1644 "sgx1", "sgx2", NULL, NULL, 1645 NULL, NULL, NULL, NULL, 1646 NULL, NULL, NULL, "sgx-edeccssa", 1647 NULL, NULL, NULL, NULL, 1648 NULL, NULL, NULL, NULL, 1649 NULL, NULL, NULL, NULL, 1650 NULL, NULL, NULL, NULL, 1651 NULL, NULL, NULL, NULL, 1652 }, 1653 .cpuid = { 1654 .eax = 0x12, 1655 .needs_ecx = true, .ecx = 0, 1656 .reg = R_EAX, 1657 }, 1658 .tcg_features = TCG_SGX_12_0_EAX_FEATURES, 1659 }, 1660 1661 [FEAT_SGX_12_0_EBX] = { 1662 .type = CPUID_FEATURE_WORD, 1663 .feat_names = { 1664 "sgx-exinfo" , NULL, NULL, NULL, 1665 NULL, NULL, NULL, NULL, 1666 NULL, NULL, NULL, NULL, 1667 NULL, NULL, NULL, NULL, 1668 NULL, NULL, NULL, NULL, 1669 NULL, NULL, NULL, NULL, 1670 NULL, NULL, NULL, NULL, 1671 NULL, NULL, NULL, NULL, 1672 }, 1673 .cpuid = { 1674 .eax = 0x12, 1675 .needs_ecx = true, .ecx = 0, 1676 .reg = R_EBX, 1677 }, 1678 .tcg_features = TCG_SGX_12_0_EBX_FEATURES, 1679 }, 1680 1681 [FEAT_SGX_12_1_EAX] = { 1682 .type = CPUID_FEATURE_WORD, 1683 .feat_names = { 1684 NULL, "sgx-debug", "sgx-mode64", NULL, 1685 "sgx-provisionkey", "sgx-tokenkey", NULL, "sgx-kss", 1686 NULL, NULL, "sgx-aex-notify", NULL, 1687 NULL, NULL, NULL, NULL, 1688 NULL, NULL, NULL, NULL, 1689 NULL, NULL, NULL, NULL, 1690 NULL, NULL, NULL, NULL, 1691 NULL, NULL, NULL, NULL, 1692 }, 1693 .cpuid = { 1694 .eax = 0x12, 1695 .needs_ecx = true, .ecx = 1, 1696 .reg = R_EAX, 1697 }, 1698 .tcg_features = TCG_SGX_12_1_EAX_FEATURES, 1699 }, 1700 }; 1701 1702 bool is_feature_word_cpuid(uint32_t feature, uint32_t index, int reg) 1703 { 1704 FeatureWordInfo *wi; 1705 FeatureWord w; 1706 1707 for (w = 0; w < FEATURE_WORDS; w++) { 1708 wi = &feature_word_info[w]; 1709 if (wi->type == CPUID_FEATURE_WORD && wi->cpuid.eax == feature && 1710 (!wi->cpuid.needs_ecx || wi->cpuid.ecx == index) && 1711 wi->cpuid.reg == reg) { 1712 return true; 1713 } 1714 } 1715 return false; 1716 } 1717 1718 static FeatureDep feature_dependencies[] = { 1719 { 1720 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_ARCH_CAPABILITIES }, 1721 .to = { FEAT_ARCH_CAPABILITIES, ~0ull }, 1722 }, 1723 { 1724 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_CORE_CAPABILITY }, 1725 .to = { FEAT_CORE_CAPABILITY, ~0ull }, 1726 }, 1727 { 1728 .from = { FEAT_1_ECX, CPUID_EXT_PDCM }, 1729 .to = { FEAT_PERF_CAPABILITIES, ~0ull }, 1730 }, 1731 { 1732 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1733 .to = { FEAT_VMX_PROCBASED_CTLS, ~0ull }, 1734 }, 1735 { 1736 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1737 .to = { FEAT_VMX_PINBASED_CTLS, ~0ull }, 1738 }, 1739 { 1740 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1741 .to = { FEAT_VMX_EXIT_CTLS, ~0ull }, 1742 }, 1743 { 1744 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1745 .to = { FEAT_VMX_ENTRY_CTLS, ~0ull }, 1746 }, 1747 { 1748 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1749 .to = { FEAT_VMX_MISC, ~0ull }, 1750 }, 1751 { 1752 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1753 .to = { FEAT_VMX_BASIC, ~0ull }, 1754 }, 1755 { 1756 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_LM }, 1757 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_IA32E_MODE }, 1758 }, 1759 { 1760 .from = { FEAT_VMX_PROCBASED_CTLS, VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS }, 1761 .to = { FEAT_VMX_SECONDARY_CTLS, ~0ull }, 1762 }, 1763 { 1764 .from = { FEAT_XSAVE, CPUID_XSAVE_XSAVES }, 1765 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_XSAVES }, 1766 }, 1767 { 1768 .from = { FEAT_1_ECX, CPUID_EXT_RDRAND }, 1769 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDRAND_EXITING }, 1770 }, 1771 { 1772 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INVPCID }, 1773 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_INVPCID }, 1774 }, 1775 { 1776 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_MPX }, 1777 .to = { FEAT_VMX_EXIT_CTLS, VMX_VM_EXIT_CLEAR_BNDCFGS }, 1778 }, 1779 { 1780 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_MPX }, 1781 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_LOAD_BNDCFGS }, 1782 }, 1783 { 1784 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_RDSEED }, 1785 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDSEED_EXITING }, 1786 }, 1787 { 1788 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT }, 1789 .to = { FEAT_14_0_ECX, ~0ull }, 1790 }, 1791 { 1792 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_RDTSCP }, 1793 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDTSCP }, 1794 }, 1795 { 1796 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT }, 1797 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull }, 1798 }, 1799 { 1800 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT }, 1801 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST }, 1802 }, 1803 { 1804 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VPID }, 1805 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull << 32 }, 1806 }, 1807 { 1808 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VMFUNC }, 1809 .to = { FEAT_VMX_VMFUNC, ~0ull }, 1810 }, 1811 { 1812 .from = { FEAT_8000_0001_ECX, CPUID_EXT3_SVM }, 1813 .to = { FEAT_SVM, ~0ull }, 1814 }, 1815 { 1816 .from = { FEAT_7_0_ECX, CPUID_7_0_ECX_WAITPKG }, 1817 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_USER_WAIT_PAUSE }, 1818 }, 1819 { 1820 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_LM }, 1821 .to = { FEAT_7_1_EAX, CPUID_7_1_EAX_FRED }, 1822 }, 1823 { 1824 .from = { FEAT_7_1_EAX, CPUID_7_1_EAX_LKGS }, 1825 .to = { FEAT_7_1_EAX, CPUID_7_1_EAX_FRED }, 1826 }, 1827 { 1828 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_SGX }, 1829 .to = { FEAT_7_0_ECX, CPUID_7_0_ECX_SGX_LC }, 1830 }, 1831 { 1832 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_SGX }, 1833 .to = { FEAT_SGX_12_0_EAX, ~0ull }, 1834 }, 1835 { 1836 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_SGX }, 1837 .to = { FEAT_SGX_12_0_EBX, ~0ull }, 1838 }, 1839 { 1840 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_SGX }, 1841 .to = { FEAT_SGX_12_1_EAX, ~0ull }, 1842 }, 1843 { 1844 .from = { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_128 }, 1845 .to = { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_256 }, 1846 }, 1847 { 1848 .from = { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_256 }, 1849 .to = { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_512 }, 1850 }, 1851 { 1852 .from = { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_VL_MASK }, 1853 .to = { FEAT_7_1_EDX, CPUID_7_1_EDX_AVX10 }, 1854 }, 1855 { 1856 .from = { FEAT_7_1_EDX, CPUID_7_1_EDX_AVX10 }, 1857 .to = { FEAT_24_0_EBX, ~0ull }, 1858 }, 1859 }; 1860 1861 typedef struct X86RegisterInfo32 { 1862 /* Name of register */ 1863 const char *name; 1864 /* QAPI enum value register */ 1865 X86CPURegister32 qapi_enum; 1866 } X86RegisterInfo32; 1867 1868 #define REGISTER(reg) \ 1869 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg } 1870 static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = { 1871 REGISTER(EAX), 1872 REGISTER(ECX), 1873 REGISTER(EDX), 1874 REGISTER(EBX), 1875 REGISTER(ESP), 1876 REGISTER(EBP), 1877 REGISTER(ESI), 1878 REGISTER(EDI), 1879 }; 1880 #undef REGISTER 1881 1882 ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUNT] = { 1883 [XSTATE_FP_BIT] = { 1884 /* x87 FP state component is always enabled if XSAVE is supported */ 1885 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE, 1886 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader), 1887 }, 1888 [XSTATE_SSE_BIT] = { 1889 /* SSE state component is always enabled if XSAVE is supported */ 1890 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE, 1891 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader), 1892 }, 1893 [XSTATE_YMM_BIT] = 1894 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX, 1895 .size = sizeof(XSaveAVX) }, 1896 [XSTATE_BNDREGS_BIT] = 1897 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX, 1898 .size = sizeof(XSaveBNDREG) }, 1899 [XSTATE_BNDCSR_BIT] = 1900 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX, 1901 .size = sizeof(XSaveBNDCSR) }, 1902 [XSTATE_OPMASK_BIT] = 1903 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1904 .size = sizeof(XSaveOpmask) }, 1905 [XSTATE_ZMM_Hi256_BIT] = 1906 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1907 .size = sizeof(XSaveZMM_Hi256) }, 1908 [XSTATE_Hi16_ZMM_BIT] = 1909 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1910 .size = sizeof(XSaveHi16_ZMM) }, 1911 [XSTATE_PKRU_BIT] = 1912 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU, 1913 .size = sizeof(XSavePKRU) }, 1914 [XSTATE_ARCH_LBR_BIT] = { 1915 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_ARCH_LBR, 1916 .offset = 0 /*supervisor mode component, offset = 0 */, 1917 .size = sizeof(XSavesArchLBR) }, 1918 [XSTATE_XTILE_CFG_BIT] = { 1919 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_AMX_TILE, 1920 .size = sizeof(XSaveXTILECFG), 1921 }, 1922 [XSTATE_XTILE_DATA_BIT] = { 1923 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_AMX_TILE, 1924 .size = sizeof(XSaveXTILEDATA) 1925 }, 1926 }; 1927 1928 uint32_t xsave_area_size(uint64_t mask, bool compacted) 1929 { 1930 uint64_t ret = x86_ext_save_areas[0].size; 1931 const ExtSaveArea *esa; 1932 uint32_t offset = 0; 1933 int i; 1934 1935 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 1936 esa = &x86_ext_save_areas[i]; 1937 if ((mask >> i) & 1) { 1938 offset = compacted ? ret : esa->offset; 1939 ret = MAX(ret, offset + esa->size); 1940 } 1941 } 1942 return ret; 1943 } 1944 1945 static inline bool accel_uses_host_cpuid(void) 1946 { 1947 return !tcg_enabled() && !qtest_enabled(); 1948 } 1949 1950 static inline uint64_t x86_cpu_xsave_xcr0_components(X86CPU *cpu) 1951 { 1952 return ((uint64_t)cpu->env.features[FEAT_XSAVE_XCR0_HI]) << 32 | 1953 cpu->env.features[FEAT_XSAVE_XCR0_LO]; 1954 } 1955 1956 /* Return name of 32-bit register, from a R_* constant */ 1957 static const char *get_register_name_32(unsigned int reg) 1958 { 1959 if (reg >= CPU_NB_REGS32) { 1960 return NULL; 1961 } 1962 return x86_reg_info_32[reg].name; 1963 } 1964 1965 static inline uint64_t x86_cpu_xsave_xss_components(X86CPU *cpu) 1966 { 1967 return ((uint64_t)cpu->env.features[FEAT_XSAVE_XSS_HI]) << 32 | 1968 cpu->env.features[FEAT_XSAVE_XSS_LO]; 1969 } 1970 1971 /* 1972 * Returns the set of feature flags that are supported and migratable by 1973 * QEMU, for a given FeatureWord. 1974 */ 1975 static uint64_t x86_cpu_get_migratable_flags(X86CPU *cpu, FeatureWord w) 1976 { 1977 FeatureWordInfo *wi = &feature_word_info[w]; 1978 CPUX86State *env = &cpu->env; 1979 uint64_t r = 0; 1980 int i; 1981 1982 for (i = 0; i < 64; i++) { 1983 uint64_t f = 1ULL << i; 1984 1985 /* If the feature name is known, it is implicitly considered migratable, 1986 * unless it is explicitly set in unmigratable_flags */ 1987 if ((wi->migratable_flags & f) || 1988 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) { 1989 r |= f; 1990 } 1991 } 1992 1993 /* when tsc-khz is set explicitly, invtsc is migratable */ 1994 if ((w == FEAT_8000_0007_EDX) && env->user_tsc_khz) { 1995 r |= CPUID_APM_INVTSC; 1996 } 1997 1998 return r; 1999 } 2000 2001 void host_cpuid(uint32_t function, uint32_t count, 2002 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) 2003 { 2004 uint32_t vec[4]; 2005 2006 #ifdef __x86_64__ 2007 asm volatile("cpuid" 2008 : "=a"(vec[0]), "=b"(vec[1]), 2009 "=c"(vec[2]), "=d"(vec[3]) 2010 : "0"(function), "c"(count) : "cc"); 2011 #elif defined(__i386__) 2012 asm volatile("pusha \n\t" 2013 "cpuid \n\t" 2014 "mov %%eax, 0(%2) \n\t" 2015 "mov %%ebx, 4(%2) \n\t" 2016 "mov %%ecx, 8(%2) \n\t" 2017 "mov %%edx, 12(%2) \n\t" 2018 "popa" 2019 : : "a"(function), "c"(count), "S"(vec) 2020 : "memory", "cc"); 2021 #else 2022 abort(); 2023 #endif 2024 2025 if (eax) 2026 *eax = vec[0]; 2027 if (ebx) 2028 *ebx = vec[1]; 2029 if (ecx) 2030 *ecx = vec[2]; 2031 if (edx) 2032 *edx = vec[3]; 2033 } 2034 2035 /* CPU class name definitions: */ 2036 2037 /* Return type name for a given CPU model name 2038 * Caller is responsible for freeing the returned string. 2039 */ 2040 static char *x86_cpu_type_name(const char *model_name) 2041 { 2042 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name); 2043 } 2044 2045 static ObjectClass *x86_cpu_class_by_name(const char *cpu_model) 2046 { 2047 g_autofree char *typename = x86_cpu_type_name(cpu_model); 2048 return object_class_by_name(typename); 2049 } 2050 2051 static char *x86_cpu_class_get_model_name(X86CPUClass *cc) 2052 { 2053 const char *class_name = object_class_get_name(OBJECT_CLASS(cc)); 2054 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX)); 2055 return cpu_model_from_type(class_name); 2056 } 2057 2058 typedef struct X86CPUVersionDefinition { 2059 X86CPUVersion version; 2060 const char *alias; 2061 const char *note; 2062 PropValue *props; 2063 const CPUCaches *const cache_info; 2064 } X86CPUVersionDefinition; 2065 2066 /* Base definition for a CPU model */ 2067 typedef struct X86CPUDefinition { 2068 const char *name; 2069 uint32_t level; 2070 uint32_t xlevel; 2071 /* vendor is zero-terminated, 12 character ASCII string */ 2072 char vendor[CPUID_VENDOR_SZ + 1]; 2073 int family; 2074 int model; 2075 int stepping; 2076 uint8_t avx10_version; 2077 FeatureWordArray features; 2078 const char *model_id; 2079 const CPUCaches *const cache_info; 2080 /* 2081 * Definitions for alternative versions of CPU model. 2082 * List is terminated by item with version == 0. 2083 * If NULL, version 1 will be registered automatically. 2084 */ 2085 const X86CPUVersionDefinition *versions; 2086 const char *deprecation_note; 2087 } X86CPUDefinition; 2088 2089 /* Reference to a specific CPU model version */ 2090 struct X86CPUModel { 2091 /* Base CPU definition */ 2092 const X86CPUDefinition *cpudef; 2093 /* CPU model version */ 2094 X86CPUVersion version; 2095 const char *note; 2096 /* 2097 * If true, this is an alias CPU model. 2098 * This matters only for "-cpu help" and query-cpu-definitions 2099 */ 2100 bool is_alias; 2101 }; 2102 2103 /* Get full model name for CPU version */ 2104 static char *x86_cpu_versioned_model_name(const X86CPUDefinition *cpudef, 2105 X86CPUVersion version) 2106 { 2107 assert(version > 0); 2108 return g_strdup_printf("%s-v%d", cpudef->name, (int)version); 2109 } 2110 2111 static const X86CPUVersionDefinition * 2112 x86_cpu_def_get_versions(const X86CPUDefinition *def) 2113 { 2114 /* When X86CPUDefinition::versions is NULL, we register only v1 */ 2115 static const X86CPUVersionDefinition default_version_list[] = { 2116 { 1 }, 2117 { /* end of list */ } 2118 }; 2119 2120 return def->versions ?: default_version_list; 2121 } 2122 2123 static const CPUCaches epyc_cache_info = { 2124 .l1d_cache = &(CPUCacheInfo) { 2125 .type = DATA_CACHE, 2126 .level = 1, 2127 .size = 32 * KiB, 2128 .line_size = 64, 2129 .associativity = 8, 2130 .partitions = 1, 2131 .sets = 64, 2132 .lines_per_tag = 1, 2133 .self_init = 1, 2134 .no_invd_sharing = true, 2135 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2136 }, 2137 .l1i_cache = &(CPUCacheInfo) { 2138 .type = INSTRUCTION_CACHE, 2139 .level = 1, 2140 .size = 64 * KiB, 2141 .line_size = 64, 2142 .associativity = 4, 2143 .partitions = 1, 2144 .sets = 256, 2145 .lines_per_tag = 1, 2146 .self_init = 1, 2147 .no_invd_sharing = true, 2148 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2149 }, 2150 .l2_cache = &(CPUCacheInfo) { 2151 .type = UNIFIED_CACHE, 2152 .level = 2, 2153 .size = 512 * KiB, 2154 .line_size = 64, 2155 .associativity = 8, 2156 .partitions = 1, 2157 .sets = 1024, 2158 .lines_per_tag = 1, 2159 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2160 }, 2161 .l3_cache = &(CPUCacheInfo) { 2162 .type = UNIFIED_CACHE, 2163 .level = 3, 2164 .size = 8 * MiB, 2165 .line_size = 64, 2166 .associativity = 16, 2167 .partitions = 1, 2168 .sets = 8192, 2169 .lines_per_tag = 1, 2170 .self_init = true, 2171 .inclusive = true, 2172 .complex_indexing = true, 2173 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2174 }, 2175 }; 2176 2177 static CPUCaches epyc_v4_cache_info = { 2178 .l1d_cache = &(CPUCacheInfo) { 2179 .type = DATA_CACHE, 2180 .level = 1, 2181 .size = 32 * KiB, 2182 .line_size = 64, 2183 .associativity = 8, 2184 .partitions = 1, 2185 .sets = 64, 2186 .lines_per_tag = 1, 2187 .self_init = 1, 2188 .no_invd_sharing = true, 2189 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2190 }, 2191 .l1i_cache = &(CPUCacheInfo) { 2192 .type = INSTRUCTION_CACHE, 2193 .level = 1, 2194 .size = 64 * KiB, 2195 .line_size = 64, 2196 .associativity = 4, 2197 .partitions = 1, 2198 .sets = 256, 2199 .lines_per_tag = 1, 2200 .self_init = 1, 2201 .no_invd_sharing = true, 2202 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2203 }, 2204 .l2_cache = &(CPUCacheInfo) { 2205 .type = UNIFIED_CACHE, 2206 .level = 2, 2207 .size = 512 * KiB, 2208 .line_size = 64, 2209 .associativity = 8, 2210 .partitions = 1, 2211 .sets = 1024, 2212 .lines_per_tag = 1, 2213 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2214 }, 2215 .l3_cache = &(CPUCacheInfo) { 2216 .type = UNIFIED_CACHE, 2217 .level = 3, 2218 .size = 8 * MiB, 2219 .line_size = 64, 2220 .associativity = 16, 2221 .partitions = 1, 2222 .sets = 8192, 2223 .lines_per_tag = 1, 2224 .self_init = true, 2225 .inclusive = true, 2226 .complex_indexing = false, 2227 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2228 }, 2229 }; 2230 2231 static CPUCaches epyc_v5_cache_info = { 2232 .l1d_cache = &(CPUCacheInfo) { 2233 .type = DATA_CACHE, 2234 .level = 1, 2235 .size = 32 * KiB, 2236 .line_size = 64, 2237 .associativity = 8, 2238 .partitions = 1, 2239 .sets = 64, 2240 .lines_per_tag = 1, 2241 .self_init = true, 2242 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2243 }, 2244 .l1i_cache = &(CPUCacheInfo) { 2245 .type = INSTRUCTION_CACHE, 2246 .level = 1, 2247 .size = 64 * KiB, 2248 .line_size = 64, 2249 .associativity = 4, 2250 .partitions = 1, 2251 .sets = 256, 2252 .lines_per_tag = 1, 2253 .self_init = true, 2254 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2255 }, 2256 .l2_cache = &(CPUCacheInfo) { 2257 .type = UNIFIED_CACHE, 2258 .level = 2, 2259 .size = 512 * KiB, 2260 .line_size = 64, 2261 .associativity = 8, 2262 .partitions = 1, 2263 .sets = 1024, 2264 .lines_per_tag = 1, 2265 .self_init = true, 2266 .inclusive = true, 2267 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2268 }, 2269 .l3_cache = &(CPUCacheInfo) { 2270 .type = UNIFIED_CACHE, 2271 .level = 3, 2272 .size = 8 * MiB, 2273 .line_size = 64, 2274 .associativity = 16, 2275 .partitions = 1, 2276 .sets = 8192, 2277 .lines_per_tag = 1, 2278 .self_init = true, 2279 .no_invd_sharing = true, 2280 .complex_indexing = false, 2281 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2282 }, 2283 }; 2284 2285 static const CPUCaches epyc_rome_cache_info = { 2286 .l1d_cache = &(CPUCacheInfo) { 2287 .type = DATA_CACHE, 2288 .level = 1, 2289 .size = 32 * KiB, 2290 .line_size = 64, 2291 .associativity = 8, 2292 .partitions = 1, 2293 .sets = 64, 2294 .lines_per_tag = 1, 2295 .self_init = 1, 2296 .no_invd_sharing = true, 2297 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2298 }, 2299 .l1i_cache = &(CPUCacheInfo) { 2300 .type = INSTRUCTION_CACHE, 2301 .level = 1, 2302 .size = 32 * KiB, 2303 .line_size = 64, 2304 .associativity = 8, 2305 .partitions = 1, 2306 .sets = 64, 2307 .lines_per_tag = 1, 2308 .self_init = 1, 2309 .no_invd_sharing = true, 2310 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2311 }, 2312 .l2_cache = &(CPUCacheInfo) { 2313 .type = UNIFIED_CACHE, 2314 .level = 2, 2315 .size = 512 * KiB, 2316 .line_size = 64, 2317 .associativity = 8, 2318 .partitions = 1, 2319 .sets = 1024, 2320 .lines_per_tag = 1, 2321 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2322 }, 2323 .l3_cache = &(CPUCacheInfo) { 2324 .type = UNIFIED_CACHE, 2325 .level = 3, 2326 .size = 16 * MiB, 2327 .line_size = 64, 2328 .associativity = 16, 2329 .partitions = 1, 2330 .sets = 16384, 2331 .lines_per_tag = 1, 2332 .self_init = true, 2333 .inclusive = true, 2334 .complex_indexing = true, 2335 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2336 }, 2337 }; 2338 2339 static const CPUCaches epyc_rome_v3_cache_info = { 2340 .l1d_cache = &(CPUCacheInfo) { 2341 .type = DATA_CACHE, 2342 .level = 1, 2343 .size = 32 * KiB, 2344 .line_size = 64, 2345 .associativity = 8, 2346 .partitions = 1, 2347 .sets = 64, 2348 .lines_per_tag = 1, 2349 .self_init = 1, 2350 .no_invd_sharing = true, 2351 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2352 }, 2353 .l1i_cache = &(CPUCacheInfo) { 2354 .type = INSTRUCTION_CACHE, 2355 .level = 1, 2356 .size = 32 * KiB, 2357 .line_size = 64, 2358 .associativity = 8, 2359 .partitions = 1, 2360 .sets = 64, 2361 .lines_per_tag = 1, 2362 .self_init = 1, 2363 .no_invd_sharing = true, 2364 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2365 }, 2366 .l2_cache = &(CPUCacheInfo) { 2367 .type = UNIFIED_CACHE, 2368 .level = 2, 2369 .size = 512 * KiB, 2370 .line_size = 64, 2371 .associativity = 8, 2372 .partitions = 1, 2373 .sets = 1024, 2374 .lines_per_tag = 1, 2375 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2376 }, 2377 .l3_cache = &(CPUCacheInfo) { 2378 .type = UNIFIED_CACHE, 2379 .level = 3, 2380 .size = 16 * MiB, 2381 .line_size = 64, 2382 .associativity = 16, 2383 .partitions = 1, 2384 .sets = 16384, 2385 .lines_per_tag = 1, 2386 .self_init = true, 2387 .inclusive = true, 2388 .complex_indexing = false, 2389 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2390 }, 2391 }; 2392 2393 static const CPUCaches epyc_rome_v5_cache_info = { 2394 .l1d_cache = &(CPUCacheInfo) { 2395 .type = DATA_CACHE, 2396 .level = 1, 2397 .size = 32 * KiB, 2398 .line_size = 64, 2399 .associativity = 8, 2400 .partitions = 1, 2401 .sets = 64, 2402 .lines_per_tag = 1, 2403 .self_init = true, 2404 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2405 }, 2406 .l1i_cache = &(CPUCacheInfo) { 2407 .type = INSTRUCTION_CACHE, 2408 .level = 1, 2409 .size = 32 * KiB, 2410 .line_size = 64, 2411 .associativity = 8, 2412 .partitions = 1, 2413 .sets = 64, 2414 .lines_per_tag = 1, 2415 .self_init = true, 2416 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2417 }, 2418 .l2_cache = &(CPUCacheInfo) { 2419 .type = UNIFIED_CACHE, 2420 .level = 2, 2421 .size = 512 * KiB, 2422 .line_size = 64, 2423 .associativity = 8, 2424 .partitions = 1, 2425 .sets = 1024, 2426 .lines_per_tag = 1, 2427 .self_init = true, 2428 .inclusive = true, 2429 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2430 }, 2431 .l3_cache = &(CPUCacheInfo) { 2432 .type = UNIFIED_CACHE, 2433 .level = 3, 2434 .size = 16 * MiB, 2435 .line_size = 64, 2436 .associativity = 16, 2437 .partitions = 1, 2438 .sets = 16384, 2439 .lines_per_tag = 1, 2440 .self_init = true, 2441 .no_invd_sharing = true, 2442 .complex_indexing = false, 2443 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2444 }, 2445 }; 2446 2447 static const CPUCaches epyc_milan_cache_info = { 2448 .l1d_cache = &(CPUCacheInfo) { 2449 .type = DATA_CACHE, 2450 .level = 1, 2451 .size = 32 * KiB, 2452 .line_size = 64, 2453 .associativity = 8, 2454 .partitions = 1, 2455 .sets = 64, 2456 .lines_per_tag = 1, 2457 .self_init = 1, 2458 .no_invd_sharing = true, 2459 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2460 }, 2461 .l1i_cache = &(CPUCacheInfo) { 2462 .type = INSTRUCTION_CACHE, 2463 .level = 1, 2464 .size = 32 * KiB, 2465 .line_size = 64, 2466 .associativity = 8, 2467 .partitions = 1, 2468 .sets = 64, 2469 .lines_per_tag = 1, 2470 .self_init = 1, 2471 .no_invd_sharing = true, 2472 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2473 }, 2474 .l2_cache = &(CPUCacheInfo) { 2475 .type = UNIFIED_CACHE, 2476 .level = 2, 2477 .size = 512 * KiB, 2478 .line_size = 64, 2479 .associativity = 8, 2480 .partitions = 1, 2481 .sets = 1024, 2482 .lines_per_tag = 1, 2483 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2484 }, 2485 .l3_cache = &(CPUCacheInfo) { 2486 .type = UNIFIED_CACHE, 2487 .level = 3, 2488 .size = 32 * MiB, 2489 .line_size = 64, 2490 .associativity = 16, 2491 .partitions = 1, 2492 .sets = 32768, 2493 .lines_per_tag = 1, 2494 .self_init = true, 2495 .inclusive = true, 2496 .complex_indexing = true, 2497 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2498 }, 2499 }; 2500 2501 static const CPUCaches epyc_milan_v2_cache_info = { 2502 .l1d_cache = &(CPUCacheInfo) { 2503 .type = DATA_CACHE, 2504 .level = 1, 2505 .size = 32 * KiB, 2506 .line_size = 64, 2507 .associativity = 8, 2508 .partitions = 1, 2509 .sets = 64, 2510 .lines_per_tag = 1, 2511 .self_init = 1, 2512 .no_invd_sharing = true, 2513 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2514 }, 2515 .l1i_cache = &(CPUCacheInfo) { 2516 .type = INSTRUCTION_CACHE, 2517 .level = 1, 2518 .size = 32 * KiB, 2519 .line_size = 64, 2520 .associativity = 8, 2521 .partitions = 1, 2522 .sets = 64, 2523 .lines_per_tag = 1, 2524 .self_init = 1, 2525 .no_invd_sharing = true, 2526 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2527 }, 2528 .l2_cache = &(CPUCacheInfo) { 2529 .type = UNIFIED_CACHE, 2530 .level = 2, 2531 .size = 512 * KiB, 2532 .line_size = 64, 2533 .associativity = 8, 2534 .partitions = 1, 2535 .sets = 1024, 2536 .lines_per_tag = 1, 2537 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2538 }, 2539 .l3_cache = &(CPUCacheInfo) { 2540 .type = UNIFIED_CACHE, 2541 .level = 3, 2542 .size = 32 * MiB, 2543 .line_size = 64, 2544 .associativity = 16, 2545 .partitions = 1, 2546 .sets = 32768, 2547 .lines_per_tag = 1, 2548 .self_init = true, 2549 .inclusive = true, 2550 .complex_indexing = false, 2551 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2552 }, 2553 }; 2554 2555 static const CPUCaches epyc_milan_v3_cache_info = { 2556 .l1d_cache = &(CPUCacheInfo) { 2557 .type = DATA_CACHE, 2558 .level = 1, 2559 .size = 32 * KiB, 2560 .line_size = 64, 2561 .associativity = 8, 2562 .partitions = 1, 2563 .sets = 64, 2564 .lines_per_tag = 1, 2565 .self_init = true, 2566 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2567 }, 2568 .l1i_cache = &(CPUCacheInfo) { 2569 .type = INSTRUCTION_CACHE, 2570 .level = 1, 2571 .size = 32 * KiB, 2572 .line_size = 64, 2573 .associativity = 8, 2574 .partitions = 1, 2575 .sets = 64, 2576 .lines_per_tag = 1, 2577 .self_init = true, 2578 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2579 }, 2580 .l2_cache = &(CPUCacheInfo) { 2581 .type = UNIFIED_CACHE, 2582 .level = 2, 2583 .size = 512 * KiB, 2584 .line_size = 64, 2585 .associativity = 8, 2586 .partitions = 1, 2587 .sets = 1024, 2588 .lines_per_tag = 1, 2589 .self_init = true, 2590 .inclusive = true, 2591 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2592 }, 2593 .l3_cache = &(CPUCacheInfo) { 2594 .type = UNIFIED_CACHE, 2595 .level = 3, 2596 .size = 32 * MiB, 2597 .line_size = 64, 2598 .associativity = 16, 2599 .partitions = 1, 2600 .sets = 32768, 2601 .lines_per_tag = 1, 2602 .self_init = true, 2603 .no_invd_sharing = true, 2604 .complex_indexing = false, 2605 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2606 }, 2607 }; 2608 2609 static const CPUCaches epyc_genoa_cache_info = { 2610 .l1d_cache = &(CPUCacheInfo) { 2611 .type = DATA_CACHE, 2612 .level = 1, 2613 .size = 32 * KiB, 2614 .line_size = 64, 2615 .associativity = 8, 2616 .partitions = 1, 2617 .sets = 64, 2618 .lines_per_tag = 1, 2619 .self_init = 1, 2620 .no_invd_sharing = true, 2621 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2622 }, 2623 .l1i_cache = &(CPUCacheInfo) { 2624 .type = INSTRUCTION_CACHE, 2625 .level = 1, 2626 .size = 32 * KiB, 2627 .line_size = 64, 2628 .associativity = 8, 2629 .partitions = 1, 2630 .sets = 64, 2631 .lines_per_tag = 1, 2632 .self_init = 1, 2633 .no_invd_sharing = true, 2634 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2635 }, 2636 .l2_cache = &(CPUCacheInfo) { 2637 .type = UNIFIED_CACHE, 2638 .level = 2, 2639 .size = 1 * MiB, 2640 .line_size = 64, 2641 .associativity = 8, 2642 .partitions = 1, 2643 .sets = 2048, 2644 .lines_per_tag = 1, 2645 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2646 }, 2647 .l3_cache = &(CPUCacheInfo) { 2648 .type = UNIFIED_CACHE, 2649 .level = 3, 2650 .size = 32 * MiB, 2651 .line_size = 64, 2652 .associativity = 16, 2653 .partitions = 1, 2654 .sets = 32768, 2655 .lines_per_tag = 1, 2656 .self_init = true, 2657 .inclusive = true, 2658 .complex_indexing = false, 2659 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2660 }, 2661 }; 2662 2663 static const CPUCaches epyc_genoa_v2_cache_info = { 2664 .l1d_cache = &(CPUCacheInfo) { 2665 .type = DATA_CACHE, 2666 .level = 1, 2667 .size = 32 * KiB, 2668 .line_size = 64, 2669 .associativity = 8, 2670 .partitions = 1, 2671 .sets = 64, 2672 .lines_per_tag = 1, 2673 .self_init = true, 2674 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2675 }, 2676 .l1i_cache = &(CPUCacheInfo) { 2677 .type = INSTRUCTION_CACHE, 2678 .level = 1, 2679 .size = 32 * KiB, 2680 .line_size = 64, 2681 .associativity = 8, 2682 .partitions = 1, 2683 .sets = 64, 2684 .lines_per_tag = 1, 2685 .self_init = true, 2686 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2687 }, 2688 .l2_cache = &(CPUCacheInfo) { 2689 .type = UNIFIED_CACHE, 2690 .level = 2, 2691 .size = 1 * MiB, 2692 .line_size = 64, 2693 .associativity = 8, 2694 .partitions = 1, 2695 .sets = 2048, 2696 .lines_per_tag = 1, 2697 .self_init = true, 2698 .inclusive = true, 2699 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2700 }, 2701 .l3_cache = &(CPUCacheInfo) { 2702 .type = UNIFIED_CACHE, 2703 .level = 3, 2704 .size = 32 * MiB, 2705 .line_size = 64, 2706 .associativity = 16, 2707 .partitions = 1, 2708 .sets = 32768, 2709 .lines_per_tag = 1, 2710 .self_init = true, 2711 .no_invd_sharing = true, 2712 .complex_indexing = false, 2713 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2714 }, 2715 }; 2716 2717 static const CPUCaches epyc_turin_cache_info = { 2718 .l1d_cache = &(CPUCacheInfo) { 2719 .type = DATA_CACHE, 2720 .level = 1, 2721 .size = 48 * KiB, 2722 .line_size = 64, 2723 .associativity = 12, 2724 .partitions = 1, 2725 .sets = 64, 2726 .lines_per_tag = 1, 2727 .self_init = true, 2728 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2729 }, 2730 .l1i_cache = &(CPUCacheInfo) { 2731 .type = INSTRUCTION_CACHE, 2732 .level = 1, 2733 .size = 32 * KiB, 2734 .line_size = 64, 2735 .associativity = 8, 2736 .partitions = 1, 2737 .sets = 64, 2738 .lines_per_tag = 1, 2739 .self_init = true, 2740 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2741 }, 2742 .l2_cache = &(CPUCacheInfo) { 2743 .type = UNIFIED_CACHE, 2744 .level = 2, 2745 .size = 1 * MiB, 2746 .line_size = 64, 2747 .associativity = 16, 2748 .partitions = 1, 2749 .sets = 1024, 2750 .lines_per_tag = 1, 2751 .self_init = true, 2752 .inclusive = true, 2753 .share_level = CPU_TOPOLOGY_LEVEL_CORE, 2754 }, 2755 .l3_cache = &(CPUCacheInfo) { 2756 .type = UNIFIED_CACHE, 2757 .level = 3, 2758 .size = 32 * MiB, 2759 .line_size = 64, 2760 .associativity = 16, 2761 .partitions = 1, 2762 .sets = 32768, 2763 .lines_per_tag = 1, 2764 .self_init = true, 2765 .no_invd_sharing = true, 2766 .complex_indexing = false, 2767 .share_level = CPU_TOPOLOGY_LEVEL_DIE, 2768 }, 2769 }; 2770 2771 /* The following VMX features are not supported by KVM and are left out in the 2772 * CPU definitions: 2773 * 2774 * Dual-monitor support (all processors) 2775 * Entry to SMM 2776 * Deactivate dual-monitor treatment 2777 * Number of CR3-target values 2778 * Shutdown activity state 2779 * Wait-for-SIPI activity state 2780 * PAUSE-loop exiting (Westmere and newer) 2781 * EPT-violation #VE (Broadwell and newer) 2782 * Inject event with insn length=0 (Skylake and newer) 2783 * Conceal non-root operation from PT 2784 * Conceal VM exits from PT 2785 * Conceal VM entries from PT 2786 * Enable ENCLS exiting 2787 * Mode-based execute control (XS/XU) 2788 * TSC scaling (Skylake Server and newer) 2789 * GPA translation for PT (IceLake and newer) 2790 * User wait and pause 2791 * ENCLV exiting 2792 * Load IA32_RTIT_CTL 2793 * Clear IA32_RTIT_CTL 2794 * Advanced VM-exit information for EPT violations 2795 * Sub-page write permissions 2796 * PT in VMX operation 2797 */ 2798 2799 static const X86CPUDefinition builtin_x86_defs[] = { 2800 { 2801 .name = "qemu64", 2802 .level = 0xd, 2803 .vendor = CPUID_VENDOR_AMD, 2804 .family = 15, 2805 .model = 107, 2806 .stepping = 1, 2807 .features[FEAT_1_EDX] = 2808 PPRO_FEATURES | 2809 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2810 CPUID_PSE36, 2811 .features[FEAT_1_ECX] = 2812 CPUID_EXT_SSE3 | CPUID_EXT_CX16, 2813 .features[FEAT_8000_0001_EDX] = 2814 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2815 .features[FEAT_8000_0001_ECX] = 2816 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM, 2817 .xlevel = 0x8000000A, 2818 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 2819 }, 2820 { 2821 .name = "phenom", 2822 .level = 5, 2823 .vendor = CPUID_VENDOR_AMD, 2824 .family = 16, 2825 .model = 2, 2826 .stepping = 3, 2827 /* Missing: CPUID_HT */ 2828 .features[FEAT_1_EDX] = 2829 PPRO_FEATURES | 2830 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2831 CPUID_PSE36 | CPUID_VME, 2832 .features[FEAT_1_ECX] = 2833 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 | 2834 CPUID_EXT_POPCNT, 2835 .features[FEAT_8000_0001_EDX] = 2836 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | 2837 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT | 2838 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP, 2839 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, 2840 CPUID_EXT3_CR8LEG, 2841 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, 2842 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */ 2843 .features[FEAT_8000_0001_ECX] = 2844 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | 2845 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A, 2846 /* Missing: CPUID_SVM_LBRV */ 2847 .features[FEAT_SVM] = 2848 CPUID_SVM_NPT, 2849 .xlevel = 0x8000001A, 2850 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor" 2851 }, 2852 { 2853 .name = "core2duo", 2854 .level = 10, 2855 .vendor = CPUID_VENDOR_INTEL, 2856 .family = 6, 2857 .model = 15, 2858 .stepping = 11, 2859 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2860 .features[FEAT_1_EDX] = 2861 PPRO_FEATURES | 2862 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2863 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS, 2864 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST, 2865 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */ 2866 .features[FEAT_1_ECX] = 2867 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | 2868 CPUID_EXT_CX16, 2869 .features[FEAT_8000_0001_EDX] = 2870 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2871 .features[FEAT_8000_0001_ECX] = 2872 CPUID_EXT3_LAHF_LM, 2873 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2874 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2875 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2876 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2877 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2878 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2879 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2880 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2881 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2882 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2883 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2884 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2885 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2886 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2887 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2888 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2889 .features[FEAT_VMX_SECONDARY_CTLS] = 2890 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES, 2891 .xlevel = 0x80000008, 2892 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz", 2893 }, 2894 { 2895 .name = "kvm64", 2896 .level = 0xd, 2897 .vendor = CPUID_VENDOR_INTEL, 2898 .family = 15, 2899 .model = 6, 2900 .stepping = 1, 2901 /* Missing: CPUID_HT */ 2902 .features[FEAT_1_EDX] = 2903 PPRO_FEATURES | CPUID_VME | 2904 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 2905 CPUID_PSE36, 2906 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */ 2907 .features[FEAT_1_ECX] = 2908 CPUID_EXT_SSE3 | CPUID_EXT_CX16, 2909 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */ 2910 .features[FEAT_8000_0001_EDX] = 2911 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2912 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, 2913 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A, 2914 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, 2915 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */ 2916 .features[FEAT_8000_0001_ECX] = 2917 0, 2918 /* VMX features from Cedar Mill/Prescott */ 2919 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2920 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2921 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2922 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2923 VMX_PIN_BASED_NMI_EXITING, 2924 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2925 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2926 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2927 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2928 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2929 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2930 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2931 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING, 2932 .xlevel = 0x80000008, 2933 .model_id = "Common KVM processor" 2934 }, 2935 { 2936 .name = "qemu32", 2937 .level = 4, 2938 .vendor = CPUID_VENDOR_INTEL, 2939 .family = 6, 2940 .model = 6, 2941 .stepping = 3, 2942 .features[FEAT_1_EDX] = 2943 PPRO_FEATURES, 2944 .features[FEAT_1_ECX] = 2945 CPUID_EXT_SSE3, 2946 .xlevel = 0x80000004, 2947 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 2948 }, 2949 { 2950 .name = "kvm32", 2951 .level = 5, 2952 .vendor = CPUID_VENDOR_INTEL, 2953 .family = 15, 2954 .model = 6, 2955 .stepping = 1, 2956 .features[FEAT_1_EDX] = 2957 PPRO_FEATURES | CPUID_VME | 2958 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36, 2959 .features[FEAT_1_ECX] = 2960 CPUID_EXT_SSE3, 2961 .features[FEAT_8000_0001_ECX] = 2962 0, 2963 /* VMX features from Yonah */ 2964 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2965 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2966 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2967 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2968 VMX_PIN_BASED_NMI_EXITING, 2969 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2970 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2971 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2972 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2973 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 2974 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 2975 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS, 2976 .xlevel = 0x80000008, 2977 .model_id = "Common 32-bit KVM processor" 2978 }, 2979 { 2980 .name = "coreduo", 2981 .level = 10, 2982 .vendor = CPUID_VENDOR_INTEL, 2983 .family = 6, 2984 .model = 14, 2985 .stepping = 8, 2986 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2987 .features[FEAT_1_EDX] = 2988 PPRO_FEATURES | CPUID_VME | 2989 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI | 2990 CPUID_SS, 2991 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR, 2992 * CPUID_EXT_PDCM, CPUID_EXT_VMX */ 2993 .features[FEAT_1_ECX] = 2994 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR, 2995 .features[FEAT_8000_0001_EDX] = 2996 CPUID_EXT2_NX, 2997 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2998 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2999 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 3000 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3001 VMX_PIN_BASED_NMI_EXITING, 3002 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3003 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3004 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3005 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3006 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 3007 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 3008 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS, 3009 .xlevel = 0x80000008, 3010 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz", 3011 }, 3012 { 3013 .name = "486", 3014 .level = 1, 3015 .vendor = CPUID_VENDOR_INTEL, 3016 .family = 4, 3017 .model = 8, 3018 .stepping = 0, 3019 .features[FEAT_1_EDX] = 3020 I486_FEATURES, 3021 .xlevel = 0, 3022 .model_id = "", 3023 }, 3024 { 3025 .name = "pentium", 3026 .level = 1, 3027 .vendor = CPUID_VENDOR_INTEL, 3028 .family = 5, 3029 .model = 4, 3030 .stepping = 3, 3031 .features[FEAT_1_EDX] = 3032 PENTIUM_FEATURES, 3033 .xlevel = 0, 3034 .model_id = "", 3035 }, 3036 { 3037 .name = "pentium2", 3038 .level = 2, 3039 .vendor = CPUID_VENDOR_INTEL, 3040 .family = 6, 3041 .model = 5, 3042 .stepping = 2, 3043 .features[FEAT_1_EDX] = 3044 PENTIUM2_FEATURES, 3045 .xlevel = 0, 3046 .model_id = "", 3047 }, 3048 { 3049 .name = "pentium3", 3050 .level = 3, 3051 .vendor = CPUID_VENDOR_INTEL, 3052 .family = 6, 3053 .model = 7, 3054 .stepping = 3, 3055 .features[FEAT_1_EDX] = 3056 PENTIUM3_FEATURES, 3057 .xlevel = 0, 3058 .model_id = "", 3059 }, 3060 { 3061 .name = "athlon", 3062 .level = 2, 3063 .vendor = CPUID_VENDOR_AMD, 3064 .family = 6, 3065 .model = 2, 3066 .stepping = 3, 3067 .features[FEAT_1_EDX] = 3068 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR | 3069 CPUID_MCA, 3070 .features[FEAT_8000_0001_EDX] = 3071 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT, 3072 .xlevel = 0x80000008, 3073 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 3074 }, 3075 { 3076 .name = "n270", 3077 .level = 10, 3078 .vendor = CPUID_VENDOR_INTEL, 3079 .family = 6, 3080 .model = 28, 3081 .stepping = 2, 3082 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 3083 .features[FEAT_1_EDX] = 3084 PPRO_FEATURES | 3085 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | 3086 CPUID_ACPI | CPUID_SS, 3087 /* Some CPUs got no CPUID_SEP */ 3088 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2, 3089 * CPUID_EXT_XTPR */ 3090 .features[FEAT_1_ECX] = 3091 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | 3092 CPUID_EXT_MOVBE, 3093 .features[FEAT_8000_0001_EDX] = 3094 CPUID_EXT2_NX, 3095 .features[FEAT_8000_0001_ECX] = 3096 CPUID_EXT3_LAHF_LM, 3097 .xlevel = 0x80000008, 3098 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz", 3099 }, 3100 { 3101 .name = "Conroe", 3102 .level = 10, 3103 .vendor = CPUID_VENDOR_INTEL, 3104 .family = 6, 3105 .model = 15, 3106 .stepping = 3, 3107 .features[FEAT_1_EDX] = 3108 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3109 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3110 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3111 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3112 CPUID_DE | CPUID_FP87, 3113 .features[FEAT_1_ECX] = 3114 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, 3115 .features[FEAT_8000_0001_EDX] = 3116 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3117 .features[FEAT_8000_0001_ECX] = 3118 CPUID_EXT3_LAHF_LM, 3119 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 3120 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 3121 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 3122 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 3123 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3124 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 3125 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3126 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3127 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3128 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3129 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3130 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3131 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3132 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3133 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3134 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3135 .features[FEAT_VMX_SECONDARY_CTLS] = 3136 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES, 3137 .xlevel = 0x80000008, 3138 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)", 3139 }, 3140 { 3141 .name = "Penryn", 3142 .level = 10, 3143 .vendor = CPUID_VENDOR_INTEL, 3144 .family = 6, 3145 .model = 23, 3146 .stepping = 3, 3147 .features[FEAT_1_EDX] = 3148 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3149 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3150 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3151 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3152 CPUID_DE | CPUID_FP87, 3153 .features[FEAT_1_ECX] = 3154 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3155 CPUID_EXT_SSE3, 3156 .features[FEAT_8000_0001_EDX] = 3157 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3158 .features[FEAT_8000_0001_ECX] = 3159 CPUID_EXT3_LAHF_LM, 3160 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 3161 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3162 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, 3163 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT | 3164 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL, 3165 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 3166 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3167 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 3168 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3169 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3170 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3171 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3172 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3173 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3174 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3175 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3176 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3177 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3178 .features[FEAT_VMX_SECONDARY_CTLS] = 3179 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3180 VMX_SECONDARY_EXEC_WBINVD_EXITING, 3181 .xlevel = 0x80000008, 3182 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)", 3183 }, 3184 { 3185 .name = "Nehalem", 3186 .level = 11, 3187 .vendor = CPUID_VENDOR_INTEL, 3188 .family = 6, 3189 .model = 26, 3190 .stepping = 3, 3191 .features[FEAT_1_EDX] = 3192 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3193 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3194 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3195 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3196 CPUID_DE | CPUID_FP87, 3197 .features[FEAT_1_ECX] = 3198 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 3199 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, 3200 .features[FEAT_8000_0001_EDX] = 3201 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 3202 .features[FEAT_8000_0001_ECX] = 3203 CPUID_EXT3_LAHF_LM, 3204 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3205 MSR_VMX_BASIC_TRUE_CTLS, 3206 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3207 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3208 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3209 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3210 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3211 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3212 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3213 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3214 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3215 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 3216 .features[FEAT_VMX_EXIT_CTLS] = 3217 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3218 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3219 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3220 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3221 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3222 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 3223 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3224 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3225 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 3226 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3227 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3228 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3229 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3230 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3231 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3232 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3233 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3234 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3235 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3236 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3237 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3238 .features[FEAT_VMX_SECONDARY_CTLS] = 3239 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3240 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3241 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3242 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3243 VMX_SECONDARY_EXEC_ENABLE_VPID, 3244 .xlevel = 0x80000008, 3245 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)", 3246 .versions = (X86CPUVersionDefinition[]) { 3247 { .version = 1 }, 3248 { 3249 .version = 2, 3250 .alias = "Nehalem-IBRS", 3251 .props = (PropValue[]) { 3252 { "spec-ctrl", "on" }, 3253 { "model-id", 3254 "Intel Core i7 9xx (Nehalem Core i7, IBRS update)" }, 3255 { /* end of list */ } 3256 } 3257 }, 3258 { /* end of list */ } 3259 } 3260 }, 3261 { 3262 .name = "Westmere", 3263 .level = 11, 3264 .vendor = CPUID_VENDOR_INTEL, 3265 .family = 6, 3266 .model = 44, 3267 .stepping = 1, 3268 .features[FEAT_1_EDX] = 3269 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3270 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3271 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3272 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3273 CPUID_DE | CPUID_FP87, 3274 .features[FEAT_1_ECX] = 3275 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | 3276 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3277 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 3278 .features[FEAT_8000_0001_EDX] = 3279 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 3280 .features[FEAT_8000_0001_ECX] = 3281 CPUID_EXT3_LAHF_LM, 3282 .features[FEAT_6_EAX] = 3283 CPUID_6_EAX_ARAT, 3284 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3285 MSR_VMX_BASIC_TRUE_CTLS, 3286 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3287 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3288 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3289 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3290 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3291 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3292 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3293 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3294 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3295 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 3296 .features[FEAT_VMX_EXIT_CTLS] = 3297 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3298 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3299 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3300 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3301 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3302 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3303 MSR_VMX_MISC_STORE_LMA, 3304 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3305 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3306 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 3307 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3308 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3309 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3310 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3311 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3312 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3313 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3314 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3315 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3316 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3317 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3318 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3319 .features[FEAT_VMX_SECONDARY_CTLS] = 3320 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3321 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3322 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3323 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3324 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST, 3325 .xlevel = 0x80000008, 3326 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)", 3327 .versions = (X86CPUVersionDefinition[]) { 3328 { .version = 1 }, 3329 { 3330 .version = 2, 3331 .alias = "Westmere-IBRS", 3332 .props = (PropValue[]) { 3333 { "spec-ctrl", "on" }, 3334 { "model-id", 3335 "Westmere E56xx/L56xx/X56xx (IBRS update)" }, 3336 { /* end of list */ } 3337 } 3338 }, 3339 { /* end of list */ } 3340 } 3341 }, 3342 { 3343 .name = "SandyBridge", 3344 .level = 0xd, 3345 .vendor = CPUID_VENDOR_INTEL, 3346 .family = 6, 3347 .model = 42, 3348 .stepping = 1, 3349 .features[FEAT_1_EDX] = 3350 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3351 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3352 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3353 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3354 CPUID_DE | CPUID_FP87, 3355 .features[FEAT_1_ECX] = 3356 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3357 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | 3358 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 3359 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 3360 CPUID_EXT_SSE3, 3361 .features[FEAT_8000_0001_EDX] = 3362 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3363 CPUID_EXT2_SYSCALL, 3364 .features[FEAT_8000_0001_ECX] = 3365 CPUID_EXT3_LAHF_LM, 3366 .features[FEAT_XSAVE] = 3367 CPUID_XSAVE_XSAVEOPT, 3368 .features[FEAT_6_EAX] = 3369 CPUID_6_EAX_ARAT, 3370 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3371 MSR_VMX_BASIC_TRUE_CTLS, 3372 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3373 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3374 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3375 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3376 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3377 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3378 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3379 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3380 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3381 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 3382 .features[FEAT_VMX_EXIT_CTLS] = 3383 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3384 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3385 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3386 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3387 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3388 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3389 MSR_VMX_MISC_STORE_LMA, 3390 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3391 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3392 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 3393 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3394 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3395 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3396 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3397 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3398 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3399 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3400 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3401 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3402 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3403 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3404 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3405 .features[FEAT_VMX_SECONDARY_CTLS] = 3406 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3407 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3408 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3409 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3410 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST, 3411 .xlevel = 0x80000008, 3412 .model_id = "Intel Xeon E312xx (Sandy Bridge)", 3413 .versions = (X86CPUVersionDefinition[]) { 3414 { .version = 1 }, 3415 { 3416 .version = 2, 3417 .alias = "SandyBridge-IBRS", 3418 .props = (PropValue[]) { 3419 { "spec-ctrl", "on" }, 3420 { "model-id", 3421 "Intel Xeon E312xx (Sandy Bridge, IBRS update)" }, 3422 { /* end of list */ } 3423 } 3424 }, 3425 { /* end of list */ } 3426 } 3427 }, 3428 { 3429 .name = "IvyBridge", 3430 .level = 0xd, 3431 .vendor = CPUID_VENDOR_INTEL, 3432 .family = 6, 3433 .model = 58, 3434 .stepping = 9, 3435 .features[FEAT_1_EDX] = 3436 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3437 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3438 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3439 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3440 CPUID_DE | CPUID_FP87, 3441 .features[FEAT_1_ECX] = 3442 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3443 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | 3444 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 3445 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 3446 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3447 .features[FEAT_7_0_EBX] = 3448 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | 3449 CPUID_7_0_EBX_ERMS, 3450 .features[FEAT_8000_0001_EDX] = 3451 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3452 CPUID_EXT2_SYSCALL, 3453 .features[FEAT_8000_0001_ECX] = 3454 CPUID_EXT3_LAHF_LM, 3455 .features[FEAT_XSAVE] = 3456 CPUID_XSAVE_XSAVEOPT, 3457 .features[FEAT_6_EAX] = 3458 CPUID_6_EAX_ARAT, 3459 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3460 MSR_VMX_BASIC_TRUE_CTLS, 3461 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3462 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3463 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3464 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3465 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3466 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3467 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3468 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3469 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3470 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 3471 .features[FEAT_VMX_EXIT_CTLS] = 3472 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3473 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3474 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3475 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3476 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3477 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3478 MSR_VMX_MISC_STORE_LMA, 3479 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3480 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3481 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3482 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3483 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3484 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3485 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3486 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3487 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3488 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3489 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3490 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3491 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3492 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3493 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3494 .features[FEAT_VMX_SECONDARY_CTLS] = 3495 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3496 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3497 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3498 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3499 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3500 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3501 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3502 VMX_SECONDARY_EXEC_RDRAND_EXITING, 3503 .xlevel = 0x80000008, 3504 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)", 3505 .versions = (X86CPUVersionDefinition[]) { 3506 { .version = 1 }, 3507 { 3508 .version = 2, 3509 .alias = "IvyBridge-IBRS", 3510 .props = (PropValue[]) { 3511 { "spec-ctrl", "on" }, 3512 { "model-id", 3513 "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)" }, 3514 { /* end of list */ } 3515 } 3516 }, 3517 { /* end of list */ } 3518 } 3519 }, 3520 { 3521 .name = "Haswell", 3522 .level = 0xd, 3523 .vendor = CPUID_VENDOR_INTEL, 3524 .family = 6, 3525 .model = 60, 3526 .stepping = 4, 3527 .features[FEAT_1_EDX] = 3528 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3529 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3530 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3531 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3532 CPUID_DE | CPUID_FP87, 3533 .features[FEAT_1_ECX] = 3534 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3535 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3536 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3537 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3538 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3539 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3540 .features[FEAT_8000_0001_EDX] = 3541 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3542 CPUID_EXT2_SYSCALL, 3543 .features[FEAT_8000_0001_ECX] = 3544 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM, 3545 .features[FEAT_7_0_EBX] = 3546 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3547 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3548 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3549 CPUID_7_0_EBX_RTM, 3550 .features[FEAT_XSAVE] = 3551 CPUID_XSAVE_XSAVEOPT, 3552 .features[FEAT_6_EAX] = 3553 CPUID_6_EAX_ARAT, 3554 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3555 MSR_VMX_BASIC_TRUE_CTLS, 3556 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3557 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3558 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3559 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3560 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3561 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3562 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3563 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3564 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3565 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3566 .features[FEAT_VMX_EXIT_CTLS] = 3567 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3568 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3569 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3570 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3571 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3572 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3573 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3574 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3575 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3576 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3577 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3578 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3579 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3580 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3581 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3582 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3583 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3584 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3585 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3586 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3587 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3588 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3589 .features[FEAT_VMX_SECONDARY_CTLS] = 3590 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3591 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3592 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3593 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3594 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3595 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3596 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3597 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3598 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS, 3599 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3600 .xlevel = 0x80000008, 3601 .model_id = "Intel Core Processor (Haswell)", 3602 .versions = (X86CPUVersionDefinition[]) { 3603 { .version = 1 }, 3604 { 3605 .version = 2, 3606 .alias = "Haswell-noTSX", 3607 .props = (PropValue[]) { 3608 { "hle", "off" }, 3609 { "rtm", "off" }, 3610 { "stepping", "1" }, 3611 { "model-id", "Intel Core Processor (Haswell, no TSX)", }, 3612 { /* end of list */ } 3613 }, 3614 }, 3615 { 3616 .version = 3, 3617 .alias = "Haswell-IBRS", 3618 .props = (PropValue[]) { 3619 /* Restore TSX features removed by -v2 above */ 3620 { "hle", "on" }, 3621 { "rtm", "on" }, 3622 /* 3623 * Haswell and Haswell-IBRS had stepping=4 in 3624 * QEMU 4.0 and older 3625 */ 3626 { "stepping", "4" }, 3627 { "spec-ctrl", "on" }, 3628 { "model-id", 3629 "Intel Core Processor (Haswell, IBRS)" }, 3630 { /* end of list */ } 3631 } 3632 }, 3633 { 3634 .version = 4, 3635 .alias = "Haswell-noTSX-IBRS", 3636 .props = (PropValue[]) { 3637 { "hle", "off" }, 3638 { "rtm", "off" }, 3639 /* spec-ctrl was already enabled by -v3 above */ 3640 { "stepping", "1" }, 3641 { "model-id", 3642 "Intel Core Processor (Haswell, no TSX, IBRS)" }, 3643 { /* end of list */ } 3644 } 3645 }, 3646 { /* end of list */ } 3647 } 3648 }, 3649 { 3650 .name = "Broadwell", 3651 .level = 0xd, 3652 .vendor = CPUID_VENDOR_INTEL, 3653 .family = 6, 3654 .model = 61, 3655 .stepping = 2, 3656 .features[FEAT_1_EDX] = 3657 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3658 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3659 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3660 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3661 CPUID_DE | CPUID_FP87, 3662 .features[FEAT_1_ECX] = 3663 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3664 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3665 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3666 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3667 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3668 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3669 .features[FEAT_8000_0001_EDX] = 3670 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3671 CPUID_EXT2_SYSCALL, 3672 .features[FEAT_8000_0001_ECX] = 3673 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3674 .features[FEAT_7_0_EBX] = 3675 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3676 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3677 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3678 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3679 CPUID_7_0_EBX_SMAP, 3680 .features[FEAT_XSAVE] = 3681 CPUID_XSAVE_XSAVEOPT, 3682 .features[FEAT_6_EAX] = 3683 CPUID_6_EAX_ARAT, 3684 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3685 MSR_VMX_BASIC_TRUE_CTLS, 3686 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3687 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3688 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3689 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3690 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3691 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3692 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3693 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3694 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3695 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3696 .features[FEAT_VMX_EXIT_CTLS] = 3697 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3698 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3699 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3700 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3701 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3702 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3703 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3704 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3705 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3706 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3707 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3708 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3709 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3710 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3711 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3712 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3713 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3714 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3715 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3716 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3717 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3718 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3719 .features[FEAT_VMX_SECONDARY_CTLS] = 3720 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3721 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3722 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3723 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3724 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3725 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3726 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3727 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3728 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3729 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3730 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3731 .xlevel = 0x80000008, 3732 .model_id = "Intel Core Processor (Broadwell)", 3733 .versions = (X86CPUVersionDefinition[]) { 3734 { .version = 1 }, 3735 { 3736 .version = 2, 3737 .alias = "Broadwell-noTSX", 3738 .props = (PropValue[]) { 3739 { "hle", "off" }, 3740 { "rtm", "off" }, 3741 { "model-id", "Intel Core Processor (Broadwell, no TSX)", }, 3742 { /* end of list */ } 3743 }, 3744 }, 3745 { 3746 .version = 3, 3747 .alias = "Broadwell-IBRS", 3748 .props = (PropValue[]) { 3749 /* Restore TSX features removed by -v2 above */ 3750 { "hle", "on" }, 3751 { "rtm", "on" }, 3752 { "spec-ctrl", "on" }, 3753 { "model-id", 3754 "Intel Core Processor (Broadwell, IBRS)" }, 3755 { /* end of list */ } 3756 } 3757 }, 3758 { 3759 .version = 4, 3760 .alias = "Broadwell-noTSX-IBRS", 3761 .props = (PropValue[]) { 3762 { "hle", "off" }, 3763 { "rtm", "off" }, 3764 /* spec-ctrl was already enabled by -v3 above */ 3765 { "model-id", 3766 "Intel Core Processor (Broadwell, no TSX, IBRS)" }, 3767 { /* end of list */ } 3768 } 3769 }, 3770 { /* end of list */ } 3771 } 3772 }, 3773 { 3774 .name = "Skylake-Client", 3775 .level = 0xd, 3776 .vendor = CPUID_VENDOR_INTEL, 3777 .family = 6, 3778 .model = 94, 3779 .stepping = 3, 3780 .features[FEAT_1_EDX] = 3781 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3782 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3783 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3784 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3785 CPUID_DE | CPUID_FP87, 3786 .features[FEAT_1_ECX] = 3787 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3788 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3789 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3790 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3791 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3792 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3793 .features[FEAT_8000_0001_EDX] = 3794 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 3795 CPUID_EXT2_SYSCALL, 3796 .features[FEAT_8000_0001_ECX] = 3797 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3798 .features[FEAT_7_0_EBX] = 3799 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3800 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3801 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3802 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3803 CPUID_7_0_EBX_SMAP, 3804 /* XSAVES is added in version 4 */ 3805 .features[FEAT_XSAVE] = 3806 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3807 CPUID_XSAVE_XGETBV1, 3808 .features[FEAT_6_EAX] = 3809 CPUID_6_EAX_ARAT, 3810 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3811 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3812 MSR_VMX_BASIC_TRUE_CTLS, 3813 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3814 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3815 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3816 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3817 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3818 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3819 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3820 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3821 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3822 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3823 .features[FEAT_VMX_EXIT_CTLS] = 3824 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3825 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3826 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3827 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3828 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3829 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3830 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3831 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3832 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3833 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 3834 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3835 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3836 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3837 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3838 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3839 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3840 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3841 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3842 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3843 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3844 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3845 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3846 .features[FEAT_VMX_SECONDARY_CTLS] = 3847 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3848 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3849 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3850 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3851 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3852 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3853 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3854 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3855 .xlevel = 0x80000008, 3856 .model_id = "Intel Core Processor (Skylake)", 3857 .versions = (X86CPUVersionDefinition[]) { 3858 { .version = 1 }, 3859 { 3860 .version = 2, 3861 .alias = "Skylake-Client-IBRS", 3862 .props = (PropValue[]) { 3863 { "spec-ctrl", "on" }, 3864 { "model-id", 3865 "Intel Core Processor (Skylake, IBRS)" }, 3866 { /* end of list */ } 3867 } 3868 }, 3869 { 3870 .version = 3, 3871 .alias = "Skylake-Client-noTSX-IBRS", 3872 .props = (PropValue[]) { 3873 { "hle", "off" }, 3874 { "rtm", "off" }, 3875 { "model-id", 3876 "Intel Core Processor (Skylake, IBRS, no TSX)" }, 3877 { /* end of list */ } 3878 } 3879 }, 3880 { 3881 .version = 4, 3882 .note = "IBRS, XSAVES, no TSX", 3883 .props = (PropValue[]) { 3884 { "xsaves", "on" }, 3885 { "vmx-xsaves", "on" }, 3886 { /* end of list */ } 3887 } 3888 }, 3889 { /* end of list */ } 3890 } 3891 }, 3892 { 3893 .name = "Skylake-Server", 3894 .level = 0xd, 3895 .vendor = CPUID_VENDOR_INTEL, 3896 .family = 6, 3897 .model = 85, 3898 .stepping = 4, 3899 .features[FEAT_1_EDX] = 3900 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3901 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3902 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3903 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3904 CPUID_DE | CPUID_FP87, 3905 .features[FEAT_1_ECX] = 3906 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3907 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3908 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3909 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3910 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3911 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3912 .features[FEAT_8000_0001_EDX] = 3913 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3914 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3915 .features[FEAT_8000_0001_ECX] = 3916 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3917 .features[FEAT_7_0_EBX] = 3918 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3919 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3920 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3921 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3922 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3923 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3924 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3925 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3926 .features[FEAT_7_0_ECX] = 3927 CPUID_7_0_ECX_PKU, 3928 /* XSAVES is added in version 5 */ 3929 .features[FEAT_XSAVE] = 3930 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3931 CPUID_XSAVE_XGETBV1, 3932 .features[FEAT_6_EAX] = 3933 CPUID_6_EAX_ARAT, 3934 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3935 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3936 MSR_VMX_BASIC_TRUE_CTLS, 3937 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3938 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3939 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3940 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3941 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3942 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3943 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3944 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3945 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3946 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3947 .features[FEAT_VMX_EXIT_CTLS] = 3948 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3949 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3950 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3951 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3952 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3953 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3954 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3955 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3956 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3957 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3958 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3959 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3960 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3961 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3962 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3963 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3964 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3965 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3966 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3967 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3968 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3969 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3970 .features[FEAT_VMX_SECONDARY_CTLS] = 3971 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3972 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3973 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3974 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3975 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3976 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3977 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3978 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3979 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3980 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3981 .xlevel = 0x80000008, 3982 .model_id = "Intel Xeon Processor (Skylake)", 3983 .versions = (X86CPUVersionDefinition[]) { 3984 { .version = 1 }, 3985 { 3986 .version = 2, 3987 .alias = "Skylake-Server-IBRS", 3988 .props = (PropValue[]) { 3989 /* clflushopt was not added to Skylake-Server-IBRS */ 3990 /* TODO: add -v3 including clflushopt */ 3991 { "clflushopt", "off" }, 3992 { "spec-ctrl", "on" }, 3993 { "model-id", 3994 "Intel Xeon Processor (Skylake, IBRS)" }, 3995 { /* end of list */ } 3996 } 3997 }, 3998 { 3999 .version = 3, 4000 .alias = "Skylake-Server-noTSX-IBRS", 4001 .props = (PropValue[]) { 4002 { "hle", "off" }, 4003 { "rtm", "off" }, 4004 { "model-id", 4005 "Intel Xeon Processor (Skylake, IBRS, no TSX)" }, 4006 { /* end of list */ } 4007 } 4008 }, 4009 { 4010 .version = 4, 4011 .note = "IBRS, EPT switching, no TSX", 4012 .props = (PropValue[]) { 4013 { "vmx-eptp-switching", "on" }, 4014 { /* end of list */ } 4015 } 4016 }, 4017 { 4018 .version = 5, 4019 .note = "IBRS, XSAVES, EPT switching, no TSX", 4020 .props = (PropValue[]) { 4021 { "xsaves", "on" }, 4022 { "vmx-xsaves", "on" }, 4023 { /* end of list */ } 4024 } 4025 }, 4026 { /* end of list */ } 4027 } 4028 }, 4029 { 4030 .name = "Cascadelake-Server", 4031 .level = 0xd, 4032 .vendor = CPUID_VENDOR_INTEL, 4033 .family = 6, 4034 .model = 85, 4035 .stepping = 6, 4036 .features[FEAT_1_EDX] = 4037 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4038 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4039 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4040 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4041 CPUID_DE | CPUID_FP87, 4042 .features[FEAT_1_ECX] = 4043 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 4044 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 4045 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 4046 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 4047 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 4048 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4049 .features[FEAT_8000_0001_EDX] = 4050 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 4051 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 4052 .features[FEAT_8000_0001_ECX] = 4053 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 4054 .features[FEAT_7_0_EBX] = 4055 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 4056 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 4057 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 4058 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 4059 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 4060 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 4061 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 4062 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 4063 .features[FEAT_7_0_ECX] = 4064 CPUID_7_0_ECX_PKU | 4065 CPUID_7_0_ECX_AVX512VNNI, 4066 .features[FEAT_7_0_EDX] = 4067 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4068 /* XSAVES is added in version 5 */ 4069 .features[FEAT_XSAVE] = 4070 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4071 CPUID_XSAVE_XGETBV1, 4072 .features[FEAT_6_EAX] = 4073 CPUID_6_EAX_ARAT, 4074 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 4075 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 4076 MSR_VMX_BASIC_TRUE_CTLS, 4077 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 4078 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 4079 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 4080 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 4081 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 4082 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 4083 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4084 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4085 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4086 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 4087 .features[FEAT_VMX_EXIT_CTLS] = 4088 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4089 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4090 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 4091 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4092 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4093 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 4094 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 4095 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 4096 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 4097 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 4098 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4099 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4100 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4101 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4102 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4103 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 4104 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 4105 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 4106 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 4107 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4108 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4109 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4110 .features[FEAT_VMX_SECONDARY_CTLS] = 4111 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4112 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 4113 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 4114 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4115 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4116 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4117 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4118 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4119 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4120 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 4121 .xlevel = 0x80000008, 4122 .model_id = "Intel Xeon Processor (Cascadelake)", 4123 .versions = (X86CPUVersionDefinition[]) { 4124 { .version = 1 }, 4125 { .version = 2, 4126 .note = "ARCH_CAPABILITIES", 4127 .props = (PropValue[]) { 4128 { "arch-capabilities", "on" }, 4129 { "rdctl-no", "on" }, 4130 { "ibrs-all", "on" }, 4131 { "skip-l1dfl-vmentry", "on" }, 4132 { "mds-no", "on" }, 4133 { /* end of list */ } 4134 }, 4135 }, 4136 { .version = 3, 4137 .alias = "Cascadelake-Server-noTSX", 4138 .note = "ARCH_CAPABILITIES, no TSX", 4139 .props = (PropValue[]) { 4140 { "hle", "off" }, 4141 { "rtm", "off" }, 4142 { /* end of list */ } 4143 }, 4144 }, 4145 { .version = 4, 4146 .note = "ARCH_CAPABILITIES, EPT switching, no TSX", 4147 .props = (PropValue[]) { 4148 { "vmx-eptp-switching", "on" }, 4149 { /* end of list */ } 4150 }, 4151 }, 4152 { .version = 5, 4153 .note = "ARCH_CAPABILITIES, EPT switching, XSAVES, no TSX", 4154 .props = (PropValue[]) { 4155 { "xsaves", "on" }, 4156 { "vmx-xsaves", "on" }, 4157 { /* end of list */ } 4158 }, 4159 }, 4160 { /* end of list */ } 4161 } 4162 }, 4163 { 4164 .name = "Cooperlake", 4165 .level = 0xd, 4166 .vendor = CPUID_VENDOR_INTEL, 4167 .family = 6, 4168 .model = 85, 4169 .stepping = 10, 4170 .features[FEAT_1_EDX] = 4171 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4172 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4173 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4174 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4175 CPUID_DE | CPUID_FP87, 4176 .features[FEAT_1_ECX] = 4177 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 4178 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 4179 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 4180 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 4181 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 4182 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4183 .features[FEAT_8000_0001_EDX] = 4184 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 4185 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 4186 .features[FEAT_8000_0001_ECX] = 4187 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 4188 .features[FEAT_7_0_EBX] = 4189 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 4190 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 4191 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 4192 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 4193 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 4194 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 4195 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 4196 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 4197 .features[FEAT_7_0_ECX] = 4198 CPUID_7_0_ECX_PKU | 4199 CPUID_7_0_ECX_AVX512VNNI, 4200 .features[FEAT_7_0_EDX] = 4201 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_STIBP | 4202 CPUID_7_0_EDX_SPEC_CTRL_SSBD | CPUID_7_0_EDX_ARCH_CAPABILITIES, 4203 .features[FEAT_ARCH_CAPABILITIES] = 4204 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 4205 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 4206 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO, 4207 .features[FEAT_7_1_EAX] = 4208 CPUID_7_1_EAX_AVX512_BF16, 4209 /* XSAVES is added in version 2 */ 4210 .features[FEAT_XSAVE] = 4211 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4212 CPUID_XSAVE_XGETBV1, 4213 .features[FEAT_6_EAX] = 4214 CPUID_6_EAX_ARAT, 4215 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 4216 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 4217 MSR_VMX_BASIC_TRUE_CTLS, 4218 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 4219 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 4220 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 4221 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 4222 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 4223 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 4224 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4225 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4226 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4227 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 4228 .features[FEAT_VMX_EXIT_CTLS] = 4229 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4230 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4231 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 4232 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4233 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4234 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 4235 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 4236 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 4237 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 4238 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 4239 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4240 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4241 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4242 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4243 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4244 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 4245 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 4246 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 4247 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 4248 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4249 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4250 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4251 .features[FEAT_VMX_SECONDARY_CTLS] = 4252 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4253 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 4254 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 4255 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4256 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4257 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4258 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4259 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4260 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4261 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 4262 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 4263 .xlevel = 0x80000008, 4264 .model_id = "Intel Xeon Processor (Cooperlake)", 4265 .versions = (X86CPUVersionDefinition[]) { 4266 { .version = 1 }, 4267 { .version = 2, 4268 .note = "XSAVES", 4269 .props = (PropValue[]) { 4270 { "xsaves", "on" }, 4271 { "vmx-xsaves", "on" }, 4272 { /* end of list */ } 4273 }, 4274 }, 4275 { /* end of list */ } 4276 } 4277 }, 4278 { 4279 .name = "Icelake-Server", 4280 .level = 0xd, 4281 .vendor = CPUID_VENDOR_INTEL, 4282 .family = 6, 4283 .model = 134, 4284 .stepping = 0, 4285 .features[FEAT_1_EDX] = 4286 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 4287 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 4288 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 4289 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 4290 CPUID_DE | CPUID_FP87, 4291 .features[FEAT_1_ECX] = 4292 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 4293 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 4294 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 4295 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 4296 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 4297 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4298 .features[FEAT_8000_0001_EDX] = 4299 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 4300 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 4301 .features[FEAT_8000_0001_ECX] = 4302 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 4303 .features[FEAT_8000_0008_EBX] = 4304 CPUID_8000_0008_EBX_WBNOINVD, 4305 .features[FEAT_7_0_EBX] = 4306 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 4307 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 4308 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 4309 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 4310 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 4311 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 4312 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 4313 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 4314 .features[FEAT_7_0_ECX] = 4315 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 4316 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 4317 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4318 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 4319 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57, 4320 .features[FEAT_7_0_EDX] = 4321 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4322 /* XSAVES is added in version 5 */ 4323 .features[FEAT_XSAVE] = 4324 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4325 CPUID_XSAVE_XGETBV1, 4326 .features[FEAT_6_EAX] = 4327 CPUID_6_EAX_ARAT, 4328 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 4329 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 4330 MSR_VMX_BASIC_TRUE_CTLS, 4331 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 4332 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 4333 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 4334 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 4335 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 4336 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 4337 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4338 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4339 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4340 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 4341 .features[FEAT_VMX_EXIT_CTLS] = 4342 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4343 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4344 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 4345 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4346 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4347 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 4348 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 4349 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 4350 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 4351 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 4352 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4353 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4354 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4355 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4356 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4357 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 4358 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 4359 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 4360 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 4361 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4362 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4363 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4364 .features[FEAT_VMX_SECONDARY_CTLS] = 4365 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4366 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 4367 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 4368 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4369 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4370 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4371 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4372 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4373 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS, 4374 .xlevel = 0x80000008, 4375 .model_id = "Intel Xeon Processor (Icelake)", 4376 .versions = (X86CPUVersionDefinition[]) { 4377 { .version = 1 }, 4378 { 4379 .version = 2, 4380 .note = "no TSX", 4381 .alias = "Icelake-Server-noTSX", 4382 .props = (PropValue[]) { 4383 { "hle", "off" }, 4384 { "rtm", "off" }, 4385 { /* end of list */ } 4386 }, 4387 }, 4388 { 4389 .version = 3, 4390 .props = (PropValue[]) { 4391 { "arch-capabilities", "on" }, 4392 { "rdctl-no", "on" }, 4393 { "ibrs-all", "on" }, 4394 { "skip-l1dfl-vmentry", "on" }, 4395 { "mds-no", "on" }, 4396 { "pschange-mc-no", "on" }, 4397 { "taa-no", "on" }, 4398 { /* end of list */ } 4399 }, 4400 }, 4401 { 4402 .version = 4, 4403 .props = (PropValue[]) { 4404 { "sha-ni", "on" }, 4405 { "avx512ifma", "on" }, 4406 { "rdpid", "on" }, 4407 { "fsrm", "on" }, 4408 { "vmx-rdseed-exit", "on" }, 4409 { "vmx-pml", "on" }, 4410 { "vmx-eptp-switching", "on" }, 4411 { "model", "106" }, 4412 { /* end of list */ } 4413 }, 4414 }, 4415 { 4416 .version = 5, 4417 .note = "XSAVES", 4418 .props = (PropValue[]) { 4419 { "xsaves", "on" }, 4420 { "vmx-xsaves", "on" }, 4421 { /* end of list */ } 4422 }, 4423 }, 4424 { 4425 .version = 6, 4426 .note = "5-level EPT", 4427 .props = (PropValue[]) { 4428 { "vmx-page-walk-5", "on" }, 4429 { /* end of list */ } 4430 }, 4431 }, 4432 { 4433 .version = 7, 4434 .note = "TSX, taa-no", 4435 .props = (PropValue[]) { 4436 /* Restore TSX features removed by -v2 above */ 4437 { "hle", "on" }, 4438 { "rtm", "on" }, 4439 { /* end of list */ } 4440 }, 4441 }, 4442 { /* end of list */ } 4443 } 4444 }, 4445 { 4446 .name = "SapphireRapids", 4447 .level = 0x20, 4448 .vendor = CPUID_VENDOR_INTEL, 4449 .family = 6, 4450 .model = 143, 4451 .stepping = 4, 4452 /* 4453 * please keep the ascending order so that we can have a clear view of 4454 * bit position of each feature. 4455 */ 4456 .features[FEAT_1_EDX] = 4457 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4458 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4459 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4460 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4461 CPUID_SSE | CPUID_SSE2, 4462 .features[FEAT_1_ECX] = 4463 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 4464 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 4465 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4466 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 4467 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4468 .features[FEAT_8000_0001_EDX] = 4469 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4470 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4471 .features[FEAT_8000_0001_ECX] = 4472 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 4473 .features[FEAT_8000_0008_EBX] = 4474 CPUID_8000_0008_EBX_WBNOINVD, 4475 .features[FEAT_7_0_EBX] = 4476 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_HLE | 4477 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | 4478 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RTM | 4479 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 4480 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | 4481 CPUID_7_0_EBX_AVX512IFMA | CPUID_7_0_EBX_CLFLUSHOPT | 4482 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | 4483 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, 4484 .features[FEAT_7_0_ECX] = 4485 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 4486 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 4487 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4488 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 4489 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | 4490 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT, 4491 .features[FEAT_7_0_EDX] = 4492 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 4493 CPUID_7_0_EDX_TSX_LDTRK | CPUID_7_0_EDX_AMX_BF16 | 4494 CPUID_7_0_EDX_AVX512_FP16 | CPUID_7_0_EDX_AMX_TILE | 4495 CPUID_7_0_EDX_AMX_INT8 | CPUID_7_0_EDX_SPEC_CTRL | 4496 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4497 .features[FEAT_ARCH_CAPABILITIES] = 4498 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 4499 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 4500 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO, 4501 .features[FEAT_XSAVE] = 4502 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4503 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES | CPUID_D_1_EAX_XFD, 4504 .features[FEAT_6_EAX] = 4505 CPUID_6_EAX_ARAT, 4506 .features[FEAT_7_1_EAX] = 4507 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_AVX512_BF16 | 4508 CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC, 4509 .features[FEAT_VMX_BASIC] = 4510 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 4511 .features[FEAT_VMX_ENTRY_CTLS] = 4512 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 4513 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 4514 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 4515 .features[FEAT_VMX_EPT_VPID_CAPS] = 4516 MSR_VMX_EPT_EXECONLY | 4517 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_PAGE_WALK_LENGTH_5 | 4518 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 4519 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 4520 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4521 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4522 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 4523 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4524 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 4525 .features[FEAT_VMX_EXIT_CTLS] = 4526 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4527 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4528 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 4529 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4530 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4531 .features[FEAT_VMX_MISC] = 4532 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 4533 MSR_VMX_MISC_VMWRITE_VMEXIT, 4534 .features[FEAT_VMX_PINBASED_CTLS] = 4535 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 4536 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 4537 VMX_PIN_BASED_POSTED_INTR, 4538 .features[FEAT_VMX_PROCBASED_CTLS] = 4539 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4540 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4541 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4542 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4543 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4544 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4545 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 4546 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 4547 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4548 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 4549 VMX_CPU_BASED_PAUSE_EXITING | 4550 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4551 .features[FEAT_VMX_SECONDARY_CTLS] = 4552 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4553 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 4554 VMX_SECONDARY_EXEC_RDTSCP | 4555 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4556 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 4557 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4558 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4559 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4560 VMX_SECONDARY_EXEC_RDRAND_EXITING | 4561 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4562 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4563 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 4564 VMX_SECONDARY_EXEC_XSAVES, 4565 .features[FEAT_VMX_VMFUNC] = 4566 MSR_VMX_VMFUNC_EPT_SWITCHING, 4567 .xlevel = 0x80000008, 4568 .model_id = "Intel Xeon Processor (SapphireRapids)", 4569 .versions = (X86CPUVersionDefinition[]) { 4570 { .version = 1 }, 4571 { 4572 .version = 2, 4573 .props = (PropValue[]) { 4574 { "sbdr-ssdp-no", "on" }, 4575 { "fbsdp-no", "on" }, 4576 { "psdp-no", "on" }, 4577 { /* end of list */ } 4578 } 4579 }, 4580 { 4581 .version = 3, 4582 .props = (PropValue[]) { 4583 { "ss", "on" }, 4584 { "tsc-adjust", "on" }, 4585 { "cldemote", "on" }, 4586 { "movdiri", "on" }, 4587 { "movdir64b", "on" }, 4588 { /* end of list */ } 4589 } 4590 }, 4591 { /* end of list */ } 4592 } 4593 }, 4594 { 4595 .name = "GraniteRapids", 4596 .level = 0x20, 4597 .vendor = CPUID_VENDOR_INTEL, 4598 .family = 6, 4599 .model = 173, 4600 .stepping = 0, 4601 /* 4602 * please keep the ascending order so that we can have a clear view of 4603 * bit position of each feature. 4604 */ 4605 .features[FEAT_1_EDX] = 4606 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4607 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4608 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4609 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4610 CPUID_SSE | CPUID_SSE2, 4611 .features[FEAT_1_ECX] = 4612 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 4613 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 4614 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4615 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 4616 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4617 .features[FEAT_8000_0001_EDX] = 4618 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4619 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4620 .features[FEAT_8000_0001_ECX] = 4621 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 4622 .features[FEAT_8000_0008_EBX] = 4623 CPUID_8000_0008_EBX_WBNOINVD, 4624 .features[FEAT_7_0_EBX] = 4625 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_HLE | 4626 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | 4627 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RTM | 4628 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 4629 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | 4630 CPUID_7_0_EBX_AVX512IFMA | CPUID_7_0_EBX_CLFLUSHOPT | 4631 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | 4632 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, 4633 .features[FEAT_7_0_ECX] = 4634 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 4635 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 4636 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4637 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 4638 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | 4639 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT, 4640 .features[FEAT_7_0_EDX] = 4641 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 4642 CPUID_7_0_EDX_TSX_LDTRK | CPUID_7_0_EDX_AMX_BF16 | 4643 CPUID_7_0_EDX_AVX512_FP16 | CPUID_7_0_EDX_AMX_TILE | 4644 CPUID_7_0_EDX_AMX_INT8 | CPUID_7_0_EDX_SPEC_CTRL | 4645 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4646 .features[FEAT_ARCH_CAPABILITIES] = 4647 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 4648 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 4649 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO | 4650 MSR_ARCH_CAP_SBDR_SSDP_NO | MSR_ARCH_CAP_FBSDP_NO | 4651 MSR_ARCH_CAP_PSDP_NO | MSR_ARCH_CAP_PBRSB_NO, 4652 .features[FEAT_XSAVE] = 4653 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4654 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES | CPUID_D_1_EAX_XFD, 4655 .features[FEAT_6_EAX] = 4656 CPUID_6_EAX_ARAT, 4657 .features[FEAT_7_1_EAX] = 4658 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_AVX512_BF16 | 4659 CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC | 4660 CPUID_7_1_EAX_AMX_FP16, 4661 .features[FEAT_7_1_EDX] = 4662 CPUID_7_1_EDX_PREFETCHITI, 4663 .features[FEAT_7_2_EDX] = 4664 CPUID_7_2_EDX_MCDT_NO, 4665 .features[FEAT_VMX_BASIC] = 4666 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 4667 .features[FEAT_VMX_ENTRY_CTLS] = 4668 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 4669 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 4670 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 4671 .features[FEAT_VMX_EPT_VPID_CAPS] = 4672 MSR_VMX_EPT_EXECONLY | 4673 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_PAGE_WALK_LENGTH_5 | 4674 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 4675 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 4676 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4677 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4678 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 4679 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4680 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 4681 .features[FEAT_VMX_EXIT_CTLS] = 4682 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4683 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4684 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 4685 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4686 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4687 .features[FEAT_VMX_MISC] = 4688 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 4689 MSR_VMX_MISC_VMWRITE_VMEXIT, 4690 .features[FEAT_VMX_PINBASED_CTLS] = 4691 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 4692 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 4693 VMX_PIN_BASED_POSTED_INTR, 4694 .features[FEAT_VMX_PROCBASED_CTLS] = 4695 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4696 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4697 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4698 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4699 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4700 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4701 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 4702 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 4703 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4704 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 4705 VMX_CPU_BASED_PAUSE_EXITING | 4706 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4707 .features[FEAT_VMX_SECONDARY_CTLS] = 4708 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4709 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 4710 VMX_SECONDARY_EXEC_RDTSCP | 4711 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4712 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 4713 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4714 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4715 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4716 VMX_SECONDARY_EXEC_RDRAND_EXITING | 4717 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4718 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4719 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 4720 VMX_SECONDARY_EXEC_XSAVES, 4721 .features[FEAT_VMX_VMFUNC] = 4722 MSR_VMX_VMFUNC_EPT_SWITCHING, 4723 .xlevel = 0x80000008, 4724 .model_id = "Intel Xeon Processor (GraniteRapids)", 4725 .versions = (X86CPUVersionDefinition[]) { 4726 { .version = 1 }, 4727 { 4728 .version = 2, 4729 .props = (PropValue[]) { 4730 { "ss", "on" }, 4731 { "tsc-adjust", "on" }, 4732 { "cldemote", "on" }, 4733 { "movdiri", "on" }, 4734 { "movdir64b", "on" }, 4735 { "avx10", "on" }, 4736 { "avx10-128", "on" }, 4737 { "avx10-256", "on" }, 4738 { "avx10-512", "on" }, 4739 { "avx10-version", "1" }, 4740 { "stepping", "1" }, 4741 { /* end of list */ } 4742 } 4743 }, 4744 { /* end of list */ }, 4745 }, 4746 }, 4747 { 4748 .name = "SierraForest", 4749 .level = 0x23, 4750 .vendor = CPUID_VENDOR_INTEL, 4751 .family = 6, 4752 .model = 175, 4753 .stepping = 0, 4754 /* 4755 * please keep the ascending order so that we can have a clear view of 4756 * bit position of each feature. 4757 */ 4758 .features[FEAT_1_EDX] = 4759 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4760 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4761 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4762 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4763 CPUID_SSE | CPUID_SSE2, 4764 .features[FEAT_1_ECX] = 4765 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 4766 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 4767 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4768 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 4769 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4770 .features[FEAT_8000_0001_EDX] = 4771 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4772 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4773 .features[FEAT_8000_0001_ECX] = 4774 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 4775 .features[FEAT_8000_0008_EBX] = 4776 CPUID_8000_0008_EBX_WBNOINVD, 4777 .features[FEAT_7_0_EBX] = 4778 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4779 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 4780 CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 4781 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB | 4782 CPUID_7_0_EBX_SHA_NI, 4783 .features[FEAT_7_0_ECX] = 4784 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_GFNI | 4785 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4786 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT, 4787 .features[FEAT_7_0_EDX] = 4788 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 4789 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES | 4790 CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4791 .features[FEAT_ARCH_CAPABILITIES] = 4792 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 4793 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 4794 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_SBDR_SSDP_NO | 4795 MSR_ARCH_CAP_FBSDP_NO | MSR_ARCH_CAP_PSDP_NO | 4796 MSR_ARCH_CAP_PBRSB_NO, 4797 .features[FEAT_XSAVE] = 4798 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4799 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 4800 .features[FEAT_6_EAX] = 4801 CPUID_6_EAX_ARAT, 4802 .features[FEAT_7_1_EAX] = 4803 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_CMPCCXADD | 4804 CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_AVX_IFMA, 4805 .features[FEAT_7_1_EDX] = 4806 CPUID_7_1_EDX_AVX_VNNI_INT8 | CPUID_7_1_EDX_AVX_NE_CONVERT, 4807 .features[FEAT_7_2_EDX] = 4808 CPUID_7_2_EDX_MCDT_NO, 4809 .features[FEAT_VMX_BASIC] = 4810 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 4811 .features[FEAT_VMX_ENTRY_CTLS] = 4812 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 4813 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 4814 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 4815 .features[FEAT_VMX_EPT_VPID_CAPS] = 4816 MSR_VMX_EPT_EXECONLY | MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | 4817 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 4818 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 4819 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4820 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4821 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 4822 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4823 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 4824 .features[FEAT_VMX_EXIT_CTLS] = 4825 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4826 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4827 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 4828 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4829 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4830 .features[FEAT_VMX_MISC] = 4831 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 4832 MSR_VMX_MISC_VMWRITE_VMEXIT, 4833 .features[FEAT_VMX_PINBASED_CTLS] = 4834 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 4835 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 4836 VMX_PIN_BASED_POSTED_INTR, 4837 .features[FEAT_VMX_PROCBASED_CTLS] = 4838 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4839 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4840 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4841 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4842 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4843 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4844 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 4845 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 4846 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 4847 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 4848 VMX_CPU_BASED_PAUSE_EXITING | 4849 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 4850 .features[FEAT_VMX_SECONDARY_CTLS] = 4851 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 4852 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 4853 VMX_SECONDARY_EXEC_RDTSCP | 4854 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 4855 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 4856 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 4857 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 4858 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 4859 VMX_SECONDARY_EXEC_RDRAND_EXITING | 4860 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 4861 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 4862 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 4863 VMX_SECONDARY_EXEC_XSAVES, 4864 .features[FEAT_VMX_VMFUNC] = 4865 MSR_VMX_VMFUNC_EPT_SWITCHING, 4866 .xlevel = 0x80000008, 4867 .model_id = "Intel Xeon Processor (SierraForest)", 4868 .versions = (X86CPUVersionDefinition[]) { 4869 { .version = 1 }, 4870 { 4871 .version = 2, 4872 .props = (PropValue[]) { 4873 { "ss", "on" }, 4874 { "tsc-adjust", "on" }, 4875 { "cldemote", "on" }, 4876 { "movdiri", "on" }, 4877 { "movdir64b", "on" }, 4878 { "gds-no", "on" }, 4879 { "rfds-no", "on" }, 4880 { "lam", "on" }, 4881 { "intel-psfd", "on"}, 4882 { "ipred-ctrl", "on"}, 4883 { "rrsba-ctrl", "on"}, 4884 { "bhi-ctrl", "on"}, 4885 { "stepping", "3" }, 4886 { /* end of list */ } 4887 } 4888 }, 4889 { /* end of list */ }, 4890 }, 4891 }, 4892 { 4893 .name = "ClearwaterForest", 4894 .level = 0x23, 4895 .xlevel = 0x80000008, 4896 .vendor = CPUID_VENDOR_INTEL, 4897 .family = 6, 4898 .model = 221, 4899 .stepping = 0, 4900 /* 4901 * please keep the ascending order so that we can have a clear view of 4902 * bit position of each feature. 4903 */ 4904 .features[FEAT_1_EDX] = 4905 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 4906 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 4907 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 4908 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 4909 CPUID_SSE | CPUID_SSE2 | CPUID_SS, 4910 .features[FEAT_1_ECX] = 4911 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | 4912 CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | 4913 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 4914 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | 4915 CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 4916 .features[FEAT_8000_0001_EDX] = 4917 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 4918 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 4919 .features[FEAT_8000_0001_ECX] = 4920 CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, 4921 .features[FEAT_8000_0008_EBX] = 4922 CPUID_8000_0008_EBX_WBNOINVD, 4923 .features[FEAT_7_0_EBX] = 4924 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_TSC_ADJUST | 4925 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 4926 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 4927 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | 4928 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB | 4929 CPUID_7_0_EBX_SHA_NI, 4930 .features[FEAT_7_0_ECX] = 4931 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_GFNI | 4932 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 4933 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT | 4934 CPUID_7_0_ECX_CLDEMOTE | CPUID_7_0_ECX_MOVDIRI | 4935 CPUID_7_0_ECX_MOVDIR64B, 4936 .features[FEAT_7_0_EDX] = 4937 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE | 4938 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES | 4939 CPUID_7_0_EDX_SPEC_CTRL_SSBD, 4940 .features[FEAT_ARCH_CAPABILITIES] = 4941 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 4942 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 4943 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_SBDR_SSDP_NO | 4944 MSR_ARCH_CAP_FBSDP_NO | MSR_ARCH_CAP_PSDP_NO | 4945 MSR_ARCH_CAP_BHI_NO | MSR_ARCH_CAP_PBRSB_NO | 4946 MSR_ARCH_CAP_GDS_NO | MSR_ARCH_CAP_RFDS_NO, 4947 .features[FEAT_XSAVE] = 4948 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4949 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 4950 .features[FEAT_6_EAX] = 4951 CPUID_6_EAX_ARAT, 4952 .features[FEAT_7_1_EAX] = 4953 CPUID_7_1_EAX_SHA512 | CPUID_7_1_EAX_SM3 | CPUID_7_1_EAX_SM4 | 4954 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_CMPCCXADD | 4955 CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_AVX_IFMA | 4956 CPUID_7_1_EAX_LAM, 4957 .features[FEAT_7_1_EDX] = 4958 CPUID_7_1_EDX_AVX_VNNI_INT8 | CPUID_7_1_EDX_AVX_NE_CONVERT | 4959 CPUID_7_1_EDX_AVX_VNNI_INT16 | CPUID_7_1_EDX_PREFETCHITI, 4960 .features[FEAT_7_2_EDX] = 4961 CPUID_7_2_EDX_PSFD | CPUID_7_2_EDX_IPRED_CTRL | 4962 CPUID_7_2_EDX_RRSBA_CTRL | CPUID_7_2_EDX_DDPD_U | 4963 CPUID_7_2_EDX_BHI_CTRL | CPUID_7_2_EDX_MCDT_NO, 4964 .features[FEAT_VMX_BASIC] = 4965 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 4966 .features[FEAT_VMX_ENTRY_CTLS] = 4967 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 4968 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 4969 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 4970 .features[FEAT_VMX_EPT_VPID_CAPS] = 4971 MSR_VMX_EPT_EXECONLY | MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | 4972 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 4973 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 4974 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 4975 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 4976 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | 4977 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 4978 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 4979 .features[FEAT_VMX_EXIT_CTLS] = 4980 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 4981 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 4982 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 4983 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 4984 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 4985 .features[FEAT_VMX_MISC] = 4986 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 4987 MSR_VMX_MISC_VMWRITE_VMEXIT, 4988 .features[FEAT_VMX_PINBASED_CTLS] = 4989 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 4990 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 4991 VMX_PIN_BASED_POSTED_INTR, 4992 .features[FEAT_VMX_PROCBASED_CTLS] = 4993 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 4994 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 4995 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 4996 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 4997 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 4998 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 4999 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | 5000 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 5001 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG | 5002 VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 5003 VMX_CPU_BASED_PAUSE_EXITING | 5004 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 5005 .features[FEAT_VMX_SECONDARY_CTLS] = 5006 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 5007 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 5008 VMX_SECONDARY_EXEC_RDTSCP | 5009 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 5010 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING | 5011 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 5012 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 5013 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 5014 VMX_SECONDARY_EXEC_RDRAND_EXITING | 5015 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 5016 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 5017 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML | 5018 VMX_SECONDARY_EXEC_XSAVES, 5019 .features[FEAT_VMX_VMFUNC] = 5020 MSR_VMX_VMFUNC_EPT_SWITCHING, 5021 .model_id = "Intel Xeon Processor (ClearwaterForest)", 5022 .versions = (X86CPUVersionDefinition[]) { 5023 { .version = 1 }, 5024 { /* end of list */ }, 5025 }, 5026 }, 5027 { 5028 .name = "Denverton", 5029 .level = 21, 5030 .vendor = CPUID_VENDOR_INTEL, 5031 .family = 6, 5032 .model = 95, 5033 .stepping = 1, 5034 .features[FEAT_1_EDX] = 5035 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 5036 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 5037 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 5038 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 5039 CPUID_SSE | CPUID_SSE2, 5040 .features[FEAT_1_ECX] = 5041 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR | 5042 CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_SSE41 | 5043 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 5044 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | 5045 CPUID_EXT_AES | CPUID_EXT_XSAVE | CPUID_EXT_RDRAND, 5046 .features[FEAT_8000_0001_EDX] = 5047 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 5048 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 5049 .features[FEAT_8000_0001_ECX] = 5050 CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 5051 .features[FEAT_7_0_EBX] = 5052 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_ERMS | 5053 CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_SMAP | 5054 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_SHA_NI, 5055 .features[FEAT_7_0_EDX] = 5056 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES | 5057 CPUID_7_0_EDX_SPEC_CTRL_SSBD, 5058 /* XSAVES is added in version 3 */ 5059 .features[FEAT_XSAVE] = 5060 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | CPUID_XSAVE_XGETBV1, 5061 .features[FEAT_6_EAX] = 5062 CPUID_6_EAX_ARAT, 5063 .features[FEAT_ARCH_CAPABILITIES] = 5064 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY, 5065 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 5066 MSR_VMX_BASIC_TRUE_CTLS, 5067 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 5068 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 5069 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 5070 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 5071 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 5072 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 5073 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 5074 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 5075 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 5076 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 5077 .features[FEAT_VMX_EXIT_CTLS] = 5078 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 5079 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 5080 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 5081 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 5082 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 5083 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 5084 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 5085 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 5086 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 5087 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 5088 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 5089 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 5090 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 5091 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 5092 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 5093 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 5094 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 5095 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 5096 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 5097 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 5098 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 5099 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 5100 .features[FEAT_VMX_SECONDARY_CTLS] = 5101 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 5102 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 5103 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 5104 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 5105 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 5106 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 5107 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 5108 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 5109 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 5110 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 5111 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 5112 .xlevel = 0x80000008, 5113 .model_id = "Intel Atom Processor (Denverton)", 5114 .versions = (X86CPUVersionDefinition[]) { 5115 { .version = 1 }, 5116 { 5117 .version = 2, 5118 .note = "no MPX, no MONITOR", 5119 .props = (PropValue[]) { 5120 { "monitor", "off" }, 5121 { "mpx", "off" }, 5122 { /* end of list */ }, 5123 }, 5124 }, 5125 { 5126 .version = 3, 5127 .note = "XSAVES, no MPX, no MONITOR", 5128 .props = (PropValue[]) { 5129 { "xsaves", "on" }, 5130 { "vmx-xsaves", "on" }, 5131 { /* end of list */ }, 5132 }, 5133 }, 5134 { /* end of list */ }, 5135 }, 5136 }, 5137 { 5138 .name = "Snowridge", 5139 .level = 27, 5140 .vendor = CPUID_VENDOR_INTEL, 5141 .family = 6, 5142 .model = 134, 5143 .stepping = 1, 5144 .features[FEAT_1_EDX] = 5145 /* missing: CPUID_PN CPUID_IA64 */ 5146 /* missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 5147 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | 5148 CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_MCE | 5149 CPUID_CX8 | CPUID_APIC | CPUID_SEP | 5150 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 5151 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | 5152 CPUID_MMX | 5153 CPUID_FXSR | CPUID_SSE | CPUID_SSE2, 5154 .features[FEAT_1_ECX] = 5155 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR | 5156 CPUID_EXT_SSSE3 | 5157 CPUID_EXT_CX16 | 5158 CPUID_EXT_SSE41 | 5159 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 5160 CPUID_EXT_POPCNT | 5161 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | CPUID_EXT_XSAVE | 5162 CPUID_EXT_RDRAND, 5163 .features[FEAT_8000_0001_EDX] = 5164 CPUID_EXT2_SYSCALL | 5165 CPUID_EXT2_NX | 5166 CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 5167 CPUID_EXT2_LM, 5168 .features[FEAT_8000_0001_ECX] = 5169 CPUID_EXT3_LAHF_LM | 5170 CPUID_EXT3_3DNOWPREFETCH, 5171 .features[FEAT_7_0_EBX] = 5172 CPUID_7_0_EBX_FSGSBASE | 5173 CPUID_7_0_EBX_SMEP | 5174 CPUID_7_0_EBX_ERMS | 5175 CPUID_7_0_EBX_MPX | /* missing bits 13, 15 */ 5176 CPUID_7_0_EBX_RDSEED | 5177 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 5178 CPUID_7_0_EBX_CLWB | 5179 CPUID_7_0_EBX_SHA_NI, 5180 .features[FEAT_7_0_ECX] = 5181 CPUID_7_0_ECX_UMIP | 5182 /* missing bit 5 */ 5183 CPUID_7_0_ECX_GFNI | 5184 CPUID_7_0_ECX_MOVDIRI | CPUID_7_0_ECX_CLDEMOTE | 5185 CPUID_7_0_ECX_MOVDIR64B, 5186 .features[FEAT_7_0_EDX] = 5187 CPUID_7_0_EDX_SPEC_CTRL | 5188 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD | 5189 CPUID_7_0_EDX_CORE_CAPABILITY, 5190 .features[FEAT_CORE_CAPABILITY] = 5191 MSR_CORE_CAP_SPLIT_LOCK_DETECT, 5192 /* XSAVES is added in version 3 */ 5193 .features[FEAT_XSAVE] = 5194 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5195 CPUID_XSAVE_XGETBV1, 5196 .features[FEAT_6_EAX] = 5197 CPUID_6_EAX_ARAT, 5198 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 5199 MSR_VMX_BASIC_TRUE_CTLS, 5200 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 5201 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 5202 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 5203 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 5204 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 5205 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 5206 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 5207 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 5208 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 5209 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 5210 .features[FEAT_VMX_EXIT_CTLS] = 5211 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 5212 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 5213 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 5214 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 5215 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 5216 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 5217 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 5218 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 5219 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 5220 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 5221 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 5222 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 5223 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 5224 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 5225 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 5226 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 5227 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 5228 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 5229 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 5230 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 5231 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 5232 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 5233 .features[FEAT_VMX_SECONDARY_CTLS] = 5234 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 5235 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 5236 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 5237 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 5238 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 5239 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 5240 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 5241 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 5242 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 5243 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 5244 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 5245 .xlevel = 0x80000008, 5246 .model_id = "Intel Atom Processor (SnowRidge)", 5247 .versions = (X86CPUVersionDefinition[]) { 5248 { .version = 1 }, 5249 { 5250 .version = 2, 5251 .props = (PropValue[]) { 5252 { "mpx", "off" }, 5253 { "model-id", "Intel Atom Processor (Snowridge, no MPX)" }, 5254 { /* end of list */ }, 5255 }, 5256 }, 5257 { 5258 .version = 3, 5259 .note = "XSAVES, no MPX", 5260 .props = (PropValue[]) { 5261 { "xsaves", "on" }, 5262 { "vmx-xsaves", "on" }, 5263 { /* end of list */ }, 5264 }, 5265 }, 5266 { 5267 .version = 4, 5268 .note = "no split lock detect, no core-capability", 5269 .props = (PropValue[]) { 5270 { "split-lock-detect", "off" }, 5271 { "core-capability", "off" }, 5272 { /* end of list */ }, 5273 }, 5274 }, 5275 { /* end of list */ }, 5276 }, 5277 }, 5278 { 5279 .name = "KnightsMill", 5280 .level = 0xd, 5281 .vendor = CPUID_VENDOR_INTEL, 5282 .family = 6, 5283 .model = 133, 5284 .stepping = 0, 5285 .features[FEAT_1_EDX] = 5286 CPUID_VME | CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | 5287 CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | 5288 CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | 5289 CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | 5290 CPUID_PSE | CPUID_DE | CPUID_FP87, 5291 .features[FEAT_1_ECX] = 5292 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 5293 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 5294 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 5295 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 5296 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 5297 CPUID_EXT_F16C | CPUID_EXT_RDRAND, 5298 .features[FEAT_8000_0001_EDX] = 5299 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 5300 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 5301 .features[FEAT_8000_0001_ECX] = 5302 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 5303 .features[FEAT_7_0_EBX] = 5304 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5305 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 5306 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_AVX512F | 5307 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_AVX512PF | 5308 CPUID_7_0_EBX_AVX512ER, 5309 .features[FEAT_7_0_ECX] = 5310 CPUID_7_0_ECX_AVX512_VPOPCNTDQ, 5311 .features[FEAT_7_0_EDX] = 5312 CPUID_7_0_EDX_AVX512_4VNNIW | CPUID_7_0_EDX_AVX512_4FMAPS, 5313 .features[FEAT_XSAVE] = 5314 CPUID_XSAVE_XSAVEOPT, 5315 .features[FEAT_6_EAX] = 5316 CPUID_6_EAX_ARAT, 5317 .xlevel = 0x80000008, 5318 .model_id = "Intel Xeon Phi Processor (Knights Mill)", 5319 }, 5320 { 5321 .name = "Opteron_G1", 5322 .level = 5, 5323 .vendor = CPUID_VENDOR_AMD, 5324 .family = 15, 5325 .model = 6, 5326 .stepping = 1, 5327 .features[FEAT_1_EDX] = 5328 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 5329 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 5330 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 5331 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 5332 CPUID_DE | CPUID_FP87, 5333 .features[FEAT_1_ECX] = 5334 CPUID_EXT_SSE3, 5335 .features[FEAT_8000_0001_EDX] = 5336 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 5337 .xlevel = 0x80000008, 5338 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)", 5339 }, 5340 { 5341 .name = "Opteron_G2", 5342 .level = 5, 5343 .vendor = CPUID_VENDOR_AMD, 5344 .family = 15, 5345 .model = 6, 5346 .stepping = 1, 5347 .features[FEAT_1_EDX] = 5348 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 5349 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 5350 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 5351 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 5352 CPUID_DE | CPUID_FP87, 5353 .features[FEAT_1_ECX] = 5354 CPUID_EXT_CX16 | CPUID_EXT_SSE3, 5355 .features[FEAT_8000_0001_EDX] = 5356 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 5357 .features[FEAT_8000_0001_ECX] = 5358 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, 5359 .xlevel = 0x80000008, 5360 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)", 5361 }, 5362 { 5363 .name = "Opteron_G3", 5364 .level = 5, 5365 .vendor = CPUID_VENDOR_AMD, 5366 .family = 16, 5367 .model = 2, 5368 .stepping = 3, 5369 .features[FEAT_1_EDX] = 5370 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 5371 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 5372 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 5373 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 5374 CPUID_DE | CPUID_FP87, 5375 .features[FEAT_1_ECX] = 5376 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR | 5377 CPUID_EXT_SSE3, 5378 .features[FEAT_8000_0001_EDX] = 5379 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL | 5380 CPUID_EXT2_RDTSCP, 5381 .features[FEAT_8000_0001_ECX] = 5382 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | 5383 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, 5384 .xlevel = 0x80000008, 5385 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)", 5386 }, 5387 { 5388 .name = "Opteron_G4", 5389 .level = 0xd, 5390 .vendor = CPUID_VENDOR_AMD, 5391 .family = 21, 5392 .model = 1, 5393 .stepping = 2, 5394 .features[FEAT_1_EDX] = 5395 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 5396 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 5397 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 5398 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 5399 CPUID_DE | CPUID_FP87, 5400 .features[FEAT_1_ECX] = 5401 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 5402 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5403 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 5404 CPUID_EXT_SSE3, 5405 .features[FEAT_8000_0001_EDX] = 5406 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX | 5407 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP, 5408 .features[FEAT_8000_0001_ECX] = 5409 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP | 5410 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | 5411 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | 5412 CPUID_EXT3_LAHF_LM, 5413 .features[FEAT_SVM] = 5414 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 5415 /* no xsaveopt! */ 5416 .xlevel = 0x8000001A, 5417 .model_id = "AMD Opteron 62xx class CPU", 5418 }, 5419 { 5420 .name = "Opteron_G5", 5421 .level = 0xd, 5422 .vendor = CPUID_VENDOR_AMD, 5423 .family = 21, 5424 .model = 2, 5425 .stepping = 0, 5426 .features[FEAT_1_EDX] = 5427 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 5428 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 5429 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 5430 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 5431 CPUID_DE | CPUID_FP87, 5432 .features[FEAT_1_ECX] = 5433 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE | 5434 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | 5435 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA | 5436 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 5437 .features[FEAT_8000_0001_EDX] = 5438 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX | 5439 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP, 5440 .features[FEAT_8000_0001_ECX] = 5441 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP | 5442 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | 5443 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | 5444 CPUID_EXT3_LAHF_LM, 5445 .features[FEAT_SVM] = 5446 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 5447 /* no xsaveopt! */ 5448 .xlevel = 0x8000001A, 5449 .model_id = "AMD Opteron 63xx class CPU", 5450 }, 5451 { 5452 .name = "EPYC", 5453 .level = 0xd, 5454 .vendor = CPUID_VENDOR_AMD, 5455 .family = 23, 5456 .model = 1, 5457 .stepping = 2, 5458 .features[FEAT_1_EDX] = 5459 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 5460 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 5461 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 5462 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 5463 CPUID_VME | CPUID_FP87, 5464 .features[FEAT_1_ECX] = 5465 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5466 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 5467 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5468 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 5469 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 5470 .features[FEAT_8000_0001_EDX] = 5471 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5472 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5473 CPUID_EXT2_SYSCALL, 5474 .features[FEAT_8000_0001_ECX] = 5475 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5476 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5477 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5478 CPUID_EXT3_TOPOEXT, 5479 .features[FEAT_7_0_EBX] = 5480 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5481 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 5482 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 5483 CPUID_7_0_EBX_SHA_NI, 5484 .features[FEAT_XSAVE] = 5485 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5486 CPUID_XSAVE_XGETBV1, 5487 .features[FEAT_6_EAX] = 5488 CPUID_6_EAX_ARAT, 5489 .features[FEAT_SVM] = 5490 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 5491 .xlevel = 0x8000001E, 5492 .model_id = "AMD EPYC Processor", 5493 .cache_info = &epyc_cache_info, 5494 .versions = (X86CPUVersionDefinition[]) { 5495 { .version = 1 }, 5496 { 5497 .version = 2, 5498 .alias = "EPYC-IBPB", 5499 .props = (PropValue[]) { 5500 { "ibpb", "on" }, 5501 { "model-id", 5502 "AMD EPYC Processor (with IBPB)" }, 5503 { /* end of list */ } 5504 } 5505 }, 5506 { 5507 .version = 3, 5508 .props = (PropValue[]) { 5509 { "ibpb", "on" }, 5510 { "perfctr-core", "on" }, 5511 { "clzero", "on" }, 5512 { "xsaveerptr", "on" }, 5513 { "xsaves", "on" }, 5514 { "model-id", 5515 "AMD EPYC Processor" }, 5516 { /* end of list */ } 5517 } 5518 }, 5519 { 5520 .version = 4, 5521 .props = (PropValue[]) { 5522 { "model-id", 5523 "AMD EPYC-v4 Processor" }, 5524 { /* end of list */ } 5525 }, 5526 .cache_info = &epyc_v4_cache_info 5527 }, 5528 { 5529 .version = 5, 5530 .props = (PropValue[]) { 5531 { "overflow-recov", "on" }, 5532 { "succor", "on" }, 5533 { "lbrv", "on" }, 5534 { "tsc-scale", "on" }, 5535 { "vmcb-clean", "on" }, 5536 { "flushbyasid", "on" }, 5537 { "pause-filter", "on" }, 5538 { "pfthreshold", "on" }, 5539 { "v-vmsave-vmload", "on" }, 5540 { "vgif", "on" }, 5541 { "model-id", 5542 "AMD EPYC-v5 Processor" }, 5543 { /* end of list */ } 5544 }, 5545 .cache_info = &epyc_v5_cache_info 5546 }, 5547 { /* end of list */ } 5548 } 5549 }, 5550 { 5551 .name = "Dhyana", 5552 .level = 0xd, 5553 .vendor = CPUID_VENDOR_HYGON, 5554 .family = 24, 5555 .model = 0, 5556 .stepping = 1, 5557 .features[FEAT_1_EDX] = 5558 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 5559 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 5560 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 5561 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 5562 CPUID_VME | CPUID_FP87, 5563 .features[FEAT_1_ECX] = 5564 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5565 CPUID_EXT_XSAVE | CPUID_EXT_POPCNT | 5566 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5567 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 5568 CPUID_EXT_MONITOR | CPUID_EXT_SSE3, 5569 .features[FEAT_8000_0001_EDX] = 5570 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5571 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5572 CPUID_EXT2_SYSCALL, 5573 .features[FEAT_8000_0001_ECX] = 5574 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5575 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5576 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5577 CPUID_EXT3_TOPOEXT, 5578 .features[FEAT_8000_0008_EBX] = 5579 CPUID_8000_0008_EBX_IBPB, 5580 .features[FEAT_7_0_EBX] = 5581 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5582 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 5583 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT, 5584 /* XSAVES is added in version 2 */ 5585 .features[FEAT_XSAVE] = 5586 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5587 CPUID_XSAVE_XGETBV1, 5588 .features[FEAT_6_EAX] = 5589 CPUID_6_EAX_ARAT, 5590 .features[FEAT_SVM] = 5591 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 5592 .xlevel = 0x8000001E, 5593 .model_id = "Hygon Dhyana Processor", 5594 .cache_info = &epyc_cache_info, 5595 .versions = (X86CPUVersionDefinition[]) { 5596 { .version = 1 }, 5597 { .version = 2, 5598 .note = "XSAVES", 5599 .props = (PropValue[]) { 5600 { "xsaves", "on" }, 5601 { /* end of list */ } 5602 }, 5603 }, 5604 { /* end of list */ } 5605 } 5606 }, 5607 { 5608 .name = "EPYC-Rome", 5609 .level = 0xd, 5610 .vendor = CPUID_VENDOR_AMD, 5611 .family = 23, 5612 .model = 49, 5613 .stepping = 0, 5614 .features[FEAT_1_EDX] = 5615 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 5616 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 5617 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 5618 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 5619 CPUID_VME | CPUID_FP87, 5620 .features[FEAT_1_ECX] = 5621 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5622 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 5623 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5624 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 5625 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 5626 .features[FEAT_8000_0001_EDX] = 5627 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5628 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5629 CPUID_EXT2_SYSCALL, 5630 .features[FEAT_8000_0001_ECX] = 5631 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5632 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5633 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5634 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 5635 .features[FEAT_8000_0008_EBX] = 5636 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 5637 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 5638 CPUID_8000_0008_EBX_STIBP, 5639 .features[FEAT_7_0_EBX] = 5640 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5641 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 5642 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 5643 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB, 5644 .features[FEAT_7_0_ECX] = 5645 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID, 5646 .features[FEAT_XSAVE] = 5647 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5648 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 5649 .features[FEAT_6_EAX] = 5650 CPUID_6_EAX_ARAT, 5651 .features[FEAT_SVM] = 5652 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 5653 .xlevel = 0x8000001E, 5654 .model_id = "AMD EPYC-Rome Processor", 5655 .cache_info = &epyc_rome_cache_info, 5656 .versions = (X86CPUVersionDefinition[]) { 5657 { .version = 1 }, 5658 { 5659 .version = 2, 5660 .props = (PropValue[]) { 5661 { "ibrs", "on" }, 5662 { "amd-ssbd", "on" }, 5663 { /* end of list */ } 5664 } 5665 }, 5666 { 5667 .version = 3, 5668 .props = (PropValue[]) { 5669 { "model-id", 5670 "AMD EPYC-Rome-v3 Processor" }, 5671 { /* end of list */ } 5672 }, 5673 .cache_info = &epyc_rome_v3_cache_info 5674 }, 5675 { 5676 .version = 4, 5677 .props = (PropValue[]) { 5678 /* Erratum 1386 */ 5679 { "model-id", 5680 "AMD EPYC-Rome-v4 Processor (no XSAVES)" }, 5681 { "xsaves", "off" }, 5682 { /* end of list */ } 5683 }, 5684 }, 5685 { 5686 .version = 5, 5687 .props = (PropValue[]) { 5688 { "overflow-recov", "on" }, 5689 { "succor", "on" }, 5690 { "lbrv", "on" }, 5691 { "tsc-scale", "on" }, 5692 { "vmcb-clean", "on" }, 5693 { "flushbyasid", "on" }, 5694 { "pause-filter", "on" }, 5695 { "pfthreshold", "on" }, 5696 { "v-vmsave-vmload", "on" }, 5697 { "vgif", "on" }, 5698 { "model-id", 5699 "AMD EPYC-Rome-v5 Processor" }, 5700 { /* end of list */ } 5701 }, 5702 .cache_info = &epyc_rome_v5_cache_info 5703 }, 5704 { /* end of list */ } 5705 } 5706 }, 5707 { 5708 .name = "EPYC-Milan", 5709 .level = 0xd, 5710 .vendor = CPUID_VENDOR_AMD, 5711 .family = 25, 5712 .model = 1, 5713 .stepping = 1, 5714 .features[FEAT_1_EDX] = 5715 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 5716 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 5717 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 5718 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 5719 CPUID_VME | CPUID_FP87, 5720 .features[FEAT_1_ECX] = 5721 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5722 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 5723 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5724 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 5725 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 5726 CPUID_EXT_PCID, 5727 .features[FEAT_8000_0001_EDX] = 5728 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5729 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5730 CPUID_EXT2_SYSCALL, 5731 .features[FEAT_8000_0001_ECX] = 5732 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5733 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5734 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5735 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 5736 .features[FEAT_8000_0008_EBX] = 5737 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 5738 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 5739 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | 5740 CPUID_8000_0008_EBX_AMD_SSBD, 5741 .features[FEAT_7_0_EBX] = 5742 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5743 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 5744 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 5745 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_ERMS | 5746 CPUID_7_0_EBX_INVPCID, 5747 .features[FEAT_7_0_ECX] = 5748 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_PKU, 5749 .features[FEAT_7_0_EDX] = 5750 CPUID_7_0_EDX_FSRM, 5751 .features[FEAT_XSAVE] = 5752 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5753 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 5754 .features[FEAT_6_EAX] = 5755 CPUID_6_EAX_ARAT, 5756 .features[FEAT_SVM] = 5757 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE | CPUID_SVM_SVME_ADDR_CHK, 5758 .xlevel = 0x8000001E, 5759 .model_id = "AMD EPYC-Milan Processor", 5760 .cache_info = &epyc_milan_cache_info, 5761 .versions = (X86CPUVersionDefinition[]) { 5762 { .version = 1 }, 5763 { 5764 .version = 2, 5765 .props = (PropValue[]) { 5766 { "model-id", 5767 "AMD EPYC-Milan-v2 Processor" }, 5768 { "vaes", "on" }, 5769 { "vpclmulqdq", "on" }, 5770 { "stibp-always-on", "on" }, 5771 { "amd-psfd", "on" }, 5772 { "no-nested-data-bp", "on" }, 5773 { "lfence-always-serializing", "on" }, 5774 { "null-sel-clr-base", "on" }, 5775 { /* end of list */ } 5776 }, 5777 .cache_info = &epyc_milan_v2_cache_info 5778 }, 5779 { 5780 .version = 3, 5781 .props = (PropValue[]) { 5782 { "overflow-recov", "on" }, 5783 { "succor", "on" }, 5784 { "lbrv", "on" }, 5785 { "tsc-scale", "on" }, 5786 { "vmcb-clean", "on" }, 5787 { "flushbyasid", "on" }, 5788 { "pause-filter", "on" }, 5789 { "pfthreshold", "on" }, 5790 { "v-vmsave-vmload", "on" }, 5791 { "vgif", "on" }, 5792 { "model-id", 5793 "AMD EPYC-Milan-v3 Processor" }, 5794 { /* end of list */ } 5795 }, 5796 .cache_info = &epyc_milan_v3_cache_info 5797 }, 5798 { /* end of list */ } 5799 } 5800 }, 5801 { 5802 .name = "EPYC-Genoa", 5803 .level = 0xd, 5804 .vendor = CPUID_VENDOR_AMD, 5805 .family = 25, 5806 .model = 17, 5807 .stepping = 0, 5808 .features[FEAT_1_EDX] = 5809 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 5810 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 5811 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 5812 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 5813 CPUID_VME | CPUID_FP87, 5814 .features[FEAT_1_ECX] = 5815 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5816 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 5817 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 5818 CPUID_EXT_PCID | CPUID_EXT_CX16 | CPUID_EXT_FMA | 5819 CPUID_EXT_SSSE3 | CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | 5820 CPUID_EXT_SSE3, 5821 .features[FEAT_8000_0001_EDX] = 5822 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5823 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 5824 CPUID_EXT2_SYSCALL, 5825 .features[FEAT_8000_0001_ECX] = 5826 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 5827 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 5828 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 5829 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 5830 .features[FEAT_8000_0008_EBX] = 5831 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 5832 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 5833 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | 5834 CPUID_8000_0008_EBX_STIBP_ALWAYS_ON | 5835 CPUID_8000_0008_EBX_AMD_SSBD | CPUID_8000_0008_EBX_AMD_PSFD, 5836 .features[FEAT_8000_0021_EAX] = 5837 CPUID_8000_0021_EAX_NO_NESTED_DATA_BP | 5838 CPUID_8000_0021_EAX_LFENCE_ALWAYS_SERIALIZING | 5839 CPUID_8000_0021_EAX_NULL_SEL_CLR_BASE | 5840 CPUID_8000_0021_EAX_AUTO_IBRS, 5841 .features[FEAT_7_0_EBX] = 5842 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 5843 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 5844 CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_AVX512F | 5845 CPUID_7_0_EBX_AVX512DQ | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 5846 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_AVX512IFMA | 5847 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB | 5848 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | 5849 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, 5850 .features[FEAT_7_0_ECX] = 5851 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 5852 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 5853 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 5854 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 5855 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | 5856 CPUID_7_0_ECX_RDPID, 5857 .features[FEAT_7_0_EDX] = 5858 CPUID_7_0_EDX_FSRM, 5859 .features[FEAT_7_1_EAX] = 5860 CPUID_7_1_EAX_AVX512_BF16, 5861 .features[FEAT_XSAVE] = 5862 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 5863 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 5864 .features[FEAT_6_EAX] = 5865 CPUID_6_EAX_ARAT, 5866 .features[FEAT_SVM] = 5867 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE | CPUID_SVM_VNMI | 5868 CPUID_SVM_SVME_ADDR_CHK, 5869 .xlevel = 0x80000022, 5870 .model_id = "AMD EPYC-Genoa Processor", 5871 .cache_info = &epyc_genoa_cache_info, 5872 .versions = (X86CPUVersionDefinition[]) { 5873 { .version = 1 }, 5874 { 5875 .version = 2, 5876 .props = (PropValue[]) { 5877 { "overflow-recov", "on" }, 5878 { "succor", "on" }, 5879 { "lbrv", "on" }, 5880 { "tsc-scale", "on" }, 5881 { "vmcb-clean", "on" }, 5882 { "flushbyasid", "on" }, 5883 { "pause-filter", "on" }, 5884 { "pfthreshold", "on" }, 5885 { "v-vmsave-vmload", "on" }, 5886 { "vgif", "on" }, 5887 { "fs-gs-base-ns", "on" }, 5888 { "perfmon-v2", "on" }, 5889 { "model-id", 5890 "AMD EPYC-Genoa-v2 Processor" }, 5891 { /* end of list */ } 5892 }, 5893 .cache_info = &epyc_genoa_v2_cache_info 5894 }, 5895 { /* end of list */ } 5896 } 5897 }, 5898 { 5899 .name = "YongFeng", 5900 .level = 0x1F, 5901 .vendor = CPUID_VENDOR_ZHAOXIN1, 5902 .family = 7, 5903 .model = 11, 5904 .stepping = 3, 5905 /* missing: CPUID_HT, CPUID_TM, CPUID_PBE */ 5906 .features[FEAT_1_EDX] = 5907 CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 5908 CPUID_ACPI | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | 5909 CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | 5910 CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | 5911 CPUID_PSE | CPUID_DE | CPUID_VME | CPUID_FP87, 5912 /* 5913 * missing: CPUID_EXT_OSXSAVE, CPUID_EXT_XTPR, CPUID_EXT_TM2, 5914 * CPUID_EXT_EST, CPUID_EXT_SMX, CPUID_EXT_VMX 5915 */ 5916 .features[FEAT_1_ECX] = 5917 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 5918 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_TSC_DEADLINE_TIMER | 5919 CPUID_EXT_POPCNT | CPUID_EXT_MOVBE | CPUID_EXT_X2APIC | 5920 CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | CPUID_EXT_PCID | 5921 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 5922 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 5923 .features[FEAT_7_0_EBX] = 5924 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_ADX | 5925 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_BMI2 | 5926 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_BMI1 | 5927 CPUID_7_0_EBX_FSGSBASE, 5928 /* missing: CPUID_7_0_ECX_OSPKE */ 5929 .features[FEAT_7_0_ECX] = 5930 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_UMIP, 5931 .features[FEAT_7_0_EDX] = 5932 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL, 5933 .features[FEAT_8000_0001_EDX] = 5934 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 5935 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 5936 .features[FEAT_8000_0001_ECX] = 5937 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM, 5938 .features[FEAT_8000_0007_EDX] = CPUID_APM_INVTSC, 5939 /* 5940 * TODO: When the Linux kernel introduces other existing definitions 5941 * for this leaf, remember to update the definitions here. 5942 */ 5943 .features[FEAT_C000_0001_EDX] = 5944 CPUID_C000_0001_EDX_PMM_EN | CPUID_C000_0001_EDX_PMM | 5945 CPUID_C000_0001_EDX_PHE_EN | CPUID_C000_0001_EDX_PHE | 5946 CPUID_C000_0001_EDX_ACE2 | 5947 CPUID_C000_0001_EDX_XCRYPT_EN | CPUID_C000_0001_EDX_XCRYPT | 5948 CPUID_C000_0001_EDX_XSTORE_EN | CPUID_C000_0001_EDX_XSTORE, 5949 .features[FEAT_XSAVE] = 5950 CPUID_XSAVE_XSAVEOPT, 5951 .features[FEAT_ARCH_CAPABILITIES] = 5952 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | 5953 MSR_ARCH_CAP_MDS_NO | MSR_ARCH_CAP_PSCHANGE_MC_NO | 5954 MSR_ARCH_CAP_SSB_NO, 5955 .features[FEAT_VMX_PROCBASED_CTLS] = 5956 VMX_CPU_BASED_VIRTUAL_INTR_PENDING | VMX_CPU_BASED_HLT_EXITING | 5957 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_INVLPG_EXITING | 5958 VMX_CPU_BASED_MWAIT_EXITING | VMX_CPU_BASED_RDPMC_EXITING | 5959 VMX_CPU_BASED_RDTSC_EXITING | VMX_CPU_BASED_CR3_LOAD_EXITING | 5960 VMX_CPU_BASED_CR3_STORE_EXITING | VMX_CPU_BASED_CR8_LOAD_EXITING | 5961 VMX_CPU_BASED_CR8_STORE_EXITING | VMX_CPU_BASED_TPR_SHADOW | 5962 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_MOV_DR_EXITING | 5963 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 5964 VMX_CPU_BASED_MONITOR_TRAP_FLAG | VMX_CPU_BASED_USE_MSR_BITMAPS | 5965 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 5966 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 5967 /* 5968 * missing: VMX_SECONDARY_EXEC_PAUSE_LOOP_EXITING, 5969 * VMX_SECONDARY_EXEC_TSC_SCALING 5970 */ 5971 .features[FEAT_VMX_SECONDARY_CTLS] = 5972 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 5973 VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | 5974 VMX_SECONDARY_EXEC_RDTSCP | VMX_SECONDARY_EXEC_ENABLE_VPID | 5975 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 5976 VMX_SECONDARY_EXEC_WBINVD_EXITING | 5977 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 5978 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 5979 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 5980 VMX_SECONDARY_EXEC_RDRAND_EXITING | 5981 VMX_SECONDARY_EXEC_ENABLE_INVPCID | 5982 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | 5983 VMX_SECONDARY_EXEC_SHADOW_VMCS | 5984 VMX_SECONDARY_EXEC_ENABLE_PML, 5985 .features[FEAT_VMX_PINBASED_CTLS] = 5986 VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | 5987 VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER | 5988 VMX_PIN_BASED_POSTED_INTR, 5989 .features[FEAT_VMX_EXIT_CTLS] = 5990 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE | 5991 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 5992 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | 5993 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 5994 VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 5995 /* missing: VMX_VM_ENTRY_SMM, VMX_VM_ENTRY_DEACT_DUAL_MONITOR */ 5996 .features[FEAT_VMX_ENTRY_CTLS] = 5997 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | 5998 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 5999 VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER, 6000 /* 6001 * missing: MSR_VMX_MISC_ACTIVITY_SHUTDOWN, 6002 * MSR_VMX_MISC_ACTIVITY_WAIT_SIPI 6003 */ 6004 .features[FEAT_VMX_MISC] = 6005 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | 6006 MSR_VMX_MISC_VMWRITE_VMEXIT, 6007 /* missing: MSR_VMX_EPT_UC */ 6008 .features[FEAT_VMX_EPT_VPID_CAPS] = 6009 MSR_VMX_EPT_EXECONLY | MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | 6010 MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | 6011 MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | 6012 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 6013 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID | 6014 MSR_VMX_EPT_INVVPID_ALL_CONTEXT | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 6015 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 6016 .features[FEAT_VMX_BASIC] = 6017 MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS, 6018 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 6019 .xlevel = 0x80000008, 6020 .model_id = "Zhaoxin YongFeng Processor", 6021 .versions = (X86CPUVersionDefinition[]) { 6022 { .version = 1 }, 6023 { 6024 .version = 2, 6025 .note = "with the correct model number", 6026 .props = (PropValue[]) { 6027 { "model", "0x5b" }, 6028 { /* end of list */ } 6029 } 6030 }, 6031 { /* end of list */ } 6032 } 6033 }, 6034 { 6035 .name = "EPYC-Turin", 6036 .level = 0xd, 6037 .vendor = CPUID_VENDOR_AMD, 6038 .family = 26, 6039 .model = 0, 6040 .stepping = 0, 6041 .features[FEAT_1_ECX] = 6042 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 6043 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 6044 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 6045 CPUID_EXT_PCID | CPUID_EXT_CX16 | CPUID_EXT_FMA | 6046 CPUID_EXT_SSSE3 | CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | 6047 CPUID_EXT_SSE3, 6048 .features[FEAT_1_EDX] = 6049 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 6050 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 6051 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 6052 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 6053 CPUID_VME | CPUID_FP87, 6054 .features[FEAT_6_EAX] = 6055 CPUID_6_EAX_ARAT, 6056 .features[FEAT_7_0_EBX] = 6057 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 6058 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 6059 CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_AVX512F | 6060 CPUID_7_0_EBX_AVX512DQ | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 6061 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_AVX512IFMA | 6062 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB | 6063 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI | 6064 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL, 6065 .features[FEAT_7_0_ECX] = 6066 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 6067 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 6068 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 6069 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 6070 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 | 6071 CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_MOVDIRI | 6072 CPUID_7_0_ECX_MOVDIR64B, 6073 .features[FEAT_7_0_EDX] = 6074 CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_AVX512_VP2INTERSECT, 6075 .features[FEAT_7_1_EAX] = 6076 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_AVX512_BF16, 6077 .features[FEAT_8000_0001_ECX] = 6078 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 6079 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 6080 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 6081 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 6082 .features[FEAT_8000_0001_EDX] = 6083 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 6084 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 6085 CPUID_EXT2_SYSCALL, 6086 .features[FEAT_8000_0007_EBX] = 6087 CPUID_8000_0007_EBX_OVERFLOW_RECOV | CPUID_8000_0007_EBX_SUCCOR, 6088 .features[FEAT_8000_0008_EBX] = 6089 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 6090 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 6091 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | 6092 CPUID_8000_0008_EBX_STIBP_ALWAYS_ON | 6093 CPUID_8000_0008_EBX_AMD_SSBD | CPUID_8000_0008_EBX_AMD_PSFD, 6094 .features[FEAT_8000_0021_EAX] = 6095 CPUID_8000_0021_EAX_NO_NESTED_DATA_BP | 6096 CPUID_8000_0021_EAX_FS_GS_BASE_NS | 6097 CPUID_8000_0021_EAX_LFENCE_ALWAYS_SERIALIZING | 6098 CPUID_8000_0021_EAX_NULL_SEL_CLR_BASE | 6099 CPUID_8000_0021_EAX_AUTO_IBRS | CPUID_8000_0021_EAX_PREFETCHI | 6100 CPUID_8000_0021_EAX_SBPB | CPUID_8000_0021_EAX_IBPB_BRTYPE | 6101 CPUID_8000_0021_EAX_SRSO_USER_KERNEL_NO, 6102 .features[FEAT_8000_0022_EAX] = 6103 CPUID_8000_0022_EAX_PERFMON_V2, 6104 .features[FEAT_XSAVE] = 6105 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 6106 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 6107 .features[FEAT_SVM] = 6108 CPUID_SVM_NPT | CPUID_SVM_LBRV | CPUID_SVM_NRIPSAVE | 6109 CPUID_SVM_TSCSCALE | CPUID_SVM_VMCBCLEAN | CPUID_SVM_FLUSHASID | 6110 CPUID_SVM_PAUSEFILTER | CPUID_SVM_PFTHRESHOLD | 6111 CPUID_SVM_V_VMSAVE_VMLOAD | CPUID_SVM_VGIF | 6112 CPUID_SVM_VNMI | CPUID_SVM_SVME_ADDR_CHK, 6113 .xlevel = 0x80000022, 6114 .model_id = "AMD EPYC-Turin Processor", 6115 .cache_info = &epyc_turin_cache_info, 6116 }, 6117 }; 6118 6119 /* 6120 * We resolve CPU model aliases using -v1 when using "-machine 6121 * none", but this is just for compatibility while libvirt isn't 6122 * adapted to resolve CPU model versions before creating VMs. 6123 * See "Runnability guarantee of CPU models" at 6124 * docs/about/deprecated.rst. 6125 */ 6126 X86CPUVersion default_cpu_version = 1; 6127 6128 void x86_cpu_set_default_version(X86CPUVersion version) 6129 { 6130 /* Translating CPU_VERSION_AUTO to CPU_VERSION_AUTO doesn't make sense */ 6131 assert(version != CPU_VERSION_AUTO); 6132 default_cpu_version = version; 6133 } 6134 6135 static X86CPUVersion x86_cpu_model_last_version(const X86CPUModel *model) 6136 { 6137 int v = 0; 6138 const X86CPUVersionDefinition *vdef = 6139 x86_cpu_def_get_versions(model->cpudef); 6140 while (vdef->version) { 6141 v = vdef->version; 6142 vdef++; 6143 } 6144 return v; 6145 } 6146 6147 /* Return the actual version being used for a specific CPU model */ 6148 static X86CPUVersion x86_cpu_model_resolve_version(const X86CPUModel *model) 6149 { 6150 X86CPUVersion v = model->version; 6151 if (v == CPU_VERSION_AUTO) { 6152 v = default_cpu_version; 6153 } 6154 if (v == CPU_VERSION_LATEST) { 6155 return x86_cpu_model_last_version(model); 6156 } 6157 return v; 6158 } 6159 6160 static const Property max_x86_cpu_properties[] = { 6161 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true), 6162 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false), 6163 }; 6164 6165 static void max_x86_cpu_realize(DeviceState *dev, Error **errp) 6166 { 6167 Object *obj = OBJECT(dev); 6168 6169 if (!object_property_get_int(obj, "family", &error_abort)) { 6170 if (X86_CPU(obj)->env.features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 6171 object_property_set_int(obj, "family", 15, &error_abort); 6172 object_property_set_int(obj, "model", 107, &error_abort); 6173 object_property_set_int(obj, "stepping", 1, &error_abort); 6174 } else { 6175 object_property_set_int(obj, "family", 6, &error_abort); 6176 object_property_set_int(obj, "model", 6, &error_abort); 6177 object_property_set_int(obj, "stepping", 3, &error_abort); 6178 } 6179 } 6180 6181 x86_cpu_realizefn(dev, errp); 6182 } 6183 6184 static void max_x86_cpu_class_init(ObjectClass *oc, const void *data) 6185 { 6186 DeviceClass *dc = DEVICE_CLASS(oc); 6187 X86CPUClass *xcc = X86_CPU_CLASS(oc); 6188 6189 xcc->ordering = 9; 6190 6191 xcc->max_features = true; 6192 xcc->model_description = 6193 "Enables all features supported by the accelerator in the current host"; 6194 6195 device_class_set_props(dc, max_x86_cpu_properties); 6196 dc->realize = max_x86_cpu_realize; 6197 } 6198 6199 static void max_x86_cpu_initfn(Object *obj) 6200 { 6201 X86CPU *cpu = X86_CPU(obj); 6202 CPUX86State *env = &cpu->env; 6203 6204 /* 6205 * these defaults are used for TCG, other accelerators have overwritten 6206 * these values 6207 */ 6208 if (!env->cpuid_vendor1) { 6209 object_property_set_str(OBJECT(cpu), "vendor", CPUID_VENDOR_AMD, 6210 &error_abort); 6211 } 6212 if (!env->cpuid_model[0]) { 6213 object_property_set_str(OBJECT(cpu), "model-id", 6214 "QEMU TCG CPU version " QEMU_HW_VERSION, 6215 &error_abort); 6216 } 6217 } 6218 6219 static const TypeInfo max_x86_cpu_type_info = { 6220 .name = X86_CPU_TYPE_NAME("max"), 6221 .parent = TYPE_X86_CPU, 6222 .instance_init = max_x86_cpu_initfn, 6223 .class_init = max_x86_cpu_class_init, 6224 }; 6225 6226 static char *feature_word_description(FeatureWordInfo *f) 6227 { 6228 assert(f->type == CPUID_FEATURE_WORD || f->type == MSR_FEATURE_WORD); 6229 6230 switch (f->type) { 6231 case CPUID_FEATURE_WORD: 6232 { 6233 const char *reg = get_register_name_32(f->cpuid.reg); 6234 assert(reg); 6235 if (!f->cpuid.needs_ecx) { 6236 return g_strdup_printf("CPUID[eax=%02Xh].%s", f->cpuid.eax, reg); 6237 } else { 6238 return g_strdup_printf("CPUID[eax=%02Xh,ecx=%02Xh].%s", 6239 f->cpuid.eax, f->cpuid.ecx, reg); 6240 } 6241 } 6242 case MSR_FEATURE_WORD: 6243 return g_strdup_printf("MSR(%02Xh)", 6244 f->msr.index); 6245 } 6246 6247 return NULL; 6248 } 6249 6250 static bool x86_cpu_have_filtered_features(X86CPU *cpu) 6251 { 6252 FeatureWord w; 6253 6254 for (w = 0; w < FEATURE_WORDS; w++) { 6255 if (cpu->filtered_features[w]) { 6256 return true; 6257 } 6258 } 6259 6260 return false; 6261 } 6262 6263 void mark_unavailable_features(X86CPU *cpu, FeatureWord w, uint64_t mask, 6264 const char *verbose_prefix) 6265 { 6266 CPUX86State *env = &cpu->env; 6267 FeatureWordInfo *f = &feature_word_info[w]; 6268 int i; 6269 g_autofree char *feat_word_str = feature_word_description(f); 6270 6271 if (!cpu->force_features) { 6272 env->features[w] &= ~mask; 6273 } 6274 cpu->filtered_features[w] |= mask; 6275 6276 if (!verbose_prefix) { 6277 return; 6278 } 6279 6280 for (i = 0; i < 64; ++i) { 6281 if ((1ULL << i) & mask) { 6282 warn_report("%s: %s%s%s [bit %d]", 6283 verbose_prefix, 6284 feat_word_str, 6285 f->feat_names[i] ? "." : "", 6286 f->feat_names[i] ? f->feat_names[i] : "", i); 6287 } 6288 } 6289 } 6290 6291 void mark_forced_on_features(X86CPU *cpu, FeatureWord w, uint64_t mask, 6292 const char *verbose_prefix) 6293 { 6294 CPUX86State *env = &cpu->env; 6295 FeatureWordInfo *f = &feature_word_info[w]; 6296 int i; 6297 6298 if (!cpu->force_features) { 6299 env->features[w] |= mask; 6300 } 6301 6302 cpu->forced_on_features[w] |= mask; 6303 6304 if (!verbose_prefix) { 6305 return; 6306 } 6307 6308 for (i = 0; i < 64; ++i) { 6309 if ((1ULL << i) & mask) { 6310 g_autofree char *feat_word_str = feature_word_description(f); 6311 warn_report("%s: %s%s%s [bit %d]", 6312 verbose_prefix, 6313 feat_word_str, 6314 f->feat_names[i] ? "." : "", 6315 f->feat_names[i] ? f->feat_names[i] : "", i); 6316 } 6317 } 6318 } 6319 6320 static void x86_cpuid_version_get_family(Object *obj, Visitor *v, 6321 const char *name, void *opaque, 6322 Error **errp) 6323 { 6324 X86CPU *cpu = X86_CPU(obj); 6325 CPUX86State *env = &cpu->env; 6326 uint64_t value; 6327 6328 value = (env->cpuid_version >> 8) & 0xf; 6329 if (value == 0xf) { 6330 value += (env->cpuid_version >> 20) & 0xff; 6331 } 6332 visit_type_uint64(v, name, &value, errp); 6333 } 6334 6335 static void x86_cpuid_version_set_family(Object *obj, Visitor *v, 6336 const char *name, void *opaque, 6337 Error **errp) 6338 { 6339 X86CPU *cpu = X86_CPU(obj); 6340 CPUX86State *env = &cpu->env; 6341 const uint64_t max = 0xff + 0xf; 6342 uint64_t value; 6343 6344 if (!visit_type_uint64(v, name, &value, errp)) { 6345 return; 6346 } 6347 if (value > max) { 6348 error_setg(errp, "parameter '%s' can be at most %" PRIu64, 6349 name ? name : "null", max); 6350 return; 6351 } 6352 6353 env->cpuid_version &= ~0xff00f00; 6354 if (value > 0x0f) { 6355 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20); 6356 } else { 6357 env->cpuid_version |= value << 8; 6358 } 6359 } 6360 6361 static void x86_cpuid_version_get_model(Object *obj, Visitor *v, 6362 const char *name, void *opaque, 6363 Error **errp) 6364 { 6365 X86CPU *cpu = X86_CPU(obj); 6366 CPUX86State *env = &cpu->env; 6367 uint64_t value; 6368 6369 value = (env->cpuid_version >> 4) & 0xf; 6370 value |= ((env->cpuid_version >> 16) & 0xf) << 4; 6371 visit_type_uint64(v, name, &value, errp); 6372 } 6373 6374 static void x86_cpuid_version_set_model(Object *obj, Visitor *v, 6375 const char *name, void *opaque, 6376 Error **errp) 6377 { 6378 X86CPU *cpu = X86_CPU(obj); 6379 CPUX86State *env = &cpu->env; 6380 const uint64_t max = 0xff; 6381 uint64_t value; 6382 6383 if (!visit_type_uint64(v, name, &value, errp)) { 6384 return; 6385 } 6386 if (value > max) { 6387 error_setg(errp, "parameter '%s' can be at most %" PRIu64, 6388 name ? name : "null", max); 6389 return; 6390 } 6391 6392 env->cpuid_version &= ~0xf00f0; 6393 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16); 6394 } 6395 6396 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v, 6397 const char *name, void *opaque, 6398 Error **errp) 6399 { 6400 X86CPU *cpu = X86_CPU(obj); 6401 CPUX86State *env = &cpu->env; 6402 uint64_t value; 6403 6404 value = env->cpuid_version & 0xf; 6405 visit_type_uint64(v, name, &value, errp); 6406 } 6407 6408 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v, 6409 const char *name, void *opaque, 6410 Error **errp) 6411 { 6412 X86CPU *cpu = X86_CPU(obj); 6413 CPUX86State *env = &cpu->env; 6414 const uint64_t max = 0xf; 6415 uint64_t value; 6416 6417 if (!visit_type_uint64(v, name, &value, errp)) { 6418 return; 6419 } 6420 if (value > max) { 6421 error_setg(errp, "parameter '%s' can be at most %" PRIu64, 6422 name ? name : "null", max); 6423 return; 6424 } 6425 6426 env->cpuid_version &= ~0xf; 6427 env->cpuid_version |= value & 0xf; 6428 } 6429 6430 static char *x86_cpuid_get_vendor(Object *obj, Error **errp) 6431 { 6432 X86CPU *cpu = X86_CPU(obj); 6433 CPUX86State *env = &cpu->env; 6434 char *value; 6435 6436 value = g_malloc(CPUID_VENDOR_SZ + 1); 6437 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2, 6438 env->cpuid_vendor3); 6439 return value; 6440 } 6441 6442 static void x86_cpuid_set_vendor(Object *obj, const char *value, 6443 Error **errp) 6444 { 6445 X86CPU *cpu = X86_CPU(obj); 6446 CPUX86State *env = &cpu->env; 6447 int i; 6448 6449 if (strlen(value) != CPUID_VENDOR_SZ) { 6450 error_setg(errp, "value of property 'vendor' must consist of" 6451 " exactly " stringify(CPUID_VENDOR_SZ) " characters"); 6452 return; 6453 } 6454 6455 env->cpuid_vendor1 = 0; 6456 env->cpuid_vendor2 = 0; 6457 env->cpuid_vendor3 = 0; 6458 for (i = 0; i < 4; i++) { 6459 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i); 6460 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i); 6461 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i); 6462 } 6463 } 6464 6465 static char *x86_cpuid_get_model_id(Object *obj, Error **errp) 6466 { 6467 X86CPU *cpu = X86_CPU(obj); 6468 CPUX86State *env = &cpu->env; 6469 char *value; 6470 int i; 6471 6472 value = g_malloc(48 + 1); 6473 for (i = 0; i < 48; i++) { 6474 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3)); 6475 } 6476 value[48] = '\0'; 6477 return value; 6478 } 6479 6480 static void x86_cpuid_set_model_id(Object *obj, const char *model_id, 6481 Error **errp) 6482 { 6483 X86CPU *cpu = X86_CPU(obj); 6484 CPUX86State *env = &cpu->env; 6485 int c, len, i; 6486 6487 if (model_id == NULL) { 6488 model_id = ""; 6489 } 6490 len = strlen(model_id); 6491 memset(env->cpuid_model, 0, 48); 6492 for (i = 0; i < 48; i++) { 6493 if (i >= len) { 6494 c = '\0'; 6495 } else { 6496 c = (uint8_t)model_id[i]; 6497 } 6498 env->cpuid_model[i >> 2] |= c << (8 * (i & 3)); 6499 } 6500 } 6501 6502 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name, 6503 void *opaque, Error **errp) 6504 { 6505 X86CPU *cpu = X86_CPU(obj); 6506 int64_t value; 6507 6508 value = cpu->env.tsc_khz * 1000; 6509 visit_type_int(v, name, &value, errp); 6510 } 6511 6512 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name, 6513 void *opaque, Error **errp) 6514 { 6515 X86CPU *cpu = X86_CPU(obj); 6516 const int64_t max = INT64_MAX; 6517 int64_t value; 6518 6519 if (!visit_type_int(v, name, &value, errp)) { 6520 return; 6521 } 6522 if (value < 0 || value > max) { 6523 error_setg(errp, "parameter '%s' can be at most %" PRId64, 6524 name ? name : "null", max); 6525 return; 6526 } 6527 6528 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000; 6529 } 6530 6531 /* Generic getter for "feature-words" and "filtered-features" properties */ 6532 static void x86_cpu_get_feature_words(Object *obj, Visitor *v, 6533 const char *name, void *opaque, 6534 Error **errp) 6535 { 6536 uint64_t *array = (uint64_t *)opaque; 6537 FeatureWord w; 6538 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { }; 6539 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { }; 6540 X86CPUFeatureWordInfoList *list = NULL; 6541 6542 for (w = 0; w < FEATURE_WORDS; w++) { 6543 FeatureWordInfo *wi = &feature_word_info[w]; 6544 /* 6545 * We didn't have MSR features when "feature-words" was 6546 * introduced. Therefore skipped other type entries. 6547 */ 6548 if (wi->type != CPUID_FEATURE_WORD) { 6549 continue; 6550 } 6551 X86CPUFeatureWordInfo *qwi = &word_infos[w]; 6552 qwi->cpuid_input_eax = wi->cpuid.eax; 6553 qwi->has_cpuid_input_ecx = wi->cpuid.needs_ecx; 6554 qwi->cpuid_input_ecx = wi->cpuid.ecx; 6555 qwi->cpuid_register = x86_reg_info_32[wi->cpuid.reg].qapi_enum; 6556 qwi->features = array[w]; 6557 6558 /* List will be in reverse order, but order shouldn't matter */ 6559 list_entries[w].next = list; 6560 list_entries[w].value = &word_infos[w]; 6561 list = &list_entries[w]; 6562 } 6563 6564 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp); 6565 } 6566 6567 /* Convert all '_' in a feature string option name to '-', to make feature 6568 * name conform to QOM property naming rule, which uses '-' instead of '_'. 6569 */ 6570 static inline void feat2prop(char *s) 6571 { 6572 while ((s = strchr(s, '_'))) { 6573 *s = '-'; 6574 } 6575 } 6576 6577 /* Return the feature property name for a feature flag bit */ 6578 static const char *x86_cpu_feature_name(FeatureWord w, int bitnr) 6579 { 6580 const char *name; 6581 /* XSAVE components are automatically enabled by other features, 6582 * so return the original feature name instead 6583 */ 6584 if (w == FEAT_XSAVE_XCR0_LO || w == FEAT_XSAVE_XCR0_HI) { 6585 int comp = (w == FEAT_XSAVE_XCR0_HI) ? bitnr + 32 : bitnr; 6586 6587 if (comp < ARRAY_SIZE(x86_ext_save_areas) && 6588 x86_ext_save_areas[comp].bits) { 6589 w = x86_ext_save_areas[comp].feature; 6590 bitnr = ctz32(x86_ext_save_areas[comp].bits); 6591 } 6592 } 6593 6594 assert(bitnr < 64); 6595 assert(w < FEATURE_WORDS); 6596 name = feature_word_info[w].feat_names[bitnr]; 6597 assert(bitnr < 32 || !(name && feature_word_info[w].type == CPUID_FEATURE_WORD)); 6598 return name; 6599 } 6600 6601 /* Compatibility hack to maintain legacy +-feat semantic, 6602 * where +-feat overwrites any feature set by 6603 * feat=on|feat even if the later is parsed after +-feat 6604 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled) 6605 */ 6606 static GList *plus_features, *minus_features; 6607 6608 static gint compare_string(gconstpointer a, gconstpointer b) 6609 { 6610 return g_strcmp0(a, b); 6611 } 6612 6613 /* Parse "+feature,-feature,feature=foo" CPU feature string 6614 */ 6615 static void x86_cpu_parse_featurestr(const char *typename, char *features, 6616 Error **errp) 6617 { 6618 char *featurestr; /* Single 'key=value" string being parsed */ 6619 static bool cpu_globals_initialized; 6620 bool ambiguous = false; 6621 6622 if (cpu_globals_initialized) { 6623 return; 6624 } 6625 cpu_globals_initialized = true; 6626 6627 if (!features) { 6628 return; 6629 } 6630 6631 for (featurestr = strtok(features, ","); 6632 featurestr; 6633 featurestr = strtok(NULL, ",")) { 6634 const char *name; 6635 const char *val = NULL; 6636 char *eq = NULL; 6637 char num[32]; 6638 GlobalProperty *prop; 6639 6640 /* Compatibility syntax: */ 6641 if (featurestr[0] == '+') { 6642 plus_features = g_list_append(plus_features, 6643 g_strdup(featurestr + 1)); 6644 continue; 6645 } else if (featurestr[0] == '-') { 6646 minus_features = g_list_append(minus_features, 6647 g_strdup(featurestr + 1)); 6648 continue; 6649 } 6650 6651 eq = strchr(featurestr, '='); 6652 if (eq) { 6653 *eq++ = 0; 6654 val = eq; 6655 } else { 6656 val = "on"; 6657 } 6658 6659 feat2prop(featurestr); 6660 name = featurestr; 6661 6662 if (g_list_find_custom(plus_features, name, compare_string)) { 6663 warn_report("Ambiguous CPU model string. " 6664 "Don't mix both \"+%s\" and \"%s=%s\"", 6665 name, name, val); 6666 ambiguous = true; 6667 } 6668 if (g_list_find_custom(minus_features, name, compare_string)) { 6669 warn_report("Ambiguous CPU model string. " 6670 "Don't mix both \"-%s\" and \"%s=%s\"", 6671 name, name, val); 6672 ambiguous = true; 6673 } 6674 6675 /* Special case: */ 6676 if (!strcmp(name, "tsc-freq")) { 6677 int ret; 6678 uint64_t tsc_freq; 6679 6680 ret = qemu_strtosz_metric(val, NULL, &tsc_freq); 6681 if (ret < 0 || tsc_freq > INT64_MAX) { 6682 error_setg(errp, "bad numerical value %s", val); 6683 return; 6684 } 6685 snprintf(num, sizeof(num), "%" PRId64, tsc_freq); 6686 val = num; 6687 name = "tsc-frequency"; 6688 } 6689 6690 prop = g_new0(typeof(*prop), 1); 6691 prop->driver = typename; 6692 prop->property = g_strdup(name); 6693 prop->value = g_strdup(val); 6694 qdev_prop_register_global(prop); 6695 } 6696 6697 if (ambiguous) { 6698 warn_report("Compatibility of ambiguous CPU model " 6699 "strings won't be kept on future QEMU versions"); 6700 } 6701 } 6702 6703 static bool x86_cpu_filter_features(X86CPU *cpu, bool verbose); 6704 6705 /* Build a list with the name of all features on a feature word array */ 6706 static void x86_cpu_list_feature_names(FeatureWordArray features, 6707 strList **list) 6708 { 6709 strList **tail = list; 6710 FeatureWord w; 6711 6712 for (w = 0; w < FEATURE_WORDS; w++) { 6713 uint64_t filtered = features[w]; 6714 int i; 6715 for (i = 0; i < 64; i++) { 6716 if (filtered & (1ULL << i)) { 6717 QAPI_LIST_APPEND(tail, g_strdup(x86_cpu_feature_name(w, i))); 6718 } 6719 } 6720 } 6721 } 6722 6723 static void x86_cpu_get_unavailable_features(Object *obj, Visitor *v, 6724 const char *name, void *opaque, 6725 Error **errp) 6726 { 6727 X86CPU *xc = X86_CPU(obj); 6728 strList *result = NULL; 6729 6730 x86_cpu_list_feature_names(xc->filtered_features, &result); 6731 visit_type_strList(v, "unavailable-features", &result, errp); 6732 } 6733 6734 /* Print all cpuid feature names in featureset 6735 */ 6736 static void listflags(GList *features) 6737 { 6738 size_t len = 0; 6739 GList *tmp; 6740 6741 for (tmp = features; tmp; tmp = tmp->next) { 6742 const char *name = tmp->data; 6743 if ((len + strlen(name) + 1) >= 75) { 6744 qemu_printf("\n"); 6745 len = 0; 6746 } 6747 qemu_printf("%s%s", len == 0 ? " " : " ", name); 6748 len += strlen(name) + 1; 6749 } 6750 qemu_printf("\n"); 6751 } 6752 6753 /* Sort alphabetically by type name, respecting X86CPUClass::ordering. */ 6754 static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b, gpointer d) 6755 { 6756 ObjectClass *class_a = (ObjectClass *)a; 6757 ObjectClass *class_b = (ObjectClass *)b; 6758 X86CPUClass *cc_a = X86_CPU_CLASS(class_a); 6759 X86CPUClass *cc_b = X86_CPU_CLASS(class_b); 6760 int ret; 6761 6762 if (cc_a->ordering != cc_b->ordering) { 6763 ret = cc_a->ordering - cc_b->ordering; 6764 } else { 6765 g_autofree char *name_a = x86_cpu_class_get_model_name(cc_a); 6766 g_autofree char *name_b = x86_cpu_class_get_model_name(cc_b); 6767 ret = strcmp(name_a, name_b); 6768 } 6769 return ret; 6770 } 6771 6772 static GSList *get_sorted_cpu_model_list(void) 6773 { 6774 GSList *list = object_class_get_list(TYPE_X86_CPU, false); 6775 list = g_slist_sort_with_data(list, x86_cpu_list_compare, NULL); 6776 return list; 6777 } 6778 6779 static char *x86_cpu_class_get_model_id(X86CPUClass *xc) 6780 { 6781 Object *obj = object_new_with_class(OBJECT_CLASS(xc)); 6782 char *r = object_property_get_str(obj, "model-id", &error_abort); 6783 object_unref(obj); 6784 return r; 6785 } 6786 6787 static char *x86_cpu_class_get_alias_of(X86CPUClass *cc) 6788 { 6789 X86CPUVersion version; 6790 6791 if (!cc->model || !cc->model->is_alias) { 6792 return NULL; 6793 } 6794 version = x86_cpu_model_resolve_version(cc->model); 6795 if (version <= 0) { 6796 return NULL; 6797 } 6798 return x86_cpu_versioned_model_name(cc->model->cpudef, version); 6799 } 6800 6801 static void x86_cpu_list_entry(gpointer data, gpointer user_data) 6802 { 6803 ObjectClass *oc = data; 6804 X86CPUClass *cc = X86_CPU_CLASS(oc); 6805 g_autofree char *name = x86_cpu_class_get_model_name(cc); 6806 g_autofree char *desc = g_strdup(cc->model_description); 6807 g_autofree char *alias_of = x86_cpu_class_get_alias_of(cc); 6808 g_autofree char *model_id = x86_cpu_class_get_model_id(cc); 6809 6810 if (!desc && alias_of) { 6811 if (cc->model && cc->model->version == CPU_VERSION_AUTO) { 6812 desc = g_strdup("(alias configured by machine type)"); 6813 } else { 6814 desc = g_strdup_printf("(alias of %s)", alias_of); 6815 } 6816 } 6817 if (!desc && cc->model && cc->model->note) { 6818 desc = g_strdup_printf("%s [%s]", model_id, cc->model->note); 6819 } 6820 if (!desc) { 6821 desc = g_strdup(model_id); 6822 } 6823 6824 if (cc->model && cc->model->cpudef->deprecation_note) { 6825 g_autofree char *olddesc = desc; 6826 desc = g_strdup_printf("%s (deprecated)", olddesc); 6827 } 6828 6829 qemu_printf(" %-20s %s\n", name, desc); 6830 } 6831 6832 static gint strcmp_wrap(gconstpointer a, gconstpointer b, gpointer d) 6833 { 6834 return strcmp(a, b); 6835 } 6836 6837 /* list available CPU models and flags */ 6838 static void x86_cpu_list(void) 6839 { 6840 int i, j; 6841 GSList *list; 6842 GList *names = NULL; 6843 6844 qemu_printf("Available CPUs:\n"); 6845 list = get_sorted_cpu_model_list(); 6846 g_slist_foreach(list, x86_cpu_list_entry, NULL); 6847 g_slist_free(list); 6848 6849 names = NULL; 6850 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) { 6851 FeatureWordInfo *fw = &feature_word_info[i]; 6852 for (j = 0; j < 64; j++) { 6853 if (fw->feat_names[j]) { 6854 names = g_list_append(names, (gpointer)fw->feat_names[j]); 6855 } 6856 } 6857 } 6858 6859 names = g_list_sort_with_data(names, strcmp_wrap, NULL); 6860 6861 qemu_printf("\nRecognized CPUID flags:\n"); 6862 listflags(names); 6863 qemu_printf("\n"); 6864 g_list_free(names); 6865 } 6866 6867 #ifndef CONFIG_USER_ONLY 6868 6869 /* Check for missing features that may prevent the CPU class from 6870 * running using the current machine and accelerator. 6871 */ 6872 static void x86_cpu_class_check_missing_features(X86CPUClass *xcc, 6873 strList **list) 6874 { 6875 strList **tail = list; 6876 X86CPU *xc; 6877 Error *err = NULL; 6878 6879 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) { 6880 QAPI_LIST_APPEND(tail, g_strdup("kvm")); 6881 return; 6882 } 6883 6884 xc = X86_CPU(object_new_with_class(OBJECT_CLASS(xcc))); 6885 6886 x86_cpu_expand_features(xc, &err); 6887 if (err) { 6888 /* Errors at x86_cpu_expand_features should never happen, 6889 * but in case it does, just report the model as not 6890 * runnable at all using the "type" property. 6891 */ 6892 QAPI_LIST_APPEND(tail, g_strdup("type")); 6893 error_free(err); 6894 } 6895 6896 x86_cpu_filter_features(xc, false); 6897 6898 x86_cpu_list_feature_names(xc->filtered_features, tail); 6899 6900 object_unref(OBJECT(xc)); 6901 } 6902 6903 static void x86_cpu_definition_entry(gpointer data, gpointer user_data) 6904 { 6905 ObjectClass *oc = data; 6906 X86CPUClass *cc = X86_CPU_CLASS(oc); 6907 CpuDefinitionInfoList **cpu_list = user_data; 6908 CpuDefinitionInfo *info; 6909 6910 info = g_malloc0(sizeof(*info)); 6911 info->name = x86_cpu_class_get_model_name(cc); 6912 x86_cpu_class_check_missing_features(cc, &info->unavailable_features); 6913 info->has_unavailable_features = true; 6914 info->q_typename = g_strdup(object_class_get_name(oc)); 6915 info->migration_safe = cc->migration_safe; 6916 info->has_migration_safe = true; 6917 info->q_static = cc->static_model; 6918 if (cc->model && cc->model->cpudef->deprecation_note) { 6919 info->deprecated = true; 6920 } else { 6921 info->deprecated = false; 6922 } 6923 /* 6924 * Old machine types won't report aliases, so that alias translation 6925 * doesn't break compatibility with previous QEMU versions. 6926 */ 6927 if (default_cpu_version != CPU_VERSION_LEGACY) { 6928 info->alias_of = x86_cpu_class_get_alias_of(cc); 6929 } 6930 6931 QAPI_LIST_PREPEND(*cpu_list, info); 6932 } 6933 6934 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) 6935 { 6936 CpuDefinitionInfoList *cpu_list = NULL; 6937 GSList *list = get_sorted_cpu_model_list(); 6938 g_slist_foreach(list, x86_cpu_definition_entry, &cpu_list); 6939 g_slist_free(list); 6940 return cpu_list; 6941 } 6942 6943 #endif /* !CONFIG_USER_ONLY */ 6944 6945 uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w) 6946 { 6947 FeatureWordInfo *wi = &feature_word_info[w]; 6948 uint64_t r = 0; 6949 uint64_t unavail = 0; 6950 6951 if (kvm_enabled()) { 6952 switch (wi->type) { 6953 case CPUID_FEATURE_WORD: 6954 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid.eax, 6955 wi->cpuid.ecx, 6956 wi->cpuid.reg); 6957 break; 6958 case MSR_FEATURE_WORD: 6959 r = kvm_arch_get_supported_msr_feature(kvm_state, 6960 wi->msr.index); 6961 break; 6962 } 6963 } else if (hvf_enabled()) { 6964 if (wi->type != CPUID_FEATURE_WORD) { 6965 return 0; 6966 } 6967 r = hvf_get_supported_cpuid(wi->cpuid.eax, 6968 wi->cpuid.ecx, 6969 wi->cpuid.reg); 6970 } else if (tcg_enabled()) { 6971 r = wi->tcg_features; 6972 } else { 6973 return ~0; 6974 } 6975 6976 switch (w) { 6977 #ifndef TARGET_X86_64 6978 case FEAT_8000_0001_EDX: 6979 /* 6980 * 32-bit TCG can emulate 64-bit compatibility mode. If there is no 6981 * way for userspace to get out of its 32-bit jail, we can leave 6982 * the LM bit set. 6983 */ 6984 unavail = tcg_enabled() 6985 ? CPUID_EXT2_LM & ~CPUID_EXT2_KERNEL_FEATURES 6986 : CPUID_EXT2_LM; 6987 break; 6988 #endif 6989 6990 case FEAT_8000_0007_EBX: 6991 if (cpu && !IS_AMD_CPU(&cpu->env)) { 6992 /* Disable AMD machine check architecture for Intel CPU. */ 6993 unavail = ~0; 6994 } 6995 break; 6996 6997 case FEAT_7_0_EBX: 6998 #ifndef CONFIG_USER_ONLY 6999 if (!check_sgx_support()) { 7000 unavail = CPUID_7_0_EBX_SGX; 7001 } 7002 #endif 7003 break; 7004 case FEAT_7_0_ECX: 7005 #ifndef CONFIG_USER_ONLY 7006 if (!check_sgx_support()) { 7007 unavail = CPUID_7_0_ECX_SGX_LC; 7008 } 7009 #endif 7010 break; 7011 7012 default: 7013 break; 7014 } 7015 7016 r &= ~unavail; 7017 if (cpu && cpu->migratable) { 7018 r &= x86_cpu_get_migratable_flags(cpu, w); 7019 } 7020 return r; 7021 } 7022 7023 static void x86_cpu_get_supported_cpuid(uint32_t func, uint32_t index, 7024 uint32_t *eax, uint32_t *ebx, 7025 uint32_t *ecx, uint32_t *edx) 7026 { 7027 if (kvm_enabled()) { 7028 *eax = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EAX); 7029 *ebx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EBX); 7030 *ecx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_ECX); 7031 *edx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EDX); 7032 } else if (hvf_enabled()) { 7033 *eax = hvf_get_supported_cpuid(func, index, R_EAX); 7034 *ebx = hvf_get_supported_cpuid(func, index, R_EBX); 7035 *ecx = hvf_get_supported_cpuid(func, index, R_ECX); 7036 *edx = hvf_get_supported_cpuid(func, index, R_EDX); 7037 } else { 7038 *eax = 0; 7039 *ebx = 0; 7040 *ecx = 0; 7041 *edx = 0; 7042 } 7043 } 7044 7045 static void x86_cpu_get_cache_cpuid(uint32_t func, uint32_t index, 7046 uint32_t *eax, uint32_t *ebx, 7047 uint32_t *ecx, uint32_t *edx) 7048 { 7049 uint32_t level, unused; 7050 7051 /* Only return valid host leaves. */ 7052 switch (func) { 7053 case 2: 7054 case 4: 7055 host_cpuid(0, 0, &level, &unused, &unused, &unused); 7056 break; 7057 case 0x80000005: 7058 case 0x80000006: 7059 case 0x8000001d: 7060 host_cpuid(0x80000000, 0, &level, &unused, &unused, &unused); 7061 break; 7062 default: 7063 return; 7064 } 7065 7066 if (func > level) { 7067 *eax = 0; 7068 *ebx = 0; 7069 *ecx = 0; 7070 *edx = 0; 7071 } else { 7072 host_cpuid(func, index, eax, ebx, ecx, edx); 7073 } 7074 } 7075 7076 /* 7077 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 7078 */ 7079 void x86_cpu_apply_props(X86CPU *cpu, PropValue *props) 7080 { 7081 PropValue *pv; 7082 for (pv = props; pv->prop; pv++) { 7083 if (!pv->value) { 7084 continue; 7085 } 7086 object_property_parse(OBJECT(cpu), pv->prop, pv->value, 7087 &error_abort); 7088 } 7089 } 7090 7091 /* 7092 * Apply properties for the CPU model version specified in model. 7093 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 7094 */ 7095 7096 static void x86_cpu_apply_version_props(X86CPU *cpu, const X86CPUModel *model) 7097 { 7098 const X86CPUVersionDefinition *vdef; 7099 X86CPUVersion version = x86_cpu_model_resolve_version(model); 7100 7101 if (version == CPU_VERSION_LEGACY) { 7102 return; 7103 } 7104 7105 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) { 7106 PropValue *p; 7107 7108 for (p = vdef->props; p && p->prop; p++) { 7109 object_property_parse(OBJECT(cpu), p->prop, p->value, 7110 &error_abort); 7111 } 7112 7113 if (vdef->version == version) { 7114 break; 7115 } 7116 } 7117 7118 /* 7119 * If we reached the end of the list, version number was invalid 7120 */ 7121 assert(vdef->version == version); 7122 } 7123 7124 static const CPUCaches *x86_cpu_get_versioned_cache_info(X86CPU *cpu, 7125 const X86CPUModel *model) 7126 { 7127 const X86CPUVersionDefinition *vdef; 7128 X86CPUVersion version = x86_cpu_model_resolve_version(model); 7129 const CPUCaches *cache_info = model->cpudef->cache_info; 7130 7131 if (version == CPU_VERSION_LEGACY) { 7132 return cache_info; 7133 } 7134 7135 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) { 7136 if (vdef->cache_info) { 7137 cache_info = vdef->cache_info; 7138 } 7139 7140 if (vdef->version == version) { 7141 break; 7142 } 7143 } 7144 7145 assert(vdef->version == version); 7146 return cache_info; 7147 } 7148 7149 /* 7150 * Load data from X86CPUDefinition into a X86CPU object. 7151 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 7152 */ 7153 static void x86_cpu_load_model(X86CPU *cpu, const X86CPUModel *model) 7154 { 7155 const X86CPUDefinition *def = model->cpudef; 7156 CPUX86State *env = &cpu->env; 7157 FeatureWord w; 7158 7159 /*NOTE: any property set by this function should be returned by 7160 * x86_cpu_static_props(), so static expansion of 7161 * query-cpu-model-expansion is always complete. 7162 */ 7163 7164 /* CPU models only set _minimum_ values for level/xlevel: */ 7165 object_property_set_uint(OBJECT(cpu), "min-level", def->level, 7166 &error_abort); 7167 object_property_set_uint(OBJECT(cpu), "min-xlevel", def->xlevel, 7168 &error_abort); 7169 7170 object_property_set_int(OBJECT(cpu), "family", def->family, &error_abort); 7171 object_property_set_int(OBJECT(cpu), "model", def->model, &error_abort); 7172 object_property_set_int(OBJECT(cpu), "stepping", def->stepping, 7173 &error_abort); 7174 object_property_set_str(OBJECT(cpu), "model-id", def->model_id, 7175 &error_abort); 7176 for (w = 0; w < FEATURE_WORDS; w++) { 7177 env->features[w] = def->features[w]; 7178 } 7179 7180 /* legacy-cache defaults to 'off' if CPU model provides cache info */ 7181 cpu->legacy_cache = !x86_cpu_get_versioned_cache_info(cpu, model); 7182 7183 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR; 7184 7185 /* sysenter isn't supported in compatibility mode on AMD, 7186 * syscall isn't supported in compatibility mode on Intel. 7187 * Normally we advertise the actual CPU vendor, but you can 7188 * override this using the 'vendor' property if you want to use 7189 * KVM's sysenter/syscall emulation in compatibility mode and 7190 * when doing cross vendor migration 7191 */ 7192 7193 /* 7194 * vendor property is set here but then overloaded with the 7195 * host cpu vendor for KVM and HVF. 7196 */ 7197 object_property_set_str(OBJECT(cpu), "vendor", def->vendor, &error_abort); 7198 7199 object_property_set_uint(OBJECT(cpu), "avx10-version", def->avx10_version, 7200 &error_abort); 7201 7202 x86_cpu_apply_version_props(cpu, model); 7203 7204 /* 7205 * Properties in versioned CPU model are not user specified features. 7206 * We can simply clear env->user_features here since it will be filled later 7207 * in x86_cpu_expand_features() based on plus_features and minus_features. 7208 */ 7209 memset(&env->user_features, 0, sizeof(env->user_features)); 7210 } 7211 7212 static const gchar *x86_gdb_arch_name(CPUState *cs) 7213 { 7214 #ifdef TARGET_X86_64 7215 return "i386:x86-64"; 7216 #else 7217 return "i386"; 7218 #endif 7219 } 7220 7221 static void x86_cpu_cpudef_class_init(ObjectClass *oc, const void *data) 7222 { 7223 const X86CPUModel *model = data; 7224 X86CPUClass *xcc = X86_CPU_CLASS(oc); 7225 CPUClass *cc = CPU_CLASS(oc); 7226 7227 xcc->model = model; 7228 xcc->migration_safe = true; 7229 cc->deprecation_note = model->cpudef->deprecation_note; 7230 } 7231 7232 static void x86_register_cpu_model_type(const char *name, X86CPUModel *model) 7233 { 7234 g_autofree char *typename = x86_cpu_type_name(name); 7235 TypeInfo ti = { 7236 .name = typename, 7237 .parent = TYPE_X86_CPU, 7238 .class_init = x86_cpu_cpudef_class_init, 7239 .class_data = model, 7240 }; 7241 7242 type_register_static(&ti); 7243 } 7244 7245 7246 /* 7247 * register builtin_x86_defs; 7248 * "max", "base" and subclasses ("host") are not registered here. 7249 * See x86_cpu_register_types for all model registrations. 7250 */ 7251 static void x86_register_cpudef_types(const X86CPUDefinition *def) 7252 { 7253 X86CPUModel *m; 7254 const X86CPUVersionDefinition *vdef; 7255 7256 /* AMD aliases are handled at runtime based on CPUID vendor, so 7257 * they shouldn't be set on the CPU model table. 7258 */ 7259 assert(!(def->features[FEAT_8000_0001_EDX] & CPUID_EXT2_AMD_ALIASES)); 7260 /* catch mistakes instead of silently truncating model_id when too long */ 7261 assert(def->model_id && strlen(def->model_id) <= 48); 7262 7263 /* Unversioned model: */ 7264 m = g_new0(X86CPUModel, 1); 7265 m->cpudef = def; 7266 m->version = CPU_VERSION_AUTO; 7267 m->is_alias = true; 7268 x86_register_cpu_model_type(def->name, m); 7269 7270 /* Versioned models: */ 7271 7272 for (vdef = x86_cpu_def_get_versions(def); vdef->version; vdef++) { 7273 g_autofree char *name = 7274 x86_cpu_versioned_model_name(def, vdef->version); 7275 7276 m = g_new0(X86CPUModel, 1); 7277 m->cpudef = def; 7278 m->version = vdef->version; 7279 m->note = vdef->note; 7280 x86_register_cpu_model_type(name, m); 7281 7282 if (vdef->alias) { 7283 X86CPUModel *am = g_new0(X86CPUModel, 1); 7284 am->cpudef = def; 7285 am->version = vdef->version; 7286 am->is_alias = true; 7287 x86_register_cpu_model_type(vdef->alias, am); 7288 } 7289 } 7290 7291 } 7292 7293 uint32_t cpu_x86_virtual_addr_width(CPUX86State *env) 7294 { 7295 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57) { 7296 return 57; /* 57 bits virtual */ 7297 } else { 7298 return 48; /* 48 bits virtual */ 7299 } 7300 } 7301 7302 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, 7303 uint32_t *eax, uint32_t *ebx, 7304 uint32_t *ecx, uint32_t *edx) 7305 { 7306 X86CPU *cpu = env_archcpu(env); 7307 CPUState *cs = env_cpu(env); 7308 uint32_t limit; 7309 uint32_t signature[3]; 7310 X86CPUTopoInfo *topo_info = &env->topo_info; 7311 uint32_t threads_per_pkg; 7312 7313 threads_per_pkg = x86_threads_per_pkg(topo_info); 7314 7315 /* Calculate & apply limits for different index ranges */ 7316 if (index >= 0xC0000000) { 7317 limit = env->cpuid_xlevel2; 7318 } else if (index >= 0x80000000) { 7319 limit = env->cpuid_xlevel; 7320 } else if (index >= 0x40000000) { 7321 limit = 0x40000001; 7322 } else { 7323 limit = env->cpuid_level; 7324 } 7325 7326 if (index > limit) { 7327 /* Intel documentation states that invalid EAX input will 7328 * return the same information as EAX=cpuid_level 7329 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID) 7330 */ 7331 index = env->cpuid_level; 7332 } 7333 7334 switch(index) { 7335 case 0: 7336 *eax = env->cpuid_level; 7337 *ebx = env->cpuid_vendor1; 7338 *edx = env->cpuid_vendor2; 7339 *ecx = env->cpuid_vendor3; 7340 break; 7341 case 1: 7342 *eax = env->cpuid_version; 7343 *ebx = (cpu->apic_id << 24) | 7344 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */ 7345 *ecx = env->features[FEAT_1_ECX]; 7346 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) { 7347 *ecx |= CPUID_EXT_OSXSAVE; 7348 } 7349 *edx = env->features[FEAT_1_EDX]; 7350 if (threads_per_pkg > 1) { 7351 *ebx |= threads_per_pkg << 16; 7352 } 7353 break; 7354 case 2: 7355 /* cache info: needed for Pentium Pro compatibility */ 7356 if (cpu->cache_info_passthrough) { 7357 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 7358 break; 7359 } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { 7360 *eax = *ebx = *ecx = *edx = 0; 7361 break; 7362 } 7363 *eax = 1; /* Number of CPUID[EAX=2] calls required */ 7364 *ebx = 0; 7365 if (!cpu->enable_l3_cache) { 7366 *ecx = 0; 7367 } else { 7368 *ecx = cpuid2_cache_descriptor(env->cache_info_cpuid2.l3_cache); 7369 } 7370 *edx = (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1d_cache) << 16) | 7371 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1i_cache) << 8) | 7372 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l2_cache)); 7373 break; 7374 case 4: 7375 /* cache info: needed for Core compatibility */ 7376 if (cpu->cache_info_passthrough) { 7377 x86_cpu_get_cache_cpuid(index, count, eax, ebx, ecx, edx); 7378 /* 7379 * QEMU has its own number of cores/logical cpus, 7380 * set 24..14, 31..26 bit to configured values 7381 */ 7382 if (*eax & 31) { 7383 int host_vcpus_per_cache = 1 + ((*eax & 0x3FFC000) >> 14); 7384 7385 *eax &= ~0xFC000000; 7386 *eax |= max_core_ids_in_package(topo_info) << 26; 7387 if (host_vcpus_per_cache > threads_per_pkg) { 7388 *eax &= ~0x3FFC000; 7389 7390 /* Share the cache at package level. */ 7391 *eax |= max_thread_ids_for_cache(topo_info, 7392 CPU_TOPOLOGY_LEVEL_SOCKET) << 14; 7393 } 7394 } 7395 } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { 7396 *eax = *ebx = *ecx = *edx = 0; 7397 } else { 7398 *eax = 0; 7399 7400 switch (count) { 7401 case 0: /* L1 dcache info */ 7402 encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache, 7403 topo_info, 7404 eax, ebx, ecx, edx); 7405 if (!cpu->l1_cache_per_core) { 7406 *eax &= ~MAKE_64BIT_MASK(14, 12); 7407 } 7408 break; 7409 case 1: /* L1 icache info */ 7410 encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache, 7411 topo_info, 7412 eax, ebx, ecx, edx); 7413 if (!cpu->l1_cache_per_core) { 7414 *eax &= ~MAKE_64BIT_MASK(14, 12); 7415 } 7416 break; 7417 case 2: /* L2 cache info */ 7418 encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache, 7419 topo_info, 7420 eax, ebx, ecx, edx); 7421 break; 7422 case 3: /* L3 cache info */ 7423 if (cpu->enable_l3_cache) { 7424 encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache, 7425 topo_info, 7426 eax, ebx, ecx, edx); 7427 break; 7428 } 7429 /* fall through */ 7430 default: /* end of info */ 7431 *eax = *ebx = *ecx = *edx = 0; 7432 break; 7433 } 7434 } 7435 break; 7436 case 5: 7437 /* MONITOR/MWAIT Leaf */ 7438 *eax = cpu->mwait.eax; /* Smallest monitor-line size in bytes */ 7439 *ebx = cpu->mwait.ebx; /* Largest monitor-line size in bytes */ 7440 *ecx = cpu->mwait.ecx; /* flags */ 7441 *edx = cpu->mwait.edx; /* mwait substates */ 7442 break; 7443 case 6: 7444 /* Thermal and Power Leaf */ 7445 *eax = env->features[FEAT_6_EAX]; 7446 *ebx = 0; 7447 *ecx = 0; 7448 *edx = 0; 7449 break; 7450 case 7: 7451 /* Structured Extended Feature Flags Enumeration Leaf */ 7452 if (count == 0) { 7453 /* Maximum ECX value for sub-leaves */ 7454 *eax = env->cpuid_level_func7; 7455 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */ 7456 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */ 7457 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) { 7458 *ecx |= CPUID_7_0_ECX_OSPKE; 7459 } 7460 *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */ 7461 } else if (count == 1) { 7462 *eax = env->features[FEAT_7_1_EAX]; 7463 *ecx = env->features[FEAT_7_1_ECX]; 7464 *edx = env->features[FEAT_7_1_EDX]; 7465 *ebx = 0; 7466 } else if (count == 2) { 7467 *edx = env->features[FEAT_7_2_EDX]; 7468 *eax = 0; 7469 *ebx = 0; 7470 *ecx = 0; 7471 } else { 7472 *eax = 0; 7473 *ebx = 0; 7474 *ecx = 0; 7475 *edx = 0; 7476 } 7477 break; 7478 case 9: 7479 /* Direct Cache Access Information Leaf */ 7480 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */ 7481 *ebx = 0; 7482 *ecx = 0; 7483 *edx = 0; 7484 break; 7485 case 0xA: 7486 /* Architectural Performance Monitoring Leaf */ 7487 if (cpu->enable_pmu) { 7488 x86_cpu_get_supported_cpuid(0xA, count, eax, ebx, ecx, edx); 7489 } else { 7490 *eax = 0; 7491 *ebx = 0; 7492 *ecx = 0; 7493 *edx = 0; 7494 } 7495 break; 7496 case 0xB: 7497 /* Extended Topology Enumeration Leaf */ 7498 if (!cpu->enable_cpuid_0xb) { 7499 *eax = *ebx = *ecx = *edx = 0; 7500 break; 7501 } 7502 7503 *ecx = count & 0xff; 7504 *edx = cpu->apic_id; 7505 7506 switch (count) { 7507 case 0: 7508 *eax = apicid_core_offset(topo_info); 7509 *ebx = topo_info->threads_per_core; 7510 *ecx |= CPUID_B_ECX_TOPO_LEVEL_SMT << 8; 7511 break; 7512 case 1: 7513 *eax = apicid_pkg_offset(topo_info); 7514 *ebx = threads_per_pkg; 7515 *ecx |= CPUID_B_ECX_TOPO_LEVEL_CORE << 8; 7516 break; 7517 default: 7518 *eax = 0; 7519 *ebx = 0; 7520 *ecx |= CPUID_B_ECX_TOPO_LEVEL_INVALID << 8; 7521 } 7522 7523 assert(!(*eax & ~0x1f)); 7524 *ebx &= 0xffff; /* The count doesn't need to be reliable. */ 7525 break; 7526 case 0x1C: 7527 if (cpu->enable_pmu && (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) { 7528 x86_cpu_get_supported_cpuid(0x1C, 0, eax, ebx, ecx, edx); 7529 *edx = 0; 7530 } 7531 break; 7532 case 0x1F: 7533 /* V2 Extended Topology Enumeration Leaf */ 7534 if (!x86_has_cpuid_0x1f(cpu)) { 7535 *eax = *ebx = *ecx = *edx = 0; 7536 break; 7537 } 7538 7539 encode_topo_cpuid1f(env, count, topo_info, eax, ebx, ecx, edx); 7540 break; 7541 case 0xD: { 7542 /* Processor Extended State */ 7543 *eax = 0; 7544 *ebx = 0; 7545 *ecx = 0; 7546 *edx = 0; 7547 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { 7548 break; 7549 } 7550 7551 if (count == 0) { 7552 *ecx = xsave_area_size(x86_cpu_xsave_xcr0_components(cpu), false); 7553 *eax = env->features[FEAT_XSAVE_XCR0_LO]; 7554 *edx = env->features[FEAT_XSAVE_XCR0_HI]; 7555 /* 7556 * The initial value of xcr0 and ebx == 0, On host without kvm 7557 * commit 412a3c41(e.g., CentOS 6), the ebx's value always == 0 7558 * even through guest update xcr0, this will crash some legacy guest 7559 * (e.g., CentOS 6), So set ebx == ecx to workaround it. 7560 */ 7561 *ebx = kvm_enabled() ? *ecx : xsave_area_size(env->xcr0, false); 7562 } else if (count == 1) { 7563 uint64_t xstate = x86_cpu_xsave_xcr0_components(cpu) | 7564 x86_cpu_xsave_xss_components(cpu); 7565 7566 *eax = env->features[FEAT_XSAVE]; 7567 *ebx = xsave_area_size(xstate, true); 7568 *ecx = env->features[FEAT_XSAVE_XSS_LO]; 7569 *edx = env->features[FEAT_XSAVE_XSS_HI]; 7570 if (kvm_enabled() && cpu->enable_pmu && 7571 (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR) && 7572 (*eax & CPUID_XSAVE_XSAVES)) { 7573 *ecx |= XSTATE_ARCH_LBR_MASK; 7574 } else { 7575 *ecx &= ~XSTATE_ARCH_LBR_MASK; 7576 } 7577 } else if (count == 0xf && cpu->enable_pmu 7578 && (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) { 7579 x86_cpu_get_supported_cpuid(0xD, count, eax, ebx, ecx, edx); 7580 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) { 7581 const ExtSaveArea *esa = &x86_ext_save_areas[count]; 7582 7583 if (x86_cpu_xsave_xcr0_components(cpu) & (1ULL << count)) { 7584 *eax = esa->size; 7585 *ebx = esa->offset; 7586 *ecx = esa->ecx & 7587 (ESA_FEATURE_ALIGN64_MASK | ESA_FEATURE_XFD_MASK); 7588 } else if (x86_cpu_xsave_xss_components(cpu) & (1ULL << count)) { 7589 *eax = esa->size; 7590 *ebx = 0; 7591 *ecx = 1; 7592 } 7593 } 7594 break; 7595 } 7596 case 0x12: 7597 #ifndef CONFIG_USER_ONLY 7598 if (!kvm_enabled() || 7599 !(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX)) { 7600 *eax = *ebx = *ecx = *edx = 0; 7601 break; 7602 } 7603 7604 /* 7605 * SGX sub-leafs CPUID.0x12.{0x2..N} enumerate EPC sections. Retrieve 7606 * the EPC properties, e.g. confidentiality and integrity, from the 7607 * host's first EPC section, i.e. assume there is one EPC section or 7608 * that all EPC sections have the same security properties. 7609 */ 7610 if (count > 1) { 7611 uint64_t epc_addr, epc_size; 7612 7613 if (sgx_epc_get_section(count - 2, &epc_addr, &epc_size)) { 7614 *eax = *ebx = *ecx = *edx = 0; 7615 break; 7616 } 7617 host_cpuid(index, 2, eax, ebx, ecx, edx); 7618 *eax = (uint32_t)(epc_addr & 0xfffff000) | 0x1; 7619 *ebx = (uint32_t)(epc_addr >> 32); 7620 *ecx = (uint32_t)(epc_size & 0xfffff000) | (*ecx & 0xf); 7621 *edx = (uint32_t)(epc_size >> 32); 7622 break; 7623 } 7624 7625 /* 7626 * SGX sub-leafs CPUID.0x12.{0x0,0x1} are heavily dependent on hardware 7627 * and KVM, i.e. QEMU cannot emulate features to override what KVM 7628 * supports. Features can be further restricted by userspace, but not 7629 * made more permissive. 7630 */ 7631 x86_cpu_get_supported_cpuid(0x12, count, eax, ebx, ecx, edx); 7632 7633 if (count == 0) { 7634 *eax &= env->features[FEAT_SGX_12_0_EAX]; 7635 *ebx &= env->features[FEAT_SGX_12_0_EBX]; 7636 } else { 7637 *eax &= env->features[FEAT_SGX_12_1_EAX]; 7638 *ebx &= 0; /* ebx reserve */ 7639 *ecx &= env->features[FEAT_XSAVE_XCR0_LO]; 7640 *edx &= env->features[FEAT_XSAVE_XCR0_HI]; 7641 7642 /* FP and SSE are always allowed regardless of XSAVE/XCR0. */ 7643 *ecx |= XSTATE_FP_MASK | XSTATE_SSE_MASK; 7644 7645 /* Access to PROVISIONKEY requires additional credentials. */ 7646 if ((*eax & (1U << 4)) && 7647 !kvm_enable_sgx_provisioning(cs->kvm_state)) { 7648 *eax &= ~(1U << 4); 7649 } 7650 } 7651 #endif 7652 break; 7653 case 0x14: { 7654 /* Intel Processor Trace Enumeration */ 7655 *eax = 0; 7656 *ebx = 0; 7657 *ecx = 0; 7658 *edx = 0; 7659 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) || 7660 !kvm_enabled()) { 7661 break; 7662 } 7663 7664 /* 7665 * If these are changed, they should stay in sync with 7666 * x86_cpu_filter_features(). 7667 */ 7668 if (count == 0) { 7669 *eax = INTEL_PT_MAX_SUBLEAF; 7670 *ebx = INTEL_PT_MINIMAL_EBX; 7671 *ecx = INTEL_PT_MINIMAL_ECX; 7672 if (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP) { 7673 *ecx |= CPUID_14_0_ECX_LIP; 7674 } 7675 } else if (count == 1) { 7676 *eax = INTEL_PT_MTC_BITMAP | INTEL_PT_ADDR_RANGES_NUM; 7677 *ebx = INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP; 7678 } 7679 break; 7680 } 7681 case 0x1D: { 7682 /* AMX TILE, for now hardcoded for Sapphire Rapids*/ 7683 *eax = 0; 7684 *ebx = 0; 7685 *ecx = 0; 7686 *edx = 0; 7687 if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) { 7688 break; 7689 } 7690 7691 if (count == 0) { 7692 /* Highest numbered palette subleaf */ 7693 *eax = INTEL_AMX_TILE_MAX_SUBLEAF; 7694 } else if (count == 1) { 7695 *eax = INTEL_AMX_TOTAL_TILE_BYTES | 7696 (INTEL_AMX_BYTES_PER_TILE << 16); 7697 *ebx = INTEL_AMX_BYTES_PER_ROW | (INTEL_AMX_TILE_MAX_NAMES << 16); 7698 *ecx = INTEL_AMX_TILE_MAX_ROWS; 7699 } 7700 break; 7701 } 7702 case 0x1E: { 7703 /* AMX TMUL, for now hardcoded for Sapphire Rapids */ 7704 *eax = 0; 7705 *ebx = 0; 7706 *ecx = 0; 7707 *edx = 0; 7708 if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) { 7709 break; 7710 } 7711 7712 if (count == 0) { 7713 /* Highest numbered palette subleaf */ 7714 *ebx = INTEL_AMX_TMUL_MAX_K | (INTEL_AMX_TMUL_MAX_N << 8); 7715 } 7716 break; 7717 } 7718 case 0x24: { 7719 *eax = 0; 7720 *ebx = 0; 7721 *ecx = 0; 7722 *edx = 0; 7723 if ((env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) && count == 0) { 7724 *ebx = env->features[FEAT_24_0_EBX] | env->avx10_version; 7725 } 7726 break; 7727 } 7728 case 0x40000000: 7729 /* 7730 * CPUID code in kvm_arch_init_vcpu() ignores stuff 7731 * set here, but we restrict to TCG none the less. 7732 */ 7733 if (tcg_enabled() && cpu->expose_tcg) { 7734 memcpy(signature, "TCGTCGTCGTCG", 12); 7735 *eax = 0x40000001; 7736 *ebx = signature[0]; 7737 *ecx = signature[1]; 7738 *edx = signature[2]; 7739 } else { 7740 *eax = 0; 7741 *ebx = 0; 7742 *ecx = 0; 7743 *edx = 0; 7744 } 7745 break; 7746 case 0x40000001: 7747 *eax = 0; 7748 *ebx = 0; 7749 *ecx = 0; 7750 *edx = 0; 7751 break; 7752 case 0x80000000: 7753 *eax = env->cpuid_xlevel; 7754 *ebx = env->cpuid_vendor1; 7755 *edx = env->cpuid_vendor2; 7756 *ecx = env->cpuid_vendor3; 7757 break; 7758 case 0x80000001: 7759 *eax = env->cpuid_version; 7760 *ebx = 0; 7761 *ecx = env->features[FEAT_8000_0001_ECX]; 7762 *edx = env->features[FEAT_8000_0001_EDX]; 7763 7764 if (tcg_enabled() && env->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && 7765 !(env->hflags & HF_LMA_MASK)) { 7766 *edx &= ~CPUID_EXT2_SYSCALL; 7767 } 7768 break; 7769 case 0x80000002: 7770 case 0x80000003: 7771 case 0x80000004: 7772 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0]; 7773 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1]; 7774 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2]; 7775 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3]; 7776 break; 7777 case 0x80000005: 7778 /* cache info (L1 cache) */ 7779 if (cpu->cache_info_passthrough) { 7780 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 7781 break; 7782 } 7783 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | 7784 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES); 7785 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | 7786 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES); 7787 *ecx = encode_cache_cpuid80000005(env->cache_info_amd.l1d_cache); 7788 *edx = encode_cache_cpuid80000005(env->cache_info_amd.l1i_cache); 7789 break; 7790 case 0x80000006: 7791 /* cache info (L2 cache) */ 7792 if (cpu->cache_info_passthrough) { 7793 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 7794 break; 7795 } 7796 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | 7797 (L2_DTLB_2M_ENTRIES << 16) | 7798 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | 7799 (L2_ITLB_2M_ENTRIES); 7800 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | 7801 (L2_DTLB_4K_ENTRIES << 16) | 7802 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | 7803 (L2_ITLB_4K_ENTRIES); 7804 encode_cache_cpuid80000006(env->cache_info_amd.l2_cache, 7805 cpu->enable_l3_cache ? 7806 env->cache_info_amd.l3_cache : NULL, 7807 ecx, edx); 7808 break; 7809 case 0x80000007: 7810 *eax = 0; 7811 *ebx = env->features[FEAT_8000_0007_EBX]; 7812 *ecx = 0; 7813 *edx = env->features[FEAT_8000_0007_EDX]; 7814 break; 7815 case 0x80000008: 7816 /* virtual & phys address size in low 2 bytes. */ 7817 *eax = cpu->phys_bits; 7818 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 7819 /* 64 bit processor */ 7820 *eax |= (cpu_x86_virtual_addr_width(env) << 8); 7821 *eax |= (cpu->guest_phys_bits << 16); 7822 } 7823 *ebx = env->features[FEAT_8000_0008_EBX]; 7824 if (threads_per_pkg > 1) { 7825 /* 7826 * Bits 15:12 is "The number of bits in the initial 7827 * Core::X86::Apic::ApicId[ApicId] value that indicate 7828 * thread ID within a package". 7829 * Bits 7:0 is "The number of threads in the package is NC+1" 7830 */ 7831 *ecx = (apicid_pkg_offset(topo_info) << 12) | 7832 (threads_per_pkg - 1); 7833 } else { 7834 *ecx = 0; 7835 } 7836 *edx = 0; 7837 break; 7838 case 0x8000000A: 7839 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { 7840 *eax = 0x00000001; /* SVM Revision */ 7841 *ebx = 0x00000010; /* nr of ASIDs */ 7842 *ecx = 0; 7843 *edx = env->features[FEAT_SVM]; /* optional features */ 7844 } else { 7845 *eax = 0; 7846 *ebx = 0; 7847 *ecx = 0; 7848 *edx = 0; 7849 } 7850 break; 7851 case 0x8000001D: 7852 *eax = 0; 7853 if (cpu->cache_info_passthrough) { 7854 x86_cpu_get_cache_cpuid(index, count, eax, ebx, ecx, edx); 7855 break; 7856 } 7857 switch (count) { 7858 case 0: /* L1 dcache info */ 7859 encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache, 7860 topo_info, eax, ebx, ecx, edx); 7861 break; 7862 case 1: /* L1 icache info */ 7863 encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache, 7864 topo_info, eax, ebx, ecx, edx); 7865 break; 7866 case 2: /* L2 cache info */ 7867 encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache, 7868 topo_info, eax, ebx, ecx, edx); 7869 break; 7870 case 3: /* L3 cache info */ 7871 encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache, 7872 topo_info, eax, ebx, ecx, edx); 7873 break; 7874 default: /* end of info */ 7875 *eax = *ebx = *ecx = *edx = 0; 7876 break; 7877 } 7878 if (cpu->amd_topoext_features_only) { 7879 *edx &= CACHE_NO_INVD_SHARING | CACHE_INCLUSIVE; 7880 } 7881 break; 7882 case 0x8000001E: 7883 if (cpu->core_id <= 255) { 7884 encode_topo_cpuid8000001e(cpu, topo_info, eax, ebx, ecx, edx); 7885 } else { 7886 *eax = 0; 7887 *ebx = 0; 7888 *ecx = 0; 7889 *edx = 0; 7890 } 7891 break; 7892 case 0x80000022: 7893 *eax = *ebx = *ecx = *edx = 0; 7894 /* AMD Extended Performance Monitoring and Debug */ 7895 if (kvm_enabled() && cpu->enable_pmu && 7896 (env->features[FEAT_8000_0022_EAX] & CPUID_8000_0022_EAX_PERFMON_V2)) { 7897 *eax |= CPUID_8000_0022_EAX_PERFMON_V2; 7898 *ebx |= kvm_arch_get_supported_cpuid(cs->kvm_state, index, count, 7899 R_EBX) & 0xf; 7900 } 7901 break; 7902 case 0xC0000000: 7903 *eax = env->cpuid_xlevel2; 7904 *ebx = 0; 7905 *ecx = 0; 7906 *edx = 0; 7907 break; 7908 case 0xC0000001: 7909 /* Support for VIA CPU's CPUID instruction */ 7910 *eax = env->cpuid_version; 7911 *ebx = 0; 7912 *ecx = 0; 7913 *edx = env->features[FEAT_C000_0001_EDX]; 7914 break; 7915 case 0xC0000002: 7916 case 0xC0000003: 7917 case 0xC0000004: 7918 /* Reserved for the future, and now filled with zero */ 7919 *eax = 0; 7920 *ebx = 0; 7921 *ecx = 0; 7922 *edx = 0; 7923 break; 7924 case 0x8000001F: 7925 *eax = *ebx = *ecx = *edx = 0; 7926 if (sev_enabled()) { 7927 *eax = 0x2; 7928 *eax |= sev_es_enabled() ? 0x8 : 0; 7929 *eax |= sev_snp_enabled() ? 0x10 : 0; 7930 *ebx = sev_get_cbit_position() & 0x3f; /* EBX[5:0] */ 7931 *ebx |= (sev_get_reduced_phys_bits() & 0x3f) << 6; /* EBX[11:6] */ 7932 } 7933 break; 7934 case 0x80000021: 7935 *eax = *ebx = *ecx = *edx = 0; 7936 *eax = env->features[FEAT_8000_0021_EAX]; 7937 *ebx = env->features[FEAT_8000_0021_EBX]; 7938 break; 7939 default: 7940 /* reserved values: zero */ 7941 *eax = 0; 7942 *ebx = 0; 7943 *ecx = 0; 7944 *edx = 0; 7945 break; 7946 } 7947 } 7948 7949 static void x86_cpu_set_sgxlepubkeyhash(CPUX86State *env) 7950 { 7951 #ifndef CONFIG_USER_ONLY 7952 /* Those default values are defined in Skylake HW */ 7953 env->msr_ia32_sgxlepubkeyhash[0] = 0xa6053e051270b7acULL; 7954 env->msr_ia32_sgxlepubkeyhash[1] = 0x6cfbe8ba8b3b413dULL; 7955 env->msr_ia32_sgxlepubkeyhash[2] = 0xc4916d99f2b3735dULL; 7956 env->msr_ia32_sgxlepubkeyhash[3] = 0xd4f8c05909f9bb3bULL; 7957 #endif 7958 } 7959 7960 static bool cpuid_has_xsave_feature(CPUX86State *env, const ExtSaveArea *esa) 7961 { 7962 if (!esa->size) { 7963 return false; 7964 } 7965 7966 if (env->features[esa->feature] & esa->bits) { 7967 return true; 7968 } 7969 if (esa->feature == FEAT_7_0_EBX && esa->bits == CPUID_7_0_EBX_AVX512F 7970 && (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10)) { 7971 return true; 7972 } 7973 7974 return false; 7975 } 7976 7977 static void x86_cpu_reset_hold(Object *obj, ResetType type) 7978 { 7979 CPUState *cs = CPU(obj); 7980 X86CPU *cpu = X86_CPU(cs); 7981 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj); 7982 CPUX86State *env = &cpu->env; 7983 target_ulong cr4; 7984 uint64_t xcr0; 7985 int i; 7986 7987 if (xcc->parent_phases.hold) { 7988 xcc->parent_phases.hold(obj, type); 7989 } 7990 7991 memset(env, 0, offsetof(CPUX86State, end_reset_fields)); 7992 7993 if (tcg_enabled()) { 7994 cpu_init_fp_statuses(env); 7995 } 7996 7997 env->old_exception = -1; 7998 7999 /* init to reset state */ 8000 env->int_ctl = 0; 8001 env->hflags2 |= HF2_GIF_MASK; 8002 env->hflags2 |= HF2_VGIF_MASK; 8003 env->hflags &= ~HF_GUEST_MASK; 8004 8005 cpu_x86_update_cr0(env, 0x60000010); 8006 env->a20_mask = ~0x0; 8007 env->smbase = 0x30000; 8008 env->msr_smi_count = 0; 8009 8010 env->idt.limit = 0xffff; 8011 env->gdt.limit = 0xffff; 8012 env->ldt.limit = 0xffff; 8013 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT); 8014 env->tr.limit = 0xffff; 8015 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT); 8016 8017 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff, 8018 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK | 8019 DESC_R_MASK | DESC_A_MASK); 8020 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff, 8021 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 8022 DESC_A_MASK); 8023 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff, 8024 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 8025 DESC_A_MASK); 8026 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff, 8027 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 8028 DESC_A_MASK); 8029 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff, 8030 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 8031 DESC_A_MASK); 8032 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff, 8033 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 8034 DESC_A_MASK); 8035 8036 env->eip = 0xfff0; 8037 env->regs[R_EDX] = env->cpuid_version; 8038 8039 env->eflags = 0x2; 8040 8041 /* FPU init */ 8042 for (i = 0; i < 8; i++) { 8043 env->fptags[i] = 1; 8044 } 8045 cpu_set_fpuc(env, 0x37f); 8046 8047 env->mxcsr = 0x1f80; 8048 /* All units are in INIT state. */ 8049 env->xstate_bv = 0; 8050 8051 env->pat = 0x0007040600070406ULL; 8052 8053 if (kvm_enabled()) { 8054 /* 8055 * KVM handles TSC = 0 specially and thinks we are hot-plugging 8056 * a new CPU, use 1 instead to force a reset. 8057 */ 8058 if (env->tsc != 0) { 8059 env->tsc = 1; 8060 } 8061 } else { 8062 env->tsc = 0; 8063 } 8064 8065 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT; 8066 if (env->features[FEAT_1_ECX] & CPUID_EXT_MONITOR) { 8067 env->msr_ia32_misc_enable |= MSR_IA32_MISC_ENABLE_MWAIT; 8068 } 8069 8070 memset(env->dr, 0, sizeof(env->dr)); 8071 env->dr[6] = DR6_FIXED_1; 8072 env->dr[7] = DR7_FIXED_1; 8073 cpu_breakpoint_remove_all(cs, BP_CPU); 8074 cpu_watchpoint_remove_all(cs, BP_CPU); 8075 8076 cr4 = 0; 8077 xcr0 = XSTATE_FP_MASK; 8078 8079 #ifdef CONFIG_USER_ONLY 8080 /* Enable all the features for user-mode. */ 8081 if (env->features[FEAT_1_EDX] & CPUID_SSE) { 8082 xcr0 |= XSTATE_SSE_MASK; 8083 } 8084 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 8085 const ExtSaveArea *esa = &x86_ext_save_areas[i]; 8086 if (!((1 << i) & CPUID_XSTATE_XCR0_MASK)) { 8087 continue; 8088 } 8089 if (cpuid_has_xsave_feature(env, esa)) { 8090 xcr0 |= 1ull << i; 8091 } 8092 } 8093 8094 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) { 8095 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK; 8096 } 8097 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) { 8098 cr4 |= CR4_FSGSBASE_MASK; 8099 } 8100 #endif 8101 8102 env->xcr0 = xcr0; 8103 cpu_x86_update_cr4(env, cr4); 8104 8105 /* 8106 * SDM 11.11.5 requires: 8107 * - IA32_MTRR_DEF_TYPE MSR.E = 0 8108 * - IA32_MTRR_PHYSMASKn.V = 0 8109 * All other bits are undefined. For simplification, zero it all. 8110 */ 8111 env->mtrr_deftype = 0; 8112 memset(env->mtrr_var, 0, sizeof(env->mtrr_var)); 8113 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed)); 8114 8115 env->interrupt_injected = -1; 8116 env->exception_nr = -1; 8117 env->exception_pending = 0; 8118 env->exception_injected = 0; 8119 env->exception_has_payload = false; 8120 env->exception_payload = 0; 8121 env->nmi_injected = false; 8122 env->triple_fault_pending = false; 8123 #if !defined(CONFIG_USER_ONLY) 8124 /* We hard-wire the BSP to the first CPU. */ 8125 apic_designate_bsp(cpu->apic_state, cs->cpu_index == 0); 8126 8127 cs->halted = !cpu_is_bsp(cpu); 8128 8129 if (kvm_enabled()) { 8130 kvm_arch_reset_vcpu(cpu); 8131 } 8132 8133 x86_cpu_set_sgxlepubkeyhash(env); 8134 8135 env->amd_tsc_scale_msr = MSR_AMD64_TSC_RATIO_DEFAULT; 8136 8137 #endif 8138 } 8139 8140 void x86_cpu_after_reset(X86CPU *cpu) 8141 { 8142 #ifndef CONFIG_USER_ONLY 8143 if (kvm_enabled()) { 8144 kvm_arch_after_reset_vcpu(cpu); 8145 } 8146 8147 if (cpu->apic_state) { 8148 device_cold_reset(cpu->apic_state); 8149 } 8150 #endif 8151 } 8152 8153 static void mce_init(X86CPU *cpu) 8154 { 8155 CPUX86State *cenv = &cpu->env; 8156 unsigned int bank; 8157 8158 if (((cenv->cpuid_version >> 8) & 0xf) >= 6 8159 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) == 8160 (CPUID_MCE | CPUID_MCA)) { 8161 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF | 8162 (cpu->enable_lmce ? MCG_LMCE_P : 0); 8163 cenv->mcg_ctl = ~(uint64_t)0; 8164 for (bank = 0; bank < MCE_BANKS_DEF; bank++) { 8165 cenv->mce_banks[bank * 4] = ~(uint64_t)0; 8166 } 8167 } 8168 } 8169 8170 static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value) 8171 { 8172 if (*min < value) { 8173 *min = value; 8174 } 8175 } 8176 8177 /* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */ 8178 static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w) 8179 { 8180 CPUX86State *env = &cpu->env; 8181 FeatureWordInfo *fi = &feature_word_info[w]; 8182 uint32_t eax = fi->cpuid.eax; 8183 uint32_t region = eax & 0xF0000000; 8184 8185 assert(feature_word_info[w].type == CPUID_FEATURE_WORD); 8186 if (!env->features[w]) { 8187 return; 8188 } 8189 8190 switch (region) { 8191 case 0x00000000: 8192 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax); 8193 break; 8194 case 0x80000000: 8195 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax); 8196 break; 8197 case 0xC0000000: 8198 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax); 8199 break; 8200 } 8201 8202 if (eax == 7) { 8203 x86_cpu_adjust_level(cpu, &env->cpuid_min_level_func7, 8204 fi->cpuid.ecx); 8205 } 8206 } 8207 8208 /* Calculate XSAVE components based on the configured CPU feature flags */ 8209 static void x86_cpu_enable_xsave_components(X86CPU *cpu) 8210 { 8211 CPUX86State *env = &cpu->env; 8212 int i; 8213 uint64_t mask; 8214 static bool request_perm; 8215 8216 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { 8217 env->features[FEAT_XSAVE_XCR0_LO] = 0; 8218 env->features[FEAT_XSAVE_XCR0_HI] = 0; 8219 env->features[FEAT_XSAVE_XSS_LO] = 0; 8220 env->features[FEAT_XSAVE_XSS_HI] = 0; 8221 return; 8222 } 8223 8224 mask = 0; 8225 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 8226 const ExtSaveArea *esa = &x86_ext_save_areas[i]; 8227 if (cpuid_has_xsave_feature(env, esa)) { 8228 mask |= (1ULL << i); 8229 } 8230 } 8231 8232 /* Only request permission for first vcpu */ 8233 if (kvm_enabled() && !request_perm) { 8234 kvm_request_xsave_components(cpu, mask); 8235 request_perm = true; 8236 } 8237 8238 env->features[FEAT_XSAVE_XCR0_LO] = mask & CPUID_XSTATE_XCR0_MASK; 8239 env->features[FEAT_XSAVE_XCR0_HI] = (mask & CPUID_XSTATE_XCR0_MASK) >> 32; 8240 env->features[FEAT_XSAVE_XSS_LO] = mask & CPUID_XSTATE_XSS_MASK; 8241 env->features[FEAT_XSAVE_XSS_HI] = (mask & CPUID_XSTATE_XSS_MASK) >> 32; 8242 } 8243 8244 /***** Steps involved on loading and filtering CPUID data 8245 * 8246 * When initializing and realizing a CPU object, the steps 8247 * involved in setting up CPUID data are: 8248 * 8249 * 1) Loading CPU model definition (X86CPUDefinition). This is 8250 * implemented by x86_cpu_load_model() and should be completely 8251 * transparent, as it is done automatically by instance_init. 8252 * No code should need to look at X86CPUDefinition structs 8253 * outside instance_init. 8254 * 8255 * 2) CPU expansion. This is done by realize before CPUID 8256 * filtering, and will make sure host/accelerator data is 8257 * loaded for CPU models that depend on host capabilities 8258 * (e.g. "host"). Done by x86_cpu_expand_features(). 8259 * 8260 * 3) CPUID filtering. This initializes extra data related to 8261 * CPUID, and checks if the host supports all capabilities 8262 * required by the CPU. Runnability of a CPU model is 8263 * determined at this step. Done by x86_cpu_filter_features(). 8264 * 8265 * Some operations don't require all steps to be performed. 8266 * More precisely: 8267 * 8268 * - CPU instance creation (instance_init) will run only CPU 8269 * model loading. CPU expansion can't run at instance_init-time 8270 * because host/accelerator data may be not available yet. 8271 * - CPU realization will perform both CPU model expansion and CPUID 8272 * filtering, and return an error in case one of them fails. 8273 * - query-cpu-definitions needs to run all 3 steps. It needs 8274 * to run CPUID filtering, as the 'unavailable-features' 8275 * field is set based on the filtering results. 8276 * - The query-cpu-model-expansion QMP command only needs to run 8277 * CPU model loading and CPU expansion. It should not filter 8278 * any CPUID data based on host capabilities. 8279 */ 8280 8281 /* Expand CPU configuration data, based on configured features 8282 * and host/accelerator capabilities when appropriate. 8283 */ 8284 void x86_cpu_expand_features(X86CPU *cpu, Error **errp) 8285 { 8286 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu); 8287 CPUX86State *env = &cpu->env; 8288 FeatureWord w; 8289 int i; 8290 GList *l; 8291 8292 for (l = plus_features; l; l = l->next) { 8293 const char *prop = l->data; 8294 if (!object_property_set_bool(OBJECT(cpu), prop, true, errp)) { 8295 return; 8296 } 8297 } 8298 8299 for (l = minus_features; l; l = l->next) { 8300 const char *prop = l->data; 8301 if (!object_property_set_bool(OBJECT(cpu), prop, false, errp)) { 8302 return; 8303 } 8304 } 8305 8306 /* TODO: Now xcc->max_features doesn't overwrite features 8307 * set using QOM properties, and we can convert 8308 * plus_features & minus_features to global properties 8309 * inside x86_cpu_parse_featurestr() too. 8310 */ 8311 if (xcc->max_features) { 8312 for (w = 0; w < FEATURE_WORDS; w++) { 8313 /* Override only features that weren't set explicitly 8314 * by the user. 8315 */ 8316 env->features[w] |= 8317 x86_cpu_get_supported_feature_word(cpu, w) & 8318 ~env->user_features[w] & 8319 ~feature_word_info[w].no_autoenable_flags; 8320 } 8321 8322 if ((env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) && !env->avx10_version) { 8323 uint32_t eax, ebx, ecx, edx; 8324 x86_cpu_get_supported_cpuid(0x24, 0, &eax, &ebx, &ecx, &edx); 8325 env->avx10_version = ebx & 0xff; 8326 } 8327 } 8328 8329 if (x86_threads_per_pkg(&env->topo_info) > 1) { 8330 env->features[FEAT_1_EDX] |= CPUID_HT; 8331 8332 /* 8333 * The Linux kernel checks for the CMPLegacy bit and 8334 * discards multiple thread information if it is set. 8335 * So don't set it here for Intel (and other processors 8336 * following Intel's behavior) to make Linux guests happy. 8337 */ 8338 if (!IS_INTEL_CPU(env) && !IS_ZHAOXIN_CPU(env)) { 8339 env->features[FEAT_8000_0001_ECX] |= CPUID_EXT3_CMP_LEG; 8340 } 8341 } 8342 8343 if (!cpu->enable_pmu) { 8344 mark_unavailable_features(cpu, FEAT_1_ECX, 8345 env->user_features[FEAT_1_ECX] & CPUID_EXT_PDCM, 8346 "This feature is not available due to PMU being disabled"); 8347 env->features[FEAT_1_ECX] &= ~CPUID_EXT_PDCM; 8348 } 8349 8350 for (i = 0; i < ARRAY_SIZE(feature_dependencies); i++) { 8351 FeatureDep *d = &feature_dependencies[i]; 8352 if (!(env->features[d->from.index] & d->from.mask)) { 8353 uint64_t unavailable_features = env->features[d->to.index] & d->to.mask; 8354 8355 /* Not an error unless the dependent feature was added explicitly. */ 8356 mark_unavailable_features(cpu, d->to.index, 8357 unavailable_features & env->user_features[d->to.index], 8358 "This feature depends on other features that were not requested"); 8359 8360 env->features[d->to.index] &= ~unavailable_features; 8361 } 8362 } 8363 8364 if (!kvm_enabled() || !cpu->expose_kvm) { 8365 env->features[FEAT_KVM] = 0; 8366 } 8367 8368 x86_cpu_enable_xsave_components(cpu); 8369 8370 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */ 8371 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX); 8372 if (cpu->full_cpuid_auto_level) { 8373 x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX); 8374 x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX); 8375 x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX); 8376 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX); 8377 x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EAX); 8378 x86_cpu_adjust_feat_level(cpu, FEAT_7_1_ECX); 8379 x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EDX); 8380 x86_cpu_adjust_feat_level(cpu, FEAT_7_2_EDX); 8381 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX); 8382 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX); 8383 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX); 8384 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0008_EBX); 8385 x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX); 8386 x86_cpu_adjust_feat_level(cpu, FEAT_SVM); 8387 x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE); 8388 8389 /* Intel Processor Trace requires CPUID[0x14] */ 8390 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT)) { 8391 if (cpu->intel_pt_auto_level) { 8392 x86_cpu_adjust_level(cpu, &cpu->env.cpuid_min_level, 0x14); 8393 } else if (cpu->env.cpuid_min_level < 0x14) { 8394 mark_unavailable_features(cpu, FEAT_7_0_EBX, 8395 CPUID_7_0_EBX_INTEL_PT, 8396 "Intel PT need CPUID leaf 0x14, please set by \"-cpu ...,intel-pt=on,min-level=0x14\""); 8397 } 8398 } 8399 8400 /* 8401 * Intel CPU topology with multi-dies support requires CPUID[0x1F]. 8402 * For AMD Rome/Milan, cpuid level is 0x10, and guest OS should detect 8403 * extended toplogy by leaf 0xB. Only adjust it for Intel CPU, unless 8404 * cpu->vendor_cpuid_only has been unset for compatibility with older 8405 * machine types. 8406 */ 8407 if (x86_has_cpuid_0x1f(cpu) && 8408 (IS_INTEL_CPU(env) || !cpu->vendor_cpuid_only)) { 8409 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x1F); 8410 } 8411 8412 /* Advanced Vector Extensions 10 (AVX10) requires CPUID[0x24] */ 8413 if (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) { 8414 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x24); 8415 } 8416 8417 /* SVM requires CPUID[0x8000000A] */ 8418 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { 8419 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A); 8420 } 8421 8422 /* SEV requires CPUID[0x8000001F] */ 8423 if (sev_enabled()) { 8424 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F); 8425 } 8426 8427 if (env->features[FEAT_8000_0021_EAX]) { 8428 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x80000021); 8429 } 8430 8431 /* SGX requires CPUID[0x12] for EPC enumeration */ 8432 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX) { 8433 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x12); 8434 } 8435 } 8436 8437 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */ 8438 if (env->cpuid_level_func7 == UINT32_MAX) { 8439 env->cpuid_level_func7 = env->cpuid_min_level_func7; 8440 } 8441 if (env->cpuid_level == UINT32_MAX) { 8442 env->cpuid_level = env->cpuid_min_level; 8443 } 8444 if (env->cpuid_xlevel == UINT32_MAX) { 8445 env->cpuid_xlevel = env->cpuid_min_xlevel; 8446 } 8447 if (env->cpuid_xlevel2 == UINT32_MAX) { 8448 env->cpuid_xlevel2 = env->cpuid_min_xlevel2; 8449 } 8450 8451 if (kvm_enabled() && !kvm_hyperv_expand_features(cpu, errp)) { 8452 return; 8453 } 8454 } 8455 8456 /* 8457 * Finishes initialization of CPUID data, filters CPU feature 8458 * words based on host availability of each feature. 8459 * 8460 * Returns: true if any flag is not supported by the host, false otherwise. 8461 */ 8462 static bool x86_cpu_filter_features(X86CPU *cpu, bool verbose) 8463 { 8464 CPUX86State *env = &cpu->env; 8465 FeatureWord w; 8466 const char *prefix = NULL; 8467 bool have_filtered_features; 8468 8469 uint32_t eax_0, ebx_0, ecx_0, edx_0; 8470 uint32_t eax_1, ebx_1, ecx_1, edx_1; 8471 8472 if (verbose) { 8473 prefix = accel_uses_host_cpuid() 8474 ? "host doesn't support requested feature" 8475 : "TCG doesn't support requested feature"; 8476 } 8477 8478 for (w = 0; w < FEATURE_WORDS; w++) { 8479 uint64_t host_feat = 8480 x86_cpu_get_supported_feature_word(NULL, w); 8481 uint64_t requested_features = env->features[w]; 8482 uint64_t unavailable_features = requested_features & ~host_feat; 8483 mark_unavailable_features(cpu, w, unavailable_features, prefix); 8484 } 8485 8486 /* 8487 * Check that KVM actually allows the processor tracing features that 8488 * are advertised by cpu_x86_cpuid(). Keep these two in sync. 8489 */ 8490 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) && 8491 kvm_enabled()) { 8492 x86_cpu_get_supported_cpuid(0x14, 0, 8493 &eax_0, &ebx_0, &ecx_0, &edx_0); 8494 x86_cpu_get_supported_cpuid(0x14, 1, 8495 &eax_1, &ebx_1, &ecx_1, &edx_1); 8496 8497 if (!eax_0 || 8498 ((ebx_0 & INTEL_PT_MINIMAL_EBX) != INTEL_PT_MINIMAL_EBX) || 8499 ((ecx_0 & INTEL_PT_MINIMAL_ECX) != INTEL_PT_MINIMAL_ECX) || 8500 ((eax_1 & INTEL_PT_MTC_BITMAP) != INTEL_PT_MTC_BITMAP) || 8501 ((eax_1 & INTEL_PT_ADDR_RANGES_NUM_MASK) < 8502 INTEL_PT_ADDR_RANGES_NUM) || 8503 ((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) != 8504 (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) || 8505 ((ecx_0 & CPUID_14_0_ECX_LIP) != 8506 (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP))) { 8507 /* 8508 * Processor Trace capabilities aren't configurable, so if the 8509 * host can't emulate the capabilities we report on 8510 * cpu_x86_cpuid(), intel-pt can't be enabled on the current host. 8511 */ 8512 mark_unavailable_features(cpu, FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT, prefix); 8513 } 8514 } 8515 8516 have_filtered_features = x86_cpu_have_filtered_features(cpu); 8517 8518 if (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) { 8519 x86_cpu_get_supported_cpuid(0x24, 0, 8520 &eax_0, &ebx_0, &ecx_0, &edx_0); 8521 uint8_t version = ebx_0 & 0xff; 8522 8523 if (version < env->avx10_version) { 8524 if (prefix) { 8525 warn_report("%s: avx10.%d. Adjust to avx10.%d", 8526 prefix, env->avx10_version, version); 8527 } 8528 env->avx10_version = version; 8529 have_filtered_features = true; 8530 } 8531 } else if (env->avx10_version) { 8532 if (prefix) { 8533 warn_report("%s: avx10.%d.", prefix, env->avx10_version); 8534 } 8535 have_filtered_features = true; 8536 } 8537 8538 return have_filtered_features; 8539 } 8540 8541 static void x86_cpu_hyperv_realize(X86CPU *cpu) 8542 { 8543 size_t len; 8544 8545 /* Hyper-V vendor id */ 8546 if (!cpu->hyperv_vendor) { 8547 object_property_set_str(OBJECT(cpu), "hv-vendor-id", "Microsoft Hv", 8548 &error_abort); 8549 } 8550 len = strlen(cpu->hyperv_vendor); 8551 if (len > 12) { 8552 warn_report("hv-vendor-id truncated to 12 characters"); 8553 len = 12; 8554 } 8555 memset(cpu->hyperv_vendor_id, 0, 12); 8556 memcpy(cpu->hyperv_vendor_id, cpu->hyperv_vendor, len); 8557 8558 /* 'Hv#1' interface identification*/ 8559 cpu->hyperv_interface_id[0] = 0x31237648; 8560 cpu->hyperv_interface_id[1] = 0; 8561 cpu->hyperv_interface_id[2] = 0; 8562 cpu->hyperv_interface_id[3] = 0; 8563 8564 /* Hypervisor implementation limits */ 8565 cpu->hyperv_limits[0] = 64; 8566 cpu->hyperv_limits[1] = 0; 8567 cpu->hyperv_limits[2] = 0; 8568 } 8569 8570 #ifndef CONFIG_USER_ONLY 8571 static bool x86_cpu_update_smp_cache_topo(MachineState *ms, X86CPU *cpu, 8572 Error **errp) 8573 { 8574 CPUX86State *env = &cpu->env; 8575 CpuTopologyLevel level; 8576 8577 level = machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1D); 8578 if (level != CPU_TOPOLOGY_LEVEL_DEFAULT) { 8579 env->cache_info_cpuid4.l1d_cache->share_level = level; 8580 env->cache_info_amd.l1d_cache->share_level = level; 8581 } else { 8582 machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1D, 8583 env->cache_info_cpuid4.l1d_cache->share_level); 8584 machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1D, 8585 env->cache_info_amd.l1d_cache->share_level); 8586 } 8587 8588 level = machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1I); 8589 if (level != CPU_TOPOLOGY_LEVEL_DEFAULT) { 8590 env->cache_info_cpuid4.l1i_cache->share_level = level; 8591 env->cache_info_amd.l1i_cache->share_level = level; 8592 } else { 8593 machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1I, 8594 env->cache_info_cpuid4.l1i_cache->share_level); 8595 machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1I, 8596 env->cache_info_amd.l1i_cache->share_level); 8597 } 8598 8599 level = machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L2); 8600 if (level != CPU_TOPOLOGY_LEVEL_DEFAULT) { 8601 env->cache_info_cpuid4.l2_cache->share_level = level; 8602 env->cache_info_amd.l2_cache->share_level = level; 8603 } else { 8604 machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L2, 8605 env->cache_info_cpuid4.l2_cache->share_level); 8606 machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L2, 8607 env->cache_info_amd.l2_cache->share_level); 8608 } 8609 8610 level = machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L3); 8611 if (level != CPU_TOPOLOGY_LEVEL_DEFAULT) { 8612 env->cache_info_cpuid4.l3_cache->share_level = level; 8613 env->cache_info_amd.l3_cache->share_level = level; 8614 } else { 8615 machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L3, 8616 env->cache_info_cpuid4.l3_cache->share_level); 8617 machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L3, 8618 env->cache_info_amd.l3_cache->share_level); 8619 } 8620 8621 if (!machine_check_smp_cache(ms, errp)) { 8622 return false; 8623 } 8624 return true; 8625 } 8626 #endif 8627 8628 static void x86_cpu_realizefn(DeviceState *dev, Error **errp) 8629 { 8630 CPUState *cs = CPU(dev); 8631 X86CPU *cpu = X86_CPU(dev); 8632 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev); 8633 CPUX86State *env = &cpu->env; 8634 Error *local_err = NULL; 8635 unsigned requested_lbr_fmt; 8636 8637 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) 8638 /* Use pc-relative instructions in system-mode */ 8639 tcg_cflags_set(cs, CF_PCREL); 8640 #endif 8641 8642 if (cpu->apic_id == UNASSIGNED_APIC_ID) { 8643 error_setg(errp, "apic-id property was not initialized properly"); 8644 return; 8645 } 8646 8647 /* 8648 * Process Hyper-V enlightenments. 8649 * Note: this currently has to happen before the expansion of CPU features. 8650 */ 8651 x86_cpu_hyperv_realize(cpu); 8652 8653 x86_cpu_expand_features(cpu, &local_err); 8654 if (local_err) { 8655 goto out; 8656 } 8657 8658 /* 8659 * Override env->features[FEAT_PERF_CAPABILITIES].LBR_FMT 8660 * with user-provided setting. 8661 */ 8662 if (cpu->lbr_fmt != ~PERF_CAP_LBR_FMT) { 8663 if ((cpu->lbr_fmt & PERF_CAP_LBR_FMT) != cpu->lbr_fmt) { 8664 error_setg(errp, "invalid lbr-fmt"); 8665 return; 8666 } 8667 env->features[FEAT_PERF_CAPABILITIES] &= ~PERF_CAP_LBR_FMT; 8668 env->features[FEAT_PERF_CAPABILITIES] |= cpu->lbr_fmt; 8669 } 8670 8671 /* 8672 * vPMU LBR is supported when 1) KVM is enabled 2) Option pmu=on and 8673 * 3)vPMU LBR format matches that of host setting. 8674 */ 8675 requested_lbr_fmt = 8676 env->features[FEAT_PERF_CAPABILITIES] & PERF_CAP_LBR_FMT; 8677 if (requested_lbr_fmt && kvm_enabled()) { 8678 uint64_t host_perf_cap = 8679 x86_cpu_get_supported_feature_word(NULL, FEAT_PERF_CAPABILITIES); 8680 unsigned host_lbr_fmt = host_perf_cap & PERF_CAP_LBR_FMT; 8681 8682 if (!cpu->enable_pmu) { 8683 error_setg(errp, "vPMU: LBR is unsupported without pmu=on"); 8684 return; 8685 } 8686 if (requested_lbr_fmt != host_lbr_fmt) { 8687 error_setg(errp, "vPMU: the lbr-fmt value (0x%x) does not match " 8688 "the host value (0x%x).", 8689 requested_lbr_fmt, host_lbr_fmt); 8690 return; 8691 } 8692 } 8693 8694 if (x86_cpu_filter_features(cpu, cpu->check_cpuid || cpu->enforce_cpuid)) { 8695 if (cpu->enforce_cpuid) { 8696 error_setg(&local_err, 8697 accel_uses_host_cpuid() ? 8698 "Host doesn't support requested features" : 8699 "TCG doesn't support requested features"); 8700 goto out; 8701 } 8702 } 8703 8704 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on 8705 * CPUID[1].EDX. 8706 */ 8707 if (IS_AMD_CPU(env)) { 8708 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES; 8709 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX] 8710 & CPUID_EXT2_AMD_ALIASES); 8711 } 8712 8713 x86_cpu_set_sgxlepubkeyhash(env); 8714 8715 /* 8716 * note: the call to the framework needs to happen after feature expansion, 8717 * but before the checks/modifications to ucode_rev, mwait, phys_bits. 8718 * These may be set by the accel-specific code, 8719 * and the results are subsequently checked / assumed in this function. 8720 */ 8721 cpu_exec_realizefn(cs, &local_err); 8722 if (local_err != NULL) { 8723 error_propagate(errp, local_err); 8724 return; 8725 } 8726 8727 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) { 8728 g_autofree char *name = x86_cpu_class_get_model_name(xcc); 8729 error_setg(&local_err, "CPU model '%s' requires KVM or HVF", name); 8730 goto out; 8731 } 8732 8733 if (cpu->guest_phys_bits == -1) { 8734 /* 8735 * If it was not set by the user, or by the accelerator via 8736 * cpu_exec_realizefn, clear. 8737 */ 8738 cpu->guest_phys_bits = 0; 8739 } 8740 8741 if (cpu->ucode_rev == 0) { 8742 /* 8743 * The default is the same as KVM's. Note that this check 8744 * needs to happen after the evenual setting of ucode_rev in 8745 * accel-specific code in cpu_exec_realizefn. 8746 */ 8747 if (IS_AMD_CPU(env)) { 8748 cpu->ucode_rev = 0x01000065; 8749 } else { 8750 cpu->ucode_rev = 0x100000000ULL; 8751 } 8752 } 8753 8754 /* 8755 * mwait extended info: needed for Core compatibility 8756 * We always wake on interrupt even if host does not have the capability. 8757 * 8758 * requires the accel-specific code in cpu_exec_realizefn to 8759 * have already acquired the CPUID data into cpu->mwait. 8760 */ 8761 cpu->mwait.ecx |= CPUID_MWAIT_EMX | CPUID_MWAIT_IBE; 8762 8763 /* 8764 * Most Intel and certain AMD CPUs support hyperthreading. Even though QEMU 8765 * fixes this issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX 8766 * based on inputs (sockets,cores,threads), it is still better to give 8767 * users a warning. 8768 */ 8769 if (IS_AMD_CPU(env) && 8770 !(env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) && 8771 env->topo_info.threads_per_core > 1) { 8772 warn_report_once("This family of AMD CPU doesn't support " 8773 "hyperthreading(%d). Please configure -smp " 8774 "options properly or try enabling topoext " 8775 "feature.", env->topo_info.threads_per_core); 8776 } 8777 8778 /* For 64bit systems think about the number of physical bits to present. 8779 * ideally this should be the same as the host; anything other than matching 8780 * the host can cause incorrect guest behaviour. 8781 * QEMU used to pick the magic value of 40 bits that corresponds to 8782 * consumer AMD devices but nothing else. 8783 * 8784 * Note that this code assumes features expansion has already been done 8785 * (as it checks for CPUID_EXT2_LM), and also assumes that potential 8786 * phys_bits adjustments to match the host have been already done in 8787 * accel-specific code in cpu_exec_realizefn. 8788 */ 8789 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 8790 if (cpu->phys_bits && 8791 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS || 8792 cpu->phys_bits < 32)) { 8793 error_setg(errp, "phys-bits should be between 32 and %u " 8794 " (but is %u)", 8795 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits); 8796 return; 8797 } 8798 /* 8799 * 0 means it was not explicitly set by the user (or by machine 8800 * compat_props or by the host code in host-cpu.c). 8801 * In this case, the default is the value used by TCG (40). 8802 */ 8803 if (cpu->phys_bits == 0) { 8804 cpu->phys_bits = TCG_PHYS_ADDR_BITS; 8805 } 8806 if (cpu->guest_phys_bits && 8807 (cpu->guest_phys_bits > cpu->phys_bits || 8808 cpu->guest_phys_bits < 32)) { 8809 error_setg(errp, "guest-phys-bits should be between 32 and %u " 8810 " (but is %u)", 8811 cpu->phys_bits, cpu->guest_phys_bits); 8812 return; 8813 } 8814 } else { 8815 /* For 32 bit systems don't use the user set value, but keep 8816 * phys_bits consistent with what we tell the guest. 8817 */ 8818 if (cpu->phys_bits != 0) { 8819 error_setg(errp, "phys-bits is not user-configurable in 32 bit"); 8820 return; 8821 } 8822 if (cpu->guest_phys_bits != 0) { 8823 error_setg(errp, "guest-phys-bits is not user-configurable in 32 bit"); 8824 return; 8825 } 8826 8827 if (env->features[FEAT_1_EDX] & (CPUID_PSE36 | CPUID_PAE)) { 8828 cpu->phys_bits = 36; 8829 } else { 8830 cpu->phys_bits = 32; 8831 } 8832 } 8833 8834 /* Cache information initialization */ 8835 if (!cpu->legacy_cache) { 8836 const CPUCaches *cache_info = 8837 x86_cpu_get_versioned_cache_info(cpu, xcc->model); 8838 8839 if (!xcc->model || !cache_info) { 8840 g_autofree char *name = x86_cpu_class_get_model_name(xcc); 8841 error_setg(errp, 8842 "CPU model '%s' doesn't support legacy-cache=off", name); 8843 return; 8844 } 8845 env->cache_info_cpuid2 = env->cache_info_cpuid4 = env->cache_info_amd = 8846 *cache_info; 8847 } else { 8848 /* Build legacy cache information */ 8849 env->cache_info_cpuid2.l1d_cache = &legacy_l1d_cache; 8850 env->cache_info_cpuid2.l1i_cache = &legacy_l1i_cache; 8851 env->cache_info_cpuid2.l2_cache = &legacy_l2_cache_cpuid2; 8852 env->cache_info_cpuid2.l3_cache = &legacy_l3_cache; 8853 8854 env->cache_info_cpuid4.l1d_cache = &legacy_l1d_cache; 8855 env->cache_info_cpuid4.l1i_cache = &legacy_l1i_cache; 8856 env->cache_info_cpuid4.l2_cache = &legacy_l2_cache; 8857 env->cache_info_cpuid4.l3_cache = &legacy_l3_cache; 8858 8859 env->cache_info_amd.l1d_cache = &legacy_l1d_cache_amd; 8860 env->cache_info_amd.l1i_cache = &legacy_l1i_cache_amd; 8861 env->cache_info_amd.l2_cache = &legacy_l2_cache_amd; 8862 env->cache_info_amd.l3_cache = &legacy_l3_cache; 8863 } 8864 8865 #ifndef CONFIG_USER_ONLY 8866 MachineState *ms = MACHINE(qdev_get_machine()); 8867 MachineClass *mc = MACHINE_GET_CLASS(ms); 8868 8869 if (mc->smp_props.has_caches) { 8870 if (!x86_cpu_update_smp_cache_topo(ms, cpu, errp)) { 8871 return; 8872 } 8873 } 8874 8875 qemu_register_reset(x86_cpu_machine_reset_cb, cpu); 8876 8877 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || ms->smp.cpus > 1) { 8878 x86_cpu_apic_create(cpu, &local_err); 8879 if (local_err != NULL) { 8880 goto out; 8881 } 8882 } 8883 #endif 8884 8885 mce_init(cpu); 8886 8887 x86_cpu_gdb_init(cs); 8888 qemu_init_vcpu(cs); 8889 8890 #ifndef CONFIG_USER_ONLY 8891 x86_cpu_apic_realize(cpu, &local_err); 8892 if (local_err != NULL) { 8893 goto out; 8894 } 8895 #endif /* !CONFIG_USER_ONLY */ 8896 cpu_reset(cs); 8897 8898 xcc->parent_realize(dev, &local_err); 8899 8900 out: 8901 if (local_err != NULL) { 8902 error_propagate(errp, local_err); 8903 return; 8904 } 8905 } 8906 8907 static void x86_cpu_unrealizefn(DeviceState *dev) 8908 { 8909 X86CPU *cpu = X86_CPU(dev); 8910 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev); 8911 8912 #ifndef CONFIG_USER_ONLY 8913 cpu_remove_sync(CPU(dev)); 8914 qemu_unregister_reset(x86_cpu_machine_reset_cb, dev); 8915 #endif 8916 8917 if (cpu->apic_state) { 8918 object_unparent(OBJECT(cpu->apic_state)); 8919 cpu->apic_state = NULL; 8920 } 8921 8922 xcc->parent_unrealize(dev); 8923 } 8924 8925 typedef struct BitProperty { 8926 FeatureWord w; 8927 uint64_t mask; 8928 } BitProperty; 8929 8930 static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name, 8931 void *opaque, Error **errp) 8932 { 8933 X86CPU *cpu = X86_CPU(obj); 8934 BitProperty *fp = opaque; 8935 uint64_t f = cpu->env.features[fp->w]; 8936 bool value = (f & fp->mask) == fp->mask; 8937 visit_type_bool(v, name, &value, errp); 8938 } 8939 8940 static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name, 8941 void *opaque, Error **errp) 8942 { 8943 DeviceState *dev = DEVICE(obj); 8944 X86CPU *cpu = X86_CPU(obj); 8945 BitProperty *fp = opaque; 8946 bool value; 8947 8948 if (dev->realized) { 8949 qdev_prop_set_after_realize(dev, name, errp); 8950 return; 8951 } 8952 8953 if (!visit_type_bool(v, name, &value, errp)) { 8954 return; 8955 } 8956 8957 if (value) { 8958 cpu->env.features[fp->w] |= fp->mask; 8959 } else { 8960 cpu->env.features[fp->w] &= ~fp->mask; 8961 } 8962 cpu->env.user_features[fp->w] |= fp->mask; 8963 } 8964 8965 /* Register a boolean property to get/set a single bit in a uint32_t field. 8966 * 8967 * The same property name can be registered multiple times to make it affect 8968 * multiple bits in the same FeatureWord. In that case, the getter will return 8969 * true only if all bits are set. 8970 */ 8971 static void x86_cpu_register_bit_prop(X86CPUClass *xcc, 8972 const char *prop_name, 8973 FeatureWord w, 8974 int bitnr) 8975 { 8976 ObjectClass *oc = OBJECT_CLASS(xcc); 8977 BitProperty *fp; 8978 ObjectProperty *op; 8979 uint64_t mask = (1ULL << bitnr); 8980 8981 op = object_class_property_find(oc, prop_name); 8982 if (op) { 8983 fp = op->opaque; 8984 assert(fp->w == w); 8985 fp->mask |= mask; 8986 } else { 8987 fp = g_new0(BitProperty, 1); 8988 fp->w = w; 8989 fp->mask = mask; 8990 object_class_property_add(oc, prop_name, "bool", 8991 x86_cpu_get_bit_prop, 8992 x86_cpu_set_bit_prop, 8993 NULL, fp); 8994 } 8995 } 8996 8997 static void x86_cpu_register_feature_bit_props(X86CPUClass *xcc, 8998 FeatureWord w, 8999 int bitnr) 9000 { 9001 FeatureWordInfo *fi = &feature_word_info[w]; 9002 const char *name = fi->feat_names[bitnr]; 9003 9004 if (!name) { 9005 return; 9006 } 9007 9008 /* Property names should use "-" instead of "_". 9009 * Old names containing underscores are registered as aliases 9010 * using object_property_add_alias() 9011 */ 9012 assert(!strchr(name, '_')); 9013 /* aliases don't use "|" delimiters anymore, they are registered 9014 * manually using object_property_add_alias() */ 9015 assert(!strchr(name, '|')); 9016 x86_cpu_register_bit_prop(xcc, name, w, bitnr); 9017 } 9018 9019 static void x86_cpu_post_initfn(Object *obj) 9020 { 9021 static bool first = true; 9022 uint64_t supported_xcr0; 9023 int i; 9024 9025 if (first) { 9026 first = false; 9027 9028 supported_xcr0 = 9029 ((uint64_t) x86_cpu_get_supported_feature_word(NULL, FEAT_XSAVE_XCR0_HI) << 32) | 9030 x86_cpu_get_supported_feature_word(NULL, FEAT_XSAVE_XCR0_LO); 9031 9032 for (i = XSTATE_SSE_BIT + 1; i < XSAVE_STATE_AREA_COUNT; i++) { 9033 ExtSaveArea *esa = &x86_ext_save_areas[i]; 9034 9035 if (!(supported_xcr0 & (1 << i))) { 9036 esa->size = 0; 9037 } 9038 } 9039 } 9040 9041 #ifndef CONFIG_USER_ONLY 9042 if (current_machine && current_machine->cgs) { 9043 x86_confidential_guest_cpu_instance_init( 9044 X86_CONFIDENTIAL_GUEST(current_machine->cgs), (CPU(obj))); 9045 } 9046 #endif 9047 } 9048 9049 static void x86_cpu_init_default_topo(X86CPU *cpu) 9050 { 9051 CPUX86State *env = &cpu->env; 9052 9053 env->topo_info = (X86CPUTopoInfo) {1, 1, 1, 1}; 9054 9055 /* thread, core and socket levels are set by default. */ 9056 set_bit(CPU_TOPOLOGY_LEVEL_THREAD, env->avail_cpu_topo); 9057 set_bit(CPU_TOPOLOGY_LEVEL_CORE, env->avail_cpu_topo); 9058 set_bit(CPU_TOPOLOGY_LEVEL_SOCKET, env->avail_cpu_topo); 9059 } 9060 9061 static void x86_cpu_initfn(Object *obj) 9062 { 9063 X86CPU *cpu = X86_CPU(obj); 9064 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj); 9065 CPUX86State *env = &cpu->env; 9066 9067 x86_cpu_init_default_topo(cpu); 9068 9069 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo", 9070 x86_cpu_get_feature_words, 9071 NULL, NULL, (void *)env->features); 9072 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo", 9073 x86_cpu_get_feature_words, 9074 NULL, NULL, (void *)cpu->filtered_features); 9075 9076 object_property_add_alias(obj, "sse3", obj, "pni"); 9077 object_property_add_alias(obj, "pclmuldq", obj, "pclmulqdq"); 9078 object_property_add_alias(obj, "sse4-1", obj, "sse4.1"); 9079 object_property_add_alias(obj, "sse4-2", obj, "sse4.2"); 9080 object_property_add_alias(obj, "xd", obj, "nx"); 9081 object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt"); 9082 object_property_add_alias(obj, "i64", obj, "lm"); 9083 9084 object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl"); 9085 object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust"); 9086 object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt"); 9087 object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm"); 9088 object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy"); 9089 object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr"); 9090 object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core"); 9091 object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb"); 9092 object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay"); 9093 object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu"); 9094 object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf"); 9095 object_property_add_alias(obj, "kvm_asyncpf_int", obj, "kvm-asyncpf-int"); 9096 object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time"); 9097 object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi"); 9098 object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt"); 9099 object_property_add_alias(obj, "kvm_poll_control", obj, "kvm-poll-control"); 9100 object_property_add_alias(obj, "svm_lock", obj, "svm-lock"); 9101 object_property_add_alias(obj, "nrip_save", obj, "nrip-save"); 9102 object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale"); 9103 object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean"); 9104 object_property_add_alias(obj, "pause_filter", obj, "pause-filter"); 9105 object_property_add_alias(obj, "sse4_1", obj, "sse4.1"); 9106 object_property_add_alias(obj, "sse4_2", obj, "sse4.2"); 9107 9108 object_property_add_alias(obj, "hv-apicv", obj, "hv-avic"); 9109 cpu->lbr_fmt = ~PERF_CAP_LBR_FMT; 9110 object_property_add_alias(obj, "lbr_fmt", obj, "lbr-fmt"); 9111 9112 if (xcc->model) { 9113 x86_cpu_load_model(cpu, xcc->model); 9114 } 9115 9116 accel_cpu_instance_init(CPU(obj)); 9117 } 9118 9119 static int64_t x86_cpu_get_arch_id(CPUState *cs) 9120 { 9121 X86CPU *cpu = X86_CPU(cs); 9122 9123 return cpu->apic_id; 9124 } 9125 9126 #if !defined(CONFIG_USER_ONLY) 9127 static bool x86_cpu_get_paging_enabled(const CPUState *cs) 9128 { 9129 X86CPU *cpu = X86_CPU(cs); 9130 9131 return cpu->env.cr[0] & CR0_PG_MASK; 9132 } 9133 #endif /* !CONFIG_USER_ONLY */ 9134 9135 static void x86_cpu_set_pc(CPUState *cs, vaddr value) 9136 { 9137 X86CPU *cpu = X86_CPU(cs); 9138 9139 cpu->env.eip = value; 9140 } 9141 9142 static vaddr x86_cpu_get_pc(CPUState *cs) 9143 { 9144 X86CPU *cpu = X86_CPU(cs); 9145 9146 /* Match cpu_get_tb_cpu_state. */ 9147 return cpu->env.eip + cpu->env.segs[R_CS].base; 9148 } 9149 9150 #if !defined(CONFIG_USER_ONLY) 9151 int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request) 9152 { 9153 X86CPU *cpu = X86_CPU(cs); 9154 CPUX86State *env = &cpu->env; 9155 9156 if (interrupt_request & CPU_INTERRUPT_POLL) { 9157 return CPU_INTERRUPT_POLL; 9158 } 9159 if (interrupt_request & CPU_INTERRUPT_SIPI) { 9160 return CPU_INTERRUPT_SIPI; 9161 } 9162 9163 if (env->hflags2 & HF2_GIF_MASK) { 9164 if ((interrupt_request & CPU_INTERRUPT_SMI) && 9165 !(env->hflags & HF_SMM_MASK)) { 9166 return CPU_INTERRUPT_SMI; 9167 } else if ((interrupt_request & CPU_INTERRUPT_NMI) && 9168 !(env->hflags2 & HF2_NMI_MASK)) { 9169 return CPU_INTERRUPT_NMI; 9170 } else if (interrupt_request & CPU_INTERRUPT_MCE) { 9171 return CPU_INTERRUPT_MCE; 9172 } else if ((interrupt_request & CPU_INTERRUPT_HARD) && 9173 (((env->hflags2 & HF2_VINTR_MASK) && 9174 (env->hflags2 & HF2_HIF_MASK)) || 9175 (!(env->hflags2 & HF2_VINTR_MASK) && 9176 (env->eflags & IF_MASK && 9177 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) { 9178 return CPU_INTERRUPT_HARD; 9179 } else if (env->hflags2 & HF2_VGIF_MASK) { 9180 if((interrupt_request & CPU_INTERRUPT_VIRQ) && 9181 (env->eflags & IF_MASK) && 9182 !(env->hflags & HF_INHIBIT_IRQ_MASK)) { 9183 return CPU_INTERRUPT_VIRQ; 9184 } 9185 } 9186 } 9187 9188 return 0; 9189 } 9190 9191 static bool x86_cpu_has_work(CPUState *cs) 9192 { 9193 return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0; 9194 } 9195 #endif /* !CONFIG_USER_ONLY */ 9196 9197 static void x86_disas_set_info(CPUState *cs, disassemble_info *info) 9198 { 9199 X86CPU *cpu = X86_CPU(cs); 9200 CPUX86State *env = &cpu->env; 9201 9202 info->endian = BFD_ENDIAN_LITTLE; 9203 info->mach = (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64 9204 : env->hflags & HF_CS32_MASK ? bfd_mach_i386_i386 9205 : bfd_mach_i386_i8086); 9206 9207 info->cap_arch = CS_ARCH_X86; 9208 info->cap_mode = (env->hflags & HF_CS64_MASK ? CS_MODE_64 9209 : env->hflags & HF_CS32_MASK ? CS_MODE_32 9210 : CS_MODE_16); 9211 info->cap_insn_unit = 1; 9212 info->cap_insn_split = 8; 9213 } 9214 9215 void x86_update_hflags(CPUX86State *env) 9216 { 9217 uint32_t hflags; 9218 #define HFLAG_COPY_MASK \ 9219 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \ 9220 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \ 9221 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \ 9222 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK) 9223 9224 hflags = env->hflags & HFLAG_COPY_MASK; 9225 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK; 9226 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT); 9227 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) & 9228 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK); 9229 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK)); 9230 9231 if (env->cr[4] & CR4_OSFXSR_MASK) { 9232 hflags |= HF_OSFXSR_MASK; 9233 } 9234 9235 if (env->efer & MSR_EFER_LMA) { 9236 hflags |= HF_LMA_MASK; 9237 } 9238 9239 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) { 9240 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; 9241 } else { 9242 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >> 9243 (DESC_B_SHIFT - HF_CS32_SHIFT); 9244 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >> 9245 (DESC_B_SHIFT - HF_SS32_SHIFT); 9246 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) || 9247 !(hflags & HF_CS32_MASK)) { 9248 hflags |= HF_ADDSEG_MASK; 9249 } else { 9250 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base | 9251 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT; 9252 } 9253 } 9254 env->hflags = hflags; 9255 } 9256 9257 static const Property x86_cpu_properties[] = { 9258 #ifdef CONFIG_USER_ONLY 9259 /* apic_id = 0 by default for *-user, see commit 9886e834 */ 9260 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0), 9261 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0), 9262 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0), 9263 DEFINE_PROP_INT32("module-id", X86CPU, module_id, 0), 9264 DEFINE_PROP_INT32("die-id", X86CPU, die_id, 0), 9265 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0), 9266 #else 9267 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID), 9268 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1), 9269 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1), 9270 DEFINE_PROP_INT32("module-id", X86CPU, module_id, -1), 9271 DEFINE_PROP_INT32("die-id", X86CPU, die_id, -1), 9272 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1), 9273 #endif 9274 DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID), 9275 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false), 9276 DEFINE_PROP_UINT64_CHECKMASK("lbr-fmt", X86CPU, lbr_fmt, PERF_CAP_LBR_FMT), 9277 9278 DEFINE_PROP_UINT32("hv-spinlocks", X86CPU, hyperv_spinlock_attempts, 9279 HYPERV_SPINLOCK_NEVER_NOTIFY), 9280 DEFINE_PROP_BIT64("hv-relaxed", X86CPU, hyperv_features, 9281 HYPERV_FEAT_RELAXED, 0), 9282 DEFINE_PROP_BIT64("hv-vapic", X86CPU, hyperv_features, 9283 HYPERV_FEAT_VAPIC, 0), 9284 DEFINE_PROP_BIT64("hv-time", X86CPU, hyperv_features, 9285 HYPERV_FEAT_TIME, 0), 9286 DEFINE_PROP_BIT64("hv-crash", X86CPU, hyperv_features, 9287 HYPERV_FEAT_CRASH, 0), 9288 DEFINE_PROP_BIT64("hv-reset", X86CPU, hyperv_features, 9289 HYPERV_FEAT_RESET, 0), 9290 DEFINE_PROP_BIT64("hv-vpindex", X86CPU, hyperv_features, 9291 HYPERV_FEAT_VPINDEX, 0), 9292 DEFINE_PROP_BIT64("hv-runtime", X86CPU, hyperv_features, 9293 HYPERV_FEAT_RUNTIME, 0), 9294 DEFINE_PROP_BIT64("hv-synic", X86CPU, hyperv_features, 9295 HYPERV_FEAT_SYNIC, 0), 9296 DEFINE_PROP_BIT64("hv-stimer", X86CPU, hyperv_features, 9297 HYPERV_FEAT_STIMER, 0), 9298 DEFINE_PROP_BIT64("hv-frequencies", X86CPU, hyperv_features, 9299 HYPERV_FEAT_FREQUENCIES, 0), 9300 DEFINE_PROP_BIT64("hv-reenlightenment", X86CPU, hyperv_features, 9301 HYPERV_FEAT_REENLIGHTENMENT, 0), 9302 DEFINE_PROP_BIT64("hv-tlbflush", X86CPU, hyperv_features, 9303 HYPERV_FEAT_TLBFLUSH, 0), 9304 DEFINE_PROP_BIT64("hv-evmcs", X86CPU, hyperv_features, 9305 HYPERV_FEAT_EVMCS, 0), 9306 DEFINE_PROP_BIT64("hv-ipi", X86CPU, hyperv_features, 9307 HYPERV_FEAT_IPI, 0), 9308 DEFINE_PROP_BIT64("hv-stimer-direct", X86CPU, hyperv_features, 9309 HYPERV_FEAT_STIMER_DIRECT, 0), 9310 DEFINE_PROP_BIT64("hv-avic", X86CPU, hyperv_features, 9311 HYPERV_FEAT_AVIC, 0), 9312 DEFINE_PROP_BIT64("hv-emsr-bitmap", X86CPU, hyperv_features, 9313 HYPERV_FEAT_MSR_BITMAP, 0), 9314 DEFINE_PROP_BIT64("hv-xmm-input", X86CPU, hyperv_features, 9315 HYPERV_FEAT_XMM_INPUT, 0), 9316 DEFINE_PROP_BIT64("hv-tlbflush-ext", X86CPU, hyperv_features, 9317 HYPERV_FEAT_TLBFLUSH_EXT, 0), 9318 DEFINE_PROP_BIT64("hv-tlbflush-direct", X86CPU, hyperv_features, 9319 HYPERV_FEAT_TLBFLUSH_DIRECT, 0), 9320 DEFINE_PROP_ON_OFF_AUTO("hv-no-nonarch-coresharing", X86CPU, 9321 hyperv_no_nonarch_cs, ON_OFF_AUTO_OFF), 9322 #ifdef CONFIG_SYNDBG 9323 DEFINE_PROP_BIT64("hv-syndbg", X86CPU, hyperv_features, 9324 HYPERV_FEAT_SYNDBG, 0), 9325 #endif 9326 DEFINE_PROP_BOOL("hv-passthrough", X86CPU, hyperv_passthrough, false), 9327 DEFINE_PROP_BOOL("hv-enforce-cpuid", X86CPU, hyperv_enforce_cpuid, false), 9328 9329 /* WS2008R2 identify by default */ 9330 DEFINE_PROP_UINT32("hv-version-id-build", X86CPU, hyperv_ver_id_build, 9331 0x3839), 9332 DEFINE_PROP_UINT16("hv-version-id-major", X86CPU, hyperv_ver_id_major, 9333 0x000A), 9334 DEFINE_PROP_UINT16("hv-version-id-minor", X86CPU, hyperv_ver_id_minor, 9335 0x0000), 9336 DEFINE_PROP_UINT32("hv-version-id-spack", X86CPU, hyperv_ver_id_sp, 0), 9337 DEFINE_PROP_UINT8("hv-version-id-sbranch", X86CPU, hyperv_ver_id_sb, 0), 9338 DEFINE_PROP_UINT32("hv-version-id-snumber", X86CPU, hyperv_ver_id_sn, 0), 9339 9340 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true), 9341 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false), 9342 DEFINE_PROP_BOOL("x-force-features", X86CPU, force_features, false), 9343 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true), 9344 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0), 9345 DEFINE_PROP_UINT32("guest-phys-bits", X86CPU, guest_phys_bits, -1), 9346 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false), 9347 DEFINE_PROP_UINT8("host-phys-bits-limit", X86CPU, host_phys_bits_limit, 0), 9348 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true), 9349 DEFINE_PROP_UINT32("level-func7", X86CPU, env.cpuid_level_func7, 9350 UINT32_MAX), 9351 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX), 9352 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX), 9353 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX), 9354 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0), 9355 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0), 9356 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0), 9357 DEFINE_PROP_UINT8("avx10-version", X86CPU, env.avx10_version, 0), 9358 DEFINE_PROP_UINT64("ucode-rev", X86CPU, ucode_rev, 0), 9359 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true), 9360 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor), 9361 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true), 9362 DEFINE_PROP_BOOL("x-vendor-cpuid-only", X86CPU, vendor_cpuid_only, true), 9363 DEFINE_PROP_BOOL("x-amd-topoext-features-only", X86CPU, amd_topoext_features_only, true), 9364 DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false), 9365 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true), 9366 DEFINE_PROP_BOOL("kvm-pv-enforce-cpuid", X86CPU, kvm_pv_enforce_cpuid, 9367 false), 9368 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true), 9369 DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true), 9370 DEFINE_PROP_BOOL("x-migrate-smi-count", X86CPU, migrate_smi_count, 9371 true), 9372 /* 9373 * lecacy_cache defaults to true unless the CPU model provides its 9374 * own cache information (see x86_cpu_load_def()). 9375 */ 9376 DEFINE_PROP_BOOL("legacy-cache", X86CPU, legacy_cache, true), 9377 DEFINE_PROP_BOOL("legacy-multi-node", X86CPU, legacy_multi_node, false), 9378 DEFINE_PROP_BOOL("xen-vapic", X86CPU, xen_vapic, false), 9379 9380 /* 9381 * From "Requirements for Implementing the Microsoft 9382 * Hypervisor Interface": 9383 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs 9384 * 9385 * "Starting with Windows Server 2012 and Windows 8, if 9386 * CPUID.40000005.EAX contains a value of -1, Windows assumes that 9387 * the hypervisor imposes no specific limit to the number of VPs. 9388 * In this case, Windows Server 2012 guest VMs may use more than 9389 * 64 VPs, up to the maximum supported number of processors applicable 9390 * to the specific Windows version being used." 9391 */ 9392 DEFINE_PROP_INT32("x-hv-max-vps", X86CPU, hv_max_vps, -1), 9393 DEFINE_PROP_BOOL("x-hv-synic-kvm-only", X86CPU, hyperv_synic_kvm_only, 9394 false), 9395 DEFINE_PROP_BOOL("x-intel-pt-auto-level", X86CPU, intel_pt_auto_level, 9396 true), 9397 DEFINE_PROP_BOOL("x-l1-cache-per-thread", X86CPU, l1_cache_per_core, true), 9398 }; 9399 9400 #ifndef CONFIG_USER_ONLY 9401 #include "hw/core/sysemu-cpu-ops.h" 9402 9403 static const struct SysemuCPUOps i386_sysemu_ops = { 9404 .has_work = x86_cpu_has_work, 9405 .get_memory_mapping = x86_cpu_get_memory_mapping, 9406 .get_paging_enabled = x86_cpu_get_paging_enabled, 9407 .get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug, 9408 .asidx_from_attrs = x86_asidx_from_attrs, 9409 .get_crash_info = x86_cpu_get_crash_info, 9410 .write_elf32_note = x86_cpu_write_elf32_note, 9411 .write_elf64_note = x86_cpu_write_elf64_note, 9412 .write_elf32_qemunote = x86_cpu_write_elf32_qemunote, 9413 .write_elf64_qemunote = x86_cpu_write_elf64_qemunote, 9414 .legacy_vmsd = &vmstate_x86_cpu, 9415 }; 9416 #endif 9417 9418 static void x86_cpu_common_class_init(ObjectClass *oc, const void *data) 9419 { 9420 X86CPUClass *xcc = X86_CPU_CLASS(oc); 9421 CPUClass *cc = CPU_CLASS(oc); 9422 DeviceClass *dc = DEVICE_CLASS(oc); 9423 ResettableClass *rc = RESETTABLE_CLASS(oc); 9424 FeatureWord w; 9425 9426 device_class_set_parent_realize(dc, x86_cpu_realizefn, 9427 &xcc->parent_realize); 9428 device_class_set_parent_unrealize(dc, x86_cpu_unrealizefn, 9429 &xcc->parent_unrealize); 9430 device_class_set_props(dc, x86_cpu_properties); 9431 9432 resettable_class_set_parent_phases(rc, NULL, x86_cpu_reset_hold, NULL, 9433 &xcc->parent_phases); 9434 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP; 9435 9436 cc->class_by_name = x86_cpu_class_by_name; 9437 cc->list_cpus = x86_cpu_list; 9438 cc->parse_features = x86_cpu_parse_featurestr; 9439 cc->dump_state = x86_cpu_dump_state; 9440 cc->set_pc = x86_cpu_set_pc; 9441 cc->get_pc = x86_cpu_get_pc; 9442 cc->gdb_read_register = x86_cpu_gdb_read_register; 9443 cc->gdb_write_register = x86_cpu_gdb_write_register; 9444 cc->get_arch_id = x86_cpu_get_arch_id; 9445 9446 #ifndef CONFIG_USER_ONLY 9447 cc->sysemu_ops = &i386_sysemu_ops; 9448 #endif /* !CONFIG_USER_ONLY */ 9449 #ifdef CONFIG_TCG 9450 cc->tcg_ops = &x86_tcg_ops; 9451 #endif /* CONFIG_TCG */ 9452 9453 cc->gdb_arch_name = x86_gdb_arch_name; 9454 #ifdef TARGET_X86_64 9455 cc->gdb_core_xml_file = "i386-64bit.xml"; 9456 #else 9457 cc->gdb_core_xml_file = "i386-32bit.xml"; 9458 #endif 9459 cc->disas_set_info = x86_disas_set_info; 9460 9461 dc->user_creatable = true; 9462 9463 object_class_property_add(oc, "family", "int", 9464 x86_cpuid_version_get_family, 9465 x86_cpuid_version_set_family, NULL, NULL); 9466 object_class_property_add(oc, "model", "int", 9467 x86_cpuid_version_get_model, 9468 x86_cpuid_version_set_model, NULL, NULL); 9469 object_class_property_add(oc, "stepping", "int", 9470 x86_cpuid_version_get_stepping, 9471 x86_cpuid_version_set_stepping, NULL, NULL); 9472 object_class_property_add_str(oc, "vendor", 9473 x86_cpuid_get_vendor, 9474 x86_cpuid_set_vendor); 9475 object_class_property_add_str(oc, "model-id", 9476 x86_cpuid_get_model_id, 9477 x86_cpuid_set_model_id); 9478 object_class_property_add(oc, "tsc-frequency", "int", 9479 x86_cpuid_get_tsc_freq, 9480 x86_cpuid_set_tsc_freq, NULL, NULL); 9481 /* 9482 * The "unavailable-features" property has the same semantics as 9483 * CpuDefinitionInfo.unavailable-features on the "query-cpu-definitions" 9484 * QMP command: they list the features that would have prevented the 9485 * CPU from running if the "enforce" flag was set. 9486 */ 9487 object_class_property_add(oc, "unavailable-features", "strList", 9488 x86_cpu_get_unavailable_features, 9489 NULL, NULL, NULL); 9490 9491 #if !defined(CONFIG_USER_ONLY) 9492 object_class_property_add(oc, "crash-information", "GuestPanicInformation", 9493 x86_cpu_get_crash_info_qom, NULL, NULL, NULL); 9494 #endif 9495 9496 for (w = 0; w < FEATURE_WORDS; w++) { 9497 int bitnr; 9498 for (bitnr = 0; bitnr < 64; bitnr++) { 9499 x86_cpu_register_feature_bit_props(xcc, w, bitnr); 9500 } 9501 } 9502 } 9503 9504 static const TypeInfo x86_cpu_type_info = { 9505 .name = TYPE_X86_CPU, 9506 .parent = TYPE_CPU, 9507 .instance_size = sizeof(X86CPU), 9508 .instance_align = __alignof(X86CPU), 9509 .instance_init = x86_cpu_initfn, 9510 .instance_post_init = x86_cpu_post_initfn, 9511 9512 .abstract = true, 9513 .class_size = sizeof(X86CPUClass), 9514 .class_init = x86_cpu_common_class_init, 9515 }; 9516 9517 /* "base" CPU model, used by query-cpu-model-expansion */ 9518 static void x86_cpu_base_class_init(ObjectClass *oc, const void *data) 9519 { 9520 X86CPUClass *xcc = X86_CPU_CLASS(oc); 9521 9522 xcc->static_model = true; 9523 xcc->migration_safe = true; 9524 xcc->model_description = "base CPU model type with no features enabled"; 9525 xcc->ordering = 8; 9526 } 9527 9528 static const TypeInfo x86_base_cpu_type_info = { 9529 .name = X86_CPU_TYPE_NAME("base"), 9530 .parent = TYPE_X86_CPU, 9531 .class_init = x86_cpu_base_class_init, 9532 }; 9533 9534 static void x86_cpu_register_types(void) 9535 { 9536 int i; 9537 9538 type_register_static(&x86_cpu_type_info); 9539 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) { 9540 x86_register_cpudef_types(&builtin_x86_defs[i]); 9541 } 9542 type_register_static(&max_x86_cpu_type_info); 9543 type_register_static(&x86_base_cpu_type_info); 9544 } 9545 9546 type_init(x86_cpu_register_types) 9547