xref: /openbmc/qemu/target/i386/cpu-qom.h (revision 9295b1aa)
1fcf5ef2aSThomas Huth /*
2fcf5ef2aSThomas Huth  * QEMU x86 CPU
3fcf5ef2aSThomas Huth  *
4fcf5ef2aSThomas Huth  * Copyright (c) 2012 SUSE LINUX Products GmbH
5fcf5ef2aSThomas Huth  *
6fcf5ef2aSThomas Huth  * This library is free software; you can redistribute it and/or
7fcf5ef2aSThomas Huth  * modify it under the terms of the GNU Lesser General Public
8fcf5ef2aSThomas Huth  * License as published by the Free Software Foundation; either
9fcf5ef2aSThomas Huth  * version 2.1 of the License, or (at your option) any later version.
10fcf5ef2aSThomas Huth  *
11fcf5ef2aSThomas Huth  * This library is distributed in the hope that it will be useful,
12fcf5ef2aSThomas Huth  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13fcf5ef2aSThomas Huth  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14fcf5ef2aSThomas Huth  * Lesser General Public License for more details.
15fcf5ef2aSThomas Huth  *
16fcf5ef2aSThomas Huth  * You should have received a copy of the GNU Lesser General Public
17fcf5ef2aSThomas Huth  * License along with this library; if not, see
18fcf5ef2aSThomas Huth  * <http://www.gnu.org/licenses/lgpl-2.1.html>
19fcf5ef2aSThomas Huth  */
20fcf5ef2aSThomas Huth #ifndef QEMU_I386_CPU_QOM_H
21fcf5ef2aSThomas Huth #define QEMU_I386_CPU_QOM_H
22fcf5ef2aSThomas Huth 
232e5b09fdSMarkus Armbruster #include "hw/core/cpu.h"
24fcf5ef2aSThomas Huth #include "qemu/notify.h"
25db1015e9SEduardo Habkost #include "qom/object.h"
26fcf5ef2aSThomas Huth 
27fcf5ef2aSThomas Huth #ifdef TARGET_X86_64
28fcf5ef2aSThomas Huth #define TYPE_X86_CPU "x86_64-cpu"
29fcf5ef2aSThomas Huth #else
30fcf5ef2aSThomas Huth #define TYPE_X86_CPU "i386-cpu"
31fcf5ef2aSThomas Huth #endif
32fcf5ef2aSThomas Huth 
33*9295b1aaSPhilippe Mathieu-Daudé OBJECT_DECLARE_CPU_TYPE(X86CPU, X86CPUClass, X86_CPU)
34fcf5ef2aSThomas Huth 
35dcafd1efSEduardo Habkost typedef struct X86CPUModel X86CPUModel;
36fcf5ef2aSThomas Huth 
37fcf5ef2aSThomas Huth /**
38fcf5ef2aSThomas Huth  * X86CPUClass:
39fcf5ef2aSThomas Huth  * @cpu_def: CPU model definition
40d6dcc558SSergio Andres Gomez Del Real  * @host_cpuid_required: Whether CPU model requires cpuid from host.
41f48c8837SEduardo Habkost  * @ordering: Ordering on the "-cpu help" CPU model list.
42bd72159dSEduardo Habkost  * @migration_safe: See CpuDefinitionInfo::migration_safe
435adbed30SEduardo Habkost  * @static_model: See CpuDefinitionInfo::static
44fcf5ef2aSThomas Huth  * @parent_realize: The parent class' realize handler.
45fcf5ef2aSThomas Huth  * @parent_reset: The parent class' reset handler.
46fcf5ef2aSThomas Huth  *
47fcf5ef2aSThomas Huth  * An x86 CPU model or family.
48fcf5ef2aSThomas Huth  */
49db1015e9SEduardo Habkost struct X86CPUClass {
50fcf5ef2aSThomas Huth     /*< private >*/
51fcf5ef2aSThomas Huth     CPUClass parent_class;
52fcf5ef2aSThomas Huth     /*< public >*/
53fcf5ef2aSThomas Huth 
540bacd8b3SEduardo Habkost     /* CPU definition, automatically loaded by instance_init if not NULL.
550bacd8b3SEduardo Habkost      * Should be eventually replaced by subclass-specific property defaults.
560bacd8b3SEduardo Habkost      */
57dcafd1efSEduardo Habkost     X86CPUModel *model;
58fcf5ef2aSThomas Huth 
59d6dcc558SSergio Andres Gomez Del Real     bool host_cpuid_required;
60f48c8837SEduardo Habkost     int ordering;
61bd72159dSEduardo Habkost     bool migration_safe;
625adbed30SEduardo Habkost     bool static_model;
63fcf5ef2aSThomas Huth 
64fcf5ef2aSThomas Huth     /* Optional description of CPU model.
65fcf5ef2aSThomas Huth      * If unavailable, cpu_def->model_id is used */
66fcf5ef2aSThomas Huth     const char *model_description;
67fcf5ef2aSThomas Huth 
68fcf5ef2aSThomas Huth     DeviceRealize parent_realize;
69fcf5ef2aSThomas Huth     DeviceUnrealize parent_unrealize;
70781c67caSPeter Maydell     DeviceReset parent_reset;
71db1015e9SEduardo Habkost };
72fcf5ef2aSThomas Huth 
73fcf5ef2aSThomas Huth 
74fcf5ef2aSThomas Huth #endif
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