1# 2# HPPA instruction decode definitions. 3# 4# Copyright (c) 2018 Richard Henderson <rth@twiddle.net> 5# 6# This library is free software; you can redistribute it and/or 7# modify it under the terms of the GNU Lesser General Public 8# License as published by the Free Software Foundation; either 9# version 2.1 of the License, or (at your option) any later version. 10# 11# This library is distributed in the hope that it will be useful, 12# but WITHOUT ANY WARRANTY; without even the implied warranty of 13# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14# Lesser General Public License for more details. 15# 16# You should have received a copy of the GNU Lesser General Public 17# License along with this library; if not, see <http://www.gnu.org/licenses/>. 18# 19 20#### 21# Field definitions 22#### 23 24%assemble_sr3 13:1 14:2 25%assemble_sr3x 13:1 14:2 !function=expand_sr3x 26 27%assemble_11a 0:s1 4:10 !function=expand_shl3 28%assemble_12 0:s1 2:1 3:10 !function=expand_shl2 29%assemble_12a 0:s1 3:11 !function=expand_shl2 30%assemble_17 0:s1 16:5 2:1 3:10 !function=expand_shl2 31%assemble_22 0:s1 16:10 2:1 3:10 !function=expand_shl2 32 33%assemble_21 0:s1 1:11 14:2 16:5 12:2 !function=expand_shl11 34 35%lowsign_11 0:s1 1:10 36%lowsign_14 0:s1 1:13 37 38%sm_imm 16:10 !function=expand_sm_imm 39 40%rm64 1:1 16:5 41%rt64 6:1 0:5 42%ra64 7:1 21:5 43%rb64 12:1 16:5 44%rc64 8:1 13:3 9:2 45%rc32 13:3 9:2 46 47%im5_0 0:s1 1:4 48%im5_16 16:s1 17:4 49%len5 0:5 !function=assemble_6 50%len6_8 8:1 0:5 !function=assemble_6 51%len6_12 12:1 0:5 !function=assemble_6 52%cpos6_11 11:1 5:5 53%ma_to_m 5:1 13:1 !function=ma_to_m 54%ma2_to_m 2:2 !function=ma_to_m 55%pos_to_m 0:1 !function=pos_to_m 56%neg_to_m 0:1 !function=neg_to_m 57%a_to_m 2:1 !function=neg_to_m 58%cmpbid_c 13:2 !function=cmpbid_c 59 60#### 61# Argument set definitions 62#### 63 64# All insns that need to form a virtual address should use this set. 65&ldst t b x disp sp m scale size 66 67&rr_cf_d t r cf d 68&rrr t r1 r2 69&rrr_cf t r1 r2 cf 70&rrr_cf_d t r1 r2 cf d 71&rrr_sh t r1 r2 sh 72&rrr_cf_d_sh t r1 r2 cf d sh 73&rri t r i 74&rri_cf t r i cf 75&rri_cf_d t r i cf d 76 77&rrb_c_f disp n c f r1 r2 78&rrb_c_d_f disp n c d f r1 r2 79&rib_c_f disp n c f r i 80&rib_c_d_f disp n c d f r i 81 82#### 83# Format definitions 84#### 85 86@rr_cf_d ...... r:5 ..... cf:4 ...... d:1 t:5 &rr_cf_d 87@rrr ...... r2:5 r1:5 .... ....... t:5 &rrr 88@rrr_cf ...... r2:5 r1:5 cf:4 ....... t:5 &rrr_cf 89@rrr_cf_d ...... r2:5 r1:5 cf:4 ...... d:1 t:5 &rrr_cf_d 90@rrr_sh ...... r2:5 r1:5 ........ sh:2 . t:5 &rrr_sh 91@rrr_cf_d_sh ...... r2:5 r1:5 cf:4 .... sh:2 d:1 t:5 &rrr_cf_d_sh 92@rrr_cf_d_sh0 ...... r2:5 r1:5 cf:4 ...... d:1 t:5 &rrr_cf_d_sh sh=0 93@rri_cf ...... r:5 t:5 cf:4 . ........... &rri_cf i=%lowsign_11 94@rri_cf_d ...... r:5 t:5 cf:4 d:1 ........... &rri_cf_d i=%lowsign_11 95 96@rrb_cf ...... r2:5 r1:5 c:3 ........... n:1 . \ 97 &rrb_c_f disp=%assemble_12 98@rrb_cdf ...... r2:5 r1:5 c:3 ........... n:1 . \ 99 &rrb_c_d_f disp=%assemble_12 100@rib_cf ...... r:5 ..... c:3 ........... n:1 . \ 101 &rib_c_f disp=%assemble_12 i=%im5_16 102@rib_cdf ...... r:5 ..... c:3 ........... n:1 . \ 103 &rib_c_d_f disp=%assemble_12 i=%im5_16 104 105#### 106# System 107#### 108 109break 000000 ----- ----- --- 00000000 ----- 110 111mtsp 000000 ----- r:5 ... 11000001 00000 sp=%assemble_sr3 112mtctl 000000 t:5 r:5 --- 11000010 00000 113mtsarcm 000000 01011 r:5 --- 11000110 00000 114mtsm 000000 00000 r:5 000 11000011 00000 115 116mfia 000000 ----- 00000 --- 10100101 t:5 117mfsp 000000 ----- 00000 ... 00100101 t:5 sp=%assemble_sr3 118mfctl 000000 r:5 00000- e:1 -01000101 t:5 119 120sync 000000 ----- ----- 000 00100000 00000 # sync, syncdma 121 122ldsid 000000 b:5 ----- sp:2 0 10000101 t:5 123 124rsm 000000 .......... 000 01110011 t:5 i=%sm_imm 125ssm 000000 .......... 000 01101011 t:5 i=%sm_imm 126 127rfi 000000 ----- ----- --- 01100000 00000 128rfi_r 000000 ----- ----- --- 01100101 00000 129 130# These are artificial instructions used by QEMU firmware. 131# They are allocated from the unassigned instruction space. 132halt 1111 1111 1111 1101 1110 1010 1101 0000 133reset 1111 1111 1111 1101 1110 1010 1101 0001 134getshadowregs 1111 1111 1111 1101 1110 1010 1101 0010 135 136#### 137# Memory Management 138#### 139 140@addrx ...... b:5 x:5 .. ........ m:1 ..... \ 141 &ldst disp=0 scale=0 t=0 sp=0 size=0 142 143nop 000001 ----- ----- -- 11001010 0 ----- # fdc, disp 144nop_addrx 000001 ..... ..... -- 01001010 . ----- @addrx # fdc, index 145nop_addrx 000001 ..... ..... -- 01001011 . ----- @addrx # fdce 146nop_addrx 000001 ..... ..... --- 0001010 . ----- @addrx # fic 0x0a 147nop_addrx 000001 ..... ..... -- 01001111 . 00000 @addrx # fic 0x4f 148nop_addrx 000001 ..... ..... --- 0001011 . ----- @addrx # fice 149nop_addrx 000001 ..... ..... -- 01001110 . 00000 @addrx # pdc 150 151probe 000001 b:5 ri:5 sp:2 imm:1 100011 write:1 0 t:5 152 153# pa1.x tlb insert instructions 154ixtlbx 000001 b:5 r:5 sp:2 0100000 addr:1 0 00000 data=1 155ixtlbx 000001 b:5 r:5 ... 000000 addr:1 0 00000 \ 156 sp=%assemble_sr3x data=0 157 158# pcxl and pcxl2 Fast TLB Insert instructions 159ixtlbxf 000001 00000 r:5 00 0 data:1 01000 addr:1 0 00000 160 161# pa2.0 tlb insert idtlbt and iitlbt instructions 162ixtlbt 000001 r2:5 r1:5 000 data:1 100000 0 00000 # idtlbt 163 164# pdtlb, pitlb 165pxtlb 000001 b:5 x:5 sp:2 01001000 m:1 ----- \ 166 &ldst disp=0 scale=0 size=0 t=0 167pxtlb 000001 b:5 x:5 ... 0001000 m:1 ----- \ 168 &ldst disp=0 scale=0 size=0 t=0 sp=%assemble_sr3x 169 170# ... pa20 local 171pxtlb_l 000001 b:5 x:5 sp:2 01011000 m:1 ----- \ 172 &ldst disp=0 scale=0 size=0 t=0 173pxtlb_l 000001 b:5 x:5 ... 0011000 m:1 ----- \ 174 &ldst disp=0 scale=0 size=0 t=0 sp=%assemble_sr3x 175 176# pdtlbe, pitlbe 177pxtlbe 000001 b:5 x:5 sp:2 01001001 m:1 ----- \ 178 &ldst disp=0 scale=0 size=0 t=0 179pxtlbe 000001 b:5 x:5 ... 0001001 m:1 ----- \ 180 &ldst disp=0 scale=0 size=0 t=0 sp=%assemble_sr3x 181 182lpa 000001 b:5 x:5 sp:2 01001101 m:1 t:5 \ 183 &ldst disp=0 scale=0 size=0 184 185lci 000001 ----- ----- -- 01001100 0 t:5 186 187#### 188# Arith/Log 189#### 190 191andcm 000010 ..... ..... .... 000000 . ..... @rrr_cf_d 192and 000010 ..... ..... .... 001000 . ..... @rrr_cf_d 193or 000010 ..... ..... .... 001001 . ..... @rrr_cf_d 194xor 000010 ..... ..... .... 001010 . ..... @rrr_cf_d 195uxor 000010 ..... ..... .... 001110 . ..... @rrr_cf_d 196ds 000010 ..... ..... .... 010001 0 ..... @rrr_cf 197cmpclr 000010 ..... ..... .... 100010 . ..... @rrr_cf_d 198uaddcm 000010 ..... ..... .... 100110 . ..... @rrr_cf_d 199uaddcm_tc 000010 ..... ..... .... 100111 . ..... @rrr_cf_d 200dcor 000010 ..... 00000 .... 101110 . ..... @rr_cf_d 201dcor_i 000010 ..... 00000 .... 101111 . ..... @rr_cf_d 202 203add 000010 ..... ..... .... 0110.. . ..... @rrr_cf_d_sh 204add_l 000010 ..... ..... .... 1010.. . ..... @rrr_cf_d_sh 205add_tsv 000010 ..... ..... .... 1110.. . ..... @rrr_cf_d_sh 206{ 207 add_c 000010 ..... ..... .... 011100 . ..... @rrr_cf_d_sh0 208 hshladd 000010 ..... ..... 0000 0111.. 0 ..... @rrr_sh 209} 210add_c_tsv 000010 ..... ..... .... 111100 . ..... @rrr_cf_d_sh0 211 212sub 000010 ..... ..... .... 010000 . ..... @rrr_cf_d 213sub_tsv 000010 ..... ..... .... 110000 . ..... @rrr_cf_d 214sub_tc 000010 ..... ..... .... 010011 . ..... @rrr_cf_d 215sub_tsv_tc 000010 ..... ..... .... 110011 . ..... @rrr_cf_d 216{ 217 sub_b 000010 ..... ..... .... 010100 . ..... @rrr_cf_d 218 hshradd 000010 ..... ..... 0000 0101.. 0 ..... @rrr_sh 219} 220sub_b_tsv 000010 ..... ..... .... 110100 . ..... @rrr_cf_d 221 222ldil 001000 t:5 ..................... i=%assemble_21 223addil 001010 r:5 ..................... i=%assemble_21 224ldo 001101 b:5 t:5 -- .............. i=%lowsign_14 225 226addi 101101 ..... ..... .... 0 ........... @rri_cf 227addi_tsv 101101 ..... ..... .... 1 ........... @rri_cf 228addi_tc 101100 ..... ..... .... 0 ........... @rri_cf 229addi_tc_tsv 101100 ..... ..... .... 1 ........... @rri_cf 230 231subi 100101 ..... ..... .... 0 ........... @rri_cf 232subi_tsv 100101 ..... ..... .... 1 ........... @rri_cf 233 234cmpiclr 100100 ..... ..... .... . ........... @rri_cf_d 235 236hadd 000010 ..... ..... 00000011 11 0 ..... @rrr 237hadd_ss 000010 ..... ..... 00000011 01 0 ..... @rrr 238hadd_us 000010 ..... ..... 00000011 00 0 ..... @rrr 239 240havg 000010 ..... ..... 00000010 11 0 ..... @rrr 241 242hshl 111110 00000 r:5 100010 i:4 0 t:5 &rri 243hshr_s 111110 r:5 00000 110011 i:4 0 t:5 &rri 244hshr_u 111110 r:5 00000 110010 i:4 0 t:5 &rri 245 246hsub 000010 ..... ..... 00000001 11 0 ..... @rrr 247hsub_ss 000010 ..... ..... 00000001 01 0 ..... @rrr 248hsub_us 000010 ..... ..... 00000001 00 0 ..... @rrr 249 250mixh_l 111110 ..... ..... 1 00 00100000 ..... @rrr 251mixh_r 111110 ..... ..... 1 10 00100000 ..... @rrr 252mixw_l 111110 ..... ..... 1 00 00000000 ..... @rrr 253mixw_r 111110 ..... ..... 1 10 00000000 ..... @rrr 254 255permh 111110 r1:5 r2:5 0 c0:2 0 c1:2 c2:2 c3:2 0 t:5 256 257#### 258# Index Mem 259#### 260 261@ldstx ...... b:5 x:5 sp:2 scale:1 ....... m:1 t:5 &ldst disp=0 262@ldim5 ...... b:5 ..... sp:2 ......... t:5 \ 263 &ldst disp=%im5_16 x=0 scale=0 m=%ma_to_m 264@stim5 ...... b:5 t:5 sp:2 ......... ..... \ 265 &ldst disp=%im5_0 x=0 scale=0 m=%ma_to_m 266 267ld 000011 ..... ..... .. . 1 -- 00 size:2 ...... @ldim5 268ld 000011 ..... ..... .. . 0 -- 00 size:2 ...... @ldstx 269st 000011 ..... ..... .. . 1 -- 10 size:2 ...... @stim5 270ldc 000011 ..... ..... .. . 1 -- 0111 ...... @ldim5 size=2 271ldc 000011 ..... ..... .. . 0 -- 0111 ...... @ldstx size=2 272ldc 000011 ..... ..... .. . 1 -- 0101 ...... @ldim5 size=3 273ldc 000011 ..... ..... .. . 0 -- 0101 ...... @ldstx size=3 274lda 000011 ..... ..... .. . 1 -- 0110 ...... @ldim5 size=2 275lda 000011 ..... ..... .. . 0 -- 0110 ...... @ldstx size=2 276lda 000011 ..... ..... .. . 1 -- 0100 ...... @ldim5 size=3 277lda 000011 ..... ..... .. . 0 -- 0100 ...... @ldstx size=3 278sta 000011 ..... ..... .. . 1 -- 1110 ...... @stim5 size=2 279sta 000011 ..... ..... .. . 1 -- 1111 ...... @stim5 size=3 280stby 000011 b:5 r:5 sp:2 a:1 1 -- 1100 m:1 ..... disp=%im5_0 281stdby 000011 b:5 r:5 sp:2 a:1 1 -- 1101 m:1 ..... disp=%im5_0 282 283@fldstwx ...... b:5 x:5 sp:2 scale:1 ....... m:1 ..... \ 284 &ldst t=%rt64 disp=0 size=2 285@fldstwi ...... b:5 ..... sp:2 . ....... . ..... \ 286 &ldst t=%rt64 disp=%im5_16 m=%ma_to_m x=0 scale=0 size=2 287 288fldw 001001 ..... ..... .. . 0 -- 000 . . ..... @fldstwx 289fldw 001001 ..... ..... .. . 1 -- 000 . . ..... @fldstwi 290fstw 001001 ..... ..... .. . 0 -- 100 . . ..... @fldstwx 291fstw 001001 ..... ..... .. . 1 -- 100 . . ..... @fldstwi 292 293@fldstdx ...... b:5 x:5 sp:2 scale:1 ....... m:1 t:5 \ 294 &ldst disp=0 size=3 295@fldstdi ...... b:5 ..... sp:2 . ....... . t:5 \ 296 &ldst disp=%im5_16 m=%ma_to_m x=0 scale=0 size=3 297 298fldd 001011 ..... ..... .. . 0 -- 000 0 . ..... @fldstdx 299fldd 001011 ..... ..... .. . 1 -- 000 0 . ..... @fldstdi 300fstd 001011 ..... ..... .. . 0 -- 100 0 . ..... @fldstdx 301fstd 001011 ..... ..... .. . 1 -- 100 0 . ..... @fldstdi 302 303#### 304# Offset Mem 305#### 306 307@ldstim11 ...... b:5 t:5 sp:2 .............. \ 308 &ldst disp=%assemble_11a m=%ma2_to_m x=0 scale=0 size=3 309@ldstim14 ...... b:5 t:5 sp:2 .............. \ 310 &ldst disp=%lowsign_14 x=0 scale=0 m=0 311@ldstim14m ...... b:5 t:5 sp:2 .............. \ 312 &ldst disp=%lowsign_14 x=0 scale=0 m=%neg_to_m 313@ldstim12m ...... b:5 t:5 sp:2 .............. \ 314 &ldst disp=%assemble_12a x=0 scale=0 m=%pos_to_m 315 316# LDB, LDH, LDW, LDWM 317ld 010000 ..... ..... .. .............. @ldstim14 size=0 318ld 010001 ..... ..... .. .............. @ldstim14 size=1 319ld 010010 ..... ..... .. .............. @ldstim14 size=2 320ld 010011 ..... ..... .. .............. @ldstim14m size=2 321ld 010111 ..... ..... .. ...........10. @ldstim12m size=2 322 323# STB, STH, STW, STWM 324st 011000 ..... ..... .. .............. @ldstim14 size=0 325st 011001 ..... ..... .. .............. @ldstim14 size=1 326st 011010 ..... ..... .. .............. @ldstim14 size=2 327st 011011 ..... ..... .. .............. @ldstim14m size=2 328st 011111 ..... ..... .. ...........10. @ldstim12m size=2 329 330fldw 010110 b:5 ..... sp:2 .............. \ 331 &ldst disp=%assemble_12a t=%rm64 m=%a_to_m x=0 scale=0 size=2 332fldw 010111 b:5 ..... sp:2 ...........0.. \ 333 &ldst disp=%assemble_12a t=%rm64 m=0 x=0 scale=0 size=2 334 335fstw 011110 b:5 ..... sp:2 .............. \ 336 &ldst disp=%assemble_12a t=%rm64 m=%a_to_m x=0 scale=0 size=2 337fstw 011111 b:5 ..... sp:2 ...........0.. \ 338 &ldst disp=%assemble_12a t=%rm64 m=0 x=0 scale=0 size=2 339 340ld 010100 ..... ..... .. ............0. @ldstim11 341fldd 010100 ..... ..... .. ............1. @ldstim11 342 343st 011100 ..... ..... .. ............0. @ldstim11 344fstd 011100 ..... ..... .. ............1. @ldstim11 345 346#### 347# Floating-point Multiply Add 348#### 349 350&mpyadd rm1 rm2 ta ra tm 351@mpyadd ...... rm1:5 rm2:5 ta:5 ra:5 . tm:5 &mpyadd 352 353fmpyadd_f 000110 ..... ..... ..... ..... 0 ..... @mpyadd 354fmpyadd_d 000110 ..... ..... ..... ..... 1 ..... @mpyadd 355fmpysub_f 100110 ..... ..... ..... ..... 0 ..... @mpyadd 356fmpysub_d 100110 ..... ..... ..... ..... 1 ..... @mpyadd 357 358#### 359# Conditional Branches 360#### 361 362bb_sar 110000 00000 r:5 c:1 1 d:1 ........... n:1 . disp=%assemble_12 363bb_imm 110001 p:5 r:5 c:1 1 d:1 ........... n:1 . disp=%assemble_12 364 365movb 110010 ..... ..... ... ........... . . @rrb_cf f=0 366movbi 110011 ..... ..... ... ........... . . @rib_cf f=0 367 368cmpb 100000 ..... ..... ... ........... . . @rrb_cdf d=0 f=0 369cmpb 100010 ..... ..... ... ........... . . @rrb_cdf d=0 f=1 370cmpb 100111 ..... ..... ... ........... . . @rrb_cdf d=1 f=0 371cmpb 101111 ..... ..... ... ........... . . @rrb_cdf d=1 f=1 372cmpbi 100001 ..... ..... ... ........... . . @rib_cdf d=0 f=0 373cmpbi 100011 ..... ..... ... ........... . . @rib_cdf d=0 f=1 374cmpbi 111011 r:5 ..... f:1 .. ........... n:1 . \ 375 &rib_c_d_f d=1 disp=%assemble_12 c=%cmpbid_c i=%im5_16 376 377addb 101000 ..... ..... ... ........... . . @rrb_cf f=0 378addb 101010 ..... ..... ... ........... . . @rrb_cf f=1 379addbi 101001 ..... ..... ... ........... . . @rib_cf f=0 380addbi 101011 ..... ..... ... ........... . . @rib_cf f=1 381 382#### 383# Shift, Extract, Deposit 384#### 385 386shrp_sar 110100 r2:5 r1:5 c:3 00 0 d:1 0000 t:5 387shrp_imm 110100 r2:5 r1:5 c:3 01 0 cpos:5 t:5 d=0 388shrp_imm 110100 r2:5 r1:5 c:3 0. 1 ..... t:5 \ 389 d=1 cpos=%cpos6_11 390 391extr_sar 110100 r:5 t:5 c:3 10 se:1 00 000 ..... d=0 len=%len5 392extr_sar 110100 r:5 t:5 c:3 10 se:1 1. 000 ..... d=1 len=%len6_8 393extr_imm 110100 r:5 t:5 c:3 11 se:1 pos:5 ..... d=0 len=%len5 394extr_imm 110110 r:5 t:5 c:3 .. se:1 ..... ..... \ 395 d=1 len=%len6_12 pos=%cpos6_11 396 397dep_sar 110101 t:5 r:5 c:3 00 nz:1 00 000 ..... d=0 len=%len5 398dep_sar 110101 t:5 r:5 c:3 00 nz:1 1. 000 ..... d=1 len=%len6_8 399dep_imm 110101 t:5 r:5 c:3 01 nz:1 cpos:5 ..... d=0 len=%len5 400dep_imm 111100 t:5 r:5 c:3 .. nz:1 ..... ..... \ 401 d=1 len=%len6_12 cpos=%cpos6_11 402depi_sar 110101 t:5 ..... c:3 10 nz:1 d:1 . 000 ..... \ 403 i=%im5_16 len=%len6_8 404depi_imm 110101 t:5 ..... c:3 11 nz:1 cpos:5 ..... \ 405 d=0 i=%im5_16 len=%len5 406depi_imm 111101 t:5 ..... c:3 .. nz:1 ..... ..... \ 407 d=1 i=%im5_16 len=%len6_12 cpos=%cpos6_11 408 409#### 410# Branch External 411#### 412 413&BE b l n disp sp 414@be ...... b:5 ..... ... ........... n:1 . \ 415 &BE disp=%assemble_17 sp=%assemble_sr3 416 417be 111000 ..... ..... ... ........... . . @be l=0 418be 111001 ..... ..... ... ........... . . @be l=31 419 420#### 421# Branch 422#### 423 424&BL l n disp 425@bl ...... l:5 ..... ... ........... n:1 . &BL disp=%assemble_17 426 427# B,L and B,L,PUSH 428bl 111010 ..... ..... 000 ........... . . @bl 429bl 111010 ..... ..... 100 ........... . . @bl 430# B,L (long displacement) 431bl 111010 ..... ..... 101 ........... n:1 . &BL l=2 \ 432 disp=%assemble_22 433b_gate 111010 ..... ..... 001 ........... . . @bl 434blr 111010 l:5 x:5 010 00000000000 n:1 0 435nopbts 111010 00000 00000 010 0---------1 0 1 # clrbts/popbts 436nopbts 111010 00000 ----- 010 00000000000 0 1 # pushbts/pushnom 437bv 111010 b:5 x:5 110 00000000000 n:1 0 438bve 111010 b:5 00000 110 10000000000 n:1 - l=0 439bve 111010 b:5 00000 111 10000000000 n:1 - l=2 440 441#### 442# FP Fused Multiple-Add 443#### 444 445fmpyfadd_f 101110 ..... ..... ... . 0 ... . . neg:1 ..... \ 446 rm1=%ra64 rm2=%rb64 ra3=%rc64 t=%rt64 447fmpyfadd_d 101110 rm1:5 rm2:5 ... 0 1 ..0 0 0 neg:1 t:5 ra3=%rc32 448 449#### 450# FP operations 451#### 452 453&fclass01 r t 454&fclass2 r1 r2 c y 455&fclass3 r1 r2 t 456 457@f0c_0 ...... r:5 00000 ..... 00 000 0 t:5 &fclass01 458@f0c_1 ...... r:5 000.. ..... 01 000 0 t:5 &fclass01 459@f0c_2 ...... r1:5 r2:5 y:3 .. 10 000 . c:5 &fclass2 460@f0c_3 ...... r1:5 r2:5 ..... 11 000 0 t:5 &fclass3 461 462@f0e_f_0 ...... ..... 00000 ... 0 0 000 .. 0 ..... \ 463 &fclass01 r=%ra64 t=%rt64 464@f0e_d_0 ...... r:5 00000 ... 0 1 000 00 0 t:5 &fclass01 465 466@f0e_ff_1 ...... ..... 000 ... 0000 010 .. 0 ..... \ 467 &fclass01 r=%ra64 t=%rt64 468@f0e_fd_1 ...... ..... 000 ... 0100 010 .0 0 t:5 &fclass01 r=%ra64 469@f0e_df_1 ...... r:5 000 ... 0001 010 0. 0 ..... &fclass01 t=%rt64 470@f0e_dd_1 ...... r:5 000 ... 0101 010 00 0 t:5 &fclass01 471 472@f0e_f_2 ...... ..... ..... y:3 .0 100 .00 c:5 \ 473 &fclass2 r1=%ra64 r2=%rb64 474@f0e_d_2 ...... r1:5 r2:5 y:3 01 100 000 c:5 &fclass2 475 476@f0e_f_3 ...... ..... ..... ... .0 110 ..0 ..... \ 477 &fclass3 r1=%ra64 r2=%rb64 t=%rt64 478@f0e_d_3 ...... r1:5 r2:5 ... 01 110 000 t:5 &fclass3 479 480# Floating point class 0 481 482fid_f 001100 00000 00000 000 00 000000 00000 483 484fcpy_f 001100 ..... ..... 010 00 ...... ..... @f0c_0 485fabs_f 001100 ..... ..... 011 00 ...... ..... @f0c_0 486fsqrt_f 001100 ..... ..... 100 00 ...... ..... @f0c_0 487frnd_f 001100 ..... ..... 101 00 ...... ..... @f0c_0 488fneg_f 001100 ..... ..... 110 00 ...... ..... @f0c_0 489fnegabs_f 001100 ..... ..... 111 00 ...... ..... @f0c_0 490 491fcpy_d 001100 ..... ..... 010 01 ...... ..... @f0c_0 492fabs_d 001100 ..... ..... 011 01 ...... ..... @f0c_0 493fsqrt_d 001100 ..... ..... 100 01 ...... ..... @f0c_0 494frnd_d 001100 ..... ..... 101 01 ...... ..... @f0c_0 495fneg_d 001100 ..... ..... 110 01 ...... ..... @f0c_0 496fnegabs_d 001100 ..... ..... 111 01 ...... ..... @f0c_0 497 498fcpy_f 001110 ..... ..... 010 ........ ..... @f0e_f_0 499fabs_f 001110 ..... ..... 011 ........ ..... @f0e_f_0 500fsqrt_f 001110 ..... ..... 100 ........ ..... @f0e_f_0 501frnd_f 001110 ..... ..... 101 ........ ..... @f0e_f_0 502fneg_f 001110 ..... ..... 110 ........ ..... @f0e_f_0 503fnegabs_f 001110 ..... ..... 111 ........ ..... @f0e_f_0 504 505fcpy_d 001110 ..... ..... 010 ........ ..... @f0e_d_0 506fabs_d 001110 ..... ..... 011 ........ ..... @f0e_d_0 507fsqrt_d 001110 ..... ..... 100 ........ ..... @f0e_d_0 508frnd_d 001110 ..... ..... 101 ........ ..... @f0e_d_0 509fneg_d 001110 ..... ..... 110 ........ ..... @f0e_d_0 510fnegabs_d 001110 ..... ..... 111 ........ ..... @f0e_d_0 511 512# Floating point class 1 513 514# float/float 515fcnv_d_f 001100 ..... ... 000 00 01 ...... ..... @f0c_1 516fcnv_f_d 001100 ..... ... 000 01 00 ...... ..... @f0c_1 517 518fcnv_d_f 001110 ..... ... 000 .......... ..... @f0e_df_1 519fcnv_f_d 001110 ..... ... 000 .......... ..... @f0e_fd_1 520 521# int/float 522fcnv_w_f 001100 ..... ... 001 00 00 ...... ..... @f0c_1 523fcnv_q_f 001100 ..... ... 001 00 01 ...... ..... @f0c_1 524fcnv_w_d 001100 ..... ... 001 01 00 ...... ..... @f0c_1 525fcnv_q_d 001100 ..... ... 001 01 01 ...... ..... @f0c_1 526 527fcnv_w_f 001110 ..... ... 001 .......... ..... @f0e_ff_1 528fcnv_q_f 001110 ..... ... 001 .......... ..... @f0e_df_1 529fcnv_w_d 001110 ..... ... 001 .......... ..... @f0e_fd_1 530fcnv_q_d 001110 ..... ... 001 .......... ..... @f0e_dd_1 531 532# float/int 533fcnv_f_w 001100 ..... ... 010 00 00 ...... ..... @f0c_1 534fcnv_d_w 001100 ..... ... 010 00 01 ...... ..... @f0c_1 535fcnv_f_q 001100 ..... ... 010 01 00 ...... ..... @f0c_1 536fcnv_d_q 001100 ..... ... 010 01 01 ...... ..... @f0c_1 537 538fcnv_f_w 001110 ..... ... 010 .......... ..... @f0e_ff_1 539fcnv_d_w 001110 ..... ... 010 .......... ..... @f0e_df_1 540fcnv_f_q 001110 ..... ... 010 .......... ..... @f0e_fd_1 541fcnv_d_q 001110 ..... ... 010 .......... ..... @f0e_dd_1 542 543# float/int truncate 544fcnv_t_f_w 001100 ..... ... 011 00 00 ...... ..... @f0c_1 545fcnv_t_d_w 001100 ..... ... 011 00 01 ...... ..... @f0c_1 546fcnv_t_f_q 001100 ..... ... 011 01 00 ...... ..... @f0c_1 547fcnv_t_d_q 001100 ..... ... 011 01 01 ...... ..... @f0c_1 548 549fcnv_t_f_w 001110 ..... ... 011 .......... ..... @f0e_ff_1 550fcnv_t_d_w 001110 ..... ... 011 .......... ..... @f0e_df_1 551fcnv_t_f_q 001110 ..... ... 011 .......... ..... @f0e_fd_1 552fcnv_t_d_q 001110 ..... ... 011 .......... ..... @f0e_dd_1 553 554# uint/float 555fcnv_uw_f 001100 ..... ... 101 00 00 ...... ..... @f0c_1 556fcnv_uq_f 001100 ..... ... 101 00 01 ...... ..... @f0c_1 557fcnv_uw_d 001100 ..... ... 101 01 00 ...... ..... @f0c_1 558fcnv_uq_d 001100 ..... ... 101 01 01 ...... ..... @f0c_1 559 560fcnv_uw_f 001110 ..... ... 101 .......... ..... @f0e_ff_1 561fcnv_uq_f 001110 ..... ... 101 .......... ..... @f0e_df_1 562fcnv_uw_d 001110 ..... ... 101 .......... ..... @f0e_fd_1 563fcnv_uq_d 001110 ..... ... 101 .......... ..... @f0e_dd_1 564 565# float/int 566fcnv_f_uw 001100 ..... ... 110 00 00 ...... ..... @f0c_1 567fcnv_d_uw 001100 ..... ... 110 00 01 ...... ..... @f0c_1 568fcnv_f_uq 001100 ..... ... 110 01 00 ...... ..... @f0c_1 569fcnv_d_uq 001100 ..... ... 110 01 01 ...... ..... @f0c_1 570 571fcnv_f_uw 001110 ..... ... 110 .......... ..... @f0e_ff_1 572fcnv_d_uw 001110 ..... ... 110 .......... ..... @f0e_df_1 573fcnv_f_uq 001110 ..... ... 110 .......... ..... @f0e_fd_1 574fcnv_d_uq 001110 ..... ... 110 .......... ..... @f0e_dd_1 575 576# float/int truncate 577fcnv_t_f_uw 001100 ..... ... 111 00 00 ...... ..... @f0c_1 578fcnv_t_d_uw 001100 ..... ... 111 00 01 ...... ..... @f0c_1 579fcnv_t_f_uq 001100 ..... ... 111 01 00 ...... ..... @f0c_1 580fcnv_t_d_uq 001100 ..... ... 111 01 01 ...... ..... @f0c_1 581 582fcnv_t_f_uw 001110 ..... ... 111 .......... ..... @f0e_ff_1 583fcnv_t_d_uw 001110 ..... ... 111 .......... ..... @f0e_df_1 584fcnv_t_f_uq 001110 ..... ... 111 .......... ..... @f0e_fd_1 585fcnv_t_d_uq 001110 ..... ... 111 .......... ..... @f0e_dd_1 586 587# Floating point class 2 588 589ftest 001100 00000 00000 y:3 00 10000 1 c:5 590 591fcmp_f 001100 ..... ..... ... 00 ..... 0 ..... @f0c_2 592fcmp_d 001100 ..... ..... ... 01 ..... 0 ..... @f0c_2 593 594fcmp_f 001110 ..... ..... ... ..... ... ..... @f0e_f_2 595fcmp_d 001110 ..... ..... ... ..... ... ..... @f0e_d_2 596 597# Floating point class 3 598 599fadd_f 001100 ..... ..... 000 00 ...... ..... @f0c_3 600fsub_f 001100 ..... ..... 001 00 ...... ..... @f0c_3 601fmpy_f 001100 ..... ..... 010 00 ...... ..... @f0c_3 602fdiv_f 001100 ..... ..... 011 00 ...... ..... @f0c_3 603 604fadd_d 001100 ..... ..... 000 01 ...... ..... @f0c_3 605fsub_d 001100 ..... ..... 001 01 ...... ..... @f0c_3 606fmpy_d 001100 ..... ..... 010 01 ...... ..... @f0c_3 607fdiv_d 001100 ..... ..... 011 01 ...... ..... @f0c_3 608 609fadd_f 001110 ..... ..... 000 ..... ... ..... @f0e_f_3 610fsub_f 001110 ..... ..... 001 ..... ... ..... @f0e_f_3 611fmpy_f 001110 ..... ..... 010 ..... ... ..... @f0e_f_3 612fdiv_f 001110 ..... ..... 011 ..... ... ..... @f0e_f_3 613 614fadd_d 001110 ..... ..... 000 ..... ... ..... @f0e_d_3 615fsub_d 001110 ..... ..... 001 ..... ... ..... @f0e_d_3 616fmpy_d 001110 ..... ..... 010 ..... ... ..... @f0e_d_3 617fdiv_d 001110 ..... ..... 011 ..... ... ..... @f0e_d_3 618 619xmpyu 001110 ..... ..... 010 .0111 .00 t:5 r1=%ra64 r2=%rb64 620 621# diag 622diag 000101 i:26 623