1# 2# HPPA instruction decode definitions. 3# 4# Copyright (c) 2018 Richard Henderson <rth@twiddle.net> 5# 6# This library is free software; you can redistribute it and/or 7# modify it under the terms of the GNU Lesser General Public 8# License as published by the Free Software Foundation; either 9# version 2 of the License, or (at your option) any later version. 10# 11# This library is distributed in the hope that it will be useful, 12# but WITHOUT ANY WARRANTY; without even the implied warranty of 13# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14# Lesser General Public License for more details. 15# 16# You should have received a copy of the GNU Lesser General Public 17# License along with this library; if not, see <http://www.gnu.org/licenses/>. 18# 19 20#### 21# Field definitions 22#### 23 24%assemble_sr3 13:1 14:2 25%assemble_sr3x 13:1 14:2 !function=expand_sr3x 26 27%assemble_11a 0:s1 4:10 !function=expand_shl3 28%assemble_12 0:s1 2:1 3:10 !function=expand_shl2 29%assemble_12a 0:s1 3:11 !function=expand_shl2 30%assemble_17 0:s1 16:5 2:1 3:10 !function=expand_shl2 31%assemble_22 0:s1 16:10 2:1 3:10 !function=expand_shl2 32 33%assemble_21 0:s1 1:11 14:2 16:5 12:2 !function=expand_shl11 34 35%lowsign_11 0:s1 1:10 36%lowsign_14 0:s1 1:13 37 38%sm_imm 16:10 !function=expand_sm_imm 39 40%rm64 1:1 16:5 41%rt64 6:1 0:5 42%ra64 7:1 21:5 43%rb64 12:1 16:5 44%rc64 8:1 13:3 9:2 45%rc32 13:3 9:2 46 47%im5_0 0:s1 1:4 48%im5_16 16:s1 17:4 49%ma_to_m 5:1 13:1 !function=ma_to_m 50%ma2_to_m 2:2 !function=ma_to_m 51%pos_to_m 0:1 !function=pos_to_m 52%neg_to_m 0:1 !function=neg_to_m 53%a_to_m 2:1 !function=neg_to_m 54 55#### 56# Argument set definitions 57#### 58 59# All insns that need to form a virtual address should use this set. 60&ldst t b x disp sp m scale size 61 62&rr_cf t r cf 63&rrr_cf t r1 r2 cf 64&rrr_cf_sh t r1 r2 cf sh 65&rri_cf t r i cf 66 67&rrb_c_f disp n c f r1 r2 68&rib_c_f disp n c f r i 69 70#### 71# Format definitions 72#### 73 74@rr_cf ...... r:5 ..... cf:4 ....... t:5 &rr_cf 75@rrr_cf ...... r2:5 r1:5 cf:4 ....... t:5 &rrr_cf 76@rrr_cf_sh ...... r2:5 r1:5 cf:4 .... sh:2 . t:5 &rrr_cf_sh 77@rrr_cf_sh0 ...... r2:5 r1:5 cf:4 ....... t:5 &rrr_cf_sh sh=0 78@rri_cf ...... r:5 t:5 cf:4 . ........... &rri_cf i=%lowsign_11 79 80@rrb_cf ...... r2:5 r1:5 c:3 ........... n:1 . \ 81 &rrb_c_f disp=%assemble_12 82@rib_cf ...... r:5 ..... c:3 ........... n:1 . \ 83 &rib_c_f disp=%assemble_12 i=%im5_16 84 85#### 86# System 87#### 88 89break 000000 ----- ----- --- 00000000 ----- 90 91mtsp 000000 ----- r:5 ... 11000001 00000 sp=%assemble_sr3 92mtctl 000000 t:5 r:5 --- 11000010 00000 93mtsarcm 000000 01011 r:5 --- 11000110 00000 94mtsm 000000 00000 r:5 000 11000011 00000 95 96mfia 000000 ----- 00000 --- 10100101 t:5 97mfsp 000000 ----- 00000 ... 00100101 t:5 sp=%assemble_sr3 98mfctl 000000 r:5 00000- e:1 -01000101 t:5 99 100sync 000000 ----- ----- 000 00100000 00000 # sync, syncdma 101 102ldsid 000000 b:5 ----- sp:2 0 10000101 t:5 103 104rsm 000000 .......... 000 01110011 t:5 i=%sm_imm 105ssm 000000 .......... 000 01101011 t:5 i=%sm_imm 106 107rfi 000000 ----- ----- --- 01100000 00000 108rfi_r 000000 ----- ----- --- 01100101 00000 109 110# These are artificial instructions used by QEMU firmware. 111# They are allocated from the unassigned instruction space. 112halt 1111 1111 1111 1101 1110 1010 1101 0000 113reset 1111 1111 1111 1101 1110 1010 1101 0001 114 115#### 116# Memory Management 117#### 118 119@addrx ...... b:5 x:5 .. ........ m:1 ..... \ 120 &ldst disp=0 scale=0 t=0 sp=0 size=0 121 122nop 000001 ----- ----- -- 11001010 0 ----- # fdc, disp 123nop_addrx 000001 ..... ..... -- 01001010 . ----- @addrx # fdc, index 124nop_addrx 000001 ..... ..... -- 01001011 . ----- @addrx # fdce 125nop_addrx 000001 ..... ..... --- 0001010 . ----- @addrx # fic 0x0a 126nop_addrx 000001 ..... ..... -- 01001111 . 00000 @addrx # fic 0x4f 127nop_addrx 000001 ..... ..... --- 0001011 . ----- @addrx # fice 128nop_addrx 000001 ..... ..... -- 01001110 . 00000 @addrx # pdc 129 130probe 000001 b:5 ri:5 sp:2 imm:1 100011 write:1 0 t:5 131 132ixtlbx 000001 b:5 r:5 sp:2 0100000 addr:1 0 00000 data=1 133ixtlbx 000001 b:5 r:5 ... 000000 addr:1 0 00000 \ 134 sp=%assemble_sr3x data=0 135 136pxtlbx 000001 b:5 x:5 sp:2 0100100 local:1 m:1 ----- data=1 137pxtlbx 000001 b:5 x:5 ... 000100 local:1 m:1 ----- \ 138 sp=%assemble_sr3x data=0 139 140lpa 000001 b:5 x:5 sp:2 01001101 m:1 t:5 \ 141 &ldst disp=0 scale=0 size=0 142 143lci 000001 ----- ----- -- 01001100 0 t:5 144 145#### 146# Arith/Log 147#### 148 149andcm 000010 ..... ..... .... 000000 0 ..... @rrr_cf 150and 000010 ..... ..... .... 001000 0 ..... @rrr_cf 151or 000010 ..... ..... .... 001001 0 ..... @rrr_cf 152xor 000010 ..... ..... .... 001010 0 ..... @rrr_cf 153uxor 000010 ..... ..... .... 001110 0 ..... @rrr_cf 154ds 000010 ..... ..... .... 010001 0 ..... @rrr_cf 155cmpclr 000010 ..... ..... .... 100010 0 ..... @rrr_cf 156uaddcm 000010 ..... ..... .... 100110 0 ..... @rrr_cf 157uaddcm_tc 000010 ..... ..... .... 100111 0 ..... @rrr_cf 158dcor 000010 ..... 00000 .... 101110 0 ..... @rr_cf 159dcor_i 000010 ..... 00000 .... 101111 0 ..... @rr_cf 160 161add 000010 ..... ..... .... 0110.. 0 ..... @rrr_cf_sh 162add_l 000010 ..... ..... .... 1010.. 0 ..... @rrr_cf_sh 163add_tsv 000010 ..... ..... .... 1110.. 0 ..... @rrr_cf_sh 164add_c 000010 ..... ..... .... 011100 0 ..... @rrr_cf_sh0 165add_c_tsv 000010 ..... ..... .... 111100 0 ..... @rrr_cf_sh0 166 167sub 000010 ..... ..... .... 010000 0 ..... @rrr_cf 168sub_tsv 000010 ..... ..... .... 110000 0 ..... @rrr_cf 169sub_tc 000010 ..... ..... .... 010011 0 ..... @rrr_cf 170sub_tsv_tc 000010 ..... ..... .... 110011 0 ..... @rrr_cf 171sub_b 000010 ..... ..... .... 010100 0 ..... @rrr_cf 172sub_b_tsv 000010 ..... ..... .... 110100 0 ..... @rrr_cf 173 174ldil 001000 t:5 ..................... i=%assemble_21 175addil 001010 r:5 ..................... i=%assemble_21 176ldo 001101 b:5 t:5 -- .............. i=%lowsign_14 177 178addi 101101 ..... ..... .... 0 ........... @rri_cf 179addi_tsv 101101 ..... ..... .... 1 ........... @rri_cf 180addi_tc 101100 ..... ..... .... 0 ........... @rri_cf 181addi_tc_tsv 101100 ..... ..... .... 1 ........... @rri_cf 182 183subi 100101 ..... ..... .... 0 ........... @rri_cf 184subi_tsv 100101 ..... ..... .... 1 ........... @rri_cf 185 186cmpiclr 100100 ..... ..... .... 0 ........... @rri_cf 187 188#### 189# Index Mem 190#### 191 192@ldstx ...... b:5 x:5 sp:2 scale:1 ....... m:1 t:5 &ldst disp=0 193@ldim5 ...... b:5 ..... sp:2 ......... t:5 \ 194 &ldst disp=%im5_16 x=0 scale=0 m=%ma_to_m 195@stim5 ...... b:5 t:5 sp:2 ......... ..... \ 196 &ldst disp=%im5_0 x=0 scale=0 m=%ma_to_m 197 198ld 000011 ..... ..... .. . 1 -- 00 size:2 ...... @ldim5 199ld 000011 ..... ..... .. . 0 -- 00 size:2 ...... @ldstx 200st 000011 ..... ..... .. . 1 -- 10 size:2 ...... @stim5 201ldc 000011 ..... ..... .. . 1 -- 0111 ...... @ldim5 size=2 202ldc 000011 ..... ..... .. . 0 -- 0111 ...... @ldstx size=2 203lda 000011 ..... ..... .. . 1 -- 0110 ...... @ldim5 size=2 204lda 000011 ..... ..... .. . 0 -- 0110 ...... @ldstx size=2 205sta 000011 ..... ..... .. . 1 -- 1110 ...... @stim5 size=2 206stby 000011 b:5 r:5 sp:2 a:1 1 -- 1100 m:1 ..... disp=%im5_0 207 208@fldstwx ...... b:5 x:5 sp:2 scale:1 ....... m:1 ..... \ 209 &ldst t=%rt64 disp=0 size=2 210@fldstwi ...... b:5 ..... sp:2 . ....... . ..... \ 211 &ldst t=%rt64 disp=%im5_16 m=%ma_to_m x=0 scale=0 size=2 212 213fldw 001001 ..... ..... .. . 0 -- 000 . . ..... @fldstwx 214fldw 001001 ..... ..... .. . 1 -- 000 . . ..... @fldstwi 215fstw 001001 ..... ..... .. . 0 -- 100 . . ..... @fldstwx 216fstw 001001 ..... ..... .. . 1 -- 100 . . ..... @fldstwi 217 218@fldstdx ...... b:5 x:5 sp:2 scale:1 ....... m:1 t:5 \ 219 &ldst disp=0 size=3 220@fldstdi ...... b:5 ..... sp:2 . ....... . t:5 \ 221 &ldst disp=%im5_16 m=%ma_to_m x=0 scale=0 size=3 222 223fldd 001011 ..... ..... .. . 0 -- 000 0 . ..... @fldstdx 224fldd 001011 ..... ..... .. . 1 -- 000 0 . ..... @fldstdi 225fstd 001011 ..... ..... .. . 0 -- 100 0 . ..... @fldstdx 226fstd 001011 ..... ..... .. . 1 -- 100 0 . ..... @fldstdi 227 228#### 229# Offset Mem 230#### 231 232@ldstim14 ...... b:5 t:5 sp:2 .............. \ 233 &ldst disp=%lowsign_14 x=0 scale=0 m=0 234@ldstim14m ...... b:5 t:5 sp:2 .............. \ 235 &ldst disp=%lowsign_14 x=0 scale=0 m=%neg_to_m 236@ldstim12m ...... b:5 t:5 sp:2 .............. \ 237 &ldst disp=%assemble_12a x=0 scale=0 m=%pos_to_m 238 239# LDB, LDH, LDW, LDWM 240ld 010000 ..... ..... .. .............. @ldstim14 size=0 241ld 010001 ..... ..... .. .............. @ldstim14 size=1 242ld 010010 ..... ..... .. .............. @ldstim14 size=2 243ld 010011 ..... ..... .. .............. @ldstim14m size=2 244ld 010111 ..... ..... .. ...........10. @ldstim12m size=2 245 246# STB, STH, STW, STWM 247st 011000 ..... ..... .. .............. @ldstim14 size=0 248st 011001 ..... ..... .. .............. @ldstim14 size=1 249st 011010 ..... ..... .. .............. @ldstim14 size=2 250st 011011 ..... ..... .. .............. @ldstim14m size=2 251st 011111 ..... ..... .. ...........10. @ldstim12m size=2 252 253fldw 010110 b:5 ..... sp:2 .............. \ 254 &ldst disp=%assemble_12a t=%rm64 m=%a_to_m x=0 scale=0 size=2 255fldw 010111 b:5 ..... sp:2 ...........0.. \ 256 &ldst disp=%assemble_12a t=%rm64 m=0 x=0 scale=0 size=2 257 258fstw 011110 b:5 ..... sp:2 .............. \ 259 &ldst disp=%assemble_12a t=%rm64 m=%a_to_m x=0 scale=0 size=2 260fstw 011111 b:5 ..... sp:2 ...........0.. \ 261 &ldst disp=%assemble_12a t=%rm64 m=0 x=0 scale=0 size=2 262 263fldd 010100 b:5 t:5 sp:2 .......... .. 1 . \ 264 &ldst disp=%assemble_11a m=%ma2_to_m x=0 scale=0 size=3 265 266fstd 011100 b:5 t:5 sp:2 .......... .. 1 . \ 267 &ldst disp=%assemble_11a m=%ma2_to_m x=0 scale=0 size=3 268 269#### 270# Floating-point Multiply Add 271#### 272 273&mpyadd rm1 rm2 ta ra tm 274@mpyadd ...... rm1:5 rm2:5 ta:5 ra:5 . tm:5 &mpyadd 275 276fmpyadd_f 000110 ..... ..... ..... ..... 0 ..... @mpyadd 277fmpyadd_d 000110 ..... ..... ..... ..... 1 ..... @mpyadd 278fmpysub_f 100110 ..... ..... ..... ..... 0 ..... @mpyadd 279fmpysub_d 100110 ..... ..... ..... ..... 1 ..... @mpyadd 280 281#### 282# Conditional Branches 283#### 284 285bb_sar 110000 00000 r:5 c:1 10 ........... n:1 . disp=%assemble_12 286bb_imm 110001 p:5 r:5 c:1 10 ........... n:1 . disp=%assemble_12 287 288movb 110010 ..... ..... ... ........... . . @rrb_cf f=0 289movbi 110011 ..... ..... ... ........... . . @rib_cf f=0 290 291cmpb 100000 ..... ..... ... ........... . . @rrb_cf f=0 292cmpb 100010 ..... ..... ... ........... . . @rrb_cf f=1 293cmpbi 100001 ..... ..... ... ........... . . @rib_cf f=0 294cmpbi 100011 ..... ..... ... ........... . . @rib_cf f=1 295 296addb 101000 ..... ..... ... ........... . . @rrb_cf f=0 297addb 101010 ..... ..... ... ........... . . @rrb_cf f=1 298addbi 101001 ..... ..... ... ........... . . @rib_cf f=0 299addbi 101011 ..... ..... ... ........... . . @rib_cf f=1 300 301#### 302# Shift, Extract, Deposit 303#### 304 305shrpw_sar 110100 r2:5 r1:5 c:3 00 0 00000 t:5 306shrpw_imm 110100 r2:5 r1:5 c:3 01 0 cpos:5 t:5 307 308extrw_sar 110100 r:5 t:5 c:3 10 se:1 00000 clen:5 309extrw_imm 110100 r:5 t:5 c:3 11 se:1 pos:5 clen:5 310 311depw_sar 110101 t:5 r:5 c:3 00 nz:1 00000 clen:5 312depw_imm 110101 t:5 r:5 c:3 01 nz:1 cpos:5 clen:5 313depwi_sar 110101 t:5 ..... c:3 10 nz:1 00000 clen:5 i=%im5_16 314depwi_imm 110101 t:5 ..... c:3 11 nz:1 cpos:5 clen:5 i=%im5_16 315 316#### 317# Branch External 318#### 319 320&BE b l n disp sp 321@be ...... b:5 ..... ... ........... n:1 . \ 322 &BE disp=%assemble_17 sp=%assemble_sr3 323 324be 111000 ..... ..... ... ........... . . @be l=0 325be 111001 ..... ..... ... ........... . . @be l=31 326 327#### 328# Branch 329#### 330 331&BL l n disp 332@bl ...... l:5 ..... ... ........... n:1 . &BL disp=%assemble_17 333 334# B,L and B,L,PUSH 335bl 111010 ..... ..... 000 ........... . . @bl 336bl 111010 ..... ..... 100 ........... . . @bl 337# B,L (long displacement) 338bl 111010 ..... ..... 101 ........... n:1 . &BL l=2 \ 339 disp=%assemble_22 340b_gate 111010 ..... ..... 001 ........... . . @bl 341blr 111010 l:5 x:5 010 00000000000 n:1 0 342bv 111010 b:5 x:5 110 00000000000 n:1 0 343bve 111010 b:5 00000 110 10000000000 n:1 - l=0 344bve 111010 b:5 00000 111 10000000000 n:1 - l=2 345 346#### 347# FP Fused Multiple-Add 348#### 349 350fmpyfadd_f 101110 ..... ..... ... . 0 ... . . neg:1 ..... \ 351 rm1=%ra64 rm2=%rb64 ra3=%rc64 t=%rt64 352fmpyfadd_d 101110 rm1:5 rm2:5 ... 0 1 ..0 0 0 neg:1 t:5 ra3=%rc32 353 354#### 355# FP operations 356#### 357 358&fclass01 r t 359&fclass2 r1 r2 c y 360&fclass3 r1 r2 t 361 362@f0c_0 ...... r:5 00000 ..... 00 000 0 t:5 &fclass01 363@f0c_1 ...... r:5 000.. ..... 01 000 0 t:5 &fclass01 364@f0c_2 ...... r1:5 r2:5 y:3 .. 10 000 . c:5 &fclass2 365@f0c_3 ...... r1:5 r2:5 ..... 11 000 0 t:5 &fclass3 366 367@f0e_f_0 ...... ..... 00000 ... 0 0 000 .. 0 ..... \ 368 &fclass01 r=%ra64 t=%rt64 369@f0e_d_0 ...... r:5 00000 ... 0 1 000 00 0 t:5 &fclass01 370 371@f0e_ff_1 ...... ..... 000 ... 0000 010 .. 0 ..... \ 372 &fclass01 r=%ra64 t=%rt64 373@f0e_fd_1 ...... ..... 000 ... 0100 010 .0 0 t:5 &fclass01 r=%ra64 374@f0e_df_1 ...... r:5 000 ... 0001 010 0. 0 ..... &fclass01 t=%rt64 375@f0e_dd_1 ...... r:5 000 ... 0101 010 00 0 t:5 &fclass01 376 377@f0e_f_2 ...... ..... ..... y:3 .0 100 .00 c:5 \ 378 &fclass2 r1=%ra64 r2=%rb64 379@f0e_d_2 ...... r1:5 r2:5 y:3 01 100 000 c:5 &fclass2 380 381@f0e_f_3 ...... ..... ..... ... .0 110 ..0 ..... \ 382 &fclass3 r1=%ra64 r2=%rb64 t=%rt64 383@f0e_d_3 ...... r1:5 r2:5 ... 01 110 000 t:5 384 385# Floating point class 0 386 387# FID. With r = t = 0, which via fcpy puts 0 into fr0. 388# This is machine/revision = 0, which is reserved for simulator. 389fcpy_f 001100 00000 00000 00000 000000 00000 \ 390 &fclass01 r=0 t=0 391 392fcpy_f 001100 ..... ..... 010 00 ...... ..... @f0c_0 393fabs_f 001100 ..... ..... 011 00 ...... ..... @f0c_0 394fsqrt_f 001100 ..... ..... 100 00 ...... ..... @f0c_0 395frnd_f 001100 ..... ..... 101 00 ...... ..... @f0c_0 396fneg_f 001100 ..... ..... 110 00 ...... ..... @f0c_0 397fnegabs_f 001100 ..... ..... 111 00 ...... ..... @f0c_0 398 399fcpy_d 001100 ..... ..... 010 01 ...... ..... @f0c_0 400fabs_d 001100 ..... ..... 011 01 ...... ..... @f0c_0 401fsqrt_d 001100 ..... ..... 100 01 ...... ..... @f0c_0 402frnd_d 001100 ..... ..... 101 01 ...... ..... @f0c_0 403fneg_d 001100 ..... ..... 110 01 ...... ..... @f0c_0 404fnegabs_d 001100 ..... ..... 111 01 ...... ..... @f0c_0 405 406fcpy_f 001110 ..... ..... 010 ........ ..... @f0e_f_0 407fabs_f 001110 ..... ..... 011 ........ ..... @f0e_f_0 408fsqrt_f 001110 ..... ..... 100 ........ ..... @f0e_f_0 409frnd_f 001110 ..... ..... 101 ........ ..... @f0e_f_0 410fneg_f 001110 ..... ..... 110 ........ ..... @f0e_f_0 411fnegabs_f 001110 ..... ..... 111 ........ ..... @f0e_f_0 412 413fcpy_d 001110 ..... ..... 010 ........ ..... @f0e_d_0 414fabs_d 001110 ..... ..... 011 ........ ..... @f0e_d_0 415fsqrt_d 001110 ..... ..... 100 ........ ..... @f0e_d_0 416frnd_d 001110 ..... ..... 101 ........ ..... @f0e_d_0 417fneg_d 001110 ..... ..... 110 ........ ..... @f0e_d_0 418fnegabs_d 001110 ..... ..... 111 ........ ..... @f0e_d_0 419 420# Floating point class 1 421 422# float/float 423fcnv_d_f 001100 ..... ... 000 00 01 ...... ..... @f0c_1 424fcnv_f_d 001100 ..... ... 000 01 00 ...... ..... @f0c_1 425 426fcnv_d_f 001110 ..... ... 000 .......... ..... @f0e_df_1 427fcnv_f_d 001110 ..... ... 000 .......... ..... @f0e_fd_1 428 429# int/float 430fcnv_w_f 001100 ..... ... 001 00 00 ...... ..... @f0c_1 431fcnv_q_f 001100 ..... ... 001 00 01 ...... ..... @f0c_1 432fcnv_w_d 001100 ..... ... 001 01 00 ...... ..... @f0c_1 433fcnv_q_d 001100 ..... ... 001 01 01 ...... ..... @f0c_1 434 435fcnv_w_f 001110 ..... ... 001 .......... ..... @f0e_ff_1 436fcnv_q_f 001110 ..... ... 001 .......... ..... @f0e_df_1 437fcnv_w_d 001110 ..... ... 001 .......... ..... @f0e_fd_1 438fcnv_q_d 001110 ..... ... 001 .......... ..... @f0e_dd_1 439 440# float/int 441fcnv_f_w 001100 ..... ... 010 00 00 ...... ..... @f0c_1 442fcnv_d_w 001100 ..... ... 010 00 01 ...... ..... @f0c_1 443fcnv_f_q 001100 ..... ... 010 01 00 ...... ..... @f0c_1 444fcnv_d_q 001100 ..... ... 010 01 01 ...... ..... @f0c_1 445 446fcnv_f_w 001110 ..... ... 010 .......... ..... @f0e_ff_1 447fcnv_d_w 001110 ..... ... 010 .......... ..... @f0e_df_1 448fcnv_f_q 001110 ..... ... 010 .......... ..... @f0e_fd_1 449fcnv_d_q 001110 ..... ... 010 .......... ..... @f0e_dd_1 450 451# float/int truncate 452fcnv_t_f_w 001100 ..... ... 011 00 00 ...... ..... @f0c_1 453fcnv_t_d_w 001100 ..... ... 011 00 01 ...... ..... @f0c_1 454fcnv_t_f_q 001100 ..... ... 011 01 00 ...... ..... @f0c_1 455fcnv_t_d_q 001100 ..... ... 011 01 01 ...... ..... @f0c_1 456 457fcnv_t_f_w 001110 ..... ... 011 .......... ..... @f0e_ff_1 458fcnv_t_d_w 001110 ..... ... 011 .......... ..... @f0e_df_1 459fcnv_t_f_q 001110 ..... ... 011 .......... ..... @f0e_fd_1 460fcnv_t_d_q 001110 ..... ... 011 .......... ..... @f0e_dd_1 461 462# uint/float 463fcnv_uw_f 001100 ..... ... 101 00 00 ...... ..... @f0c_1 464fcnv_uq_f 001100 ..... ... 101 00 01 ...... ..... @f0c_1 465fcnv_uw_d 001100 ..... ... 101 01 00 ...... ..... @f0c_1 466fcnv_uq_d 001100 ..... ... 101 01 01 ...... ..... @f0c_1 467 468fcnv_uw_f 001110 ..... ... 101 .......... ..... @f0e_ff_1 469fcnv_uq_f 001110 ..... ... 101 .......... ..... @f0e_df_1 470fcnv_uw_d 001110 ..... ... 101 .......... ..... @f0e_fd_1 471fcnv_uq_d 001110 ..... ... 101 .......... ..... @f0e_dd_1 472 473# float/int 474fcnv_f_uw 001100 ..... ... 110 00 00 ...... ..... @f0c_1 475fcnv_d_uw 001100 ..... ... 110 00 01 ...... ..... @f0c_1 476fcnv_f_uq 001100 ..... ... 110 01 00 ...... ..... @f0c_1 477fcnv_d_uq 001100 ..... ... 110 01 01 ...... ..... @f0c_1 478 479fcnv_f_uw 001110 ..... ... 110 .......... ..... @f0e_ff_1 480fcnv_d_uw 001110 ..... ... 110 .......... ..... @f0e_df_1 481fcnv_f_uq 001110 ..... ... 110 .......... ..... @f0e_fd_1 482fcnv_d_uq 001110 ..... ... 110 .......... ..... @f0e_dd_1 483 484# float/int truncate 485fcnv_t_f_uw 001100 ..... ... 111 00 00 ...... ..... @f0c_1 486fcnv_t_d_uw 001100 ..... ... 111 00 01 ...... ..... @f0c_1 487fcnv_t_f_uq 001100 ..... ... 111 01 00 ...... ..... @f0c_1 488fcnv_t_d_uq 001100 ..... ... 111 01 01 ...... ..... @f0c_1 489 490fcnv_t_f_uw 001110 ..... ... 111 .......... ..... @f0e_ff_1 491fcnv_t_d_uw 001110 ..... ... 111 .......... ..... @f0e_df_1 492fcnv_t_f_uq 001110 ..... ... 111 .......... ..... @f0e_fd_1 493fcnv_t_d_uq 001110 ..... ... 111 .......... ..... @f0e_dd_1 494 495# Floating point class 2 496 497ftest 001100 00000 00000 y:3 00 10000 1 c:5 498 499fcmp_f 001100 ..... ..... ... 00 ..... 0 ..... @f0c_2 500fcmp_d 001100 ..... ..... ... 01 ..... 0 ..... @f0c_2 501 502fcmp_f 001110 ..... ..... ... ..... ... ..... @f0e_f_2 503fcmp_d 001110 ..... ..... ... ..... ... ..... @f0e_d_2 504 505# Floating point class 3 506 507fadd_f 001100 ..... ..... 000 00 ...... ..... @f0c_3 508fsub_f 001100 ..... ..... 001 00 ...... ..... @f0c_3 509fmpy_f 001100 ..... ..... 010 00 ...... ..... @f0c_3 510fdiv_f 001100 ..... ..... 011 00 ...... ..... @f0c_3 511 512fadd_d 001100 ..... ..... 000 01 ...... ..... @f0c_3 513fsub_d 001100 ..... ..... 001 01 ...... ..... @f0c_3 514fmpy_d 001100 ..... ..... 010 01 ...... ..... @f0c_3 515fdiv_d 001100 ..... ..... 011 01 ...... ..... @f0c_3 516 517fadd_f 001110 ..... ..... 000 ..... ... ..... @f0e_f_3 518fsub_f 001110 ..... ..... 001 ..... ... ..... @f0e_f_3 519fmpy_f 001110 ..... ..... 010 ..... ... ..... @f0e_f_3 520fdiv_f 001110 ..... ..... 011 ..... ... ..... @f0e_f_3 521 522fadd_d 001110 ..... ..... 000 ..... ... ..... @f0e_d_3 523fsub_d 001110 ..... ..... 001 ..... ... ..... @f0e_d_3 524fmpy_d 001110 ..... ..... 010 ..... ... ..... @f0e_d_3 525fdiv_d 001110 ..... ..... 011 ..... ... ..... @f0e_d_3 526 527xmpyu 001110 ..... ..... 010 .0111 .00 t:5 r1=%ra64 r2=%rb64 528