1# 2# HPPA instruction decode definitions. 3# 4# Copyright (c) 2018 Richard Henderson <rth@twiddle.net> 5# 6# This library is free software; you can redistribute it and/or 7# modify it under the terms of the GNU Lesser General Public 8# License as published by the Free Software Foundation; either 9# version 2.1 of the License, or (at your option) any later version. 10# 11# This library is distributed in the hope that it will be useful, 12# but WITHOUT ANY WARRANTY; without even the implied warranty of 13# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14# Lesser General Public License for more details. 15# 16# You should have received a copy of the GNU Lesser General Public 17# License along with this library; if not, see <http://www.gnu.org/licenses/>. 18# 19 20#### 21# Field definitions 22#### 23 24%assemble_sr3 13:1 14:2 25%assemble_sr3x 13:1 14:2 !function=expand_sr3x 26 27%assemble_11a 4:12 0:1 !function=expand_11a 28%assemble_12 0:s1 2:1 3:10 !function=expand_shl2 29%assemble_12a 3:13 0:1 !function=expand_12a 30%assemble_16 0:16 !function=expand_16 31%assemble_17 0:s1 16:5 2:1 3:10 !function=expand_shl2 32%assemble_22 0:s1 16:10 2:1 3:10 !function=expand_shl2 33%assemble_sp 14:2 !function=sp0_if_wide 34 35%assemble_21 0:s1 1:11 14:2 16:5 12:2 !function=expand_shl11 36 37%lowsign_11 0:s1 1:10 38 39%sm_imm 16:10 !function=expand_sm_imm 40 41%rm64 1:1 16:5 42%rt64 6:1 0:5 43%ra64 7:1 21:5 44%rb64 12:1 16:5 45%rc64 8:1 13:3 9:2 46%rc32 13:3 9:2 47 48%im5_0 0:s1 1:4 49%im5_16 16:s1 17:4 50%len5 0:5 !function=assemble_6 51%len6_8 8:1 0:5 !function=assemble_6 52%len6_12 12:1 0:5 !function=assemble_6 53%cpos6_11 11:1 5:5 54%ma_to_m 5:1 13:1 !function=ma_to_m 55%ma2_to_m 2:2 !function=ma_to_m 56%pos_to_m 0:1 !function=pos_to_m 57%neg_to_m 0:1 !function=neg_to_m 58%a_to_m 2:1 !function=neg_to_m 59%cmpbid_c 13:2 !function=cmpbid_c 60%d_5 5:1 !function=pa20_d 61%d_11 11:1 !function=pa20_d 62%d_13 13:1 !function=pa20_d 63 64#### 65# Argument set definitions 66#### 67 68&empty 69 70# All insns that need to form a virtual address should use this set. 71&ldst t b x disp sp m scale size 72 73&rr_cf_d t r cf d 74&rrr t r1 r2 75&rrr_cf t r1 r2 cf 76&rrr_cf_d t r1 r2 cf d 77&rrr_sh t r1 r2 sh 78&rrr_cf_d_sh t r1 r2 cf d sh 79&rri t r i 80&rri_cf t r i cf 81&rri_cf_d t r i cf d 82 83&rrb_c_f disp n c f r1 r2 84&rrb_c_d_f disp n c d f r1 r2 85&rib_c_f disp n c f r i 86&rib_c_d_f disp n c d f r i 87 88#### 89# Format definitions 90#### 91 92@rr_cf_d ...... r:5 ..... cf:4 ...... . t:5 &rr_cf_d d=%d_5 93@rrr ...... r2:5 r1:5 .... ....... t:5 &rrr 94@rrr_cf ...... r2:5 r1:5 cf:4 ....... t:5 &rrr_cf 95@rrr_cf_d ...... r2:5 r1:5 cf:4 ...... . t:5 &rrr_cf_d d=%d_5 96@rrr_sh ...... r2:5 r1:5 ........ sh:2 . t:5 &rrr_sh 97@rrr_cf_d_sh ...... r2:5 r1:5 cf:4 .... sh:2 . t:5 &rrr_cf_d_sh d=%d_5 98@rrr_cf_d_sh0 ...... r2:5 r1:5 cf:4 ...... . t:5 &rrr_cf_d_sh d=%d_5 sh=0 99@rri_cf ...... r:5 t:5 cf:4 . ........... &rri_cf i=%lowsign_11 100@rri_cf_d ...... r:5 t:5 cf:4 . ........... \ 101 &rri_cf_d d=%d_11 i=%lowsign_11 102 103@rrb_cf ...... r2:5 r1:5 c:3 ........... n:1 . \ 104 &rrb_c_f disp=%assemble_12 105@rrb_cdf ...... r2:5 r1:5 c:3 ........... n:1 . \ 106 &rrb_c_d_f disp=%assemble_12 107@rib_cf ...... r:5 ..... c:3 ........... n:1 . \ 108 &rib_c_f disp=%assemble_12 i=%im5_16 109@rib_cdf ...... r:5 ..... c:3 ........... n:1 . \ 110 &rib_c_d_f disp=%assemble_12 i=%im5_16 111 112#### 113# System 114#### 115 116break 000000 ----- ----- --- 00000000 ----- 117 118mtsp 000000 ----- r:5 ... 11000001 00000 sp=%assemble_sr3 119mtctl 000000 t:5 r:5 --- 11000010 00000 120mtsarcm 000000 01011 r:5 --- 11000110 00000 121mtsm 000000 00000 r:5 000 11000011 00000 122 123mfia 000000 ----- 00000 --- 10100101 t:5 124mfsp 000000 ----- 00000 ... 00100101 t:5 sp=%assemble_sr3 125mfctl 000000 r:5 00000- e:1 -01000101 t:5 126 127sync 000000 ----- ----- 000 00100000 00000 # sync, syncdma 128 129ldsid 000000 b:5 ----- sp:2 0 10000101 t:5 130 131rsm 000000 .......... 000 01110011 t:5 i=%sm_imm 132ssm 000000 .......... 000 01101011 t:5 i=%sm_imm 133 134rfi 000000 ----- ----- --- 01100000 00000 135rfi_r 000000 ----- ----- --- 01100101 00000 136 137# These are artificial instructions used by QEMU firmware. 138# They are allocated from the unassigned instruction space. 139halt 1111 1111 1111 1101 1110 1010 1101 0000 140reset 1111 1111 1111 1101 1110 1010 1101 0001 141getshadowregs 1111 1111 1111 1101 1110 1010 1101 0010 142 143#### 144# Memory Management 145#### 146 147@addrx ...... b:5 x:5 .. ........ m:1 ..... \ 148 &ldst disp=0 scale=0 t=0 sp=0 size=0 149 150nop 000001 ----- ----- -- 11001010 0 ----- # fdc, disp 151nop_addrx 000001 ..... ..... -- 01001010 . ----- @addrx # fdc, index 152nop_addrx 000001 ..... ..... -- 01001011 . ----- @addrx # fdce 153fic 000001 ..... ..... --- 0001010 . ----- @addrx # fic 0x0a 154fic 000001 ..... ..... -- 01001111 . 00000 @addrx # fic 0x4f 155fic 000001 ..... ..... --- 0001011 . ----- @addrx # fice 156nop_addrx 000001 ..... ..... -- 01001110 . 00000 @addrx # pdc 157 158probe 000001 b:5 ri:5 sp:2 imm:1 100011 write:1 0 t:5 159 160# pa1.x tlb insert instructions 161ixtlbx 000001 b:5 r:5 sp:2 0100000 addr:1 0 00000 data=1 162ixtlbx 000001 b:5 r:5 ... 000000 addr:1 0 00000 \ 163 sp=%assemble_sr3x data=0 164 165# pcxl and pcxl2 Fast TLB Insert instructions 166ixtlbxf 000001 00000 r:5 00 0 data:1 01000 addr:1 0 00000 167 168# pa2.0 tlb insert idtlbt and iitlbt instructions 169ixtlbt 000001 r2:5 r1:5 000 data:1 100000 0 00000 # idtlbt 170 171# pdtlb, pitlb 172pxtlb 000001 b:5 x:5 sp:2 01001000 m:1 ----- \ 173 &ldst disp=0 scale=0 size=0 t=0 174pxtlb 000001 b:5 x:5 ... 0001000 m:1 ----- \ 175 &ldst disp=0 scale=0 size=0 t=0 sp=%assemble_sr3x 176 177# ... pa20 local 178pxtlb_l 000001 b:5 x:5 sp:2 01011000 m:1 ----- \ 179 &ldst disp=0 scale=0 size=0 t=0 180pxtlb_l 000001 b:5 x:5 ... 0011000 m:1 ----- \ 181 &ldst disp=0 scale=0 size=0 t=0 sp=%assemble_sr3x 182 183# pdtlbe, pitlbe 184pxtlbe 000001 b:5 x:5 sp:2 01001001 m:1 ----- \ 185 &ldst disp=0 scale=0 size=0 t=0 186pxtlbe 000001 b:5 x:5 ... 0001001 m:1 ----- \ 187 &ldst disp=0 scale=0 size=0 t=0 sp=%assemble_sr3x 188 189lpa 000001 b:5 x:5 sp:2 01001101 m:1 t:5 \ 190 &ldst disp=0 scale=0 size=0 191 192lci 000001 ----- ----- -- 01001100 0 t:5 193 194#### 195# Arith/Log 196#### 197 198andcm 000010 ..... ..... .... 000000 . ..... @rrr_cf_d 199and 000010 ..... ..... .... 001000 . ..... @rrr_cf_d 200or 000010 ..... ..... .... 001001 . ..... @rrr_cf_d 201xor 000010 ..... ..... .... 001010 . ..... @rrr_cf_d 202uxor 000010 ..... ..... .... 001110 . ..... @rrr_cf_d 203ds 000010 ..... ..... .... 010001 0 ..... @rrr_cf 204cmpclr 000010 ..... ..... .... 100010 . ..... @rrr_cf_d 205uaddcm 000010 ..... ..... .... 100110 . ..... @rrr_cf_d 206uaddcm_tc 000010 ..... ..... .... 100111 . ..... @rrr_cf_d 207dcor 000010 ..... 00000 .... 101110 . ..... @rr_cf_d 208dcor_i 000010 ..... 00000 .... 101111 . ..... @rr_cf_d 209 210add 000010 ..... ..... .... 0110.. . ..... @rrr_cf_d_sh 211add_l 000010 ..... ..... .... 1010.. . ..... @rrr_cf_d_sh 212add_tsv 000010 ..... ..... .... 1110.. . ..... @rrr_cf_d_sh 213{ 214 add_c 000010 ..... ..... .... 011100 . ..... @rrr_cf_d_sh0 215 hshladd 000010 ..... ..... 0000 0111.. 0 ..... @rrr_sh 216} 217add_c_tsv 000010 ..... ..... .... 111100 . ..... @rrr_cf_d_sh0 218 219sub 000010 ..... ..... .... 010000 . ..... @rrr_cf_d 220sub_tsv 000010 ..... ..... .... 110000 . ..... @rrr_cf_d 221sub_tc 000010 ..... ..... .... 010011 . ..... @rrr_cf_d 222sub_tsv_tc 000010 ..... ..... .... 110011 . ..... @rrr_cf_d 223{ 224 sub_b 000010 ..... ..... .... 010100 . ..... @rrr_cf_d 225 hshradd 000010 ..... ..... 0000 0101.. 0 ..... @rrr_sh 226} 227sub_b_tsv 000010 ..... ..... .... 110100 . ..... @rrr_cf_d 228 229ldil 001000 t:5 ..................... i=%assemble_21 230addil 001010 r:5 ..................... i=%assemble_21 231ldo 001101 b:5 t:5 ................ i=%assemble_16 232 233addi 101101 ..... ..... .... 0 ........... @rri_cf 234addi_tsv 101101 ..... ..... .... 1 ........... @rri_cf 235addi_tc 101100 ..... ..... .... 0 ........... @rri_cf 236addi_tc_tsv 101100 ..... ..... .... 1 ........... @rri_cf 237 238subi 100101 ..... ..... .... 0 ........... @rri_cf 239subi_tsv 100101 ..... ..... .... 1 ........... @rri_cf 240 241cmpiclr 100100 ..... ..... .... . ........... @rri_cf_d 242 243hadd 000010 ..... ..... 00000011 11 0 ..... @rrr 244hadd_ss 000010 ..... ..... 00000011 01 0 ..... @rrr 245hadd_us 000010 ..... ..... 00000011 00 0 ..... @rrr 246 247havg 000010 ..... ..... 00000010 11 0 ..... @rrr 248 249hshl 111110 00000 r:5 100010 i:4 0 t:5 &rri 250hshr_s 111110 r:5 00000 110011 i:4 0 t:5 &rri 251hshr_u 111110 r:5 00000 110010 i:4 0 t:5 &rri 252 253hsub 000010 ..... ..... 00000001 11 0 ..... @rrr 254hsub_ss 000010 ..... ..... 00000001 01 0 ..... @rrr 255hsub_us 000010 ..... ..... 00000001 00 0 ..... @rrr 256 257mixh_l 111110 ..... ..... 1 00 00100000 ..... @rrr 258mixh_r 111110 ..... ..... 1 10 00100000 ..... @rrr 259mixw_l 111110 ..... ..... 1 00 00000000 ..... @rrr 260mixw_r 111110 ..... ..... 1 10 00000000 ..... @rrr 261 262permh 111110 r1:5 r2:5 0 c0:2 0 c1:2 c2:2 c3:2 0 t:5 263 264#### 265# Index Mem 266#### 267 268@ldstx ...... b:5 x:5 sp:2 scale:1 ....... m:1 t:5 &ldst disp=0 269@ldim5 ...... b:5 ..... sp:2 ......... t:5 \ 270 &ldst disp=%im5_16 x=0 scale=0 m=%ma_to_m 271@stim5 ...... b:5 t:5 sp:2 ......... ..... \ 272 &ldst disp=%im5_0 x=0 scale=0 m=%ma_to_m 273 274ld 000011 ..... ..... .. . 1 -- 00 size:2 ...... @ldim5 275ld 000011 ..... ..... .. . 0 -- 00 size:2 ...... @ldstx 276st 000011 ..... ..... .. . 1 -- 10 size:2 ...... @stim5 277ldc 000011 ..... ..... .. . 1 -- 0111 ...... @ldim5 size=2 278ldc 000011 ..... ..... .. . 0 -- 0111 ...... @ldstx size=2 279ldc 000011 ..... ..... .. . 1 -- 0101 ...... @ldim5 size=3 280ldc 000011 ..... ..... .. . 0 -- 0101 ...... @ldstx size=3 281lda 000011 ..... ..... .. . 1 -- 0110 ...... @ldim5 size=2 282lda 000011 ..... ..... .. . 0 -- 0110 ...... @ldstx size=2 283lda 000011 ..... ..... .. . 1 -- 0100 ...... @ldim5 size=3 284lda 000011 ..... ..... .. . 0 -- 0100 ...... @ldstx size=3 285sta 000011 ..... ..... .. . 1 -- 1110 ...... @stim5 size=2 286sta 000011 ..... ..... .. . 1 -- 1111 ...... @stim5 size=3 287stby 000011 b:5 r:5 sp:2 a:1 1 -- 1100 m:1 ..... disp=%im5_0 288stdby 000011 b:5 r:5 sp:2 a:1 1 -- 1101 m:1 ..... disp=%im5_0 289 290@fldstwx ...... b:5 x:5 sp:2 scale:1 ....... m:1 ..... \ 291 &ldst t=%rt64 disp=0 size=2 292@fldstwi ...... b:5 ..... sp:2 . ....... . ..... \ 293 &ldst t=%rt64 disp=%im5_16 m=%ma_to_m x=0 scale=0 size=2 294 295fldw 001001 ..... ..... .. . 0 -- 000 . . ..... @fldstwx 296fldw 001001 ..... ..... .. . 1 -- 000 . . ..... @fldstwi 297fstw 001001 ..... ..... .. . 0 -- 100 . . ..... @fldstwx 298fstw 001001 ..... ..... .. . 1 -- 100 . . ..... @fldstwi 299 300@fldstdx ...... b:5 x:5 sp:2 scale:1 ....... m:1 t:5 \ 301 &ldst disp=0 size=3 302@fldstdi ...... b:5 ..... sp:2 . ....... . t:5 \ 303 &ldst disp=%im5_16 m=%ma_to_m x=0 scale=0 size=3 304 305fldd 001011 ..... ..... .. . 0 -- 000 0 . ..... @fldstdx 306fldd 001011 ..... ..... .. . 1 -- 000 0 . ..... @fldstdi 307fstd 001011 ..... ..... .. . 0 -- 100 0 . ..... @fldstdx 308fstd 001011 ..... ..... .. . 1 -- 100 0 . ..... @fldstdi 309 310#### 311# Offset Mem 312#### 313 314@ldstim11 ...... b:5 t:5 ................ \ 315 &ldst sp=%assemble_sp disp=%assemble_11a \ 316 m=%ma2_to_m x=0 scale=0 size=3 317@ldstim14 ...... b:5 t:5 ................ \ 318 &ldst sp=%assemble_sp disp=%assemble_16 \ 319 x=0 scale=0 m=0 320@ldstim14m ...... b:5 t:5 ................ \ 321 &ldst sp=%assemble_sp disp=%assemble_16 \ 322 x=0 scale=0 m=%neg_to_m 323@ldstim12m ...... b:5 t:5 ................ \ 324 &ldst sp=%assemble_sp disp=%assemble_12a \ 325 x=0 scale=0 m=%pos_to_m 326 327# LDB, LDH, LDW, LDWM 328ld 010000 ..... ..... .. .............. @ldstim14 size=0 329ld 010001 ..... ..... .. .............. @ldstim14 size=1 330ld 010010 ..... ..... .. .............. @ldstim14 size=2 331ld 010011 ..... ..... .. .............. @ldstim14m size=2 332ld 010111 ..... ..... .. ...........10. @ldstim12m size=2 333 334# STB, STH, STW, STWM 335st 011000 ..... ..... .. .............. @ldstim14 size=0 336st 011001 ..... ..... .. .............. @ldstim14 size=1 337st 011010 ..... ..... .. .............. @ldstim14 size=2 338st 011011 ..... ..... .. .............. @ldstim14m size=2 339st 011111 ..... ..... .. ...........10. @ldstim12m size=2 340 341fldw 010110 b:5 ..... ................ \ 342 &ldst disp=%assemble_12a sp=%assemble_sp \ 343 t=%rm64 m=%a_to_m x=0 scale=0 size=2 344fldw 010111 b:5 ..... .............0.. \ 345 &ldst disp=%assemble_12a sp=%assemble_sp \ 346 t=%rm64 m=0 x=0 scale=0 size=2 347 348fstw 011110 b:5 ..... ................ \ 349 &ldst disp=%assemble_12a sp=%assemble_sp \ 350 t=%rm64 m=%a_to_m x=0 scale=0 size=2 351fstw 011111 b:5 ..... .............0.. \ 352 &ldst disp=%assemble_12a sp=%assemble_sp \ 353 t=%rm64 m=0 x=0 scale=0 size=2 354 355ld 010100 ..... ..... .. ............0. @ldstim11 356fldd 010100 ..... ..... .. ............1. @ldstim11 357 358st 011100 ..... ..... .. ............0. @ldstim11 359fstd 011100 ..... ..... .. ............1. @ldstim11 360 361#### 362# Floating-point Multiply Add 363#### 364 365&mpyadd rm1 rm2 ta ra tm 366@mpyadd ...... rm1:5 rm2:5 ta:5 ra:5 . tm:5 &mpyadd 367 368fmpyadd_f 000110 ..... ..... ..... ..... 0 ..... @mpyadd 369fmpyadd_d 000110 ..... ..... ..... ..... 1 ..... @mpyadd 370fmpysub_f 100110 ..... ..... ..... ..... 0 ..... @mpyadd 371fmpysub_d 100110 ..... ..... ..... ..... 1 ..... @mpyadd 372 373#### 374# Conditional Branches 375#### 376 377bb_sar 110000 00000 r:5 c:1 1 . ........... n:1 . \ 378 disp=%assemble_12 d=%d_13 379bb_imm 110001 p:5 r:5 c:1 1 . ........... n:1 . \ 380 disp=%assemble_12 d=%d_13 381 382movb 110010 ..... ..... ... ........... . . @rrb_cf f=0 383movbi 110011 ..... ..... ... ........... . . @rib_cf f=0 384 385cmpb 100000 ..... ..... ... ........... . . @rrb_cdf d=0 f=0 386cmpb 100010 ..... ..... ... ........... . . @rrb_cdf d=0 f=1 387cmpb 100111 ..... ..... ... ........... . . @rrb_cdf d=1 f=0 388cmpb 101111 ..... ..... ... ........... . . @rrb_cdf d=1 f=1 389cmpbi 100001 ..... ..... ... ........... . . @rib_cdf d=0 f=0 390cmpbi 100011 ..... ..... ... ........... . . @rib_cdf d=0 f=1 391cmpbi 111011 r:5 ..... f:1 .. ........... n:1 . \ 392 &rib_c_d_f d=1 disp=%assemble_12 c=%cmpbid_c i=%im5_16 393 394addb 101000 ..... ..... ... ........... . . @rrb_cf f=0 395addb 101010 ..... ..... ... ........... . . @rrb_cf f=1 396addbi 101001 ..... ..... ... ........... . . @rib_cf f=0 397addbi 101011 ..... ..... ... ........... . . @rib_cf f=1 398 399#### 400# Shift, Extract, Deposit 401#### 402 403shrp_sar 110100 r2:5 r1:5 c:3 00 0 d:1 0000 t:5 404shrp_imm 110100 r2:5 r1:5 c:3 01 0 cpos:5 t:5 d=0 405shrp_imm 110100 r2:5 r1:5 c:3 0. 1 ..... t:5 \ 406 d=1 cpos=%cpos6_11 407 408extr_sar 110100 r:5 t:5 c:3 10 se:1 00 000 ..... d=0 len=%len5 409extr_sar 110100 r:5 t:5 c:3 10 se:1 1. 000 ..... d=1 len=%len6_8 410extr_imm 110100 r:5 t:5 c:3 11 se:1 pos:5 ..... d=0 len=%len5 411extr_imm 110110 r:5 t:5 c:3 .. se:1 ..... ..... \ 412 d=1 len=%len6_12 pos=%cpos6_11 413 414dep_sar 110101 t:5 r:5 c:3 00 nz:1 00 000 ..... d=0 len=%len5 415dep_sar 110101 t:5 r:5 c:3 00 nz:1 1. 000 ..... d=1 len=%len6_8 416dep_imm 110101 t:5 r:5 c:3 01 nz:1 cpos:5 ..... d=0 len=%len5 417dep_imm 111100 t:5 r:5 c:3 .. nz:1 ..... ..... \ 418 d=1 len=%len6_12 cpos=%cpos6_11 419depi_sar 110101 t:5 ..... c:3 10 nz:1 d:1 . 000 ..... \ 420 i=%im5_16 len=%len6_8 421depi_imm 110101 t:5 ..... c:3 11 nz:1 cpos:5 ..... \ 422 d=0 i=%im5_16 len=%len5 423depi_imm 111101 t:5 ..... c:3 .. nz:1 ..... ..... \ 424 d=1 i=%im5_16 len=%len6_12 cpos=%cpos6_11 425 426#### 427# Branch External 428#### 429 430&BE b l n disp sp 431@be ...... b:5 ..... ... ........... n:1 . \ 432 &BE disp=%assemble_17 sp=%assemble_sr3 433 434be 111000 ..... ..... ... ........... . . @be l=0 435be 111001 ..... ..... ... ........... . . @be l=31 436 437#### 438# Branch 439#### 440 441&BL l n disp 442@bl ...... l:5 ..... ... ........... n:1 . &BL disp=%assemble_17 443 444# B,L and B,L,PUSH 445bl 111010 ..... ..... 000 ........... . . @bl 446bl 111010 ..... ..... 100 ........... . . @bl 447# B,L (long displacement) 448bl 111010 ..... ..... 101 ........... n:1 . &BL l=2 \ 449 disp=%assemble_22 450b_gate 111010 ..... ..... 001 ........... . . @bl 451blr 111010 l:5 x:5 010 00000000000 n:1 0 452nopbts 111010 00000 00000 010 0---------1 0 1 # clrbts/popbts 453nopbts 111010 00000 ----- 010 00000000000 0 1 # pushbts/pushnom 454bv 111010 b:5 x:5 110 00000000000 n:1 0 455bve 111010 b:5 00000 110 10000000000 n:1 - l=0 456bve 111010 b:5 00000 111 10000000000 n:1 - l=2 457 458#### 459# FP Fused Multiple-Add 460#### 461 462fmpyfadd_f 101110 ..... ..... ... . 0 ... . . neg:1 ..... \ 463 rm1=%ra64 rm2=%rb64 ra3=%rc64 t=%rt64 464fmpyfadd_d 101110 rm1:5 rm2:5 ... 0 1 ..0 0 0 neg:1 t:5 ra3=%rc32 465 466#### 467# FP operations 468#### 469 470&fclass01 r t 471&fclass2 r1 r2 c y 472&fclass3 r1 r2 t 473 474@f0c_0 ...... r:5 00000 ..... 00 000 0 t:5 &fclass01 475@f0c_1 ...... r:5 000.. ..... 01 000 0 t:5 &fclass01 476@f0c_2 ...... r1:5 r2:5 y:3 .. 10 000 . c:5 &fclass2 477@f0c_3 ...... r1:5 r2:5 ..... 11 000 0 t:5 &fclass3 478 479@f0e_f_0 ...... ..... 00000 ... 0 0 000 .. 0 ..... \ 480 &fclass01 r=%ra64 t=%rt64 481@f0e_d_0 ...... r:5 00000 ... 0 1 000 00 0 t:5 &fclass01 482 483@f0e_ff_1 ...... ..... 000 ... 0000 010 .. 0 ..... \ 484 &fclass01 r=%ra64 t=%rt64 485@f0e_fd_1 ...... ..... 000 ... 0100 010 .0 0 t:5 &fclass01 r=%ra64 486@f0e_df_1 ...... r:5 000 ... 0001 010 0. 0 ..... &fclass01 t=%rt64 487@f0e_dd_1 ...... r:5 000 ... 0101 010 00 0 t:5 &fclass01 488 489@f0e_f_2 ...... ..... ..... y:3 .0 100 .00 c:5 \ 490 &fclass2 r1=%ra64 r2=%rb64 491@f0e_d_2 ...... r1:5 r2:5 y:3 01 100 000 c:5 &fclass2 492 493@f0e_f_3 ...... ..... ..... ... .0 110 ..0 ..... \ 494 &fclass3 r1=%ra64 r2=%rb64 t=%rt64 495@f0e_d_3 ...... r1:5 r2:5 ... 01 110 000 t:5 &fclass3 496 497# Floating point class 0 498 499fid_f 001100 00000 00000 000 00 000000 00000 500 501fcpy_f 001100 ..... ..... 010 00 ...... ..... @f0c_0 502fabs_f 001100 ..... ..... 011 00 ...... ..... @f0c_0 503fsqrt_f 001100 ..... ..... 100 00 ...... ..... @f0c_0 504frnd_f 001100 ..... ..... 101 00 ...... ..... @f0c_0 505fneg_f 001100 ..... ..... 110 00 ...... ..... @f0c_0 506fnegabs_f 001100 ..... ..... 111 00 ...... ..... @f0c_0 507 508fcpy_d 001100 ..... ..... 010 01 ...... ..... @f0c_0 509fabs_d 001100 ..... ..... 011 01 ...... ..... @f0c_0 510fsqrt_d 001100 ..... ..... 100 01 ...... ..... @f0c_0 511frnd_d 001100 ..... ..... 101 01 ...... ..... @f0c_0 512fneg_d 001100 ..... ..... 110 01 ...... ..... @f0c_0 513fnegabs_d 001100 ..... ..... 111 01 ...... ..... @f0c_0 514 515fcpy_f 001110 ..... ..... 010 ........ ..... @f0e_f_0 516fabs_f 001110 ..... ..... 011 ........ ..... @f0e_f_0 517fsqrt_f 001110 ..... ..... 100 ........ ..... @f0e_f_0 518frnd_f 001110 ..... ..... 101 ........ ..... @f0e_f_0 519fneg_f 001110 ..... ..... 110 ........ ..... @f0e_f_0 520fnegabs_f 001110 ..... ..... 111 ........ ..... @f0e_f_0 521 522fcpy_d 001110 ..... ..... 010 ........ ..... @f0e_d_0 523fabs_d 001110 ..... ..... 011 ........ ..... @f0e_d_0 524fsqrt_d 001110 ..... ..... 100 ........ ..... @f0e_d_0 525frnd_d 001110 ..... ..... 101 ........ ..... @f0e_d_0 526fneg_d 001110 ..... ..... 110 ........ ..... @f0e_d_0 527fnegabs_d 001110 ..... ..... 111 ........ ..... @f0e_d_0 528 529# Floating point class 1 530 531# float/float 532fcnv_d_f 001100 ..... ... 000 00 01 ...... ..... @f0c_1 533fcnv_f_d 001100 ..... ... 000 01 00 ...... ..... @f0c_1 534 535fcnv_d_f 001110 ..... ... 000 .......... ..... @f0e_df_1 536fcnv_f_d 001110 ..... ... 000 .......... ..... @f0e_fd_1 537 538# int/float 539fcnv_w_f 001100 ..... ... 001 00 00 ...... ..... @f0c_1 540fcnv_q_f 001100 ..... ... 001 00 01 ...... ..... @f0c_1 541fcnv_w_d 001100 ..... ... 001 01 00 ...... ..... @f0c_1 542fcnv_q_d 001100 ..... ... 001 01 01 ...... ..... @f0c_1 543 544fcnv_w_f 001110 ..... ... 001 .......... ..... @f0e_ff_1 545fcnv_q_f 001110 ..... ... 001 .......... ..... @f0e_df_1 546fcnv_w_d 001110 ..... ... 001 .......... ..... @f0e_fd_1 547fcnv_q_d 001110 ..... ... 001 .......... ..... @f0e_dd_1 548 549# float/int 550fcnv_f_w 001100 ..... ... 010 00 00 ...... ..... @f0c_1 551fcnv_d_w 001100 ..... ... 010 00 01 ...... ..... @f0c_1 552fcnv_f_q 001100 ..... ... 010 01 00 ...... ..... @f0c_1 553fcnv_d_q 001100 ..... ... 010 01 01 ...... ..... @f0c_1 554 555fcnv_f_w 001110 ..... ... 010 .......... ..... @f0e_ff_1 556fcnv_d_w 001110 ..... ... 010 .......... ..... @f0e_df_1 557fcnv_f_q 001110 ..... ... 010 .......... ..... @f0e_fd_1 558fcnv_d_q 001110 ..... ... 010 .......... ..... @f0e_dd_1 559 560# float/int truncate 561fcnv_t_f_w 001100 ..... ... 011 00 00 ...... ..... @f0c_1 562fcnv_t_d_w 001100 ..... ... 011 00 01 ...... ..... @f0c_1 563fcnv_t_f_q 001100 ..... ... 011 01 00 ...... ..... @f0c_1 564fcnv_t_d_q 001100 ..... ... 011 01 01 ...... ..... @f0c_1 565 566fcnv_t_f_w 001110 ..... ... 011 .......... ..... @f0e_ff_1 567fcnv_t_d_w 001110 ..... ... 011 .......... ..... @f0e_df_1 568fcnv_t_f_q 001110 ..... ... 011 .......... ..... @f0e_fd_1 569fcnv_t_d_q 001110 ..... ... 011 .......... ..... @f0e_dd_1 570 571# uint/float 572fcnv_uw_f 001100 ..... ... 101 00 00 ...... ..... @f0c_1 573fcnv_uq_f 001100 ..... ... 101 00 01 ...... ..... @f0c_1 574fcnv_uw_d 001100 ..... ... 101 01 00 ...... ..... @f0c_1 575fcnv_uq_d 001100 ..... ... 101 01 01 ...... ..... @f0c_1 576 577fcnv_uw_f 001110 ..... ... 101 .......... ..... @f0e_ff_1 578fcnv_uq_f 001110 ..... ... 101 .......... ..... @f0e_df_1 579fcnv_uw_d 001110 ..... ... 101 .......... ..... @f0e_fd_1 580fcnv_uq_d 001110 ..... ... 101 .......... ..... @f0e_dd_1 581 582# float/int 583fcnv_f_uw 001100 ..... ... 110 00 00 ...... ..... @f0c_1 584fcnv_d_uw 001100 ..... ... 110 00 01 ...... ..... @f0c_1 585fcnv_f_uq 001100 ..... ... 110 01 00 ...... ..... @f0c_1 586fcnv_d_uq 001100 ..... ... 110 01 01 ...... ..... @f0c_1 587 588fcnv_f_uw 001110 ..... ... 110 .......... ..... @f0e_ff_1 589fcnv_d_uw 001110 ..... ... 110 .......... ..... @f0e_df_1 590fcnv_f_uq 001110 ..... ... 110 .......... ..... @f0e_fd_1 591fcnv_d_uq 001110 ..... ... 110 .......... ..... @f0e_dd_1 592 593# float/int truncate 594fcnv_t_f_uw 001100 ..... ... 111 00 00 ...... ..... @f0c_1 595fcnv_t_d_uw 001100 ..... ... 111 00 01 ...... ..... @f0c_1 596fcnv_t_f_uq 001100 ..... ... 111 01 00 ...... ..... @f0c_1 597fcnv_t_d_uq 001100 ..... ... 111 01 01 ...... ..... @f0c_1 598 599fcnv_t_f_uw 001110 ..... ... 111 .......... ..... @f0e_ff_1 600fcnv_t_d_uw 001110 ..... ... 111 .......... ..... @f0e_df_1 601fcnv_t_f_uq 001110 ..... ... 111 .......... ..... @f0e_fd_1 602fcnv_t_d_uq 001110 ..... ... 111 .......... ..... @f0e_dd_1 603 604# Floating point class 2 605 606ftest 001100 00000 00000 y:3 00 10000 1 c:5 607 608fcmp_f 001100 ..... ..... ... 00 ..... 0 ..... @f0c_2 609fcmp_d 001100 ..... ..... ... 01 ..... 0 ..... @f0c_2 610 611fcmp_f 001110 ..... ..... ... ..... ... ..... @f0e_f_2 612fcmp_d 001110 ..... ..... ... ..... ... ..... @f0e_d_2 613 614# Floating point class 3 615 616fadd_f 001100 ..... ..... 000 00 ...... ..... @f0c_3 617fsub_f 001100 ..... ..... 001 00 ...... ..... @f0c_3 618fmpy_f 001100 ..... ..... 010 00 ...... ..... @f0c_3 619fdiv_f 001100 ..... ..... 011 00 ...... ..... @f0c_3 620 621fadd_d 001100 ..... ..... 000 01 ...... ..... @f0c_3 622fsub_d 001100 ..... ..... 001 01 ...... ..... @f0c_3 623fmpy_d 001100 ..... ..... 010 01 ...... ..... @f0c_3 624fdiv_d 001100 ..... ..... 011 01 ...... ..... @f0c_3 625 626fadd_f 001110 ..... ..... 000 ..... ... ..... @f0e_f_3 627fsub_f 001110 ..... ..... 001 ..... ... ..... @f0e_f_3 628fmpy_f 001110 ..... ..... 010 ..... ... ..... @f0e_f_3 629fdiv_f 001110 ..... ..... 011 ..... ... ..... @f0e_f_3 630 631fadd_d 001110 ..... ..... 000 ..... ... ..... @f0e_d_3 632fsub_d 001110 ..... ..... 001 ..... ... ..... @f0e_d_3 633fmpy_d 001110 ..... ..... 010 ..... ... ..... @f0e_d_3 634fdiv_d 001110 ..... ..... 011 ..... ... ..... @f0e_d_3 635 636xmpyu 001110 ..... ..... 010 .0111 .00 t:5 r1=%ra64 r2=%rb64 637 638# diag 639{ 640 [ 641 diag_btlb 000101 00 0000 0000 0000 0001 0000 0000 642 diag_cout 000101 00 0000 0000 0000 0001 0000 0001 643 644 # For 32-bit PA-7300LC (PCX-L2) 645 diag_getshadowregs_pa1 000101 00 0000 0000 0001 1010 0000 0000 646 diag_putshadowregs_pa1 000101 00 0000 0000 0001 1010 0100 0000 647 648 # For 64-bit PA8700 (PCX-W2) 649 diag_getshadowregs_pa2 000101 00 0111 1000 0001 1000 0100 0000 650 diag_putshadowregs_pa2 000101 00 0111 0000 0001 1000 0100 0000 651 ] 652 diag_unimp 000101 i:26 653} 654