1# 2# HPPA instruction decode definitions. 3# 4# Copyright (c) 2018 Richard Henderson <rth@twiddle.net> 5# 6# This library is free software; you can redistribute it and/or 7# modify it under the terms of the GNU Lesser General Public 8# License as published by the Free Software Foundation; either 9# version 2.1 of the License, or (at your option) any later version. 10# 11# This library is distributed in the hope that it will be useful, 12# but WITHOUT ANY WARRANTY; without even the implied warranty of 13# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14# Lesser General Public License for more details. 15# 16# You should have received a copy of the GNU Lesser General Public 17# License along with this library; if not, see <http://www.gnu.org/licenses/>. 18# 19 20#### 21# Field definitions 22#### 23 24%assemble_sr3 13:1 14:2 25%assemble_sr3x 13:1 14:2 !function=expand_sr3x 26 27%assemble_11a 4:12 0:1 !function=expand_11a 28%assemble_12 0:s1 2:1 3:10 !function=expand_shl2 29%assemble_12a 3:13 0:1 !function=expand_12a 30%assemble_16 0:16 !function=expand_16 31%assemble_17 0:s1 16:5 2:1 3:10 !function=expand_shl2 32%assemble_22 0:s1 16:10 2:1 3:10 !function=expand_shl2 33%assemble_sp 14:2 !function=sp0_if_wide 34 35%assemble_21 0:s1 1:11 14:2 16:5 12:2 !function=expand_shl11 36 37%lowsign_11 0:s1 1:10 38 39%sm_imm 16:10 !function=expand_sm_imm 40 41%rm64 1:1 16:5 42%rt64 6:1 0:5 43%ra64 7:1 21:5 44%rb64 12:1 16:5 45%rc64 8:1 13:3 9:2 46%rc32 13:3 9:2 47 48%im5_0 0:s1 1:4 49%im5_16 16:s1 17:4 50%len5 0:5 !function=assemble_6 51%len6_8 8:1 0:5 !function=assemble_6 52%len6_12 12:1 0:5 !function=assemble_6 53%cpos6_11 11:1 5:5 54%ma_to_m 5:1 13:1 !function=ma_to_m 55%ma2_to_m 2:2 !function=ma_to_m 56%pos_to_m 0:1 !function=pos_to_m 57%neg_to_m 0:1 !function=neg_to_m 58%a_to_m 2:1 !function=neg_to_m 59%cmpbid_c 13:2 !function=cmpbid_c 60 61#### 62# Argument set definitions 63#### 64 65# All insns that need to form a virtual address should use this set. 66&ldst t b x disp sp m scale size 67 68&rr_cf_d t r cf d 69&rrr t r1 r2 70&rrr_cf t r1 r2 cf 71&rrr_cf_d t r1 r2 cf d 72&rrr_sh t r1 r2 sh 73&rrr_cf_d_sh t r1 r2 cf d sh 74&rri t r i 75&rri_cf t r i cf 76&rri_cf_d t r i cf d 77 78&rrb_c_f disp n c f r1 r2 79&rrb_c_d_f disp n c d f r1 r2 80&rib_c_f disp n c f r i 81&rib_c_d_f disp n c d f r i 82 83#### 84# Format definitions 85#### 86 87@rr_cf_d ...... r:5 ..... cf:4 ...... d:1 t:5 &rr_cf_d 88@rrr ...... r2:5 r1:5 .... ....... t:5 &rrr 89@rrr_cf ...... r2:5 r1:5 cf:4 ....... t:5 &rrr_cf 90@rrr_cf_d ...... r2:5 r1:5 cf:4 ...... d:1 t:5 &rrr_cf_d 91@rrr_sh ...... r2:5 r1:5 ........ sh:2 . t:5 &rrr_sh 92@rrr_cf_d_sh ...... r2:5 r1:5 cf:4 .... sh:2 d:1 t:5 &rrr_cf_d_sh 93@rrr_cf_d_sh0 ...... r2:5 r1:5 cf:4 ...... d:1 t:5 &rrr_cf_d_sh sh=0 94@rri_cf ...... r:5 t:5 cf:4 . ........... &rri_cf i=%lowsign_11 95@rri_cf_d ...... r:5 t:5 cf:4 d:1 ........... &rri_cf_d i=%lowsign_11 96 97@rrb_cf ...... r2:5 r1:5 c:3 ........... n:1 . \ 98 &rrb_c_f disp=%assemble_12 99@rrb_cdf ...... r2:5 r1:5 c:3 ........... n:1 . \ 100 &rrb_c_d_f disp=%assemble_12 101@rib_cf ...... r:5 ..... c:3 ........... n:1 . \ 102 &rib_c_f disp=%assemble_12 i=%im5_16 103@rib_cdf ...... r:5 ..... c:3 ........... n:1 . \ 104 &rib_c_d_f disp=%assemble_12 i=%im5_16 105 106#### 107# System 108#### 109 110break 000000 ----- ----- --- 00000000 ----- 111 112mtsp 000000 ----- r:5 ... 11000001 00000 sp=%assemble_sr3 113mtctl 000000 t:5 r:5 --- 11000010 00000 114mtsarcm 000000 01011 r:5 --- 11000110 00000 115mtsm 000000 00000 r:5 000 11000011 00000 116 117mfia 000000 ----- 00000 --- 10100101 t:5 118mfsp 000000 ----- 00000 ... 00100101 t:5 sp=%assemble_sr3 119mfctl 000000 r:5 00000- e:1 -01000101 t:5 120 121sync 000000 ----- ----- 000 00100000 00000 # sync, syncdma 122 123ldsid 000000 b:5 ----- sp:2 0 10000101 t:5 124 125rsm 000000 .......... 000 01110011 t:5 i=%sm_imm 126ssm 000000 .......... 000 01101011 t:5 i=%sm_imm 127 128rfi 000000 ----- ----- --- 01100000 00000 129rfi_r 000000 ----- ----- --- 01100101 00000 130 131# These are artificial instructions used by QEMU firmware. 132# They are allocated from the unassigned instruction space. 133halt 1111 1111 1111 1101 1110 1010 1101 0000 134reset 1111 1111 1111 1101 1110 1010 1101 0001 135getshadowregs 1111 1111 1111 1101 1110 1010 1101 0010 136 137#### 138# Memory Management 139#### 140 141@addrx ...... b:5 x:5 .. ........ m:1 ..... \ 142 &ldst disp=0 scale=0 t=0 sp=0 size=0 143 144nop 000001 ----- ----- -- 11001010 0 ----- # fdc, disp 145nop_addrx 000001 ..... ..... -- 01001010 . ----- @addrx # fdc, index 146nop_addrx 000001 ..... ..... -- 01001011 . ----- @addrx # fdce 147fic 000001 ..... ..... --- 0001010 . ----- @addrx # fic 0x0a 148fic 000001 ..... ..... -- 01001111 . 00000 @addrx # fic 0x4f 149fic 000001 ..... ..... --- 0001011 . ----- @addrx # fice 150nop_addrx 000001 ..... ..... -- 01001110 . 00000 @addrx # pdc 151 152probe 000001 b:5 ri:5 sp:2 imm:1 100011 write:1 0 t:5 153 154# pa1.x tlb insert instructions 155ixtlbx 000001 b:5 r:5 sp:2 0100000 addr:1 0 00000 data=1 156ixtlbx 000001 b:5 r:5 ... 000000 addr:1 0 00000 \ 157 sp=%assemble_sr3x data=0 158 159# pcxl and pcxl2 Fast TLB Insert instructions 160ixtlbxf 000001 00000 r:5 00 0 data:1 01000 addr:1 0 00000 161 162# pa2.0 tlb insert idtlbt and iitlbt instructions 163ixtlbt 000001 r2:5 r1:5 000 data:1 100000 0 00000 # idtlbt 164 165# pdtlb, pitlb 166pxtlb 000001 b:5 x:5 sp:2 01001000 m:1 ----- \ 167 &ldst disp=0 scale=0 size=0 t=0 168pxtlb 000001 b:5 x:5 ... 0001000 m:1 ----- \ 169 &ldst disp=0 scale=0 size=0 t=0 sp=%assemble_sr3x 170 171# ... pa20 local 172pxtlb_l 000001 b:5 x:5 sp:2 01011000 m:1 ----- \ 173 &ldst disp=0 scale=0 size=0 t=0 174pxtlb_l 000001 b:5 x:5 ... 0011000 m:1 ----- \ 175 &ldst disp=0 scale=0 size=0 t=0 sp=%assemble_sr3x 176 177# pdtlbe, pitlbe 178pxtlbe 000001 b:5 x:5 sp:2 01001001 m:1 ----- \ 179 &ldst disp=0 scale=0 size=0 t=0 180pxtlbe 000001 b:5 x:5 ... 0001001 m:1 ----- \ 181 &ldst disp=0 scale=0 size=0 t=0 sp=%assemble_sr3x 182 183lpa 000001 b:5 x:5 sp:2 01001101 m:1 t:5 \ 184 &ldst disp=0 scale=0 size=0 185 186lci 000001 ----- ----- -- 01001100 0 t:5 187 188#### 189# Arith/Log 190#### 191 192andcm 000010 ..... ..... .... 000000 . ..... @rrr_cf_d 193and 000010 ..... ..... .... 001000 . ..... @rrr_cf_d 194or 000010 ..... ..... .... 001001 . ..... @rrr_cf_d 195xor 000010 ..... ..... .... 001010 . ..... @rrr_cf_d 196uxor 000010 ..... ..... .... 001110 . ..... @rrr_cf_d 197ds 000010 ..... ..... .... 010001 0 ..... @rrr_cf 198cmpclr 000010 ..... ..... .... 100010 . ..... @rrr_cf_d 199uaddcm 000010 ..... ..... .... 100110 . ..... @rrr_cf_d 200uaddcm_tc 000010 ..... ..... .... 100111 . ..... @rrr_cf_d 201dcor 000010 ..... 00000 .... 101110 . ..... @rr_cf_d 202dcor_i 000010 ..... 00000 .... 101111 . ..... @rr_cf_d 203 204add 000010 ..... ..... .... 0110.. . ..... @rrr_cf_d_sh 205add_l 000010 ..... ..... .... 1010.. . ..... @rrr_cf_d_sh 206add_tsv 000010 ..... ..... .... 1110.. . ..... @rrr_cf_d_sh 207{ 208 add_c 000010 ..... ..... .... 011100 . ..... @rrr_cf_d_sh0 209 hshladd 000010 ..... ..... 0000 0111.. 0 ..... @rrr_sh 210} 211add_c_tsv 000010 ..... ..... .... 111100 . ..... @rrr_cf_d_sh0 212 213sub 000010 ..... ..... .... 010000 . ..... @rrr_cf_d 214sub_tsv 000010 ..... ..... .... 110000 . ..... @rrr_cf_d 215sub_tc 000010 ..... ..... .... 010011 . ..... @rrr_cf_d 216sub_tsv_tc 000010 ..... ..... .... 110011 . ..... @rrr_cf_d 217{ 218 sub_b 000010 ..... ..... .... 010100 . ..... @rrr_cf_d 219 hshradd 000010 ..... ..... 0000 0101.. 0 ..... @rrr_sh 220} 221sub_b_tsv 000010 ..... ..... .... 110100 . ..... @rrr_cf_d 222 223ldil 001000 t:5 ..................... i=%assemble_21 224addil 001010 r:5 ..................... i=%assemble_21 225ldo 001101 b:5 t:5 ................ i=%assemble_16 226 227addi 101101 ..... ..... .... 0 ........... @rri_cf 228addi_tsv 101101 ..... ..... .... 1 ........... @rri_cf 229addi_tc 101100 ..... ..... .... 0 ........... @rri_cf 230addi_tc_tsv 101100 ..... ..... .... 1 ........... @rri_cf 231 232subi 100101 ..... ..... .... 0 ........... @rri_cf 233subi_tsv 100101 ..... ..... .... 1 ........... @rri_cf 234 235cmpiclr 100100 ..... ..... .... . ........... @rri_cf_d 236 237hadd 000010 ..... ..... 00000011 11 0 ..... @rrr 238hadd_ss 000010 ..... ..... 00000011 01 0 ..... @rrr 239hadd_us 000010 ..... ..... 00000011 00 0 ..... @rrr 240 241havg 000010 ..... ..... 00000010 11 0 ..... @rrr 242 243hshl 111110 00000 r:5 100010 i:4 0 t:5 &rri 244hshr_s 111110 r:5 00000 110011 i:4 0 t:5 &rri 245hshr_u 111110 r:5 00000 110010 i:4 0 t:5 &rri 246 247hsub 000010 ..... ..... 00000001 11 0 ..... @rrr 248hsub_ss 000010 ..... ..... 00000001 01 0 ..... @rrr 249hsub_us 000010 ..... ..... 00000001 00 0 ..... @rrr 250 251mixh_l 111110 ..... ..... 1 00 00100000 ..... @rrr 252mixh_r 111110 ..... ..... 1 10 00100000 ..... @rrr 253mixw_l 111110 ..... ..... 1 00 00000000 ..... @rrr 254mixw_r 111110 ..... ..... 1 10 00000000 ..... @rrr 255 256permh 111110 r1:5 r2:5 0 c0:2 0 c1:2 c2:2 c3:2 0 t:5 257 258#### 259# Index Mem 260#### 261 262@ldstx ...... b:5 x:5 sp:2 scale:1 ....... m:1 t:5 &ldst disp=0 263@ldim5 ...... b:5 ..... sp:2 ......... t:5 \ 264 &ldst disp=%im5_16 x=0 scale=0 m=%ma_to_m 265@stim5 ...... b:5 t:5 sp:2 ......... ..... \ 266 &ldst disp=%im5_0 x=0 scale=0 m=%ma_to_m 267 268ld 000011 ..... ..... .. . 1 -- 00 size:2 ...... @ldim5 269ld 000011 ..... ..... .. . 0 -- 00 size:2 ...... @ldstx 270st 000011 ..... ..... .. . 1 -- 10 size:2 ...... @stim5 271ldc 000011 ..... ..... .. . 1 -- 0111 ...... @ldim5 size=2 272ldc 000011 ..... ..... .. . 0 -- 0111 ...... @ldstx size=2 273ldc 000011 ..... ..... .. . 1 -- 0101 ...... @ldim5 size=3 274ldc 000011 ..... ..... .. . 0 -- 0101 ...... @ldstx size=3 275lda 000011 ..... ..... .. . 1 -- 0110 ...... @ldim5 size=2 276lda 000011 ..... ..... .. . 0 -- 0110 ...... @ldstx size=2 277lda 000011 ..... ..... .. . 1 -- 0100 ...... @ldim5 size=3 278lda 000011 ..... ..... .. . 0 -- 0100 ...... @ldstx size=3 279sta 000011 ..... ..... .. . 1 -- 1110 ...... @stim5 size=2 280sta 000011 ..... ..... .. . 1 -- 1111 ...... @stim5 size=3 281stby 000011 b:5 r:5 sp:2 a:1 1 -- 1100 m:1 ..... disp=%im5_0 282stdby 000011 b:5 r:5 sp:2 a:1 1 -- 1101 m:1 ..... disp=%im5_0 283 284@fldstwx ...... b:5 x:5 sp:2 scale:1 ....... m:1 ..... \ 285 &ldst t=%rt64 disp=0 size=2 286@fldstwi ...... b:5 ..... sp:2 . ....... . ..... \ 287 &ldst t=%rt64 disp=%im5_16 m=%ma_to_m x=0 scale=0 size=2 288 289fldw 001001 ..... ..... .. . 0 -- 000 . . ..... @fldstwx 290fldw 001001 ..... ..... .. . 1 -- 000 . . ..... @fldstwi 291fstw 001001 ..... ..... .. . 0 -- 100 . . ..... @fldstwx 292fstw 001001 ..... ..... .. . 1 -- 100 . . ..... @fldstwi 293 294@fldstdx ...... b:5 x:5 sp:2 scale:1 ....... m:1 t:5 \ 295 &ldst disp=0 size=3 296@fldstdi ...... b:5 ..... sp:2 . ....... . t:5 \ 297 &ldst disp=%im5_16 m=%ma_to_m x=0 scale=0 size=3 298 299fldd 001011 ..... ..... .. . 0 -- 000 0 . ..... @fldstdx 300fldd 001011 ..... ..... .. . 1 -- 000 0 . ..... @fldstdi 301fstd 001011 ..... ..... .. . 0 -- 100 0 . ..... @fldstdx 302fstd 001011 ..... ..... .. . 1 -- 100 0 . ..... @fldstdi 303 304#### 305# Offset Mem 306#### 307 308@ldstim11 ...... b:5 t:5 ................ \ 309 &ldst sp=%assemble_sp disp=%assemble_11a \ 310 m=%ma2_to_m x=0 scale=0 size=3 311@ldstim14 ...... b:5 t:5 ................ \ 312 &ldst sp=%assemble_sp disp=%assemble_16 \ 313 x=0 scale=0 m=0 314@ldstim14m ...... b:5 t:5 ................ \ 315 &ldst sp=%assemble_sp disp=%assemble_16 \ 316 x=0 scale=0 m=%neg_to_m 317@ldstim12m ...... b:5 t:5 ................ \ 318 &ldst sp=%assemble_sp disp=%assemble_12a \ 319 x=0 scale=0 m=%pos_to_m 320 321# LDB, LDH, LDW, LDWM 322ld 010000 ..... ..... .. .............. @ldstim14 size=0 323ld 010001 ..... ..... .. .............. @ldstim14 size=1 324ld 010010 ..... ..... .. .............. @ldstim14 size=2 325ld 010011 ..... ..... .. .............. @ldstim14m size=2 326ld 010111 ..... ..... .. ...........10. @ldstim12m size=2 327 328# STB, STH, STW, STWM 329st 011000 ..... ..... .. .............. @ldstim14 size=0 330st 011001 ..... ..... .. .............. @ldstim14 size=1 331st 011010 ..... ..... .. .............. @ldstim14 size=2 332st 011011 ..... ..... .. .............. @ldstim14m size=2 333st 011111 ..... ..... .. ...........10. @ldstim12m size=2 334 335fldw 010110 b:5 ..... ................ \ 336 &ldst disp=%assemble_12a sp=%assemble_sp \ 337 t=%rm64 m=%a_to_m x=0 scale=0 size=2 338fldw 010111 b:5 ..... .............0.. \ 339 &ldst disp=%assemble_12a sp=%assemble_sp \ 340 t=%rm64 m=0 x=0 scale=0 size=2 341 342fstw 011110 b:5 ..... ................ \ 343 &ldst disp=%assemble_12a sp=%assemble_sp \ 344 t=%rm64 m=%a_to_m x=0 scale=0 size=2 345fstw 011111 b:5 ..... .............0.. \ 346 &ldst disp=%assemble_12a sp=%assemble_sp \ 347 t=%rm64 m=0 x=0 scale=0 size=2 348 349ld 010100 ..... ..... .. ............0. @ldstim11 350fldd 010100 ..... ..... .. ............1. @ldstim11 351 352st 011100 ..... ..... .. ............0. @ldstim11 353fstd 011100 ..... ..... .. ............1. @ldstim11 354 355#### 356# Floating-point Multiply Add 357#### 358 359&mpyadd rm1 rm2 ta ra tm 360@mpyadd ...... rm1:5 rm2:5 ta:5 ra:5 . tm:5 &mpyadd 361 362fmpyadd_f 000110 ..... ..... ..... ..... 0 ..... @mpyadd 363fmpyadd_d 000110 ..... ..... ..... ..... 1 ..... @mpyadd 364fmpysub_f 100110 ..... ..... ..... ..... 0 ..... @mpyadd 365fmpysub_d 100110 ..... ..... ..... ..... 1 ..... @mpyadd 366 367#### 368# Conditional Branches 369#### 370 371bb_sar 110000 00000 r:5 c:1 1 d:1 ........... n:1 . disp=%assemble_12 372bb_imm 110001 p:5 r:5 c:1 1 d:1 ........... n:1 . disp=%assemble_12 373 374movb 110010 ..... ..... ... ........... . . @rrb_cf f=0 375movbi 110011 ..... ..... ... ........... . . @rib_cf f=0 376 377cmpb 100000 ..... ..... ... ........... . . @rrb_cdf d=0 f=0 378cmpb 100010 ..... ..... ... ........... . . @rrb_cdf d=0 f=1 379cmpb 100111 ..... ..... ... ........... . . @rrb_cdf d=1 f=0 380cmpb 101111 ..... ..... ... ........... . . @rrb_cdf d=1 f=1 381cmpbi 100001 ..... ..... ... ........... . . @rib_cdf d=0 f=0 382cmpbi 100011 ..... ..... ... ........... . . @rib_cdf d=0 f=1 383cmpbi 111011 r:5 ..... f:1 .. ........... n:1 . \ 384 &rib_c_d_f d=1 disp=%assemble_12 c=%cmpbid_c i=%im5_16 385 386addb 101000 ..... ..... ... ........... . . @rrb_cf f=0 387addb 101010 ..... ..... ... ........... . . @rrb_cf f=1 388addbi 101001 ..... ..... ... ........... . . @rib_cf f=0 389addbi 101011 ..... ..... ... ........... . . @rib_cf f=1 390 391#### 392# Shift, Extract, Deposit 393#### 394 395shrp_sar 110100 r2:5 r1:5 c:3 00 0 d:1 0000 t:5 396shrp_imm 110100 r2:5 r1:5 c:3 01 0 cpos:5 t:5 d=0 397shrp_imm 110100 r2:5 r1:5 c:3 0. 1 ..... t:5 \ 398 d=1 cpos=%cpos6_11 399 400extr_sar 110100 r:5 t:5 c:3 10 se:1 00 000 ..... d=0 len=%len5 401extr_sar 110100 r:5 t:5 c:3 10 se:1 1. 000 ..... d=1 len=%len6_8 402extr_imm 110100 r:5 t:5 c:3 11 se:1 pos:5 ..... d=0 len=%len5 403extr_imm 110110 r:5 t:5 c:3 .. se:1 ..... ..... \ 404 d=1 len=%len6_12 pos=%cpos6_11 405 406dep_sar 110101 t:5 r:5 c:3 00 nz:1 00 000 ..... d=0 len=%len5 407dep_sar 110101 t:5 r:5 c:3 00 nz:1 1. 000 ..... d=1 len=%len6_8 408dep_imm 110101 t:5 r:5 c:3 01 nz:1 cpos:5 ..... d=0 len=%len5 409dep_imm 111100 t:5 r:5 c:3 .. nz:1 ..... ..... \ 410 d=1 len=%len6_12 cpos=%cpos6_11 411depi_sar 110101 t:5 ..... c:3 10 nz:1 d:1 . 000 ..... \ 412 i=%im5_16 len=%len6_8 413depi_imm 110101 t:5 ..... c:3 11 nz:1 cpos:5 ..... \ 414 d=0 i=%im5_16 len=%len5 415depi_imm 111101 t:5 ..... c:3 .. nz:1 ..... ..... \ 416 d=1 i=%im5_16 len=%len6_12 cpos=%cpos6_11 417 418#### 419# Branch External 420#### 421 422&BE b l n disp sp 423@be ...... b:5 ..... ... ........... n:1 . \ 424 &BE disp=%assemble_17 sp=%assemble_sr3 425 426be 111000 ..... ..... ... ........... . . @be l=0 427be 111001 ..... ..... ... ........... . . @be l=31 428 429#### 430# Branch 431#### 432 433&BL l n disp 434@bl ...... l:5 ..... ... ........... n:1 . &BL disp=%assemble_17 435 436# B,L and B,L,PUSH 437bl 111010 ..... ..... 000 ........... . . @bl 438bl 111010 ..... ..... 100 ........... . . @bl 439# B,L (long displacement) 440bl 111010 ..... ..... 101 ........... n:1 . &BL l=2 \ 441 disp=%assemble_22 442b_gate 111010 ..... ..... 001 ........... . . @bl 443blr 111010 l:5 x:5 010 00000000000 n:1 0 444nopbts 111010 00000 00000 010 0---------1 0 1 # clrbts/popbts 445nopbts 111010 00000 ----- 010 00000000000 0 1 # pushbts/pushnom 446bv 111010 b:5 x:5 110 00000000000 n:1 0 447bve 111010 b:5 00000 110 10000000000 n:1 - l=0 448bve 111010 b:5 00000 111 10000000000 n:1 - l=2 449 450#### 451# FP Fused Multiple-Add 452#### 453 454fmpyfadd_f 101110 ..... ..... ... . 0 ... . . neg:1 ..... \ 455 rm1=%ra64 rm2=%rb64 ra3=%rc64 t=%rt64 456fmpyfadd_d 101110 rm1:5 rm2:5 ... 0 1 ..0 0 0 neg:1 t:5 ra3=%rc32 457 458#### 459# FP operations 460#### 461 462&fclass01 r t 463&fclass2 r1 r2 c y 464&fclass3 r1 r2 t 465 466@f0c_0 ...... r:5 00000 ..... 00 000 0 t:5 &fclass01 467@f0c_1 ...... r:5 000.. ..... 01 000 0 t:5 &fclass01 468@f0c_2 ...... r1:5 r2:5 y:3 .. 10 000 . c:5 &fclass2 469@f0c_3 ...... r1:5 r2:5 ..... 11 000 0 t:5 &fclass3 470 471@f0e_f_0 ...... ..... 00000 ... 0 0 000 .. 0 ..... \ 472 &fclass01 r=%ra64 t=%rt64 473@f0e_d_0 ...... r:5 00000 ... 0 1 000 00 0 t:5 &fclass01 474 475@f0e_ff_1 ...... ..... 000 ... 0000 010 .. 0 ..... \ 476 &fclass01 r=%ra64 t=%rt64 477@f0e_fd_1 ...... ..... 000 ... 0100 010 .0 0 t:5 &fclass01 r=%ra64 478@f0e_df_1 ...... r:5 000 ... 0001 010 0. 0 ..... &fclass01 t=%rt64 479@f0e_dd_1 ...... r:5 000 ... 0101 010 00 0 t:5 &fclass01 480 481@f0e_f_2 ...... ..... ..... y:3 .0 100 .00 c:5 \ 482 &fclass2 r1=%ra64 r2=%rb64 483@f0e_d_2 ...... r1:5 r2:5 y:3 01 100 000 c:5 &fclass2 484 485@f0e_f_3 ...... ..... ..... ... .0 110 ..0 ..... \ 486 &fclass3 r1=%ra64 r2=%rb64 t=%rt64 487@f0e_d_3 ...... r1:5 r2:5 ... 01 110 000 t:5 &fclass3 488 489# Floating point class 0 490 491fid_f 001100 00000 00000 000 00 000000 00000 492 493fcpy_f 001100 ..... ..... 010 00 ...... ..... @f0c_0 494fabs_f 001100 ..... ..... 011 00 ...... ..... @f0c_0 495fsqrt_f 001100 ..... ..... 100 00 ...... ..... @f0c_0 496frnd_f 001100 ..... ..... 101 00 ...... ..... @f0c_0 497fneg_f 001100 ..... ..... 110 00 ...... ..... @f0c_0 498fnegabs_f 001100 ..... ..... 111 00 ...... ..... @f0c_0 499 500fcpy_d 001100 ..... ..... 010 01 ...... ..... @f0c_0 501fabs_d 001100 ..... ..... 011 01 ...... ..... @f0c_0 502fsqrt_d 001100 ..... ..... 100 01 ...... ..... @f0c_0 503frnd_d 001100 ..... ..... 101 01 ...... ..... @f0c_0 504fneg_d 001100 ..... ..... 110 01 ...... ..... @f0c_0 505fnegabs_d 001100 ..... ..... 111 01 ...... ..... @f0c_0 506 507fcpy_f 001110 ..... ..... 010 ........ ..... @f0e_f_0 508fabs_f 001110 ..... ..... 011 ........ ..... @f0e_f_0 509fsqrt_f 001110 ..... ..... 100 ........ ..... @f0e_f_0 510frnd_f 001110 ..... ..... 101 ........ ..... @f0e_f_0 511fneg_f 001110 ..... ..... 110 ........ ..... @f0e_f_0 512fnegabs_f 001110 ..... ..... 111 ........ ..... @f0e_f_0 513 514fcpy_d 001110 ..... ..... 010 ........ ..... @f0e_d_0 515fabs_d 001110 ..... ..... 011 ........ ..... @f0e_d_0 516fsqrt_d 001110 ..... ..... 100 ........ ..... @f0e_d_0 517frnd_d 001110 ..... ..... 101 ........ ..... @f0e_d_0 518fneg_d 001110 ..... ..... 110 ........ ..... @f0e_d_0 519fnegabs_d 001110 ..... ..... 111 ........ ..... @f0e_d_0 520 521# Floating point class 1 522 523# float/float 524fcnv_d_f 001100 ..... ... 000 00 01 ...... ..... @f0c_1 525fcnv_f_d 001100 ..... ... 000 01 00 ...... ..... @f0c_1 526 527fcnv_d_f 001110 ..... ... 000 .......... ..... @f0e_df_1 528fcnv_f_d 001110 ..... ... 000 .......... ..... @f0e_fd_1 529 530# int/float 531fcnv_w_f 001100 ..... ... 001 00 00 ...... ..... @f0c_1 532fcnv_q_f 001100 ..... ... 001 00 01 ...... ..... @f0c_1 533fcnv_w_d 001100 ..... ... 001 01 00 ...... ..... @f0c_1 534fcnv_q_d 001100 ..... ... 001 01 01 ...... ..... @f0c_1 535 536fcnv_w_f 001110 ..... ... 001 .......... ..... @f0e_ff_1 537fcnv_q_f 001110 ..... ... 001 .......... ..... @f0e_df_1 538fcnv_w_d 001110 ..... ... 001 .......... ..... @f0e_fd_1 539fcnv_q_d 001110 ..... ... 001 .......... ..... @f0e_dd_1 540 541# float/int 542fcnv_f_w 001100 ..... ... 010 00 00 ...... ..... @f0c_1 543fcnv_d_w 001100 ..... ... 010 00 01 ...... ..... @f0c_1 544fcnv_f_q 001100 ..... ... 010 01 00 ...... ..... @f0c_1 545fcnv_d_q 001100 ..... ... 010 01 01 ...... ..... @f0c_1 546 547fcnv_f_w 001110 ..... ... 010 .......... ..... @f0e_ff_1 548fcnv_d_w 001110 ..... ... 010 .......... ..... @f0e_df_1 549fcnv_f_q 001110 ..... ... 010 .......... ..... @f0e_fd_1 550fcnv_d_q 001110 ..... ... 010 .......... ..... @f0e_dd_1 551 552# float/int truncate 553fcnv_t_f_w 001100 ..... ... 011 00 00 ...... ..... @f0c_1 554fcnv_t_d_w 001100 ..... ... 011 00 01 ...... ..... @f0c_1 555fcnv_t_f_q 001100 ..... ... 011 01 00 ...... ..... @f0c_1 556fcnv_t_d_q 001100 ..... ... 011 01 01 ...... ..... @f0c_1 557 558fcnv_t_f_w 001110 ..... ... 011 .......... ..... @f0e_ff_1 559fcnv_t_d_w 001110 ..... ... 011 .......... ..... @f0e_df_1 560fcnv_t_f_q 001110 ..... ... 011 .......... ..... @f0e_fd_1 561fcnv_t_d_q 001110 ..... ... 011 .......... ..... @f0e_dd_1 562 563# uint/float 564fcnv_uw_f 001100 ..... ... 101 00 00 ...... ..... @f0c_1 565fcnv_uq_f 001100 ..... ... 101 00 01 ...... ..... @f0c_1 566fcnv_uw_d 001100 ..... ... 101 01 00 ...... ..... @f0c_1 567fcnv_uq_d 001100 ..... ... 101 01 01 ...... ..... @f0c_1 568 569fcnv_uw_f 001110 ..... ... 101 .......... ..... @f0e_ff_1 570fcnv_uq_f 001110 ..... ... 101 .......... ..... @f0e_df_1 571fcnv_uw_d 001110 ..... ... 101 .......... ..... @f0e_fd_1 572fcnv_uq_d 001110 ..... ... 101 .......... ..... @f0e_dd_1 573 574# float/int 575fcnv_f_uw 001100 ..... ... 110 00 00 ...... ..... @f0c_1 576fcnv_d_uw 001100 ..... ... 110 00 01 ...... ..... @f0c_1 577fcnv_f_uq 001100 ..... ... 110 01 00 ...... ..... @f0c_1 578fcnv_d_uq 001100 ..... ... 110 01 01 ...... ..... @f0c_1 579 580fcnv_f_uw 001110 ..... ... 110 .......... ..... @f0e_ff_1 581fcnv_d_uw 001110 ..... ... 110 .......... ..... @f0e_df_1 582fcnv_f_uq 001110 ..... ... 110 .......... ..... @f0e_fd_1 583fcnv_d_uq 001110 ..... ... 110 .......... ..... @f0e_dd_1 584 585# float/int truncate 586fcnv_t_f_uw 001100 ..... ... 111 00 00 ...... ..... @f0c_1 587fcnv_t_d_uw 001100 ..... ... 111 00 01 ...... ..... @f0c_1 588fcnv_t_f_uq 001100 ..... ... 111 01 00 ...... ..... @f0c_1 589fcnv_t_d_uq 001100 ..... ... 111 01 01 ...... ..... @f0c_1 590 591fcnv_t_f_uw 001110 ..... ... 111 .......... ..... @f0e_ff_1 592fcnv_t_d_uw 001110 ..... ... 111 .......... ..... @f0e_df_1 593fcnv_t_f_uq 001110 ..... ... 111 .......... ..... @f0e_fd_1 594fcnv_t_d_uq 001110 ..... ... 111 .......... ..... @f0e_dd_1 595 596# Floating point class 2 597 598ftest 001100 00000 00000 y:3 00 10000 1 c:5 599 600fcmp_f 001100 ..... ..... ... 00 ..... 0 ..... @f0c_2 601fcmp_d 001100 ..... ..... ... 01 ..... 0 ..... @f0c_2 602 603fcmp_f 001110 ..... ..... ... ..... ... ..... @f0e_f_2 604fcmp_d 001110 ..... ..... ... ..... ... ..... @f0e_d_2 605 606# Floating point class 3 607 608fadd_f 001100 ..... ..... 000 00 ...... ..... @f0c_3 609fsub_f 001100 ..... ..... 001 00 ...... ..... @f0c_3 610fmpy_f 001100 ..... ..... 010 00 ...... ..... @f0c_3 611fdiv_f 001100 ..... ..... 011 00 ...... ..... @f0c_3 612 613fadd_d 001100 ..... ..... 000 01 ...... ..... @f0c_3 614fsub_d 001100 ..... ..... 001 01 ...... ..... @f0c_3 615fmpy_d 001100 ..... ..... 010 01 ...... ..... @f0c_3 616fdiv_d 001100 ..... ..... 011 01 ...... ..... @f0c_3 617 618fadd_f 001110 ..... ..... 000 ..... ... ..... @f0e_f_3 619fsub_f 001110 ..... ..... 001 ..... ... ..... @f0e_f_3 620fmpy_f 001110 ..... ..... 010 ..... ... ..... @f0e_f_3 621fdiv_f 001110 ..... ..... 011 ..... ... ..... @f0e_f_3 622 623fadd_d 001110 ..... ..... 000 ..... ... ..... @f0e_d_3 624fsub_d 001110 ..... ..... 001 ..... ... ..... @f0e_d_3 625fmpy_d 001110 ..... ..... 010 ..... ... ..... @f0e_d_3 626fdiv_d 001110 ..... ..... 011 ..... ... ..... @f0e_d_3 627 628xmpyu 001110 ..... ..... 010 .0111 .00 t:5 r1=%ra64 r2=%rb64 629 630# diag 631diag 000101 i:26 632