1# 2# HPPA instruction decode definitions. 3# 4# Copyright (c) 2018 Richard Henderson <rth@twiddle.net> 5# 6# This library is free software; you can redistribute it and/or 7# modify it under the terms of the GNU Lesser General Public 8# License as published by the Free Software Foundation; either 9# version 2.1 of the License, or (at your option) any later version. 10# 11# This library is distributed in the hope that it will be useful, 12# but WITHOUT ANY WARRANTY; without even the implied warranty of 13# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14# Lesser General Public License for more details. 15# 16# You should have received a copy of the GNU Lesser General Public 17# License along with this library; if not, see <http://www.gnu.org/licenses/>. 18# 19 20#### 21# Field definitions 22#### 23 24%assemble_sr3 13:1 14:2 25%assemble_sr3x 13:1 14:2 !function=expand_sr3x 26 27%assemble_11a 0:s1 4:10 !function=expand_shl3 28%assemble_12 0:s1 2:1 3:10 !function=expand_shl2 29%assemble_12a 0:s1 3:11 !function=expand_shl2 30%assemble_17 0:s1 16:5 2:1 3:10 !function=expand_shl2 31%assemble_22 0:s1 16:10 2:1 3:10 !function=expand_shl2 32 33%assemble_21 0:s1 1:11 14:2 16:5 12:2 !function=expand_shl11 34 35%lowsign_11 0:s1 1:10 36%lowsign_14 0:s1 1:13 37 38%sm_imm 16:10 !function=expand_sm_imm 39 40%rm64 1:1 16:5 41%rt64 6:1 0:5 42%ra64 7:1 21:5 43%rb64 12:1 16:5 44%rc64 8:1 13:3 9:2 45%rc32 13:3 9:2 46 47%im5_0 0:s1 1:4 48%im5_16 16:s1 17:4 49%ma_to_m 5:1 13:1 !function=ma_to_m 50%ma2_to_m 2:2 !function=ma_to_m 51%pos_to_m 0:1 !function=pos_to_m 52%neg_to_m 0:1 !function=neg_to_m 53%a_to_m 2:1 !function=neg_to_m 54 55#### 56# Argument set definitions 57#### 58 59# All insns that need to form a virtual address should use this set. 60&ldst t b x disp sp m scale size 61 62&rr_cf t r cf 63&rrr_cf t r1 r2 cf 64&rrr_cf_sh t r1 r2 cf sh 65&rri_cf t r i cf 66 67&rrb_c_f disp n c f r1 r2 68&rib_c_f disp n c f r i 69 70#### 71# Format definitions 72#### 73 74@rr_cf ...... r:5 ..... cf:4 ....... t:5 &rr_cf 75@rrr_cf ...... r2:5 r1:5 cf:4 ....... t:5 &rrr_cf 76@rrr_cf_sh ...... r2:5 r1:5 cf:4 .... sh:2 . t:5 &rrr_cf_sh 77@rrr_cf_sh0 ...... r2:5 r1:5 cf:4 ....... t:5 &rrr_cf_sh sh=0 78@rri_cf ...... r:5 t:5 cf:4 . ........... &rri_cf i=%lowsign_11 79 80@rrb_cf ...... r2:5 r1:5 c:3 ........... n:1 . \ 81 &rrb_c_f disp=%assemble_12 82@rib_cf ...... r:5 ..... c:3 ........... n:1 . \ 83 &rib_c_f disp=%assemble_12 i=%im5_16 84 85#### 86# System 87#### 88 89break 000000 ----- ----- --- 00000000 ----- 90 91mtsp 000000 ----- r:5 ... 11000001 00000 sp=%assemble_sr3 92mtctl 000000 t:5 r:5 --- 11000010 00000 93mtsarcm 000000 01011 r:5 --- 11000110 00000 94mtsm 000000 00000 r:5 000 11000011 00000 95 96mfia 000000 ----- 00000 --- 10100101 t:5 97mfsp 000000 ----- 00000 ... 00100101 t:5 sp=%assemble_sr3 98mfctl 000000 r:5 00000- e:1 -01000101 t:5 99 100sync 000000 ----- ----- 000 00100000 00000 # sync, syncdma 101 102ldsid 000000 b:5 ----- sp:2 0 10000101 t:5 103 104rsm 000000 .......... 000 01110011 t:5 i=%sm_imm 105ssm 000000 .......... 000 01101011 t:5 i=%sm_imm 106 107rfi 000000 ----- ----- --- 01100000 00000 108rfi_r 000000 ----- ----- --- 01100101 00000 109 110# These are artificial instructions used by QEMU firmware. 111# They are allocated from the unassigned instruction space. 112halt 1111 1111 1111 1101 1110 1010 1101 0000 113reset 1111 1111 1111 1101 1110 1010 1101 0001 114getshadowregs 1111 1111 1111 1101 1110 1010 1101 0010 115 116#### 117# Memory Management 118#### 119 120@addrx ...... b:5 x:5 .. ........ m:1 ..... \ 121 &ldst disp=0 scale=0 t=0 sp=0 size=0 122 123nop 000001 ----- ----- -- 11001010 0 ----- # fdc, disp 124nop_addrx 000001 ..... ..... -- 01001010 . ----- @addrx # fdc, index 125nop_addrx 000001 ..... ..... -- 01001011 . ----- @addrx # fdce 126nop_addrx 000001 ..... ..... --- 0001010 . ----- @addrx # fic 0x0a 127nop_addrx 000001 ..... ..... -- 01001111 . 00000 @addrx # fic 0x4f 128nop_addrx 000001 ..... ..... --- 0001011 . ----- @addrx # fice 129nop_addrx 000001 ..... ..... -- 01001110 . 00000 @addrx # pdc 130 131probe 000001 b:5 ri:5 sp:2 imm:1 100011 write:1 0 t:5 132 133ixtlbx 000001 b:5 r:5 sp:2 0100000 addr:1 0 00000 data=1 134ixtlbx 000001 b:5 r:5 ... 000000 addr:1 0 00000 \ 135 sp=%assemble_sr3x data=0 136 137# pcxl and pcxl2 Fast TLB Insert instructions 138ixtlbxf 000001 00000 r:5 00 0 data:1 01000 addr:1 0 00000 139 140pxtlbx 000001 b:5 x:5 sp:2 0100100 local:1 m:1 ----- data=1 141pxtlbx 000001 b:5 x:5 ... 000100 local:1 m:1 ----- \ 142 sp=%assemble_sr3x data=0 143 144lpa 000001 b:5 x:5 sp:2 01001101 m:1 t:5 \ 145 &ldst disp=0 scale=0 size=0 146 147lci 000001 ----- ----- -- 01001100 0 t:5 148 149#### 150# Arith/Log 151#### 152 153andcm 000010 ..... ..... .... 000000 - ..... @rrr_cf 154and 000010 ..... ..... .... 001000 - ..... @rrr_cf 155or 000010 ..... ..... .... 001001 - ..... @rrr_cf 156xor 000010 ..... ..... .... 001010 0 ..... @rrr_cf 157uxor 000010 ..... ..... .... 001110 0 ..... @rrr_cf 158ds 000010 ..... ..... .... 010001 0 ..... @rrr_cf 159cmpclr 000010 ..... ..... .... 100010 0 ..... @rrr_cf 160uaddcm 000010 ..... ..... .... 100110 0 ..... @rrr_cf 161uaddcm_tc 000010 ..... ..... .... 100111 0 ..... @rrr_cf 162dcor 000010 ..... 00000 .... 101110 0 ..... @rr_cf 163dcor_i 000010 ..... 00000 .... 101111 0 ..... @rr_cf 164 165add 000010 ..... ..... .... 0110.. - ..... @rrr_cf_sh 166add_l 000010 ..... ..... .... 1010.. 0 ..... @rrr_cf_sh 167add_tsv 000010 ..... ..... .... 1110.. 0 ..... @rrr_cf_sh 168add_c 000010 ..... ..... .... 011100 0 ..... @rrr_cf_sh0 169add_c_tsv 000010 ..... ..... .... 111100 0 ..... @rrr_cf_sh0 170 171sub 000010 ..... ..... .... 010000 - ..... @rrr_cf 172sub_tsv 000010 ..... ..... .... 110000 0 ..... @rrr_cf 173sub_tc 000010 ..... ..... .... 010011 0 ..... @rrr_cf 174sub_tsv_tc 000010 ..... ..... .... 110011 0 ..... @rrr_cf 175sub_b 000010 ..... ..... .... 010100 0 ..... @rrr_cf 176sub_b_tsv 000010 ..... ..... .... 110100 0 ..... @rrr_cf 177 178ldil 001000 t:5 ..................... i=%assemble_21 179addil 001010 r:5 ..................... i=%assemble_21 180ldo 001101 b:5 t:5 -- .............. i=%lowsign_14 181 182addi 101101 ..... ..... .... 0 ........... @rri_cf 183addi_tsv 101101 ..... ..... .... 1 ........... @rri_cf 184addi_tc 101100 ..... ..... .... 0 ........... @rri_cf 185addi_tc_tsv 101100 ..... ..... .... 1 ........... @rri_cf 186 187subi 100101 ..... ..... .... 0 ........... @rri_cf 188subi_tsv 100101 ..... ..... .... 1 ........... @rri_cf 189 190cmpiclr 100100 ..... ..... .... 0 ........... @rri_cf 191 192#### 193# Index Mem 194#### 195 196@ldstx ...... b:5 x:5 sp:2 scale:1 ....... m:1 t:5 &ldst disp=0 197@ldim5 ...... b:5 ..... sp:2 ......... t:5 \ 198 &ldst disp=%im5_16 x=0 scale=0 m=%ma_to_m 199@stim5 ...... b:5 t:5 sp:2 ......... ..... \ 200 &ldst disp=%im5_0 x=0 scale=0 m=%ma_to_m 201 202ld 000011 ..... ..... .. . 1 -- 00 size:2 ...... @ldim5 203ld 000011 ..... ..... .. . 0 -- 00 size:2 ...... @ldstx 204st 000011 ..... ..... .. . 1 -- 10 size:2 ...... @stim5 205ldc 000011 ..... ..... .. . 1 -- 0111 ...... @ldim5 size=2 206ldc 000011 ..... ..... .. . 0 -- 0111 ...... @ldstx size=2 207lda 000011 ..... ..... .. . 1 -- 0110 ...... @ldim5 size=2 208lda 000011 ..... ..... .. . 0 -- 0110 ...... @ldstx size=2 209sta 000011 ..... ..... .. . 1 -- 1110 ...... @stim5 size=2 210stby 000011 b:5 r:5 sp:2 a:1 1 -- 1100 m:1 ..... disp=%im5_0 211 212@fldstwx ...... b:5 x:5 sp:2 scale:1 ....... m:1 ..... \ 213 &ldst t=%rt64 disp=0 size=2 214@fldstwi ...... b:5 ..... sp:2 . ....... . ..... \ 215 &ldst t=%rt64 disp=%im5_16 m=%ma_to_m x=0 scale=0 size=2 216 217fldw 001001 ..... ..... .. . 0 -- 000 . . ..... @fldstwx 218fldw 001001 ..... ..... .. . 1 -- 000 . . ..... @fldstwi 219fstw 001001 ..... ..... .. . 0 -- 100 . . ..... @fldstwx 220fstw 001001 ..... ..... .. . 1 -- 100 . . ..... @fldstwi 221 222@fldstdx ...... b:5 x:5 sp:2 scale:1 ....... m:1 t:5 \ 223 &ldst disp=0 size=3 224@fldstdi ...... b:5 ..... sp:2 . ....... . t:5 \ 225 &ldst disp=%im5_16 m=%ma_to_m x=0 scale=0 size=3 226 227fldd 001011 ..... ..... .. . 0 -- 000 0 . ..... @fldstdx 228fldd 001011 ..... ..... .. . 1 -- 000 0 . ..... @fldstdi 229fstd 001011 ..... ..... .. . 0 -- 100 0 . ..... @fldstdx 230fstd 001011 ..... ..... .. . 1 -- 100 0 . ..... @fldstdi 231 232#### 233# Offset Mem 234#### 235 236@ldstim14 ...... b:5 t:5 sp:2 .............. \ 237 &ldst disp=%lowsign_14 x=0 scale=0 m=0 238@ldstim14m ...... b:5 t:5 sp:2 .............. \ 239 &ldst disp=%lowsign_14 x=0 scale=0 m=%neg_to_m 240@ldstim12m ...... b:5 t:5 sp:2 .............. \ 241 &ldst disp=%assemble_12a x=0 scale=0 m=%pos_to_m 242 243# LDB, LDH, LDW, LDWM 244ld 010000 ..... ..... .. .............. @ldstim14 size=0 245ld 010001 ..... ..... .. .............. @ldstim14 size=1 246ld 010010 ..... ..... .. .............. @ldstim14 size=2 247ld 010011 ..... ..... .. .............. @ldstim14m size=2 248ld 010111 ..... ..... .. ...........10. @ldstim12m size=2 249 250# STB, STH, STW, STWM 251st 011000 ..... ..... .. .............. @ldstim14 size=0 252st 011001 ..... ..... .. .............. @ldstim14 size=1 253st 011010 ..... ..... .. .............. @ldstim14 size=2 254st 011011 ..... ..... .. .............. @ldstim14m size=2 255st 011111 ..... ..... .. ...........10. @ldstim12m size=2 256 257fldw 010110 b:5 ..... sp:2 .............. \ 258 &ldst disp=%assemble_12a t=%rm64 m=%a_to_m x=0 scale=0 size=2 259fldw 010111 b:5 ..... sp:2 ...........0.. \ 260 &ldst disp=%assemble_12a t=%rm64 m=0 x=0 scale=0 size=2 261 262fstw 011110 b:5 ..... sp:2 .............. \ 263 &ldst disp=%assemble_12a t=%rm64 m=%a_to_m x=0 scale=0 size=2 264fstw 011111 b:5 ..... sp:2 ...........0.. \ 265 &ldst disp=%assemble_12a t=%rm64 m=0 x=0 scale=0 size=2 266 267fldd 010100 b:5 t:5 sp:2 .......... .. 1 . \ 268 &ldst disp=%assemble_11a m=%ma2_to_m x=0 scale=0 size=3 269 270fstd 011100 b:5 t:5 sp:2 .......... .. 1 . \ 271 &ldst disp=%assemble_11a m=%ma2_to_m x=0 scale=0 size=3 272 273#### 274# Floating-point Multiply Add 275#### 276 277&mpyadd rm1 rm2 ta ra tm 278@mpyadd ...... rm1:5 rm2:5 ta:5 ra:5 . tm:5 &mpyadd 279 280fmpyadd_f 000110 ..... ..... ..... ..... 0 ..... @mpyadd 281fmpyadd_d 000110 ..... ..... ..... ..... 1 ..... @mpyadd 282fmpysub_f 100110 ..... ..... ..... ..... 0 ..... @mpyadd 283fmpysub_d 100110 ..... ..... ..... ..... 1 ..... @mpyadd 284 285#### 286# Conditional Branches 287#### 288 289bb_sar 110000 00000 r:5 c:1 10 ........... n:1 . disp=%assemble_12 290bb_imm 110001 p:5 r:5 c:1 10 ........... n:1 . disp=%assemble_12 291 292movb 110010 ..... ..... ... ........... . . @rrb_cf f=0 293movbi 110011 ..... ..... ... ........... . . @rib_cf f=0 294 295cmpb 100000 ..... ..... ... ........... . . @rrb_cf f=0 296cmpb 100010 ..... ..... ... ........... . . @rrb_cf f=1 297cmpbi 100001 ..... ..... ... ........... . . @rib_cf f=0 298cmpbi 100011 ..... ..... ... ........... . . @rib_cf f=1 299 300addb 101000 ..... ..... ... ........... . . @rrb_cf f=0 301addb 101010 ..... ..... ... ........... . . @rrb_cf f=1 302addbi 101001 ..... ..... ... ........... . . @rib_cf f=0 303addbi 101011 ..... ..... ... ........... . . @rib_cf f=1 304 305#### 306# Shift, Extract, Deposit 307#### 308 309shrpw_sar 110100 r2:5 r1:5 c:3 00 0 00000 t:5 310shrpw_imm 110100 r2:5 r1:5 c:3 01 0 cpos:5 t:5 311 312extrw_sar 110100 r:5 t:5 c:3 10 se:1 00000 clen:5 313extrw_imm 110100 r:5 t:5 c:3 11 se:1 pos:5 clen:5 314 315depw_sar 110101 t:5 r:5 c:3 00 nz:1 00000 clen:5 316depw_imm 110101 t:5 r:5 c:3 01 nz:1 cpos:5 clen:5 317depwi_sar 110101 t:5 ..... c:3 10 nz:1 00000 clen:5 i=%im5_16 318depwi_imm 110101 t:5 ..... c:3 11 nz:1 cpos:5 clen:5 i=%im5_16 319 320#### 321# Branch External 322#### 323 324&BE b l n disp sp 325@be ...... b:5 ..... ... ........... n:1 . \ 326 &BE disp=%assemble_17 sp=%assemble_sr3 327 328be 111000 ..... ..... ... ........... . . @be l=0 329be 111001 ..... ..... ... ........... . . @be l=31 330 331#### 332# Branch 333#### 334 335&BL l n disp 336@bl ...... l:5 ..... ... ........... n:1 . &BL disp=%assemble_17 337 338# B,L and B,L,PUSH 339bl 111010 ..... ..... 000 ........... . . @bl 340bl 111010 ..... ..... 100 ........... . . @bl 341# B,L (long displacement) 342bl 111010 ..... ..... 101 ........... n:1 . &BL l=2 \ 343 disp=%assemble_22 344b_gate 111010 ..... ..... 001 ........... . . @bl 345blr 111010 l:5 x:5 010 00000000000 n:1 0 346bv 111010 b:5 x:5 110 00000000000 n:1 0 347bve 111010 b:5 00000 110 10000000000 n:1 - l=0 348bve 111010 b:5 00000 111 10000000000 n:1 - l=2 349 350#### 351# FP Fused Multiple-Add 352#### 353 354fmpyfadd_f 101110 ..... ..... ... . 0 ... . . neg:1 ..... \ 355 rm1=%ra64 rm2=%rb64 ra3=%rc64 t=%rt64 356fmpyfadd_d 101110 rm1:5 rm2:5 ... 0 1 ..0 0 0 neg:1 t:5 ra3=%rc32 357 358#### 359# FP operations 360#### 361 362&fclass01 r t 363&fclass2 r1 r2 c y 364&fclass3 r1 r2 t 365 366@f0c_0 ...... r:5 00000 ..... 00 000 0 t:5 &fclass01 367@f0c_1 ...... r:5 000.. ..... 01 000 0 t:5 &fclass01 368@f0c_2 ...... r1:5 r2:5 y:3 .. 10 000 . c:5 &fclass2 369@f0c_3 ...... r1:5 r2:5 ..... 11 000 0 t:5 &fclass3 370 371@f0e_f_0 ...... ..... 00000 ... 0 0 000 .. 0 ..... \ 372 &fclass01 r=%ra64 t=%rt64 373@f0e_d_0 ...... r:5 00000 ... 0 1 000 00 0 t:5 &fclass01 374 375@f0e_ff_1 ...... ..... 000 ... 0000 010 .. 0 ..... \ 376 &fclass01 r=%ra64 t=%rt64 377@f0e_fd_1 ...... ..... 000 ... 0100 010 .0 0 t:5 &fclass01 r=%ra64 378@f0e_df_1 ...... r:5 000 ... 0001 010 0. 0 ..... &fclass01 t=%rt64 379@f0e_dd_1 ...... r:5 000 ... 0101 010 00 0 t:5 &fclass01 380 381@f0e_f_2 ...... ..... ..... y:3 .0 100 .00 c:5 \ 382 &fclass2 r1=%ra64 r2=%rb64 383@f0e_d_2 ...... r1:5 r2:5 y:3 01 100 000 c:5 &fclass2 384 385@f0e_f_3 ...... ..... ..... ... .0 110 ..0 ..... \ 386 &fclass3 r1=%ra64 r2=%rb64 t=%rt64 387@f0e_d_3 ...... r1:5 r2:5 ... 01 110 000 t:5 388 389# Floating point class 0 390 391# FID. With r = t = 0, which via fcpy puts 0 into fr0. 392# This is machine/revision = 0, which is reserved for simulator. 393fcpy_f 001100 00000 00000 00000 000000 00000 \ 394 &fclass01 r=0 t=0 395 396fcpy_f 001100 ..... ..... 010 00 ...... ..... @f0c_0 397fabs_f 001100 ..... ..... 011 00 ...... ..... @f0c_0 398fsqrt_f 001100 ..... ..... 100 00 ...... ..... @f0c_0 399frnd_f 001100 ..... ..... 101 00 ...... ..... @f0c_0 400fneg_f 001100 ..... ..... 110 00 ...... ..... @f0c_0 401fnegabs_f 001100 ..... ..... 111 00 ...... ..... @f0c_0 402 403fcpy_d 001100 ..... ..... 010 01 ...... ..... @f0c_0 404fabs_d 001100 ..... ..... 011 01 ...... ..... @f0c_0 405fsqrt_d 001100 ..... ..... 100 01 ...... ..... @f0c_0 406frnd_d 001100 ..... ..... 101 01 ...... ..... @f0c_0 407fneg_d 001100 ..... ..... 110 01 ...... ..... @f0c_0 408fnegabs_d 001100 ..... ..... 111 01 ...... ..... @f0c_0 409 410fcpy_f 001110 ..... ..... 010 ........ ..... @f0e_f_0 411fabs_f 001110 ..... ..... 011 ........ ..... @f0e_f_0 412fsqrt_f 001110 ..... ..... 100 ........ ..... @f0e_f_0 413frnd_f 001110 ..... ..... 101 ........ ..... @f0e_f_0 414fneg_f 001110 ..... ..... 110 ........ ..... @f0e_f_0 415fnegabs_f 001110 ..... ..... 111 ........ ..... @f0e_f_0 416 417fcpy_d 001110 ..... ..... 010 ........ ..... @f0e_d_0 418fabs_d 001110 ..... ..... 011 ........ ..... @f0e_d_0 419fsqrt_d 001110 ..... ..... 100 ........ ..... @f0e_d_0 420frnd_d 001110 ..... ..... 101 ........ ..... @f0e_d_0 421fneg_d 001110 ..... ..... 110 ........ ..... @f0e_d_0 422fnegabs_d 001110 ..... ..... 111 ........ ..... @f0e_d_0 423 424# Floating point class 1 425 426# float/float 427fcnv_d_f 001100 ..... ... 000 00 01 ...... ..... @f0c_1 428fcnv_f_d 001100 ..... ... 000 01 00 ...... ..... @f0c_1 429 430fcnv_d_f 001110 ..... ... 000 .......... ..... @f0e_df_1 431fcnv_f_d 001110 ..... ... 000 .......... ..... @f0e_fd_1 432 433# int/float 434fcnv_w_f 001100 ..... ... 001 00 00 ...... ..... @f0c_1 435fcnv_q_f 001100 ..... ... 001 00 01 ...... ..... @f0c_1 436fcnv_w_d 001100 ..... ... 001 01 00 ...... ..... @f0c_1 437fcnv_q_d 001100 ..... ... 001 01 01 ...... ..... @f0c_1 438 439fcnv_w_f 001110 ..... ... 001 .......... ..... @f0e_ff_1 440fcnv_q_f 001110 ..... ... 001 .......... ..... @f0e_df_1 441fcnv_w_d 001110 ..... ... 001 .......... ..... @f0e_fd_1 442fcnv_q_d 001110 ..... ... 001 .......... ..... @f0e_dd_1 443 444# float/int 445fcnv_f_w 001100 ..... ... 010 00 00 ...... ..... @f0c_1 446fcnv_d_w 001100 ..... ... 010 00 01 ...... ..... @f0c_1 447fcnv_f_q 001100 ..... ... 010 01 00 ...... ..... @f0c_1 448fcnv_d_q 001100 ..... ... 010 01 01 ...... ..... @f0c_1 449 450fcnv_f_w 001110 ..... ... 010 .......... ..... @f0e_ff_1 451fcnv_d_w 001110 ..... ... 010 .......... ..... @f0e_df_1 452fcnv_f_q 001110 ..... ... 010 .......... ..... @f0e_fd_1 453fcnv_d_q 001110 ..... ... 010 .......... ..... @f0e_dd_1 454 455# float/int truncate 456fcnv_t_f_w 001100 ..... ... 011 00 00 ...... ..... @f0c_1 457fcnv_t_d_w 001100 ..... ... 011 00 01 ...... ..... @f0c_1 458fcnv_t_f_q 001100 ..... ... 011 01 00 ...... ..... @f0c_1 459fcnv_t_d_q 001100 ..... ... 011 01 01 ...... ..... @f0c_1 460 461fcnv_t_f_w 001110 ..... ... 011 .......... ..... @f0e_ff_1 462fcnv_t_d_w 001110 ..... ... 011 .......... ..... @f0e_df_1 463fcnv_t_f_q 001110 ..... ... 011 .......... ..... @f0e_fd_1 464fcnv_t_d_q 001110 ..... ... 011 .......... ..... @f0e_dd_1 465 466# uint/float 467fcnv_uw_f 001100 ..... ... 101 00 00 ...... ..... @f0c_1 468fcnv_uq_f 001100 ..... ... 101 00 01 ...... ..... @f0c_1 469fcnv_uw_d 001100 ..... ... 101 01 00 ...... ..... @f0c_1 470fcnv_uq_d 001100 ..... ... 101 01 01 ...... ..... @f0c_1 471 472fcnv_uw_f 001110 ..... ... 101 .......... ..... @f0e_ff_1 473fcnv_uq_f 001110 ..... ... 101 .......... ..... @f0e_df_1 474fcnv_uw_d 001110 ..... ... 101 .......... ..... @f0e_fd_1 475fcnv_uq_d 001110 ..... ... 101 .......... ..... @f0e_dd_1 476 477# float/int 478fcnv_f_uw 001100 ..... ... 110 00 00 ...... ..... @f0c_1 479fcnv_d_uw 001100 ..... ... 110 00 01 ...... ..... @f0c_1 480fcnv_f_uq 001100 ..... ... 110 01 00 ...... ..... @f0c_1 481fcnv_d_uq 001100 ..... ... 110 01 01 ...... ..... @f0c_1 482 483fcnv_f_uw 001110 ..... ... 110 .......... ..... @f0e_ff_1 484fcnv_d_uw 001110 ..... ... 110 .......... ..... @f0e_df_1 485fcnv_f_uq 001110 ..... ... 110 .......... ..... @f0e_fd_1 486fcnv_d_uq 001110 ..... ... 110 .......... ..... @f0e_dd_1 487 488# float/int truncate 489fcnv_t_f_uw 001100 ..... ... 111 00 00 ...... ..... @f0c_1 490fcnv_t_d_uw 001100 ..... ... 111 00 01 ...... ..... @f0c_1 491fcnv_t_f_uq 001100 ..... ... 111 01 00 ...... ..... @f0c_1 492fcnv_t_d_uq 001100 ..... ... 111 01 01 ...... ..... @f0c_1 493 494fcnv_t_f_uw 001110 ..... ... 111 .......... ..... @f0e_ff_1 495fcnv_t_d_uw 001110 ..... ... 111 .......... ..... @f0e_df_1 496fcnv_t_f_uq 001110 ..... ... 111 .......... ..... @f0e_fd_1 497fcnv_t_d_uq 001110 ..... ... 111 .......... ..... @f0e_dd_1 498 499# Floating point class 2 500 501ftest 001100 00000 00000 y:3 00 10000 1 c:5 502 503fcmp_f 001100 ..... ..... ... 00 ..... 0 ..... @f0c_2 504fcmp_d 001100 ..... ..... ... 01 ..... 0 ..... @f0c_2 505 506fcmp_f 001110 ..... ..... ... ..... ... ..... @f0e_f_2 507fcmp_d 001110 ..... ..... ... ..... ... ..... @f0e_d_2 508 509# Floating point class 3 510 511fadd_f 001100 ..... ..... 000 00 ...... ..... @f0c_3 512fsub_f 001100 ..... ..... 001 00 ...... ..... @f0c_3 513fmpy_f 001100 ..... ..... 010 00 ...... ..... @f0c_3 514fdiv_f 001100 ..... ..... 011 00 ...... ..... @f0c_3 515 516fadd_d 001100 ..... ..... 000 01 ...... ..... @f0c_3 517fsub_d 001100 ..... ..... 001 01 ...... ..... @f0c_3 518fmpy_d 001100 ..... ..... 010 01 ...... ..... @f0c_3 519fdiv_d 001100 ..... ..... 011 01 ...... ..... @f0c_3 520 521fadd_f 001110 ..... ..... 000 ..... ... ..... @f0e_f_3 522fsub_f 001110 ..... ..... 001 ..... ... ..... @f0e_f_3 523fmpy_f 001110 ..... ..... 010 ..... ... ..... @f0e_f_3 524fdiv_f 001110 ..... ..... 011 ..... ... ..... @f0e_f_3 525 526fadd_d 001110 ..... ..... 000 ..... ... ..... @f0e_d_3 527fsub_d 001110 ..... ..... 001 ..... ... ..... @f0e_d_3 528fmpy_d 001110 ..... ..... 010 ..... ... ..... @f0e_d_3 529fdiv_d 001110 ..... ..... 011 ..... ... ..... @f0e_d_3 530 531xmpyu 001110 ..... ..... 010 .0111 .00 t:5 r1=%ra64 r2=%rb64 532 533# diag 534diag 000101 ----- ----- ---- ---- ---- ---- 535