1 /* 2 * PA-RISC emulation cpu definitions for qemu. 3 * 4 * Copyright (c) 2016 Richard Henderson <rth@twiddle.net> 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef HPPA_CPU_H 21 #define HPPA_CPU_H 22 23 #include "qemu-common.h" 24 #include "cpu-qom.h" 25 26 #ifdef TARGET_HPPA64 27 #define TARGET_LONG_BITS 64 28 #define TARGET_VIRT_ADDR_SPACE_BITS 64 29 #define TARGET_REGISTER_BITS 64 30 #define TARGET_PHYS_ADDR_SPACE_BITS 64 31 #elif defined(CONFIG_USER_ONLY) 32 #define TARGET_LONG_BITS 32 33 #define TARGET_VIRT_ADDR_SPACE_BITS 32 34 #define TARGET_REGISTER_BITS 32 35 #define TARGET_PHYS_ADDR_SPACE_BITS 32 36 #else 37 /* In order to form the GVA from space:offset, 38 we need a 64-bit virtual address space. */ 39 #define TARGET_LONG_BITS 64 40 #define TARGET_VIRT_ADDR_SPACE_BITS 64 41 #define TARGET_REGISTER_BITS 32 42 #define TARGET_PHYS_ADDR_SPACE_BITS 32 43 #endif 44 45 /* PA-RISC 1.x processors have a strong memory model. */ 46 /* ??? While we do not yet implement PA-RISC 2.0, those processors have 47 a weak memory model, but with TLB bits that force ordering on a per-page 48 basis. It's probably easier to fall back to a strong memory model. */ 49 #define TCG_GUEST_DEFAULT_MO TCG_MO_ALL 50 51 #define CPUArchState struct CPUHPPAState 52 53 #include "exec/cpu-defs.h" 54 #include "fpu/softfloat.h" 55 56 #define TARGET_PAGE_BITS 12 57 58 #define ALIGNED_ONLY 59 #define NB_MMU_MODES 5 60 #define MMU_KERNEL_IDX 0 61 #define MMU_USER_IDX 3 62 #define MMU_PHYS_IDX 4 63 #define TARGET_INSN_START_EXTRA_WORDS 1 64 65 /* Hardware exceptions, interupts, faults, and traps. */ 66 #define EXCP_HPMC 1 /* high priority machine check */ 67 #define EXCP_POWER_FAIL 2 68 #define EXCP_RC 3 /* recovery counter */ 69 #define EXCP_EXT_INTERRUPT 4 /* external interrupt */ 70 #define EXCP_LPMC 5 /* low priority machine check */ 71 #define EXCP_ITLB_MISS 6 /* itlb miss / instruction page fault */ 72 #define EXCP_IMP 7 /* instruction memory protection trap */ 73 #define EXCP_ILL 8 /* illegal instruction trap */ 74 #define EXCP_BREAK 9 /* break instruction */ 75 #define EXCP_PRIV_OPR 10 /* privileged operation trap */ 76 #define EXCP_PRIV_REG 11 /* privileged register trap */ 77 #define EXCP_OVERFLOW 12 /* signed overflow trap */ 78 #define EXCP_COND 13 /* trap-on-condition */ 79 #define EXCP_ASSIST 14 /* assist exception trap */ 80 #define EXCP_DTLB_MISS 15 /* dtlb miss / data page fault */ 81 #define EXCP_NA_ITLB_MISS 16 /* non-access itlb miss */ 82 #define EXCP_NA_DTLB_MISS 17 /* non-access dtlb miss */ 83 #define EXCP_DMP 18 /* data memory protection trap */ 84 #define EXCP_DMB 19 /* data memory break trap */ 85 #define EXCP_TLB_DIRTY 20 /* tlb dirty bit trap */ 86 #define EXCP_PAGE_REF 21 /* page reference trap */ 87 #define EXCP_ASSIST_EMU 22 /* assist emulation trap */ 88 #define EXCP_HPT 23 /* high-privilege transfer trap */ 89 #define EXCP_LPT 24 /* low-privilege transfer trap */ 90 #define EXCP_TB 25 /* taken branch trap */ 91 #define EXCP_DMAR 26 /* data memory access rights trap */ 92 #define EXCP_DMPI 27 /* data memory protection id trap */ 93 #define EXCP_UNALIGN 28 /* unaligned data reference trap */ 94 #define EXCP_PER_INTERRUPT 29 /* performance monitor interrupt */ 95 96 /* Exceptions for linux-user emulation. */ 97 #define EXCP_SYSCALL 30 98 #define EXCP_SYSCALL_LWS 31 99 100 /* Taken from Linux kernel: arch/parisc/include/asm/psw.h */ 101 #define PSW_I 0x00000001 102 #define PSW_D 0x00000002 103 #define PSW_P 0x00000004 104 #define PSW_Q 0x00000008 105 #define PSW_R 0x00000010 106 #define PSW_F 0x00000020 107 #define PSW_G 0x00000040 /* PA1.x only */ 108 #define PSW_O 0x00000080 /* PA2.0 only */ 109 #define PSW_CB 0x0000ff00 110 #define PSW_M 0x00010000 111 #define PSW_V 0x00020000 112 #define PSW_C 0x00040000 113 #define PSW_B 0x00080000 114 #define PSW_X 0x00100000 115 #define PSW_N 0x00200000 116 #define PSW_L 0x00400000 117 #define PSW_H 0x00800000 118 #define PSW_T 0x01000000 119 #define PSW_S 0x02000000 120 #define PSW_E 0x04000000 121 #ifdef TARGET_HPPA64 122 #define PSW_W 0x08000000 /* PA2.0 only */ 123 #else 124 #define PSW_W 0 125 #endif 126 #define PSW_Z 0x40000000 /* PA1.x only */ 127 #define PSW_Y 0x80000000 /* PA1.x only */ 128 129 #define PSW_SM (PSW_W | PSW_E | PSW_O | PSW_G | PSW_F \ 130 | PSW_R | PSW_Q | PSW_P | PSW_D | PSW_I) 131 132 /* ssm/rsm instructions number PSW_W and PSW_E differently */ 133 #define PSW_SM_I PSW_I /* Enable External Interrupts */ 134 #define PSW_SM_D PSW_D 135 #define PSW_SM_P PSW_P 136 #define PSW_SM_Q PSW_Q /* Enable Interrupt State Collection */ 137 #define PSW_SM_R PSW_R /* Enable Recover Counter Trap */ 138 #ifdef TARGET_HPPA64 139 #define PSW_SM_E 0x100 140 #define PSW_SM_W 0x200 /* PA2.0 only : Enable Wide Mode */ 141 #else 142 #define PSW_SM_E 0 143 #define PSW_SM_W 0 144 #endif 145 146 #define CR_RC 0 147 #define CR_SCRCCR 10 148 #define CR_SAR 11 149 #define CR_IVA 14 150 #define CR_EIEM 15 151 #define CR_IT 16 152 #define CR_IIASQ 17 153 #define CR_IIAOQ 18 154 #define CR_IIR 19 155 #define CR_ISR 20 156 #define CR_IOR 21 157 #define CR_IPSW 22 158 #define CR_EIRR 23 159 160 typedef struct CPUHPPAState CPUHPPAState; 161 162 #if TARGET_REGISTER_BITS == 32 163 typedef uint32_t target_ureg; 164 typedef int32_t target_sreg; 165 #define TREG_FMT_lx "%08"PRIx32 166 #define TREG_FMT_ld "%"PRId32 167 #else 168 typedef uint64_t target_ureg; 169 typedef int64_t target_sreg; 170 #define TREG_FMT_lx "%016"PRIx64 171 #define TREG_FMT_ld "%"PRId64 172 #endif 173 174 typedef struct { 175 uint64_t va_b; 176 uint64_t va_e; 177 target_ureg pa; 178 unsigned u : 1; 179 unsigned t : 1; 180 unsigned d : 1; 181 unsigned b : 1; 182 unsigned page_size : 4; 183 unsigned ar_type : 3; 184 unsigned ar_pl1 : 2; 185 unsigned ar_pl2 : 2; 186 unsigned entry_valid : 1; 187 unsigned access_id : 16; 188 } hppa_tlb_entry; 189 190 struct CPUHPPAState { 191 target_ureg gr[32]; 192 uint64_t fr[32]; 193 uint64_t sr[8]; /* stored shifted into place for gva */ 194 195 target_ureg psw; /* All psw bits except the following: */ 196 target_ureg psw_n; /* boolean */ 197 target_sreg psw_v; /* in most significant bit */ 198 199 /* Splitting the carry-borrow field into the MSB and "the rest", allows 200 * for "the rest" to be deleted when it is unused, but the MSB is in use. 201 * In addition, it's easier to compute carry-in for bit B+1 than it is to 202 * compute carry-out for bit B (3 vs 4 insns for addition, assuming the 203 * host has the appropriate add-with-carry insn to compute the msb). 204 * Therefore the carry bits are stored as: cb_msb : cb & 0x11111110. 205 */ 206 target_ureg psw_cb; /* in least significant bit of next nibble */ 207 target_ureg psw_cb_msb; /* boolean */ 208 209 target_ureg iaoq_f; /* front */ 210 target_ureg iaoq_b; /* back, aka next instruction */ 211 uint64_t iasq_f; 212 uint64_t iasq_b; 213 214 uint32_t fr0_shadow; /* flags, c, ca/cq, rm, d, enables */ 215 float_status fp_status; 216 217 target_ureg cr[32]; /* control registers */ 218 target_ureg cr_back[2]; /* back of cr17/cr18 */ 219 target_ureg shadow[7]; /* shadow registers */ 220 221 /* Those resources are used only in QEMU core */ 222 CPU_COMMON 223 224 /* ??? The number of entries isn't specified by the architecture. */ 225 /* ??? Implement a unified itlb/dtlb for the moment. */ 226 /* ??? We should use a more intelligent data structure. */ 227 hppa_tlb_entry tlb[256]; 228 uint32_t tlb_last; 229 }; 230 231 /** 232 * HPPACPU: 233 * @env: #CPUHPPAState 234 * 235 * An HPPA CPU. 236 */ 237 struct HPPACPU { 238 /*< private >*/ 239 CPUState parent_obj; 240 /*< public >*/ 241 242 CPUHPPAState env; 243 QEMUTimer *alarm_timer; 244 }; 245 246 static inline HPPACPU *hppa_env_get_cpu(CPUHPPAState *env) 247 { 248 return container_of(env, HPPACPU, env); 249 } 250 251 #define ENV_GET_CPU(e) CPU(hppa_env_get_cpu(e)) 252 #define ENV_OFFSET offsetof(HPPACPU, env) 253 254 #include "exec/cpu-all.h" 255 256 static inline int cpu_mmu_index(CPUHPPAState *env, bool ifetch) 257 { 258 #ifdef CONFIG_USER_ONLY 259 return MMU_USER_IDX; 260 #else 261 if (env->psw & (ifetch ? PSW_C : PSW_D)) { 262 return env->iaoq_f & 3; 263 } 264 return MMU_PHYS_IDX; /* mmu disabled */ 265 #endif 266 } 267 268 void hppa_translate_init(void); 269 270 #define cpu_init(cpu_model) cpu_generic_init(TYPE_HPPA_CPU, cpu_model) 271 272 void hppa_cpu_list(FILE *f, fprintf_function cpu_fprintf); 273 274 static inline target_ulong hppa_form_gva_psw(target_ureg psw, uint64_t spc, 275 target_ureg off) 276 { 277 #ifdef CONFIG_USER_ONLY 278 return off; 279 #else 280 off &= (psw & PSW_W ? 0x3fffffffffffffffull : 0xffffffffull); 281 return spc | off; 282 #endif 283 } 284 285 static inline target_ulong hppa_form_gva(CPUHPPAState *env, uint64_t spc, 286 target_ureg off) 287 { 288 return hppa_form_gva_psw(env->psw, spc, off); 289 } 290 291 /* Since PSW_{I,CB} will never need to be in tb->flags, reuse them. 292 * TB_FLAG_SR_SAME indicates that SR4 through SR7 all contain the 293 * same value. 294 */ 295 #define TB_FLAG_SR_SAME PSW_I 296 #define TB_FLAG_PRIV_SHIFT 8 297 298 static inline void cpu_get_tb_cpu_state(CPUHPPAState *env, target_ulong *pc, 299 target_ulong *cs_base, 300 uint32_t *pflags) 301 { 302 uint32_t flags = env->psw_n * PSW_N; 303 304 /* TB lookup assumes that PC contains the complete virtual address. 305 If we leave space+offset separate, we'll get ITLB misses to an 306 incomplete virtual address. This also means that we must separate 307 out current cpu priviledge from the low bits of IAOQ_F. */ 308 #ifdef CONFIG_USER_ONLY 309 *pc = env->iaoq_f; 310 *cs_base = env->iaoq_b; 311 #else 312 /* ??? E, T, H, L, B, P bits need to be here, when implemented. */ 313 flags |= env->psw & (PSW_W | PSW_C | PSW_D); 314 flags |= (env->iaoq_f & 3) << TB_FLAG_PRIV_SHIFT; 315 316 *pc = (env->psw & PSW_C 317 ? hppa_form_gva_psw(env->psw, env->iasq_f, env->iaoq_f & -4) 318 : env->iaoq_f & -4); 319 *cs_base = env->iasq_f; 320 321 /* Insert a difference between IAOQ_B and IAOQ_F within the otherwise zero 322 low 32-bits of CS_BASE. This will succeed for all direct branches, 323 which is the primary case we care about -- using goto_tb within a page. 324 Failure is indicated by a zero difference. */ 325 if (env->iasq_f == env->iasq_b) { 326 target_sreg diff = env->iaoq_b - env->iaoq_f; 327 if (TARGET_REGISTER_BITS == 32 || diff == (int32_t)diff) { 328 *cs_base |= (uint32_t)diff; 329 } 330 } 331 if ((env->sr[4] == env->sr[5]) 332 & (env->sr[4] == env->sr[6]) 333 & (env->sr[4] == env->sr[7])) { 334 flags |= TB_FLAG_SR_SAME; 335 } 336 #endif 337 338 *pflags = flags; 339 } 340 341 target_ureg cpu_hppa_get_psw(CPUHPPAState *env); 342 void cpu_hppa_put_psw(CPUHPPAState *env, target_ureg); 343 void cpu_hppa_loaded_fr0(CPUHPPAState *env); 344 345 #define cpu_signal_handler cpu_hppa_signal_handler 346 347 int cpu_hppa_signal_handler(int host_signum, void *pinfo, void *puc); 348 hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr); 349 int hppa_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 350 int hppa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 351 void hppa_cpu_do_interrupt(CPUState *cpu); 352 bool hppa_cpu_exec_interrupt(CPUState *cpu, int int_req); 353 void hppa_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function, int); 354 #ifdef CONFIG_USER_ONLY 355 int hppa_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, 356 int rw, int midx); 357 #else 358 int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, 359 int type, hwaddr *pphys, int *pprot); 360 extern const MemoryRegionOps hppa_io_eir_ops; 361 extern const struct VMStateDescription vmstate_hppa_cpu; 362 void hppa_cpu_alarm_timer(void *); 363 int hppa_artype_for_page(CPUHPPAState *env, target_ulong vaddr); 364 #endif 365 void QEMU_NORETURN hppa_dynamic_excp(CPUHPPAState *env, int excp, uintptr_t ra); 366 367 #endif /* HPPA_CPU_H */ 368