1 /* 2 * PA-RISC emulation cpu definitions for qemu. 3 * 4 * Copyright (c) 2016 Richard Henderson <rth@twiddle.net> 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef HPPA_CPU_H 21 #define HPPA_CPU_H 22 23 #include "cpu-qom.h" 24 #include "exec/cpu-defs.h" 25 #include "qemu/cpu-float.h" 26 #include "qemu/interval-tree.h" 27 28 /* PA-RISC 1.x processors have a strong memory model. */ 29 /* ??? While we do not yet implement PA-RISC 2.0, those processors have 30 a weak memory model, but with TLB bits that force ordering on a per-page 31 basis. It's probably easier to fall back to a strong memory model. */ 32 #define TCG_GUEST_DEFAULT_MO TCG_MO_ALL 33 34 #define MMU_ABS_W_IDX 6 35 #define MMU_ABS_IDX 7 36 #define MMU_KERNEL_IDX 8 37 #define MMU_KERNEL_P_IDX 9 38 #define MMU_PL1_IDX 10 39 #define MMU_PL1_P_IDX 11 40 #define MMU_PL2_IDX 12 41 #define MMU_PL2_P_IDX 13 42 #define MMU_USER_IDX 14 43 #define MMU_USER_P_IDX 15 44 45 #define MMU_IDX_MMU_DISABLED(MIDX) ((MIDX) < MMU_KERNEL_IDX) 46 #define MMU_IDX_TO_PRIV(MIDX) (((MIDX) - MMU_KERNEL_IDX) / 2) 47 #define MMU_IDX_TO_P(MIDX) (((MIDX) - MMU_KERNEL_IDX) & 1) 48 #define PRIV_P_TO_MMU_IDX(PRIV, P) ((PRIV) * 2 + !!(P) + MMU_KERNEL_IDX) 49 50 #define TARGET_INSN_START_EXTRA_WORDS 2 51 52 /* No need to flush MMU_ABS*_IDX */ 53 #define HPPA_MMU_FLUSH_MASK \ 54 (1 << MMU_KERNEL_IDX | 1 << MMU_KERNEL_P_IDX | \ 55 1 << MMU_PL1_IDX | 1 << MMU_PL1_P_IDX | \ 56 1 << MMU_PL2_IDX | 1 << MMU_PL2_P_IDX | \ 57 1 << MMU_USER_IDX | 1 << MMU_USER_P_IDX) 58 59 /* Indicies to flush for access_id changes. */ 60 #define HPPA_MMU_FLUSH_P_MASK \ 61 (1 << MMU_KERNEL_P_IDX | 1 << MMU_PL1_P_IDX | \ 62 1 << MMU_PL2_P_IDX | 1 << MMU_USER_P_IDX) 63 64 /* Hardware exceptions, interrupts, faults, and traps. */ 65 #define EXCP_HPMC 1 /* high priority machine check */ 66 #define EXCP_POWER_FAIL 2 67 #define EXCP_RC 3 /* recovery counter */ 68 #define EXCP_EXT_INTERRUPT 4 /* external interrupt */ 69 #define EXCP_LPMC 5 /* low priority machine check */ 70 #define EXCP_ITLB_MISS 6 /* itlb miss / instruction page fault */ 71 #define EXCP_IMP 7 /* instruction memory protection trap */ 72 #define EXCP_ILL 8 /* illegal instruction trap */ 73 #define EXCP_BREAK 9 /* break instruction */ 74 #define EXCP_PRIV_OPR 10 /* privileged operation trap */ 75 #define EXCP_PRIV_REG 11 /* privileged register trap */ 76 #define EXCP_OVERFLOW 12 /* signed overflow trap */ 77 #define EXCP_COND 13 /* trap-on-condition */ 78 #define EXCP_ASSIST 14 /* assist exception trap */ 79 #define EXCP_DTLB_MISS 15 /* dtlb miss / data page fault */ 80 #define EXCP_NA_ITLB_MISS 16 /* non-access itlb miss */ 81 #define EXCP_NA_DTLB_MISS 17 /* non-access dtlb miss */ 82 #define EXCP_DMP 18 /* data memory protection trap */ 83 #define EXCP_DMB 19 /* data memory break trap */ 84 #define EXCP_TLB_DIRTY 20 /* tlb dirty bit trap */ 85 #define EXCP_PAGE_REF 21 /* page reference trap */ 86 #define EXCP_ASSIST_EMU 22 /* assist emulation trap */ 87 #define EXCP_HPT 23 /* high-privilege transfer trap */ 88 #define EXCP_LPT 24 /* low-privilege transfer trap */ 89 #define EXCP_TB 25 /* taken branch trap */ 90 #define EXCP_DMAR 26 /* data memory access rights trap */ 91 #define EXCP_DMPI 27 /* data memory protection id trap */ 92 #define EXCP_UNALIGN 28 /* unaligned data reference trap */ 93 #define EXCP_PER_INTERRUPT 29 /* performance monitor interrupt */ 94 95 /* Exceptions for linux-user emulation. */ 96 #define EXCP_SYSCALL 30 97 #define EXCP_SYSCALL_LWS 31 98 99 /* Emulated hardware TOC button */ 100 #define EXCP_TOC 32 /* TOC = Transfer of control (NMI) */ 101 102 #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3 /* TOC */ 103 104 /* Taken from Linux kernel: arch/parisc/include/asm/psw.h */ 105 #define PSW_I 0x00000001 106 #define PSW_D 0x00000002 107 #define PSW_P 0x00000004 108 #define PSW_Q 0x00000008 109 #define PSW_R 0x00000010 110 #define PSW_F 0x00000020 111 #define PSW_G 0x00000040 /* PA1.x only */ 112 #define PSW_O 0x00000080 /* PA2.0 only */ 113 #define PSW_CB 0x0000ff00 114 #define PSW_M 0x00010000 115 #define PSW_V 0x00020000 116 #define PSW_C 0x00040000 117 #define PSW_B 0x00080000 118 #define PSW_X 0x00100000 119 #define PSW_N 0x00200000 120 #define PSW_L 0x00400000 121 #define PSW_H 0x00800000 122 #define PSW_T 0x01000000 123 #define PSW_S 0x02000000 124 #define PSW_E 0x04000000 125 #define PSW_W 0x08000000 /* PA2.0 only */ 126 #define PSW_Z 0x40000000 /* PA1.x only */ 127 #define PSW_Y 0x80000000 /* PA1.x only */ 128 129 #define PSW_SM (PSW_W | PSW_E | PSW_O | PSW_G | PSW_F \ 130 | PSW_R | PSW_Q | PSW_P | PSW_D | PSW_I) 131 132 /* ssm/rsm instructions number PSW_W and PSW_E differently */ 133 #define PSW_SM_I PSW_I /* Enable External Interrupts */ 134 #define PSW_SM_D PSW_D 135 #define PSW_SM_P PSW_P 136 #define PSW_SM_Q PSW_Q /* Enable Interrupt State Collection */ 137 #define PSW_SM_R PSW_R /* Enable Recover Counter Trap */ 138 #define PSW_SM_E 0x100 139 #define PSW_SM_W 0x200 /* PA2.0 only : Enable Wide Mode */ 140 141 #define CR_RC 0 142 #define CR_PSW_DEFAULT 6 /* see SeaBIOS PDC_PSW firmware call */ 143 #define PDC_PSW_WIDE_BIT 2 144 #define CR_PID1 8 145 #define CR_PID2 9 146 #define CR_PID3 12 147 #define CR_PID4 13 148 #define CR_SCRCCR 10 149 #define CR_SAR 11 150 #define CR_IVA 14 151 #define CR_EIEM 15 152 #define CR_IT 16 153 #define CR_IIASQ 17 154 #define CR_IIAOQ 18 155 #define CR_IIR 19 156 #define CR_ISR 20 157 #define CR_IOR 21 158 #define CR_IPSW 22 159 #define CR_EIRR 23 160 161 typedef struct HPPATLBEntry { 162 union { 163 IntervalTreeNode itree; 164 struct HPPATLBEntry *unused_next; 165 }; 166 167 target_ulong pa; 168 169 unsigned entry_valid : 1; 170 171 unsigned u : 1; 172 unsigned t : 1; 173 unsigned d : 1; 174 unsigned b : 1; 175 unsigned ar_type : 3; 176 unsigned ar_pl1 : 2; 177 unsigned ar_pl2 : 2; 178 unsigned access_id : 16; 179 } HPPATLBEntry; 180 181 typedef struct CPUArchState { 182 target_ulong iaoq_f; /* front */ 183 target_ulong iaoq_b; /* back, aka next instruction */ 184 185 target_ulong gr[32]; 186 uint64_t fr[32]; 187 uint64_t sr[8]; /* stored shifted into place for gva */ 188 189 target_ulong psw; /* All psw bits except the following: */ 190 target_ulong psw_n; /* boolean */ 191 target_long psw_v; /* in most significant bit */ 192 193 /* Splitting the carry-borrow field into the MSB and "the rest", allows 194 * for "the rest" to be deleted when it is unused, but the MSB is in use. 195 * In addition, it's easier to compute carry-in for bit B+1 than it is to 196 * compute carry-out for bit B (3 vs 4 insns for addition, assuming the 197 * host has the appropriate add-with-carry insn to compute the msb). 198 * Therefore the carry bits are stored as: cb_msb : cb & 0x11111110. 199 */ 200 target_ulong psw_cb; /* in least significant bit of next nibble */ 201 target_ulong psw_cb_msb; /* boolean */ 202 203 uint64_t iasq_f; 204 uint64_t iasq_b; 205 206 uint32_t fr0_shadow; /* flags, c, ca/cq, rm, d, enables */ 207 float_status fp_status; 208 209 target_ulong cr[32]; /* control registers */ 210 target_ulong cr_back[2]; /* back of cr17/cr18 */ 211 target_ulong shadow[7]; /* shadow registers */ 212 213 /* 214 * During unwind of a memory insn, the base register of the address. 215 * This is used to construct CR_IOR for pa2.0. 216 */ 217 uint32_t unwind_breg; 218 219 /* 220 * ??? The number of entries isn't specified by the architecture. 221 * BTLBs are not supported in 64-bit machines. 222 */ 223 #define PA10_BTLB_FIXED 16 224 #define PA10_BTLB_VARIABLE 0 225 #define HPPA_TLB_ENTRIES 256 226 227 /* Index for round-robin tlb eviction. */ 228 uint32_t tlb_last; 229 230 /* 231 * For pa1.x, the partial initialized, still invalid tlb entry 232 * which has had ITLBA performed, but not yet ITLBP. 233 */ 234 HPPATLBEntry *tlb_partial; 235 236 /* Linked list of all invalid (unused) tlb entries. */ 237 HPPATLBEntry *tlb_unused; 238 239 /* Root of the search tree for all valid tlb entries. */ 240 IntervalTreeRoot tlb_root; 241 242 HPPATLBEntry tlb[HPPA_TLB_ENTRIES]; 243 } CPUHPPAState; 244 245 /** 246 * HPPACPU: 247 * @env: #CPUHPPAState 248 * 249 * An HPPA CPU. 250 */ 251 struct ArchCPU { 252 CPUState parent_obj; 253 254 CPUHPPAState env; 255 QEMUTimer *alarm_timer; 256 }; 257 258 /** 259 * HPPACPUClass: 260 * @parent_realize: The parent class' realize handler. 261 * @parent_reset: The parent class' reset handler. 262 * 263 * An HPPA CPU model. 264 */ 265 struct HPPACPUClass { 266 CPUClass parent_class; 267 268 DeviceRealize parent_realize; 269 DeviceReset parent_reset; 270 }; 271 272 #include "exec/cpu-all.h" 273 274 static inline bool hppa_is_pa20(CPUHPPAState *env) 275 { 276 return object_dynamic_cast(OBJECT(env_cpu(env)), TYPE_HPPA64_CPU) != NULL; 277 } 278 279 static inline int HPPA_BTLB_ENTRIES(CPUHPPAState *env) 280 { 281 return hppa_is_pa20(env) ? 0 : PA10_BTLB_FIXED + PA10_BTLB_VARIABLE; 282 } 283 284 static inline int cpu_mmu_index(CPUHPPAState *env, bool ifetch) 285 { 286 #ifdef CONFIG_USER_ONLY 287 return MMU_USER_IDX; 288 #else 289 if (env->psw & (ifetch ? PSW_C : PSW_D)) { 290 return PRIV_P_TO_MMU_IDX(env->iaoq_f & 3, env->psw & PSW_P); 291 } 292 /* mmu disabled */ 293 return env->psw & PSW_W ? MMU_ABS_W_IDX : MMU_ABS_IDX; 294 #endif 295 } 296 297 void hppa_translate_init(void); 298 299 #define CPU_RESOLVING_TYPE TYPE_HPPA_CPU 300 301 static inline target_ulong hppa_form_gva_psw(target_ulong psw, uint64_t spc, 302 target_ulong off) 303 { 304 #ifdef CONFIG_USER_ONLY 305 return off; 306 #else 307 off &= psw & PSW_W ? MAKE_64BIT_MASK(0, 62) : MAKE_64BIT_MASK(0, 32); 308 return spc | off; 309 #endif 310 } 311 312 static inline target_ulong hppa_form_gva(CPUHPPAState *env, uint64_t spc, 313 target_ulong off) 314 { 315 return hppa_form_gva_psw(env->psw, spc, off); 316 } 317 318 hwaddr hppa_abs_to_phys_pa2_w0(vaddr addr); 319 hwaddr hppa_abs_to_phys_pa2_w1(vaddr addr); 320 321 /* 322 * Since PSW_{I,CB} will never need to be in tb->flags, reuse them. 323 * TB_FLAG_SR_SAME indicates that SR4 through SR7 all contain the 324 * same value. 325 */ 326 #define TB_FLAG_SR_SAME PSW_I 327 #define TB_FLAG_PRIV_SHIFT 8 328 #define TB_FLAG_UNALIGN 0x400 329 330 static inline void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc, 331 uint64_t *cs_base, uint32_t *pflags) 332 { 333 uint32_t flags = env->psw_n * PSW_N; 334 335 /* TB lookup assumes that PC contains the complete virtual address. 336 If we leave space+offset separate, we'll get ITLB misses to an 337 incomplete virtual address. This also means that we must separate 338 out current cpu privilege from the low bits of IAOQ_F. */ 339 #ifdef CONFIG_USER_ONLY 340 *pc = env->iaoq_f & -4; 341 *cs_base = env->iaoq_b & -4; 342 flags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; 343 #else 344 /* ??? E, T, H, L, B bits need to be here, when implemented. */ 345 flags |= env->psw & (PSW_W | PSW_C | PSW_D | PSW_P); 346 flags |= (env->iaoq_f & 3) << TB_FLAG_PRIV_SHIFT; 347 348 *pc = hppa_form_gva_psw(env->psw, (env->psw & PSW_C ? env->iasq_f : 0), 349 env->iaoq_f & -4); 350 *cs_base = env->iasq_f; 351 352 /* Insert a difference between IAOQ_B and IAOQ_F within the otherwise zero 353 low 32-bits of CS_BASE. This will succeed for all direct branches, 354 which is the primary case we care about -- using goto_tb within a page. 355 Failure is indicated by a zero difference. */ 356 if (env->iasq_f == env->iasq_b) { 357 target_long diff = env->iaoq_b - env->iaoq_f; 358 if (diff == (int32_t)diff) { 359 *cs_base |= (uint32_t)diff; 360 } 361 } 362 if ((env->sr[4] == env->sr[5]) 363 & (env->sr[4] == env->sr[6]) 364 & (env->sr[4] == env->sr[7])) { 365 flags |= TB_FLAG_SR_SAME; 366 } 367 #endif 368 369 *pflags = flags; 370 } 371 372 target_ulong cpu_hppa_get_psw(CPUHPPAState *env); 373 void cpu_hppa_put_psw(CPUHPPAState *env, target_ulong); 374 void cpu_hppa_loaded_fr0(CPUHPPAState *env); 375 376 #ifdef CONFIG_USER_ONLY 377 static inline void cpu_hppa_change_prot_id(CPUHPPAState *env) { } 378 #else 379 void cpu_hppa_change_prot_id(CPUHPPAState *env); 380 #endif 381 382 int hppa_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 383 int hppa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 384 void hppa_cpu_dump_state(CPUState *cs, FILE *f, int); 385 #ifndef CONFIG_USER_ONLY 386 void hppa_ptlbe(CPUHPPAState *env); 387 hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr); 388 bool hppa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 389 MMUAccessType access_type, int mmu_idx, 390 bool probe, uintptr_t retaddr); 391 void hppa_cpu_do_interrupt(CPUState *cpu); 392 bool hppa_cpu_exec_interrupt(CPUState *cpu, int int_req); 393 int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, 394 int type, hwaddr *pphys, int *pprot, 395 HPPATLBEntry **tlb_entry); 396 extern const MemoryRegionOps hppa_io_eir_ops; 397 extern const VMStateDescription vmstate_hppa_cpu; 398 void hppa_cpu_alarm_timer(void *); 399 int hppa_artype_for_page(CPUHPPAState *env, target_ulong vaddr); 400 #endif 401 G_NORETURN void hppa_dynamic_excp(CPUHPPAState *env, int excp, uintptr_t ra); 402 403 #define CPU_RESOLVING_TYPE TYPE_HPPA_CPU 404 405 #define cpu_list hppa_cpu_list 406 void hppa_cpu_list(void); 407 408 #endif /* HPPA_CPU_H */ 409