1 /* 2 * PA-RISC emulation cpu definitions for qemu. 3 * 4 * Copyright (c) 2016 Richard Henderson <rth@twiddle.net> 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef HPPA_CPU_H 21 #define HPPA_CPU_H 22 23 #include "cpu-qom.h" 24 #include "exec/cpu-defs.h" 25 #include "qemu/cpu-float.h" 26 27 /* PA-RISC 1.x processors have a strong memory model. */ 28 /* ??? While we do not yet implement PA-RISC 2.0, those processors have 29 a weak memory model, but with TLB bits that force ordering on a per-page 30 basis. It's probably easier to fall back to a strong memory model. */ 31 #define TCG_GUEST_DEFAULT_MO TCG_MO_ALL 32 33 #define MMU_KERNEL_IDX 0 34 #define MMU_USER_IDX 3 35 #define MMU_PHYS_IDX 4 36 #define TARGET_INSN_START_EXTRA_WORDS 1 37 38 /* Hardware exceptions, interupts, faults, and traps. */ 39 #define EXCP_HPMC 1 /* high priority machine check */ 40 #define EXCP_POWER_FAIL 2 41 #define EXCP_RC 3 /* recovery counter */ 42 #define EXCP_EXT_INTERRUPT 4 /* external interrupt */ 43 #define EXCP_LPMC 5 /* low priority machine check */ 44 #define EXCP_ITLB_MISS 6 /* itlb miss / instruction page fault */ 45 #define EXCP_IMP 7 /* instruction memory protection trap */ 46 #define EXCP_ILL 8 /* illegal instruction trap */ 47 #define EXCP_BREAK 9 /* break instruction */ 48 #define EXCP_PRIV_OPR 10 /* privileged operation trap */ 49 #define EXCP_PRIV_REG 11 /* privileged register trap */ 50 #define EXCP_OVERFLOW 12 /* signed overflow trap */ 51 #define EXCP_COND 13 /* trap-on-condition */ 52 #define EXCP_ASSIST 14 /* assist exception trap */ 53 #define EXCP_DTLB_MISS 15 /* dtlb miss / data page fault */ 54 #define EXCP_NA_ITLB_MISS 16 /* non-access itlb miss */ 55 #define EXCP_NA_DTLB_MISS 17 /* non-access dtlb miss */ 56 #define EXCP_DMP 18 /* data memory protection trap */ 57 #define EXCP_DMB 19 /* data memory break trap */ 58 #define EXCP_TLB_DIRTY 20 /* tlb dirty bit trap */ 59 #define EXCP_PAGE_REF 21 /* page reference trap */ 60 #define EXCP_ASSIST_EMU 22 /* assist emulation trap */ 61 #define EXCP_HPT 23 /* high-privilege transfer trap */ 62 #define EXCP_LPT 24 /* low-privilege transfer trap */ 63 #define EXCP_TB 25 /* taken branch trap */ 64 #define EXCP_DMAR 26 /* data memory access rights trap */ 65 #define EXCP_DMPI 27 /* data memory protection id trap */ 66 #define EXCP_UNALIGN 28 /* unaligned data reference trap */ 67 #define EXCP_PER_INTERRUPT 29 /* performance monitor interrupt */ 68 69 /* Exceptions for linux-user emulation. */ 70 #define EXCP_SYSCALL 30 71 #define EXCP_SYSCALL_LWS 31 72 73 /* Emulated hardware TOC button */ 74 #define EXCP_TOC 32 /* TOC = Transfer of control (NMI) */ 75 76 #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3 /* TOC */ 77 78 /* Taken from Linux kernel: arch/parisc/include/asm/psw.h */ 79 #define PSW_I 0x00000001 80 #define PSW_D 0x00000002 81 #define PSW_P 0x00000004 82 #define PSW_Q 0x00000008 83 #define PSW_R 0x00000010 84 #define PSW_F 0x00000020 85 #define PSW_G 0x00000040 /* PA1.x only */ 86 #define PSW_O 0x00000080 /* PA2.0 only */ 87 #define PSW_CB 0x0000ff00 88 #define PSW_M 0x00010000 89 #define PSW_V 0x00020000 90 #define PSW_C 0x00040000 91 #define PSW_B 0x00080000 92 #define PSW_X 0x00100000 93 #define PSW_N 0x00200000 94 #define PSW_L 0x00400000 95 #define PSW_H 0x00800000 96 #define PSW_T 0x01000000 97 #define PSW_S 0x02000000 98 #define PSW_E 0x04000000 99 #ifdef TARGET_HPPA64 100 #define PSW_W 0x08000000 /* PA2.0 only */ 101 #else 102 #define PSW_W 0 103 #endif 104 #define PSW_Z 0x40000000 /* PA1.x only */ 105 #define PSW_Y 0x80000000 /* PA1.x only */ 106 107 #define PSW_SM (PSW_W | PSW_E | PSW_O | PSW_G | PSW_F \ 108 | PSW_R | PSW_Q | PSW_P | PSW_D | PSW_I) 109 110 /* ssm/rsm instructions number PSW_W and PSW_E differently */ 111 #define PSW_SM_I PSW_I /* Enable External Interrupts */ 112 #define PSW_SM_D PSW_D 113 #define PSW_SM_P PSW_P 114 #define PSW_SM_Q PSW_Q /* Enable Interrupt State Collection */ 115 #define PSW_SM_R PSW_R /* Enable Recover Counter Trap */ 116 #ifdef TARGET_HPPA64 117 #define PSW_SM_E 0x100 118 #define PSW_SM_W 0x200 /* PA2.0 only : Enable Wide Mode */ 119 #else 120 #define PSW_SM_E 0 121 #define PSW_SM_W 0 122 #endif 123 124 #define CR_RC 0 125 #define CR_PID1 8 126 #define CR_PID2 9 127 #define CR_PID3 12 128 #define CR_PID4 13 129 #define CR_SCRCCR 10 130 #define CR_SAR 11 131 #define CR_IVA 14 132 #define CR_EIEM 15 133 #define CR_IT 16 134 #define CR_IIASQ 17 135 #define CR_IIAOQ 18 136 #define CR_IIR 19 137 #define CR_ISR 20 138 #define CR_IOR 21 139 #define CR_IPSW 22 140 #define CR_EIRR 23 141 142 #if TARGET_REGISTER_BITS == 32 143 typedef uint32_t target_ureg; 144 typedef int32_t target_sreg; 145 #define TREG_FMT_lx "%08"PRIx32 146 #define TREG_FMT_ld "%"PRId32 147 #else 148 typedef uint64_t target_ureg; 149 typedef int64_t target_sreg; 150 #define TREG_FMT_lx "%016"PRIx64 151 #define TREG_FMT_ld "%"PRId64 152 #endif 153 154 typedef struct { 155 uint64_t va_b; 156 uint64_t va_e; 157 target_ureg pa; 158 unsigned u : 1; 159 unsigned t : 1; 160 unsigned d : 1; 161 unsigned b : 1; 162 unsigned page_size : 4; 163 unsigned ar_type : 3; 164 unsigned ar_pl1 : 2; 165 unsigned ar_pl2 : 2; 166 unsigned entry_valid : 1; 167 unsigned access_id : 16; 168 } hppa_tlb_entry; 169 170 typedef struct CPUArchState { 171 target_ureg gr[32]; 172 uint64_t fr[32]; 173 uint64_t sr[8]; /* stored shifted into place for gva */ 174 175 target_ureg psw; /* All psw bits except the following: */ 176 target_ureg psw_n; /* boolean */ 177 target_sreg psw_v; /* in most significant bit */ 178 179 /* Splitting the carry-borrow field into the MSB and "the rest", allows 180 * for "the rest" to be deleted when it is unused, but the MSB is in use. 181 * In addition, it's easier to compute carry-in for bit B+1 than it is to 182 * compute carry-out for bit B (3 vs 4 insns for addition, assuming the 183 * host has the appropriate add-with-carry insn to compute the msb). 184 * Therefore the carry bits are stored as: cb_msb : cb & 0x11111110. 185 */ 186 target_ureg psw_cb; /* in least significant bit of next nibble */ 187 target_ureg psw_cb_msb; /* boolean */ 188 189 target_ureg iaoq_f; /* front */ 190 target_ureg iaoq_b; /* back, aka next instruction */ 191 uint64_t iasq_f; 192 uint64_t iasq_b; 193 194 uint32_t fr0_shadow; /* flags, c, ca/cq, rm, d, enables */ 195 float_status fp_status; 196 197 target_ureg cr[32]; /* control registers */ 198 target_ureg cr_back[2]; /* back of cr17/cr18 */ 199 target_ureg shadow[7]; /* shadow registers */ 200 201 /* ??? The number of entries isn't specified by the architecture. */ 202 #define HPPA_TLB_ENTRIES 256 203 #define HPPA_BTLB_ENTRIES 0 204 205 /* ??? Implement a unified itlb/dtlb for the moment. */ 206 /* ??? We should use a more intelligent data structure. */ 207 hppa_tlb_entry tlb[HPPA_TLB_ENTRIES]; 208 uint32_t tlb_last; 209 } CPUHPPAState; 210 211 /** 212 * HPPACPU: 213 * @env: #CPUHPPAState 214 * 215 * An HPPA CPU. 216 */ 217 struct ArchCPU { 218 /*< private >*/ 219 CPUState parent_obj; 220 /*< public >*/ 221 222 CPUNegativeOffsetState neg; 223 CPUHPPAState env; 224 QEMUTimer *alarm_timer; 225 }; 226 227 #include "exec/cpu-all.h" 228 229 static inline int cpu_mmu_index(CPUHPPAState *env, bool ifetch) 230 { 231 #ifdef CONFIG_USER_ONLY 232 return MMU_USER_IDX; 233 #else 234 if (env->psw & (ifetch ? PSW_C : PSW_D)) { 235 return env->iaoq_f & 3; 236 } 237 return MMU_PHYS_IDX; /* mmu disabled */ 238 #endif 239 } 240 241 void hppa_translate_init(void); 242 243 #define CPU_RESOLVING_TYPE TYPE_HPPA_CPU 244 245 static inline target_ulong hppa_form_gva_psw(target_ureg psw, uint64_t spc, 246 target_ureg off) 247 { 248 #ifdef CONFIG_USER_ONLY 249 return off; 250 #else 251 off &= (psw & PSW_W ? 0x3fffffffffffffffull : 0xffffffffull); 252 return spc | off; 253 #endif 254 } 255 256 static inline target_ulong hppa_form_gva(CPUHPPAState *env, uint64_t spc, 257 target_ureg off) 258 { 259 return hppa_form_gva_psw(env->psw, spc, off); 260 } 261 262 /* 263 * Since PSW_{I,CB} will never need to be in tb->flags, reuse them. 264 * TB_FLAG_SR_SAME indicates that SR4 through SR7 all contain the 265 * same value. 266 */ 267 #define TB_FLAG_SR_SAME PSW_I 268 #define TB_FLAG_PRIV_SHIFT 8 269 #define TB_FLAG_UNALIGN 0x400 270 271 static inline void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc, 272 uint64_t *cs_base, uint32_t *pflags) 273 { 274 uint32_t flags = env->psw_n * PSW_N; 275 276 /* TB lookup assumes that PC contains the complete virtual address. 277 If we leave space+offset separate, we'll get ITLB misses to an 278 incomplete virtual address. This also means that we must separate 279 out current cpu priviledge from the low bits of IAOQ_F. */ 280 #ifdef CONFIG_USER_ONLY 281 *pc = env->iaoq_f & -4; 282 *cs_base = env->iaoq_b & -4; 283 flags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; 284 #else 285 /* ??? E, T, H, L, B, P bits need to be here, when implemented. */ 286 flags |= env->psw & (PSW_W | PSW_C | PSW_D); 287 flags |= (env->iaoq_f & 3) << TB_FLAG_PRIV_SHIFT; 288 289 *pc = (env->psw & PSW_C 290 ? hppa_form_gva_psw(env->psw, env->iasq_f, env->iaoq_f & -4) 291 : env->iaoq_f & -4); 292 *cs_base = env->iasq_f; 293 294 /* Insert a difference between IAOQ_B and IAOQ_F within the otherwise zero 295 low 32-bits of CS_BASE. This will succeed for all direct branches, 296 which is the primary case we care about -- using goto_tb within a page. 297 Failure is indicated by a zero difference. */ 298 if (env->iasq_f == env->iasq_b) { 299 target_sreg diff = env->iaoq_b - env->iaoq_f; 300 if (TARGET_REGISTER_BITS == 32 || diff == (int32_t)diff) { 301 *cs_base |= (uint32_t)diff; 302 } 303 } 304 if ((env->sr[4] == env->sr[5]) 305 & (env->sr[4] == env->sr[6]) 306 & (env->sr[4] == env->sr[7])) { 307 flags |= TB_FLAG_SR_SAME; 308 } 309 #endif 310 311 *pflags = flags; 312 } 313 314 target_ureg cpu_hppa_get_psw(CPUHPPAState *env); 315 void cpu_hppa_put_psw(CPUHPPAState *env, target_ureg); 316 void cpu_hppa_loaded_fr0(CPUHPPAState *env); 317 318 #ifdef CONFIG_USER_ONLY 319 static inline void cpu_hppa_change_prot_id(CPUHPPAState *env) { } 320 #else 321 void cpu_hppa_change_prot_id(CPUHPPAState *env); 322 #endif 323 324 int hppa_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 325 int hppa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 326 void hppa_cpu_dump_state(CPUState *cs, FILE *f, int); 327 #ifndef CONFIG_USER_ONLY 328 hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr); 329 bool hppa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 330 MMUAccessType access_type, int mmu_idx, 331 bool probe, uintptr_t retaddr); 332 void hppa_cpu_do_interrupt(CPUState *cpu); 333 bool hppa_cpu_exec_interrupt(CPUState *cpu, int int_req); 334 int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, 335 int type, hwaddr *pphys, int *pprot); 336 extern const MemoryRegionOps hppa_io_eir_ops; 337 extern const VMStateDescription vmstate_hppa_cpu; 338 void hppa_cpu_alarm_timer(void *); 339 int hppa_artype_for_page(CPUHPPAState *env, target_ulong vaddr); 340 #endif 341 G_NORETURN void hppa_dynamic_excp(CPUHPPAState *env, int excp, uintptr_t ra); 342 343 #endif /* HPPA_CPU_H */ 344