1 /* 2 * PA-RISC emulation cpu definitions for qemu. 3 * 4 * Copyright (c) 2016 Richard Henderson <rth@twiddle.net> 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef HPPA_CPU_H 21 #define HPPA_CPU_H 22 23 #include "cpu-qom.h" 24 #include "exec/cpu-defs.h" 25 #include "qemu/cpu-float.h" 26 #include "qemu/interval-tree.h" 27 28 #define MMU_ABS_W_IDX 6 29 #define MMU_ABS_IDX 7 30 #define MMU_KERNEL_IDX 8 31 #define MMU_KERNEL_P_IDX 9 32 #define MMU_PL1_IDX 10 33 #define MMU_PL1_P_IDX 11 34 #define MMU_PL2_IDX 12 35 #define MMU_PL2_P_IDX 13 36 #define MMU_USER_IDX 14 37 #define MMU_USER_P_IDX 15 38 39 #define MMU_IDX_MMU_DISABLED(MIDX) ((MIDX) < MMU_KERNEL_IDX) 40 #define MMU_IDX_TO_PRIV(MIDX) (((MIDX) - MMU_KERNEL_IDX) / 2) 41 #define MMU_IDX_TO_P(MIDX) (((MIDX) - MMU_KERNEL_IDX) & 1) 42 #define PRIV_P_TO_MMU_IDX(PRIV, P) ((PRIV) * 2 + !!(P) + MMU_KERNEL_IDX) 43 44 #define TARGET_INSN_START_EXTRA_WORDS 2 45 46 /* No need to flush MMU_ABS*_IDX */ 47 #define HPPA_MMU_FLUSH_MASK \ 48 (1 << MMU_KERNEL_IDX | 1 << MMU_KERNEL_P_IDX | \ 49 1 << MMU_PL1_IDX | 1 << MMU_PL1_P_IDX | \ 50 1 << MMU_PL2_IDX | 1 << MMU_PL2_P_IDX | \ 51 1 << MMU_USER_IDX | 1 << MMU_USER_P_IDX) 52 53 /* Indices to flush for access_id changes. */ 54 #define HPPA_MMU_FLUSH_P_MASK \ 55 (1 << MMU_KERNEL_P_IDX | 1 << MMU_PL1_P_IDX | \ 56 1 << MMU_PL2_P_IDX | 1 << MMU_USER_P_IDX) 57 58 /* Hardware exceptions, interrupts, faults, and traps. */ 59 #define EXCP_HPMC 1 /* high priority machine check */ 60 #define EXCP_POWER_FAIL 2 61 #define EXCP_RC 3 /* recovery counter */ 62 #define EXCP_EXT_INTERRUPT 4 /* external interrupt */ 63 #define EXCP_LPMC 5 /* low priority machine check */ 64 #define EXCP_ITLB_MISS 6 /* itlb miss / instruction page fault */ 65 #define EXCP_IMP 7 /* instruction memory protection trap */ 66 #define EXCP_ILL 8 /* illegal instruction trap */ 67 #define EXCP_BREAK 9 /* break instruction */ 68 #define EXCP_PRIV_OPR 10 /* privileged operation trap */ 69 #define EXCP_PRIV_REG 11 /* privileged register trap */ 70 #define EXCP_OVERFLOW 12 /* signed overflow trap */ 71 #define EXCP_COND 13 /* trap-on-condition */ 72 #define EXCP_ASSIST 14 /* assist exception trap */ 73 #define EXCP_DTLB_MISS 15 /* dtlb miss / data page fault */ 74 #define EXCP_NA_ITLB_MISS 16 /* non-access itlb miss */ 75 #define EXCP_NA_DTLB_MISS 17 /* non-access dtlb miss */ 76 #define EXCP_DMP 18 /* data memory protection trap */ 77 #define EXCP_DMB 19 /* data memory break trap */ 78 #define EXCP_TLB_DIRTY 20 /* tlb dirty bit trap */ 79 #define EXCP_PAGE_REF 21 /* page reference trap */ 80 #define EXCP_ASSIST_EMU 22 /* assist emulation trap */ 81 #define EXCP_HPT 23 /* high-privilege transfer trap */ 82 #define EXCP_LPT 24 /* low-privilege transfer trap */ 83 #define EXCP_TB 25 /* taken branch trap */ 84 #define EXCP_DMAR 26 /* data memory access rights trap */ 85 #define EXCP_DMPI 27 /* data memory protection id trap */ 86 #define EXCP_UNALIGN 28 /* unaligned data reference trap */ 87 #define EXCP_PER_INTERRUPT 29 /* performance monitor interrupt */ 88 89 /* Exceptions for linux-user emulation. */ 90 #define EXCP_SYSCALL 30 91 #define EXCP_SYSCALL_LWS 31 92 93 /* Emulated hardware TOC button */ 94 #define EXCP_TOC 32 /* TOC = Transfer of control (NMI) */ 95 96 #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3 /* TOC */ 97 98 /* Taken from Linux kernel: arch/parisc/include/asm/psw.h */ 99 #define PSW_I 0x00000001 100 #define PSW_D 0x00000002 101 #define PSW_P 0x00000004 102 #define PSW_Q 0x00000008 103 #define PSW_R 0x00000010 104 #define PSW_F 0x00000020 105 #define PSW_G 0x00000040 /* PA1.x only */ 106 #define PSW_O 0x00000080 /* PA2.0 only */ 107 #define PSW_CB 0x0000ff00 108 #define PSW_M 0x00010000 109 #define PSW_V 0x00020000 110 #define PSW_C 0x00040000 111 #define PSW_B 0x00080000 112 #define PSW_X 0x00100000 113 #define PSW_N 0x00200000 114 #define PSW_L 0x00400000 115 #define PSW_H 0x00800000 116 #define PSW_T 0x01000000 117 #define PSW_S 0x02000000 118 #define PSW_E 0x04000000 119 #define PSW_W 0x08000000 /* PA2.0 only */ 120 #define PSW_Z 0x40000000 /* PA1.x only */ 121 #define PSW_Y 0x80000000 /* PA1.x only */ 122 123 #define PSW_SM (PSW_W | PSW_E | PSW_O | PSW_G | PSW_F \ 124 | PSW_R | PSW_Q | PSW_P | PSW_D | PSW_I) 125 126 /* ssm/rsm instructions number PSW_W and PSW_E differently */ 127 #define PSW_SM_I PSW_I /* Enable External Interrupts */ 128 #define PSW_SM_D PSW_D 129 #define PSW_SM_P PSW_P 130 #define PSW_SM_Q PSW_Q /* Enable Interrupt State Collection */ 131 #define PSW_SM_R PSW_R /* Enable Recover Counter Trap */ 132 #define PSW_SM_E 0x100 133 #define PSW_SM_W 0x200 /* PA2.0 only : Enable Wide Mode */ 134 135 #define CR_RC 0 136 #define CR_PSW_DEFAULT 6 /* see SeaBIOS PDC_PSW firmware call */ 137 #define PDC_PSW_WIDE_BIT 2 138 #define CR_PID1 8 139 #define CR_PID2 9 140 #define CR_PID3 12 141 #define CR_PID4 13 142 #define CR_SCRCCR 10 143 #define CR_SAR 11 144 #define CR_IVA 14 145 #define CR_EIEM 15 146 #define CR_IT 16 147 #define CR_IIASQ 17 148 #define CR_IIAOQ 18 149 #define CR_IIR 19 150 #define CR_ISR 20 151 #define CR_IOR 21 152 #define CR_IPSW 22 153 #define CR_EIRR 23 154 155 typedef struct HPPATLBEntry { 156 union { 157 IntervalTreeNode itree; 158 struct HPPATLBEntry *unused_next; 159 }; 160 161 target_ulong pa; 162 163 unsigned entry_valid : 1; 164 165 unsigned u : 1; 166 unsigned t : 1; 167 unsigned d : 1; 168 unsigned b : 1; 169 unsigned ar_type : 3; 170 unsigned ar_pl1 : 2; 171 unsigned ar_pl2 : 2; 172 unsigned access_id : 16; 173 } HPPATLBEntry; 174 175 typedef struct CPUArchState { 176 target_ulong iaoq_f; /* front */ 177 target_ulong iaoq_b; /* back, aka next instruction */ 178 179 target_ulong gr[32]; 180 uint64_t fr[32]; 181 uint64_t sr[8]; /* stored shifted into place for gva */ 182 183 target_ulong psw; /* All psw bits except the following: */ 184 target_ulong psw_n; /* boolean */ 185 target_long psw_v; /* in most significant bit */ 186 187 /* Splitting the carry-borrow field into the MSB and "the rest", allows 188 * for "the rest" to be deleted when it is unused, but the MSB is in use. 189 * In addition, it's easier to compute carry-in for bit B+1 than it is to 190 * compute carry-out for bit B (3 vs 4 insns for addition, assuming the 191 * host has the appropriate add-with-carry insn to compute the msb). 192 * Therefore the carry bits are stored as: cb_msb : cb & 0x11111110. 193 */ 194 target_ulong psw_cb; /* in least significant bit of next nibble */ 195 target_ulong psw_cb_msb; /* boolean */ 196 197 uint64_t iasq_f; 198 uint64_t iasq_b; 199 200 uint32_t fr0_shadow; /* flags, c, ca/cq, rm, d, enables */ 201 float_status fp_status; 202 203 target_ulong cr[32]; /* control registers */ 204 target_ulong cr_back[2]; /* back of cr17/cr18 */ 205 target_ulong shadow[7]; /* shadow registers */ 206 207 /* 208 * During unwind of a memory insn, the base register of the address. 209 * This is used to construct CR_IOR for pa2.0. 210 */ 211 uint32_t unwind_breg; 212 213 /* 214 * ??? The number of entries isn't specified by the architecture. 215 * BTLBs are not supported in 64-bit machines. 216 */ 217 #define PA10_BTLB_FIXED 16 218 #define PA10_BTLB_VARIABLE 0 219 #define HPPA_TLB_ENTRIES 256 220 221 /* Index for round-robin tlb eviction. */ 222 uint32_t tlb_last; 223 224 /* 225 * For pa1.x, the partial initialized, still invalid tlb entry 226 * which has had ITLBA performed, but not yet ITLBP. 227 */ 228 HPPATLBEntry *tlb_partial; 229 230 /* Linked list of all invalid (unused) tlb entries. */ 231 HPPATLBEntry *tlb_unused; 232 233 /* Root of the search tree for all valid tlb entries. */ 234 IntervalTreeRoot tlb_root; 235 236 HPPATLBEntry tlb[HPPA_TLB_ENTRIES]; 237 } CPUHPPAState; 238 239 /** 240 * HPPACPU: 241 * @env: #CPUHPPAState 242 * 243 * An HPPA CPU. 244 */ 245 struct ArchCPU { 246 CPUState parent_obj; 247 248 CPUHPPAState env; 249 QEMUTimer *alarm_timer; 250 }; 251 252 /** 253 * HPPACPUClass: 254 * @parent_realize: The parent class' realize handler. 255 * @parent_reset: The parent class' reset handler. 256 * 257 * An HPPA CPU model. 258 */ 259 struct HPPACPUClass { 260 CPUClass parent_class; 261 262 DeviceRealize parent_realize; 263 DeviceReset parent_reset; 264 }; 265 266 #include "exec/cpu-all.h" 267 268 static inline bool hppa_is_pa20(CPUHPPAState *env) 269 { 270 return object_dynamic_cast(OBJECT(env_cpu(env)), TYPE_HPPA64_CPU) != NULL; 271 } 272 273 static inline int HPPA_BTLB_ENTRIES(CPUHPPAState *env) 274 { 275 return hppa_is_pa20(env) ? 0 : PA10_BTLB_FIXED + PA10_BTLB_VARIABLE; 276 } 277 278 void hppa_translate_init(void); 279 280 #define CPU_RESOLVING_TYPE TYPE_HPPA_CPU 281 282 static inline uint64_t gva_offset_mask(target_ulong psw) 283 { 284 return (psw & PSW_W 285 ? MAKE_64BIT_MASK(0, 62) 286 : MAKE_64BIT_MASK(0, 32)); 287 } 288 289 static inline target_ulong hppa_form_gva_psw(target_ulong psw, uint64_t spc, 290 target_ulong off) 291 { 292 #ifdef CONFIG_USER_ONLY 293 return off; 294 #else 295 return spc | (off & gva_offset_mask(psw)); 296 #endif 297 } 298 299 static inline target_ulong hppa_form_gva(CPUHPPAState *env, uint64_t spc, 300 target_ulong off) 301 { 302 return hppa_form_gva_psw(env->psw, spc, off); 303 } 304 305 hwaddr hppa_abs_to_phys_pa2_w0(vaddr addr); 306 hwaddr hppa_abs_to_phys_pa2_w1(vaddr addr); 307 308 /* 309 * Since PSW_{I,CB} will never need to be in tb->flags, reuse them. 310 * TB_FLAG_SR_SAME indicates that SR4 through SR7 all contain the 311 * same value. 312 */ 313 #define TB_FLAG_SR_SAME PSW_I 314 #define TB_FLAG_PRIV_SHIFT 8 315 #define TB_FLAG_UNALIGN 0x400 316 317 static inline void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc, 318 uint64_t *cs_base, uint32_t *pflags) 319 { 320 uint32_t flags = env->psw_n * PSW_N; 321 322 /* TB lookup assumes that PC contains the complete virtual address. 323 If we leave space+offset separate, we'll get ITLB misses to an 324 incomplete virtual address. This also means that we must separate 325 out current cpu privilege from the low bits of IAOQ_F. */ 326 #ifdef CONFIG_USER_ONLY 327 *pc = env->iaoq_f & -4; 328 *cs_base = env->iaoq_b & -4; 329 flags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; 330 #else 331 /* ??? E, T, H, L, B bits need to be here, when implemented. */ 332 flags |= env->psw & (PSW_W | PSW_C | PSW_D | PSW_P); 333 flags |= (env->iaoq_f & 3) << TB_FLAG_PRIV_SHIFT; 334 335 *pc = hppa_form_gva_psw(env->psw, (env->psw & PSW_C ? env->iasq_f : 0), 336 env->iaoq_f & -4); 337 *cs_base = env->iasq_f; 338 339 /* Insert a difference between IAOQ_B and IAOQ_F within the otherwise zero 340 low 32-bits of CS_BASE. This will succeed for all direct branches, 341 which is the primary case we care about -- using goto_tb within a page. 342 Failure is indicated by a zero difference. */ 343 if (env->iasq_f == env->iasq_b) { 344 target_long diff = env->iaoq_b - env->iaoq_f; 345 if (diff == (int32_t)diff) { 346 *cs_base |= (uint32_t)diff; 347 } 348 } 349 if ((env->sr[4] == env->sr[5]) 350 & (env->sr[4] == env->sr[6]) 351 & (env->sr[4] == env->sr[7])) { 352 flags |= TB_FLAG_SR_SAME; 353 } 354 #endif 355 356 *pflags = flags; 357 } 358 359 target_ulong cpu_hppa_get_psw(CPUHPPAState *env); 360 void cpu_hppa_put_psw(CPUHPPAState *env, target_ulong); 361 void cpu_hppa_loaded_fr0(CPUHPPAState *env); 362 363 #ifdef CONFIG_USER_ONLY 364 static inline void cpu_hppa_change_prot_id(CPUHPPAState *env) { } 365 #else 366 void cpu_hppa_change_prot_id(CPUHPPAState *env); 367 #endif 368 369 int hppa_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 370 int hppa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 371 void hppa_cpu_dump_state(CPUState *cs, FILE *f, int); 372 #ifndef CONFIG_USER_ONLY 373 void hppa_ptlbe(CPUHPPAState *env); 374 hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr); 375 void hppa_set_ior_and_isr(CPUHPPAState *env, vaddr addr, bool mmu_disabled); 376 bool hppa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 377 MMUAccessType access_type, int mmu_idx, 378 bool probe, uintptr_t retaddr); 379 void hppa_cpu_do_interrupt(CPUState *cpu); 380 bool hppa_cpu_exec_interrupt(CPUState *cpu, int int_req); 381 int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, 382 int type, hwaddr *pphys, int *pprot, 383 HPPATLBEntry **tlb_entry); 384 void hppa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 385 vaddr addr, unsigned size, 386 MMUAccessType access_type, 387 int mmu_idx, MemTxAttrs attrs, 388 MemTxResult response, uintptr_t retaddr); 389 extern const MemoryRegionOps hppa_io_eir_ops; 390 extern const VMStateDescription vmstate_hppa_cpu; 391 void hppa_cpu_alarm_timer(void *); 392 int hppa_artype_for_page(CPUHPPAState *env, target_ulong vaddr); 393 #endif 394 G_NORETURN void hppa_dynamic_excp(CPUHPPAState *env, int excp, uintptr_t ra); 395 396 #define CPU_RESOLVING_TYPE TYPE_HPPA_CPU 397 398 #endif /* HPPA_CPU_H */ 399