1 /* 2 * PA-RISC emulation cpu definitions for qemu. 3 * 4 * Copyright (c) 2016 Richard Henderson <rth@twiddle.net> 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef HPPA_CPU_H 21 #define HPPA_CPU_H 22 23 #include "qemu-common.h" 24 #include "cpu-qom.h" 25 26 #ifdef TARGET_HPPA64 27 #define TARGET_LONG_BITS 64 28 #define TARGET_VIRT_ADDR_SPACE_BITS 64 29 #define TARGET_REGISTER_BITS 64 30 #define TARGET_PHYS_ADDR_SPACE_BITS 64 31 #elif defined(CONFIG_USER_ONLY) 32 #define TARGET_LONG_BITS 32 33 #define TARGET_VIRT_ADDR_SPACE_BITS 32 34 #define TARGET_REGISTER_BITS 32 35 #define TARGET_PHYS_ADDR_SPACE_BITS 32 36 #else 37 /* In order to form the GVA from space:offset, 38 we need a 64-bit virtual address space. */ 39 #define TARGET_LONG_BITS 64 40 #define TARGET_VIRT_ADDR_SPACE_BITS 64 41 #define TARGET_REGISTER_BITS 32 42 #define TARGET_PHYS_ADDR_SPACE_BITS 32 43 #endif 44 45 /* PA-RISC 1.x processors have a strong memory model. */ 46 /* ??? While we do not yet implement PA-RISC 2.0, those processors have 47 a weak memory model, but with TLB bits that force ordering on a per-page 48 basis. It's probably easier to fall back to a strong memory model. */ 49 #define TCG_GUEST_DEFAULT_MO TCG_MO_ALL 50 51 #define CPUArchState struct CPUHPPAState 52 53 #include "exec/cpu-defs.h" 54 55 #define TARGET_PAGE_BITS 12 56 57 #define ALIGNED_ONLY 58 #define NB_MMU_MODES 5 59 #define MMU_KERNEL_IDX 0 60 #define MMU_USER_IDX 3 61 #define MMU_PHYS_IDX 4 62 #define TARGET_INSN_START_EXTRA_WORDS 1 63 64 /* Hardware exceptions, interupts, faults, and traps. */ 65 #define EXCP_HPMC 1 /* high priority machine check */ 66 #define EXCP_POWER_FAIL 2 67 #define EXCP_RC 3 /* recovery counter */ 68 #define EXCP_EXT_INTERRUPT 4 /* external interrupt */ 69 #define EXCP_LPMC 5 /* low priority machine check */ 70 #define EXCP_ITLB_MISS 6 /* itlb miss / instruction page fault */ 71 #define EXCP_IMP 7 /* instruction memory protection trap */ 72 #define EXCP_ILL 8 /* illegal instruction trap */ 73 #define EXCP_BREAK 9 /* break instruction */ 74 #define EXCP_PRIV_OPR 10 /* privileged operation trap */ 75 #define EXCP_PRIV_REG 11 /* privileged register trap */ 76 #define EXCP_OVERFLOW 12 /* signed overflow trap */ 77 #define EXCP_COND 13 /* trap-on-condition */ 78 #define EXCP_ASSIST 14 /* assist exception trap */ 79 #define EXCP_DTLB_MISS 15 /* dtlb miss / data page fault */ 80 #define EXCP_NA_ITLB_MISS 16 /* non-access itlb miss */ 81 #define EXCP_NA_DTLB_MISS 17 /* non-access dtlb miss */ 82 #define EXCP_DMP 18 /* data memory protection trap */ 83 #define EXCP_DMB 19 /* data memory break trap */ 84 #define EXCP_TLB_DIRTY 20 /* tlb dirty bit trap */ 85 #define EXCP_PAGE_REF 21 /* page reference trap */ 86 #define EXCP_ASSIST_EMU 22 /* assist emulation trap */ 87 #define EXCP_HPT 23 /* high-privilege transfer trap */ 88 #define EXCP_LPT 24 /* low-privilege transfer trap */ 89 #define EXCP_TB 25 /* taken branch trap */ 90 #define EXCP_DMAR 26 /* data memory access rights trap */ 91 #define EXCP_DMPI 27 /* data memory protection id trap */ 92 #define EXCP_UNALIGN 28 /* unaligned data reference trap */ 93 #define EXCP_PER_INTERRUPT 29 /* performance monitor interrupt */ 94 95 /* Exceptions for linux-user emulation. */ 96 #define EXCP_SYSCALL 30 97 #define EXCP_SYSCALL_LWS 31 98 99 /* Taken from Linux kernel: arch/parisc/include/asm/psw.h */ 100 #define PSW_I 0x00000001 101 #define PSW_D 0x00000002 102 #define PSW_P 0x00000004 103 #define PSW_Q 0x00000008 104 #define PSW_R 0x00000010 105 #define PSW_F 0x00000020 106 #define PSW_G 0x00000040 /* PA1.x only */ 107 #define PSW_O 0x00000080 /* PA2.0 only */ 108 #define PSW_CB 0x0000ff00 109 #define PSW_M 0x00010000 110 #define PSW_V 0x00020000 111 #define PSW_C 0x00040000 112 #define PSW_B 0x00080000 113 #define PSW_X 0x00100000 114 #define PSW_N 0x00200000 115 #define PSW_L 0x00400000 116 #define PSW_H 0x00800000 117 #define PSW_T 0x01000000 118 #define PSW_S 0x02000000 119 #define PSW_E 0x04000000 120 #ifdef TARGET_HPPA64 121 #define PSW_W 0x08000000 /* PA2.0 only */ 122 #else 123 #define PSW_W 0 124 #endif 125 #define PSW_Z 0x40000000 /* PA1.x only */ 126 #define PSW_Y 0x80000000 /* PA1.x only */ 127 128 #define PSW_SM (PSW_W | PSW_E | PSW_O | PSW_G | PSW_F \ 129 | PSW_R | PSW_Q | PSW_P | PSW_D | PSW_I) 130 131 /* ssm/rsm instructions number PSW_W and PSW_E differently */ 132 #define PSW_SM_I PSW_I /* Enable External Interrupts */ 133 #define PSW_SM_D PSW_D 134 #define PSW_SM_P PSW_P 135 #define PSW_SM_Q PSW_Q /* Enable Interrupt State Collection */ 136 #define PSW_SM_R PSW_R /* Enable Recover Counter Trap */ 137 #ifdef TARGET_HPPA64 138 #define PSW_SM_E 0x100 139 #define PSW_SM_W 0x200 /* PA2.0 only : Enable Wide Mode */ 140 #else 141 #define PSW_SM_E 0 142 #define PSW_SM_W 0 143 #endif 144 145 #define CR_RC 0 146 #define CR_PID1 8 147 #define CR_PID2 9 148 #define CR_PID3 12 149 #define CR_PID4 13 150 #define CR_SCRCCR 10 151 #define CR_SAR 11 152 #define CR_IVA 14 153 #define CR_EIEM 15 154 #define CR_IT 16 155 #define CR_IIASQ 17 156 #define CR_IIAOQ 18 157 #define CR_IIR 19 158 #define CR_ISR 20 159 #define CR_IOR 21 160 #define CR_IPSW 22 161 #define CR_EIRR 23 162 163 typedef struct CPUHPPAState CPUHPPAState; 164 165 #if TARGET_REGISTER_BITS == 32 166 typedef uint32_t target_ureg; 167 typedef int32_t target_sreg; 168 #define TREG_FMT_lx "%08"PRIx32 169 #define TREG_FMT_ld "%"PRId32 170 #else 171 typedef uint64_t target_ureg; 172 typedef int64_t target_sreg; 173 #define TREG_FMT_lx "%016"PRIx64 174 #define TREG_FMT_ld "%"PRId64 175 #endif 176 177 typedef struct { 178 uint64_t va_b; 179 uint64_t va_e; 180 target_ureg pa; 181 unsigned u : 1; 182 unsigned t : 1; 183 unsigned d : 1; 184 unsigned b : 1; 185 unsigned page_size : 4; 186 unsigned ar_type : 3; 187 unsigned ar_pl1 : 2; 188 unsigned ar_pl2 : 2; 189 unsigned entry_valid : 1; 190 unsigned access_id : 16; 191 } hppa_tlb_entry; 192 193 struct CPUHPPAState { 194 target_ureg gr[32]; 195 uint64_t fr[32]; 196 uint64_t sr[8]; /* stored shifted into place for gva */ 197 198 target_ureg psw; /* All psw bits except the following: */ 199 target_ureg psw_n; /* boolean */ 200 target_sreg psw_v; /* in most significant bit */ 201 202 /* Splitting the carry-borrow field into the MSB and "the rest", allows 203 * for "the rest" to be deleted when it is unused, but the MSB is in use. 204 * In addition, it's easier to compute carry-in for bit B+1 than it is to 205 * compute carry-out for bit B (3 vs 4 insns for addition, assuming the 206 * host has the appropriate add-with-carry insn to compute the msb). 207 * Therefore the carry bits are stored as: cb_msb : cb & 0x11111110. 208 */ 209 target_ureg psw_cb; /* in least significant bit of next nibble */ 210 target_ureg psw_cb_msb; /* boolean */ 211 212 target_ureg iaoq_f; /* front */ 213 target_ureg iaoq_b; /* back, aka next instruction */ 214 uint64_t iasq_f; 215 uint64_t iasq_b; 216 217 uint32_t fr0_shadow; /* flags, c, ca/cq, rm, d, enables */ 218 float_status fp_status; 219 220 target_ureg cr[32]; /* control registers */ 221 target_ureg cr_back[2]; /* back of cr17/cr18 */ 222 target_ureg shadow[7]; /* shadow registers */ 223 224 /* Those resources are used only in QEMU core */ 225 CPU_COMMON 226 227 /* ??? The number of entries isn't specified by the architecture. */ 228 /* ??? Implement a unified itlb/dtlb for the moment. */ 229 /* ??? We should use a more intelligent data structure. */ 230 hppa_tlb_entry tlb[256]; 231 uint32_t tlb_last; 232 }; 233 234 /** 235 * HPPACPU: 236 * @env: #CPUHPPAState 237 * 238 * An HPPA CPU. 239 */ 240 struct HPPACPU { 241 /*< private >*/ 242 CPUState parent_obj; 243 /*< public >*/ 244 245 CPUHPPAState env; 246 QEMUTimer *alarm_timer; 247 }; 248 249 static inline HPPACPU *hppa_env_get_cpu(CPUHPPAState *env) 250 { 251 return container_of(env, HPPACPU, env); 252 } 253 254 #define ENV_GET_CPU(e) CPU(hppa_env_get_cpu(e)) 255 #define ENV_OFFSET offsetof(HPPACPU, env) 256 257 #include "exec/cpu-all.h" 258 259 static inline int cpu_mmu_index(CPUHPPAState *env, bool ifetch) 260 { 261 #ifdef CONFIG_USER_ONLY 262 return MMU_USER_IDX; 263 #else 264 if (env->psw & (ifetch ? PSW_C : PSW_D)) { 265 return env->iaoq_f & 3; 266 } 267 return MMU_PHYS_IDX; /* mmu disabled */ 268 #endif 269 } 270 271 void hppa_translate_init(void); 272 273 #define CPU_RESOLVING_TYPE TYPE_HPPA_CPU 274 275 void hppa_cpu_list(void); 276 277 static inline target_ulong hppa_form_gva_psw(target_ureg psw, uint64_t spc, 278 target_ureg off) 279 { 280 #ifdef CONFIG_USER_ONLY 281 return off; 282 #else 283 off &= (psw & PSW_W ? 0x3fffffffffffffffull : 0xffffffffull); 284 return spc | off; 285 #endif 286 } 287 288 static inline target_ulong hppa_form_gva(CPUHPPAState *env, uint64_t spc, 289 target_ureg off) 290 { 291 return hppa_form_gva_psw(env->psw, spc, off); 292 } 293 294 /* Since PSW_{I,CB} will never need to be in tb->flags, reuse them. 295 * TB_FLAG_SR_SAME indicates that SR4 through SR7 all contain the 296 * same value. 297 */ 298 #define TB_FLAG_SR_SAME PSW_I 299 #define TB_FLAG_PRIV_SHIFT 8 300 301 static inline void cpu_get_tb_cpu_state(CPUHPPAState *env, target_ulong *pc, 302 target_ulong *cs_base, 303 uint32_t *pflags) 304 { 305 uint32_t flags = env->psw_n * PSW_N; 306 307 /* TB lookup assumes that PC contains the complete virtual address. 308 If we leave space+offset separate, we'll get ITLB misses to an 309 incomplete virtual address. This also means that we must separate 310 out current cpu priviledge from the low bits of IAOQ_F. */ 311 #ifdef CONFIG_USER_ONLY 312 *pc = env->iaoq_f & -4; 313 *cs_base = env->iaoq_b & -4; 314 #else 315 /* ??? E, T, H, L, B, P bits need to be here, when implemented. */ 316 flags |= env->psw & (PSW_W | PSW_C | PSW_D); 317 flags |= (env->iaoq_f & 3) << TB_FLAG_PRIV_SHIFT; 318 319 *pc = (env->psw & PSW_C 320 ? hppa_form_gva_psw(env->psw, env->iasq_f, env->iaoq_f & -4) 321 : env->iaoq_f & -4); 322 *cs_base = env->iasq_f; 323 324 /* Insert a difference between IAOQ_B and IAOQ_F within the otherwise zero 325 low 32-bits of CS_BASE. This will succeed for all direct branches, 326 which is the primary case we care about -- using goto_tb within a page. 327 Failure is indicated by a zero difference. */ 328 if (env->iasq_f == env->iasq_b) { 329 target_sreg diff = env->iaoq_b - env->iaoq_f; 330 if (TARGET_REGISTER_BITS == 32 || diff == (int32_t)diff) { 331 *cs_base |= (uint32_t)diff; 332 } 333 } 334 if ((env->sr[4] == env->sr[5]) 335 & (env->sr[4] == env->sr[6]) 336 & (env->sr[4] == env->sr[7])) { 337 flags |= TB_FLAG_SR_SAME; 338 } 339 #endif 340 341 *pflags = flags; 342 } 343 344 target_ureg cpu_hppa_get_psw(CPUHPPAState *env); 345 void cpu_hppa_put_psw(CPUHPPAState *env, target_ureg); 346 void cpu_hppa_loaded_fr0(CPUHPPAState *env); 347 348 #ifdef CONFIG_USER_ONLY 349 static inline void cpu_hppa_change_prot_id(CPUHPPAState *env) { } 350 #else 351 void cpu_hppa_change_prot_id(CPUHPPAState *env); 352 #endif 353 354 #define cpu_signal_handler cpu_hppa_signal_handler 355 356 int cpu_hppa_signal_handler(int host_signum, void *pinfo, void *puc); 357 hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr); 358 int hppa_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 359 int hppa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 360 void hppa_cpu_do_interrupt(CPUState *cpu); 361 bool hppa_cpu_exec_interrupt(CPUState *cpu, int int_req); 362 void hppa_cpu_dump_state(CPUState *cs, FILE *f, int); 363 #ifdef CONFIG_USER_ONLY 364 int hppa_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, 365 int rw, int midx); 366 #else 367 int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, 368 int type, hwaddr *pphys, int *pprot); 369 extern const MemoryRegionOps hppa_io_eir_ops; 370 extern const struct VMStateDescription vmstate_hppa_cpu; 371 void hppa_cpu_alarm_timer(void *); 372 int hppa_artype_for_page(CPUHPPAState *env, target_ulong vaddr); 373 #endif 374 void QEMU_NORETURN hppa_dynamic_excp(CPUHPPAState *env, int excp, uintptr_t ra); 375 376 #endif /* HPPA_CPU_H */ 377