xref: /openbmc/qemu/target/hppa/cpu.c (revision efb91426)
1 /*
2  * QEMU HPPA CPU
3  *
4  * Copyright (c) 2016 Richard Henderson <rth@twiddle.net>
5  *
6  * This library is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU Lesser General Public
8  * License as published by the Free Software Foundation; either
9  * version 2.1 of the License, or (at your option) any later version.
10  *
11  * This library is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14  * Lesser General Public License for more details.
15  *
16  * You should have received a copy of the GNU Lesser General Public
17  * License along with this library; if not, see
18  * <http://www.gnu.org/licenses/lgpl-2.1.html>
19  */
20 
21 #include "qemu/osdep.h"
22 #include "qapi/error.h"
23 #include "qemu/qemu-print.h"
24 #include "qemu/timer.h"
25 #include "cpu.h"
26 #include "qemu/module.h"
27 #include "exec/exec-all.h"
28 #include "fpu/softfloat.h"
29 #include "tcg/tcg.h"
30 
31 static void hppa_cpu_set_pc(CPUState *cs, vaddr value)
32 {
33     HPPACPU *cpu = HPPA_CPU(cs);
34 
35     cpu->env.iaoq_f = value;
36     cpu->env.iaoq_b = value + 4;
37 }
38 
39 static vaddr hppa_cpu_get_pc(CPUState *cs)
40 {
41     HPPACPU *cpu = HPPA_CPU(cs);
42 
43     return cpu->env.iaoq_f;
44 }
45 
46 static void hppa_cpu_synchronize_from_tb(CPUState *cs,
47                                          const TranslationBlock *tb)
48 {
49     HPPACPU *cpu = HPPA_CPU(cs);
50 
51     tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
52 
53 #ifdef CONFIG_USER_ONLY
54     cpu->env.iaoq_f = tb->pc;
55     cpu->env.iaoq_b = tb->cs_base;
56 #else
57     /* Recover the IAOQ values from the GVA + PRIV.  */
58     uint32_t priv = (tb->flags >> TB_FLAG_PRIV_SHIFT) & 3;
59     target_ulong cs_base = tb->cs_base;
60     target_ulong iasq_f = cs_base & ~0xffffffffull;
61     int32_t diff = cs_base;
62 
63     cpu->env.iasq_f = iasq_f;
64     cpu->env.iaoq_f = (tb->pc & ~iasq_f) + priv;
65     if (diff) {
66         cpu->env.iaoq_b = cpu->env.iaoq_f + diff;
67     }
68 #endif
69 
70     cpu->env.psw_n = (tb->flags & PSW_N) != 0;
71 }
72 
73 static void hppa_restore_state_to_opc(CPUState *cs,
74                                       const TranslationBlock *tb,
75                                       const uint64_t *data)
76 {
77     HPPACPU *cpu = HPPA_CPU(cs);
78 
79     cpu->env.iaoq_f = data[0];
80     if (data[1] != (target_ulong)-1) {
81         cpu->env.iaoq_b = data[1];
82     }
83     cpu->env.unwind_breg = data[2];
84     /*
85      * Since we were executing the instruction at IAOQ_F, and took some
86      * sort of action that provoked the cpu_restore_state, we can infer
87      * that the instruction was not nullified.
88      */
89     cpu->env.psw_n = 0;
90 }
91 
92 static bool hppa_cpu_has_work(CPUState *cs)
93 {
94     return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
95 }
96 
97 static void hppa_cpu_disas_set_info(CPUState *cs, disassemble_info *info)
98 {
99     info->mach = bfd_mach_hppa20;
100     info->print_insn = print_insn_hppa;
101 }
102 
103 #ifndef CONFIG_USER_ONLY
104 static G_NORETURN
105 void hppa_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
106                                   MMUAccessType access_type, int mmu_idx,
107                                   uintptr_t retaddr)
108 {
109     HPPACPU *cpu = HPPA_CPU(cs);
110     CPUHPPAState *env = &cpu->env;
111 
112     cs->exception_index = EXCP_UNALIGN;
113     if (env->psw & PSW_Q) {
114         /* ??? Needs tweaking for hppa64.  */
115         env->cr[CR_IOR] = addr;
116         env->cr[CR_ISR] = addr >> 32;
117     }
118 
119     cpu_loop_exit_restore(cs, retaddr);
120 }
121 #endif /* CONFIG_USER_ONLY */
122 
123 static void hppa_cpu_realizefn(DeviceState *dev, Error **errp)
124 {
125     CPUState *cs = CPU(dev);
126     HPPACPUClass *acc = HPPA_CPU_GET_CLASS(dev);
127     Error *local_err = NULL;
128 
129     cpu_exec_realizefn(cs, &local_err);
130     if (local_err != NULL) {
131         error_propagate(errp, local_err);
132         return;
133     }
134 
135     qemu_init_vcpu(cs);
136     acc->parent_realize(dev, errp);
137 
138 #ifndef CONFIG_USER_ONLY
139     {
140         HPPACPU *cpu = HPPA_CPU(cs);
141 
142         cpu->alarm_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
143                                         hppa_cpu_alarm_timer, cpu);
144         hppa_ptlbe(&cpu->env);
145     }
146 #endif
147 }
148 
149 static void hppa_cpu_initfn(Object *obj)
150 {
151     CPUState *cs = CPU(obj);
152     HPPACPU *cpu = HPPA_CPU(obj);
153     CPUHPPAState *env = &cpu->env;
154 
155     cs->exception_index = -1;
156     cpu_hppa_loaded_fr0(env);
157     cpu_hppa_put_psw(env, PSW_W);
158 }
159 
160 static ObjectClass *hppa_cpu_class_by_name(const char *cpu_model)
161 {
162     g_autofree char *typename = g_strconcat(cpu_model, "-cpu", NULL);
163 
164     return object_class_by_name(typename);
165 }
166 
167 #ifndef CONFIG_USER_ONLY
168 #include "hw/core/sysemu-cpu-ops.h"
169 
170 static const struct SysemuCPUOps hppa_sysemu_ops = {
171     .get_phys_page_debug = hppa_cpu_get_phys_page_debug,
172 };
173 #endif
174 
175 #include "hw/core/tcg-cpu-ops.h"
176 
177 static const struct TCGCPUOps hppa_tcg_ops = {
178     .initialize = hppa_translate_init,
179     .synchronize_from_tb = hppa_cpu_synchronize_from_tb,
180     .restore_state_to_opc = hppa_restore_state_to_opc,
181 
182 #ifndef CONFIG_USER_ONLY
183     .tlb_fill = hppa_cpu_tlb_fill,
184     .cpu_exec_interrupt = hppa_cpu_exec_interrupt,
185     .do_interrupt = hppa_cpu_do_interrupt,
186     .do_unaligned_access = hppa_cpu_do_unaligned_access,
187 #endif /* !CONFIG_USER_ONLY */
188 };
189 
190 static void hppa_cpu_class_init(ObjectClass *oc, void *data)
191 {
192     DeviceClass *dc = DEVICE_CLASS(oc);
193     CPUClass *cc = CPU_CLASS(oc);
194     HPPACPUClass *acc = HPPA_CPU_CLASS(oc);
195 
196     device_class_set_parent_realize(dc, hppa_cpu_realizefn,
197                                     &acc->parent_realize);
198 
199     cc->class_by_name = hppa_cpu_class_by_name;
200     cc->has_work = hppa_cpu_has_work;
201     cc->dump_state = hppa_cpu_dump_state;
202     cc->set_pc = hppa_cpu_set_pc;
203     cc->get_pc = hppa_cpu_get_pc;
204     cc->gdb_read_register = hppa_cpu_gdb_read_register;
205     cc->gdb_write_register = hppa_cpu_gdb_write_register;
206 #ifndef CONFIG_USER_ONLY
207     dc->vmsd = &vmstate_hppa_cpu;
208     cc->sysemu_ops = &hppa_sysemu_ops;
209 #endif
210     cc->disas_set_info = hppa_cpu_disas_set_info;
211     cc->gdb_num_core_regs = 128;
212     cc->tcg_ops = &hppa_tcg_ops;
213 }
214 
215 static const TypeInfo hppa_cpu_type_infos[] = {
216     {
217         .name = TYPE_HPPA_CPU,
218         .parent = TYPE_CPU,
219         .instance_size = sizeof(HPPACPU),
220         .instance_align = __alignof(HPPACPU),
221         .instance_init = hppa_cpu_initfn,
222         .abstract = false,
223         .class_size = sizeof(HPPACPUClass),
224         .class_init = hppa_cpu_class_init,
225     },
226     {
227         .name = TYPE_HPPA64_CPU,
228         .parent = TYPE_HPPA_CPU,
229     },
230 };
231 
232 DEFINE_TYPES(hppa_cpu_type_infos)
233