1 /* 2 * QEMU HPPA CPU 3 * 4 * Copyright (c) 2016 Richard Henderson <rth@twiddle.net> 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see 18 * <http://www.gnu.org/licenses/lgpl-2.1.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qapi/error.h" 23 #include "qemu/qemu-print.h" 24 #include "qemu/timer.h" 25 #include "cpu.h" 26 #include "qemu/module.h" 27 #include "exec/exec-all.h" 28 #include "fpu/softfloat.h" 29 30 31 static void hppa_cpu_set_pc(CPUState *cs, vaddr value) 32 { 33 HPPACPU *cpu = HPPA_CPU(cs); 34 35 cpu->env.iaoq_f = value; 36 cpu->env.iaoq_b = value + 4; 37 } 38 39 static vaddr hppa_cpu_get_pc(CPUState *cs) 40 { 41 HPPACPU *cpu = HPPA_CPU(cs); 42 43 return cpu->env.iaoq_f; 44 } 45 46 static void hppa_cpu_synchronize_from_tb(CPUState *cs, 47 const TranslationBlock *tb) 48 { 49 HPPACPU *cpu = HPPA_CPU(cs); 50 51 #ifdef CONFIG_USER_ONLY 52 cpu->env.iaoq_f = tb->pc; 53 cpu->env.iaoq_b = tb->cs_base; 54 #else 55 /* Recover the IAOQ values from the GVA + PRIV. */ 56 uint32_t priv = (tb->flags >> TB_FLAG_PRIV_SHIFT) & 3; 57 target_ulong cs_base = tb->cs_base; 58 target_ulong iasq_f = cs_base & ~0xffffffffull; 59 int32_t diff = cs_base; 60 61 cpu->env.iasq_f = iasq_f; 62 cpu->env.iaoq_f = (tb->pc & ~iasq_f) + priv; 63 if (diff) { 64 cpu->env.iaoq_b = cpu->env.iaoq_f + diff; 65 } 66 #endif 67 68 cpu->env.psw_n = (tb->flags & PSW_N) != 0; 69 } 70 71 static bool hppa_cpu_has_work(CPUState *cs) 72 { 73 return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI); 74 } 75 76 static void hppa_cpu_disas_set_info(CPUState *cs, disassemble_info *info) 77 { 78 info->mach = bfd_mach_hppa20; 79 info->print_insn = print_insn_hppa; 80 } 81 82 #ifndef CONFIG_USER_ONLY 83 static G_NORETURN 84 void hppa_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 85 MMUAccessType access_type, int mmu_idx, 86 uintptr_t retaddr) 87 { 88 HPPACPU *cpu = HPPA_CPU(cs); 89 CPUHPPAState *env = &cpu->env; 90 91 cs->exception_index = EXCP_UNALIGN; 92 if (env->psw & PSW_Q) { 93 /* ??? Needs tweaking for hppa64. */ 94 env->cr[CR_IOR] = addr; 95 env->cr[CR_ISR] = addr >> 32; 96 } 97 98 cpu_loop_exit_restore(cs, retaddr); 99 } 100 #endif /* CONFIG_USER_ONLY */ 101 102 static void hppa_cpu_realizefn(DeviceState *dev, Error **errp) 103 { 104 CPUState *cs = CPU(dev); 105 HPPACPUClass *acc = HPPA_CPU_GET_CLASS(dev); 106 Error *local_err = NULL; 107 108 cpu_exec_realizefn(cs, &local_err); 109 if (local_err != NULL) { 110 error_propagate(errp, local_err); 111 return; 112 } 113 114 qemu_init_vcpu(cs); 115 acc->parent_realize(dev, errp); 116 117 #ifndef CONFIG_USER_ONLY 118 { 119 HPPACPU *cpu = HPPA_CPU(cs); 120 cpu->alarm_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 121 hppa_cpu_alarm_timer, cpu); 122 } 123 #endif 124 } 125 126 static void hppa_cpu_initfn(Object *obj) 127 { 128 CPUState *cs = CPU(obj); 129 HPPACPU *cpu = HPPA_CPU(obj); 130 CPUHPPAState *env = &cpu->env; 131 132 cpu_set_cpustate_pointers(cpu); 133 cs->exception_index = -1; 134 cpu_hppa_loaded_fr0(env); 135 cpu_hppa_put_psw(env, PSW_W); 136 } 137 138 static ObjectClass *hppa_cpu_class_by_name(const char *cpu_model) 139 { 140 return object_class_by_name(TYPE_HPPA_CPU); 141 } 142 143 #ifndef CONFIG_USER_ONLY 144 #include "hw/core/sysemu-cpu-ops.h" 145 146 static const struct SysemuCPUOps hppa_sysemu_ops = { 147 .get_phys_page_debug = hppa_cpu_get_phys_page_debug, 148 }; 149 #endif 150 151 #include "hw/core/tcg-cpu-ops.h" 152 153 static const struct TCGCPUOps hppa_tcg_ops = { 154 .initialize = hppa_translate_init, 155 .synchronize_from_tb = hppa_cpu_synchronize_from_tb, 156 157 #ifndef CONFIG_USER_ONLY 158 .tlb_fill = hppa_cpu_tlb_fill, 159 .cpu_exec_interrupt = hppa_cpu_exec_interrupt, 160 .do_interrupt = hppa_cpu_do_interrupt, 161 .do_unaligned_access = hppa_cpu_do_unaligned_access, 162 #endif /* !CONFIG_USER_ONLY */ 163 }; 164 165 static void hppa_cpu_class_init(ObjectClass *oc, void *data) 166 { 167 DeviceClass *dc = DEVICE_CLASS(oc); 168 CPUClass *cc = CPU_CLASS(oc); 169 HPPACPUClass *acc = HPPA_CPU_CLASS(oc); 170 171 device_class_set_parent_realize(dc, hppa_cpu_realizefn, 172 &acc->parent_realize); 173 174 cc->class_by_name = hppa_cpu_class_by_name; 175 cc->has_work = hppa_cpu_has_work; 176 cc->dump_state = hppa_cpu_dump_state; 177 cc->set_pc = hppa_cpu_set_pc; 178 cc->get_pc = hppa_cpu_get_pc; 179 cc->gdb_read_register = hppa_cpu_gdb_read_register; 180 cc->gdb_write_register = hppa_cpu_gdb_write_register; 181 #ifndef CONFIG_USER_ONLY 182 dc->vmsd = &vmstate_hppa_cpu; 183 cc->sysemu_ops = &hppa_sysemu_ops; 184 #endif 185 cc->disas_set_info = hppa_cpu_disas_set_info; 186 cc->gdb_num_core_regs = 128; 187 cc->tcg_ops = &hppa_tcg_ops; 188 } 189 190 static const TypeInfo hppa_cpu_type_info = { 191 .name = TYPE_HPPA_CPU, 192 .parent = TYPE_CPU, 193 .instance_size = sizeof(HPPACPU), 194 .instance_init = hppa_cpu_initfn, 195 .abstract = false, 196 .class_size = sizeof(HPPACPUClass), 197 .class_init = hppa_cpu_class_init, 198 }; 199 200 static void hppa_cpu_register_types(void) 201 { 202 type_register_static(&hppa_cpu_type_info); 203 } 204 205 type_init(hppa_cpu_register_types) 206