1 /* 2 * QEMU HPPA CPU 3 * 4 * Copyright (c) 2016 Richard Henderson <rth@twiddle.net> 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see 18 * <http://www.gnu.org/licenses/lgpl-2.1.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qapi/error.h" 23 #include "qemu/qemu-print.h" 24 #include "cpu.h" 25 #include "qemu/module.h" 26 #include "exec/exec-all.h" 27 #include "fpu/softfloat.h" 28 29 30 static void hppa_cpu_set_pc(CPUState *cs, vaddr value) 31 { 32 HPPACPU *cpu = HPPA_CPU(cs); 33 34 cpu->env.iaoq_f = value; 35 cpu->env.iaoq_b = value + 4; 36 } 37 38 static void hppa_cpu_synchronize_from_tb(CPUState *cs, 39 const TranslationBlock *tb) 40 { 41 HPPACPU *cpu = HPPA_CPU(cs); 42 43 #ifdef CONFIG_USER_ONLY 44 cpu->env.iaoq_f = tb->pc; 45 cpu->env.iaoq_b = tb->cs_base; 46 #else 47 /* Recover the IAOQ values from the GVA + PRIV. */ 48 uint32_t priv = (tb->flags >> TB_FLAG_PRIV_SHIFT) & 3; 49 target_ulong cs_base = tb->cs_base; 50 target_ulong iasq_f = cs_base & ~0xffffffffull; 51 int32_t diff = cs_base; 52 53 cpu->env.iasq_f = iasq_f; 54 cpu->env.iaoq_f = (tb->pc & ~iasq_f) + priv; 55 if (diff) { 56 cpu->env.iaoq_b = cpu->env.iaoq_f + diff; 57 } 58 #endif 59 60 cpu->env.psw_n = (tb->flags & PSW_N) != 0; 61 } 62 63 static bool hppa_cpu_has_work(CPUState *cs) 64 { 65 return cs->interrupt_request & CPU_INTERRUPT_HARD; 66 } 67 68 static void hppa_cpu_disas_set_info(CPUState *cs, disassemble_info *info) 69 { 70 info->mach = bfd_mach_hppa20; 71 info->print_insn = print_insn_hppa; 72 } 73 74 #ifndef CONFIG_USER_ONLY 75 static void hppa_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 76 MMUAccessType access_type, 77 int mmu_idx, uintptr_t retaddr) 78 { 79 HPPACPU *cpu = HPPA_CPU(cs); 80 CPUHPPAState *env = &cpu->env; 81 82 cs->exception_index = EXCP_UNALIGN; 83 if (env->psw & PSW_Q) { 84 /* ??? Needs tweaking for hppa64. */ 85 env->cr[CR_IOR] = addr; 86 env->cr[CR_ISR] = addr >> 32; 87 } 88 89 cpu_loop_exit_restore(cs, retaddr); 90 } 91 #endif /* CONFIG_USER_ONLY */ 92 93 static void hppa_cpu_realizefn(DeviceState *dev, Error **errp) 94 { 95 CPUState *cs = CPU(dev); 96 HPPACPUClass *acc = HPPA_CPU_GET_CLASS(dev); 97 Error *local_err = NULL; 98 99 cpu_exec_realizefn(cs, &local_err); 100 if (local_err != NULL) { 101 error_propagate(errp, local_err); 102 return; 103 } 104 105 qemu_init_vcpu(cs); 106 acc->parent_realize(dev, errp); 107 108 #ifndef CONFIG_USER_ONLY 109 { 110 HPPACPU *cpu = HPPA_CPU(cs); 111 cpu->alarm_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 112 hppa_cpu_alarm_timer, cpu); 113 } 114 #endif 115 } 116 117 static void hppa_cpu_initfn(Object *obj) 118 { 119 CPUState *cs = CPU(obj); 120 HPPACPU *cpu = HPPA_CPU(obj); 121 CPUHPPAState *env = &cpu->env; 122 123 cpu_set_cpustate_pointers(cpu); 124 cs->exception_index = -1; 125 cpu_hppa_loaded_fr0(env); 126 cpu_hppa_put_psw(env, PSW_W); 127 } 128 129 static ObjectClass *hppa_cpu_class_by_name(const char *cpu_model) 130 { 131 return object_class_by_name(TYPE_HPPA_CPU); 132 } 133 134 static void hppa_cpu_class_init(ObjectClass *oc, void *data) 135 { 136 DeviceClass *dc = DEVICE_CLASS(oc); 137 CPUClass *cc = CPU_CLASS(oc); 138 HPPACPUClass *acc = HPPA_CPU_CLASS(oc); 139 140 device_class_set_parent_realize(dc, hppa_cpu_realizefn, 141 &acc->parent_realize); 142 143 cc->class_by_name = hppa_cpu_class_by_name; 144 cc->has_work = hppa_cpu_has_work; 145 cc->tcg_ops.do_interrupt = hppa_cpu_do_interrupt; 146 cc->tcg_ops.cpu_exec_interrupt = hppa_cpu_exec_interrupt; 147 cc->dump_state = hppa_cpu_dump_state; 148 cc->set_pc = hppa_cpu_set_pc; 149 cc->tcg_ops.synchronize_from_tb = hppa_cpu_synchronize_from_tb; 150 cc->gdb_read_register = hppa_cpu_gdb_read_register; 151 cc->gdb_write_register = hppa_cpu_gdb_write_register; 152 cc->tcg_ops.tlb_fill = hppa_cpu_tlb_fill; 153 #ifndef CONFIG_USER_ONLY 154 cc->get_phys_page_debug = hppa_cpu_get_phys_page_debug; 155 cc->tcg_ops.do_unaligned_access = hppa_cpu_do_unaligned_access; 156 dc->vmsd = &vmstate_hppa_cpu; 157 #endif 158 cc->disas_set_info = hppa_cpu_disas_set_info; 159 cc->tcg_ops.initialize = hppa_translate_init; 160 161 cc->gdb_num_core_regs = 128; 162 } 163 164 static const TypeInfo hppa_cpu_type_info = { 165 .name = TYPE_HPPA_CPU, 166 .parent = TYPE_CPU, 167 .instance_size = sizeof(HPPACPU), 168 .instance_init = hppa_cpu_initfn, 169 .abstract = false, 170 .class_size = sizeof(HPPACPUClass), 171 .class_init = hppa_cpu_class_init, 172 }; 173 174 static void hppa_cpu_register_types(void) 175 { 176 type_register_static(&hppa_cpu_type_info); 177 } 178 179 type_init(hppa_cpu_register_types) 180