1 /* 2 * QEMU HPPA CPU 3 * 4 * Copyright (c) 2016 Richard Henderson <rth@twiddle.net> 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see 18 * <http://www.gnu.org/licenses/lgpl-2.1.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qapi/error.h" 23 #include "qemu/qemu-print.h" 24 #include "qemu/timer.h" 25 #include "cpu.h" 26 #include "qemu/module.h" 27 #include "exec/exec-all.h" 28 #include "fpu/softfloat.h" 29 30 31 static void hppa_cpu_set_pc(CPUState *cs, vaddr value) 32 { 33 HPPACPU *cpu = HPPA_CPU(cs); 34 35 cpu->env.iaoq_f = value; 36 cpu->env.iaoq_b = value + 4; 37 } 38 39 static void hppa_cpu_synchronize_from_tb(CPUState *cs, 40 const TranslationBlock *tb) 41 { 42 HPPACPU *cpu = HPPA_CPU(cs); 43 44 #ifdef CONFIG_USER_ONLY 45 cpu->env.iaoq_f = tb->pc; 46 cpu->env.iaoq_b = tb->cs_base; 47 #else 48 /* Recover the IAOQ values from the GVA + PRIV. */ 49 uint32_t priv = (tb->flags >> TB_FLAG_PRIV_SHIFT) & 3; 50 target_ulong cs_base = tb->cs_base; 51 target_ulong iasq_f = cs_base & ~0xffffffffull; 52 int32_t diff = cs_base; 53 54 cpu->env.iasq_f = iasq_f; 55 cpu->env.iaoq_f = (tb->pc & ~iasq_f) + priv; 56 if (diff) { 57 cpu->env.iaoq_b = cpu->env.iaoq_f + diff; 58 } 59 #endif 60 61 cpu->env.psw_n = (tb->flags & PSW_N) != 0; 62 } 63 64 static bool hppa_cpu_has_work(CPUState *cs) 65 { 66 return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI); 67 } 68 69 static void hppa_cpu_disas_set_info(CPUState *cs, disassemble_info *info) 70 { 71 info->mach = bfd_mach_hppa20; 72 info->print_insn = print_insn_hppa; 73 } 74 75 #ifndef CONFIG_USER_ONLY 76 static void QEMU_NORETURN 77 hppa_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 78 MMUAccessType access_type, int mmu_idx, 79 uintptr_t retaddr) 80 { 81 HPPACPU *cpu = HPPA_CPU(cs); 82 CPUHPPAState *env = &cpu->env; 83 84 cs->exception_index = EXCP_UNALIGN; 85 if (env->psw & PSW_Q) { 86 /* ??? Needs tweaking for hppa64. */ 87 env->cr[CR_IOR] = addr; 88 env->cr[CR_ISR] = addr >> 32; 89 } 90 91 cpu_loop_exit_restore(cs, retaddr); 92 } 93 #endif /* CONFIG_USER_ONLY */ 94 95 static void hppa_cpu_realizefn(DeviceState *dev, Error **errp) 96 { 97 CPUState *cs = CPU(dev); 98 HPPACPUClass *acc = HPPA_CPU_GET_CLASS(dev); 99 Error *local_err = NULL; 100 101 cpu_exec_realizefn(cs, &local_err); 102 if (local_err != NULL) { 103 error_propagate(errp, local_err); 104 return; 105 } 106 107 qemu_init_vcpu(cs); 108 acc->parent_realize(dev, errp); 109 110 #ifndef CONFIG_USER_ONLY 111 { 112 HPPACPU *cpu = HPPA_CPU(cs); 113 cpu->alarm_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 114 hppa_cpu_alarm_timer, cpu); 115 } 116 #endif 117 } 118 119 static void hppa_cpu_initfn(Object *obj) 120 { 121 CPUState *cs = CPU(obj); 122 HPPACPU *cpu = HPPA_CPU(obj); 123 CPUHPPAState *env = &cpu->env; 124 125 cpu_set_cpustate_pointers(cpu); 126 cs->exception_index = -1; 127 cpu_hppa_loaded_fr0(env); 128 cpu_hppa_put_psw(env, PSW_W); 129 } 130 131 static ObjectClass *hppa_cpu_class_by_name(const char *cpu_model) 132 { 133 return object_class_by_name(TYPE_HPPA_CPU); 134 } 135 136 #ifndef CONFIG_USER_ONLY 137 #include "hw/core/sysemu-cpu-ops.h" 138 139 static const struct SysemuCPUOps hppa_sysemu_ops = { 140 .get_phys_page_debug = hppa_cpu_get_phys_page_debug, 141 }; 142 #endif 143 144 #include "hw/core/tcg-cpu-ops.h" 145 146 static const struct TCGCPUOps hppa_tcg_ops = { 147 .initialize = hppa_translate_init, 148 .synchronize_from_tb = hppa_cpu_synchronize_from_tb, 149 150 #ifndef CONFIG_USER_ONLY 151 .tlb_fill = hppa_cpu_tlb_fill, 152 .cpu_exec_interrupt = hppa_cpu_exec_interrupt, 153 .do_interrupt = hppa_cpu_do_interrupt, 154 .do_unaligned_access = hppa_cpu_do_unaligned_access, 155 #endif /* !CONFIG_USER_ONLY */ 156 }; 157 158 static void hppa_cpu_class_init(ObjectClass *oc, void *data) 159 { 160 DeviceClass *dc = DEVICE_CLASS(oc); 161 CPUClass *cc = CPU_CLASS(oc); 162 HPPACPUClass *acc = HPPA_CPU_CLASS(oc); 163 164 device_class_set_parent_realize(dc, hppa_cpu_realizefn, 165 &acc->parent_realize); 166 167 cc->class_by_name = hppa_cpu_class_by_name; 168 cc->has_work = hppa_cpu_has_work; 169 cc->dump_state = hppa_cpu_dump_state; 170 cc->set_pc = hppa_cpu_set_pc; 171 cc->gdb_read_register = hppa_cpu_gdb_read_register; 172 cc->gdb_write_register = hppa_cpu_gdb_write_register; 173 #ifndef CONFIG_USER_ONLY 174 dc->vmsd = &vmstate_hppa_cpu; 175 cc->sysemu_ops = &hppa_sysemu_ops; 176 #endif 177 cc->disas_set_info = hppa_cpu_disas_set_info; 178 cc->gdb_num_core_regs = 128; 179 cc->tcg_ops = &hppa_tcg_ops; 180 } 181 182 static const TypeInfo hppa_cpu_type_info = { 183 .name = TYPE_HPPA_CPU, 184 .parent = TYPE_CPU, 185 .instance_size = sizeof(HPPACPU), 186 .instance_init = hppa_cpu_initfn, 187 .abstract = false, 188 .class_size = sizeof(HPPACPUClass), 189 .class_init = hppa_cpu_class_init, 190 }; 191 192 static void hppa_cpu_register_types(void) 193 { 194 type_register_static(&hppa_cpu_type_info); 195 } 196 197 type_init(hppa_cpu_register_types) 198