1 /* 2 * QEMU HPPA CPU 3 * 4 * Copyright (c) 2016 Richard Henderson <rth@twiddle.net> 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see 18 * <http://www.gnu.org/licenses/lgpl-2.1.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qapi/error.h" 23 #include "cpu.h" 24 #include "qemu-common.h" 25 #include "exec/exec-all.h" 26 #include "fpu/softfloat.h" 27 28 29 static void hppa_cpu_set_pc(CPUState *cs, vaddr value) 30 { 31 HPPACPU *cpu = HPPA_CPU(cs); 32 33 cpu->env.iaoq_f = value; 34 cpu->env.iaoq_b = value + 4; 35 } 36 37 static void hppa_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) 38 { 39 HPPACPU *cpu = HPPA_CPU(cs); 40 41 #ifdef CONFIG_USER_ONLY 42 cpu->env.iaoq_f = tb->pc; 43 cpu->env.iaoq_b = tb->cs_base; 44 #else 45 /* Recover the IAOQ values from the GVA + PRIV. */ 46 uint32_t priv = (tb->flags >> TB_FLAG_PRIV_SHIFT) & 3; 47 target_ulong cs_base = tb->cs_base; 48 target_ulong iasq_f = cs_base & ~0xffffffffull; 49 int32_t diff = cs_base; 50 51 cpu->env.iasq_f = iasq_f; 52 cpu->env.iaoq_f = (tb->pc & ~iasq_f) + priv; 53 if (diff) { 54 cpu->env.iaoq_b = cpu->env.iaoq_f + diff; 55 } 56 #endif 57 58 cpu->env.psw_n = (tb->flags & PSW_N) != 0; 59 } 60 61 static bool hppa_cpu_has_work(CPUState *cs) 62 { 63 return cs->interrupt_request & CPU_INTERRUPT_HARD; 64 } 65 66 static void hppa_cpu_disas_set_info(CPUState *cs, disassemble_info *info) 67 { 68 info->mach = bfd_mach_hppa20; 69 info->print_insn = print_insn_hppa; 70 } 71 72 static void hppa_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 73 MMUAccessType access_type, 74 int mmu_idx, uintptr_t retaddr) 75 { 76 HPPACPU *cpu = HPPA_CPU(cs); 77 CPUHPPAState *env = &cpu->env; 78 79 cs->exception_index = EXCP_UNALIGN; 80 if (env->psw & PSW_Q) { 81 /* ??? Needs tweaking for hppa64. */ 82 env->cr[CR_IOR] = addr; 83 env->cr[CR_ISR] = addr >> 32; 84 } 85 86 cpu_loop_exit_restore(cs, retaddr); 87 } 88 89 static void hppa_cpu_realizefn(DeviceState *dev, Error **errp) 90 { 91 CPUState *cs = CPU(dev); 92 HPPACPUClass *acc = HPPA_CPU_GET_CLASS(dev); 93 Error *local_err = NULL; 94 95 cpu_exec_realizefn(cs, &local_err); 96 if (local_err != NULL) { 97 error_propagate(errp, local_err); 98 return; 99 } 100 101 qemu_init_vcpu(cs); 102 acc->parent_realize(dev, errp); 103 104 #ifndef CONFIG_USER_ONLY 105 { 106 HPPACPU *cpu = HPPA_CPU(cs); 107 cpu->alarm_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 108 hppa_cpu_alarm_timer, cpu); 109 } 110 #endif 111 } 112 113 static void hppa_cpu_list_entry(gpointer data, gpointer user_data) 114 { 115 ObjectClass *oc = data; 116 CPUListState *s = user_data; 117 118 (*s->cpu_fprintf)(s->file, " %s\n", object_class_get_name(oc)); 119 } 120 121 void hppa_cpu_list(FILE *f, fprintf_function cpu_fprintf) 122 { 123 CPUListState s = { 124 .file = f, 125 .cpu_fprintf = cpu_fprintf, 126 }; 127 GSList *list; 128 129 list = object_class_get_list_sorted(TYPE_HPPA_CPU, false); 130 (*cpu_fprintf)(f, "Available CPUs:\n"); 131 g_slist_foreach(list, hppa_cpu_list_entry, &s); 132 g_slist_free(list); 133 } 134 135 static void hppa_cpu_initfn(Object *obj) 136 { 137 CPUState *cs = CPU(obj); 138 HPPACPU *cpu = HPPA_CPU(obj); 139 CPUHPPAState *env = &cpu->env; 140 141 cs->env_ptr = env; 142 cs->exception_index = -1; 143 cpu_hppa_loaded_fr0(env); 144 cpu_hppa_put_psw(env, PSW_W); 145 } 146 147 static ObjectClass *hppa_cpu_class_by_name(const char *cpu_model) 148 { 149 return object_class_by_name(TYPE_HPPA_CPU); 150 } 151 152 static void hppa_cpu_class_init(ObjectClass *oc, void *data) 153 { 154 DeviceClass *dc = DEVICE_CLASS(oc); 155 CPUClass *cc = CPU_CLASS(oc); 156 HPPACPUClass *acc = HPPA_CPU_CLASS(oc); 157 158 device_class_set_parent_realize(dc, hppa_cpu_realizefn, 159 &acc->parent_realize); 160 161 cc->class_by_name = hppa_cpu_class_by_name; 162 cc->has_work = hppa_cpu_has_work; 163 cc->do_interrupt = hppa_cpu_do_interrupt; 164 cc->cpu_exec_interrupt = hppa_cpu_exec_interrupt; 165 cc->dump_state = hppa_cpu_dump_state; 166 cc->set_pc = hppa_cpu_set_pc; 167 cc->synchronize_from_tb = hppa_cpu_synchronize_from_tb; 168 cc->gdb_read_register = hppa_cpu_gdb_read_register; 169 cc->gdb_write_register = hppa_cpu_gdb_write_register; 170 #ifdef CONFIG_USER_ONLY 171 cc->handle_mmu_fault = hppa_cpu_handle_mmu_fault; 172 #else 173 cc->get_phys_page_debug = hppa_cpu_get_phys_page_debug; 174 dc->vmsd = &vmstate_hppa_cpu; 175 #endif 176 cc->do_unaligned_access = hppa_cpu_do_unaligned_access; 177 cc->disas_set_info = hppa_cpu_disas_set_info; 178 cc->tcg_initialize = hppa_translate_init; 179 180 cc->gdb_num_core_regs = 128; 181 } 182 183 static const TypeInfo hppa_cpu_type_info = { 184 .name = TYPE_HPPA_CPU, 185 .parent = TYPE_CPU, 186 .instance_size = sizeof(HPPACPU), 187 .instance_init = hppa_cpu_initfn, 188 .abstract = false, 189 .class_size = sizeof(HPPACPUClass), 190 .class_init = hppa_cpu_class_init, 191 }; 192 193 static void hppa_cpu_register_types(void) 194 { 195 type_register_static(&hppa_cpu_type_info); 196 } 197 198 type_init(hppa_cpu_register_types) 199