1 /* 2 * PA-RISC cpu parameters for qemu. 3 * 4 * Copyright (c) 2016 Richard Henderson <rth@twiddle.net> 5 * SPDX-License-Identifier: LGPL-2.0-or-later 6 */ 7 8 #ifndef HPPA_CPU_PARAM_H 9 #define HPPA_CPU_PARAM_H 10 11 #define TARGET_LONG_BITS 64 12 13 #if defined(CONFIG_USER_ONLY) && defined(TARGET_ABI32) 14 # define TARGET_PHYS_ADDR_SPACE_BITS 32 15 # define TARGET_VIRT_ADDR_SPACE_BITS 32 16 #else 17 /* ??? PA-8000 through 8600 have 40 bits; PA-8700 and 8900 have 44 bits. */ 18 # define TARGET_PHYS_ADDR_SPACE_BITS 40 19 # define TARGET_VIRT_ADDR_SPACE_BITS 64 20 #endif 21 22 #define TARGET_PAGE_BITS 12 23 24 /* PA-RISC 1.x processors have a strong memory model. */ 25 /* 26 * ??? While we do not yet implement PA-RISC 2.0, those processors have 27 * a weak memory model, but with TLB bits that force ordering on a per-page 28 * basis. It's probably easier to fall back to a strong memory model. 29 */ 30 #define TCG_GUEST_DEFAULT_MO TCG_MO_ALL 31 32 #endif 33