1 /* 2 * Copyright(c) 2019-2022 Qualcomm Innovation Center, Inc. All Rights Reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #ifndef HEXAGON_TRANSLATE_H 19 #define HEXAGON_TRANSLATE_H 20 21 #include "qemu/bitmap.h" 22 #include "qemu/log.h" 23 #include "cpu.h" 24 #include "exec/translator.h" 25 #include "tcg/tcg-op.h" 26 #include "insn.h" 27 #include "internal.h" 28 29 typedef struct DisasContext { 30 DisasContextBase base; 31 Packet *pkt; 32 Insn *insn; 33 uint32_t next_PC; 34 uint32_t mem_idx; 35 uint32_t num_packets; 36 uint32_t num_insns; 37 uint32_t num_hvx_insns; 38 int reg_log[REG_WRITES_MAX]; 39 int reg_log_idx; 40 DECLARE_BITMAP(regs_written, TOTAL_PER_THREAD_REGS); 41 int preg_log[PRED_WRITES_MAX]; 42 int preg_log_idx; 43 DECLARE_BITMAP(pregs_written, NUM_PREGS); 44 uint8_t store_width[STORES_MAX]; 45 bool s1_store_processed; 46 int future_vregs_idx; 47 int future_vregs_num[VECTOR_TEMPS_MAX]; 48 int tmp_vregs_idx; 49 int tmp_vregs_num[VECTOR_TEMPS_MAX]; 50 int vreg_log[NUM_VREGS]; 51 bool vreg_is_predicated[NUM_VREGS]; 52 int vreg_log_idx; 53 DECLARE_BITMAP(vregs_updated_tmp, NUM_VREGS); 54 DECLARE_BITMAP(vregs_updated, NUM_VREGS); 55 DECLARE_BITMAP(vregs_select, NUM_VREGS); 56 int qreg_log[NUM_QREGS]; 57 bool qreg_is_predicated[NUM_QREGS]; 58 int qreg_log_idx; 59 bool pre_commit; 60 TCGCond branch_cond; 61 target_ulong branch_dest; 62 bool is_tight_loop; 63 } DisasContext; 64 65 static inline void ctx_log_reg_write(DisasContext *ctx, int rnum) 66 { 67 if (test_bit(rnum, ctx->regs_written)) { 68 HEX_DEBUG_LOG("WARNING: Multiple writes to r%d\n", rnum); 69 } 70 ctx->reg_log[ctx->reg_log_idx] = rnum; 71 ctx->reg_log_idx++; 72 set_bit(rnum, ctx->regs_written); 73 } 74 75 static inline void ctx_log_reg_write_pair(DisasContext *ctx, int rnum) 76 { 77 ctx_log_reg_write(ctx, rnum); 78 ctx_log_reg_write(ctx, rnum + 1); 79 } 80 81 static inline void ctx_log_pred_write(DisasContext *ctx, int pnum) 82 { 83 ctx->preg_log[ctx->preg_log_idx] = pnum; 84 ctx->preg_log_idx++; 85 set_bit(pnum, ctx->pregs_written); 86 } 87 88 static inline bool is_preloaded(DisasContext *ctx, int num) 89 { 90 return test_bit(num, ctx->regs_written); 91 } 92 93 static inline bool is_vreg_preloaded(DisasContext *ctx, int num) 94 { 95 return test_bit(num, ctx->vregs_updated) || 96 test_bit(num, ctx->vregs_updated_tmp); 97 } 98 99 intptr_t ctx_future_vreg_off(DisasContext *ctx, int regnum, 100 int num, bool alloc_ok); 101 intptr_t ctx_tmp_vreg_off(DisasContext *ctx, int regnum, 102 int num, bool alloc_ok); 103 104 static inline void ctx_log_vreg_write(DisasContext *ctx, 105 int rnum, VRegWriteType type, 106 bool is_predicated) 107 { 108 if (type != EXT_TMP) { 109 ctx->vreg_log[ctx->vreg_log_idx] = rnum; 110 ctx->vreg_is_predicated[ctx->vreg_log_idx] = is_predicated; 111 ctx->vreg_log_idx++; 112 113 set_bit(rnum, ctx->vregs_updated); 114 } 115 if (type == EXT_NEW) { 116 set_bit(rnum, ctx->vregs_select); 117 } 118 if (type == EXT_TMP) { 119 set_bit(rnum, ctx->vregs_updated_tmp); 120 } 121 } 122 123 static inline void ctx_log_vreg_write_pair(DisasContext *ctx, 124 int rnum, VRegWriteType type, 125 bool is_predicated) 126 { 127 ctx_log_vreg_write(ctx, rnum ^ 0, type, is_predicated); 128 ctx_log_vreg_write(ctx, rnum ^ 1, type, is_predicated); 129 } 130 131 static inline void ctx_log_qreg_write(DisasContext *ctx, 132 int rnum, bool is_predicated) 133 { 134 ctx->qreg_log[ctx->qreg_log_idx] = rnum; 135 ctx->qreg_is_predicated[ctx->qreg_log_idx] = is_predicated; 136 ctx->qreg_log_idx++; 137 } 138 139 extern TCGv hex_gpr[TOTAL_PER_THREAD_REGS]; 140 extern TCGv hex_pred[NUM_PREGS]; 141 extern TCGv hex_this_PC; 142 extern TCGv hex_slot_cancelled; 143 extern TCGv hex_branch_taken; 144 extern TCGv hex_new_value[TOTAL_PER_THREAD_REGS]; 145 extern TCGv hex_reg_written[TOTAL_PER_THREAD_REGS]; 146 extern TCGv hex_new_pred_value[NUM_PREGS]; 147 extern TCGv hex_pred_written; 148 extern TCGv hex_store_addr[STORES_MAX]; 149 extern TCGv hex_store_width[STORES_MAX]; 150 extern TCGv hex_store_val32[STORES_MAX]; 151 extern TCGv_i64 hex_store_val64[STORES_MAX]; 152 extern TCGv hex_dczero_addr; 153 extern TCGv hex_llsc_addr; 154 extern TCGv hex_llsc_val; 155 extern TCGv_i64 hex_llsc_val_i64; 156 extern TCGv hex_VRegs_updated; 157 extern TCGv hex_QRegs_updated; 158 extern TCGv hex_vstore_addr[VSTORES_MAX]; 159 extern TCGv hex_vstore_size[VSTORES_MAX]; 160 extern TCGv hex_vstore_pending[VSTORES_MAX]; 161 162 bool is_gather_store_insn(DisasContext *ctx); 163 void process_store(DisasContext *ctx, int slot_num); 164 #endif 165