xref: /openbmc/qemu/target/hexagon/translate.h (revision 2e1cacfb)
1 /*
2  *  Copyright(c) 2019-2024 Qualcomm Innovation Center, Inc. All Rights Reserved.
3  *
4  *  This program is free software; you can redistribute it and/or modify
5  *  it under the terms of the GNU General Public License as published by
6  *  the Free Software Foundation; either version 2 of the License, or
7  *  (at your option) any later version.
8  *
9  *  This program is distributed in the hope that it will be useful,
10  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
11  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12  *  GNU General Public License for more details.
13  *
14  *  You should have received a copy of the GNU General Public License
15  *  along with this program; if not, see <http://www.gnu.org/licenses/>.
16  */
17 
18 #ifndef HEXAGON_TRANSLATE_H
19 #define HEXAGON_TRANSLATE_H
20 
21 #include "qemu/bitmap.h"
22 #include "qemu/log.h"
23 #include "cpu.h"
24 #include "exec/translator.h"
25 #include "tcg/tcg-op.h"
26 #include "insn.h"
27 #include "internal.h"
28 
29 typedef struct DisasContext {
30     DisasContextBase base;
31     Packet *pkt;
32     Insn *insn;
33     uint32_t next_PC;
34     uint32_t mem_idx;
35     uint32_t num_packets;
36     uint32_t num_insns;
37     uint32_t num_hvx_insns;
38     int reg_log[REG_WRITES_MAX];
39     int reg_log_idx;
40     DECLARE_BITMAP(regs_written, TOTAL_PER_THREAD_REGS);
41     DECLARE_BITMAP(predicated_regs, TOTAL_PER_THREAD_REGS);
42     int preg_log[PRED_WRITES_MAX];
43     int preg_log_idx;
44     DECLARE_BITMAP(pregs_written, NUM_PREGS);
45     uint8_t store_width[STORES_MAX];
46     bool s1_store_processed;
47     int future_vregs_idx;
48     int future_vregs_num[VECTOR_TEMPS_MAX];
49     int tmp_vregs_idx;
50     int tmp_vregs_num[VECTOR_TEMPS_MAX];
51     int vreg_log[NUM_VREGS];
52     int vreg_log_idx;
53     DECLARE_BITMAP(vregs_written, NUM_VREGS);
54     DECLARE_BITMAP(insn_vregs_written, NUM_VREGS);
55     DECLARE_BITMAP(vregs_updated_tmp, NUM_VREGS);
56     DECLARE_BITMAP(vregs_updated, NUM_VREGS);
57     DECLARE_BITMAP(vregs_select, NUM_VREGS);
58     DECLARE_BITMAP(predicated_future_vregs, NUM_VREGS);
59     DECLARE_BITMAP(predicated_tmp_vregs, NUM_VREGS);
60     DECLARE_BITMAP(insn_vregs_read, NUM_VREGS);
61     int qreg_log[NUM_QREGS];
62     int qreg_log_idx;
63     DECLARE_BITMAP(qregs_written, NUM_QREGS);
64     DECLARE_BITMAP(insn_qregs_written, NUM_QREGS);
65     DECLARE_BITMAP(insn_qregs_read, NUM_QREGS);
66     bool pre_commit;
67     bool need_commit;
68     TCGCond branch_cond;
69     target_ulong branch_dest;
70     bool is_tight_loop;
71     bool short_circuit;
72     bool read_after_write;
73     bool has_hvx_overlap;
74     TCGv new_value[TOTAL_PER_THREAD_REGS];
75     TCGv new_pred_value[NUM_PREGS];
76     TCGv pred_written;
77     TCGv branch_taken;
78     TCGv dczero_addr;
79 } DisasContext;
80 
81 bool is_gather_store_insn(DisasContext *ctx);
82 
83 static inline void ctx_log_pred_write(DisasContext *ctx, int pnum)
84 {
85     if (!test_bit(pnum, ctx->pregs_written)) {
86         ctx->preg_log[ctx->preg_log_idx] = pnum;
87         ctx->preg_log_idx++;
88         set_bit(pnum, ctx->pregs_written);
89     }
90 }
91 
92 static inline void ctx_log_pred_read(DisasContext *ctx, int pnum)
93 {
94     if (test_bit(pnum, ctx->pregs_written)) {
95         ctx->read_after_write = true;
96     }
97 }
98 
99 static inline void ctx_log_pred_read_new(DisasContext *ctx, int pnum)
100 {
101     g_assert(test_bit(pnum, ctx->pregs_written));
102 }
103 
104 static inline void ctx_log_reg_write(DisasContext *ctx, int rnum,
105                                      bool is_predicated)
106 {
107     if (rnum == HEX_REG_P3_0_ALIASED) {
108         for (int i = 0; i < NUM_PREGS; i++) {
109             ctx_log_pred_write(ctx, i);
110         }
111     } else {
112         if (!test_bit(rnum, ctx->regs_written)) {
113             ctx->reg_log[ctx->reg_log_idx] = rnum;
114             ctx->reg_log_idx++;
115             set_bit(rnum, ctx->regs_written);
116         }
117         if (is_predicated) {
118             set_bit(rnum, ctx->predicated_regs);
119         }
120     }
121 }
122 
123 static inline void ctx_log_reg_write_pair(DisasContext *ctx, int rnum,
124                                           bool is_predicated)
125 {
126     ctx_log_reg_write(ctx, rnum, is_predicated);
127     ctx_log_reg_write(ctx, rnum + 1, is_predicated);
128 }
129 
130 static inline void ctx_log_reg_read(DisasContext *ctx, int rnum)
131 {
132     if (test_bit(rnum, ctx->regs_written)) {
133         ctx->read_after_write = true;
134     }
135 }
136 
137 static inline void ctx_log_reg_read_new(DisasContext *ctx, int rnum)
138 {
139     g_assert(test_bit(rnum, ctx->regs_written));
140 }
141 
142 static inline void ctx_log_reg_read_pair(DisasContext *ctx, int rnum)
143 {
144     ctx_log_reg_read(ctx, rnum);
145     ctx_log_reg_read(ctx, rnum + 1);
146 }
147 
148 intptr_t ctx_future_vreg_off(DisasContext *ctx, int regnum,
149                              int num, bool alloc_ok);
150 intptr_t ctx_tmp_vreg_off(DisasContext *ctx, int regnum,
151                           int num, bool alloc_ok);
152 
153 static inline void ctx_start_hvx_insn(DisasContext *ctx)
154 {
155     bitmap_zero(ctx->insn_vregs_written, NUM_VREGS);
156     bitmap_zero(ctx->insn_vregs_read, NUM_VREGS);
157     bitmap_zero(ctx->insn_qregs_written, NUM_QREGS);
158     bitmap_zero(ctx->insn_qregs_read, NUM_QREGS);
159 }
160 
161 static inline void ctx_log_vreg_write(DisasContext *ctx,
162                                       int rnum, VRegWriteType type,
163                                       bool is_predicated, bool has_helper)
164 {
165     if (has_helper) {
166         set_bit(rnum, ctx->insn_vregs_written);
167         if (test_bit(rnum, ctx->insn_vregs_read)) {
168             ctx->has_hvx_overlap = true;
169         }
170     }
171     set_bit(rnum, ctx->vregs_written);
172     if (type != EXT_TMP) {
173         if (!test_bit(rnum, ctx->vregs_updated)) {
174             ctx->vreg_log[ctx->vreg_log_idx] = rnum;
175             ctx->vreg_log_idx++;
176             set_bit(rnum, ctx->vregs_updated);
177         }
178 
179         set_bit(rnum, ctx->vregs_updated);
180         if (is_predicated) {
181             set_bit(rnum, ctx->predicated_future_vregs);
182         }
183     }
184     if (type == EXT_NEW) {
185         set_bit(rnum, ctx->vregs_select);
186     }
187     if (type == EXT_TMP) {
188         set_bit(rnum, ctx->vregs_updated_tmp);
189         if (is_predicated) {
190             set_bit(rnum, ctx->predicated_tmp_vregs);
191         }
192     }
193 }
194 
195 static inline void ctx_log_vreg_write_pair(DisasContext *ctx,
196                                            int rnum, VRegWriteType type,
197                                            bool is_predicated, bool has_helper)
198 {
199     ctx_log_vreg_write(ctx, rnum ^ 0, type, is_predicated, has_helper);
200     ctx_log_vreg_write(ctx, rnum ^ 1, type, is_predicated, has_helper);
201 }
202 
203 static inline void ctx_log_vreg_read(DisasContext *ctx, int rnum,
204                                      bool has_helper)
205 {
206     if (has_helper) {
207         set_bit(rnum, ctx->insn_vregs_read);
208         if (test_bit(rnum, ctx->insn_vregs_written)) {
209             ctx->has_hvx_overlap = true;
210         }
211     }
212     if (test_bit(rnum, ctx->vregs_written)) {
213         ctx->read_after_write = true;
214     }
215 }
216 
217 static inline void ctx_log_vreg_read_new(DisasContext *ctx, int rnum,
218                                          bool has_helper)
219 {
220     g_assert(is_gather_store_insn(ctx) ||
221              test_bit(rnum, ctx->vregs_updated) ||
222              test_bit(rnum, ctx->vregs_select) ||
223              test_bit(rnum, ctx->vregs_updated_tmp));
224     if (has_helper) {
225         set_bit(rnum, ctx->insn_vregs_read);
226         if (test_bit(rnum, ctx->insn_vregs_written)) {
227             ctx->has_hvx_overlap = true;
228         }
229     }
230     if (is_gather_store_insn(ctx)) {
231         ctx->read_after_write = true;
232     }
233 }
234 
235 static inline void ctx_log_vreg_read_pair(DisasContext *ctx, int rnum,
236                                           bool has_helper)
237 {
238     ctx_log_vreg_read(ctx, rnum ^ 0, has_helper);
239     ctx_log_vreg_read(ctx, rnum ^ 1, has_helper);
240 }
241 
242 static inline void ctx_log_qreg_write(DisasContext *ctx,
243                                       int rnum, bool has_helper)
244 {
245     if (has_helper) {
246         set_bit(rnum, ctx->insn_qregs_written);
247         if (test_bit(rnum, ctx->insn_qregs_read)) {
248             ctx->has_hvx_overlap = true;
249         }
250     }
251     set_bit(rnum, ctx->qregs_written);
252     ctx->qreg_log[ctx->qreg_log_idx] = rnum;
253     ctx->qreg_log_idx++;
254 }
255 
256 static inline void ctx_log_qreg_read(DisasContext *ctx,
257                                      int qnum, bool has_helper)
258 {
259     if (has_helper) {
260         set_bit(qnum, ctx->insn_qregs_read);
261         if (test_bit(qnum, ctx->insn_qregs_written)) {
262             ctx->has_hvx_overlap = true;
263         }
264     }
265     if (test_bit(qnum, ctx->qregs_written)) {
266         ctx->read_after_write = true;
267     }
268 }
269 
270 extern TCGv hex_gpr[TOTAL_PER_THREAD_REGS];
271 extern TCGv hex_pred[NUM_PREGS];
272 extern TCGv hex_slot_cancelled;
273 extern TCGv hex_new_value_usr;
274 extern TCGv hex_reg_written[TOTAL_PER_THREAD_REGS];
275 extern TCGv hex_store_addr[STORES_MAX];
276 extern TCGv hex_store_width[STORES_MAX];
277 extern TCGv hex_store_val32[STORES_MAX];
278 extern TCGv_i64 hex_store_val64[STORES_MAX];
279 extern TCGv hex_llsc_addr;
280 extern TCGv hex_llsc_val;
281 extern TCGv_i64 hex_llsc_val_i64;
282 extern TCGv hex_vstore_addr[VSTORES_MAX];
283 extern TCGv hex_vstore_size[VSTORES_MAX];
284 extern TCGv hex_vstore_pending[VSTORES_MAX];
285 
286 void process_store(DisasContext *ctx, int slot_num);
287 
288 FIELD(PROBE_PKT_SCALAR_STORE_S0, MMU_IDX,       0, 2)
289 FIELD(PROBE_PKT_SCALAR_STORE_S0, IS_PREDICATED, 2, 1)
290 
291 FIELD(PROBE_PKT_SCALAR_HVX_STORES, HAS_ST0,        0, 1)
292 FIELD(PROBE_PKT_SCALAR_HVX_STORES, HAS_ST1,        1, 1)
293 FIELD(PROBE_PKT_SCALAR_HVX_STORES, HAS_HVX_STORES, 2, 1)
294 FIELD(PROBE_PKT_SCALAR_HVX_STORES, S0_IS_PRED,     3, 1)
295 FIELD(PROBE_PKT_SCALAR_HVX_STORES, S1_IS_PRED,     4, 1)
296 FIELD(PROBE_PKT_SCALAR_HVX_STORES, MMU_IDX,        5, 2)
297 
298 #endif
299