1 /* 2 * Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #define QEMU_GENERATE 19 #include "qemu/osdep.h" 20 #include "cpu.h" 21 #include "tcg/tcg-op.h" 22 #include "exec/cpu_ldst.h" 23 #include "exec/log.h" 24 #include "internal.h" 25 #include "attribs.h" 26 #include "insn.h" 27 #include "decode.h" 28 #include "translate.h" 29 #include "printinsn.h" 30 31 TCGv hex_gpr[TOTAL_PER_THREAD_REGS]; 32 TCGv hex_pred[NUM_PREGS]; 33 TCGv hex_next_PC; 34 TCGv hex_this_PC; 35 TCGv hex_slot_cancelled; 36 TCGv hex_branch_taken; 37 TCGv hex_new_value[TOTAL_PER_THREAD_REGS]; 38 TCGv hex_reg_written[TOTAL_PER_THREAD_REGS]; 39 TCGv hex_new_pred_value[NUM_PREGS]; 40 TCGv hex_pred_written; 41 TCGv hex_store_addr[STORES_MAX]; 42 TCGv hex_store_width[STORES_MAX]; 43 TCGv hex_store_val32[STORES_MAX]; 44 TCGv_i64 hex_store_val64[STORES_MAX]; 45 TCGv hex_pkt_has_store_s1; 46 TCGv hex_dczero_addr; 47 TCGv hex_llsc_addr; 48 TCGv hex_llsc_val; 49 TCGv_i64 hex_llsc_val_i64; 50 51 static const char * const hexagon_prednames[] = { 52 "p0", "p1", "p2", "p3" 53 }; 54 55 static void gen_exception_raw(int excp) 56 { 57 TCGv_i32 helper_tmp = tcg_const_i32(excp); 58 gen_helper_raise_exception(cpu_env, helper_tmp); 59 tcg_temp_free_i32(helper_tmp); 60 } 61 62 static void gen_exec_counters(DisasContext *ctx) 63 { 64 tcg_gen_addi_tl(hex_gpr[HEX_REG_QEMU_PKT_CNT], 65 hex_gpr[HEX_REG_QEMU_PKT_CNT], ctx->num_packets); 66 tcg_gen_addi_tl(hex_gpr[HEX_REG_QEMU_INSN_CNT], 67 hex_gpr[HEX_REG_QEMU_INSN_CNT], ctx->num_insns); 68 } 69 70 static void gen_end_tb(DisasContext *ctx) 71 { 72 gen_exec_counters(ctx); 73 tcg_gen_mov_tl(hex_gpr[HEX_REG_PC], hex_next_PC); 74 if (ctx->base.singlestep_enabled) { 75 gen_exception_raw(EXCP_DEBUG); 76 } else { 77 tcg_gen_exit_tb(NULL, 0); 78 } 79 ctx->base.is_jmp = DISAS_NORETURN; 80 } 81 82 static void gen_exception_end_tb(DisasContext *ctx, int excp) 83 { 84 gen_exec_counters(ctx); 85 tcg_gen_mov_tl(hex_gpr[HEX_REG_PC], hex_next_PC); 86 gen_exception_raw(excp); 87 ctx->base.is_jmp = DISAS_NORETURN; 88 89 } 90 91 #define PACKET_BUFFER_LEN 1028 92 static void print_pkt(Packet *pkt) 93 { 94 GString *buf = g_string_sized_new(PACKET_BUFFER_LEN); 95 snprint_a_pkt_debug(buf, pkt); 96 HEX_DEBUG_LOG("%s", buf->str); 97 g_string_free(buf, true); 98 } 99 #define HEX_DEBUG_PRINT_PKT(pkt) \ 100 do { \ 101 if (HEX_DEBUG) { \ 102 print_pkt(pkt); \ 103 } \ 104 } while (0) 105 106 static int read_packet_words(CPUHexagonState *env, DisasContext *ctx, 107 uint32_t words[]) 108 { 109 bool found_end = false; 110 int nwords, max_words; 111 112 memset(words, 0, PACKET_WORDS_MAX * sizeof(uint32_t)); 113 for (nwords = 0; !found_end && nwords < PACKET_WORDS_MAX; nwords++) { 114 words[nwords] = 115 translator_ldl(env, ctx->base.pc_next + nwords * sizeof(uint32_t)); 116 found_end = is_packet_end(words[nwords]); 117 } 118 if (!found_end) { 119 /* Read too many words without finding the end */ 120 return 0; 121 } 122 123 /* Check for page boundary crossing */ 124 max_words = -(ctx->base.pc_next | TARGET_PAGE_MASK) / sizeof(uint32_t); 125 if (nwords > max_words) { 126 /* We can only cross a page boundary at the beginning of a TB */ 127 g_assert(ctx->base.num_insns == 1); 128 } 129 130 HEX_DEBUG_LOG("decode_packet: pc = 0x%x\n", ctx->base.pc_next); 131 HEX_DEBUG_LOG(" words = { "); 132 for (int i = 0; i < nwords; i++) { 133 HEX_DEBUG_LOG("0x%x, ", words[i]); 134 } 135 HEX_DEBUG_LOG("}\n"); 136 137 return nwords; 138 } 139 140 static bool check_for_attrib(Packet *pkt, int attrib) 141 { 142 for (int i = 0; i < pkt->num_insns; i++) { 143 if (GET_ATTRIB(pkt->insn[i].opcode, attrib)) { 144 return true; 145 } 146 } 147 return false; 148 } 149 150 static bool need_pc(Packet *pkt) 151 { 152 return check_for_attrib(pkt, A_IMPLICIT_READS_PC); 153 } 154 155 static bool need_slot_cancelled(Packet *pkt) 156 { 157 return check_for_attrib(pkt, A_CONDEXEC); 158 } 159 160 static bool need_pred_written(Packet *pkt) 161 { 162 return check_for_attrib(pkt, A_WRITES_PRED_REG); 163 } 164 165 static void gen_start_packet(DisasContext *ctx, Packet *pkt) 166 { 167 target_ulong next_PC = ctx->base.pc_next + pkt->encod_pkt_size_in_bytes; 168 int i; 169 170 /* Clear out the disassembly context */ 171 ctx->reg_log_idx = 0; 172 bitmap_zero(ctx->regs_written, TOTAL_PER_THREAD_REGS); 173 ctx->preg_log_idx = 0; 174 bitmap_zero(ctx->pregs_written, NUM_PREGS); 175 for (i = 0; i < STORES_MAX; i++) { 176 ctx->store_width[i] = 0; 177 } 178 tcg_gen_movi_tl(hex_pkt_has_store_s1, pkt->pkt_has_store_s1); 179 ctx->s1_store_processed = false; 180 181 if (HEX_DEBUG) { 182 /* Handy place to set a breakpoint before the packet executes */ 183 gen_helper_debug_start_packet(cpu_env); 184 tcg_gen_movi_tl(hex_this_PC, ctx->base.pc_next); 185 } 186 187 /* Initialize the runtime state for packet semantics */ 188 if (need_pc(pkt)) { 189 tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], ctx->base.pc_next); 190 } 191 if (need_slot_cancelled(pkt)) { 192 tcg_gen_movi_tl(hex_slot_cancelled, 0); 193 } 194 if (pkt->pkt_has_cof) { 195 tcg_gen_movi_tl(hex_branch_taken, 0); 196 tcg_gen_movi_tl(hex_next_PC, next_PC); 197 } 198 if (need_pred_written(pkt)) { 199 tcg_gen_movi_tl(hex_pred_written, 0); 200 } 201 } 202 203 /* 204 * The LOG_*_WRITE macros mark most of the writes in a packet 205 * However, there are some implicit writes marked as attributes 206 * of the applicable instructions. 207 */ 208 static void mark_implicit_reg_write(DisasContext *ctx, Insn *insn, 209 int attrib, int rnum) 210 { 211 if (GET_ATTRIB(insn->opcode, attrib)) { 212 bool is_predicated = GET_ATTRIB(insn->opcode, A_CONDEXEC); 213 if (is_predicated && !is_preloaded(ctx, rnum)) { 214 tcg_gen_mov_tl(hex_new_value[rnum], hex_gpr[rnum]); 215 } 216 217 ctx_log_reg_write(ctx, rnum); 218 } 219 } 220 221 static void mark_implicit_pred_write(DisasContext *ctx, Insn *insn, 222 int attrib, int pnum) 223 { 224 if (GET_ATTRIB(insn->opcode, attrib)) { 225 ctx_log_pred_write(ctx, pnum); 226 } 227 } 228 229 static void mark_implicit_reg_writes(DisasContext *ctx, Insn *insn) 230 { 231 mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_FP, HEX_REG_FP); 232 mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_SP, HEX_REG_SP); 233 mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_LR, HEX_REG_LR); 234 mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_LC0, HEX_REG_LC0); 235 mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_SA0, HEX_REG_SA0); 236 mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_LC1, HEX_REG_LC1); 237 mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_SA1, HEX_REG_SA1); 238 } 239 240 static void mark_implicit_pred_writes(DisasContext *ctx, Insn *insn) 241 { 242 mark_implicit_pred_write(ctx, insn, A_IMPLICIT_WRITES_P0, 0); 243 mark_implicit_pred_write(ctx, insn, A_IMPLICIT_WRITES_P1, 1); 244 mark_implicit_pred_write(ctx, insn, A_IMPLICIT_WRITES_P2, 2); 245 mark_implicit_pred_write(ctx, insn, A_IMPLICIT_WRITES_P3, 3); 246 } 247 248 static void gen_insn(CPUHexagonState *env, DisasContext *ctx, 249 Insn *insn, Packet *pkt) 250 { 251 if (insn->generate) { 252 mark_implicit_reg_writes(ctx, insn); 253 insn->generate(env, ctx, insn, pkt); 254 mark_implicit_pred_writes(ctx, insn); 255 } else { 256 gen_exception_end_tb(ctx, HEX_EXCP_INVALID_OPCODE); 257 } 258 } 259 260 /* 261 * Helpers for generating the packet commit 262 */ 263 static void gen_reg_writes(DisasContext *ctx) 264 { 265 int i; 266 267 for (i = 0; i < ctx->reg_log_idx; i++) { 268 int reg_num = ctx->reg_log[i]; 269 270 tcg_gen_mov_tl(hex_gpr[reg_num], hex_new_value[reg_num]); 271 } 272 } 273 274 static void gen_pred_writes(DisasContext *ctx, Packet *pkt) 275 { 276 TCGv zero, control_reg, pval; 277 int i; 278 279 /* Early exit if the log is empty */ 280 if (!ctx->preg_log_idx) { 281 return; 282 } 283 284 zero = tcg_const_tl(0); 285 control_reg = tcg_temp_new(); 286 pval = tcg_temp_new(); 287 288 /* 289 * Only endloop instructions will conditionally 290 * write a predicate. If there are no endloop 291 * instructions, we can use the non-conditional 292 * write of the predicates. 293 */ 294 if (pkt->pkt_has_endloop) { 295 TCGv pred_written = tcg_temp_new(); 296 for (i = 0; i < ctx->preg_log_idx; i++) { 297 int pred_num = ctx->preg_log[i]; 298 299 tcg_gen_andi_tl(pred_written, hex_pred_written, 1 << pred_num); 300 tcg_gen_movcond_tl(TCG_COND_NE, hex_pred[pred_num], 301 pred_written, zero, 302 hex_new_pred_value[pred_num], 303 hex_pred[pred_num]); 304 } 305 tcg_temp_free(pred_written); 306 } else { 307 for (i = 0; i < ctx->preg_log_idx; i++) { 308 int pred_num = ctx->preg_log[i]; 309 tcg_gen_mov_tl(hex_pred[pred_num], hex_new_pred_value[pred_num]); 310 if (HEX_DEBUG) { 311 /* Do this so HELPER(debug_commit_end) will know */ 312 tcg_gen_ori_tl(hex_pred_written, hex_pred_written, 313 1 << pred_num); 314 } 315 } 316 } 317 318 tcg_temp_free(zero); 319 tcg_temp_free(control_reg); 320 tcg_temp_free(pval); 321 } 322 323 static void gen_check_store_width(DisasContext *ctx, int slot_num) 324 { 325 if (HEX_DEBUG) { 326 TCGv slot = tcg_const_tl(slot_num); 327 TCGv check = tcg_const_tl(ctx->store_width[slot_num]); 328 gen_helper_debug_check_store_width(cpu_env, slot, check); 329 tcg_temp_free(slot); 330 tcg_temp_free(check); 331 } 332 } 333 334 static bool slot_is_predicated(Packet *pkt, int slot_num) 335 { 336 for (int i = 0; i < pkt->num_insns; i++) { 337 if (pkt->insn[i].slot == slot_num) { 338 return GET_ATTRIB(pkt->insn[i].opcode, A_CONDEXEC); 339 } 340 } 341 /* If we get to here, we didn't find an instruction in the requested slot */ 342 g_assert_not_reached(); 343 } 344 345 void process_store(DisasContext *ctx, Packet *pkt, int slot_num) 346 { 347 bool is_predicated = slot_is_predicated(pkt, slot_num); 348 TCGLabel *label_end = NULL; 349 350 /* 351 * We may have already processed this store 352 * See CHECK_NOSHUF in macros.h 353 */ 354 if (slot_num == 1 && ctx->s1_store_processed) { 355 return; 356 } 357 ctx->s1_store_processed = true; 358 359 if (is_predicated) { 360 TCGv cancelled = tcg_temp_new(); 361 label_end = gen_new_label(); 362 363 /* Don't do anything if the slot was cancelled */ 364 tcg_gen_extract_tl(cancelled, hex_slot_cancelled, slot_num, 1); 365 tcg_gen_brcondi_tl(TCG_COND_NE, cancelled, 0, label_end); 366 tcg_temp_free(cancelled); 367 } 368 { 369 TCGv address = tcg_temp_local_new(); 370 tcg_gen_mov_tl(address, hex_store_addr[slot_num]); 371 372 /* 373 * If we know the width from the DisasContext, we can 374 * generate much cleaner code. 375 * Unfortunately, not all instructions execute the fSTORE 376 * macro during code generation. Anything that uses the 377 * generic helper will have this problem. Instructions 378 * that use fWRAP to generate proper TCG code will be OK. 379 */ 380 switch (ctx->store_width[slot_num]) { 381 case 1: 382 gen_check_store_width(ctx, slot_num); 383 tcg_gen_qemu_st8(hex_store_val32[slot_num], 384 hex_store_addr[slot_num], 385 ctx->mem_idx); 386 break; 387 case 2: 388 gen_check_store_width(ctx, slot_num); 389 tcg_gen_qemu_st16(hex_store_val32[slot_num], 390 hex_store_addr[slot_num], 391 ctx->mem_idx); 392 break; 393 case 4: 394 gen_check_store_width(ctx, slot_num); 395 tcg_gen_qemu_st32(hex_store_val32[slot_num], 396 hex_store_addr[slot_num], 397 ctx->mem_idx); 398 break; 399 case 8: 400 gen_check_store_width(ctx, slot_num); 401 tcg_gen_qemu_st64(hex_store_val64[slot_num], 402 hex_store_addr[slot_num], 403 ctx->mem_idx); 404 break; 405 default: 406 { 407 /* 408 * If we get to here, we don't know the width at 409 * TCG generation time, we'll use a helper to 410 * avoid branching based on the width at runtime. 411 */ 412 TCGv slot = tcg_const_tl(slot_num); 413 gen_helper_commit_store(cpu_env, slot); 414 tcg_temp_free(slot); 415 } 416 } 417 tcg_temp_free(address); 418 } 419 if (is_predicated) { 420 gen_set_label(label_end); 421 } 422 } 423 424 static void process_store_log(DisasContext *ctx, Packet *pkt) 425 { 426 /* 427 * When a packet has two stores, the hardware processes 428 * slot 1 and then slot 2. This will be important when 429 * the memory accesses overlap. 430 */ 431 if (pkt->pkt_has_store_s1 && !pkt->pkt_has_dczeroa) { 432 process_store(ctx, pkt, 1); 433 } 434 if (pkt->pkt_has_store_s0 && !pkt->pkt_has_dczeroa) { 435 process_store(ctx, pkt, 0); 436 } 437 } 438 439 /* Zero out a 32-bit cache line */ 440 static void process_dczeroa(DisasContext *ctx, Packet *pkt) 441 { 442 if (pkt->pkt_has_dczeroa) { 443 /* Store 32 bytes of zero starting at (addr & ~0x1f) */ 444 TCGv addr = tcg_temp_new(); 445 TCGv_i64 zero = tcg_const_i64(0); 446 447 tcg_gen_andi_tl(addr, hex_dczero_addr, ~0x1f); 448 tcg_gen_qemu_st64(zero, addr, ctx->mem_idx); 449 tcg_gen_addi_tl(addr, addr, 8); 450 tcg_gen_qemu_st64(zero, addr, ctx->mem_idx); 451 tcg_gen_addi_tl(addr, addr, 8); 452 tcg_gen_qemu_st64(zero, addr, ctx->mem_idx); 453 tcg_gen_addi_tl(addr, addr, 8); 454 tcg_gen_qemu_st64(zero, addr, ctx->mem_idx); 455 456 tcg_temp_free(addr); 457 tcg_temp_free_i64(zero); 458 } 459 } 460 461 static void update_exec_counters(DisasContext *ctx, Packet *pkt) 462 { 463 int num_insns = pkt->num_insns; 464 int num_real_insns = 0; 465 466 for (int i = 0; i < num_insns; i++) { 467 if (!pkt->insn[i].is_endloop && 468 !pkt->insn[i].part1 && 469 !GET_ATTRIB(pkt->insn[i].opcode, A_IT_NOP)) { 470 num_real_insns++; 471 } 472 } 473 474 ctx->num_packets++; 475 ctx->num_insns += num_real_insns; 476 } 477 478 static void gen_commit_packet(DisasContext *ctx, Packet *pkt) 479 { 480 gen_reg_writes(ctx); 481 gen_pred_writes(ctx, pkt); 482 process_store_log(ctx, pkt); 483 process_dczeroa(ctx, pkt); 484 update_exec_counters(ctx, pkt); 485 if (HEX_DEBUG) { 486 TCGv has_st0 = 487 tcg_const_tl(pkt->pkt_has_store_s0 && !pkt->pkt_has_dczeroa); 488 TCGv has_st1 = 489 tcg_const_tl(pkt->pkt_has_store_s1 && !pkt->pkt_has_dczeroa); 490 491 /* Handy place to set a breakpoint at the end of execution */ 492 gen_helper_debug_commit_end(cpu_env, has_st0, has_st1); 493 494 tcg_temp_free(has_st0); 495 tcg_temp_free(has_st1); 496 } 497 498 if (pkt->pkt_has_cof) { 499 gen_end_tb(ctx); 500 } 501 } 502 503 static void decode_and_translate_packet(CPUHexagonState *env, DisasContext *ctx) 504 { 505 uint32_t words[PACKET_WORDS_MAX]; 506 int nwords; 507 Packet pkt; 508 int i; 509 510 nwords = read_packet_words(env, ctx, words); 511 if (!nwords) { 512 gen_exception_end_tb(ctx, HEX_EXCP_INVALID_PACKET); 513 return; 514 } 515 516 if (decode_packet(nwords, words, &pkt, false) > 0) { 517 HEX_DEBUG_PRINT_PKT(&pkt); 518 gen_start_packet(ctx, &pkt); 519 for (i = 0; i < pkt.num_insns; i++) { 520 gen_insn(env, ctx, &pkt.insn[i], &pkt); 521 } 522 gen_commit_packet(ctx, &pkt); 523 ctx->base.pc_next += pkt.encod_pkt_size_in_bytes; 524 } else { 525 gen_exception_end_tb(ctx, HEX_EXCP_INVALID_PACKET); 526 } 527 } 528 529 static void hexagon_tr_init_disas_context(DisasContextBase *dcbase, 530 CPUState *cs) 531 { 532 DisasContext *ctx = container_of(dcbase, DisasContext, base); 533 534 ctx->mem_idx = MMU_USER_IDX; 535 ctx->num_packets = 0; 536 ctx->num_insns = 0; 537 } 538 539 static void hexagon_tr_tb_start(DisasContextBase *db, CPUState *cpu) 540 { 541 } 542 543 static void hexagon_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) 544 { 545 DisasContext *ctx = container_of(dcbase, DisasContext, base); 546 547 tcg_gen_insn_start(ctx->base.pc_next); 548 } 549 550 static bool hexagon_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu, 551 const CPUBreakpoint *bp) 552 { 553 DisasContext *ctx = container_of(dcbase, DisasContext, base); 554 555 gen_exception_end_tb(ctx, EXCP_DEBUG); 556 /* 557 * The address covered by the breakpoint must be included in 558 * [tb->pc, tb->pc + tb->size) in order to for it to be 559 * properly cleared -- thus we increment the PC here so that 560 * the logic setting tb->size below does the right thing. 561 */ 562 ctx->base.pc_next += 4; 563 return true; 564 } 565 566 static bool pkt_crosses_page(CPUHexagonState *env, DisasContext *ctx) 567 { 568 target_ulong page_start = ctx->base.pc_first & TARGET_PAGE_MASK; 569 bool found_end = false; 570 int nwords; 571 572 for (nwords = 0; !found_end && nwords < PACKET_WORDS_MAX; nwords++) { 573 uint32_t word = cpu_ldl_code(env, 574 ctx->base.pc_next + nwords * sizeof(uint32_t)); 575 found_end = is_packet_end(word); 576 } 577 uint32_t next_ptr = ctx->base.pc_next + nwords * sizeof(uint32_t); 578 return found_end && next_ptr - page_start >= TARGET_PAGE_SIZE; 579 } 580 581 static void hexagon_tr_translate_packet(DisasContextBase *dcbase, CPUState *cpu) 582 { 583 DisasContext *ctx = container_of(dcbase, DisasContext, base); 584 CPUHexagonState *env = cpu->env_ptr; 585 586 decode_and_translate_packet(env, ctx); 587 588 if (ctx->base.is_jmp == DISAS_NEXT) { 589 target_ulong page_start = ctx->base.pc_first & TARGET_PAGE_MASK; 590 target_ulong bytes_max = PACKET_WORDS_MAX * sizeof(target_ulong); 591 592 if (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE || 593 (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE - bytes_max && 594 pkt_crosses_page(env, ctx))) { 595 ctx->base.is_jmp = DISAS_TOO_MANY; 596 } 597 598 /* 599 * The CPU log is used to compare against LLDB single stepping, 600 * so end the TLB after every packet. 601 */ 602 HexagonCPU *hex_cpu = env_archcpu(env); 603 if (hex_cpu->lldb_compat && qemu_loglevel_mask(CPU_LOG_TB_CPU)) { 604 ctx->base.is_jmp = DISAS_TOO_MANY; 605 } 606 } 607 } 608 609 static void hexagon_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) 610 { 611 DisasContext *ctx = container_of(dcbase, DisasContext, base); 612 613 switch (ctx->base.is_jmp) { 614 case DISAS_TOO_MANY: 615 gen_exec_counters(ctx); 616 tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], ctx->base.pc_next); 617 if (ctx->base.singlestep_enabled) { 618 gen_exception_raw(EXCP_DEBUG); 619 } else { 620 tcg_gen_exit_tb(NULL, 0); 621 } 622 break; 623 case DISAS_NORETURN: 624 break; 625 default: 626 g_assert_not_reached(); 627 } 628 } 629 630 static void hexagon_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu) 631 { 632 qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); 633 log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size); 634 } 635 636 637 static const TranslatorOps hexagon_tr_ops = { 638 .init_disas_context = hexagon_tr_init_disas_context, 639 .tb_start = hexagon_tr_tb_start, 640 .insn_start = hexagon_tr_insn_start, 641 .breakpoint_check = hexagon_tr_breakpoint_check, 642 .translate_insn = hexagon_tr_translate_packet, 643 .tb_stop = hexagon_tr_tb_stop, 644 .disas_log = hexagon_tr_disas_log, 645 }; 646 647 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) 648 { 649 DisasContext ctx; 650 651 translator_loop(&hexagon_tr_ops, &ctx.base, cs, tb, max_insns); 652 } 653 654 #define NAME_LEN 64 655 static char new_value_names[TOTAL_PER_THREAD_REGS][NAME_LEN]; 656 static char reg_written_names[TOTAL_PER_THREAD_REGS][NAME_LEN]; 657 static char new_pred_value_names[NUM_PREGS][NAME_LEN]; 658 static char store_addr_names[STORES_MAX][NAME_LEN]; 659 static char store_width_names[STORES_MAX][NAME_LEN]; 660 static char store_val32_names[STORES_MAX][NAME_LEN]; 661 static char store_val64_names[STORES_MAX][NAME_LEN]; 662 663 void hexagon_translate_init(void) 664 { 665 int i; 666 667 opcode_init(); 668 669 if (HEX_DEBUG) { 670 if (!qemu_logfile) { 671 qemu_set_log(qemu_loglevel); 672 } 673 } 674 675 for (i = 0; i < TOTAL_PER_THREAD_REGS; i++) { 676 hex_gpr[i] = tcg_global_mem_new(cpu_env, 677 offsetof(CPUHexagonState, gpr[i]), 678 hexagon_regnames[i]); 679 680 snprintf(new_value_names[i], NAME_LEN, "new_%s", hexagon_regnames[i]); 681 hex_new_value[i] = tcg_global_mem_new(cpu_env, 682 offsetof(CPUHexagonState, new_value[i]), 683 new_value_names[i]); 684 685 if (HEX_DEBUG) { 686 snprintf(reg_written_names[i], NAME_LEN, "reg_written_%s", 687 hexagon_regnames[i]); 688 hex_reg_written[i] = tcg_global_mem_new(cpu_env, 689 offsetof(CPUHexagonState, reg_written[i]), 690 reg_written_names[i]); 691 } 692 } 693 for (i = 0; i < NUM_PREGS; i++) { 694 hex_pred[i] = tcg_global_mem_new(cpu_env, 695 offsetof(CPUHexagonState, pred[i]), 696 hexagon_prednames[i]); 697 698 snprintf(new_pred_value_names[i], NAME_LEN, "new_pred_%s", 699 hexagon_prednames[i]); 700 hex_new_pred_value[i] = tcg_global_mem_new(cpu_env, 701 offsetof(CPUHexagonState, new_pred_value[i]), 702 new_pred_value_names[i]); 703 } 704 hex_pred_written = tcg_global_mem_new(cpu_env, 705 offsetof(CPUHexagonState, pred_written), "pred_written"); 706 hex_next_PC = tcg_global_mem_new(cpu_env, 707 offsetof(CPUHexagonState, next_PC), "next_PC"); 708 hex_this_PC = tcg_global_mem_new(cpu_env, 709 offsetof(CPUHexagonState, this_PC), "this_PC"); 710 hex_slot_cancelled = tcg_global_mem_new(cpu_env, 711 offsetof(CPUHexagonState, slot_cancelled), "slot_cancelled"); 712 hex_branch_taken = tcg_global_mem_new(cpu_env, 713 offsetof(CPUHexagonState, branch_taken), "branch_taken"); 714 hex_pkt_has_store_s1 = tcg_global_mem_new(cpu_env, 715 offsetof(CPUHexagonState, pkt_has_store_s1), "pkt_has_store_s1"); 716 hex_dczero_addr = tcg_global_mem_new(cpu_env, 717 offsetof(CPUHexagonState, dczero_addr), "dczero_addr"); 718 hex_llsc_addr = tcg_global_mem_new(cpu_env, 719 offsetof(CPUHexagonState, llsc_addr), "llsc_addr"); 720 hex_llsc_val = tcg_global_mem_new(cpu_env, 721 offsetof(CPUHexagonState, llsc_val), "llsc_val"); 722 hex_llsc_val_i64 = tcg_global_mem_new_i64(cpu_env, 723 offsetof(CPUHexagonState, llsc_val_i64), "llsc_val_i64"); 724 for (i = 0; i < STORES_MAX; i++) { 725 snprintf(store_addr_names[i], NAME_LEN, "store_addr_%d", i); 726 hex_store_addr[i] = tcg_global_mem_new(cpu_env, 727 offsetof(CPUHexagonState, mem_log_stores[i].va), 728 store_addr_names[i]); 729 730 snprintf(store_width_names[i], NAME_LEN, "store_width_%d", i); 731 hex_store_width[i] = tcg_global_mem_new(cpu_env, 732 offsetof(CPUHexagonState, mem_log_stores[i].width), 733 store_width_names[i]); 734 735 snprintf(store_val32_names[i], NAME_LEN, "store_val32_%d", i); 736 hex_store_val32[i] = tcg_global_mem_new(cpu_env, 737 offsetof(CPUHexagonState, mem_log_stores[i].data32), 738 store_val32_names[i]); 739 740 snprintf(store_val64_names[i], NAME_LEN, "store_val64_%d", i); 741 hex_store_val64[i] = tcg_global_mem_new_i64(cpu_env, 742 offsetof(CPUHexagonState, mem_log_stores[i].data64), 743 store_val64_names[i]); 744 } 745 } 746