1 /* 2 * Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #define QEMU_GENERATE 19 #include "qemu/osdep.h" 20 #include "cpu.h" 21 #include "tcg/tcg-op.h" 22 #include "exec/cpu_ldst.h" 23 #include "exec/log.h" 24 #include "internal.h" 25 #include "attribs.h" 26 #include "insn.h" 27 #include "decode.h" 28 #include "translate.h" 29 #include "printinsn.h" 30 31 TCGv hex_gpr[TOTAL_PER_THREAD_REGS]; 32 TCGv hex_pred[NUM_PREGS]; 33 TCGv hex_next_PC; 34 TCGv hex_this_PC; 35 TCGv hex_slot_cancelled; 36 TCGv hex_branch_taken; 37 TCGv hex_new_value[TOTAL_PER_THREAD_REGS]; 38 TCGv hex_reg_written[TOTAL_PER_THREAD_REGS]; 39 TCGv hex_new_pred_value[NUM_PREGS]; 40 TCGv hex_pred_written; 41 TCGv hex_store_addr[STORES_MAX]; 42 TCGv hex_store_width[STORES_MAX]; 43 TCGv hex_store_val32[STORES_MAX]; 44 TCGv_i64 hex_store_val64[STORES_MAX]; 45 TCGv hex_pkt_has_store_s1; 46 TCGv hex_dczero_addr; 47 TCGv hex_llsc_addr; 48 TCGv hex_llsc_val; 49 TCGv_i64 hex_llsc_val_i64; 50 51 static const char * const hexagon_prednames[] = { 52 "p0", "p1", "p2", "p3" 53 }; 54 55 static void gen_exception_raw(int excp) 56 { 57 gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); 58 } 59 60 static void gen_exec_counters(DisasContext *ctx) 61 { 62 tcg_gen_addi_tl(hex_gpr[HEX_REG_QEMU_PKT_CNT], 63 hex_gpr[HEX_REG_QEMU_PKT_CNT], ctx->num_packets); 64 tcg_gen_addi_tl(hex_gpr[HEX_REG_QEMU_INSN_CNT], 65 hex_gpr[HEX_REG_QEMU_INSN_CNT], ctx->num_insns); 66 } 67 68 static void gen_end_tb(DisasContext *ctx) 69 { 70 gen_exec_counters(ctx); 71 tcg_gen_mov_tl(hex_gpr[HEX_REG_PC], hex_next_PC); 72 tcg_gen_exit_tb(NULL, 0); 73 ctx->base.is_jmp = DISAS_NORETURN; 74 } 75 76 static void gen_exception_end_tb(DisasContext *ctx, int excp) 77 { 78 gen_exec_counters(ctx); 79 tcg_gen_mov_tl(hex_gpr[HEX_REG_PC], hex_next_PC); 80 gen_exception_raw(excp); 81 ctx->base.is_jmp = DISAS_NORETURN; 82 83 } 84 85 #define PACKET_BUFFER_LEN 1028 86 static void print_pkt(Packet *pkt) 87 { 88 GString *buf = g_string_sized_new(PACKET_BUFFER_LEN); 89 snprint_a_pkt_debug(buf, pkt); 90 HEX_DEBUG_LOG("%s", buf->str); 91 g_string_free(buf, true); 92 } 93 #define HEX_DEBUG_PRINT_PKT(pkt) \ 94 do { \ 95 if (HEX_DEBUG) { \ 96 print_pkt(pkt); \ 97 } \ 98 } while (0) 99 100 static int read_packet_words(CPUHexagonState *env, DisasContext *ctx, 101 uint32_t words[]) 102 { 103 bool found_end = false; 104 int nwords, max_words; 105 106 memset(words, 0, PACKET_WORDS_MAX * sizeof(uint32_t)); 107 for (nwords = 0; !found_end && nwords < PACKET_WORDS_MAX; nwords++) { 108 words[nwords] = 109 translator_ldl(env, &ctx->base, 110 ctx->base.pc_next + nwords * sizeof(uint32_t)); 111 found_end = is_packet_end(words[nwords]); 112 } 113 if (!found_end) { 114 /* Read too many words without finding the end */ 115 return 0; 116 } 117 118 /* Check for page boundary crossing */ 119 max_words = -(ctx->base.pc_next | TARGET_PAGE_MASK) / sizeof(uint32_t); 120 if (nwords > max_words) { 121 /* We can only cross a page boundary at the beginning of a TB */ 122 g_assert(ctx->base.num_insns == 1); 123 } 124 125 HEX_DEBUG_LOG("decode_packet: pc = 0x%x\n", ctx->base.pc_next); 126 HEX_DEBUG_LOG(" words = { "); 127 for (int i = 0; i < nwords; i++) { 128 HEX_DEBUG_LOG("0x%x, ", words[i]); 129 } 130 HEX_DEBUG_LOG("}\n"); 131 132 return nwords; 133 } 134 135 static bool check_for_attrib(Packet *pkt, int attrib) 136 { 137 for (int i = 0; i < pkt->num_insns; i++) { 138 if (GET_ATTRIB(pkt->insn[i].opcode, attrib)) { 139 return true; 140 } 141 } 142 return false; 143 } 144 145 static bool need_pc(Packet *pkt) 146 { 147 return check_for_attrib(pkt, A_IMPLICIT_READS_PC); 148 } 149 150 static bool need_slot_cancelled(Packet *pkt) 151 { 152 return check_for_attrib(pkt, A_CONDEXEC); 153 } 154 155 static bool need_pred_written(Packet *pkt) 156 { 157 return check_for_attrib(pkt, A_WRITES_PRED_REG); 158 } 159 160 static void gen_start_packet(DisasContext *ctx, Packet *pkt) 161 { 162 target_ulong next_PC = ctx->base.pc_next + pkt->encod_pkt_size_in_bytes; 163 int i; 164 165 /* Clear out the disassembly context */ 166 ctx->reg_log_idx = 0; 167 bitmap_zero(ctx->regs_written, TOTAL_PER_THREAD_REGS); 168 ctx->preg_log_idx = 0; 169 bitmap_zero(ctx->pregs_written, NUM_PREGS); 170 for (i = 0; i < STORES_MAX; i++) { 171 ctx->store_width[i] = 0; 172 } 173 tcg_gen_movi_tl(hex_pkt_has_store_s1, pkt->pkt_has_store_s1); 174 ctx->s1_store_processed = false; 175 176 if (HEX_DEBUG) { 177 /* Handy place to set a breakpoint before the packet executes */ 178 gen_helper_debug_start_packet(cpu_env); 179 tcg_gen_movi_tl(hex_this_PC, ctx->base.pc_next); 180 } 181 182 /* Initialize the runtime state for packet semantics */ 183 if (need_pc(pkt)) { 184 tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], ctx->base.pc_next); 185 } 186 if (need_slot_cancelled(pkt)) { 187 tcg_gen_movi_tl(hex_slot_cancelled, 0); 188 } 189 if (pkt->pkt_has_cof) { 190 tcg_gen_movi_tl(hex_branch_taken, 0); 191 tcg_gen_movi_tl(hex_next_PC, next_PC); 192 } 193 if (need_pred_written(pkt)) { 194 tcg_gen_movi_tl(hex_pred_written, 0); 195 } 196 } 197 198 /* 199 * The LOG_*_WRITE macros mark most of the writes in a packet 200 * However, there are some implicit writes marked as attributes 201 * of the applicable instructions. 202 */ 203 static void mark_implicit_reg_write(DisasContext *ctx, Insn *insn, 204 int attrib, int rnum) 205 { 206 if (GET_ATTRIB(insn->opcode, attrib)) { 207 bool is_predicated = GET_ATTRIB(insn->opcode, A_CONDEXEC); 208 if (is_predicated && !is_preloaded(ctx, rnum)) { 209 tcg_gen_mov_tl(hex_new_value[rnum], hex_gpr[rnum]); 210 } 211 212 ctx_log_reg_write(ctx, rnum); 213 } 214 } 215 216 static void mark_implicit_pred_write(DisasContext *ctx, Insn *insn, 217 int attrib, int pnum) 218 { 219 if (GET_ATTRIB(insn->opcode, attrib)) { 220 ctx_log_pred_write(ctx, pnum); 221 } 222 } 223 224 static void mark_implicit_reg_writes(DisasContext *ctx, Insn *insn) 225 { 226 mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_FP, HEX_REG_FP); 227 mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_SP, HEX_REG_SP); 228 mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_LR, HEX_REG_LR); 229 mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_LC0, HEX_REG_LC0); 230 mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_SA0, HEX_REG_SA0); 231 mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_LC1, HEX_REG_LC1); 232 mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_SA1, HEX_REG_SA1); 233 } 234 235 static void mark_implicit_pred_writes(DisasContext *ctx, Insn *insn) 236 { 237 mark_implicit_pred_write(ctx, insn, A_IMPLICIT_WRITES_P0, 0); 238 mark_implicit_pred_write(ctx, insn, A_IMPLICIT_WRITES_P1, 1); 239 mark_implicit_pred_write(ctx, insn, A_IMPLICIT_WRITES_P2, 2); 240 mark_implicit_pred_write(ctx, insn, A_IMPLICIT_WRITES_P3, 3); 241 } 242 243 static void gen_insn(CPUHexagonState *env, DisasContext *ctx, 244 Insn *insn, Packet *pkt) 245 { 246 if (insn->generate) { 247 mark_implicit_reg_writes(ctx, insn); 248 insn->generate(env, ctx, insn, pkt); 249 mark_implicit_pred_writes(ctx, insn); 250 } else { 251 gen_exception_end_tb(ctx, HEX_EXCP_INVALID_OPCODE); 252 } 253 } 254 255 /* 256 * Helpers for generating the packet commit 257 */ 258 static void gen_reg_writes(DisasContext *ctx) 259 { 260 int i; 261 262 for (i = 0; i < ctx->reg_log_idx; i++) { 263 int reg_num = ctx->reg_log[i]; 264 265 tcg_gen_mov_tl(hex_gpr[reg_num], hex_new_value[reg_num]); 266 } 267 } 268 269 static void gen_pred_writes(DisasContext *ctx, Packet *pkt) 270 { 271 int i; 272 273 /* Early exit if the log is empty */ 274 if (!ctx->preg_log_idx) { 275 return; 276 } 277 278 /* 279 * Only endloop instructions will conditionally 280 * write a predicate. If there are no endloop 281 * instructions, we can use the non-conditional 282 * write of the predicates. 283 */ 284 if (pkt->pkt_has_endloop) { 285 TCGv zero = tcg_constant_tl(0); 286 TCGv pred_written = tcg_temp_new(); 287 for (i = 0; i < ctx->preg_log_idx; i++) { 288 int pred_num = ctx->preg_log[i]; 289 290 tcg_gen_andi_tl(pred_written, hex_pred_written, 1 << pred_num); 291 tcg_gen_movcond_tl(TCG_COND_NE, hex_pred[pred_num], 292 pred_written, zero, 293 hex_new_pred_value[pred_num], 294 hex_pred[pred_num]); 295 } 296 tcg_temp_free(pred_written); 297 } else { 298 for (i = 0; i < ctx->preg_log_idx; i++) { 299 int pred_num = ctx->preg_log[i]; 300 tcg_gen_mov_tl(hex_pred[pred_num], hex_new_pred_value[pred_num]); 301 if (HEX_DEBUG) { 302 /* Do this so HELPER(debug_commit_end) will know */ 303 tcg_gen_ori_tl(hex_pred_written, hex_pred_written, 304 1 << pred_num); 305 } 306 } 307 } 308 } 309 310 static void gen_check_store_width(DisasContext *ctx, int slot_num) 311 { 312 if (HEX_DEBUG) { 313 TCGv slot = tcg_constant_tl(slot_num); 314 TCGv check = tcg_constant_tl(ctx->store_width[slot_num]); 315 gen_helper_debug_check_store_width(cpu_env, slot, check); 316 } 317 } 318 319 static bool slot_is_predicated(Packet *pkt, int slot_num) 320 { 321 for (int i = 0; i < pkt->num_insns; i++) { 322 if (pkt->insn[i].slot == slot_num) { 323 return GET_ATTRIB(pkt->insn[i].opcode, A_CONDEXEC); 324 } 325 } 326 /* If we get to here, we didn't find an instruction in the requested slot */ 327 g_assert_not_reached(); 328 } 329 330 void process_store(DisasContext *ctx, Packet *pkt, int slot_num) 331 { 332 bool is_predicated = slot_is_predicated(pkt, slot_num); 333 TCGLabel *label_end = NULL; 334 335 /* 336 * We may have already processed this store 337 * See CHECK_NOSHUF in macros.h 338 */ 339 if (slot_num == 1 && ctx->s1_store_processed) { 340 return; 341 } 342 ctx->s1_store_processed = true; 343 344 if (is_predicated) { 345 TCGv cancelled = tcg_temp_new(); 346 label_end = gen_new_label(); 347 348 /* Don't do anything if the slot was cancelled */ 349 tcg_gen_extract_tl(cancelled, hex_slot_cancelled, slot_num, 1); 350 tcg_gen_brcondi_tl(TCG_COND_NE, cancelled, 0, label_end); 351 tcg_temp_free(cancelled); 352 } 353 { 354 TCGv address = tcg_temp_local_new(); 355 tcg_gen_mov_tl(address, hex_store_addr[slot_num]); 356 357 /* 358 * If we know the width from the DisasContext, we can 359 * generate much cleaner code. 360 * Unfortunately, not all instructions execute the fSTORE 361 * macro during code generation. Anything that uses the 362 * generic helper will have this problem. Instructions 363 * that use fWRAP to generate proper TCG code will be OK. 364 */ 365 switch (ctx->store_width[slot_num]) { 366 case 1: 367 gen_check_store_width(ctx, slot_num); 368 tcg_gen_qemu_st8(hex_store_val32[slot_num], 369 hex_store_addr[slot_num], 370 ctx->mem_idx); 371 break; 372 case 2: 373 gen_check_store_width(ctx, slot_num); 374 tcg_gen_qemu_st16(hex_store_val32[slot_num], 375 hex_store_addr[slot_num], 376 ctx->mem_idx); 377 break; 378 case 4: 379 gen_check_store_width(ctx, slot_num); 380 tcg_gen_qemu_st32(hex_store_val32[slot_num], 381 hex_store_addr[slot_num], 382 ctx->mem_idx); 383 break; 384 case 8: 385 gen_check_store_width(ctx, slot_num); 386 tcg_gen_qemu_st64(hex_store_val64[slot_num], 387 hex_store_addr[slot_num], 388 ctx->mem_idx); 389 break; 390 default: 391 { 392 /* 393 * If we get to here, we don't know the width at 394 * TCG generation time, we'll use a helper to 395 * avoid branching based on the width at runtime. 396 */ 397 TCGv slot = tcg_constant_tl(slot_num); 398 gen_helper_commit_store(cpu_env, slot); 399 } 400 } 401 tcg_temp_free(address); 402 } 403 if (is_predicated) { 404 gen_set_label(label_end); 405 } 406 } 407 408 static void process_store_log(DisasContext *ctx, Packet *pkt) 409 { 410 /* 411 * When a packet has two stores, the hardware processes 412 * slot 1 and then slot 0. This will be important when 413 * the memory accesses overlap. 414 */ 415 if (pkt->pkt_has_store_s1 && !pkt->pkt_has_dczeroa) { 416 process_store(ctx, pkt, 1); 417 } 418 if (pkt->pkt_has_store_s0 && !pkt->pkt_has_dczeroa) { 419 process_store(ctx, pkt, 0); 420 } 421 } 422 423 /* Zero out a 32-bit cache line */ 424 static void process_dczeroa(DisasContext *ctx, Packet *pkt) 425 { 426 if (pkt->pkt_has_dczeroa) { 427 /* Store 32 bytes of zero starting at (addr & ~0x1f) */ 428 TCGv addr = tcg_temp_new(); 429 TCGv_i64 zero = tcg_constant_i64(0); 430 431 tcg_gen_andi_tl(addr, hex_dczero_addr, ~0x1f); 432 tcg_gen_qemu_st64(zero, addr, ctx->mem_idx); 433 tcg_gen_addi_tl(addr, addr, 8); 434 tcg_gen_qemu_st64(zero, addr, ctx->mem_idx); 435 tcg_gen_addi_tl(addr, addr, 8); 436 tcg_gen_qemu_st64(zero, addr, ctx->mem_idx); 437 tcg_gen_addi_tl(addr, addr, 8); 438 tcg_gen_qemu_st64(zero, addr, ctx->mem_idx); 439 440 tcg_temp_free(addr); 441 } 442 } 443 444 static void update_exec_counters(DisasContext *ctx, Packet *pkt) 445 { 446 int num_insns = pkt->num_insns; 447 int num_real_insns = 0; 448 449 for (int i = 0; i < num_insns; i++) { 450 if (!pkt->insn[i].is_endloop && 451 !pkt->insn[i].part1 && 452 !GET_ATTRIB(pkt->insn[i].opcode, A_IT_NOP)) { 453 num_real_insns++; 454 } 455 } 456 457 ctx->num_packets++; 458 ctx->num_insns += num_real_insns; 459 } 460 461 static void gen_commit_packet(DisasContext *ctx, Packet *pkt) 462 { 463 /* 464 * If there is more than one store in a packet, make sure they are all OK 465 * before proceeding with the rest of the packet commit. 466 * 467 * dczeroa has to be the only store operation in the packet, so we go 468 * ahead and process that first. 469 * 470 * When there are two scalar stores, we probe the one in slot 0. 471 * 472 * Note that we don't call the probe helper for packets with only one 473 * store. Therefore, we call process_store_log before anything else 474 * involved in committing the packet. 475 */ 476 bool has_store_s0 = pkt->pkt_has_store_s0; 477 bool has_store_s1 = (pkt->pkt_has_store_s1 && !ctx->s1_store_processed); 478 if (pkt->pkt_has_dczeroa) { 479 /* 480 * The dczeroa will be the store in slot 0, check that we don't have 481 * a store in slot 1. 482 */ 483 g_assert(has_store_s0 && !has_store_s1); 484 process_dczeroa(ctx, pkt); 485 } else if (has_store_s0 && has_store_s1) { 486 /* 487 * process_store_log will execute the slot 1 store first, 488 * so we only have to probe the store in slot 0 489 */ 490 TCGv mem_idx = tcg_const_tl(ctx->mem_idx); 491 gen_helper_probe_pkt_scalar_store_s0(cpu_env, mem_idx); 492 tcg_temp_free(mem_idx); 493 } 494 495 process_store_log(ctx, pkt); 496 497 gen_reg_writes(ctx); 498 gen_pred_writes(ctx, pkt); 499 update_exec_counters(ctx, pkt); 500 if (HEX_DEBUG) { 501 TCGv has_st0 = 502 tcg_constant_tl(pkt->pkt_has_store_s0 && !pkt->pkt_has_dczeroa); 503 TCGv has_st1 = 504 tcg_constant_tl(pkt->pkt_has_store_s1 && !pkt->pkt_has_dczeroa); 505 506 /* Handy place to set a breakpoint at the end of execution */ 507 gen_helper_debug_commit_end(cpu_env, has_st0, has_st1); 508 } 509 510 if (pkt->pkt_has_cof) { 511 gen_end_tb(ctx); 512 } 513 } 514 515 static void decode_and_translate_packet(CPUHexagonState *env, DisasContext *ctx) 516 { 517 uint32_t words[PACKET_WORDS_MAX]; 518 int nwords; 519 Packet pkt; 520 int i; 521 522 nwords = read_packet_words(env, ctx, words); 523 if (!nwords) { 524 gen_exception_end_tb(ctx, HEX_EXCP_INVALID_PACKET); 525 return; 526 } 527 528 if (decode_packet(nwords, words, &pkt, false) > 0) { 529 HEX_DEBUG_PRINT_PKT(&pkt); 530 gen_start_packet(ctx, &pkt); 531 for (i = 0; i < pkt.num_insns; i++) { 532 gen_insn(env, ctx, &pkt.insn[i], &pkt); 533 } 534 gen_commit_packet(ctx, &pkt); 535 ctx->base.pc_next += pkt.encod_pkt_size_in_bytes; 536 } else { 537 gen_exception_end_tb(ctx, HEX_EXCP_INVALID_PACKET); 538 } 539 } 540 541 static void hexagon_tr_init_disas_context(DisasContextBase *dcbase, 542 CPUState *cs) 543 { 544 DisasContext *ctx = container_of(dcbase, DisasContext, base); 545 546 ctx->mem_idx = MMU_USER_IDX; 547 ctx->num_packets = 0; 548 ctx->num_insns = 0; 549 } 550 551 static void hexagon_tr_tb_start(DisasContextBase *db, CPUState *cpu) 552 { 553 } 554 555 static void hexagon_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) 556 { 557 DisasContext *ctx = container_of(dcbase, DisasContext, base); 558 559 tcg_gen_insn_start(ctx->base.pc_next); 560 } 561 562 static bool pkt_crosses_page(CPUHexagonState *env, DisasContext *ctx) 563 { 564 target_ulong page_start = ctx->base.pc_first & TARGET_PAGE_MASK; 565 bool found_end = false; 566 int nwords; 567 568 for (nwords = 0; !found_end && nwords < PACKET_WORDS_MAX; nwords++) { 569 uint32_t word = cpu_ldl_code(env, 570 ctx->base.pc_next + nwords * sizeof(uint32_t)); 571 found_end = is_packet_end(word); 572 } 573 uint32_t next_ptr = ctx->base.pc_next + nwords * sizeof(uint32_t); 574 return found_end && next_ptr - page_start >= TARGET_PAGE_SIZE; 575 } 576 577 static void hexagon_tr_translate_packet(DisasContextBase *dcbase, CPUState *cpu) 578 { 579 DisasContext *ctx = container_of(dcbase, DisasContext, base); 580 CPUHexagonState *env = cpu->env_ptr; 581 582 decode_and_translate_packet(env, ctx); 583 584 if (ctx->base.is_jmp == DISAS_NEXT) { 585 target_ulong page_start = ctx->base.pc_first & TARGET_PAGE_MASK; 586 target_ulong bytes_max = PACKET_WORDS_MAX * sizeof(target_ulong); 587 588 if (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE || 589 (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE - bytes_max && 590 pkt_crosses_page(env, ctx))) { 591 ctx->base.is_jmp = DISAS_TOO_MANY; 592 } 593 594 /* 595 * The CPU log is used to compare against LLDB single stepping, 596 * so end the TLB after every packet. 597 */ 598 HexagonCPU *hex_cpu = env_archcpu(env); 599 if (hex_cpu->lldb_compat && qemu_loglevel_mask(CPU_LOG_TB_CPU)) { 600 ctx->base.is_jmp = DISAS_TOO_MANY; 601 } 602 } 603 } 604 605 static void hexagon_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) 606 { 607 DisasContext *ctx = container_of(dcbase, DisasContext, base); 608 609 switch (ctx->base.is_jmp) { 610 case DISAS_TOO_MANY: 611 gen_exec_counters(ctx); 612 tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], ctx->base.pc_next); 613 tcg_gen_exit_tb(NULL, 0); 614 break; 615 case DISAS_NORETURN: 616 break; 617 default: 618 g_assert_not_reached(); 619 } 620 } 621 622 static void hexagon_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu) 623 { 624 qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); 625 log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size); 626 } 627 628 629 static const TranslatorOps hexagon_tr_ops = { 630 .init_disas_context = hexagon_tr_init_disas_context, 631 .tb_start = hexagon_tr_tb_start, 632 .insn_start = hexagon_tr_insn_start, 633 .translate_insn = hexagon_tr_translate_packet, 634 .tb_stop = hexagon_tr_tb_stop, 635 .disas_log = hexagon_tr_disas_log, 636 }; 637 638 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) 639 { 640 DisasContext ctx; 641 642 translator_loop(&hexagon_tr_ops, &ctx.base, cs, tb, max_insns); 643 } 644 645 #define NAME_LEN 64 646 static char new_value_names[TOTAL_PER_THREAD_REGS][NAME_LEN]; 647 static char reg_written_names[TOTAL_PER_THREAD_REGS][NAME_LEN]; 648 static char new_pred_value_names[NUM_PREGS][NAME_LEN]; 649 static char store_addr_names[STORES_MAX][NAME_LEN]; 650 static char store_width_names[STORES_MAX][NAME_LEN]; 651 static char store_val32_names[STORES_MAX][NAME_LEN]; 652 static char store_val64_names[STORES_MAX][NAME_LEN]; 653 654 void hexagon_translate_init(void) 655 { 656 int i; 657 658 opcode_init(); 659 660 if (HEX_DEBUG) { 661 if (!qemu_logfile) { 662 qemu_set_log(qemu_loglevel); 663 } 664 } 665 666 for (i = 0; i < TOTAL_PER_THREAD_REGS; i++) { 667 hex_gpr[i] = tcg_global_mem_new(cpu_env, 668 offsetof(CPUHexagonState, gpr[i]), 669 hexagon_regnames[i]); 670 671 snprintf(new_value_names[i], NAME_LEN, "new_%s", hexagon_regnames[i]); 672 hex_new_value[i] = tcg_global_mem_new(cpu_env, 673 offsetof(CPUHexagonState, new_value[i]), 674 new_value_names[i]); 675 676 if (HEX_DEBUG) { 677 snprintf(reg_written_names[i], NAME_LEN, "reg_written_%s", 678 hexagon_regnames[i]); 679 hex_reg_written[i] = tcg_global_mem_new(cpu_env, 680 offsetof(CPUHexagonState, reg_written[i]), 681 reg_written_names[i]); 682 } 683 } 684 for (i = 0; i < NUM_PREGS; i++) { 685 hex_pred[i] = tcg_global_mem_new(cpu_env, 686 offsetof(CPUHexagonState, pred[i]), 687 hexagon_prednames[i]); 688 689 snprintf(new_pred_value_names[i], NAME_LEN, "new_pred_%s", 690 hexagon_prednames[i]); 691 hex_new_pred_value[i] = tcg_global_mem_new(cpu_env, 692 offsetof(CPUHexagonState, new_pred_value[i]), 693 new_pred_value_names[i]); 694 } 695 hex_pred_written = tcg_global_mem_new(cpu_env, 696 offsetof(CPUHexagonState, pred_written), "pred_written"); 697 hex_next_PC = tcg_global_mem_new(cpu_env, 698 offsetof(CPUHexagonState, next_PC), "next_PC"); 699 hex_this_PC = tcg_global_mem_new(cpu_env, 700 offsetof(CPUHexagonState, this_PC), "this_PC"); 701 hex_slot_cancelled = tcg_global_mem_new(cpu_env, 702 offsetof(CPUHexagonState, slot_cancelled), "slot_cancelled"); 703 hex_branch_taken = tcg_global_mem_new(cpu_env, 704 offsetof(CPUHexagonState, branch_taken), "branch_taken"); 705 hex_pkt_has_store_s1 = tcg_global_mem_new(cpu_env, 706 offsetof(CPUHexagonState, pkt_has_store_s1), "pkt_has_store_s1"); 707 hex_dczero_addr = tcg_global_mem_new(cpu_env, 708 offsetof(CPUHexagonState, dczero_addr), "dczero_addr"); 709 hex_llsc_addr = tcg_global_mem_new(cpu_env, 710 offsetof(CPUHexagonState, llsc_addr), "llsc_addr"); 711 hex_llsc_val = tcg_global_mem_new(cpu_env, 712 offsetof(CPUHexagonState, llsc_val), "llsc_val"); 713 hex_llsc_val_i64 = tcg_global_mem_new_i64(cpu_env, 714 offsetof(CPUHexagonState, llsc_val_i64), "llsc_val_i64"); 715 for (i = 0; i < STORES_MAX; i++) { 716 snprintf(store_addr_names[i], NAME_LEN, "store_addr_%d", i); 717 hex_store_addr[i] = tcg_global_mem_new(cpu_env, 718 offsetof(CPUHexagonState, mem_log_stores[i].va), 719 store_addr_names[i]); 720 721 snprintf(store_width_names[i], NAME_LEN, "store_width_%d", i); 722 hex_store_width[i] = tcg_global_mem_new(cpu_env, 723 offsetof(CPUHexagonState, mem_log_stores[i].width), 724 store_width_names[i]); 725 726 snprintf(store_val32_names[i], NAME_LEN, "store_val32_%d", i); 727 hex_store_val32[i] = tcg_global_mem_new(cpu_env, 728 offsetof(CPUHexagonState, mem_log_stores[i].data32), 729 store_val32_names[i]); 730 731 snprintf(store_val64_names[i], NAME_LEN, "store_val64_%d", i); 732 hex_store_val64[i] = tcg_global_mem_new_i64(cpu_env, 733 offsetof(CPUHexagonState, mem_log_stores[i].data64), 734 store_val64_names[i]); 735 } 736 } 737