1 /* 2 * Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #define QEMU_GENERATE 19 #include "qemu/osdep.h" 20 #include "cpu.h" 21 #include "tcg/tcg-op.h" 22 #include "exec/cpu_ldst.h" 23 #include "exec/log.h" 24 #include "internal.h" 25 #include "attribs.h" 26 #include "insn.h" 27 #include "decode.h" 28 #include "translate.h" 29 #include "printinsn.h" 30 31 TCGv hex_gpr[TOTAL_PER_THREAD_REGS]; 32 TCGv hex_pred[NUM_PREGS]; 33 TCGv hex_next_PC; 34 TCGv hex_this_PC; 35 TCGv hex_slot_cancelled; 36 TCGv hex_branch_taken; 37 TCGv hex_new_value[TOTAL_PER_THREAD_REGS]; 38 TCGv hex_reg_written[TOTAL_PER_THREAD_REGS]; 39 TCGv hex_new_pred_value[NUM_PREGS]; 40 TCGv hex_pred_written; 41 TCGv hex_store_addr[STORES_MAX]; 42 TCGv hex_store_width[STORES_MAX]; 43 TCGv hex_store_val32[STORES_MAX]; 44 TCGv_i64 hex_store_val64[STORES_MAX]; 45 TCGv hex_pkt_has_store_s1; 46 TCGv hex_dczero_addr; 47 TCGv hex_llsc_addr; 48 TCGv hex_llsc_val; 49 TCGv_i64 hex_llsc_val_i64; 50 51 static const char * const hexagon_prednames[] = { 52 "p0", "p1", "p2", "p3" 53 }; 54 55 static void gen_exception_raw(int excp) 56 { 57 gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); 58 } 59 60 static void gen_exec_counters(DisasContext *ctx) 61 { 62 tcg_gen_addi_tl(hex_gpr[HEX_REG_QEMU_PKT_CNT], 63 hex_gpr[HEX_REG_QEMU_PKT_CNT], ctx->num_packets); 64 tcg_gen_addi_tl(hex_gpr[HEX_REG_QEMU_INSN_CNT], 65 hex_gpr[HEX_REG_QEMU_INSN_CNT], ctx->num_insns); 66 } 67 68 static void gen_end_tb(DisasContext *ctx) 69 { 70 gen_exec_counters(ctx); 71 tcg_gen_mov_tl(hex_gpr[HEX_REG_PC], hex_next_PC); 72 tcg_gen_exit_tb(NULL, 0); 73 ctx->base.is_jmp = DISAS_NORETURN; 74 } 75 76 static void gen_exception_end_tb(DisasContext *ctx, int excp) 77 { 78 gen_exec_counters(ctx); 79 tcg_gen_mov_tl(hex_gpr[HEX_REG_PC], hex_next_PC); 80 gen_exception_raw(excp); 81 ctx->base.is_jmp = DISAS_NORETURN; 82 83 } 84 85 #define PACKET_BUFFER_LEN 1028 86 static void print_pkt(Packet *pkt) 87 { 88 GString *buf = g_string_sized_new(PACKET_BUFFER_LEN); 89 snprint_a_pkt_debug(buf, pkt); 90 HEX_DEBUG_LOG("%s", buf->str); 91 g_string_free(buf, true); 92 } 93 #define HEX_DEBUG_PRINT_PKT(pkt) \ 94 do { \ 95 if (HEX_DEBUG) { \ 96 print_pkt(pkt); \ 97 } \ 98 } while (0) 99 100 static int read_packet_words(CPUHexagonState *env, DisasContext *ctx, 101 uint32_t words[]) 102 { 103 bool found_end = false; 104 int nwords, max_words; 105 106 memset(words, 0, PACKET_WORDS_MAX * sizeof(uint32_t)); 107 for (nwords = 0; !found_end && nwords < PACKET_WORDS_MAX; nwords++) { 108 words[nwords] = 109 translator_ldl(env, &ctx->base, 110 ctx->base.pc_next + nwords * sizeof(uint32_t)); 111 found_end = is_packet_end(words[nwords]); 112 } 113 if (!found_end) { 114 /* Read too many words without finding the end */ 115 return 0; 116 } 117 118 /* Check for page boundary crossing */ 119 max_words = -(ctx->base.pc_next | TARGET_PAGE_MASK) / sizeof(uint32_t); 120 if (nwords > max_words) { 121 /* We can only cross a page boundary at the beginning of a TB */ 122 g_assert(ctx->base.num_insns == 1); 123 } 124 125 HEX_DEBUG_LOG("decode_packet: pc = 0x%x\n", ctx->base.pc_next); 126 HEX_DEBUG_LOG(" words = { "); 127 for (int i = 0; i < nwords; i++) { 128 HEX_DEBUG_LOG("0x%x, ", words[i]); 129 } 130 HEX_DEBUG_LOG("}\n"); 131 132 return nwords; 133 } 134 135 static bool check_for_attrib(Packet *pkt, int attrib) 136 { 137 for (int i = 0; i < pkt->num_insns; i++) { 138 if (GET_ATTRIB(pkt->insn[i].opcode, attrib)) { 139 return true; 140 } 141 } 142 return false; 143 } 144 145 static bool need_pc(Packet *pkt) 146 { 147 return check_for_attrib(pkt, A_IMPLICIT_READS_PC); 148 } 149 150 static bool need_slot_cancelled(Packet *pkt) 151 { 152 return check_for_attrib(pkt, A_CONDEXEC); 153 } 154 155 static bool need_pred_written(Packet *pkt) 156 { 157 return check_for_attrib(pkt, A_WRITES_PRED_REG); 158 } 159 160 static void gen_start_packet(DisasContext *ctx, Packet *pkt) 161 { 162 target_ulong next_PC = ctx->base.pc_next + pkt->encod_pkt_size_in_bytes; 163 int i; 164 165 /* Clear out the disassembly context */ 166 ctx->reg_log_idx = 0; 167 bitmap_zero(ctx->regs_written, TOTAL_PER_THREAD_REGS); 168 ctx->preg_log_idx = 0; 169 bitmap_zero(ctx->pregs_written, NUM_PREGS); 170 for (i = 0; i < STORES_MAX; i++) { 171 ctx->store_width[i] = 0; 172 } 173 tcg_gen_movi_tl(hex_pkt_has_store_s1, pkt->pkt_has_store_s1); 174 ctx->s1_store_processed = false; 175 176 if (HEX_DEBUG) { 177 /* Handy place to set a breakpoint before the packet executes */ 178 gen_helper_debug_start_packet(cpu_env); 179 tcg_gen_movi_tl(hex_this_PC, ctx->base.pc_next); 180 } 181 182 /* Initialize the runtime state for packet semantics */ 183 if (need_pc(pkt)) { 184 tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], ctx->base.pc_next); 185 } 186 if (need_slot_cancelled(pkt)) { 187 tcg_gen_movi_tl(hex_slot_cancelled, 0); 188 } 189 if (pkt->pkt_has_cof) { 190 tcg_gen_movi_tl(hex_branch_taken, 0); 191 tcg_gen_movi_tl(hex_next_PC, next_PC); 192 } 193 if (need_pred_written(pkt)) { 194 tcg_gen_movi_tl(hex_pred_written, 0); 195 } 196 } 197 198 /* 199 * The LOG_*_WRITE macros mark most of the writes in a packet 200 * However, there are some implicit writes marked as attributes 201 * of the applicable instructions. 202 */ 203 static void mark_implicit_reg_write(DisasContext *ctx, Insn *insn, 204 int attrib, int rnum) 205 { 206 if (GET_ATTRIB(insn->opcode, attrib)) { 207 /* 208 * USR is used to set overflow and FP exceptions, 209 * so treat it as conditional 210 */ 211 bool is_predicated = GET_ATTRIB(insn->opcode, A_CONDEXEC) || 212 rnum == HEX_REG_USR; 213 if (is_predicated && !is_preloaded(ctx, rnum)) { 214 tcg_gen_mov_tl(hex_new_value[rnum], hex_gpr[rnum]); 215 } 216 217 ctx_log_reg_write(ctx, rnum); 218 } 219 } 220 221 static void mark_implicit_pred_write(DisasContext *ctx, Insn *insn, 222 int attrib, int pnum) 223 { 224 if (GET_ATTRIB(insn->opcode, attrib)) { 225 ctx_log_pred_write(ctx, pnum); 226 } 227 } 228 229 static void mark_implicit_reg_writes(DisasContext *ctx, Insn *insn) 230 { 231 mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_FP, HEX_REG_FP); 232 mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_SP, HEX_REG_SP); 233 mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_LR, HEX_REG_LR); 234 mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_LC0, HEX_REG_LC0); 235 mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_SA0, HEX_REG_SA0); 236 mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_LC1, HEX_REG_LC1); 237 mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_SA1, HEX_REG_SA1); 238 mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_USR, HEX_REG_USR); 239 mark_implicit_reg_write(ctx, insn, A_FPOP, HEX_REG_USR); 240 } 241 242 static void mark_implicit_pred_writes(DisasContext *ctx, Insn *insn) 243 { 244 mark_implicit_pred_write(ctx, insn, A_IMPLICIT_WRITES_P0, 0); 245 mark_implicit_pred_write(ctx, insn, A_IMPLICIT_WRITES_P1, 1); 246 mark_implicit_pred_write(ctx, insn, A_IMPLICIT_WRITES_P2, 2); 247 mark_implicit_pred_write(ctx, insn, A_IMPLICIT_WRITES_P3, 3); 248 } 249 250 static void gen_insn(CPUHexagonState *env, DisasContext *ctx, 251 Insn *insn, Packet *pkt) 252 { 253 if (insn->generate) { 254 mark_implicit_reg_writes(ctx, insn); 255 insn->generate(env, ctx, insn, pkt); 256 mark_implicit_pred_writes(ctx, insn); 257 } else { 258 gen_exception_end_tb(ctx, HEX_EXCP_INVALID_OPCODE); 259 } 260 } 261 262 /* 263 * Helpers for generating the packet commit 264 */ 265 static void gen_reg_writes(DisasContext *ctx) 266 { 267 int i; 268 269 for (i = 0; i < ctx->reg_log_idx; i++) { 270 int reg_num = ctx->reg_log[i]; 271 272 tcg_gen_mov_tl(hex_gpr[reg_num], hex_new_value[reg_num]); 273 } 274 } 275 276 static void gen_pred_writes(DisasContext *ctx, Packet *pkt) 277 { 278 int i; 279 280 /* Early exit if the log is empty */ 281 if (!ctx->preg_log_idx) { 282 return; 283 } 284 285 /* 286 * Only endloop instructions will conditionally 287 * write a predicate. If there are no endloop 288 * instructions, we can use the non-conditional 289 * write of the predicates. 290 */ 291 if (pkt->pkt_has_endloop) { 292 TCGv zero = tcg_constant_tl(0); 293 TCGv pred_written = tcg_temp_new(); 294 for (i = 0; i < ctx->preg_log_idx; i++) { 295 int pred_num = ctx->preg_log[i]; 296 297 tcg_gen_andi_tl(pred_written, hex_pred_written, 1 << pred_num); 298 tcg_gen_movcond_tl(TCG_COND_NE, hex_pred[pred_num], 299 pred_written, zero, 300 hex_new_pred_value[pred_num], 301 hex_pred[pred_num]); 302 } 303 tcg_temp_free(pred_written); 304 } else { 305 for (i = 0; i < ctx->preg_log_idx; i++) { 306 int pred_num = ctx->preg_log[i]; 307 tcg_gen_mov_tl(hex_pred[pred_num], hex_new_pred_value[pred_num]); 308 if (HEX_DEBUG) { 309 /* Do this so HELPER(debug_commit_end) will know */ 310 tcg_gen_ori_tl(hex_pred_written, hex_pred_written, 311 1 << pred_num); 312 } 313 } 314 } 315 } 316 317 static void gen_check_store_width(DisasContext *ctx, int slot_num) 318 { 319 if (HEX_DEBUG) { 320 TCGv slot = tcg_constant_tl(slot_num); 321 TCGv check = tcg_constant_tl(ctx->store_width[slot_num]); 322 gen_helper_debug_check_store_width(cpu_env, slot, check); 323 } 324 } 325 326 static bool slot_is_predicated(Packet *pkt, int slot_num) 327 { 328 for (int i = 0; i < pkt->num_insns; i++) { 329 if (pkt->insn[i].slot == slot_num) { 330 return GET_ATTRIB(pkt->insn[i].opcode, A_CONDEXEC); 331 } 332 } 333 /* If we get to here, we didn't find an instruction in the requested slot */ 334 g_assert_not_reached(); 335 } 336 337 void process_store(DisasContext *ctx, Packet *pkt, int slot_num) 338 { 339 bool is_predicated = slot_is_predicated(pkt, slot_num); 340 TCGLabel *label_end = NULL; 341 342 /* 343 * We may have already processed this store 344 * See CHECK_NOSHUF in macros.h 345 */ 346 if (slot_num == 1 && ctx->s1_store_processed) { 347 return; 348 } 349 ctx->s1_store_processed = true; 350 351 if (is_predicated) { 352 TCGv cancelled = tcg_temp_new(); 353 label_end = gen_new_label(); 354 355 /* Don't do anything if the slot was cancelled */ 356 tcg_gen_extract_tl(cancelled, hex_slot_cancelled, slot_num, 1); 357 tcg_gen_brcondi_tl(TCG_COND_NE, cancelled, 0, label_end); 358 tcg_temp_free(cancelled); 359 } 360 { 361 TCGv address = tcg_temp_local_new(); 362 tcg_gen_mov_tl(address, hex_store_addr[slot_num]); 363 364 /* 365 * If we know the width from the DisasContext, we can 366 * generate much cleaner code. 367 * Unfortunately, not all instructions execute the fSTORE 368 * macro during code generation. Anything that uses the 369 * generic helper will have this problem. Instructions 370 * that use fWRAP to generate proper TCG code will be OK. 371 */ 372 switch (ctx->store_width[slot_num]) { 373 case 1: 374 gen_check_store_width(ctx, slot_num); 375 tcg_gen_qemu_st8(hex_store_val32[slot_num], 376 hex_store_addr[slot_num], 377 ctx->mem_idx); 378 break; 379 case 2: 380 gen_check_store_width(ctx, slot_num); 381 tcg_gen_qemu_st16(hex_store_val32[slot_num], 382 hex_store_addr[slot_num], 383 ctx->mem_idx); 384 break; 385 case 4: 386 gen_check_store_width(ctx, slot_num); 387 tcg_gen_qemu_st32(hex_store_val32[slot_num], 388 hex_store_addr[slot_num], 389 ctx->mem_idx); 390 break; 391 case 8: 392 gen_check_store_width(ctx, slot_num); 393 tcg_gen_qemu_st64(hex_store_val64[slot_num], 394 hex_store_addr[slot_num], 395 ctx->mem_idx); 396 break; 397 default: 398 { 399 /* 400 * If we get to here, we don't know the width at 401 * TCG generation time, we'll use a helper to 402 * avoid branching based on the width at runtime. 403 */ 404 TCGv slot = tcg_constant_tl(slot_num); 405 gen_helper_commit_store(cpu_env, slot); 406 } 407 } 408 tcg_temp_free(address); 409 } 410 if (is_predicated) { 411 gen_set_label(label_end); 412 } 413 } 414 415 static void process_store_log(DisasContext *ctx, Packet *pkt) 416 { 417 /* 418 * When a packet has two stores, the hardware processes 419 * slot 1 and then slot 0. This will be important when 420 * the memory accesses overlap. 421 */ 422 if (pkt->pkt_has_store_s1 && !pkt->pkt_has_dczeroa) { 423 process_store(ctx, pkt, 1); 424 } 425 if (pkt->pkt_has_store_s0 && !pkt->pkt_has_dczeroa) { 426 process_store(ctx, pkt, 0); 427 } 428 } 429 430 /* Zero out a 32-bit cache line */ 431 static void process_dczeroa(DisasContext *ctx, Packet *pkt) 432 { 433 if (pkt->pkt_has_dczeroa) { 434 /* Store 32 bytes of zero starting at (addr & ~0x1f) */ 435 TCGv addr = tcg_temp_new(); 436 TCGv_i64 zero = tcg_constant_i64(0); 437 438 tcg_gen_andi_tl(addr, hex_dczero_addr, ~0x1f); 439 tcg_gen_qemu_st64(zero, addr, ctx->mem_idx); 440 tcg_gen_addi_tl(addr, addr, 8); 441 tcg_gen_qemu_st64(zero, addr, ctx->mem_idx); 442 tcg_gen_addi_tl(addr, addr, 8); 443 tcg_gen_qemu_st64(zero, addr, ctx->mem_idx); 444 tcg_gen_addi_tl(addr, addr, 8); 445 tcg_gen_qemu_st64(zero, addr, ctx->mem_idx); 446 447 tcg_temp_free(addr); 448 } 449 } 450 451 static void update_exec_counters(DisasContext *ctx, Packet *pkt) 452 { 453 int num_insns = pkt->num_insns; 454 int num_real_insns = 0; 455 456 for (int i = 0; i < num_insns; i++) { 457 if (!pkt->insn[i].is_endloop && 458 !pkt->insn[i].part1 && 459 !GET_ATTRIB(pkt->insn[i].opcode, A_IT_NOP)) { 460 num_real_insns++; 461 } 462 } 463 464 ctx->num_packets++; 465 ctx->num_insns += num_real_insns; 466 } 467 468 static void gen_commit_packet(DisasContext *ctx, Packet *pkt) 469 { 470 /* 471 * If there is more than one store in a packet, make sure they are all OK 472 * before proceeding with the rest of the packet commit. 473 * 474 * dczeroa has to be the only store operation in the packet, so we go 475 * ahead and process that first. 476 * 477 * When there are two scalar stores, we probe the one in slot 0. 478 * 479 * Note that we don't call the probe helper for packets with only one 480 * store. Therefore, we call process_store_log before anything else 481 * involved in committing the packet. 482 */ 483 bool has_store_s0 = pkt->pkt_has_store_s0; 484 bool has_store_s1 = (pkt->pkt_has_store_s1 && !ctx->s1_store_processed); 485 if (pkt->pkt_has_dczeroa) { 486 /* 487 * The dczeroa will be the store in slot 0, check that we don't have 488 * a store in slot 1. 489 */ 490 g_assert(has_store_s0 && !has_store_s1); 491 process_dczeroa(ctx, pkt); 492 } else if (has_store_s0 && has_store_s1) { 493 /* 494 * process_store_log will execute the slot 1 store first, 495 * so we only have to probe the store in slot 0 496 */ 497 TCGv mem_idx = tcg_constant_tl(ctx->mem_idx); 498 gen_helper_probe_pkt_scalar_store_s0(cpu_env, mem_idx); 499 } 500 501 process_store_log(ctx, pkt); 502 503 gen_reg_writes(ctx); 504 gen_pred_writes(ctx, pkt); 505 update_exec_counters(ctx, pkt); 506 if (HEX_DEBUG) { 507 TCGv has_st0 = 508 tcg_constant_tl(pkt->pkt_has_store_s0 && !pkt->pkt_has_dczeroa); 509 TCGv has_st1 = 510 tcg_constant_tl(pkt->pkt_has_store_s1 && !pkt->pkt_has_dczeroa); 511 512 /* Handy place to set a breakpoint at the end of execution */ 513 gen_helper_debug_commit_end(cpu_env, has_st0, has_st1); 514 } 515 516 if (pkt->pkt_has_cof) { 517 gen_end_tb(ctx); 518 } 519 } 520 521 static void decode_and_translate_packet(CPUHexagonState *env, DisasContext *ctx) 522 { 523 uint32_t words[PACKET_WORDS_MAX]; 524 int nwords; 525 Packet pkt; 526 int i; 527 528 nwords = read_packet_words(env, ctx, words); 529 if (!nwords) { 530 gen_exception_end_tb(ctx, HEX_EXCP_INVALID_PACKET); 531 return; 532 } 533 534 if (decode_packet(nwords, words, &pkt, false) > 0) { 535 HEX_DEBUG_PRINT_PKT(&pkt); 536 gen_start_packet(ctx, &pkt); 537 for (i = 0; i < pkt.num_insns; i++) { 538 gen_insn(env, ctx, &pkt.insn[i], &pkt); 539 } 540 gen_commit_packet(ctx, &pkt); 541 ctx->base.pc_next += pkt.encod_pkt_size_in_bytes; 542 } else { 543 gen_exception_end_tb(ctx, HEX_EXCP_INVALID_PACKET); 544 } 545 } 546 547 static void hexagon_tr_init_disas_context(DisasContextBase *dcbase, 548 CPUState *cs) 549 { 550 DisasContext *ctx = container_of(dcbase, DisasContext, base); 551 552 ctx->mem_idx = MMU_USER_IDX; 553 ctx->num_packets = 0; 554 ctx->num_insns = 0; 555 } 556 557 static void hexagon_tr_tb_start(DisasContextBase *db, CPUState *cpu) 558 { 559 } 560 561 static void hexagon_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) 562 { 563 DisasContext *ctx = container_of(dcbase, DisasContext, base); 564 565 tcg_gen_insn_start(ctx->base.pc_next); 566 } 567 568 static bool pkt_crosses_page(CPUHexagonState *env, DisasContext *ctx) 569 { 570 target_ulong page_start = ctx->base.pc_first & TARGET_PAGE_MASK; 571 bool found_end = false; 572 int nwords; 573 574 for (nwords = 0; !found_end && nwords < PACKET_WORDS_MAX; nwords++) { 575 uint32_t word = cpu_ldl_code(env, 576 ctx->base.pc_next + nwords * sizeof(uint32_t)); 577 found_end = is_packet_end(word); 578 } 579 uint32_t next_ptr = ctx->base.pc_next + nwords * sizeof(uint32_t); 580 return found_end && next_ptr - page_start >= TARGET_PAGE_SIZE; 581 } 582 583 static void hexagon_tr_translate_packet(DisasContextBase *dcbase, CPUState *cpu) 584 { 585 DisasContext *ctx = container_of(dcbase, DisasContext, base); 586 CPUHexagonState *env = cpu->env_ptr; 587 588 decode_and_translate_packet(env, ctx); 589 590 if (ctx->base.is_jmp == DISAS_NEXT) { 591 target_ulong page_start = ctx->base.pc_first & TARGET_PAGE_MASK; 592 target_ulong bytes_max = PACKET_WORDS_MAX * sizeof(target_ulong); 593 594 if (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE || 595 (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE - bytes_max && 596 pkt_crosses_page(env, ctx))) { 597 ctx->base.is_jmp = DISAS_TOO_MANY; 598 } 599 600 /* 601 * The CPU log is used to compare against LLDB single stepping, 602 * so end the TLB after every packet. 603 */ 604 HexagonCPU *hex_cpu = env_archcpu(env); 605 if (hex_cpu->lldb_compat && qemu_loglevel_mask(CPU_LOG_TB_CPU)) { 606 ctx->base.is_jmp = DISAS_TOO_MANY; 607 } 608 } 609 } 610 611 static void hexagon_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) 612 { 613 DisasContext *ctx = container_of(dcbase, DisasContext, base); 614 615 switch (ctx->base.is_jmp) { 616 case DISAS_TOO_MANY: 617 gen_exec_counters(ctx); 618 tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], ctx->base.pc_next); 619 tcg_gen_exit_tb(NULL, 0); 620 break; 621 case DISAS_NORETURN: 622 break; 623 default: 624 g_assert_not_reached(); 625 } 626 } 627 628 static void hexagon_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu) 629 { 630 qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); 631 log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size); 632 } 633 634 635 static const TranslatorOps hexagon_tr_ops = { 636 .init_disas_context = hexagon_tr_init_disas_context, 637 .tb_start = hexagon_tr_tb_start, 638 .insn_start = hexagon_tr_insn_start, 639 .translate_insn = hexagon_tr_translate_packet, 640 .tb_stop = hexagon_tr_tb_stop, 641 .disas_log = hexagon_tr_disas_log, 642 }; 643 644 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) 645 { 646 DisasContext ctx; 647 648 translator_loop(&hexagon_tr_ops, &ctx.base, cs, tb, max_insns); 649 } 650 651 #define NAME_LEN 64 652 static char new_value_names[TOTAL_PER_THREAD_REGS][NAME_LEN]; 653 static char reg_written_names[TOTAL_PER_THREAD_REGS][NAME_LEN]; 654 static char new_pred_value_names[NUM_PREGS][NAME_LEN]; 655 static char store_addr_names[STORES_MAX][NAME_LEN]; 656 static char store_width_names[STORES_MAX][NAME_LEN]; 657 static char store_val32_names[STORES_MAX][NAME_LEN]; 658 static char store_val64_names[STORES_MAX][NAME_LEN]; 659 660 void hexagon_translate_init(void) 661 { 662 int i; 663 664 opcode_init(); 665 666 if (HEX_DEBUG) { 667 if (!qemu_logfile) { 668 qemu_set_log(qemu_loglevel); 669 } 670 } 671 672 for (i = 0; i < TOTAL_PER_THREAD_REGS; i++) { 673 hex_gpr[i] = tcg_global_mem_new(cpu_env, 674 offsetof(CPUHexagonState, gpr[i]), 675 hexagon_regnames[i]); 676 677 snprintf(new_value_names[i], NAME_LEN, "new_%s", hexagon_regnames[i]); 678 hex_new_value[i] = tcg_global_mem_new(cpu_env, 679 offsetof(CPUHexagonState, new_value[i]), 680 new_value_names[i]); 681 682 if (HEX_DEBUG) { 683 snprintf(reg_written_names[i], NAME_LEN, "reg_written_%s", 684 hexagon_regnames[i]); 685 hex_reg_written[i] = tcg_global_mem_new(cpu_env, 686 offsetof(CPUHexagonState, reg_written[i]), 687 reg_written_names[i]); 688 } 689 } 690 for (i = 0; i < NUM_PREGS; i++) { 691 hex_pred[i] = tcg_global_mem_new(cpu_env, 692 offsetof(CPUHexagonState, pred[i]), 693 hexagon_prednames[i]); 694 695 snprintf(new_pred_value_names[i], NAME_LEN, "new_pred_%s", 696 hexagon_prednames[i]); 697 hex_new_pred_value[i] = tcg_global_mem_new(cpu_env, 698 offsetof(CPUHexagonState, new_pred_value[i]), 699 new_pred_value_names[i]); 700 } 701 hex_pred_written = tcg_global_mem_new(cpu_env, 702 offsetof(CPUHexagonState, pred_written), "pred_written"); 703 hex_next_PC = tcg_global_mem_new(cpu_env, 704 offsetof(CPUHexagonState, next_PC), "next_PC"); 705 hex_this_PC = tcg_global_mem_new(cpu_env, 706 offsetof(CPUHexagonState, this_PC), "this_PC"); 707 hex_slot_cancelled = tcg_global_mem_new(cpu_env, 708 offsetof(CPUHexagonState, slot_cancelled), "slot_cancelled"); 709 hex_branch_taken = tcg_global_mem_new(cpu_env, 710 offsetof(CPUHexagonState, branch_taken), "branch_taken"); 711 hex_pkt_has_store_s1 = tcg_global_mem_new(cpu_env, 712 offsetof(CPUHexagonState, pkt_has_store_s1), "pkt_has_store_s1"); 713 hex_dczero_addr = tcg_global_mem_new(cpu_env, 714 offsetof(CPUHexagonState, dczero_addr), "dczero_addr"); 715 hex_llsc_addr = tcg_global_mem_new(cpu_env, 716 offsetof(CPUHexagonState, llsc_addr), "llsc_addr"); 717 hex_llsc_val = tcg_global_mem_new(cpu_env, 718 offsetof(CPUHexagonState, llsc_val), "llsc_val"); 719 hex_llsc_val_i64 = tcg_global_mem_new_i64(cpu_env, 720 offsetof(CPUHexagonState, llsc_val_i64), "llsc_val_i64"); 721 for (i = 0; i < STORES_MAX; i++) { 722 snprintf(store_addr_names[i], NAME_LEN, "store_addr_%d", i); 723 hex_store_addr[i] = tcg_global_mem_new(cpu_env, 724 offsetof(CPUHexagonState, mem_log_stores[i].va), 725 store_addr_names[i]); 726 727 snprintf(store_width_names[i], NAME_LEN, "store_width_%d", i); 728 hex_store_width[i] = tcg_global_mem_new(cpu_env, 729 offsetof(CPUHexagonState, mem_log_stores[i].width), 730 store_width_names[i]); 731 732 snprintf(store_val32_names[i], NAME_LEN, "store_val32_%d", i); 733 hex_store_val32[i] = tcg_global_mem_new(cpu_env, 734 offsetof(CPUHexagonState, mem_log_stores[i].data32), 735 store_val32_names[i]); 736 737 snprintf(store_val64_names[i], NAME_LEN, "store_val64_%d", i); 738 hex_store_val64[i] = tcg_global_mem_new_i64(cpu_env, 739 offsetof(CPUHexagonState, mem_log_stores[i].data64), 740 store_val64_names[i]); 741 } 742 } 743