xref: /openbmc/qemu/target/hexagon/translate.c (revision 40f23e4e)
1 /*
2  *  Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
3  *
4  *  This program is free software; you can redistribute it and/or modify
5  *  it under the terms of the GNU General Public License as published by
6  *  the Free Software Foundation; either version 2 of the License, or
7  *  (at your option) any later version.
8  *
9  *  This program is distributed in the hope that it will be useful,
10  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
11  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12  *  GNU General Public License for more details.
13  *
14  *  You should have received a copy of the GNU General Public License
15  *  along with this program; if not, see <http://www.gnu.org/licenses/>.
16  */
17 
18 #define QEMU_GENERATE
19 #include "qemu/osdep.h"
20 #include "cpu.h"
21 #include "tcg/tcg-op.h"
22 #include "exec/cpu_ldst.h"
23 #include "exec/log.h"
24 #include "internal.h"
25 #include "attribs.h"
26 #include "insn.h"
27 #include "decode.h"
28 #include "translate.h"
29 #include "printinsn.h"
30 
31 TCGv hex_gpr[TOTAL_PER_THREAD_REGS];
32 TCGv hex_pred[NUM_PREGS];
33 TCGv hex_next_PC;
34 TCGv hex_this_PC;
35 TCGv hex_slot_cancelled;
36 TCGv hex_branch_taken;
37 TCGv hex_new_value[TOTAL_PER_THREAD_REGS];
38 TCGv hex_reg_written[TOTAL_PER_THREAD_REGS];
39 TCGv hex_new_pred_value[NUM_PREGS];
40 TCGv hex_pred_written;
41 TCGv hex_store_addr[STORES_MAX];
42 TCGv hex_store_width[STORES_MAX];
43 TCGv hex_store_val32[STORES_MAX];
44 TCGv_i64 hex_store_val64[STORES_MAX];
45 TCGv hex_pkt_has_store_s1;
46 TCGv hex_dczero_addr;
47 TCGv hex_llsc_addr;
48 TCGv hex_llsc_val;
49 TCGv_i64 hex_llsc_val_i64;
50 
51 static const char * const hexagon_prednames[] = {
52   "p0", "p1", "p2", "p3"
53 };
54 
55 static void gen_exception_raw(int excp)
56 {
57     TCGv_i32 helper_tmp = tcg_const_i32(excp);
58     gen_helper_raise_exception(cpu_env, helper_tmp);
59     tcg_temp_free_i32(helper_tmp);
60 }
61 
62 static void gen_exec_counters(DisasContext *ctx)
63 {
64     tcg_gen_addi_tl(hex_gpr[HEX_REG_QEMU_PKT_CNT],
65                     hex_gpr[HEX_REG_QEMU_PKT_CNT], ctx->num_packets);
66     tcg_gen_addi_tl(hex_gpr[HEX_REG_QEMU_INSN_CNT],
67                     hex_gpr[HEX_REG_QEMU_INSN_CNT], ctx->num_insns);
68 }
69 
70 static void gen_end_tb(DisasContext *ctx)
71 {
72     gen_exec_counters(ctx);
73     tcg_gen_mov_tl(hex_gpr[HEX_REG_PC], hex_next_PC);
74     if (ctx->base.singlestep_enabled) {
75         gen_exception_raw(EXCP_DEBUG);
76     } else {
77         tcg_gen_exit_tb(NULL, 0);
78     }
79     ctx->base.is_jmp = DISAS_NORETURN;
80 }
81 
82 static void gen_exception_end_tb(DisasContext *ctx, int excp)
83 {
84     gen_exec_counters(ctx);
85     tcg_gen_mov_tl(hex_gpr[HEX_REG_PC], hex_next_PC);
86     gen_exception_raw(excp);
87     ctx->base.is_jmp = DISAS_NORETURN;
88 
89 }
90 
91 #define PACKET_BUFFER_LEN              1028
92 static void print_pkt(Packet *pkt)
93 {
94     GString *buf = g_string_sized_new(PACKET_BUFFER_LEN);
95     snprint_a_pkt_debug(buf, pkt);
96     HEX_DEBUG_LOG("%s", buf->str);
97     g_string_free(buf, true);
98 }
99 #define HEX_DEBUG_PRINT_PKT(pkt) \
100     do { \
101         if (HEX_DEBUG) { \
102             print_pkt(pkt); \
103         } \
104     } while (0)
105 
106 static int read_packet_words(CPUHexagonState *env, DisasContext *ctx,
107                              uint32_t words[])
108 {
109     bool found_end = false;
110     int nwords, max_words;
111 
112     memset(words, 0, PACKET_WORDS_MAX * sizeof(uint32_t));
113     for (nwords = 0; !found_end && nwords < PACKET_WORDS_MAX; nwords++) {
114         words[nwords] =
115             translator_ldl(env, ctx->base.pc_next + nwords * sizeof(uint32_t));
116         found_end = is_packet_end(words[nwords]);
117     }
118     if (!found_end) {
119         /* Read too many words without finding the end */
120         return 0;
121     }
122 
123     /* Check for page boundary crossing */
124     max_words = -(ctx->base.pc_next | TARGET_PAGE_MASK) / sizeof(uint32_t);
125     if (nwords > max_words) {
126         /* We can only cross a page boundary at the beginning of a TB */
127         g_assert(ctx->base.num_insns == 1);
128     }
129 
130     HEX_DEBUG_LOG("decode_packet: pc = 0x%x\n", ctx->base.pc_next);
131     HEX_DEBUG_LOG("    words = { ");
132     for (int i = 0; i < nwords; i++) {
133         HEX_DEBUG_LOG("0x%x, ", words[i]);
134     }
135     HEX_DEBUG_LOG("}\n");
136 
137     return nwords;
138 }
139 
140 static bool check_for_attrib(Packet *pkt, int attrib)
141 {
142     for (int i = 0; i < pkt->num_insns; i++) {
143         if (GET_ATTRIB(pkt->insn[i].opcode, attrib)) {
144             return true;
145         }
146     }
147     return false;
148 }
149 
150 static bool need_pc(Packet *pkt)
151 {
152     return check_for_attrib(pkt, A_IMPLICIT_READS_PC);
153 }
154 
155 static bool need_slot_cancelled(Packet *pkt)
156 {
157     return check_for_attrib(pkt, A_CONDEXEC);
158 }
159 
160 static bool need_pred_written(Packet *pkt)
161 {
162     return check_for_attrib(pkt, A_WRITES_PRED_REG);
163 }
164 
165 static void gen_start_packet(DisasContext *ctx, Packet *pkt)
166 {
167     target_ulong next_PC = ctx->base.pc_next + pkt->encod_pkt_size_in_bytes;
168     int i;
169 
170     /* Clear out the disassembly context */
171     ctx->reg_log_idx = 0;
172     bitmap_zero(ctx->regs_written, TOTAL_PER_THREAD_REGS);
173     ctx->preg_log_idx = 0;
174     bitmap_zero(ctx->pregs_written, NUM_PREGS);
175     for (i = 0; i < STORES_MAX; i++) {
176         ctx->store_width[i] = 0;
177     }
178     tcg_gen_movi_tl(hex_pkt_has_store_s1, pkt->pkt_has_store_s1);
179     ctx->s1_store_processed = false;
180 
181     if (HEX_DEBUG) {
182         /* Handy place to set a breakpoint before the packet executes */
183         gen_helper_debug_start_packet(cpu_env);
184         tcg_gen_movi_tl(hex_this_PC, ctx->base.pc_next);
185     }
186 
187     /* Initialize the runtime state for packet semantics */
188     if (need_pc(pkt)) {
189         tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], ctx->base.pc_next);
190     }
191     if (need_slot_cancelled(pkt)) {
192         tcg_gen_movi_tl(hex_slot_cancelled, 0);
193     }
194     if (pkt->pkt_has_cof) {
195         tcg_gen_movi_tl(hex_branch_taken, 0);
196         tcg_gen_movi_tl(hex_next_PC, next_PC);
197     }
198     if (need_pred_written(pkt)) {
199         tcg_gen_movi_tl(hex_pred_written, 0);
200     }
201 }
202 
203 /*
204  * The LOG_*_WRITE macros mark most of the writes in a packet
205  * However, there are some implicit writes marked as attributes
206  * of the applicable instructions.
207  */
208 static void mark_implicit_reg_write(DisasContext *ctx, Insn *insn,
209                                     int attrib, int rnum)
210 {
211     if (GET_ATTRIB(insn->opcode, attrib)) {
212         bool is_predicated = GET_ATTRIB(insn->opcode, A_CONDEXEC);
213         if (is_predicated && !is_preloaded(ctx, rnum)) {
214             tcg_gen_mov_tl(hex_new_value[rnum], hex_gpr[rnum]);
215         }
216 
217         ctx_log_reg_write(ctx, rnum);
218     }
219 }
220 
221 static void mark_implicit_pred_write(DisasContext *ctx, Insn *insn,
222                                      int attrib, int pnum)
223 {
224     if (GET_ATTRIB(insn->opcode, attrib)) {
225         ctx_log_pred_write(ctx, pnum);
226     }
227 }
228 
229 static void mark_implicit_reg_writes(DisasContext *ctx, Insn *insn)
230 {
231     mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_FP,  HEX_REG_FP);
232     mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_SP,  HEX_REG_SP);
233     mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_LR,  HEX_REG_LR);
234     mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_LC0, HEX_REG_LC0);
235     mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_SA0, HEX_REG_SA0);
236     mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_LC1, HEX_REG_LC1);
237     mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_SA1, HEX_REG_SA1);
238 }
239 
240 static void mark_implicit_pred_writes(DisasContext *ctx, Insn *insn)
241 {
242     mark_implicit_pred_write(ctx, insn, A_IMPLICIT_WRITES_P0, 0);
243     mark_implicit_pred_write(ctx, insn, A_IMPLICIT_WRITES_P1, 1);
244     mark_implicit_pred_write(ctx, insn, A_IMPLICIT_WRITES_P2, 2);
245     mark_implicit_pred_write(ctx, insn, A_IMPLICIT_WRITES_P3, 3);
246 }
247 
248 static void gen_insn(CPUHexagonState *env, DisasContext *ctx,
249                      Insn *insn, Packet *pkt)
250 {
251     if (insn->generate) {
252         mark_implicit_reg_writes(ctx, insn);
253         insn->generate(env, ctx, insn, pkt);
254         mark_implicit_pred_writes(ctx, insn);
255     } else {
256         gen_exception_end_tb(ctx, HEX_EXCP_INVALID_OPCODE);
257     }
258 }
259 
260 /*
261  * Helpers for generating the packet commit
262  */
263 static void gen_reg_writes(DisasContext *ctx)
264 {
265     int i;
266 
267     for (i = 0; i < ctx->reg_log_idx; i++) {
268         int reg_num = ctx->reg_log[i];
269 
270         tcg_gen_mov_tl(hex_gpr[reg_num], hex_new_value[reg_num]);
271     }
272 }
273 
274 static void gen_pred_writes(DisasContext *ctx, Packet *pkt)
275 {
276     int i;
277 
278     /* Early exit if the log is empty */
279     if (!ctx->preg_log_idx) {
280         return;
281     }
282 
283     /*
284      * Only endloop instructions will conditionally
285      * write a predicate.  If there are no endloop
286      * instructions, we can use the non-conditional
287      * write of the predicates.
288      */
289     if (pkt->pkt_has_endloop) {
290         TCGv zero = tcg_const_tl(0);
291         TCGv pred_written = tcg_temp_new();
292         for (i = 0; i < ctx->preg_log_idx; i++) {
293             int pred_num = ctx->preg_log[i];
294 
295             tcg_gen_andi_tl(pred_written, hex_pred_written, 1 << pred_num);
296             tcg_gen_movcond_tl(TCG_COND_NE, hex_pred[pred_num],
297                                pred_written, zero,
298                                hex_new_pred_value[pred_num],
299                                hex_pred[pred_num]);
300         }
301         tcg_temp_free(zero);
302         tcg_temp_free(pred_written);
303     } else {
304         for (i = 0; i < ctx->preg_log_idx; i++) {
305             int pred_num = ctx->preg_log[i];
306             tcg_gen_mov_tl(hex_pred[pred_num], hex_new_pred_value[pred_num]);
307             if (HEX_DEBUG) {
308                 /* Do this so HELPER(debug_commit_end) will know */
309                 tcg_gen_ori_tl(hex_pred_written, hex_pred_written,
310                                1 << pred_num);
311             }
312         }
313     }
314 }
315 
316 static void gen_check_store_width(DisasContext *ctx, int slot_num)
317 {
318     if (HEX_DEBUG) {
319         TCGv slot = tcg_const_tl(slot_num);
320         TCGv check = tcg_const_tl(ctx->store_width[slot_num]);
321         gen_helper_debug_check_store_width(cpu_env, slot, check);
322         tcg_temp_free(slot);
323         tcg_temp_free(check);
324     }
325 }
326 
327 static bool slot_is_predicated(Packet *pkt, int slot_num)
328 {
329     for (int i = 0; i < pkt->num_insns; i++) {
330         if (pkt->insn[i].slot == slot_num) {
331             return GET_ATTRIB(pkt->insn[i].opcode, A_CONDEXEC);
332         }
333     }
334     /* If we get to here, we didn't find an instruction in the requested slot */
335     g_assert_not_reached();
336 }
337 
338 void process_store(DisasContext *ctx, Packet *pkt, int slot_num)
339 {
340     bool is_predicated = slot_is_predicated(pkt, slot_num);
341     TCGLabel *label_end = NULL;
342 
343     /*
344      * We may have already processed this store
345      * See CHECK_NOSHUF in macros.h
346      */
347     if (slot_num == 1 && ctx->s1_store_processed) {
348         return;
349     }
350     ctx->s1_store_processed = true;
351 
352     if (is_predicated) {
353         TCGv cancelled = tcg_temp_new();
354         label_end = gen_new_label();
355 
356         /* Don't do anything if the slot was cancelled */
357         tcg_gen_extract_tl(cancelled, hex_slot_cancelled, slot_num, 1);
358         tcg_gen_brcondi_tl(TCG_COND_NE, cancelled, 0, label_end);
359         tcg_temp_free(cancelled);
360     }
361     {
362         TCGv address = tcg_temp_local_new();
363         tcg_gen_mov_tl(address, hex_store_addr[slot_num]);
364 
365         /*
366          * If we know the width from the DisasContext, we can
367          * generate much cleaner code.
368          * Unfortunately, not all instructions execute the fSTORE
369          * macro during code generation.  Anything that uses the
370          * generic helper will have this problem.  Instructions
371          * that use fWRAP to generate proper TCG code will be OK.
372          */
373         switch (ctx->store_width[slot_num]) {
374         case 1:
375             gen_check_store_width(ctx, slot_num);
376             tcg_gen_qemu_st8(hex_store_val32[slot_num],
377                              hex_store_addr[slot_num],
378                              ctx->mem_idx);
379             break;
380         case 2:
381             gen_check_store_width(ctx, slot_num);
382             tcg_gen_qemu_st16(hex_store_val32[slot_num],
383                               hex_store_addr[slot_num],
384                               ctx->mem_idx);
385             break;
386         case 4:
387             gen_check_store_width(ctx, slot_num);
388             tcg_gen_qemu_st32(hex_store_val32[slot_num],
389                               hex_store_addr[slot_num],
390                               ctx->mem_idx);
391             break;
392         case 8:
393             gen_check_store_width(ctx, slot_num);
394             tcg_gen_qemu_st64(hex_store_val64[slot_num],
395                               hex_store_addr[slot_num],
396                               ctx->mem_idx);
397             break;
398         default:
399             {
400                 /*
401                  * If we get to here, we don't know the width at
402                  * TCG generation time, we'll use a helper to
403                  * avoid branching based on the width at runtime.
404                  */
405                 TCGv slot = tcg_const_tl(slot_num);
406                 gen_helper_commit_store(cpu_env, slot);
407                 tcg_temp_free(slot);
408             }
409         }
410         tcg_temp_free(address);
411     }
412     if (is_predicated) {
413         gen_set_label(label_end);
414     }
415 }
416 
417 static void process_store_log(DisasContext *ctx, Packet *pkt)
418 {
419     /*
420      *  When a packet has two stores, the hardware processes
421      *  slot 1 and then slot 2.  This will be important when
422      *  the memory accesses overlap.
423      */
424     if (pkt->pkt_has_store_s1 && !pkt->pkt_has_dczeroa) {
425         process_store(ctx, pkt, 1);
426     }
427     if (pkt->pkt_has_store_s0 && !pkt->pkt_has_dczeroa) {
428         process_store(ctx, pkt, 0);
429     }
430 }
431 
432 /* Zero out a 32-bit cache line */
433 static void process_dczeroa(DisasContext *ctx, Packet *pkt)
434 {
435     if (pkt->pkt_has_dczeroa) {
436         /* Store 32 bytes of zero starting at (addr & ~0x1f) */
437         TCGv addr = tcg_temp_new();
438         TCGv_i64 zero = tcg_const_i64(0);
439 
440         tcg_gen_andi_tl(addr, hex_dczero_addr, ~0x1f);
441         tcg_gen_qemu_st64(zero, addr, ctx->mem_idx);
442         tcg_gen_addi_tl(addr, addr, 8);
443         tcg_gen_qemu_st64(zero, addr, ctx->mem_idx);
444         tcg_gen_addi_tl(addr, addr, 8);
445         tcg_gen_qemu_st64(zero, addr, ctx->mem_idx);
446         tcg_gen_addi_tl(addr, addr, 8);
447         tcg_gen_qemu_st64(zero, addr, ctx->mem_idx);
448 
449         tcg_temp_free(addr);
450         tcg_temp_free_i64(zero);
451     }
452 }
453 
454 static void update_exec_counters(DisasContext *ctx, Packet *pkt)
455 {
456     int num_insns = pkt->num_insns;
457     int num_real_insns = 0;
458 
459     for (int i = 0; i < num_insns; i++) {
460         if (!pkt->insn[i].is_endloop &&
461             !pkt->insn[i].part1 &&
462             !GET_ATTRIB(pkt->insn[i].opcode, A_IT_NOP)) {
463             num_real_insns++;
464         }
465     }
466 
467     ctx->num_packets++;
468     ctx->num_insns += num_real_insns;
469 }
470 
471 static void gen_commit_packet(DisasContext *ctx, Packet *pkt)
472 {
473     gen_reg_writes(ctx);
474     gen_pred_writes(ctx, pkt);
475     process_store_log(ctx, pkt);
476     process_dczeroa(ctx, pkt);
477     update_exec_counters(ctx, pkt);
478     if (HEX_DEBUG) {
479         TCGv has_st0 =
480             tcg_const_tl(pkt->pkt_has_store_s0 && !pkt->pkt_has_dczeroa);
481         TCGv has_st1 =
482             tcg_const_tl(pkt->pkt_has_store_s1 && !pkt->pkt_has_dczeroa);
483 
484         /* Handy place to set a breakpoint at the end of execution */
485         gen_helper_debug_commit_end(cpu_env, has_st0, has_st1);
486 
487         tcg_temp_free(has_st0);
488         tcg_temp_free(has_st1);
489     }
490 
491     if (pkt->pkt_has_cof) {
492         gen_end_tb(ctx);
493     }
494 }
495 
496 static void decode_and_translate_packet(CPUHexagonState *env, DisasContext *ctx)
497 {
498     uint32_t words[PACKET_WORDS_MAX];
499     int nwords;
500     Packet pkt;
501     int i;
502 
503     nwords = read_packet_words(env, ctx, words);
504     if (!nwords) {
505         gen_exception_end_tb(ctx, HEX_EXCP_INVALID_PACKET);
506         return;
507     }
508 
509     if (decode_packet(nwords, words, &pkt, false) > 0) {
510         HEX_DEBUG_PRINT_PKT(&pkt);
511         gen_start_packet(ctx, &pkt);
512         for (i = 0; i < pkt.num_insns; i++) {
513             gen_insn(env, ctx, &pkt.insn[i], &pkt);
514         }
515         gen_commit_packet(ctx, &pkt);
516         ctx->base.pc_next += pkt.encod_pkt_size_in_bytes;
517     } else {
518         gen_exception_end_tb(ctx, HEX_EXCP_INVALID_PACKET);
519     }
520 }
521 
522 static void hexagon_tr_init_disas_context(DisasContextBase *dcbase,
523                                           CPUState *cs)
524 {
525     DisasContext *ctx = container_of(dcbase, DisasContext, base);
526 
527     ctx->mem_idx = MMU_USER_IDX;
528     ctx->num_packets = 0;
529     ctx->num_insns = 0;
530 }
531 
532 static void hexagon_tr_tb_start(DisasContextBase *db, CPUState *cpu)
533 {
534 }
535 
536 static void hexagon_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
537 {
538     DisasContext *ctx = container_of(dcbase, DisasContext, base);
539 
540     tcg_gen_insn_start(ctx->base.pc_next);
541 }
542 
543 static bool hexagon_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu,
544                                         const CPUBreakpoint *bp)
545 {
546     DisasContext *ctx = container_of(dcbase, DisasContext, base);
547 
548     gen_exception_end_tb(ctx, EXCP_DEBUG);
549     /*
550      * The address covered by the breakpoint must be included in
551      * [tb->pc, tb->pc + tb->size) in order to for it to be
552      * properly cleared -- thus we increment the PC here so that
553      * the logic setting tb->size below does the right thing.
554      */
555     ctx->base.pc_next += 4;
556     return true;
557 }
558 
559 static bool pkt_crosses_page(CPUHexagonState *env, DisasContext *ctx)
560 {
561     target_ulong page_start = ctx->base.pc_first & TARGET_PAGE_MASK;
562     bool found_end = false;
563     int nwords;
564 
565     for (nwords = 0; !found_end && nwords < PACKET_WORDS_MAX; nwords++) {
566         uint32_t word = cpu_ldl_code(env,
567                             ctx->base.pc_next + nwords * sizeof(uint32_t));
568         found_end = is_packet_end(word);
569     }
570     uint32_t next_ptr =  ctx->base.pc_next + nwords * sizeof(uint32_t);
571     return found_end && next_ptr - page_start >= TARGET_PAGE_SIZE;
572 }
573 
574 static void hexagon_tr_translate_packet(DisasContextBase *dcbase, CPUState *cpu)
575 {
576     DisasContext *ctx = container_of(dcbase, DisasContext, base);
577     CPUHexagonState *env = cpu->env_ptr;
578 
579     decode_and_translate_packet(env, ctx);
580 
581     if (ctx->base.is_jmp == DISAS_NEXT) {
582         target_ulong page_start = ctx->base.pc_first & TARGET_PAGE_MASK;
583         target_ulong bytes_max = PACKET_WORDS_MAX * sizeof(target_ulong);
584 
585         if (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE ||
586             (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE - bytes_max &&
587              pkt_crosses_page(env, ctx))) {
588             ctx->base.is_jmp = DISAS_TOO_MANY;
589         }
590 
591         /*
592          * The CPU log is used to compare against LLDB single stepping,
593          * so end the TLB after every packet.
594          */
595         HexagonCPU *hex_cpu = env_archcpu(env);
596         if (hex_cpu->lldb_compat && qemu_loglevel_mask(CPU_LOG_TB_CPU)) {
597             ctx->base.is_jmp = DISAS_TOO_MANY;
598         }
599     }
600 }
601 
602 static void hexagon_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
603 {
604     DisasContext *ctx = container_of(dcbase, DisasContext, base);
605 
606     switch (ctx->base.is_jmp) {
607     case DISAS_TOO_MANY:
608         gen_exec_counters(ctx);
609         tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], ctx->base.pc_next);
610         if (ctx->base.singlestep_enabled) {
611             gen_exception_raw(EXCP_DEBUG);
612         } else {
613             tcg_gen_exit_tb(NULL, 0);
614         }
615         break;
616     case DISAS_NORETURN:
617         break;
618     default:
619         g_assert_not_reached();
620     }
621 }
622 
623 static void hexagon_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu)
624 {
625     qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first));
626     log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size);
627 }
628 
629 
630 static const TranslatorOps hexagon_tr_ops = {
631     .init_disas_context = hexagon_tr_init_disas_context,
632     .tb_start           = hexagon_tr_tb_start,
633     .insn_start         = hexagon_tr_insn_start,
634     .breakpoint_check   = hexagon_tr_breakpoint_check,
635     .translate_insn     = hexagon_tr_translate_packet,
636     .tb_stop            = hexagon_tr_tb_stop,
637     .disas_log          = hexagon_tr_disas_log,
638 };
639 
640 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
641 {
642     DisasContext ctx;
643 
644     translator_loop(&hexagon_tr_ops, &ctx.base, cs, tb, max_insns);
645 }
646 
647 #define NAME_LEN               64
648 static char new_value_names[TOTAL_PER_THREAD_REGS][NAME_LEN];
649 static char reg_written_names[TOTAL_PER_THREAD_REGS][NAME_LEN];
650 static char new_pred_value_names[NUM_PREGS][NAME_LEN];
651 static char store_addr_names[STORES_MAX][NAME_LEN];
652 static char store_width_names[STORES_MAX][NAME_LEN];
653 static char store_val32_names[STORES_MAX][NAME_LEN];
654 static char store_val64_names[STORES_MAX][NAME_LEN];
655 
656 void hexagon_translate_init(void)
657 {
658     int i;
659 
660     opcode_init();
661 
662     if (HEX_DEBUG) {
663         if (!qemu_logfile) {
664             qemu_set_log(qemu_loglevel);
665         }
666     }
667 
668     for (i = 0; i < TOTAL_PER_THREAD_REGS; i++) {
669         hex_gpr[i] = tcg_global_mem_new(cpu_env,
670             offsetof(CPUHexagonState, gpr[i]),
671             hexagon_regnames[i]);
672 
673         snprintf(new_value_names[i], NAME_LEN, "new_%s", hexagon_regnames[i]);
674         hex_new_value[i] = tcg_global_mem_new(cpu_env,
675             offsetof(CPUHexagonState, new_value[i]),
676             new_value_names[i]);
677 
678         if (HEX_DEBUG) {
679             snprintf(reg_written_names[i], NAME_LEN, "reg_written_%s",
680                      hexagon_regnames[i]);
681             hex_reg_written[i] = tcg_global_mem_new(cpu_env,
682                 offsetof(CPUHexagonState, reg_written[i]),
683                 reg_written_names[i]);
684         }
685     }
686     for (i = 0; i < NUM_PREGS; i++) {
687         hex_pred[i] = tcg_global_mem_new(cpu_env,
688             offsetof(CPUHexagonState, pred[i]),
689             hexagon_prednames[i]);
690 
691         snprintf(new_pred_value_names[i], NAME_LEN, "new_pred_%s",
692                  hexagon_prednames[i]);
693         hex_new_pred_value[i] = tcg_global_mem_new(cpu_env,
694             offsetof(CPUHexagonState, new_pred_value[i]),
695             new_pred_value_names[i]);
696     }
697     hex_pred_written = tcg_global_mem_new(cpu_env,
698         offsetof(CPUHexagonState, pred_written), "pred_written");
699     hex_next_PC = tcg_global_mem_new(cpu_env,
700         offsetof(CPUHexagonState, next_PC), "next_PC");
701     hex_this_PC = tcg_global_mem_new(cpu_env,
702         offsetof(CPUHexagonState, this_PC), "this_PC");
703     hex_slot_cancelled = tcg_global_mem_new(cpu_env,
704         offsetof(CPUHexagonState, slot_cancelled), "slot_cancelled");
705     hex_branch_taken = tcg_global_mem_new(cpu_env,
706         offsetof(CPUHexagonState, branch_taken), "branch_taken");
707     hex_pkt_has_store_s1 = tcg_global_mem_new(cpu_env,
708         offsetof(CPUHexagonState, pkt_has_store_s1), "pkt_has_store_s1");
709     hex_dczero_addr = tcg_global_mem_new(cpu_env,
710         offsetof(CPUHexagonState, dczero_addr), "dczero_addr");
711     hex_llsc_addr = tcg_global_mem_new(cpu_env,
712         offsetof(CPUHexagonState, llsc_addr), "llsc_addr");
713     hex_llsc_val = tcg_global_mem_new(cpu_env,
714         offsetof(CPUHexagonState, llsc_val), "llsc_val");
715     hex_llsc_val_i64 = tcg_global_mem_new_i64(cpu_env,
716         offsetof(CPUHexagonState, llsc_val_i64), "llsc_val_i64");
717     for (i = 0; i < STORES_MAX; i++) {
718         snprintf(store_addr_names[i], NAME_LEN, "store_addr_%d", i);
719         hex_store_addr[i] = tcg_global_mem_new(cpu_env,
720             offsetof(CPUHexagonState, mem_log_stores[i].va),
721             store_addr_names[i]);
722 
723         snprintf(store_width_names[i], NAME_LEN, "store_width_%d", i);
724         hex_store_width[i] = tcg_global_mem_new(cpu_env,
725             offsetof(CPUHexagonState, mem_log_stores[i].width),
726             store_width_names[i]);
727 
728         snprintf(store_val32_names[i], NAME_LEN, "store_val32_%d", i);
729         hex_store_val32[i] = tcg_global_mem_new(cpu_env,
730             offsetof(CPUHexagonState, mem_log_stores[i].data32),
731             store_val32_names[i]);
732 
733         snprintf(store_val64_names[i], NAME_LEN, "store_val64_%d", i);
734         hex_store_val64[i] = tcg_global_mem_new_i64(cpu_env,
735             offsetof(CPUHexagonState, mem_log_stores[i].data64),
736             store_val64_names[i]);
737     }
738 }
739