1 /* 2 * Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #define QEMU_GENERATE 19 #include "qemu/osdep.h" 20 #include "cpu.h" 21 #include "tcg/tcg-op.h" 22 #include "exec/cpu_ldst.h" 23 #include "exec/log.h" 24 #include "internal.h" 25 #include "attribs.h" 26 #include "insn.h" 27 #include "decode.h" 28 #include "translate.h" 29 #include "printinsn.h" 30 31 TCGv hex_gpr[TOTAL_PER_THREAD_REGS]; 32 TCGv hex_pred[NUM_PREGS]; 33 TCGv hex_next_PC; 34 TCGv hex_this_PC; 35 TCGv hex_slot_cancelled; 36 TCGv hex_branch_taken; 37 TCGv hex_new_value[TOTAL_PER_THREAD_REGS]; 38 TCGv hex_reg_written[TOTAL_PER_THREAD_REGS]; 39 TCGv hex_new_pred_value[NUM_PREGS]; 40 TCGv hex_pred_written; 41 TCGv hex_store_addr[STORES_MAX]; 42 TCGv hex_store_width[STORES_MAX]; 43 TCGv hex_store_val32[STORES_MAX]; 44 TCGv_i64 hex_store_val64[STORES_MAX]; 45 TCGv hex_pkt_has_store_s1; 46 TCGv hex_dczero_addr; 47 TCGv hex_llsc_addr; 48 TCGv hex_llsc_val; 49 TCGv_i64 hex_llsc_val_i64; 50 51 static const char * const hexagon_prednames[] = { 52 "p0", "p1", "p2", "p3" 53 }; 54 55 static void gen_exception_raw(int excp) 56 { 57 TCGv_i32 helper_tmp = tcg_const_i32(excp); 58 gen_helper_raise_exception(cpu_env, helper_tmp); 59 tcg_temp_free_i32(helper_tmp); 60 } 61 62 static void gen_exec_counters(DisasContext *ctx) 63 { 64 tcg_gen_addi_tl(hex_gpr[HEX_REG_QEMU_PKT_CNT], 65 hex_gpr[HEX_REG_QEMU_PKT_CNT], ctx->num_packets); 66 tcg_gen_addi_tl(hex_gpr[HEX_REG_QEMU_INSN_CNT], 67 hex_gpr[HEX_REG_QEMU_INSN_CNT], ctx->num_insns); 68 } 69 70 static void gen_end_tb(DisasContext *ctx) 71 { 72 gen_exec_counters(ctx); 73 tcg_gen_mov_tl(hex_gpr[HEX_REG_PC], hex_next_PC); 74 if (ctx->base.singlestep_enabled) { 75 gen_exception_raw(EXCP_DEBUG); 76 } else { 77 tcg_gen_exit_tb(NULL, 0); 78 } 79 ctx->base.is_jmp = DISAS_NORETURN; 80 } 81 82 static void gen_exception_end_tb(DisasContext *ctx, int excp) 83 { 84 gen_exec_counters(ctx); 85 tcg_gen_mov_tl(hex_gpr[HEX_REG_PC], hex_next_PC); 86 gen_exception_raw(excp); 87 ctx->base.is_jmp = DISAS_NORETURN; 88 89 } 90 91 #define PACKET_BUFFER_LEN 1028 92 static void print_pkt(Packet *pkt) 93 { 94 GString *buf = g_string_sized_new(PACKET_BUFFER_LEN); 95 snprint_a_pkt_debug(buf, pkt); 96 HEX_DEBUG_LOG("%s", buf->str); 97 g_string_free(buf, true); 98 } 99 #define HEX_DEBUG_PRINT_PKT(pkt) \ 100 do { \ 101 if (HEX_DEBUG) { \ 102 print_pkt(pkt); \ 103 } \ 104 } while (0) 105 106 static int read_packet_words(CPUHexagonState *env, DisasContext *ctx, 107 uint32_t words[]) 108 { 109 bool found_end = false; 110 int nwords, max_words; 111 112 memset(words, 0, PACKET_WORDS_MAX * sizeof(uint32_t)); 113 for (nwords = 0; !found_end && nwords < PACKET_WORDS_MAX; nwords++) { 114 words[nwords] = 115 translator_ldl(env, &ctx->base, 116 ctx->base.pc_next + nwords * sizeof(uint32_t)); 117 found_end = is_packet_end(words[nwords]); 118 } 119 if (!found_end) { 120 /* Read too many words without finding the end */ 121 return 0; 122 } 123 124 /* Check for page boundary crossing */ 125 max_words = -(ctx->base.pc_next | TARGET_PAGE_MASK) / sizeof(uint32_t); 126 if (nwords > max_words) { 127 /* We can only cross a page boundary at the beginning of a TB */ 128 g_assert(ctx->base.num_insns == 1); 129 } 130 131 HEX_DEBUG_LOG("decode_packet: pc = 0x%x\n", ctx->base.pc_next); 132 HEX_DEBUG_LOG(" words = { "); 133 for (int i = 0; i < nwords; i++) { 134 HEX_DEBUG_LOG("0x%x, ", words[i]); 135 } 136 HEX_DEBUG_LOG("}\n"); 137 138 return nwords; 139 } 140 141 static bool check_for_attrib(Packet *pkt, int attrib) 142 { 143 for (int i = 0; i < pkt->num_insns; i++) { 144 if (GET_ATTRIB(pkt->insn[i].opcode, attrib)) { 145 return true; 146 } 147 } 148 return false; 149 } 150 151 static bool need_pc(Packet *pkt) 152 { 153 return check_for_attrib(pkt, A_IMPLICIT_READS_PC); 154 } 155 156 static bool need_slot_cancelled(Packet *pkt) 157 { 158 return check_for_attrib(pkt, A_CONDEXEC); 159 } 160 161 static bool need_pred_written(Packet *pkt) 162 { 163 return check_for_attrib(pkt, A_WRITES_PRED_REG); 164 } 165 166 static void gen_start_packet(DisasContext *ctx, Packet *pkt) 167 { 168 target_ulong next_PC = ctx->base.pc_next + pkt->encod_pkt_size_in_bytes; 169 int i; 170 171 /* Clear out the disassembly context */ 172 ctx->reg_log_idx = 0; 173 bitmap_zero(ctx->regs_written, TOTAL_PER_THREAD_REGS); 174 ctx->preg_log_idx = 0; 175 bitmap_zero(ctx->pregs_written, NUM_PREGS); 176 for (i = 0; i < STORES_MAX; i++) { 177 ctx->store_width[i] = 0; 178 } 179 tcg_gen_movi_tl(hex_pkt_has_store_s1, pkt->pkt_has_store_s1); 180 ctx->s1_store_processed = false; 181 182 if (HEX_DEBUG) { 183 /* Handy place to set a breakpoint before the packet executes */ 184 gen_helper_debug_start_packet(cpu_env); 185 tcg_gen_movi_tl(hex_this_PC, ctx->base.pc_next); 186 } 187 188 /* Initialize the runtime state for packet semantics */ 189 if (need_pc(pkt)) { 190 tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], ctx->base.pc_next); 191 } 192 if (need_slot_cancelled(pkt)) { 193 tcg_gen_movi_tl(hex_slot_cancelled, 0); 194 } 195 if (pkt->pkt_has_cof) { 196 tcg_gen_movi_tl(hex_branch_taken, 0); 197 tcg_gen_movi_tl(hex_next_PC, next_PC); 198 } 199 if (need_pred_written(pkt)) { 200 tcg_gen_movi_tl(hex_pred_written, 0); 201 } 202 } 203 204 /* 205 * The LOG_*_WRITE macros mark most of the writes in a packet 206 * However, there are some implicit writes marked as attributes 207 * of the applicable instructions. 208 */ 209 static void mark_implicit_reg_write(DisasContext *ctx, Insn *insn, 210 int attrib, int rnum) 211 { 212 if (GET_ATTRIB(insn->opcode, attrib)) { 213 bool is_predicated = GET_ATTRIB(insn->opcode, A_CONDEXEC); 214 if (is_predicated && !is_preloaded(ctx, rnum)) { 215 tcg_gen_mov_tl(hex_new_value[rnum], hex_gpr[rnum]); 216 } 217 218 ctx_log_reg_write(ctx, rnum); 219 } 220 } 221 222 static void mark_implicit_pred_write(DisasContext *ctx, Insn *insn, 223 int attrib, int pnum) 224 { 225 if (GET_ATTRIB(insn->opcode, attrib)) { 226 ctx_log_pred_write(ctx, pnum); 227 } 228 } 229 230 static void mark_implicit_reg_writes(DisasContext *ctx, Insn *insn) 231 { 232 mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_FP, HEX_REG_FP); 233 mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_SP, HEX_REG_SP); 234 mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_LR, HEX_REG_LR); 235 mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_LC0, HEX_REG_LC0); 236 mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_SA0, HEX_REG_SA0); 237 mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_LC1, HEX_REG_LC1); 238 mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_SA1, HEX_REG_SA1); 239 } 240 241 static void mark_implicit_pred_writes(DisasContext *ctx, Insn *insn) 242 { 243 mark_implicit_pred_write(ctx, insn, A_IMPLICIT_WRITES_P0, 0); 244 mark_implicit_pred_write(ctx, insn, A_IMPLICIT_WRITES_P1, 1); 245 mark_implicit_pred_write(ctx, insn, A_IMPLICIT_WRITES_P2, 2); 246 mark_implicit_pred_write(ctx, insn, A_IMPLICIT_WRITES_P3, 3); 247 } 248 249 static void gen_insn(CPUHexagonState *env, DisasContext *ctx, 250 Insn *insn, Packet *pkt) 251 { 252 if (insn->generate) { 253 mark_implicit_reg_writes(ctx, insn); 254 insn->generate(env, ctx, insn, pkt); 255 mark_implicit_pred_writes(ctx, insn); 256 } else { 257 gen_exception_end_tb(ctx, HEX_EXCP_INVALID_OPCODE); 258 } 259 } 260 261 /* 262 * Helpers for generating the packet commit 263 */ 264 static void gen_reg_writes(DisasContext *ctx) 265 { 266 int i; 267 268 for (i = 0; i < ctx->reg_log_idx; i++) { 269 int reg_num = ctx->reg_log[i]; 270 271 tcg_gen_mov_tl(hex_gpr[reg_num], hex_new_value[reg_num]); 272 } 273 } 274 275 static void gen_pred_writes(DisasContext *ctx, Packet *pkt) 276 { 277 int i; 278 279 /* Early exit if the log is empty */ 280 if (!ctx->preg_log_idx) { 281 return; 282 } 283 284 /* 285 * Only endloop instructions will conditionally 286 * write a predicate. If there are no endloop 287 * instructions, we can use the non-conditional 288 * write of the predicates. 289 */ 290 if (pkt->pkt_has_endloop) { 291 TCGv zero = tcg_const_tl(0); 292 TCGv pred_written = tcg_temp_new(); 293 for (i = 0; i < ctx->preg_log_idx; i++) { 294 int pred_num = ctx->preg_log[i]; 295 296 tcg_gen_andi_tl(pred_written, hex_pred_written, 1 << pred_num); 297 tcg_gen_movcond_tl(TCG_COND_NE, hex_pred[pred_num], 298 pred_written, zero, 299 hex_new_pred_value[pred_num], 300 hex_pred[pred_num]); 301 } 302 tcg_temp_free(zero); 303 tcg_temp_free(pred_written); 304 } else { 305 for (i = 0; i < ctx->preg_log_idx; i++) { 306 int pred_num = ctx->preg_log[i]; 307 tcg_gen_mov_tl(hex_pred[pred_num], hex_new_pred_value[pred_num]); 308 if (HEX_DEBUG) { 309 /* Do this so HELPER(debug_commit_end) will know */ 310 tcg_gen_ori_tl(hex_pred_written, hex_pred_written, 311 1 << pred_num); 312 } 313 } 314 } 315 } 316 317 static void gen_check_store_width(DisasContext *ctx, int slot_num) 318 { 319 if (HEX_DEBUG) { 320 TCGv slot = tcg_const_tl(slot_num); 321 TCGv check = tcg_const_tl(ctx->store_width[slot_num]); 322 gen_helper_debug_check_store_width(cpu_env, slot, check); 323 tcg_temp_free(slot); 324 tcg_temp_free(check); 325 } 326 } 327 328 static bool slot_is_predicated(Packet *pkt, int slot_num) 329 { 330 for (int i = 0; i < pkt->num_insns; i++) { 331 if (pkt->insn[i].slot == slot_num) { 332 return GET_ATTRIB(pkt->insn[i].opcode, A_CONDEXEC); 333 } 334 } 335 /* If we get to here, we didn't find an instruction in the requested slot */ 336 g_assert_not_reached(); 337 } 338 339 void process_store(DisasContext *ctx, Packet *pkt, int slot_num) 340 { 341 bool is_predicated = slot_is_predicated(pkt, slot_num); 342 TCGLabel *label_end = NULL; 343 344 /* 345 * We may have already processed this store 346 * See CHECK_NOSHUF in macros.h 347 */ 348 if (slot_num == 1 && ctx->s1_store_processed) { 349 return; 350 } 351 ctx->s1_store_processed = true; 352 353 if (is_predicated) { 354 TCGv cancelled = tcg_temp_new(); 355 label_end = gen_new_label(); 356 357 /* Don't do anything if the slot was cancelled */ 358 tcg_gen_extract_tl(cancelled, hex_slot_cancelled, slot_num, 1); 359 tcg_gen_brcondi_tl(TCG_COND_NE, cancelled, 0, label_end); 360 tcg_temp_free(cancelled); 361 } 362 { 363 TCGv address = tcg_temp_local_new(); 364 tcg_gen_mov_tl(address, hex_store_addr[slot_num]); 365 366 /* 367 * If we know the width from the DisasContext, we can 368 * generate much cleaner code. 369 * Unfortunately, not all instructions execute the fSTORE 370 * macro during code generation. Anything that uses the 371 * generic helper will have this problem. Instructions 372 * that use fWRAP to generate proper TCG code will be OK. 373 */ 374 switch (ctx->store_width[slot_num]) { 375 case 1: 376 gen_check_store_width(ctx, slot_num); 377 tcg_gen_qemu_st8(hex_store_val32[slot_num], 378 hex_store_addr[slot_num], 379 ctx->mem_idx); 380 break; 381 case 2: 382 gen_check_store_width(ctx, slot_num); 383 tcg_gen_qemu_st16(hex_store_val32[slot_num], 384 hex_store_addr[slot_num], 385 ctx->mem_idx); 386 break; 387 case 4: 388 gen_check_store_width(ctx, slot_num); 389 tcg_gen_qemu_st32(hex_store_val32[slot_num], 390 hex_store_addr[slot_num], 391 ctx->mem_idx); 392 break; 393 case 8: 394 gen_check_store_width(ctx, slot_num); 395 tcg_gen_qemu_st64(hex_store_val64[slot_num], 396 hex_store_addr[slot_num], 397 ctx->mem_idx); 398 break; 399 default: 400 { 401 /* 402 * If we get to here, we don't know the width at 403 * TCG generation time, we'll use a helper to 404 * avoid branching based on the width at runtime. 405 */ 406 TCGv slot = tcg_const_tl(slot_num); 407 gen_helper_commit_store(cpu_env, slot); 408 tcg_temp_free(slot); 409 } 410 } 411 tcg_temp_free(address); 412 } 413 if (is_predicated) { 414 gen_set_label(label_end); 415 } 416 } 417 418 static void process_store_log(DisasContext *ctx, Packet *pkt) 419 { 420 /* 421 * When a packet has two stores, the hardware processes 422 * slot 1 and then slot 2. This will be important when 423 * the memory accesses overlap. 424 */ 425 if (pkt->pkt_has_store_s1 && !pkt->pkt_has_dczeroa) { 426 process_store(ctx, pkt, 1); 427 } 428 if (pkt->pkt_has_store_s0 && !pkt->pkt_has_dczeroa) { 429 process_store(ctx, pkt, 0); 430 } 431 } 432 433 /* Zero out a 32-bit cache line */ 434 static void process_dczeroa(DisasContext *ctx, Packet *pkt) 435 { 436 if (pkt->pkt_has_dczeroa) { 437 /* Store 32 bytes of zero starting at (addr & ~0x1f) */ 438 TCGv addr = tcg_temp_new(); 439 TCGv_i64 zero = tcg_const_i64(0); 440 441 tcg_gen_andi_tl(addr, hex_dczero_addr, ~0x1f); 442 tcg_gen_qemu_st64(zero, addr, ctx->mem_idx); 443 tcg_gen_addi_tl(addr, addr, 8); 444 tcg_gen_qemu_st64(zero, addr, ctx->mem_idx); 445 tcg_gen_addi_tl(addr, addr, 8); 446 tcg_gen_qemu_st64(zero, addr, ctx->mem_idx); 447 tcg_gen_addi_tl(addr, addr, 8); 448 tcg_gen_qemu_st64(zero, addr, ctx->mem_idx); 449 450 tcg_temp_free(addr); 451 tcg_temp_free_i64(zero); 452 } 453 } 454 455 static void update_exec_counters(DisasContext *ctx, Packet *pkt) 456 { 457 int num_insns = pkt->num_insns; 458 int num_real_insns = 0; 459 460 for (int i = 0; i < num_insns; i++) { 461 if (!pkt->insn[i].is_endloop && 462 !pkt->insn[i].part1 && 463 !GET_ATTRIB(pkt->insn[i].opcode, A_IT_NOP)) { 464 num_real_insns++; 465 } 466 } 467 468 ctx->num_packets++; 469 ctx->num_insns += num_real_insns; 470 } 471 472 static void gen_commit_packet(DisasContext *ctx, Packet *pkt) 473 { 474 gen_reg_writes(ctx); 475 gen_pred_writes(ctx, pkt); 476 process_store_log(ctx, pkt); 477 process_dczeroa(ctx, pkt); 478 update_exec_counters(ctx, pkt); 479 if (HEX_DEBUG) { 480 TCGv has_st0 = 481 tcg_const_tl(pkt->pkt_has_store_s0 && !pkt->pkt_has_dczeroa); 482 TCGv has_st1 = 483 tcg_const_tl(pkt->pkt_has_store_s1 && !pkt->pkt_has_dczeroa); 484 485 /* Handy place to set a breakpoint at the end of execution */ 486 gen_helper_debug_commit_end(cpu_env, has_st0, has_st1); 487 488 tcg_temp_free(has_st0); 489 tcg_temp_free(has_st1); 490 } 491 492 if (pkt->pkt_has_cof) { 493 gen_end_tb(ctx); 494 } 495 } 496 497 static void decode_and_translate_packet(CPUHexagonState *env, DisasContext *ctx) 498 { 499 uint32_t words[PACKET_WORDS_MAX]; 500 int nwords; 501 Packet pkt; 502 int i; 503 504 nwords = read_packet_words(env, ctx, words); 505 if (!nwords) { 506 gen_exception_end_tb(ctx, HEX_EXCP_INVALID_PACKET); 507 return; 508 } 509 510 if (decode_packet(nwords, words, &pkt, false) > 0) { 511 HEX_DEBUG_PRINT_PKT(&pkt); 512 gen_start_packet(ctx, &pkt); 513 for (i = 0; i < pkt.num_insns; i++) { 514 gen_insn(env, ctx, &pkt.insn[i], &pkt); 515 } 516 gen_commit_packet(ctx, &pkt); 517 ctx->base.pc_next += pkt.encod_pkt_size_in_bytes; 518 } else { 519 gen_exception_end_tb(ctx, HEX_EXCP_INVALID_PACKET); 520 } 521 } 522 523 static void hexagon_tr_init_disas_context(DisasContextBase *dcbase, 524 CPUState *cs) 525 { 526 DisasContext *ctx = container_of(dcbase, DisasContext, base); 527 528 ctx->mem_idx = MMU_USER_IDX; 529 ctx->num_packets = 0; 530 ctx->num_insns = 0; 531 } 532 533 static void hexagon_tr_tb_start(DisasContextBase *db, CPUState *cpu) 534 { 535 } 536 537 static void hexagon_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) 538 { 539 DisasContext *ctx = container_of(dcbase, DisasContext, base); 540 541 tcg_gen_insn_start(ctx->base.pc_next); 542 } 543 544 static bool pkt_crosses_page(CPUHexagonState *env, DisasContext *ctx) 545 { 546 target_ulong page_start = ctx->base.pc_first & TARGET_PAGE_MASK; 547 bool found_end = false; 548 int nwords; 549 550 for (nwords = 0; !found_end && nwords < PACKET_WORDS_MAX; nwords++) { 551 uint32_t word = cpu_ldl_code(env, 552 ctx->base.pc_next + nwords * sizeof(uint32_t)); 553 found_end = is_packet_end(word); 554 } 555 uint32_t next_ptr = ctx->base.pc_next + nwords * sizeof(uint32_t); 556 return found_end && next_ptr - page_start >= TARGET_PAGE_SIZE; 557 } 558 559 static void hexagon_tr_translate_packet(DisasContextBase *dcbase, CPUState *cpu) 560 { 561 DisasContext *ctx = container_of(dcbase, DisasContext, base); 562 CPUHexagonState *env = cpu->env_ptr; 563 564 decode_and_translate_packet(env, ctx); 565 566 if (ctx->base.is_jmp == DISAS_NEXT) { 567 target_ulong page_start = ctx->base.pc_first & TARGET_PAGE_MASK; 568 target_ulong bytes_max = PACKET_WORDS_MAX * sizeof(target_ulong); 569 570 if (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE || 571 (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE - bytes_max && 572 pkt_crosses_page(env, ctx))) { 573 ctx->base.is_jmp = DISAS_TOO_MANY; 574 } 575 576 /* 577 * The CPU log is used to compare against LLDB single stepping, 578 * so end the TLB after every packet. 579 */ 580 HexagonCPU *hex_cpu = env_archcpu(env); 581 if (hex_cpu->lldb_compat && qemu_loglevel_mask(CPU_LOG_TB_CPU)) { 582 ctx->base.is_jmp = DISAS_TOO_MANY; 583 } 584 } 585 } 586 587 static void hexagon_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) 588 { 589 DisasContext *ctx = container_of(dcbase, DisasContext, base); 590 591 switch (ctx->base.is_jmp) { 592 case DISAS_TOO_MANY: 593 gen_exec_counters(ctx); 594 tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], ctx->base.pc_next); 595 if (ctx->base.singlestep_enabled) { 596 gen_exception_raw(EXCP_DEBUG); 597 } else { 598 tcg_gen_exit_tb(NULL, 0); 599 } 600 break; 601 case DISAS_NORETURN: 602 break; 603 default: 604 g_assert_not_reached(); 605 } 606 } 607 608 static void hexagon_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu) 609 { 610 qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); 611 log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size); 612 } 613 614 615 static const TranslatorOps hexagon_tr_ops = { 616 .init_disas_context = hexagon_tr_init_disas_context, 617 .tb_start = hexagon_tr_tb_start, 618 .insn_start = hexagon_tr_insn_start, 619 .translate_insn = hexagon_tr_translate_packet, 620 .tb_stop = hexagon_tr_tb_stop, 621 .disas_log = hexagon_tr_disas_log, 622 }; 623 624 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) 625 { 626 DisasContext ctx; 627 628 translator_loop(&hexagon_tr_ops, &ctx.base, cs, tb, max_insns); 629 } 630 631 #define NAME_LEN 64 632 static char new_value_names[TOTAL_PER_THREAD_REGS][NAME_LEN]; 633 static char reg_written_names[TOTAL_PER_THREAD_REGS][NAME_LEN]; 634 static char new_pred_value_names[NUM_PREGS][NAME_LEN]; 635 static char store_addr_names[STORES_MAX][NAME_LEN]; 636 static char store_width_names[STORES_MAX][NAME_LEN]; 637 static char store_val32_names[STORES_MAX][NAME_LEN]; 638 static char store_val64_names[STORES_MAX][NAME_LEN]; 639 640 void hexagon_translate_init(void) 641 { 642 int i; 643 644 opcode_init(); 645 646 if (HEX_DEBUG) { 647 if (!qemu_logfile) { 648 qemu_set_log(qemu_loglevel); 649 } 650 } 651 652 for (i = 0; i < TOTAL_PER_THREAD_REGS; i++) { 653 hex_gpr[i] = tcg_global_mem_new(cpu_env, 654 offsetof(CPUHexagonState, gpr[i]), 655 hexagon_regnames[i]); 656 657 snprintf(new_value_names[i], NAME_LEN, "new_%s", hexagon_regnames[i]); 658 hex_new_value[i] = tcg_global_mem_new(cpu_env, 659 offsetof(CPUHexagonState, new_value[i]), 660 new_value_names[i]); 661 662 if (HEX_DEBUG) { 663 snprintf(reg_written_names[i], NAME_LEN, "reg_written_%s", 664 hexagon_regnames[i]); 665 hex_reg_written[i] = tcg_global_mem_new(cpu_env, 666 offsetof(CPUHexagonState, reg_written[i]), 667 reg_written_names[i]); 668 } 669 } 670 for (i = 0; i < NUM_PREGS; i++) { 671 hex_pred[i] = tcg_global_mem_new(cpu_env, 672 offsetof(CPUHexagonState, pred[i]), 673 hexagon_prednames[i]); 674 675 snprintf(new_pred_value_names[i], NAME_LEN, "new_pred_%s", 676 hexagon_prednames[i]); 677 hex_new_pred_value[i] = tcg_global_mem_new(cpu_env, 678 offsetof(CPUHexagonState, new_pred_value[i]), 679 new_pred_value_names[i]); 680 } 681 hex_pred_written = tcg_global_mem_new(cpu_env, 682 offsetof(CPUHexagonState, pred_written), "pred_written"); 683 hex_next_PC = tcg_global_mem_new(cpu_env, 684 offsetof(CPUHexagonState, next_PC), "next_PC"); 685 hex_this_PC = tcg_global_mem_new(cpu_env, 686 offsetof(CPUHexagonState, this_PC), "this_PC"); 687 hex_slot_cancelled = tcg_global_mem_new(cpu_env, 688 offsetof(CPUHexagonState, slot_cancelled), "slot_cancelled"); 689 hex_branch_taken = tcg_global_mem_new(cpu_env, 690 offsetof(CPUHexagonState, branch_taken), "branch_taken"); 691 hex_pkt_has_store_s1 = tcg_global_mem_new(cpu_env, 692 offsetof(CPUHexagonState, pkt_has_store_s1), "pkt_has_store_s1"); 693 hex_dczero_addr = tcg_global_mem_new(cpu_env, 694 offsetof(CPUHexagonState, dczero_addr), "dczero_addr"); 695 hex_llsc_addr = tcg_global_mem_new(cpu_env, 696 offsetof(CPUHexagonState, llsc_addr), "llsc_addr"); 697 hex_llsc_val = tcg_global_mem_new(cpu_env, 698 offsetof(CPUHexagonState, llsc_val), "llsc_val"); 699 hex_llsc_val_i64 = tcg_global_mem_new_i64(cpu_env, 700 offsetof(CPUHexagonState, llsc_val_i64), "llsc_val_i64"); 701 for (i = 0; i < STORES_MAX; i++) { 702 snprintf(store_addr_names[i], NAME_LEN, "store_addr_%d", i); 703 hex_store_addr[i] = tcg_global_mem_new(cpu_env, 704 offsetof(CPUHexagonState, mem_log_stores[i].va), 705 store_addr_names[i]); 706 707 snprintf(store_width_names[i], NAME_LEN, "store_width_%d", i); 708 hex_store_width[i] = tcg_global_mem_new(cpu_env, 709 offsetof(CPUHexagonState, mem_log_stores[i].width), 710 store_width_names[i]); 711 712 snprintf(store_val32_names[i], NAME_LEN, "store_val32_%d", i); 713 hex_store_val32[i] = tcg_global_mem_new(cpu_env, 714 offsetof(CPUHexagonState, mem_log_stores[i].data32), 715 store_val32_names[i]); 716 717 snprintf(store_val64_names[i], NAME_LEN, "store_val64_%d", i); 718 hex_store_val64[i] = tcg_global_mem_new_i64(cpu_env, 719 offsetof(CPUHexagonState, mem_log_stores[i].data64), 720 store_val64_names[i]); 721 } 722 } 723