1 /* 2 * Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #define QEMU_GENERATE 19 #include "qemu/osdep.h" 20 #include "cpu.h" 21 #include "tcg/tcg-op.h" 22 #include "tcg/tcg-op-gvec.h" 23 #include "exec/helper-gen.h" 24 #include "exec/helper-proto.h" 25 #include "exec/translation-block.h" 26 #include "exec/cpu_ldst.h" 27 #include "exec/log.h" 28 #include "internal.h" 29 #include "attribs.h" 30 #include "insn.h" 31 #include "decode.h" 32 #include "translate.h" 33 #include "genptr.h" 34 #include "printinsn.h" 35 36 #define HELPER_H "helper.h" 37 #include "exec/helper-info.c.inc" 38 #undef HELPER_H 39 40 #include "analyze_funcs_generated.c.inc" 41 42 typedef void (*AnalyzeInsn)(DisasContext *ctx); 43 static const AnalyzeInsn opcode_analyze[XX_LAST_OPCODE] = { 44 #define OPCODE(X) [X] = analyze_##X 45 #include "opcodes_def_generated.h.inc" 46 #undef OPCODE 47 }; 48 49 TCGv hex_gpr[TOTAL_PER_THREAD_REGS]; 50 TCGv hex_pred[NUM_PREGS]; 51 TCGv hex_slot_cancelled; 52 TCGv hex_new_value_usr; 53 TCGv hex_reg_written[TOTAL_PER_THREAD_REGS]; 54 TCGv hex_store_addr[STORES_MAX]; 55 TCGv hex_store_width[STORES_MAX]; 56 TCGv hex_store_val32[STORES_MAX]; 57 TCGv_i64 hex_store_val64[STORES_MAX]; 58 TCGv hex_llsc_addr; 59 TCGv hex_llsc_val; 60 TCGv_i64 hex_llsc_val_i64; 61 TCGv hex_vstore_addr[VSTORES_MAX]; 62 TCGv hex_vstore_size[VSTORES_MAX]; 63 TCGv hex_vstore_pending[VSTORES_MAX]; 64 65 static const char * const hexagon_prednames[] = { 66 "p0", "p1", "p2", "p3" 67 }; 68 69 intptr_t ctx_future_vreg_off(DisasContext *ctx, int regnum, 70 int num, bool alloc_ok) 71 { 72 intptr_t offset; 73 74 if (!ctx->need_commit) { 75 return offsetof(CPUHexagonState, VRegs[regnum]); 76 } 77 78 /* See if it is already allocated */ 79 for (int i = 0; i < ctx->future_vregs_idx; i++) { 80 if (ctx->future_vregs_num[i] == regnum) { 81 return offsetof(CPUHexagonState, future_VRegs[i]); 82 } 83 } 84 85 g_assert(alloc_ok); 86 offset = offsetof(CPUHexagonState, future_VRegs[ctx->future_vregs_idx]); 87 for (int i = 0; i < num; i++) { 88 ctx->future_vregs_num[ctx->future_vregs_idx + i] = regnum++; 89 } 90 ctx->future_vregs_idx += num; 91 g_assert(ctx->future_vregs_idx <= VECTOR_TEMPS_MAX); 92 return offset; 93 } 94 95 intptr_t ctx_tmp_vreg_off(DisasContext *ctx, int regnum, 96 int num, bool alloc_ok) 97 { 98 intptr_t offset; 99 100 /* See if it is already allocated */ 101 for (int i = 0; i < ctx->tmp_vregs_idx; i++) { 102 if (ctx->tmp_vregs_num[i] == regnum) { 103 return offsetof(CPUHexagonState, tmp_VRegs[i]); 104 } 105 } 106 107 g_assert(alloc_ok); 108 offset = offsetof(CPUHexagonState, tmp_VRegs[ctx->tmp_vregs_idx]); 109 for (int i = 0; i < num; i++) { 110 ctx->tmp_vregs_num[ctx->tmp_vregs_idx + i] = regnum++; 111 } 112 ctx->tmp_vregs_idx += num; 113 g_assert(ctx->tmp_vregs_idx <= VECTOR_TEMPS_MAX); 114 return offset; 115 } 116 117 static void gen_exception_raw(int excp) 118 { 119 gen_helper_raise_exception(tcg_env, tcg_constant_i32(excp)); 120 } 121 122 static void gen_exec_counters(DisasContext *ctx) 123 { 124 tcg_gen_addi_tl(hex_gpr[HEX_REG_QEMU_PKT_CNT], 125 hex_gpr[HEX_REG_QEMU_PKT_CNT], ctx->num_packets); 126 tcg_gen_addi_tl(hex_gpr[HEX_REG_QEMU_INSN_CNT], 127 hex_gpr[HEX_REG_QEMU_INSN_CNT], ctx->num_insns); 128 tcg_gen_addi_tl(hex_gpr[HEX_REG_QEMU_HVX_CNT], 129 hex_gpr[HEX_REG_QEMU_HVX_CNT], ctx->num_hvx_insns); 130 } 131 132 static bool use_goto_tb(DisasContext *ctx, target_ulong dest) 133 { 134 return translator_use_goto_tb(&ctx->base, dest); 135 } 136 137 static void gen_goto_tb(DisasContext *ctx, int idx, target_ulong dest, bool 138 move_to_pc) 139 { 140 if (use_goto_tb(ctx, dest)) { 141 tcg_gen_goto_tb(idx); 142 if (move_to_pc) { 143 tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], dest); 144 } 145 tcg_gen_exit_tb(ctx->base.tb, idx); 146 } else { 147 if (move_to_pc) { 148 tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], dest); 149 } 150 tcg_gen_lookup_and_goto_ptr(); 151 } 152 } 153 154 static void gen_end_tb(DisasContext *ctx) 155 { 156 Packet *pkt = ctx->pkt; 157 158 gen_exec_counters(ctx); 159 160 if (ctx->branch_cond != TCG_COND_NEVER) { 161 if (ctx->branch_cond != TCG_COND_ALWAYS) { 162 TCGLabel *skip = gen_new_label(); 163 tcg_gen_brcondi_tl(ctx->branch_cond, ctx->branch_taken, 0, skip); 164 gen_goto_tb(ctx, 0, ctx->branch_dest, true); 165 gen_set_label(skip); 166 gen_goto_tb(ctx, 1, ctx->next_PC, false); 167 } else { 168 gen_goto_tb(ctx, 0, ctx->branch_dest, true); 169 } 170 } else if (ctx->is_tight_loop && 171 pkt->insn[pkt->num_insns - 1].opcode == J2_endloop0) { 172 /* 173 * When we're in a tight loop, we defer the endloop0 processing 174 * to take advantage of direct block chaining 175 */ 176 TCGLabel *skip = gen_new_label(); 177 tcg_gen_brcondi_tl(TCG_COND_LEU, hex_gpr[HEX_REG_LC0], 1, skip); 178 tcg_gen_subi_tl(hex_gpr[HEX_REG_LC0], hex_gpr[HEX_REG_LC0], 1); 179 gen_goto_tb(ctx, 0, ctx->base.tb->pc, true); 180 gen_set_label(skip); 181 gen_goto_tb(ctx, 1, ctx->next_PC, false); 182 } else { 183 tcg_gen_lookup_and_goto_ptr(); 184 } 185 186 ctx->base.is_jmp = DISAS_NORETURN; 187 } 188 189 static void gen_exception_end_tb(DisasContext *ctx, int excp) 190 { 191 gen_exec_counters(ctx); 192 tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], ctx->next_PC); 193 gen_exception_raw(excp); 194 ctx->base.is_jmp = DISAS_NORETURN; 195 196 } 197 198 #define PACKET_BUFFER_LEN 1028 199 static void print_pkt(Packet *pkt) 200 { 201 GString *buf = g_string_sized_new(PACKET_BUFFER_LEN); 202 snprint_a_pkt_debug(buf, pkt); 203 HEX_DEBUG_LOG("%s", buf->str); 204 g_string_free(buf, true); 205 } 206 #define HEX_DEBUG_PRINT_PKT(pkt) \ 207 do { \ 208 if (HEX_DEBUG) { \ 209 print_pkt(pkt); \ 210 } \ 211 } while (0) 212 213 static int read_packet_words(CPUHexagonState *env, DisasContext *ctx, 214 uint32_t words[]) 215 { 216 bool found_end = false; 217 int nwords, max_words; 218 219 memset(words, 0, PACKET_WORDS_MAX * sizeof(uint32_t)); 220 for (nwords = 0; !found_end && nwords < PACKET_WORDS_MAX; nwords++) { 221 words[nwords] = 222 translator_ldl(env, &ctx->base, 223 ctx->base.pc_next + nwords * sizeof(uint32_t)); 224 found_end = is_packet_end(words[nwords]); 225 } 226 if (!found_end) { 227 /* Read too many words without finding the end */ 228 return 0; 229 } 230 231 /* Check for page boundary crossing */ 232 max_words = -(ctx->base.pc_next | TARGET_PAGE_MASK) / sizeof(uint32_t); 233 if (nwords > max_words) { 234 /* We can only cross a page boundary at the beginning of a TB */ 235 g_assert(ctx->base.num_insns == 1); 236 } 237 238 HEX_DEBUG_LOG("decode_packet: pc = 0x%" VADDR_PRIx "\n", 239 ctx->base.pc_next); 240 HEX_DEBUG_LOG(" words = { "); 241 for (int i = 0; i < nwords; i++) { 242 HEX_DEBUG_LOG("0x%x, ", words[i]); 243 } 244 HEX_DEBUG_LOG("}\n"); 245 246 return nwords; 247 } 248 249 static bool check_for_attrib(Packet *pkt, int attrib) 250 { 251 for (int i = 0; i < pkt->num_insns; i++) { 252 if (GET_ATTRIB(pkt->insn[i].opcode, attrib)) { 253 return true; 254 } 255 } 256 return false; 257 } 258 259 static bool need_slot_cancelled(Packet *pkt) 260 { 261 /* We only need slot_cancelled for conditional store instructions */ 262 for (int i = 0; i < pkt->num_insns; i++) { 263 uint16_t opcode = pkt->insn[i].opcode; 264 if (GET_ATTRIB(opcode, A_CONDEXEC) && 265 GET_ATTRIB(opcode, A_SCALAR_STORE)) { 266 return true; 267 } 268 } 269 return false; 270 } 271 272 static bool need_next_PC(DisasContext *ctx) 273 { 274 Packet *pkt = ctx->pkt; 275 276 /* Check for conditional control flow or HW loop end */ 277 for (int i = 0; i < pkt->num_insns; i++) { 278 uint16_t opcode = pkt->insn[i].opcode; 279 if (GET_ATTRIB(opcode, A_CONDEXEC) && GET_ATTRIB(opcode, A_COF)) { 280 return true; 281 } 282 if (GET_ATTRIB(opcode, A_HWLOOP0_END) || 283 GET_ATTRIB(opcode, A_HWLOOP1_END)) { 284 return true; 285 } 286 } 287 return false; 288 } 289 290 /* 291 * The opcode_analyze functions mark most of the writes in a packet 292 * However, there are some implicit writes marked as attributes 293 * of the applicable instructions. 294 */ 295 static void mark_implicit_reg_write(DisasContext *ctx, int attrib, int rnum) 296 { 297 uint16_t opcode = ctx->insn->opcode; 298 if (GET_ATTRIB(opcode, attrib)) { 299 /* 300 * USR is used to set overflow and FP exceptions, 301 * so treat it as conditional 302 */ 303 bool is_predicated = GET_ATTRIB(opcode, A_CONDEXEC) || 304 rnum == HEX_REG_USR; 305 306 /* LC0/LC1 is conditionally written by endloop instructions */ 307 if ((rnum == HEX_REG_LC0 || rnum == HEX_REG_LC1) && 308 (opcode == J2_endloop0 || 309 opcode == J2_endloop1 || 310 opcode == J2_endloop01)) { 311 is_predicated = true; 312 } 313 314 ctx_log_reg_write(ctx, rnum, is_predicated); 315 } 316 } 317 318 static void mark_implicit_reg_writes(DisasContext *ctx) 319 { 320 mark_implicit_reg_write(ctx, A_IMPLICIT_WRITES_FP, HEX_REG_FP); 321 mark_implicit_reg_write(ctx, A_IMPLICIT_WRITES_SP, HEX_REG_SP); 322 mark_implicit_reg_write(ctx, A_IMPLICIT_WRITES_LR, HEX_REG_LR); 323 mark_implicit_reg_write(ctx, A_IMPLICIT_WRITES_LC0, HEX_REG_LC0); 324 mark_implicit_reg_write(ctx, A_IMPLICIT_WRITES_SA0, HEX_REG_SA0); 325 mark_implicit_reg_write(ctx, A_IMPLICIT_WRITES_LC1, HEX_REG_LC1); 326 mark_implicit_reg_write(ctx, A_IMPLICIT_WRITES_SA1, HEX_REG_SA1); 327 mark_implicit_reg_write(ctx, A_IMPLICIT_WRITES_USR, HEX_REG_USR); 328 mark_implicit_reg_write(ctx, A_FPOP, HEX_REG_USR); 329 } 330 331 static void mark_implicit_pred_write(DisasContext *ctx, int attrib, int pnum) 332 { 333 if (GET_ATTRIB(ctx->insn->opcode, attrib)) { 334 ctx_log_pred_write(ctx, pnum); 335 } 336 } 337 338 static void mark_implicit_pred_writes(DisasContext *ctx) 339 { 340 mark_implicit_pred_write(ctx, A_IMPLICIT_WRITES_P0, 0); 341 mark_implicit_pred_write(ctx, A_IMPLICIT_WRITES_P1, 1); 342 mark_implicit_pred_write(ctx, A_IMPLICIT_WRITES_P2, 2); 343 mark_implicit_pred_write(ctx, A_IMPLICIT_WRITES_P3, 3); 344 } 345 346 static bool pkt_raises_exception(Packet *pkt) 347 { 348 if (check_for_attrib(pkt, A_LOAD) || 349 check_for_attrib(pkt, A_STORE)) { 350 return true; 351 } 352 return false; 353 } 354 355 static bool need_commit(DisasContext *ctx) 356 { 357 Packet *pkt = ctx->pkt; 358 359 /* 360 * If the short-circuit property is set to false, we'll always do the commit 361 */ 362 if (!ctx->short_circuit) { 363 return true; 364 } 365 366 if (pkt_raises_exception(pkt)) { 367 return true; 368 } 369 370 /* Registers with immutability flags require new_value */ 371 for (int i = 0; i < ctx->reg_log_idx; i++) { 372 int rnum = ctx->reg_log[i]; 373 if (reg_immut_masks[rnum]) { 374 return true; 375 } 376 } 377 378 /* Floating point instructions are hard-coded to use new_value */ 379 if (check_for_attrib(pkt, A_FPOP)) { 380 return true; 381 } 382 383 if (pkt->num_insns == 1) { 384 if (pkt->pkt_has_hvx) { 385 /* 386 * The HVX instructions with generated helpers use 387 * pass-by-reference, so they need the read/write overlap 388 * check below. 389 * The HVX instructions with overrides are OK. 390 */ 391 if (!ctx->has_hvx_helper) { 392 return false; 393 } 394 } else { 395 return false; 396 } 397 } 398 399 /* Check for overlap between register reads and writes */ 400 for (int i = 0; i < ctx->reg_log_idx; i++) { 401 int rnum = ctx->reg_log[i]; 402 if (test_bit(rnum, ctx->regs_read)) { 403 return true; 404 } 405 } 406 407 /* Check for overlap between predicate reads and writes */ 408 for (int i = 0; i < ctx->preg_log_idx; i++) { 409 int pnum = ctx->preg_log[i]; 410 if (test_bit(pnum, ctx->pregs_read)) { 411 return true; 412 } 413 } 414 415 /* Check for overlap between HVX reads and writes */ 416 for (int i = 0; i < ctx->vreg_log_idx; i++) { 417 int vnum = ctx->vreg_log[i]; 418 if (test_bit(vnum, ctx->vregs_read)) { 419 return true; 420 } 421 } 422 if (!bitmap_empty(ctx->vregs_updated_tmp, NUM_VREGS)) { 423 int i = find_first_bit(ctx->vregs_updated_tmp, NUM_VREGS); 424 while (i < NUM_VREGS) { 425 if (test_bit(i, ctx->vregs_read)) { 426 return true; 427 } 428 i = find_next_bit(ctx->vregs_updated_tmp, NUM_VREGS, i + 1); 429 } 430 } 431 if (!bitmap_empty(ctx->vregs_select, NUM_VREGS)) { 432 int i = find_first_bit(ctx->vregs_select, NUM_VREGS); 433 while (i < NUM_VREGS) { 434 if (test_bit(i, ctx->vregs_read)) { 435 return true; 436 } 437 i = find_next_bit(ctx->vregs_select, NUM_VREGS, i + 1); 438 } 439 } 440 441 /* Check for overlap between HVX predicate reads and writes */ 442 for (int i = 0; i < ctx->qreg_log_idx; i++) { 443 int qnum = ctx->qreg_log[i]; 444 if (test_bit(qnum, ctx->qregs_read)) { 445 return true; 446 } 447 } 448 449 return false; 450 } 451 452 static void mark_implicit_pred_read(DisasContext *ctx, int attrib, int pnum) 453 { 454 if (GET_ATTRIB(ctx->insn->opcode, attrib)) { 455 ctx_log_pred_read(ctx, pnum); 456 } 457 } 458 459 static void mark_implicit_pred_reads(DisasContext *ctx) 460 { 461 mark_implicit_pred_read(ctx, A_IMPLICIT_READS_P0, 0); 462 mark_implicit_pred_read(ctx, A_IMPLICIT_READS_P1, 1); 463 mark_implicit_pred_read(ctx, A_IMPLICIT_READS_P3, 2); 464 mark_implicit_pred_read(ctx, A_IMPLICIT_READS_P3, 3); 465 } 466 467 static void analyze_packet(DisasContext *ctx) 468 { 469 Packet *pkt = ctx->pkt; 470 ctx->has_hvx_helper = false; 471 for (int i = 0; i < pkt->num_insns; i++) { 472 Insn *insn = &pkt->insn[i]; 473 ctx->insn = insn; 474 if (opcode_analyze[insn->opcode]) { 475 opcode_analyze[insn->opcode](ctx); 476 } 477 mark_implicit_reg_writes(ctx); 478 mark_implicit_pred_writes(ctx); 479 mark_implicit_pred_reads(ctx); 480 } 481 482 ctx->need_commit = need_commit(ctx); 483 } 484 485 static void gen_start_packet(DisasContext *ctx) 486 { 487 Packet *pkt = ctx->pkt; 488 target_ulong next_PC = ctx->base.pc_next + pkt->encod_pkt_size_in_bytes; 489 int i; 490 491 /* Clear out the disassembly context */ 492 ctx->next_PC = next_PC; 493 ctx->reg_log_idx = 0; 494 bitmap_zero(ctx->regs_written, TOTAL_PER_THREAD_REGS); 495 bitmap_zero(ctx->regs_read, TOTAL_PER_THREAD_REGS); 496 bitmap_zero(ctx->predicated_regs, TOTAL_PER_THREAD_REGS); 497 ctx->preg_log_idx = 0; 498 bitmap_zero(ctx->pregs_written, NUM_PREGS); 499 bitmap_zero(ctx->pregs_read, NUM_PREGS); 500 ctx->future_vregs_idx = 0; 501 ctx->tmp_vregs_idx = 0; 502 ctx->vreg_log_idx = 0; 503 bitmap_zero(ctx->vregs_updated_tmp, NUM_VREGS); 504 bitmap_zero(ctx->vregs_updated, NUM_VREGS); 505 bitmap_zero(ctx->vregs_select, NUM_VREGS); 506 bitmap_zero(ctx->predicated_future_vregs, NUM_VREGS); 507 bitmap_zero(ctx->predicated_tmp_vregs, NUM_VREGS); 508 bitmap_zero(ctx->vregs_read, NUM_VREGS); 509 bitmap_zero(ctx->qregs_read, NUM_QREGS); 510 ctx->qreg_log_idx = 0; 511 for (i = 0; i < STORES_MAX; i++) { 512 ctx->store_width[i] = 0; 513 } 514 ctx->s1_store_processed = false; 515 ctx->pre_commit = true; 516 for (i = 0; i < TOTAL_PER_THREAD_REGS; i++) { 517 ctx->new_value[i] = NULL; 518 } 519 for (i = 0; i < NUM_PREGS; i++) { 520 ctx->new_pred_value[i] = NULL; 521 } 522 523 analyze_packet(ctx); 524 525 /* 526 * pregs_written is used both in the analyze phase as well as the code 527 * gen phase, so clear it again. 528 */ 529 bitmap_zero(ctx->pregs_written, NUM_PREGS); 530 531 if (HEX_DEBUG) { 532 /* Handy place to set a breakpoint before the packet executes */ 533 gen_helper_debug_start_packet(tcg_env); 534 } 535 536 /* Initialize the runtime state for packet semantics */ 537 if (need_slot_cancelled(pkt)) { 538 tcg_gen_movi_tl(hex_slot_cancelled, 0); 539 } 540 ctx->branch_taken = NULL; 541 if (pkt->pkt_has_cof) { 542 ctx->branch_taken = tcg_temp_new(); 543 if (pkt->pkt_has_multi_cof) { 544 tcg_gen_movi_tl(ctx->branch_taken, 0); 545 } 546 if (need_next_PC(ctx)) { 547 tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], next_PC); 548 } 549 } 550 if (HEX_DEBUG) { 551 ctx->pred_written = tcg_temp_new(); 552 tcg_gen_movi_tl(ctx->pred_written, 0); 553 } 554 555 /* Preload the predicated registers into get_result_gpr(ctx, i) */ 556 if (ctx->need_commit && 557 !bitmap_empty(ctx->predicated_regs, TOTAL_PER_THREAD_REGS)) { 558 i = find_first_bit(ctx->predicated_regs, TOTAL_PER_THREAD_REGS); 559 while (i < TOTAL_PER_THREAD_REGS) { 560 tcg_gen_mov_tl(get_result_gpr(ctx, i), hex_gpr[i]); 561 i = find_next_bit(ctx->predicated_regs, TOTAL_PER_THREAD_REGS, 562 i + 1); 563 } 564 } 565 566 /* 567 * Preload the predicated pred registers into ctx->new_pred_value[pred_num] 568 * Only endloop instructions conditionally write to pred registers 569 */ 570 if (ctx->need_commit && pkt->pkt_has_endloop) { 571 for (i = 0; i < ctx->preg_log_idx; i++) { 572 int pred_num = ctx->preg_log[i]; 573 ctx->new_pred_value[pred_num] = tcg_temp_new(); 574 tcg_gen_mov_tl(ctx->new_pred_value[pred_num], hex_pred[pred_num]); 575 } 576 } 577 578 /* Preload the predicated HVX registers into future_VRegs and tmp_VRegs */ 579 if (!bitmap_empty(ctx->predicated_future_vregs, NUM_VREGS)) { 580 i = find_first_bit(ctx->predicated_future_vregs, NUM_VREGS); 581 while (i < NUM_VREGS) { 582 const intptr_t VdV_off = 583 ctx_future_vreg_off(ctx, i, 1, true); 584 intptr_t src_off = offsetof(CPUHexagonState, VRegs[i]); 585 tcg_gen_gvec_mov(MO_64, VdV_off, 586 src_off, 587 sizeof(MMVector), 588 sizeof(MMVector)); 589 i = find_next_bit(ctx->predicated_future_vregs, NUM_VREGS, i + 1); 590 } 591 } 592 if (!bitmap_empty(ctx->predicated_tmp_vregs, NUM_VREGS)) { 593 i = find_first_bit(ctx->predicated_tmp_vregs, NUM_VREGS); 594 while (i < NUM_VREGS) { 595 const intptr_t VdV_off = 596 ctx_tmp_vreg_off(ctx, i, 1, true); 597 intptr_t src_off = offsetof(CPUHexagonState, VRegs[i]); 598 tcg_gen_gvec_mov(MO_64, VdV_off, 599 src_off, 600 sizeof(MMVector), 601 sizeof(MMVector)); 602 i = find_next_bit(ctx->predicated_tmp_vregs, NUM_VREGS, i + 1); 603 } 604 } 605 } 606 607 bool is_gather_store_insn(DisasContext *ctx) 608 { 609 Packet *pkt = ctx->pkt; 610 Insn *insn = ctx->insn; 611 if (GET_ATTRIB(insn->opcode, A_CVI_NEW) && 612 insn->new_value_producer_slot == 1) { 613 /* Look for gather instruction */ 614 for (int i = 0; i < pkt->num_insns; i++) { 615 Insn *in = &pkt->insn[i]; 616 if (GET_ATTRIB(in->opcode, A_CVI_GATHER) && in->slot == 1) { 617 return true; 618 } 619 } 620 } 621 return false; 622 } 623 624 static void mark_store_width(DisasContext *ctx) 625 { 626 uint16_t opcode = ctx->insn->opcode; 627 uint32_t slot = ctx->insn->slot; 628 uint8_t width = 0; 629 630 if (GET_ATTRIB(opcode, A_SCALAR_STORE)) { 631 if (GET_ATTRIB(opcode, A_MEMSIZE_0B)) { 632 return; 633 } 634 if (GET_ATTRIB(opcode, A_MEMSIZE_1B)) { 635 width |= 1; 636 } 637 if (GET_ATTRIB(opcode, A_MEMSIZE_2B)) { 638 width |= 2; 639 } 640 if (GET_ATTRIB(opcode, A_MEMSIZE_4B)) { 641 width |= 4; 642 } 643 if (GET_ATTRIB(opcode, A_MEMSIZE_8B)) { 644 width |= 8; 645 } 646 tcg_debug_assert(is_power_of_2(width)); 647 ctx->store_width[slot] = width; 648 } 649 } 650 651 static void gen_insn(DisasContext *ctx) 652 { 653 if (ctx->insn->generate) { 654 ctx->insn->generate(ctx); 655 mark_store_width(ctx); 656 } else { 657 gen_exception_end_tb(ctx, HEX_EXCP_INVALID_OPCODE); 658 } 659 } 660 661 /* 662 * Helpers for generating the packet commit 663 */ 664 static void gen_reg_writes(DisasContext *ctx) 665 { 666 int i; 667 668 /* Early exit if not needed */ 669 if (!ctx->need_commit) { 670 return; 671 } 672 673 for (i = 0; i < ctx->reg_log_idx; i++) { 674 int reg_num = ctx->reg_log[i]; 675 676 tcg_gen_mov_tl(hex_gpr[reg_num], get_result_gpr(ctx, reg_num)); 677 678 /* 679 * ctx->is_tight_loop is set when SA0 points to the beginning of the TB. 680 * If we write to SA0, we have to turn off tight loop handling. 681 */ 682 if (reg_num == HEX_REG_SA0) { 683 ctx->is_tight_loop = false; 684 } 685 } 686 } 687 688 static void gen_pred_writes(DisasContext *ctx) 689 { 690 /* Early exit if not needed or the log is empty */ 691 if (!ctx->need_commit || !ctx->preg_log_idx) { 692 return; 693 } 694 695 for (int i = 0; i < ctx->preg_log_idx; i++) { 696 int pred_num = ctx->preg_log[i]; 697 tcg_gen_mov_tl(hex_pred[pred_num], ctx->new_pred_value[pred_num]); 698 } 699 } 700 701 static void gen_check_store_width(DisasContext *ctx, int slot_num) 702 { 703 if (HEX_DEBUG) { 704 TCGv slot = tcg_constant_tl(slot_num); 705 TCGv check = tcg_constant_tl(ctx->store_width[slot_num]); 706 gen_helper_debug_check_store_width(tcg_env, slot, check); 707 } 708 } 709 710 static bool slot_is_predicated(Packet *pkt, int slot_num) 711 { 712 for (int i = 0; i < pkt->num_insns; i++) { 713 if (pkt->insn[i].slot == slot_num) { 714 return GET_ATTRIB(pkt->insn[i].opcode, A_CONDEXEC); 715 } 716 } 717 /* If we get to here, we didn't find an instruction in the requested slot */ 718 g_assert_not_reached(); 719 } 720 721 void process_store(DisasContext *ctx, int slot_num) 722 { 723 bool is_predicated = slot_is_predicated(ctx->pkt, slot_num); 724 TCGLabel *label_end = NULL; 725 726 /* 727 * We may have already processed this store 728 * See CHECK_NOSHUF in macros.h 729 */ 730 if (slot_num == 1 && ctx->s1_store_processed) { 731 return; 732 } 733 ctx->s1_store_processed = true; 734 735 if (is_predicated) { 736 TCGv cancelled = tcg_temp_new(); 737 label_end = gen_new_label(); 738 739 /* Don't do anything if the slot was cancelled */ 740 tcg_gen_extract_tl(cancelled, hex_slot_cancelled, slot_num, 1); 741 tcg_gen_brcondi_tl(TCG_COND_NE, cancelled, 0, label_end); 742 } 743 { 744 TCGv address = tcg_temp_new(); 745 tcg_gen_mov_tl(address, hex_store_addr[slot_num]); 746 747 /* 748 * If we know the width from the DisasContext, we can 749 * generate much cleaner code. 750 * Unfortunately, not all instructions execute the fSTORE 751 * macro during code generation. Anything that uses the 752 * generic helper will have this problem. Instructions 753 * that use fWRAP to generate proper TCG code will be OK. 754 */ 755 switch (ctx->store_width[slot_num]) { 756 case 1: 757 gen_check_store_width(ctx, slot_num); 758 tcg_gen_qemu_st_tl(hex_store_val32[slot_num], 759 hex_store_addr[slot_num], 760 ctx->mem_idx, MO_UB); 761 break; 762 case 2: 763 gen_check_store_width(ctx, slot_num); 764 tcg_gen_qemu_st_tl(hex_store_val32[slot_num], 765 hex_store_addr[slot_num], 766 ctx->mem_idx, MO_TEUW); 767 break; 768 case 4: 769 gen_check_store_width(ctx, slot_num); 770 tcg_gen_qemu_st_tl(hex_store_val32[slot_num], 771 hex_store_addr[slot_num], 772 ctx->mem_idx, MO_TEUL); 773 break; 774 case 8: 775 gen_check_store_width(ctx, slot_num); 776 tcg_gen_qemu_st_i64(hex_store_val64[slot_num], 777 hex_store_addr[slot_num], 778 ctx->mem_idx, MO_TEUQ); 779 break; 780 default: 781 { 782 /* 783 * If we get to here, we don't know the width at 784 * TCG generation time, we'll use a helper to 785 * avoid branching based on the width at runtime. 786 */ 787 TCGv slot = tcg_constant_tl(slot_num); 788 gen_helper_commit_store(tcg_env, slot); 789 } 790 } 791 } 792 if (is_predicated) { 793 gen_set_label(label_end); 794 } 795 } 796 797 static void process_store_log(DisasContext *ctx) 798 { 799 /* 800 * When a packet has two stores, the hardware processes 801 * slot 1 and then slot 0. This will be important when 802 * the memory accesses overlap. 803 */ 804 Packet *pkt = ctx->pkt; 805 if (pkt->pkt_has_store_s1) { 806 g_assert(!pkt->pkt_has_dczeroa); 807 process_store(ctx, 1); 808 } 809 if (pkt->pkt_has_store_s0) { 810 g_assert(!pkt->pkt_has_dczeroa); 811 process_store(ctx, 0); 812 } 813 } 814 815 /* Zero out a 32-bit cache line */ 816 static void process_dczeroa(DisasContext *ctx) 817 { 818 if (ctx->pkt->pkt_has_dczeroa) { 819 /* Store 32 bytes of zero starting at (addr & ~0x1f) */ 820 TCGv addr = tcg_temp_new(); 821 TCGv_i64 zero = tcg_constant_i64(0); 822 823 tcg_gen_andi_tl(addr, ctx->dczero_addr, ~0x1f); 824 tcg_gen_qemu_st_i64(zero, addr, ctx->mem_idx, MO_UQ); 825 tcg_gen_addi_tl(addr, addr, 8); 826 tcg_gen_qemu_st_i64(zero, addr, ctx->mem_idx, MO_UQ); 827 tcg_gen_addi_tl(addr, addr, 8); 828 tcg_gen_qemu_st_i64(zero, addr, ctx->mem_idx, MO_UQ); 829 tcg_gen_addi_tl(addr, addr, 8); 830 tcg_gen_qemu_st_i64(zero, addr, ctx->mem_idx, MO_UQ); 831 } 832 } 833 834 static bool pkt_has_hvx_store(Packet *pkt) 835 { 836 int i; 837 for (i = 0; i < pkt->num_insns; i++) { 838 int opcode = pkt->insn[i].opcode; 839 if (GET_ATTRIB(opcode, A_CVI) && GET_ATTRIB(opcode, A_STORE)) { 840 return true; 841 } 842 } 843 return false; 844 } 845 846 static void gen_commit_hvx(DisasContext *ctx) 847 { 848 int i; 849 850 /* Early exit if not needed */ 851 if (!ctx->need_commit) { 852 g_assert(!pkt_has_hvx_store(ctx->pkt)); 853 return; 854 } 855 856 /* 857 * for (i = 0; i < ctx->vreg_log_idx; i++) { 858 * int rnum = ctx->vreg_log[i]; 859 * env->VRegs[rnum] = env->future_VRegs[rnum]; 860 * } 861 */ 862 for (i = 0; i < ctx->vreg_log_idx; i++) { 863 int rnum = ctx->vreg_log[i]; 864 intptr_t dstoff = offsetof(CPUHexagonState, VRegs[rnum]); 865 intptr_t srcoff = ctx_future_vreg_off(ctx, rnum, 1, false); 866 size_t size = sizeof(MMVector); 867 868 tcg_gen_gvec_mov(MO_64, dstoff, srcoff, size, size); 869 } 870 871 /* 872 * for (i = 0; i < ctx->qreg_log_idx; i++) { 873 * int rnum = ctx->qreg_log[i]; 874 * env->QRegs[rnum] = env->future_QRegs[rnum]; 875 * } 876 */ 877 for (i = 0; i < ctx->qreg_log_idx; i++) { 878 int rnum = ctx->qreg_log[i]; 879 intptr_t dstoff = offsetof(CPUHexagonState, QRegs[rnum]); 880 intptr_t srcoff = offsetof(CPUHexagonState, future_QRegs[rnum]); 881 size_t size = sizeof(MMQReg); 882 883 tcg_gen_gvec_mov(MO_64, dstoff, srcoff, size, size); 884 } 885 886 if (pkt_has_hvx_store(ctx->pkt)) { 887 gen_helper_commit_hvx_stores(tcg_env); 888 } 889 } 890 891 static void update_exec_counters(DisasContext *ctx) 892 { 893 Packet *pkt = ctx->pkt; 894 int num_insns = pkt->num_insns; 895 int num_real_insns = 0; 896 int num_hvx_insns = 0; 897 898 for (int i = 0; i < num_insns; i++) { 899 if (!pkt->insn[i].is_endloop && 900 !pkt->insn[i].part1 && 901 !GET_ATTRIB(pkt->insn[i].opcode, A_IT_NOP)) { 902 num_real_insns++; 903 } 904 if (GET_ATTRIB(pkt->insn[i].opcode, A_CVI)) { 905 num_hvx_insns++; 906 } 907 } 908 909 ctx->num_packets++; 910 ctx->num_insns += num_real_insns; 911 ctx->num_hvx_insns += num_hvx_insns; 912 } 913 914 static void gen_commit_packet(DisasContext *ctx) 915 { 916 /* 917 * If there is more than one store in a packet, make sure they are all OK 918 * before proceeding with the rest of the packet commit. 919 * 920 * dczeroa has to be the only store operation in the packet, so we go 921 * ahead and process that first. 922 * 923 * When there is an HVX store, there can also be a scalar store in either 924 * slot 0 or slot1, so we create a mask for the helper to indicate what 925 * work to do. 926 * 927 * When there are two scalar stores, we probe the one in slot 0. 928 * 929 * Note that we don't call the probe helper for packets with only one 930 * store. Therefore, we call process_store_log before anything else 931 * involved in committing the packet. 932 */ 933 Packet *pkt = ctx->pkt; 934 bool has_store_s0 = pkt->pkt_has_store_s0; 935 bool has_store_s1 = (pkt->pkt_has_store_s1 && !ctx->s1_store_processed); 936 bool has_hvx_store = pkt_has_hvx_store(pkt); 937 if (pkt->pkt_has_dczeroa) { 938 /* 939 * The dczeroa will be the store in slot 0, check that we don't have 940 * a store in slot 1 or an HVX store. 941 */ 942 g_assert(!has_store_s1 && !has_hvx_store); 943 process_dczeroa(ctx); 944 } else if (has_hvx_store) { 945 if (!has_store_s0 && !has_store_s1) { 946 TCGv mem_idx = tcg_constant_tl(ctx->mem_idx); 947 gen_helper_probe_hvx_stores(tcg_env, mem_idx); 948 } else { 949 int mask = 0; 950 951 if (has_store_s0) { 952 mask = 953 FIELD_DP32(mask, PROBE_PKT_SCALAR_HVX_STORES, HAS_ST0, 1); 954 } 955 if (has_store_s1) { 956 mask = 957 FIELD_DP32(mask, PROBE_PKT_SCALAR_HVX_STORES, HAS_ST1, 1); 958 } 959 if (has_hvx_store) { 960 mask = 961 FIELD_DP32(mask, PROBE_PKT_SCALAR_HVX_STORES, 962 HAS_HVX_STORES, 1); 963 } 964 if (has_store_s0 && slot_is_predicated(pkt, 0)) { 965 mask = 966 FIELD_DP32(mask, PROBE_PKT_SCALAR_HVX_STORES, 967 S0_IS_PRED, 1); 968 } 969 if (has_store_s1 && slot_is_predicated(pkt, 1)) { 970 mask = 971 FIELD_DP32(mask, PROBE_PKT_SCALAR_HVX_STORES, 972 S1_IS_PRED, 1); 973 } 974 mask = FIELD_DP32(mask, PROBE_PKT_SCALAR_HVX_STORES, MMU_IDX, 975 ctx->mem_idx); 976 gen_helper_probe_pkt_scalar_hvx_stores(tcg_env, 977 tcg_constant_tl(mask)); 978 } 979 } else if (has_store_s0 && has_store_s1) { 980 /* 981 * process_store_log will execute the slot 1 store first, 982 * so we only have to probe the store in slot 0 983 */ 984 int args = 0; 985 args = 986 FIELD_DP32(args, PROBE_PKT_SCALAR_STORE_S0, MMU_IDX, ctx->mem_idx); 987 if (slot_is_predicated(pkt, 0)) { 988 args = 989 FIELD_DP32(args, PROBE_PKT_SCALAR_STORE_S0, IS_PREDICATED, 1); 990 } 991 TCGv args_tcgv = tcg_constant_tl(args); 992 gen_helper_probe_pkt_scalar_store_s0(tcg_env, args_tcgv); 993 } 994 995 process_store_log(ctx); 996 997 gen_reg_writes(ctx); 998 gen_pred_writes(ctx); 999 if (pkt->pkt_has_hvx) { 1000 gen_commit_hvx(ctx); 1001 } 1002 update_exec_counters(ctx); 1003 if (HEX_DEBUG) { 1004 TCGv has_st0 = 1005 tcg_constant_tl(pkt->pkt_has_store_s0 && !pkt->pkt_has_dczeroa); 1006 TCGv has_st1 = 1007 tcg_constant_tl(pkt->pkt_has_store_s1 && !pkt->pkt_has_dczeroa); 1008 1009 /* Handy place to set a breakpoint at the end of execution */ 1010 gen_helper_debug_commit_end(tcg_env, tcg_constant_tl(ctx->pkt->pc), 1011 ctx->pred_written, has_st0, has_st1); 1012 } 1013 1014 if (pkt->vhist_insn != NULL) { 1015 ctx->pre_commit = false; 1016 ctx->insn = pkt->vhist_insn; 1017 pkt->vhist_insn->generate(ctx); 1018 } 1019 1020 if (pkt->pkt_has_cof) { 1021 gen_end_tb(ctx); 1022 } 1023 } 1024 1025 static void decode_and_translate_packet(CPUHexagonState *env, DisasContext *ctx) 1026 { 1027 uint32_t words[PACKET_WORDS_MAX]; 1028 int nwords; 1029 Packet pkt; 1030 int i; 1031 1032 nwords = read_packet_words(env, ctx, words); 1033 if (!nwords) { 1034 gen_exception_end_tb(ctx, HEX_EXCP_INVALID_PACKET); 1035 return; 1036 } 1037 1038 ctx->pkt = &pkt; 1039 if (decode_packet(ctx, nwords, words, &pkt, false) > 0) { 1040 pkt.pc = ctx->base.pc_next; 1041 HEX_DEBUG_PRINT_PKT(&pkt); 1042 gen_start_packet(ctx); 1043 for (i = 0; i < pkt.num_insns; i++) { 1044 ctx->insn = &pkt.insn[i]; 1045 gen_insn(ctx); 1046 } 1047 gen_commit_packet(ctx); 1048 ctx->base.pc_next += pkt.encod_pkt_size_in_bytes; 1049 } else { 1050 gen_exception_end_tb(ctx, HEX_EXCP_INVALID_PACKET); 1051 } 1052 } 1053 1054 static void hexagon_tr_init_disas_context(DisasContextBase *dcbase, 1055 CPUState *cs) 1056 { 1057 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1058 HexagonCPU *hex_cpu = env_archcpu(cpu_env(cs)); 1059 uint32_t hex_flags = dcbase->tb->flags; 1060 1061 ctx->mem_idx = MMU_USER_IDX; 1062 ctx->num_packets = 0; 1063 ctx->num_insns = 0; 1064 ctx->num_hvx_insns = 0; 1065 ctx->branch_cond = TCG_COND_NEVER; 1066 ctx->is_tight_loop = FIELD_EX32(hex_flags, TB_FLAGS, IS_TIGHT_LOOP); 1067 ctx->short_circuit = hex_cpu->short_circuit; 1068 } 1069 1070 static void hexagon_tr_tb_start(DisasContextBase *db, CPUState *cpu) 1071 { 1072 } 1073 1074 static void hexagon_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) 1075 { 1076 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1077 1078 tcg_gen_insn_start(ctx->base.pc_next); 1079 } 1080 1081 static bool pkt_crosses_page(CPUHexagonState *env, DisasContext *ctx) 1082 { 1083 target_ulong page_start = ctx->base.pc_first & TARGET_PAGE_MASK; 1084 bool found_end = false; 1085 int nwords; 1086 1087 for (nwords = 0; !found_end && nwords < PACKET_WORDS_MAX; nwords++) { 1088 uint32_t word = cpu_ldl_code(env, 1089 ctx->base.pc_next + nwords * sizeof(uint32_t)); 1090 found_end = is_packet_end(word); 1091 } 1092 uint32_t next_ptr = ctx->base.pc_next + nwords * sizeof(uint32_t); 1093 return found_end && next_ptr - page_start >= TARGET_PAGE_SIZE; 1094 } 1095 1096 static void hexagon_tr_translate_packet(DisasContextBase *dcbase, CPUState *cpu) 1097 { 1098 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1099 CPUHexagonState *env = cpu_env(cpu); 1100 1101 decode_and_translate_packet(env, ctx); 1102 1103 if (ctx->base.is_jmp == DISAS_NEXT) { 1104 target_ulong page_start = ctx->base.pc_first & TARGET_PAGE_MASK; 1105 target_ulong bytes_max = PACKET_WORDS_MAX * sizeof(target_ulong); 1106 1107 if (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE || 1108 (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE - bytes_max && 1109 pkt_crosses_page(env, ctx))) { 1110 ctx->base.is_jmp = DISAS_TOO_MANY; 1111 } 1112 1113 /* 1114 * The CPU log is used to compare against LLDB single stepping, 1115 * so end the TLB after every packet. 1116 */ 1117 HexagonCPU *hex_cpu = env_archcpu(env); 1118 if (hex_cpu->lldb_compat && qemu_loglevel_mask(CPU_LOG_TB_CPU)) { 1119 ctx->base.is_jmp = DISAS_TOO_MANY; 1120 } 1121 } 1122 } 1123 1124 static void hexagon_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) 1125 { 1126 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1127 1128 switch (ctx->base.is_jmp) { 1129 case DISAS_TOO_MANY: 1130 gen_exec_counters(ctx); 1131 tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], ctx->base.pc_next); 1132 tcg_gen_exit_tb(NULL, 0); 1133 break; 1134 case DISAS_NORETURN: 1135 break; 1136 default: 1137 g_assert_not_reached(); 1138 } 1139 } 1140 1141 static void hexagon_tr_disas_log(const DisasContextBase *dcbase, 1142 CPUState *cpu, FILE *logfile) 1143 { 1144 fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first)); 1145 target_disas(logfile, cpu, dcbase->pc_first, dcbase->tb->size); 1146 } 1147 1148 1149 static const TranslatorOps hexagon_tr_ops = { 1150 .init_disas_context = hexagon_tr_init_disas_context, 1151 .tb_start = hexagon_tr_tb_start, 1152 .insn_start = hexagon_tr_insn_start, 1153 .translate_insn = hexagon_tr_translate_packet, 1154 .tb_stop = hexagon_tr_tb_stop, 1155 .disas_log = hexagon_tr_disas_log, 1156 }; 1157 1158 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, 1159 vaddr pc, void *host_pc) 1160 { 1161 DisasContext ctx; 1162 1163 translator_loop(cs, tb, max_insns, pc, host_pc, 1164 &hexagon_tr_ops, &ctx.base); 1165 } 1166 1167 #define NAME_LEN 64 1168 static char reg_written_names[TOTAL_PER_THREAD_REGS][NAME_LEN]; 1169 static char store_addr_names[STORES_MAX][NAME_LEN]; 1170 static char store_width_names[STORES_MAX][NAME_LEN]; 1171 static char store_val32_names[STORES_MAX][NAME_LEN]; 1172 static char store_val64_names[STORES_MAX][NAME_LEN]; 1173 static char vstore_addr_names[VSTORES_MAX][NAME_LEN]; 1174 static char vstore_size_names[VSTORES_MAX][NAME_LEN]; 1175 static char vstore_pending_names[VSTORES_MAX][NAME_LEN]; 1176 1177 void hexagon_translate_init(void) 1178 { 1179 int i; 1180 1181 opcode_init(); 1182 1183 for (i = 0; i < TOTAL_PER_THREAD_REGS; i++) { 1184 hex_gpr[i] = tcg_global_mem_new(tcg_env, 1185 offsetof(CPUHexagonState, gpr[i]), 1186 hexagon_regnames[i]); 1187 1188 if (HEX_DEBUG) { 1189 snprintf(reg_written_names[i], NAME_LEN, "reg_written_%s", 1190 hexagon_regnames[i]); 1191 hex_reg_written[i] = tcg_global_mem_new(tcg_env, 1192 offsetof(CPUHexagonState, reg_written[i]), 1193 reg_written_names[i]); 1194 } 1195 } 1196 hex_new_value_usr = tcg_global_mem_new(tcg_env, 1197 offsetof(CPUHexagonState, new_value_usr), "new_value_usr"); 1198 1199 for (i = 0; i < NUM_PREGS; i++) { 1200 hex_pred[i] = tcg_global_mem_new(tcg_env, 1201 offsetof(CPUHexagonState, pred[i]), 1202 hexagon_prednames[i]); 1203 } 1204 hex_slot_cancelled = tcg_global_mem_new(tcg_env, 1205 offsetof(CPUHexagonState, slot_cancelled), "slot_cancelled"); 1206 hex_llsc_addr = tcg_global_mem_new(tcg_env, 1207 offsetof(CPUHexagonState, llsc_addr), "llsc_addr"); 1208 hex_llsc_val = tcg_global_mem_new(tcg_env, 1209 offsetof(CPUHexagonState, llsc_val), "llsc_val"); 1210 hex_llsc_val_i64 = tcg_global_mem_new_i64(tcg_env, 1211 offsetof(CPUHexagonState, llsc_val_i64), "llsc_val_i64"); 1212 for (i = 0; i < STORES_MAX; i++) { 1213 snprintf(store_addr_names[i], NAME_LEN, "store_addr_%d", i); 1214 hex_store_addr[i] = tcg_global_mem_new(tcg_env, 1215 offsetof(CPUHexagonState, mem_log_stores[i].va), 1216 store_addr_names[i]); 1217 1218 snprintf(store_width_names[i], NAME_LEN, "store_width_%d", i); 1219 hex_store_width[i] = tcg_global_mem_new(tcg_env, 1220 offsetof(CPUHexagonState, mem_log_stores[i].width), 1221 store_width_names[i]); 1222 1223 snprintf(store_val32_names[i], NAME_LEN, "store_val32_%d", i); 1224 hex_store_val32[i] = tcg_global_mem_new(tcg_env, 1225 offsetof(CPUHexagonState, mem_log_stores[i].data32), 1226 store_val32_names[i]); 1227 1228 snprintf(store_val64_names[i], NAME_LEN, "store_val64_%d", i); 1229 hex_store_val64[i] = tcg_global_mem_new_i64(tcg_env, 1230 offsetof(CPUHexagonState, mem_log_stores[i].data64), 1231 store_val64_names[i]); 1232 } 1233 for (i = 0; i < VSTORES_MAX; i++) { 1234 snprintf(vstore_addr_names[i], NAME_LEN, "vstore_addr_%d", i); 1235 hex_vstore_addr[i] = tcg_global_mem_new(tcg_env, 1236 offsetof(CPUHexagonState, vstore[i].va), 1237 vstore_addr_names[i]); 1238 1239 snprintf(vstore_size_names[i], NAME_LEN, "vstore_size_%d", i); 1240 hex_vstore_size[i] = tcg_global_mem_new(tcg_env, 1241 offsetof(CPUHexagonState, vstore[i].size), 1242 vstore_size_names[i]); 1243 1244 snprintf(vstore_pending_names[i], NAME_LEN, "vstore_pending_%d", i); 1245 hex_vstore_pending[i] = tcg_global_mem_new(tcg_env, 1246 offsetof(CPUHexagonState, vstore_pending[i]), 1247 vstore_pending_names[i]); 1248 } 1249 } 1250