1 /* 2 * Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #ifndef HEXAGON_MACROS_H 19 #define HEXAGON_MACROS_H 20 21 #include "cpu.h" 22 #include "hex_regs.h" 23 #include "reg_fields.h" 24 25 #define PCALIGN 4 26 #define PCALIGN_MASK (PCALIGN - 1) 27 28 #define GET_FIELD(FIELD, REGIN) \ 29 fEXTRACTU_BITS(REGIN, reg_field_info[FIELD].width, \ 30 reg_field_info[FIELD].offset) 31 32 #ifdef QEMU_GENERATE 33 #define GET_USR_FIELD(FIELD, DST) \ 34 tcg_gen_extract_tl(DST, hex_gpr[HEX_REG_USR], \ 35 reg_field_info[FIELD].offset, \ 36 reg_field_info[FIELD].width) 37 38 #define TYPE_INT(X) __builtin_types_compatible_p(typeof(X), int) 39 #define TYPE_TCGV(X) __builtin_types_compatible_p(typeof(X), TCGv) 40 #define TYPE_TCGV_I64(X) __builtin_types_compatible_p(typeof(X), TCGv_i64) 41 #else 42 #define GET_USR_FIELD(FIELD) \ 43 fEXTRACTU_BITS(env->gpr[HEX_REG_USR], reg_field_info[FIELD].width, \ 44 reg_field_info[FIELD].offset) 45 46 #define SET_USR_FIELD(FIELD, VAL) \ 47 do { \ 48 if (pkt_need_commit) { \ 49 fINSERT_BITS(env->new_value_usr, \ 50 reg_field_info[FIELD].width, \ 51 reg_field_info[FIELD].offset, (VAL)); \ 52 } else { \ 53 fINSERT_BITS(env->gpr[HEX_REG_USR], \ 54 reg_field_info[FIELD].width, \ 55 reg_field_info[FIELD].offset, (VAL)); \ 56 } \ 57 } while (0) 58 #endif 59 60 #ifdef QEMU_GENERATE 61 /* 62 * Section 5.5 of the Hexagon V67 Programmer's Reference Manual 63 * 64 * Slot 1 store with slot 0 load 65 * A slot 1 store operation with a slot 0 load operation can appear in a packet. 66 * The packet attribute :mem_noshuf inhibits the instruction reordering that 67 * would otherwise be done by the assembler. For example: 68 * { 69 * memw(R5) = R2 // slot 1 store 70 * R3 = memh(R6) // slot 0 load 71 * }:mem_noshuf 72 * Unlike most packetized operations, these memory operations are not executed 73 * in parallel (Section 3.3.1). Instead, the store instruction in Slot 1 74 * effectively executes first, followed by the load instruction in Slot 0. If 75 * the addresses of the two operations are overlapping, the load will receive 76 * the newly stored data. This feature is supported in processor versions 77 * V65 or greater. 78 * 79 * 80 * For qemu, we look for a load in slot 0 when there is a store in slot 1 81 * in the same packet. When we see this, we call a helper that probes the 82 * load to make sure it doesn't fault. Then, we process the store ahead of 83 * the actual load. 84 85 */ 86 #define CHECK_NOSHUF(VA, SIZE) \ 87 do { \ 88 if (insn->slot == 0 && ctx->pkt->pkt_has_store_s1) { \ 89 probe_noshuf_load(VA, SIZE, ctx->mem_idx); \ 90 process_store(ctx, 1); \ 91 } \ 92 } while (0) 93 94 #define CHECK_NOSHUF_PRED(GET_EA, SIZE, PRED) \ 95 do { \ 96 TCGLabel *noshuf_label = gen_new_label(); \ 97 tcg_gen_brcondi_tl(TCG_COND_EQ, PRED, 0, noshuf_label); \ 98 GET_EA; \ 99 if (insn->slot == 0 && ctx->pkt->pkt_has_store_s1) { \ 100 probe_noshuf_load(EA, SIZE, ctx->mem_idx); \ 101 } \ 102 gen_set_label(noshuf_label); \ 103 if (insn->slot == 0 && ctx->pkt->pkt_has_store_s1) { \ 104 process_store(ctx, 1); \ 105 } \ 106 } while (0) 107 108 #define MEM_LOAD1s(DST, VA) \ 109 do { \ 110 CHECK_NOSHUF(VA, 1); \ 111 tcg_gen_qemu_ld_tl(DST, VA, ctx->mem_idx, MO_SB); \ 112 } while (0) 113 #define MEM_LOAD1u(DST, VA) \ 114 do { \ 115 CHECK_NOSHUF(VA, 1); \ 116 tcg_gen_qemu_ld_tl(DST, VA, ctx->mem_idx, MO_UB); \ 117 } while (0) 118 #define MEM_LOAD2s(DST, VA) \ 119 do { \ 120 CHECK_NOSHUF(VA, 2); \ 121 tcg_gen_qemu_ld_tl(DST, VA, ctx->mem_idx, MO_TESW); \ 122 } while (0) 123 #define MEM_LOAD2u(DST, VA) \ 124 do { \ 125 CHECK_NOSHUF(VA, 2); \ 126 tcg_gen_qemu_ld_tl(DST, VA, ctx->mem_idx, MO_TEUW); \ 127 } while (0) 128 #define MEM_LOAD4s(DST, VA) \ 129 do { \ 130 CHECK_NOSHUF(VA, 4); \ 131 tcg_gen_qemu_ld_tl(DST, VA, ctx->mem_idx, MO_TESL); \ 132 } while (0) 133 #define MEM_LOAD4u(DST, VA) \ 134 do { \ 135 CHECK_NOSHUF(VA, 4); \ 136 tcg_gen_qemu_ld_tl(DST, VA, ctx->mem_idx, MO_TEUL); \ 137 } while (0) 138 #define MEM_LOAD8u(DST, VA) \ 139 do { \ 140 CHECK_NOSHUF(VA, 8); \ 141 tcg_gen_qemu_ld_i64(DST, VA, ctx->mem_idx, MO_TEUQ); \ 142 } while (0) 143 144 #define MEM_STORE1_FUNC(X) \ 145 __builtin_choose_expr(TYPE_INT(X), \ 146 gen_store1i, \ 147 __builtin_choose_expr(TYPE_TCGV(X), \ 148 gen_store1, (void)0)) 149 #define MEM_STORE1(VA, DATA, SLOT) \ 150 MEM_STORE1_FUNC(DATA)(tcg_env, VA, DATA, SLOT) 151 152 #define MEM_STORE2_FUNC(X) \ 153 __builtin_choose_expr(TYPE_INT(X), \ 154 gen_store2i, \ 155 __builtin_choose_expr(TYPE_TCGV(X), \ 156 gen_store2, (void)0)) 157 #define MEM_STORE2(VA, DATA, SLOT) \ 158 MEM_STORE2_FUNC(DATA)(tcg_env, VA, DATA, SLOT) 159 160 #define MEM_STORE4_FUNC(X) \ 161 __builtin_choose_expr(TYPE_INT(X), \ 162 gen_store4i, \ 163 __builtin_choose_expr(TYPE_TCGV(X), \ 164 gen_store4, (void)0)) 165 #define MEM_STORE4(VA, DATA, SLOT) \ 166 MEM_STORE4_FUNC(DATA)(tcg_env, VA, DATA, SLOT) 167 168 #define MEM_STORE8_FUNC(X) \ 169 __builtin_choose_expr(TYPE_INT(X), \ 170 gen_store8i, \ 171 __builtin_choose_expr(TYPE_TCGV_I64(X), \ 172 gen_store8, (void)0)) 173 #define MEM_STORE8(VA, DATA, SLOT) \ 174 MEM_STORE8_FUNC(DATA)(tcg_env, VA, DATA, SLOT) 175 #else 176 #define MEM_STORE1(VA, DATA, SLOT) log_store32(env, VA, DATA, 1, SLOT) 177 #define MEM_STORE2(VA, DATA, SLOT) log_store32(env, VA, DATA, 2, SLOT) 178 #define MEM_STORE4(VA, DATA, SLOT) log_store32(env, VA, DATA, 4, SLOT) 179 #define MEM_STORE8(VA, DATA, SLOT) log_store64(env, VA, DATA, 8, SLOT) 180 #endif 181 182 #ifdef QEMU_GENERATE 183 static inline void gen_cancel(uint32_t slot) 184 { 185 tcg_gen_ori_tl(hex_slot_cancelled, hex_slot_cancelled, 1 << slot); 186 } 187 188 #define CANCEL gen_cancel(slot); 189 #else 190 #define CANCEL do { } while (0) 191 #endif 192 193 #define LOAD_CANCEL(EA) do { CANCEL; } while (0) 194 195 #define STORE_CANCEL(EA) { env->slot_cancelled |= (1 << slot); } 196 197 #define fMAX(A, B) (((A) > (B)) ? (A) : (B)) 198 199 #define fMIN(A, B) (((A) < (B)) ? (A) : (B)) 200 201 #define fABS(A) (((A) < 0) ? (-(A)) : (A)) 202 #define fINSERT_BITS(REG, WIDTH, OFFSET, INVAL) \ 203 REG = ((WIDTH) ? deposit64(REG, (OFFSET), (WIDTH), (INVAL)) : REG) 204 #define fEXTRACTU_BITS(INREG, WIDTH, OFFSET) \ 205 ((WIDTH) ? extract64((INREG), (OFFSET), (WIDTH)) : 0LL) 206 #define fEXTRACTU_BIDIR(INREG, WIDTH, OFFSET) \ 207 (fZXTN(WIDTH, 32, fBIDIR_LSHIFTR((INREG), (OFFSET), 4_8))) 208 #define fEXTRACTU_RANGE(INREG, HIBIT, LOWBIT) \ 209 (((HIBIT) - (LOWBIT) + 1) ? \ 210 extract64((INREG), (LOWBIT), ((HIBIT) - (LOWBIT) + 1)) : \ 211 0LL) 212 #define fINSERT_RANGE(INREG, HIBIT, LOWBIT, INVAL) \ 213 do { \ 214 int width = ((HIBIT) - (LOWBIT) + 1); \ 215 INREG = (width >= 0 ? \ 216 deposit64((INREG), (LOWBIT), width, (INVAL)) : \ 217 INREG); \ 218 } while (0) 219 220 #define f8BITSOF(VAL) ((VAL) ? 0xff : 0x00) 221 222 #ifdef QEMU_GENERATE 223 #define fLSBOLD(VAL) tcg_gen_andi_tl(LSB, (VAL), 1) 224 #else 225 #define fLSBOLD(VAL) ((VAL) & 1) 226 #endif 227 228 #ifdef QEMU_GENERATE 229 #define fLSBNEW(PVAL) tcg_gen_andi_tl(LSB, (PVAL), 1) 230 #else 231 #define fLSBNEW(PVAL) ((PVAL) & 1) 232 #endif 233 234 #ifdef QEMU_GENERATE 235 #define fLSBOLDNOT(VAL) \ 236 do { \ 237 tcg_gen_andi_tl(LSB, (VAL), 1); \ 238 tcg_gen_xori_tl(LSB, LSB, 1); \ 239 } while (0) 240 #define fLSBNEWNOT(PNUM) \ 241 do { \ 242 tcg_gen_andi_tl(LSB, (PNUM), 1); \ 243 tcg_gen_xori_tl(LSB, LSB, 1); \ 244 } while (0) 245 #else 246 #define fLSBNEWNOT(PNUM) (!fLSBNEW(PNUM)) 247 #define fLSBOLDNOT(VAL) (!fLSBOLD(VAL)) 248 #define fLSBNEW0NOT (!fLSBNEW0) 249 #define fLSBNEW1NOT (!fLSBNEW1) 250 #endif 251 252 #define fNEWREG(VAL) ((int32_t)(VAL)) 253 254 #define fNEWREG_ST(VAL) (VAL) 255 256 #define fVSATUVALN(N, VAL) \ 257 ({ \ 258 (((int64_t)(VAL)) < 0) ? 0 : ((1LL << (N)) - 1); \ 259 }) 260 #define fSATUVALN(N, VAL) \ 261 ({ \ 262 fSET_OVERFLOW(); \ 263 ((VAL) < 0) ? 0 : ((1LL << (N)) - 1); \ 264 }) 265 #define fSATVALN(N, VAL) \ 266 ({ \ 267 fSET_OVERFLOW(); \ 268 ((VAL) < 0) ? (-(1LL << ((N) - 1))) : ((1LL << ((N) - 1)) - 1); \ 269 }) 270 #define fVSATVALN(N, VAL) \ 271 ({ \ 272 ((VAL) < 0) ? (-(1LL << ((N) - 1))) : ((1LL << ((N) - 1)) - 1); \ 273 }) 274 #define fZXTN(N, M, VAL) (((N) != 0) ? extract64((VAL), 0, (N)) : 0LL) 275 #define fSXTN(N, M, VAL) (((N) != 0) ? sextract64((VAL), 0, (N)) : 0LL) 276 #define fSATN(N, VAL) \ 277 ((fSXTN(N, 64, VAL) == (VAL)) ? (VAL) : fSATVALN(N, VAL)) 278 #define fVSATN(N, VAL) \ 279 ((fSXTN(N, 64, VAL) == (VAL)) ? (VAL) : fVSATVALN(N, VAL)) 280 #define fADDSAT64(DST, A, B) \ 281 do { \ 282 uint64_t __a = fCAST8u(A); \ 283 uint64_t __b = fCAST8u(B); \ 284 uint64_t __sum = __a + __b; \ 285 uint64_t __xor = __a ^ __b; \ 286 const uint64_t __mask = 0x8000000000000000ULL; \ 287 if (__xor & __mask) { \ 288 DST = __sum; \ 289 } \ 290 else if ((__a ^ __sum) & __mask) { \ 291 if (__sum & __mask) { \ 292 DST = 0x7FFFFFFFFFFFFFFFLL; \ 293 fSET_OVERFLOW(); \ 294 } else { \ 295 DST = 0x8000000000000000LL; \ 296 fSET_OVERFLOW(); \ 297 } \ 298 } else { \ 299 DST = __sum; \ 300 } \ 301 } while (0) 302 #define fVSATUN(N, VAL) \ 303 ((fZXTN(N, 64, VAL) == (VAL)) ? (VAL) : fVSATUVALN(N, VAL)) 304 #define fSATUN(N, VAL) \ 305 ((fZXTN(N, 64, VAL) == (VAL)) ? (VAL) : fSATUVALN(N, VAL)) 306 #define fSATH(VAL) (fSATN(16, VAL)) 307 #define fSATUH(VAL) (fSATUN(16, VAL)) 308 #define fVSATH(VAL) (fVSATN(16, VAL)) 309 #define fVSATUH(VAL) (fVSATUN(16, VAL)) 310 #define fSATUB(VAL) (fSATUN(8, VAL)) 311 #define fSATB(VAL) (fSATN(8, VAL)) 312 #define fVSATUB(VAL) (fVSATUN(8, VAL)) 313 #define fVSATB(VAL) (fVSATN(8, VAL)) 314 #define fIMMEXT(IMM) (IMM = IMM) 315 #define fMUST_IMMEXT(IMM) fIMMEXT(IMM) 316 317 #define fPCALIGN(IMM) IMM = (IMM & ~PCALIGN_MASK) 318 319 #ifdef QEMU_GENERATE 320 static inline TCGv gen_read_ireg(TCGv result, TCGv val, int shift) 321 { 322 /* 323 * Section 2.2.4 of the Hexagon V67 Programmer's Reference Manual 324 * 325 * The "I" value from a modifier register is divided into two pieces 326 * LSB bits 23:17 327 * MSB bits 31:28 328 * The value is signed 329 * 330 * At the end we shift the result according to the shift argument 331 */ 332 TCGv msb = tcg_temp_new(); 333 TCGv lsb = tcg_temp_new(); 334 335 tcg_gen_extract_tl(lsb, val, 17, 7); 336 tcg_gen_sari_tl(msb, val, 21); 337 tcg_gen_deposit_tl(result, msb, lsb, 0, 7); 338 339 tcg_gen_shli_tl(result, result, shift); 340 return result; 341 } 342 #endif 343 344 #define fREAD_LR() (env->gpr[HEX_REG_LR]) 345 346 #define fREAD_SP() (env->gpr[HEX_REG_SP]) 347 #define fREAD_LC0 (env->gpr[HEX_REG_LC0]) 348 #define fREAD_LC1 (env->gpr[HEX_REG_LC1]) 349 #define fREAD_SA0 (env->gpr[HEX_REG_SA0]) 350 #define fREAD_SA1 (env->gpr[HEX_REG_SA1]) 351 #define fREAD_FP() (env->gpr[HEX_REG_FP]) 352 #ifdef FIXME 353 /* Figure out how to get insn->extension_valid to helper */ 354 #define fREAD_GP() \ 355 (insn->extension_valid ? 0 : env->gpr[HEX_REG_GP]) 356 #else 357 #define fREAD_GP() (env->gpr[HEX_REG_GP]) 358 #endif 359 #define fREAD_PC() (PC) 360 361 #define fREAD_P0() (env->pred[0]) 362 363 #define fCHECK_PCALIGN(A) 364 365 #define fWRITE_NPC(A) write_new_pc(env, pkt_has_multi_cof != 0, A) 366 367 #define fBRANCH(LOC, TYPE) fWRITE_NPC(LOC) 368 #define fJUMPR(REGNO, TARGET, TYPE) fBRANCH(TARGET, COF_TYPE_JUMPR) 369 #define fHINTJR(TARGET) { /* Not modelled in qemu */} 370 371 #define fSET_OVERFLOW() SET_USR_FIELD(USR_OVF, 1) 372 #define fSET_LPCFG(VAL) SET_USR_FIELD(USR_LPCFG, (VAL)) 373 #define fGET_LPCFG (GET_USR_FIELD(USR_LPCFG)) 374 #define fPART1(WORK) if (part1) { WORK; return; } 375 #define fCAST4u(A) ((uint32_t)(A)) 376 #define fCAST4s(A) ((int32_t)(A)) 377 #define fCAST8u(A) ((uint64_t)(A)) 378 #define fCAST8s(A) ((int64_t)(A)) 379 #define fCAST2_2s(A) ((int16_t)(A)) 380 #define fCAST2_2u(A) ((uint16_t)(A)) 381 #define fCAST4_4s(A) ((int32_t)(A)) 382 #define fCAST4_4u(A) ((uint32_t)(A)) 383 #define fCAST4_8s(A) ((int64_t)((int32_t)(A))) 384 #define fCAST4_8u(A) ((uint64_t)((uint32_t)(A))) 385 #define fCAST8_8s(A) ((int64_t)(A)) 386 #define fCAST8_8u(A) ((uint64_t)(A)) 387 #define fCAST2_8s(A) ((int64_t)((int16_t)(A))) 388 #define fCAST2_8u(A) ((uint64_t)((uint16_t)(A))) 389 #define fZE8_16(A) ((int16_t)((uint8_t)(A))) 390 #define fSE8_16(A) ((int16_t)((int8_t)(A))) 391 #define fSE16_32(A) ((int32_t)((int16_t)(A))) 392 #define fZE16_32(A) ((uint32_t)((uint16_t)(A))) 393 #define fSE32_64(A) ((int64_t)((int32_t)(A))) 394 #define fZE32_64(A) ((uint64_t)((uint32_t)(A))) 395 #define fSE8_32(A) ((int32_t)((int8_t)(A))) 396 #define fZE8_32(A) ((int32_t)((uint8_t)(A))) 397 #define fMPY8UU(A, B) (int)(fZE8_16(A) * fZE8_16(B)) 398 #define fMPY8US(A, B) (int)(fZE8_16(A) * fSE8_16(B)) 399 #define fMPY8SU(A, B) (int)(fSE8_16(A) * fZE8_16(B)) 400 #define fMPY8SS(A, B) (int)((short)(A) * (short)(B)) 401 #define fMPY16SS(A, B) fSE32_64(fSE16_32(A) * fSE16_32(B)) 402 #define fMPY16UU(A, B) fZE32_64(fZE16_32(A) * fZE16_32(B)) 403 #define fMPY16SU(A, B) fSE32_64(fSE16_32(A) * fZE16_32(B)) 404 #define fMPY16US(A, B) fMPY16SU(B, A) 405 #define fMPY32SS(A, B) (fSE32_64(A) * fSE32_64(B)) 406 #define fMPY32UU(A, B) (fZE32_64(A) * fZE32_64(B)) 407 #define fMPY32SU(A, B) (fSE32_64(A) * fZE32_64(B)) 408 #define fMPY3216SS(A, B) (fSE32_64(A) * fSXTN(16, 64, B)) 409 #define fMPY3216SU(A, B) (fSE32_64(A) * fZXTN(16, 64, B)) 410 #define fROUND(A) (A + 0x8000) 411 #define fCLIP(DST, SRC, U) \ 412 do { \ 413 int32_t maxv = (1 << U) - 1; \ 414 int32_t minv = -(1 << U); \ 415 DST = fMIN(maxv, fMAX(SRC, minv)); \ 416 } while (0) 417 #define fCRND(A) ((((A) & 0x3) == 0x3) ? ((A) + 1) : ((A))) 418 #define fRNDN(A, N) ((((N) == 0) ? (A) : (((fSE32_64(A)) + (1 << ((N) - 1)))))) 419 #define fCRNDN(A, N) (conv_round(A, N)) 420 #define fADD128(A, B) (int128_add(A, B)) 421 #define fSUB128(A, B) (int128_sub(A, B)) 422 #define fSHIFTR128(A, B) (int128_rshift(A, B)) 423 #define fSHIFTL128(A, B) (int128_lshift(A, B)) 424 #define fAND128(A, B) (int128_and(A, B)) 425 #define fCAST8S_16S(A) (int128_exts64(A)) 426 #define fCAST16S_8S(A) (int128_getlo(A)) 427 428 #ifdef QEMU_GENERATE 429 #define fEA_RI(REG, IMM) tcg_gen_addi_tl(EA, REG, IMM) 430 #define fEA_RRs(REG, REG2, SCALE) \ 431 do { \ 432 TCGv tmp = tcg_temp_new(); \ 433 tcg_gen_shli_tl(tmp, REG2, SCALE); \ 434 tcg_gen_add_tl(EA, REG, tmp); \ 435 } while (0) 436 #define fEA_IRs(IMM, REG, SCALE) \ 437 do { \ 438 tcg_gen_shli_tl(EA, REG, SCALE); \ 439 tcg_gen_addi_tl(EA, EA, IMM); \ 440 } while (0) 441 #else 442 #define fEA_RI(REG, IMM) \ 443 do { \ 444 EA = REG + IMM; \ 445 } while (0) 446 #define fEA_RRs(REG, REG2, SCALE) \ 447 do { \ 448 EA = REG + (REG2 << SCALE); \ 449 } while (0) 450 #define fEA_IRs(IMM, REG, SCALE) \ 451 do { \ 452 EA = IMM + (REG << SCALE); \ 453 } while (0) 454 #endif 455 456 #ifdef QEMU_GENERATE 457 #define fEA_IMM(IMM) tcg_gen_movi_tl(EA, IMM) 458 #define fEA_REG(REG) tcg_gen_mov_tl(EA, REG) 459 #define fEA_BREVR(REG) gen_helper_fbrev(EA, REG) 460 #define fPM_I(REG, IMM) tcg_gen_addi_tl(REG, REG, IMM) 461 #define fPM_M(REG, MVAL) tcg_gen_add_tl(REG, REG, MVAL) 462 #define fPM_CIRI(REG, IMM, MVAL) \ 463 do { \ 464 TCGv tcgv_siV = tcg_constant_tl(siV); \ 465 gen_helper_fcircadd(REG, REG, tcgv_siV, MuV, CS); \ 466 } while (0) 467 #else 468 #define fEA_IMM(IMM) do { EA = (IMM); } while (0) 469 #define fEA_REG(REG) do { EA = (REG); } while (0) 470 #define fEA_GPI(IMM) do { EA = (fREAD_GP() + (IMM)); } while (0) 471 #define fPM_I(REG, IMM) do { REG = REG + (IMM); } while (0) 472 #define fPM_M(REG, MVAL) do { REG = REG + (MVAL); } while (0) 473 #endif 474 #define fSCALE(N, A) (((int64_t)(A)) << N) 475 #define fVSATW(A) fVSATN(32, ((long long)A)) 476 #define fSATW(A) fSATN(32, ((long long)A)) 477 #define fVSAT(A) fVSATN(32, (A)) 478 #define fSAT(A) fSATN(32, (A)) 479 #define fSAT_ORIG_SHL(A, ORIG_REG) \ 480 ((((int32_t)((fSAT(A)) ^ ((int32_t)(ORIG_REG)))) < 0) \ 481 ? fSATVALN(32, ((int32_t)(ORIG_REG))) \ 482 : ((((ORIG_REG) > 0) && ((A) == 0)) ? fSATVALN(32, (ORIG_REG)) \ 483 : fSAT(A))) 484 #define fPASS(A) A 485 #define fBIDIR_SHIFTL(SRC, SHAMT, REGSTYPE) \ 486 (((SHAMT) < 0) ? ((fCAST##REGSTYPE(SRC) >> ((-(SHAMT)) - 1)) >> 1) \ 487 : (fCAST##REGSTYPE(SRC) << (SHAMT))) 488 #define fBIDIR_ASHIFTL(SRC, SHAMT, REGSTYPE) \ 489 fBIDIR_SHIFTL(SRC, SHAMT, REGSTYPE##s) 490 #define fBIDIR_LSHIFTL(SRC, SHAMT, REGSTYPE) \ 491 fBIDIR_SHIFTL(SRC, SHAMT, REGSTYPE##u) 492 #define fBIDIR_ASHIFTL_SAT(SRC, SHAMT, REGSTYPE) \ 493 (((SHAMT) < 0) ? ((fCAST##REGSTYPE##s(SRC) >> ((-(SHAMT)) - 1)) >> 1) \ 494 : fSAT_ORIG_SHL(fCAST##REGSTYPE##s(SRC) << (SHAMT), (SRC))) 495 #define fBIDIR_SHIFTR(SRC, SHAMT, REGSTYPE) \ 496 (((SHAMT) < 0) ? ((fCAST##REGSTYPE(SRC) << ((-(SHAMT)) - 1)) << 1) \ 497 : (fCAST##REGSTYPE(SRC) >> (SHAMT))) 498 #define fBIDIR_ASHIFTR(SRC, SHAMT, REGSTYPE) \ 499 fBIDIR_SHIFTR(SRC, SHAMT, REGSTYPE##s) 500 #define fBIDIR_LSHIFTR(SRC, SHAMT, REGSTYPE) \ 501 fBIDIR_SHIFTR(SRC, SHAMT, REGSTYPE##u) 502 #define fBIDIR_ASHIFTR_SAT(SRC, SHAMT, REGSTYPE) \ 503 (((SHAMT) < 0) ? fSAT_ORIG_SHL((fCAST##REGSTYPE##s(SRC) \ 504 << ((-(SHAMT)) - 1)) << 1, (SRC)) \ 505 : (fCAST##REGSTYPE##s(SRC) >> (SHAMT))) 506 #define fASHIFTR(SRC, SHAMT, REGSTYPE) (fCAST##REGSTYPE##s(SRC) >> (SHAMT)) 507 #define fLSHIFTR(SRC, SHAMT, REGSTYPE) \ 508 (((SHAMT) >= (sizeof(SRC) * 8)) ? 0 : (fCAST##REGSTYPE##u(SRC) >> (SHAMT))) 509 #define fROTL(SRC, SHAMT, REGSTYPE) \ 510 (((SHAMT) == 0) ? (SRC) : ((fCAST##REGSTYPE##u(SRC) << (SHAMT)) | \ 511 ((fCAST##REGSTYPE##u(SRC) >> \ 512 ((sizeof(SRC) * 8) - (SHAMT)))))) 513 #define fROTR(SRC, SHAMT, REGSTYPE) \ 514 (((SHAMT) == 0) ? (SRC) : ((fCAST##REGSTYPE##u(SRC) >> (SHAMT)) | \ 515 ((fCAST##REGSTYPE##u(SRC) << \ 516 ((sizeof(SRC) * 8) - (SHAMT)))))) 517 #define fASHIFTL(SRC, SHAMT, REGSTYPE) \ 518 (((SHAMT) >= (sizeof(SRC) * 8)) ? 0 : (fCAST##REGSTYPE##s(SRC) << (SHAMT))) 519 520 #ifdef QEMU_GENERATE 521 #define fLOAD(NUM, SIZE, SIGN, EA, DST) MEM_LOAD##SIZE##SIGN(DST, EA) 522 #else 523 #define MEM_LOAD1 cpu_ldub_data_ra 524 #define MEM_LOAD2 cpu_lduw_data_ra 525 #define MEM_LOAD4 cpu_ldl_data_ra 526 #define MEM_LOAD8 cpu_ldq_data_ra 527 528 #define fLOAD(NUM, SIZE, SIGN, EA, DST) \ 529 do { \ 530 check_noshuf(env, pkt_has_store_s1, slot, EA, SIZE, GETPC()); \ 531 DST = (size##SIZE##SIGN##_t)MEM_LOAD##SIZE(env, EA, GETPC()); \ 532 } while (0) 533 #endif 534 535 #define fMEMOP(NUM, SIZE, SIGN, EA, FNTYPE, VALUE) 536 537 #define fGET_FRAMEKEY() (env->gpr[HEX_REG_FRAMEKEY]) 538 #define fFRAME_SCRAMBLE(VAL) ((VAL) ^ (fCAST8u(fGET_FRAMEKEY()) << 32)) 539 #define fFRAME_UNSCRAMBLE(VAL) fFRAME_SCRAMBLE(VAL) 540 541 #ifdef CONFIG_USER_ONLY 542 #define fFRAMECHECK(ADDR, EA) do { } while (0) /* Not modelled in linux-user */ 543 #else 544 /* System mode not implemented yet */ 545 #define fFRAMECHECK(ADDR, EA) g_assert_not_reached(); 546 #endif 547 548 #ifdef QEMU_GENERATE 549 #define fLOAD_LOCKED(NUM, SIZE, SIGN, EA, DST) \ 550 gen_load_locked##SIZE##SIGN(DST, EA, ctx->mem_idx); 551 #endif 552 553 #ifdef QEMU_GENERATE 554 #define fSTORE(NUM, SIZE, EA, SRC) MEM_STORE##SIZE(EA, SRC, insn->slot) 555 #else 556 #define fSTORE(NUM, SIZE, EA, SRC) MEM_STORE##SIZE(EA, SRC, slot) 557 #endif 558 559 #ifdef QEMU_GENERATE 560 #define fSTORE_LOCKED(NUM, SIZE, EA, SRC, PRED) \ 561 gen_store_conditional##SIZE(ctx, PRED, EA, SRC); 562 #endif 563 564 #ifdef QEMU_GENERATE 565 #define GETBYTE_FUNC(X) \ 566 __builtin_choose_expr(TYPE_TCGV(X), \ 567 gen_get_byte, \ 568 __builtin_choose_expr(TYPE_TCGV_I64(X), \ 569 gen_get_byte_i64, (void)0)) 570 #define fGETBYTE(N, SRC) GETBYTE_FUNC(SRC)(BYTE, N, SRC, true) 571 #define fGETUBYTE(N, SRC) GETBYTE_FUNC(SRC)(BYTE, N, SRC, false) 572 #else 573 #define fGETBYTE(N, SRC) ((int8_t)((SRC >> ((N) * 8)) & 0xff)) 574 #define fGETUBYTE(N, SRC) ((uint8_t)((SRC >> ((N) * 8)) & 0xff)) 575 #endif 576 577 #define fSETBYTE(N, DST, VAL) \ 578 do { \ 579 DST = (DST & ~(0x0ffLL << ((N) * 8))) | \ 580 (((uint64_t)((VAL) & 0x0ffLL)) << ((N) * 8)); \ 581 } while (0) 582 583 #ifdef QEMU_GENERATE 584 #define fGETHALF(N, SRC) gen_get_half(HALF, N, SRC, true) 585 #define fGETUHALF(N, SRC) gen_get_half(HALF, N, SRC, false) 586 #else 587 #define fGETHALF(N, SRC) ((int16_t)((SRC >> ((N) * 16)) & 0xffff)) 588 #define fGETUHALF(N, SRC) ((uint16_t)((SRC >> ((N) * 16)) & 0xffff)) 589 #endif 590 #define fSETHALF(N, DST, VAL) \ 591 do { \ 592 DST = (DST & ~(0x0ffffLL << ((N) * 16))) | \ 593 (((uint64_t)((VAL) & 0x0ffff)) << ((N) * 16)); \ 594 } while (0) 595 #define fSETHALFw fSETHALF 596 #define fSETHALFd fSETHALF 597 598 #define fGETWORD(N, SRC) \ 599 ((int64_t)((int32_t)((SRC >> ((N) * 32)) & 0x0ffffffffLL))) 600 #define fGETUWORD(N, SRC) \ 601 ((uint64_t)((uint32_t)((SRC >> ((N) * 32)) & 0x0ffffffffLL))) 602 603 #define fSETWORD(N, DST, VAL) \ 604 do { \ 605 DST = (DST & ~(0x0ffffffffLL << ((N) * 32))) | \ 606 (((VAL) & 0x0ffffffffLL) << ((N) * 32)); \ 607 } while (0) 608 609 #define fSETBIT(N, DST, VAL) \ 610 do { \ 611 DST = (DST & ~(1ULL << (N))) | (((uint64_t)(VAL)) << (N)); \ 612 } while (0) 613 614 #define fGETBIT(N, SRC) (((SRC) >> N) & 1) 615 #define fSETBITS(HI, LO, DST, VAL) \ 616 do { \ 617 int j; \ 618 for (j = LO; j <= HI; j++) { \ 619 fSETBIT(j, DST, VAL); \ 620 } \ 621 } while (0) 622 #define fCOUNTONES_2(VAL) ctpop16(VAL) 623 #define fCOUNTONES_4(VAL) ctpop32(VAL) 624 #define fCOUNTONES_8(VAL) ctpop64(VAL) 625 #define fBREV_8(VAL) revbit64(VAL) 626 #define fBREV_4(VAL) revbit32(VAL) 627 #define fCL1_8(VAL) clo64(VAL) 628 #define fCL1_4(VAL) clo32(VAL) 629 #define fCL1_2(VAL) (clz32(~(uint16_t)(VAL) & 0xffff) - 16) 630 #define fINTERLEAVE(ODD, EVEN) interleave(ODD, EVEN) 631 #define fDEINTERLEAVE(MIXED) deinterleave(MIXED) 632 #define fHIDE(A) A 633 #define fCONSTLL(A) A##LL 634 #define fECHO(A) (A) 635 636 #define fTRAP(TRAPTYPE, IMM) helper_raise_exception(env, HEX_EXCP_TRAP0) 637 #define fPAUSE(IMM) 638 639 #define fALIGN_REG_FIELD_VALUE(FIELD, VAL) \ 640 ((VAL) << reg_field_info[FIELD].offset) 641 #define fGET_REG_FIELD_MASK(FIELD) \ 642 (((1 << reg_field_info[FIELD].width) - 1) << reg_field_info[FIELD].offset) 643 #define fREAD_REG_FIELD(REG, FIELD) \ 644 fEXTRACTU_BITS(env->gpr[HEX_REG_##REG], \ 645 reg_field_info[FIELD].width, \ 646 reg_field_info[FIELD].offset) 647 648 #ifdef QEMU_GENERATE 649 #define fDCZEROA(REG) \ 650 do { \ 651 ctx->dczero_addr = tcg_temp_new(); \ 652 tcg_gen_mov_tl(ctx->dczero_addr, (REG)); \ 653 } while (0) 654 #endif 655 656 #define fBRANCH_SPECULATE_STALL(DOTNEWVAL, JUMP_COND, SPEC_DIR, HINTBITNUM, \ 657 STRBITNUM) /* Nothing */ 658 659 660 #endif 661