1 /* 2 * Copyright(c) 2019-2024 Qualcomm Innovation Center, Inc. All Rights Reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #ifndef HEXAGON_MACROS_H 19 #define HEXAGON_MACROS_H 20 21 #include "cpu.h" 22 #include "hex_regs.h" 23 #include "reg_fields.h" 24 25 #define GET_FIELD(FIELD, REGIN) \ 26 fEXTRACTU_BITS(REGIN, reg_field_info[FIELD].width, \ 27 reg_field_info[FIELD].offset) 28 29 #ifdef QEMU_GENERATE 30 #define GET_USR_FIELD(FIELD, DST) \ 31 tcg_gen_extract_tl(DST, hex_gpr[HEX_REG_USR], \ 32 reg_field_info[FIELD].offset, \ 33 reg_field_info[FIELD].width) 34 35 #define TYPE_INT(X) __builtin_types_compatible_p(typeof(X), int) 36 #define TYPE_TCGV(X) __builtin_types_compatible_p(typeof(X), TCGv) 37 #define TYPE_TCGV_I64(X) __builtin_types_compatible_p(typeof(X), TCGv_i64) 38 #else 39 #define GET_USR_FIELD(FIELD) \ 40 fEXTRACTU_BITS(env->gpr[HEX_REG_USR], reg_field_info[FIELD].width, \ 41 reg_field_info[FIELD].offset) 42 43 #define SET_USR_FIELD(FIELD, VAL) \ 44 do { \ 45 if (pkt_need_commit) { \ 46 fINSERT_BITS(env->new_value_usr, \ 47 reg_field_info[FIELD].width, \ 48 reg_field_info[FIELD].offset, (VAL)); \ 49 } else { \ 50 fINSERT_BITS(env->gpr[HEX_REG_USR], \ 51 reg_field_info[FIELD].width, \ 52 reg_field_info[FIELD].offset, (VAL)); \ 53 } \ 54 } while (0) 55 #endif 56 57 #ifdef QEMU_GENERATE 58 /* 59 * Section 5.5 of the Hexagon V67 Programmer's Reference Manual 60 * 61 * Slot 1 store with slot 0 load 62 * A slot 1 store operation with a slot 0 load operation can appear in a packet. 63 * The packet attribute :mem_noshuf inhibits the instruction reordering that 64 * would otherwise be done by the assembler. For example: 65 * { 66 * memw(R5) = R2 // slot 1 store 67 * R3 = memh(R6) // slot 0 load 68 * }:mem_noshuf 69 * Unlike most packetized operations, these memory operations are not executed 70 * in parallel (Section 3.3.1). Instead, the store instruction in Slot 1 71 * effectively executes first, followed by the load instruction in Slot 0. If 72 * the addresses of the two operations are overlapping, the load will receive 73 * the newly stored data. This feature is supported in processor versions 74 * V65 or greater. 75 * 76 * 77 * For qemu, we look for a load in slot 0 when there is a store in slot 1 78 * in the same packet. When we see this, we call a helper that probes the 79 * load to make sure it doesn't fault. Then, we process the store ahead of 80 * the actual load. 81 82 */ 83 #define CHECK_NOSHUF(VA, SIZE) \ 84 do { \ 85 if (insn->slot == 0 && ctx->pkt->pkt_has_store_s1) { \ 86 probe_noshuf_load(VA, SIZE, ctx->mem_idx); \ 87 process_store(ctx, 1); \ 88 } \ 89 } while (0) 90 91 #define CHECK_NOSHUF_PRED(GET_EA, SIZE, PRED) \ 92 do { \ 93 TCGLabel *noshuf_label = gen_new_label(); \ 94 tcg_gen_brcondi_tl(TCG_COND_EQ, PRED, 0, noshuf_label); \ 95 GET_EA; \ 96 if (insn->slot == 0 && ctx->pkt->pkt_has_store_s1) { \ 97 probe_noshuf_load(EA, SIZE, ctx->mem_idx); \ 98 } \ 99 gen_set_label(noshuf_label); \ 100 if (insn->slot == 0 && ctx->pkt->pkt_has_store_s1) { \ 101 process_store(ctx, 1); \ 102 } \ 103 } while (0) 104 105 #define MEM_LOAD1s(DST, VA) \ 106 do { \ 107 CHECK_NOSHUF(VA, 1); \ 108 tcg_gen_qemu_ld_tl(DST, VA, ctx->mem_idx, MO_SB); \ 109 } while (0) 110 #define MEM_LOAD1u(DST, VA) \ 111 do { \ 112 CHECK_NOSHUF(VA, 1); \ 113 tcg_gen_qemu_ld_tl(DST, VA, ctx->mem_idx, MO_UB); \ 114 } while (0) 115 #define MEM_LOAD2s(DST, VA) \ 116 do { \ 117 CHECK_NOSHUF(VA, 2); \ 118 tcg_gen_qemu_ld_tl(DST, VA, ctx->mem_idx, MO_TESW); \ 119 } while (0) 120 #define MEM_LOAD2u(DST, VA) \ 121 do { \ 122 CHECK_NOSHUF(VA, 2); \ 123 tcg_gen_qemu_ld_tl(DST, VA, ctx->mem_idx, MO_TEUW); \ 124 } while (0) 125 #define MEM_LOAD4s(DST, VA) \ 126 do { \ 127 CHECK_NOSHUF(VA, 4); \ 128 tcg_gen_qemu_ld_tl(DST, VA, ctx->mem_idx, MO_TESL); \ 129 } while (0) 130 #define MEM_LOAD4u(DST, VA) \ 131 do { \ 132 CHECK_NOSHUF(VA, 4); \ 133 tcg_gen_qemu_ld_tl(DST, VA, ctx->mem_idx, MO_TEUL); \ 134 } while (0) 135 #define MEM_LOAD8u(DST, VA) \ 136 do { \ 137 CHECK_NOSHUF(VA, 8); \ 138 tcg_gen_qemu_ld_i64(DST, VA, ctx->mem_idx, MO_TEUQ); \ 139 } while (0) 140 141 #define MEM_STORE1_FUNC(X) \ 142 __builtin_choose_expr(TYPE_INT(X), \ 143 gen_store1i, \ 144 __builtin_choose_expr(TYPE_TCGV(X), \ 145 gen_store1, (void)0)) 146 #define MEM_STORE1(VA, DATA, SLOT) \ 147 MEM_STORE1_FUNC(DATA)(tcg_env, VA, DATA, SLOT) 148 149 #define MEM_STORE2_FUNC(X) \ 150 __builtin_choose_expr(TYPE_INT(X), \ 151 gen_store2i, \ 152 __builtin_choose_expr(TYPE_TCGV(X), \ 153 gen_store2, (void)0)) 154 #define MEM_STORE2(VA, DATA, SLOT) \ 155 MEM_STORE2_FUNC(DATA)(tcg_env, VA, DATA, SLOT) 156 157 #define MEM_STORE4_FUNC(X) \ 158 __builtin_choose_expr(TYPE_INT(X), \ 159 gen_store4i, \ 160 __builtin_choose_expr(TYPE_TCGV(X), \ 161 gen_store4, (void)0)) 162 #define MEM_STORE4(VA, DATA, SLOT) \ 163 MEM_STORE4_FUNC(DATA)(tcg_env, VA, DATA, SLOT) 164 165 #define MEM_STORE8_FUNC(X) \ 166 __builtin_choose_expr(TYPE_INT(X), \ 167 gen_store8i, \ 168 __builtin_choose_expr(TYPE_TCGV_I64(X), \ 169 gen_store8, (void)0)) 170 #define MEM_STORE8(VA, DATA, SLOT) \ 171 MEM_STORE8_FUNC(DATA)(tcg_env, VA, DATA, SLOT) 172 #else 173 #define MEM_STORE1(VA, DATA, SLOT) log_store32(env, VA, DATA, 1, SLOT) 174 #define MEM_STORE2(VA, DATA, SLOT) log_store32(env, VA, DATA, 2, SLOT) 175 #define MEM_STORE4(VA, DATA, SLOT) log_store32(env, VA, DATA, 4, SLOT) 176 #define MEM_STORE8(VA, DATA, SLOT) log_store64(env, VA, DATA, 8, SLOT) 177 #endif 178 179 #ifdef QEMU_GENERATE 180 static inline void gen_cancel(uint32_t slot) 181 { 182 tcg_gen_ori_tl(hex_slot_cancelled, hex_slot_cancelled, 1 << slot); 183 } 184 185 #define CANCEL gen_cancel(slot); 186 #else 187 #define CANCEL do { } while (0) 188 #endif 189 190 #define LOAD_CANCEL(EA) do { CANCEL; } while (0) 191 192 #define STORE_CANCEL(EA) { env->slot_cancelled |= (1 << slot); } 193 194 #define fMAX(A, B) (((A) > (B)) ? (A) : (B)) 195 196 #define fMIN(A, B) (((A) < (B)) ? (A) : (B)) 197 198 #define fABS(A) (((A) < 0) ? (-(A)) : (A)) 199 #define fINSERT_BITS(REG, WIDTH, OFFSET, INVAL) \ 200 REG = ((WIDTH) ? deposit64(REG, (OFFSET), (WIDTH), (INVAL)) : REG) 201 #define fEXTRACTU_BITS(INREG, WIDTH, OFFSET) \ 202 ((WIDTH) ? extract64((INREG), (OFFSET), (WIDTH)) : 0LL) 203 #define fEXTRACTU_BIDIR(INREG, WIDTH, OFFSET) \ 204 (fZXTN(WIDTH, 32, fBIDIR_LSHIFTR((INREG), (OFFSET), 4_8))) 205 #define fEXTRACTU_RANGE(INREG, HIBIT, LOWBIT) \ 206 (((HIBIT) - (LOWBIT) + 1) ? \ 207 extract64((INREG), (LOWBIT), ((HIBIT) - (LOWBIT) + 1)) : \ 208 0LL) 209 #define fINSERT_RANGE(INREG, HIBIT, LOWBIT, INVAL) \ 210 do { \ 211 int width = ((HIBIT) - (LOWBIT) + 1); \ 212 INREG = (width >= 0 ? \ 213 deposit64((INREG), (LOWBIT), width, (INVAL)) : \ 214 INREG); \ 215 } while (0) 216 217 #define f8BITSOF(VAL) ((VAL) ? 0xff : 0x00) 218 219 #ifdef QEMU_GENERATE 220 #define fLSBOLD(VAL) tcg_gen_andi_tl(LSB, (VAL), 1) 221 #else 222 #define fLSBOLD(VAL) ((VAL) & 1) 223 #endif 224 225 #ifdef QEMU_GENERATE 226 #define fLSBNEW(PVAL) tcg_gen_andi_tl(LSB, (PVAL), 1) 227 #else 228 #define fLSBNEW(PVAL) ((PVAL) & 1) 229 #endif 230 231 #ifdef QEMU_GENERATE 232 #define fLSBOLDNOT(VAL) \ 233 do { \ 234 tcg_gen_andi_tl(LSB, (VAL), 1); \ 235 tcg_gen_xori_tl(LSB, LSB, 1); \ 236 } while (0) 237 #define fLSBNEWNOT(PNUM) \ 238 do { \ 239 tcg_gen_andi_tl(LSB, (PNUM), 1); \ 240 tcg_gen_xori_tl(LSB, LSB, 1); \ 241 } while (0) 242 #else 243 #define fLSBNEWNOT(PNUM) (!fLSBNEW(PNUM)) 244 #define fLSBOLDNOT(VAL) (!fLSBOLD(VAL)) 245 #define fLSBNEW0NOT (!fLSBNEW0) 246 #define fLSBNEW1NOT (!fLSBNEW1) 247 #endif 248 249 #define fNEWREG(VAL) ((int32_t)(VAL)) 250 251 #define fNEWREG_ST(VAL) (VAL) 252 253 #define fVSATUVALN(N, VAL) \ 254 ({ \ 255 (((int64_t)(VAL)) < 0) ? 0 : ((1LL << (N)) - 1); \ 256 }) 257 #define fSATUVALN(N, VAL) \ 258 ({ \ 259 fSET_OVERFLOW(); \ 260 ((VAL) < 0) ? 0 : ((1LL << (N)) - 1); \ 261 }) 262 #define fSATVALN(N, VAL) \ 263 ({ \ 264 fSET_OVERFLOW(); \ 265 ((VAL) < 0) ? (-(1LL << ((N) - 1))) : ((1LL << ((N) - 1)) - 1); \ 266 }) 267 #define fVSATVALN(N, VAL) \ 268 ({ \ 269 ((VAL) < 0) ? (-(1LL << ((N) - 1))) : ((1LL << ((N) - 1)) - 1); \ 270 }) 271 #define fZXTN(N, M, VAL) (((N) != 0) ? extract64((VAL), 0, (N)) : 0LL) 272 #define fSXTN(N, M, VAL) (((N) != 0) ? sextract64((VAL), 0, (N)) : 0LL) 273 #define fSATN(N, VAL) \ 274 ((fSXTN(N, 64, VAL) == (VAL)) ? (VAL) : fSATVALN(N, VAL)) 275 #define fVSATN(N, VAL) \ 276 ((fSXTN(N, 64, VAL) == (VAL)) ? (VAL) : fVSATVALN(N, VAL)) 277 #define fADDSAT64(DST, A, B) \ 278 do { \ 279 uint64_t __a = fCAST8u(A); \ 280 uint64_t __b = fCAST8u(B); \ 281 uint64_t __sum = __a + __b; \ 282 uint64_t __xor = __a ^ __b; \ 283 const uint64_t __mask = 0x8000000000000000ULL; \ 284 if (__xor & __mask) { \ 285 DST = __sum; \ 286 } \ 287 else if ((__a ^ __sum) & __mask) { \ 288 if (__sum & __mask) { \ 289 DST = 0x7FFFFFFFFFFFFFFFLL; \ 290 fSET_OVERFLOW(); \ 291 } else { \ 292 DST = 0x8000000000000000LL; \ 293 fSET_OVERFLOW(); \ 294 } \ 295 } else { \ 296 DST = __sum; \ 297 } \ 298 } while (0) 299 #define fVSATUN(N, VAL) \ 300 ((fZXTN(N, 64, VAL) == (VAL)) ? (VAL) : fVSATUVALN(N, VAL)) 301 #define fSATUN(N, VAL) \ 302 ((fZXTN(N, 64, VAL) == (VAL)) ? (VAL) : fSATUVALN(N, VAL)) 303 #define fSATH(VAL) (fSATN(16, VAL)) 304 #define fSATUH(VAL) (fSATUN(16, VAL)) 305 #define fVSATH(VAL) (fVSATN(16, VAL)) 306 #define fVSATUH(VAL) (fVSATUN(16, VAL)) 307 #define fSATUB(VAL) (fSATUN(8, VAL)) 308 #define fSATB(VAL) (fSATN(8, VAL)) 309 #define fVSATUB(VAL) (fVSATUN(8, VAL)) 310 #define fVSATB(VAL) (fVSATN(8, VAL)) 311 #define fIMMEXT(IMM) (IMM = IMM) 312 #define fMUST_IMMEXT(IMM) fIMMEXT(IMM) 313 314 #define fPCALIGN(IMM) IMM = (IMM & ~PCALIGN_MASK) 315 316 #ifdef QEMU_GENERATE 317 static inline TCGv gen_read_ireg(TCGv result, TCGv val, int shift) 318 { 319 /* 320 * Section 2.2.4 of the Hexagon V67 Programmer's Reference Manual 321 * 322 * The "I" value from a modifier register is divided into two pieces 323 * LSB bits 23:17 324 * MSB bits 31:28 325 * The value is signed 326 * 327 * At the end we shift the result according to the shift argument 328 */ 329 TCGv msb = tcg_temp_new(); 330 TCGv lsb = tcg_temp_new(); 331 332 tcg_gen_extract_tl(lsb, val, 17, 7); 333 tcg_gen_sari_tl(msb, val, 21); 334 tcg_gen_deposit_tl(result, msb, lsb, 0, 7); 335 336 tcg_gen_shli_tl(result, result, shift); 337 return result; 338 } 339 #endif 340 341 #define fREAD_LR() (env->gpr[HEX_REG_LR]) 342 343 #define fREAD_SP() (SP) 344 #define fREAD_LC0 (env->gpr[HEX_REG_LC0]) 345 #define fREAD_LC1 (env->gpr[HEX_REG_LC1]) 346 #define fREAD_SA0 (env->gpr[HEX_REG_SA0]) 347 #define fREAD_SA1 (env->gpr[HEX_REG_SA1]) 348 #define fREAD_FP() (env->gpr[HEX_REG_FP]) 349 #ifdef FIXME 350 /* Figure out how to get insn->extension_valid to helper */ 351 #define fREAD_GP() \ 352 (insn->extension_valid ? 0 : env->gpr[HEX_REG_GP]) 353 #else 354 #define fREAD_GP() (env->gpr[HEX_REG_GP]) 355 #endif 356 #define fREAD_PC() (PC) 357 358 #define fREAD_P0() (P0) 359 360 #define fCHECK_PCALIGN(A) 361 362 #define fWRITE_NPC(A) write_new_pc(env, pkt_has_multi_cof != 0, A) 363 364 #define fBRANCH(LOC, TYPE) fWRITE_NPC(LOC) 365 #define fJUMPR(REGNO, TARGET, TYPE) fBRANCH(TARGET, COF_TYPE_JUMPR) 366 #define fHINTJR(TARGET) { /* Not modelled in qemu */} 367 368 #define fSET_OVERFLOW() SET_USR_FIELD(USR_OVF, 1) 369 #define fSET_LPCFG(VAL) SET_USR_FIELD(USR_LPCFG, (VAL)) 370 #define fGET_LPCFG (GET_USR_FIELD(USR_LPCFG)) 371 #define fPART1(WORK) if (part1) { WORK; return; } 372 #define fCAST4u(A) ((uint32_t)(A)) 373 #define fCAST4s(A) ((int32_t)(A)) 374 #define fCAST8u(A) ((uint64_t)(A)) 375 #define fCAST8s(A) ((int64_t)(A)) 376 #define fCAST2_2s(A) ((int16_t)(A)) 377 #define fCAST2_2u(A) ((uint16_t)(A)) 378 #define fCAST4_4s(A) ((int32_t)(A)) 379 #define fCAST4_4u(A) ((uint32_t)(A)) 380 #define fCAST4_8s(A) ((int64_t)((int32_t)(A))) 381 #define fCAST4_8u(A) ((uint64_t)((uint32_t)(A))) 382 #define fCAST8_8s(A) ((int64_t)(A)) 383 #define fCAST8_8u(A) ((uint64_t)(A)) 384 #define fCAST2_8s(A) ((int64_t)((int16_t)(A))) 385 #define fCAST2_8u(A) ((uint64_t)((uint16_t)(A))) 386 #define fZE8_16(A) ((int16_t)((uint8_t)(A))) 387 #define fSE8_16(A) ((int16_t)((int8_t)(A))) 388 #define fSE16_32(A) ((int32_t)((int16_t)(A))) 389 #define fZE16_32(A) ((uint32_t)((uint16_t)(A))) 390 #define fSE32_64(A) ((int64_t)((int32_t)(A))) 391 #define fZE32_64(A) ((uint64_t)((uint32_t)(A))) 392 #define fSE8_32(A) ((int32_t)((int8_t)(A))) 393 #define fZE8_32(A) ((int32_t)((uint8_t)(A))) 394 #define fMPY8UU(A, B) (int)(fZE8_16(A) * fZE8_16(B)) 395 #define fMPY8US(A, B) (int)(fZE8_16(A) * fSE8_16(B)) 396 #define fMPY8SU(A, B) (int)(fSE8_16(A) * fZE8_16(B)) 397 #define fMPY8SS(A, B) (int)((short)(A) * (short)(B)) 398 #define fMPY16SS(A, B) fSE32_64(fSE16_32(A) * fSE16_32(B)) 399 #define fMPY16UU(A, B) fZE32_64(fZE16_32(A) * fZE16_32(B)) 400 #define fMPY16SU(A, B) fSE32_64(fSE16_32(A) * fZE16_32(B)) 401 #define fMPY16US(A, B) fMPY16SU(B, A) 402 #define fMPY32SS(A, B) (fSE32_64(A) * fSE32_64(B)) 403 #define fMPY32UU(A, B) (fZE32_64(A) * fZE32_64(B)) 404 #define fMPY32SU(A, B) (fSE32_64(A) * fZE32_64(B)) 405 #define fMPY3216SS(A, B) (fSE32_64(A) * fSXTN(16, 64, B)) 406 #define fMPY3216SU(A, B) (fSE32_64(A) * fZXTN(16, 64, B)) 407 #define fROUND(A) (A + 0x8000) 408 #define fCLIP(DST, SRC, U) \ 409 do { \ 410 int32_t maxv = (1 << U) - 1; \ 411 int32_t minv = -(1 << U); \ 412 DST = fMIN(maxv, fMAX(SRC, minv)); \ 413 } while (0) 414 #define fCRND(A) ((((A) & 0x3) == 0x3) ? ((A) + 1) : ((A))) 415 #define fRNDN(A, N) ((((N) == 0) ? (A) : (((fSE32_64(A)) + (1 << ((N) - 1)))))) 416 #define fCRNDN(A, N) (conv_round(A, N)) 417 #define fADD128(A, B) (int128_add(A, B)) 418 #define fSUB128(A, B) (int128_sub(A, B)) 419 #define fSHIFTR128(A, B) (int128_rshift(A, B)) 420 #define fSHIFTL128(A, B) (int128_lshift(A, B)) 421 #define fAND128(A, B) (int128_and(A, B)) 422 #define fCAST8S_16S(A) (int128_exts64(A)) 423 #define fCAST16S_8S(A) (int128_getlo(A)) 424 425 #ifdef QEMU_GENERATE 426 #define fEA_RI(REG, IMM) tcg_gen_addi_tl(EA, REG, IMM) 427 #define fEA_RRs(REG, REG2, SCALE) \ 428 do { \ 429 TCGv tmp = tcg_temp_new(); \ 430 tcg_gen_shli_tl(tmp, REG2, SCALE); \ 431 tcg_gen_add_tl(EA, REG, tmp); \ 432 } while (0) 433 #define fEA_IRs(IMM, REG, SCALE) \ 434 do { \ 435 tcg_gen_shli_tl(EA, REG, SCALE); \ 436 tcg_gen_addi_tl(EA, EA, IMM); \ 437 } while (0) 438 #else 439 #define fEA_RI(REG, IMM) \ 440 do { \ 441 EA = REG + IMM; \ 442 } while (0) 443 #define fEA_RRs(REG, REG2, SCALE) \ 444 do { \ 445 EA = REG + (REG2 << SCALE); \ 446 } while (0) 447 #define fEA_IRs(IMM, REG, SCALE) \ 448 do { \ 449 EA = IMM + (REG << SCALE); \ 450 } while (0) 451 #endif 452 453 #ifdef QEMU_GENERATE 454 #define fEA_IMM(IMM) tcg_gen_movi_tl(EA, IMM) 455 #define fEA_REG(REG) tcg_gen_mov_tl(EA, REG) 456 #define fEA_BREVR(REG) gen_helper_fbrev(EA, REG) 457 #define fPM_I(REG, IMM) tcg_gen_addi_tl(REG, REG, IMM) 458 #define fPM_M(REG, MVAL) tcg_gen_add_tl(REG, REG, MVAL) 459 #define fPM_CIRI(REG, IMM, MVAL) \ 460 do { \ 461 TCGv tcgv_siV = tcg_constant_tl(siV); \ 462 gen_helper_fcircadd(REG, REG, tcgv_siV, MuV, CS); \ 463 } while (0) 464 #else 465 #define fEA_IMM(IMM) do { EA = (IMM); } while (0) 466 #define fEA_REG(REG) do { EA = (REG); } while (0) 467 #define fEA_GPI(IMM) do { EA = (fREAD_GP() + (IMM)); } while (0) 468 #define fPM_I(REG, IMM) do { REG = REG + (IMM); } while (0) 469 #define fPM_M(REG, MVAL) do { REG = REG + (MVAL); } while (0) 470 #endif 471 #define fSCALE(N, A) (((int64_t)(A)) << N) 472 #define fVSATW(A) fVSATN(32, ((long long)A)) 473 #define fSATW(A) fSATN(32, ((long long)A)) 474 #define fVSAT(A) fVSATN(32, (A)) 475 #define fSAT(A) fSATN(32, (A)) 476 #define fSAT_ORIG_SHL(A, ORIG_REG) \ 477 ((((int32_t)((fSAT(A)) ^ ((int32_t)(ORIG_REG)))) < 0) \ 478 ? fSATVALN(32, ((int32_t)(ORIG_REG))) \ 479 : ((((ORIG_REG) > 0) && ((A) == 0)) ? fSATVALN(32, (ORIG_REG)) \ 480 : fSAT(A))) 481 #define fPASS(A) A 482 #define fBIDIR_SHIFTL(SRC, SHAMT, REGSTYPE) \ 483 (((SHAMT) < 0) ? ((fCAST##REGSTYPE(SRC) >> ((-(SHAMT)) - 1)) >> 1) \ 484 : (fCAST##REGSTYPE(SRC) << (SHAMT))) 485 #define fBIDIR_ASHIFTL(SRC, SHAMT, REGSTYPE) \ 486 fBIDIR_SHIFTL(SRC, SHAMT, REGSTYPE##s) 487 #define fBIDIR_LSHIFTL(SRC, SHAMT, REGSTYPE) \ 488 fBIDIR_SHIFTL(SRC, SHAMT, REGSTYPE##u) 489 #define fBIDIR_ASHIFTL_SAT(SRC, SHAMT, REGSTYPE) \ 490 (((SHAMT) < 0) ? ((fCAST##REGSTYPE##s(SRC) >> ((-(SHAMT)) - 1)) >> 1) \ 491 : fSAT_ORIG_SHL(fCAST##REGSTYPE##s(SRC) << (SHAMT), (SRC))) 492 #define fBIDIR_SHIFTR(SRC, SHAMT, REGSTYPE) \ 493 (((SHAMT) < 0) ? ((fCAST##REGSTYPE(SRC) << ((-(SHAMT)) - 1)) << 1) \ 494 : (fCAST##REGSTYPE(SRC) >> (SHAMT))) 495 #define fBIDIR_ASHIFTR(SRC, SHAMT, REGSTYPE) \ 496 fBIDIR_SHIFTR(SRC, SHAMT, REGSTYPE##s) 497 #define fBIDIR_LSHIFTR(SRC, SHAMT, REGSTYPE) \ 498 fBIDIR_SHIFTR(SRC, SHAMT, REGSTYPE##u) 499 #define fBIDIR_ASHIFTR_SAT(SRC, SHAMT, REGSTYPE) \ 500 (((SHAMT) < 0) ? fSAT_ORIG_SHL((fCAST##REGSTYPE##s(SRC) \ 501 << ((-(SHAMT)) - 1)) << 1, (SRC)) \ 502 : (fCAST##REGSTYPE##s(SRC) >> (SHAMT))) 503 #define fASHIFTR(SRC, SHAMT, REGSTYPE) (fCAST##REGSTYPE##s(SRC) >> (SHAMT)) 504 #define fLSHIFTR(SRC, SHAMT, REGSTYPE) \ 505 (((SHAMT) >= (sizeof(SRC) * 8)) ? 0 : (fCAST##REGSTYPE##u(SRC) >> (SHAMT))) 506 #define fROTL(SRC, SHAMT, REGSTYPE) \ 507 (((SHAMT) == 0) ? (SRC) : ((fCAST##REGSTYPE##u(SRC) << (SHAMT)) | \ 508 ((fCAST##REGSTYPE##u(SRC) >> \ 509 ((sizeof(SRC) * 8) - (SHAMT)))))) 510 #define fROTR(SRC, SHAMT, REGSTYPE) \ 511 (((SHAMT) == 0) ? (SRC) : ((fCAST##REGSTYPE##u(SRC) >> (SHAMT)) | \ 512 ((fCAST##REGSTYPE##u(SRC) << \ 513 ((sizeof(SRC) * 8) - (SHAMT)))))) 514 #define fASHIFTL(SRC, SHAMT, REGSTYPE) \ 515 (((SHAMT) >= (sizeof(SRC) * 8)) ? 0 : (fCAST##REGSTYPE##s(SRC) << (SHAMT))) 516 517 #ifdef QEMU_GENERATE 518 #define fLOAD(NUM, SIZE, SIGN, EA, DST) MEM_LOAD##SIZE##SIGN(DST, EA) 519 #else 520 #define MEM_LOAD1 cpu_ldub_data_ra 521 #define MEM_LOAD2 cpu_lduw_data_ra 522 #define MEM_LOAD4 cpu_ldl_data_ra 523 #define MEM_LOAD8 cpu_ldq_data_ra 524 525 #define fLOAD(NUM, SIZE, SIGN, EA, DST) \ 526 do { \ 527 check_noshuf(env, pkt_has_store_s1, slot, EA, SIZE, GETPC()); \ 528 DST = (size##SIZE##SIGN##_t)MEM_LOAD##SIZE(env, EA, GETPC()); \ 529 } while (0) 530 #endif 531 532 #define fMEMOP(NUM, SIZE, SIGN, EA, FNTYPE, VALUE) 533 534 #define fGET_FRAMEKEY() (env->gpr[HEX_REG_FRAMEKEY]) 535 #define fFRAME_SCRAMBLE(VAL) ((VAL) ^ (fCAST8u(fGET_FRAMEKEY()) << 32)) 536 #define fFRAME_UNSCRAMBLE(VAL) fFRAME_SCRAMBLE(VAL) 537 538 #ifdef CONFIG_USER_ONLY 539 #define fFRAMECHECK(ADDR, EA) do { } while (0) /* Not modelled in linux-user */ 540 #else 541 /* System mode not implemented yet */ 542 #define fFRAMECHECK(ADDR, EA) g_assert_not_reached(); 543 #endif 544 545 #ifdef QEMU_GENERATE 546 #define fLOAD_LOCKED(NUM, SIZE, SIGN, EA, DST) \ 547 gen_load_locked##SIZE##SIGN(DST, EA, ctx->mem_idx); 548 #endif 549 550 #ifdef QEMU_GENERATE 551 #define fSTORE(NUM, SIZE, EA, SRC) MEM_STORE##SIZE(EA, SRC, insn->slot) 552 #else 553 #define fSTORE(NUM, SIZE, EA, SRC) MEM_STORE##SIZE(EA, SRC, slot) 554 #endif 555 556 #ifdef QEMU_GENERATE 557 #define fSTORE_LOCKED(NUM, SIZE, EA, SRC, PRED) \ 558 gen_store_conditional##SIZE(ctx, PRED, EA, SRC); 559 #endif 560 561 #ifdef QEMU_GENERATE 562 #define GETBYTE_FUNC(X) \ 563 __builtin_choose_expr(TYPE_TCGV(X), \ 564 gen_get_byte, \ 565 __builtin_choose_expr(TYPE_TCGV_I64(X), \ 566 gen_get_byte_i64, (void)0)) 567 #define fGETBYTE(N, SRC) GETBYTE_FUNC(SRC)(BYTE, N, SRC, true) 568 #define fGETUBYTE(N, SRC) GETBYTE_FUNC(SRC)(BYTE, N, SRC, false) 569 #else 570 #define fGETBYTE(N, SRC) ((int8_t)((SRC >> ((N) * 8)) & 0xff)) 571 #define fGETUBYTE(N, SRC) ((uint8_t)((SRC >> ((N) * 8)) & 0xff)) 572 #endif 573 574 #define fSETBYTE(N, DST, VAL) \ 575 do { \ 576 DST = (DST & ~(0x0ffLL << ((N) * 8))) | \ 577 (((uint64_t)((VAL) & 0x0ffLL)) << ((N) * 8)); \ 578 } while (0) 579 580 #ifdef QEMU_GENERATE 581 #define fGETHALF(N, SRC) gen_get_half(HALF, N, SRC, true) 582 #define fGETUHALF(N, SRC) gen_get_half(HALF, N, SRC, false) 583 #else 584 #define fGETHALF(N, SRC) ((int16_t)((SRC >> ((N) * 16)) & 0xffff)) 585 #define fGETUHALF(N, SRC) ((uint16_t)((SRC >> ((N) * 16)) & 0xffff)) 586 #endif 587 #define fSETHALF(N, DST, VAL) \ 588 do { \ 589 DST = (DST & ~(0x0ffffLL << ((N) * 16))) | \ 590 (((uint64_t)((VAL) & 0x0ffff)) << ((N) * 16)); \ 591 } while (0) 592 #define fSETHALFw fSETHALF 593 #define fSETHALFd fSETHALF 594 595 #define fGETWORD(N, SRC) \ 596 ((int64_t)((int32_t)((SRC >> ((N) * 32)) & 0x0ffffffffLL))) 597 #define fGETUWORD(N, SRC) \ 598 ((uint64_t)((uint32_t)((SRC >> ((N) * 32)) & 0x0ffffffffLL))) 599 600 #define fSETWORD(N, DST, VAL) \ 601 do { \ 602 DST = (DST & ~(0x0ffffffffLL << ((N) * 32))) | \ 603 (((VAL) & 0x0ffffffffLL) << ((N) * 32)); \ 604 } while (0) 605 606 #define fSETBIT(N, DST, VAL) \ 607 do { \ 608 DST = (DST & ~(1ULL << (N))) | (((uint64_t)(VAL)) << (N)); \ 609 } while (0) 610 611 #define fGETBIT(N, SRC) (((SRC) >> N) & 1) 612 #define fSETBITS(HI, LO, DST, VAL) \ 613 do { \ 614 int j; \ 615 for (j = LO; j <= HI; j++) { \ 616 fSETBIT(j, DST, VAL); \ 617 } \ 618 } while (0) 619 #define fCOUNTONES_2(VAL) ctpop16(VAL) 620 #define fCOUNTONES_4(VAL) ctpop32(VAL) 621 #define fCOUNTONES_8(VAL) ctpop64(VAL) 622 #define fBREV_8(VAL) revbit64(VAL) 623 #define fBREV_4(VAL) revbit32(VAL) 624 #define fCL1_8(VAL) clo64(VAL) 625 #define fCL1_4(VAL) clo32(VAL) 626 #define fCL1_2(VAL) (clz32(~(uint16_t)(VAL) & 0xffff) - 16) 627 #define fINTERLEAVE(ODD, EVEN) interleave(ODD, EVEN) 628 #define fDEINTERLEAVE(MIXED) deinterleave(MIXED) 629 #define fHIDE(A) A 630 #define fCONSTLL(A) A##LL 631 #define fECHO(A) (A) 632 633 #define fTRAP(TRAPTYPE, IMM) helper_raise_exception(env, HEX_EXCP_TRAP0) 634 #define fPAUSE(IMM) 635 636 #define fALIGN_REG_FIELD_VALUE(FIELD, VAL) \ 637 ((VAL) << reg_field_info[FIELD].offset) 638 #define fGET_REG_FIELD_MASK(FIELD) \ 639 (((1 << reg_field_info[FIELD].width) - 1) << reg_field_info[FIELD].offset) 640 #define fREAD_REG_FIELD(REG, FIELD) \ 641 fEXTRACTU_BITS(env->gpr[HEX_REG_##REG], \ 642 reg_field_info[FIELD].width, \ 643 reg_field_info[FIELD].offset) 644 645 #ifdef QEMU_GENERATE 646 #define fDCZEROA(REG) \ 647 do { \ 648 ctx->dczero_addr = tcg_temp_new(); \ 649 tcg_gen_mov_tl(ctx->dczero_addr, (REG)); \ 650 } while (0) 651 #endif 652 653 #define fBRANCH_SPECULATE_STALL(DOTNEWVAL, JUMP_COND, SPEC_DIR, HINTBITNUM, \ 654 STRBITNUM) /* Nothing */ 655 656 657 #endif 658