1 /* 2 * Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #ifndef HEXAGON_MACROS_H 19 #define HEXAGON_MACROS_H 20 21 #include "cpu.h" 22 #include "hex_regs.h" 23 #include "reg_fields.h" 24 25 #ifdef QEMU_GENERATE 26 #define READ_REG(dest, NUM) gen_read_reg(dest, NUM) 27 #define READ_PREG(dest, NUM) gen_read_preg(dest, (NUM)) 28 #else 29 #define READ_REG(NUM) (env->gpr[(NUM)]) 30 #define READ_PREG(NUM) (env->pred[NUM]) 31 32 #define WRITE_RREG(NUM, VAL) log_reg_write(env, NUM, VAL, slot) 33 #define WRITE_PREG(NUM, VAL) log_pred_write(env, NUM, VAL) 34 #endif 35 36 #define PCALIGN 4 37 #define PCALIGN_MASK (PCALIGN - 1) 38 39 #define GET_FIELD(FIELD, REGIN) \ 40 fEXTRACTU_BITS(REGIN, reg_field_info[FIELD].width, \ 41 reg_field_info[FIELD].offset) 42 43 #ifdef QEMU_GENERATE 44 #define GET_USR_FIELD(FIELD, DST) \ 45 tcg_gen_extract_tl(DST, hex_gpr[HEX_REG_USR], \ 46 reg_field_info[FIELD].offset, \ 47 reg_field_info[FIELD].width) 48 49 #define TYPE_INT(X) __builtin_types_compatible_p(typeof(X), int) 50 #define TYPE_TCGV(X) __builtin_types_compatible_p(typeof(X), TCGv) 51 #define TYPE_TCGV_I64(X) __builtin_types_compatible_p(typeof(X), TCGv_i64) 52 53 #define SET_USR_FIELD_FUNC(X) \ 54 __builtin_choose_expr(TYPE_INT(X), \ 55 gen_set_usr_fieldi, \ 56 __builtin_choose_expr(TYPE_TCGV(X), \ 57 gen_set_usr_field, (void)0)) 58 #define SET_USR_FIELD(FIELD, VAL) \ 59 SET_USR_FIELD_FUNC(VAL)(FIELD, VAL) 60 #else 61 #define GET_USR_FIELD(FIELD) \ 62 fEXTRACTU_BITS(env->gpr[HEX_REG_USR], reg_field_info[FIELD].width, \ 63 reg_field_info[FIELD].offset) 64 65 #define SET_USR_FIELD(FIELD, VAL) \ 66 fINSERT_BITS(env->gpr[HEX_REG_USR], reg_field_info[FIELD].width, \ 67 reg_field_info[FIELD].offset, (VAL)) 68 #endif 69 70 #ifdef QEMU_GENERATE 71 /* 72 * Section 5.5 of the Hexagon V67 Programmer's Reference Manual 73 * 74 * Slot 1 store with slot 0 load 75 * A slot 1 store operation with a slot 0 load operation can appear in a packet. 76 * The packet attribute :mem_noshuf inhibits the instruction reordering that 77 * would otherwise be done by the assembler. For example: 78 * { 79 * memw(R5) = R2 // slot 1 store 80 * R3 = memh(R6) // slot 0 load 81 * }:mem_noshuf 82 * Unlike most packetized operations, these memory operations are not executed 83 * in parallel (Section 3.3.1). Instead, the store instruction in Slot 1 84 * effectively executes first, followed by the load instruction in Slot 0. If 85 * the addresses of the two operations are overlapping, the load will receive 86 * the newly stored data. This feature is supported in processor versions 87 * V65 or greater. 88 * 89 * 90 * For qemu, we look for a load in slot 0 when there is a store in slot 1 91 * in the same packet. When we see this, we call a helper that merges the 92 * bytes from the store buffer with the value loaded from memory. 93 */ 94 #define CHECK_NOSHUF \ 95 do { \ 96 if (insn->slot == 0 && pkt->pkt_has_store_s1) { \ 97 process_store(ctx, pkt, 1); \ 98 } \ 99 } while (0) 100 101 #define MEM_LOAD1s(DST, VA) \ 102 do { \ 103 CHECK_NOSHUF; \ 104 tcg_gen_qemu_ld8s(DST, VA, ctx->mem_idx); \ 105 } while (0) 106 #define MEM_LOAD1u(DST, VA) \ 107 do { \ 108 CHECK_NOSHUF; \ 109 tcg_gen_qemu_ld8u(DST, VA, ctx->mem_idx); \ 110 } while (0) 111 #define MEM_LOAD2s(DST, VA) \ 112 do { \ 113 CHECK_NOSHUF; \ 114 tcg_gen_qemu_ld16s(DST, VA, ctx->mem_idx); \ 115 } while (0) 116 #define MEM_LOAD2u(DST, VA) \ 117 do { \ 118 CHECK_NOSHUF; \ 119 tcg_gen_qemu_ld16u(DST, VA, ctx->mem_idx); \ 120 } while (0) 121 #define MEM_LOAD4s(DST, VA) \ 122 do { \ 123 CHECK_NOSHUF; \ 124 tcg_gen_qemu_ld32s(DST, VA, ctx->mem_idx); \ 125 } while (0) 126 #define MEM_LOAD4u(DST, VA) \ 127 do { \ 128 CHECK_NOSHUF; \ 129 tcg_gen_qemu_ld32s(DST, VA, ctx->mem_idx); \ 130 } while (0) 131 #define MEM_LOAD8u(DST, VA) \ 132 do { \ 133 CHECK_NOSHUF; \ 134 tcg_gen_qemu_ld64(DST, VA, ctx->mem_idx); \ 135 } while (0) 136 137 #define MEM_STORE1_FUNC(X) \ 138 __builtin_choose_expr(TYPE_INT(X), \ 139 gen_store1i, \ 140 __builtin_choose_expr(TYPE_TCGV(X), \ 141 gen_store1, (void)0)) 142 #define MEM_STORE1(VA, DATA, SLOT) \ 143 MEM_STORE1_FUNC(DATA)(cpu_env, VA, DATA, ctx, SLOT) 144 145 #define MEM_STORE2_FUNC(X) \ 146 __builtin_choose_expr(TYPE_INT(X), \ 147 gen_store2i, \ 148 __builtin_choose_expr(TYPE_TCGV(X), \ 149 gen_store2, (void)0)) 150 #define MEM_STORE2(VA, DATA, SLOT) \ 151 MEM_STORE2_FUNC(DATA)(cpu_env, VA, DATA, ctx, SLOT) 152 153 #define MEM_STORE4_FUNC(X) \ 154 __builtin_choose_expr(TYPE_INT(X), \ 155 gen_store4i, \ 156 __builtin_choose_expr(TYPE_TCGV(X), \ 157 gen_store4, (void)0)) 158 #define MEM_STORE4(VA, DATA, SLOT) \ 159 MEM_STORE4_FUNC(DATA)(cpu_env, VA, DATA, ctx, SLOT) 160 161 #define MEM_STORE8_FUNC(X) \ 162 __builtin_choose_expr(TYPE_INT(X), \ 163 gen_store8i, \ 164 __builtin_choose_expr(TYPE_TCGV_I64(X), \ 165 gen_store8, (void)0)) 166 #define MEM_STORE8(VA, DATA, SLOT) \ 167 MEM_STORE8_FUNC(DATA)(cpu_env, VA, DATA, ctx, SLOT) 168 #else 169 #define MEM_LOAD1s(VA) ((int8_t)mem_load1(env, slot, VA)) 170 #define MEM_LOAD1u(VA) ((uint8_t)mem_load1(env, slot, VA)) 171 #define MEM_LOAD2s(VA) ((int16_t)mem_load2(env, slot, VA)) 172 #define MEM_LOAD2u(VA) ((uint16_t)mem_load2(env, slot, VA)) 173 #define MEM_LOAD4s(VA) ((int32_t)mem_load4(env, slot, VA)) 174 #define MEM_LOAD4u(VA) ((uint32_t)mem_load4(env, slot, VA)) 175 #define MEM_LOAD8s(VA) ((int64_t)mem_load8(env, slot, VA)) 176 #define MEM_LOAD8u(VA) ((uint64_t)mem_load8(env, slot, VA)) 177 178 #define MEM_STORE1(VA, DATA, SLOT) log_store32(env, VA, DATA, 1, SLOT) 179 #define MEM_STORE2(VA, DATA, SLOT) log_store32(env, VA, DATA, 2, SLOT) 180 #define MEM_STORE4(VA, DATA, SLOT) log_store32(env, VA, DATA, 4, SLOT) 181 #define MEM_STORE8(VA, DATA, SLOT) log_store64(env, VA, DATA, 8, SLOT) 182 #endif 183 184 #define CANCEL cancel_slot(env, slot) 185 186 #define LOAD_CANCEL(EA) do { CANCEL; } while (0) 187 188 #ifdef QEMU_GENERATE 189 static inline void gen_pred_cancel(TCGv pred, int slot_num) 190 { 191 TCGv slot_mask = tcg_const_tl(1 << slot_num); 192 TCGv tmp = tcg_temp_new(); 193 TCGv zero = tcg_const_tl(0); 194 TCGv one = tcg_const_tl(1); 195 tcg_gen_or_tl(slot_mask, hex_slot_cancelled, slot_mask); 196 tcg_gen_andi_tl(tmp, pred, 1); 197 tcg_gen_movcond_tl(TCG_COND_EQ, hex_slot_cancelled, tmp, zero, 198 slot_mask, hex_slot_cancelled); 199 tcg_temp_free(slot_mask); 200 tcg_temp_free(tmp); 201 tcg_temp_free(zero); 202 tcg_temp_free(one); 203 } 204 #define PRED_LOAD_CANCEL(PRED, EA) \ 205 gen_pred_cancel(PRED, insn->is_endloop ? 4 : insn->slot) 206 #endif 207 208 #define STORE_CANCEL(EA) { env->slot_cancelled |= (1 << slot); } 209 210 #define fMAX(A, B) (((A) > (B)) ? (A) : (B)) 211 212 #define fMIN(A, B) (((A) < (B)) ? (A) : (B)) 213 214 #define fABS(A) (((A) < 0) ? (-(A)) : (A)) 215 #define fINSERT_BITS(REG, WIDTH, OFFSET, INVAL) \ 216 REG = ((WIDTH) ? deposit64(REG, (OFFSET), (WIDTH), (INVAL)) : REG) 217 #define fEXTRACTU_BITS(INREG, WIDTH, OFFSET) \ 218 ((WIDTH) ? extract64((INREG), (OFFSET), (WIDTH)) : 0LL) 219 #define fEXTRACTU_BIDIR(INREG, WIDTH, OFFSET) \ 220 (fZXTN(WIDTH, 32, fBIDIR_LSHIFTR((INREG), (OFFSET), 4_8))) 221 #define fEXTRACTU_RANGE(INREG, HIBIT, LOWBIT) \ 222 (((HIBIT) - (LOWBIT) + 1) ? \ 223 extract64((INREG), (LOWBIT), ((HIBIT) - (LOWBIT) + 1)) : \ 224 0LL) 225 #define fINSERT_RANGE(INREG, HIBIT, LOWBIT, INVAL) \ 226 do { \ 227 int width = ((HIBIT) - (LOWBIT) + 1); \ 228 INREG = (width >= 0 ? \ 229 deposit64((INREG), (LOWBIT), width, (INVAL)) : \ 230 INREG); \ 231 } while (0) 232 233 #define f8BITSOF(VAL) ((VAL) ? 0xff : 0x00) 234 235 #ifdef QEMU_GENERATE 236 #define fLSBOLD(VAL) tcg_gen_andi_tl(LSB, (VAL), 1) 237 #else 238 #define fLSBOLD(VAL) ((VAL) & 1) 239 #endif 240 241 #ifdef QEMU_GENERATE 242 #define fLSBNEW(PVAL) tcg_gen_mov_tl(LSB, (PVAL)) 243 #define fLSBNEW0 tcg_gen_mov_tl(LSB, hex_new_pred_value[0]) 244 #define fLSBNEW1 tcg_gen_mov_tl(LSB, hex_new_pred_value[1]) 245 #else 246 #define fLSBNEW(PVAL) (PVAL) 247 #define fLSBNEW0 new_pred_value(env, 0) 248 #define fLSBNEW1 new_pred_value(env, 1) 249 #endif 250 251 #ifdef QEMU_GENERATE 252 static inline void gen_logical_not(TCGv dest, TCGv src) 253 { 254 TCGv one = tcg_const_tl(1); 255 TCGv zero = tcg_const_tl(0); 256 257 tcg_gen_movcond_tl(TCG_COND_NE, dest, src, zero, zero, one); 258 259 tcg_temp_free(one); 260 tcg_temp_free(zero); 261 } 262 #define fLSBOLDNOT(VAL) \ 263 do { \ 264 tcg_gen_andi_tl(LSB, (VAL), 1); \ 265 tcg_gen_xori_tl(LSB, LSB, 1); \ 266 } while (0) 267 #define fLSBNEWNOT(PNUM) \ 268 gen_logical_not(LSB, (PNUM)) 269 #else 270 #define fLSBNEWNOT(PNUM) (!fLSBNEW(PNUM)) 271 #define fLSBOLDNOT(VAL) (!fLSBOLD(VAL)) 272 #define fLSBNEW0NOT (!fLSBNEW0) 273 #define fLSBNEW1NOT (!fLSBNEW1) 274 #endif 275 276 #define fNEWREG(VAL) ((int32_t)(VAL)) 277 278 #define fNEWREG_ST(VAL) (VAL) 279 280 #define fSATUVALN(N, VAL) \ 281 ({ \ 282 fSET_OVERFLOW(); \ 283 ((VAL) < 0) ? 0 : ((1LL << (N)) - 1); \ 284 }) 285 #define fSATVALN(N, VAL) \ 286 ({ \ 287 fSET_OVERFLOW(); \ 288 ((VAL) < 0) ? (-(1LL << ((N) - 1))) : ((1LL << ((N) - 1)) - 1); \ 289 }) 290 #define fZXTN(N, M, VAL) (((N) != 0) ? extract64((VAL), 0, (N)) : 0LL) 291 #define fSXTN(N, M, VAL) (((N) != 0) ? sextract64((VAL), 0, (N)) : 0LL) 292 #define fSATN(N, VAL) \ 293 ((fSXTN(N, 64, VAL) == (VAL)) ? (VAL) : fSATVALN(N, VAL)) 294 #define fADDSAT64(DST, A, B) \ 295 do { \ 296 uint64_t __a = fCAST8u(A); \ 297 uint64_t __b = fCAST8u(B); \ 298 uint64_t __sum = __a + __b; \ 299 uint64_t __xor = __a ^ __b; \ 300 const uint64_t __mask = 0x8000000000000000ULL; \ 301 if (__xor & __mask) { \ 302 DST = __sum; \ 303 } \ 304 else if ((__a ^ __sum) & __mask) { \ 305 if (__sum & __mask) { \ 306 DST = 0x7FFFFFFFFFFFFFFFLL; \ 307 fSET_OVERFLOW(); \ 308 } else { \ 309 DST = 0x8000000000000000LL; \ 310 fSET_OVERFLOW(); \ 311 } \ 312 } else { \ 313 DST = __sum; \ 314 } \ 315 } while (0) 316 #define fSATUN(N, VAL) \ 317 ((fZXTN(N, 64, VAL) == (VAL)) ? (VAL) : fSATUVALN(N, VAL)) 318 #define fSATH(VAL) (fSATN(16, VAL)) 319 #define fSATUH(VAL) (fSATUN(16, VAL)) 320 #define fSATUB(VAL) (fSATUN(8, VAL)) 321 #define fSATB(VAL) (fSATN(8, VAL)) 322 #define fIMMEXT(IMM) (IMM = IMM) 323 #define fMUST_IMMEXT(IMM) fIMMEXT(IMM) 324 325 #define fPCALIGN(IMM) IMM = (IMM & ~PCALIGN_MASK) 326 327 #ifdef QEMU_GENERATE 328 static inline TCGv gen_read_ireg(TCGv result, TCGv val, int shift) 329 { 330 /* 331 * Section 2.2.4 of the Hexagon V67 Programmer's Reference Manual 332 * 333 * The "I" value from a modifier register is divided into two pieces 334 * LSB bits 23:17 335 * MSB bits 31:28 336 * The value is signed 337 * 338 * At the end we shift the result according to the shift argument 339 */ 340 TCGv msb = tcg_temp_new(); 341 TCGv lsb = tcg_temp_new(); 342 343 tcg_gen_extract_tl(lsb, val, 17, 7); 344 tcg_gen_sari_tl(msb, val, 21); 345 tcg_gen_deposit_tl(result, msb, lsb, 0, 7); 346 347 tcg_gen_shli_tl(result, result, shift); 348 349 tcg_temp_free(msb); 350 tcg_temp_free(lsb); 351 352 return result; 353 } 354 #define fREAD_IREG(VAL, SHIFT) gen_read_ireg(ireg, (VAL), (SHIFT)) 355 #else 356 #define fREAD_IREG(VAL) \ 357 (fSXTN(11, 64, (((VAL) & 0xf0000000) >> 21) | ((VAL >> 17) & 0x7f))) 358 #endif 359 360 #define fREAD_LR() (READ_REG(HEX_REG_LR)) 361 362 #define fWRITE_LR(A) WRITE_RREG(HEX_REG_LR, A) 363 #define fWRITE_FP(A) WRITE_RREG(HEX_REG_FP, A) 364 #define fWRITE_SP(A) WRITE_RREG(HEX_REG_SP, A) 365 366 #define fREAD_SP() (READ_REG(HEX_REG_SP)) 367 #define fREAD_LC0 (READ_REG(HEX_REG_LC0)) 368 #define fREAD_LC1 (READ_REG(HEX_REG_LC1)) 369 #define fREAD_SA0 (READ_REG(HEX_REG_SA0)) 370 #define fREAD_SA1 (READ_REG(HEX_REG_SA1)) 371 #define fREAD_FP() (READ_REG(HEX_REG_FP)) 372 #ifdef FIXME 373 /* Figure out how to get insn->extension_valid to helper */ 374 #define fREAD_GP() \ 375 (insn->extension_valid ? 0 : READ_REG(HEX_REG_GP)) 376 #else 377 #define fREAD_GP() READ_REG(HEX_REG_GP) 378 #endif 379 #define fREAD_PC() (READ_REG(HEX_REG_PC)) 380 381 #define fREAD_NPC() (env->next_PC & (0xfffffffe)) 382 383 #define fREAD_P0() (READ_PREG(0)) 384 #define fREAD_P3() (READ_PREG(3)) 385 386 #define fCHECK_PCALIGN(A) 387 388 #define fWRITE_NPC(A) write_new_pc(env, A) 389 390 #define fBRANCH(LOC, TYPE) fWRITE_NPC(LOC) 391 #define fJUMPR(REGNO, TARGET, TYPE) fBRANCH(TARGET, COF_TYPE_JUMPR) 392 #define fHINTJR(TARGET) { /* Not modelled in qemu */} 393 #define fCALL(A) \ 394 do { \ 395 fWRITE_LR(fREAD_NPC()); \ 396 fBRANCH(A, COF_TYPE_CALL); \ 397 } while (0) 398 #define fCALLR(A) \ 399 do { \ 400 fWRITE_LR(fREAD_NPC()); \ 401 fBRANCH(A, COF_TYPE_CALLR); \ 402 } while (0) 403 #define fWRITE_LOOP_REGS0(START, COUNT) \ 404 do { \ 405 WRITE_RREG(HEX_REG_LC0, COUNT); \ 406 WRITE_RREG(HEX_REG_SA0, START); \ 407 } while (0) 408 #define fWRITE_LOOP_REGS1(START, COUNT) \ 409 do { \ 410 WRITE_RREG(HEX_REG_LC1, COUNT); \ 411 WRITE_RREG(HEX_REG_SA1, START);\ 412 } while (0) 413 #define fWRITE_LC0(VAL) WRITE_RREG(HEX_REG_LC0, VAL) 414 #define fWRITE_LC1(VAL) WRITE_RREG(HEX_REG_LC1, VAL) 415 416 #define fSET_OVERFLOW() SET_USR_FIELD(USR_OVF, 1) 417 #define fSET_LPCFG(VAL) SET_USR_FIELD(USR_LPCFG, (VAL)) 418 #define fGET_LPCFG (GET_USR_FIELD(USR_LPCFG)) 419 #define fWRITE_P0(VAL) WRITE_PREG(0, VAL) 420 #define fWRITE_P1(VAL) WRITE_PREG(1, VAL) 421 #define fWRITE_P2(VAL) WRITE_PREG(2, VAL) 422 #define fWRITE_P3(VAL) WRITE_PREG(3, VAL) 423 #define fPART1(WORK) if (part1) { WORK; return; } 424 #define fCAST4u(A) ((uint32_t)(A)) 425 #define fCAST4s(A) ((int32_t)(A)) 426 #define fCAST8u(A) ((uint64_t)(A)) 427 #define fCAST8s(A) ((int64_t)(A)) 428 #define fCAST4_4s(A) ((int32_t)(A)) 429 #define fCAST4_4u(A) ((uint32_t)(A)) 430 #define fCAST4_8s(A) ((int64_t)((int32_t)(A))) 431 #define fCAST4_8u(A) ((uint64_t)((uint32_t)(A))) 432 #define fCAST8_8s(A) ((int64_t)(A)) 433 #define fCAST8_8u(A) ((uint64_t)(A)) 434 #define fCAST2_8s(A) ((int64_t)((int16_t)(A))) 435 #define fCAST2_8u(A) ((uint64_t)((uint16_t)(A))) 436 #define fZE8_16(A) ((int16_t)((uint8_t)(A))) 437 #define fSE8_16(A) ((int16_t)((int8_t)(A))) 438 #define fSE16_32(A) ((int32_t)((int16_t)(A))) 439 #define fZE16_32(A) ((uint32_t)((uint16_t)(A))) 440 #define fSE32_64(A) ((int64_t)((int32_t)(A))) 441 #define fZE32_64(A) ((uint64_t)((uint32_t)(A))) 442 #define fSE8_32(A) ((int32_t)((int8_t)(A))) 443 #define fZE8_32(A) ((int32_t)((uint8_t)(A))) 444 #define fMPY8UU(A, B) (int)(fZE8_16(A) * fZE8_16(B)) 445 #define fMPY8US(A, B) (int)(fZE8_16(A) * fSE8_16(B)) 446 #define fMPY8SU(A, B) (int)(fSE8_16(A) * fZE8_16(B)) 447 #define fMPY8SS(A, B) (int)((short)(A) * (short)(B)) 448 #define fMPY16SS(A, B) fSE32_64(fSE16_32(A) * fSE16_32(B)) 449 #define fMPY16UU(A, B) fZE32_64(fZE16_32(A) * fZE16_32(B)) 450 #define fMPY16SU(A, B) fSE32_64(fSE16_32(A) * fZE16_32(B)) 451 #define fMPY16US(A, B) fMPY16SU(B, A) 452 #define fMPY32SS(A, B) (fSE32_64(A) * fSE32_64(B)) 453 #define fMPY32UU(A, B) (fZE32_64(A) * fZE32_64(B)) 454 #define fMPY32SU(A, B) (fSE32_64(A) * fZE32_64(B)) 455 #define fMPY3216SS(A, B) (fSE32_64(A) * fSXTN(16, 64, B)) 456 #define fMPY3216SU(A, B) (fSE32_64(A) * fZXTN(16, 64, B)) 457 #define fROUND(A) (A + 0x8000) 458 #define fCLIP(DST, SRC, U) \ 459 do { \ 460 int32_t maxv = (1 << U) - 1; \ 461 int32_t minv = -(1 << U); \ 462 DST = fMIN(maxv, fMAX(SRC, minv)); \ 463 } while (0) 464 #define fCRND(A) ((((A) & 0x3) == 0x3) ? ((A) + 1) : ((A))) 465 #define fRNDN(A, N) ((((N) == 0) ? (A) : (((fSE32_64(A)) + (1 << ((N) - 1)))))) 466 #define fCRNDN(A, N) (conv_round(A, N)) 467 #define fADD128(A, B) (int128_add(A, B)) 468 #define fSUB128(A, B) (int128_sub(A, B)) 469 #define fSHIFTR128(A, B) (int128_rshift(A, B)) 470 #define fSHIFTL128(A, B) (int128_lshift(A, B)) 471 #define fAND128(A, B) (int128_and(A, B)) 472 #define fCAST8S_16S(A) (int128_exts64(A)) 473 #define fCAST16S_8S(A) (int128_getlo(A)) 474 475 #ifdef QEMU_GENERATE 476 #define fEA_RI(REG, IMM) tcg_gen_addi_tl(EA, REG, IMM) 477 #define fEA_RRs(REG, REG2, SCALE) \ 478 do { \ 479 TCGv tmp = tcg_temp_new(); \ 480 tcg_gen_shli_tl(tmp, REG2, SCALE); \ 481 tcg_gen_add_tl(EA, REG, tmp); \ 482 tcg_temp_free(tmp); \ 483 } while (0) 484 #define fEA_IRs(IMM, REG, SCALE) \ 485 do { \ 486 tcg_gen_shli_tl(EA, REG, SCALE); \ 487 tcg_gen_addi_tl(EA, EA, IMM); \ 488 } while (0) 489 #else 490 #define fEA_RI(REG, IMM) \ 491 do { \ 492 EA = REG + IMM; \ 493 } while (0) 494 #define fEA_RRs(REG, REG2, SCALE) \ 495 do { \ 496 EA = REG + (REG2 << SCALE); \ 497 } while (0) 498 #define fEA_IRs(IMM, REG, SCALE) \ 499 do { \ 500 EA = IMM + (REG << SCALE); \ 501 } while (0) 502 #endif 503 504 #ifdef QEMU_GENERATE 505 #define fEA_IMM(IMM) tcg_gen_movi_tl(EA, IMM) 506 #define fEA_REG(REG) tcg_gen_mov_tl(EA, REG) 507 #define fEA_BREVR(REG) gen_helper_fbrev(EA, REG) 508 #define fPM_I(REG, IMM) tcg_gen_addi_tl(REG, REG, IMM) 509 #define fPM_M(REG, MVAL) tcg_gen_add_tl(REG, REG, MVAL) 510 #define fPM_CIRI(REG, IMM, MVAL) \ 511 do { \ 512 TCGv tcgv_siV = tcg_const_tl(siV); \ 513 gen_helper_fcircadd(REG, REG, tcgv_siV, MuV, \ 514 hex_gpr[HEX_REG_CS0 + MuN]); \ 515 tcg_temp_free(tcgv_siV); \ 516 } while (0) 517 #else 518 #define fEA_IMM(IMM) do { EA = (IMM); } while (0) 519 #define fEA_REG(REG) do { EA = (REG); } while (0) 520 #define fEA_GPI(IMM) do { EA = (fREAD_GP() + (IMM)); } while (0) 521 #define fPM_I(REG, IMM) do { REG = REG + (IMM); } while (0) 522 #define fPM_M(REG, MVAL) do { REG = REG + (MVAL); } while (0) 523 #endif 524 #define fSCALE(N, A) (((int64_t)(A)) << N) 525 #define fSATW(A) fSATN(32, ((long long)A)) 526 #define fSAT(A) fSATN(32, (A)) 527 #define fSAT_ORIG_SHL(A, ORIG_REG) \ 528 ((((int32_t)((fSAT(A)) ^ ((int32_t)(ORIG_REG)))) < 0) \ 529 ? fSATVALN(32, ((int32_t)(ORIG_REG))) \ 530 : ((((ORIG_REG) > 0) && ((A) == 0)) ? fSATVALN(32, (ORIG_REG)) \ 531 : fSAT(A))) 532 #define fPASS(A) A 533 #define fBIDIR_SHIFTL(SRC, SHAMT, REGSTYPE) \ 534 (((SHAMT) < 0) ? ((fCAST##REGSTYPE(SRC) >> ((-(SHAMT)) - 1)) >> 1) \ 535 : (fCAST##REGSTYPE(SRC) << (SHAMT))) 536 #define fBIDIR_ASHIFTL(SRC, SHAMT, REGSTYPE) \ 537 fBIDIR_SHIFTL(SRC, SHAMT, REGSTYPE##s) 538 #define fBIDIR_LSHIFTL(SRC, SHAMT, REGSTYPE) \ 539 fBIDIR_SHIFTL(SRC, SHAMT, REGSTYPE##u) 540 #define fBIDIR_ASHIFTL_SAT(SRC, SHAMT, REGSTYPE) \ 541 (((SHAMT) < 0) ? ((fCAST##REGSTYPE##s(SRC) >> ((-(SHAMT)) - 1)) >> 1) \ 542 : fSAT_ORIG_SHL(fCAST##REGSTYPE##s(SRC) << (SHAMT), (SRC))) 543 #define fBIDIR_SHIFTR(SRC, SHAMT, REGSTYPE) \ 544 (((SHAMT) < 0) ? ((fCAST##REGSTYPE(SRC) << ((-(SHAMT)) - 1)) << 1) \ 545 : (fCAST##REGSTYPE(SRC) >> (SHAMT))) 546 #define fBIDIR_ASHIFTR(SRC, SHAMT, REGSTYPE) \ 547 fBIDIR_SHIFTR(SRC, SHAMT, REGSTYPE##s) 548 #define fBIDIR_LSHIFTR(SRC, SHAMT, REGSTYPE) \ 549 fBIDIR_SHIFTR(SRC, SHAMT, REGSTYPE##u) 550 #define fBIDIR_ASHIFTR_SAT(SRC, SHAMT, REGSTYPE) \ 551 (((SHAMT) < 0) ? fSAT_ORIG_SHL((fCAST##REGSTYPE##s(SRC) \ 552 << ((-(SHAMT)) - 1)) << 1, (SRC)) \ 553 : (fCAST##REGSTYPE##s(SRC) >> (SHAMT))) 554 #define fASHIFTR(SRC, SHAMT, REGSTYPE) (fCAST##REGSTYPE##s(SRC) >> (SHAMT)) 555 #define fLSHIFTR(SRC, SHAMT, REGSTYPE) \ 556 (((SHAMT) >= (sizeof(SRC) * 8)) ? 0 : (fCAST##REGSTYPE##u(SRC) >> (SHAMT))) 557 #define fROTL(SRC, SHAMT, REGSTYPE) \ 558 (((SHAMT) == 0) ? (SRC) : ((fCAST##REGSTYPE##u(SRC) << (SHAMT)) | \ 559 ((fCAST##REGSTYPE##u(SRC) >> \ 560 ((sizeof(SRC) * 8) - (SHAMT)))))) 561 #define fROTR(SRC, SHAMT, REGSTYPE) \ 562 (((SHAMT) == 0) ? (SRC) : ((fCAST##REGSTYPE##u(SRC) >> (SHAMT)) | \ 563 ((fCAST##REGSTYPE##u(SRC) << \ 564 ((sizeof(SRC) * 8) - (SHAMT)))))) 565 #define fASHIFTL(SRC, SHAMT, REGSTYPE) \ 566 (((SHAMT) >= (sizeof(SRC) * 8)) ? 0 : (fCAST##REGSTYPE##s(SRC) << (SHAMT))) 567 568 #ifdef QEMU_GENERATE 569 #define fLOAD(NUM, SIZE, SIGN, EA, DST) MEM_LOAD##SIZE##SIGN(DST, EA) 570 #else 571 #define fLOAD(NUM, SIZE, SIGN, EA, DST) \ 572 DST = (size##SIZE##SIGN##_t)MEM_LOAD##SIZE##SIGN(EA) 573 #endif 574 575 #define fMEMOP(NUM, SIZE, SIGN, EA, FNTYPE, VALUE) 576 577 #define fGET_FRAMEKEY() READ_REG(HEX_REG_FRAMEKEY) 578 #define fFRAME_SCRAMBLE(VAL) ((VAL) ^ (fCAST8u(fGET_FRAMEKEY()) << 32)) 579 #define fFRAME_UNSCRAMBLE(VAL) fFRAME_SCRAMBLE(VAL) 580 581 #ifdef CONFIG_USER_ONLY 582 #define fFRAMECHECK(ADDR, EA) do { } while (0) /* Not modelled in linux-user */ 583 #else 584 /* System mode not implemented yet */ 585 #define fFRAMECHECK(ADDR, EA) g_assert_not_reached(); 586 #endif 587 588 #ifdef QEMU_GENERATE 589 #define fLOAD_LOCKED(NUM, SIZE, SIGN, EA, DST) \ 590 gen_load_locked##SIZE##SIGN(DST, EA, ctx->mem_idx); 591 #endif 592 593 #ifdef QEMU_GENERATE 594 #define fSTORE(NUM, SIZE, EA, SRC) MEM_STORE##SIZE(EA, SRC, insn->slot) 595 #else 596 #define fSTORE(NUM, SIZE, EA, SRC) MEM_STORE##SIZE(EA, SRC, slot) 597 #endif 598 599 #ifdef QEMU_GENERATE 600 #define fSTORE_LOCKED(NUM, SIZE, EA, SRC, PRED) \ 601 gen_store_conditional##SIZE(env, ctx, PdN, PRED, EA, SRC); 602 #endif 603 604 #ifdef QEMU_GENERATE 605 #define GETBYTE_FUNC(X) \ 606 __builtin_choose_expr(TYPE_TCGV(X), \ 607 gen_get_byte, \ 608 __builtin_choose_expr(TYPE_TCGV_I64(X), \ 609 gen_get_byte_i64, (void)0)) 610 #define fGETBYTE(N, SRC) GETBYTE_FUNC(SRC)(BYTE, N, SRC, true) 611 #define fGETUBYTE(N, SRC) GETBYTE_FUNC(SRC)(BYTE, N, SRC, false) 612 #else 613 #define fGETBYTE(N, SRC) ((int8_t)((SRC >> ((N) * 8)) & 0xff)) 614 #define fGETUBYTE(N, SRC) ((uint8_t)((SRC >> ((N) * 8)) & 0xff)) 615 #endif 616 617 #define fSETBYTE(N, DST, VAL) \ 618 do { \ 619 DST = (DST & ~(0x0ffLL << ((N) * 8))) | \ 620 (((uint64_t)((VAL) & 0x0ffLL)) << ((N) * 8)); \ 621 } while (0) 622 623 #ifdef QEMU_GENERATE 624 #define fGETHALF(N, SRC) gen_get_half(HALF, N, SRC, true) 625 #define fGETUHALF(N, SRC) gen_get_half(HALF, N, SRC, false) 626 #else 627 #define fGETHALF(N, SRC) ((int16_t)((SRC >> ((N) * 16)) & 0xffff)) 628 #define fGETUHALF(N, SRC) ((uint16_t)((SRC >> ((N) * 16)) & 0xffff)) 629 #endif 630 #define fSETHALF(N, DST, VAL) \ 631 do { \ 632 DST = (DST & ~(0x0ffffLL << ((N) * 16))) | \ 633 (((uint64_t)((VAL) & 0x0ffff)) << ((N) * 16)); \ 634 } while (0) 635 #define fSETHALFw fSETHALF 636 #define fSETHALFd fSETHALF 637 638 #define fGETWORD(N, SRC) \ 639 ((int64_t)((int32_t)((SRC >> ((N) * 32)) & 0x0ffffffffLL))) 640 #define fGETUWORD(N, SRC) \ 641 ((uint64_t)((uint32_t)((SRC >> ((N) * 32)) & 0x0ffffffffLL))) 642 643 #define fSETWORD(N, DST, VAL) \ 644 do { \ 645 DST = (DST & ~(0x0ffffffffLL << ((N) * 32))) | \ 646 (((VAL) & 0x0ffffffffLL) << ((N) * 32)); \ 647 } while (0) 648 649 #define fSETBIT(N, DST, VAL) \ 650 do { \ 651 DST = (DST & ~(1ULL << (N))) | (((uint64_t)(VAL)) << (N)); \ 652 } while (0) 653 654 #define fGETBIT(N, SRC) (((SRC) >> N) & 1) 655 #define fSETBITS(HI, LO, DST, VAL) \ 656 do { \ 657 int j; \ 658 for (j = LO; j <= HI; j++) { \ 659 fSETBIT(j, DST, VAL); \ 660 } \ 661 } while (0) 662 #define fCOUNTONES_4(VAL) ctpop32(VAL) 663 #define fCOUNTONES_8(VAL) ctpop64(VAL) 664 #define fBREV_8(VAL) revbit64(VAL) 665 #define fBREV_4(VAL) revbit32(VAL) 666 #define fCL1_8(VAL) clo64(VAL) 667 #define fCL1_4(VAL) clo32(VAL) 668 #define fINTERLEAVE(ODD, EVEN) interleave(ODD, EVEN) 669 #define fDEINTERLEAVE(MIXED) deinterleave(MIXED) 670 #define fHIDE(A) A 671 #define fCONSTLL(A) A##LL 672 #define fECHO(A) (A) 673 674 #define fTRAP(TRAPTYPE, IMM) helper_raise_exception(env, HEX_EXCP_TRAP0) 675 #define fPAUSE(IMM) 676 677 #define fALIGN_REG_FIELD_VALUE(FIELD, VAL) \ 678 ((VAL) << reg_field_info[FIELD].offset) 679 #define fGET_REG_FIELD_MASK(FIELD) \ 680 (((1 << reg_field_info[FIELD].width) - 1) << reg_field_info[FIELD].offset) 681 #define fREAD_REG_FIELD(REG, FIELD) \ 682 fEXTRACTU_BITS(env->gpr[HEX_REG_##REG], \ 683 reg_field_info[FIELD].width, \ 684 reg_field_info[FIELD].offset) 685 #define fGET_FIELD(VAL, FIELD) 686 #define fSET_FIELD(VAL, FIELD, NEWVAL) 687 #define fBARRIER() 688 #define fSYNCH() 689 #define fISYNC() 690 #define fDCFETCH(REG) \ 691 do { (void)REG; } while (0) /* Nothing to do in qemu */ 692 #define fICINVA(REG) \ 693 do { (void)REG; } while (0) /* Nothing to do in qemu */ 694 #define fL2FETCH(ADDR, HEIGHT, WIDTH, STRIDE, FLAGS) 695 #define fDCCLEANA(REG) \ 696 do { (void)REG; } while (0) /* Nothing to do in qemu */ 697 #define fDCCLEANINVA(REG) \ 698 do { (void)REG; } while (0) /* Nothing to do in qemu */ 699 700 #define fDCZEROA(REG) do { env->dczero_addr = (REG); } while (0) 701 702 #define fBRANCH_SPECULATE_STALL(DOTNEWVAL, JUMP_COND, SPEC_DIR, HINTBITNUM, \ 703 STRBITNUM) /* Nothing */ 704 705 706 #endif 707