1 /* 2 * Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #include "qemu/osdep.h" 19 #include "qemu/log.h" 20 #include "cpu.h" 21 #include "internal.h" 22 #include "tcg/tcg-op.h" 23 #include "insn.h" 24 #include "opcodes.h" 25 #include "translate.h" 26 #define QEMU_GENERATE /* Used internally by macros.h */ 27 #include "macros.h" 28 #undef QEMU_GENERATE 29 #include "gen_tcg.h" 30 31 static inline TCGv gen_read_preg(TCGv pred, uint8_t num) 32 { 33 tcg_gen_mov_tl(pred, hex_pred[num]); 34 return pred; 35 } 36 37 static inline void gen_log_predicated_reg_write(int rnum, TCGv val, int slot) 38 { 39 TCGv zero = tcg_const_tl(0); 40 TCGv slot_mask = tcg_temp_new(); 41 42 tcg_gen_andi_tl(slot_mask, hex_slot_cancelled, 1 << slot); 43 tcg_gen_movcond_tl(TCG_COND_EQ, hex_new_value[rnum], slot_mask, zero, 44 val, hex_new_value[rnum]); 45 if (HEX_DEBUG) { 46 /* 47 * Do this so HELPER(debug_commit_end) will know 48 * 49 * Note that slot_mask indicates the value is not written 50 * (i.e., slot was cancelled), so we create a true/false value before 51 * or'ing with hex_reg_written[rnum]. 52 */ 53 tcg_gen_setcond_tl(TCG_COND_EQ, slot_mask, slot_mask, zero); 54 tcg_gen_or_tl(hex_reg_written[rnum], hex_reg_written[rnum], slot_mask); 55 } 56 57 tcg_temp_free(zero); 58 tcg_temp_free(slot_mask); 59 } 60 61 static inline void gen_log_reg_write(int rnum, TCGv val) 62 { 63 tcg_gen_mov_tl(hex_new_value[rnum], val); 64 if (HEX_DEBUG) { 65 /* Do this so HELPER(debug_commit_end) will know */ 66 tcg_gen_movi_tl(hex_reg_written[rnum], 1); 67 } 68 } 69 70 static void gen_log_predicated_reg_write_pair(int rnum, TCGv_i64 val, int slot) 71 { 72 TCGv val32 = tcg_temp_new(); 73 TCGv zero = tcg_const_tl(0); 74 TCGv slot_mask = tcg_temp_new(); 75 76 tcg_gen_andi_tl(slot_mask, hex_slot_cancelled, 1 << slot); 77 /* Low word */ 78 tcg_gen_extrl_i64_i32(val32, val); 79 tcg_gen_movcond_tl(TCG_COND_EQ, hex_new_value[rnum], 80 slot_mask, zero, 81 val32, hex_new_value[rnum]); 82 /* High word */ 83 tcg_gen_extrh_i64_i32(val32, val); 84 tcg_gen_movcond_tl(TCG_COND_EQ, hex_new_value[rnum + 1], 85 slot_mask, zero, 86 val32, hex_new_value[rnum + 1]); 87 if (HEX_DEBUG) { 88 /* 89 * Do this so HELPER(debug_commit_end) will know 90 * 91 * Note that slot_mask indicates the value is not written 92 * (i.e., slot was cancelled), so we create a true/false value before 93 * or'ing with hex_reg_written[rnum]. 94 */ 95 tcg_gen_setcond_tl(TCG_COND_EQ, slot_mask, slot_mask, zero); 96 tcg_gen_or_tl(hex_reg_written[rnum], hex_reg_written[rnum], slot_mask); 97 tcg_gen_or_tl(hex_reg_written[rnum + 1], hex_reg_written[rnum + 1], 98 slot_mask); 99 } 100 101 tcg_temp_free(val32); 102 tcg_temp_free(zero); 103 tcg_temp_free(slot_mask); 104 } 105 106 static void gen_log_reg_write_pair(int rnum, TCGv_i64 val) 107 { 108 /* Low word */ 109 tcg_gen_extrl_i64_i32(hex_new_value[rnum], val); 110 if (HEX_DEBUG) { 111 /* Do this so HELPER(debug_commit_end) will know */ 112 tcg_gen_movi_tl(hex_reg_written[rnum], 1); 113 } 114 115 /* High word */ 116 tcg_gen_extrh_i64_i32(hex_new_value[rnum + 1], val); 117 if (HEX_DEBUG) { 118 /* Do this so HELPER(debug_commit_end) will know */ 119 tcg_gen_movi_tl(hex_reg_written[rnum + 1], 1); 120 } 121 } 122 123 static inline void gen_log_pred_write(DisasContext *ctx, int pnum, TCGv val) 124 { 125 TCGv zero = tcg_const_tl(0); 126 TCGv base_val = tcg_temp_new(); 127 TCGv and_val = tcg_temp_new(); 128 TCGv pred_written = tcg_temp_new(); 129 130 tcg_gen_andi_tl(base_val, val, 0xff); 131 132 /* 133 * Section 6.1.3 of the Hexagon V67 Programmer's Reference Manual 134 * 135 * Multiple writes to the same preg are and'ed together 136 * If this is the first predicate write in the packet, do a 137 * straight assignment. Otherwise, do an and. 138 */ 139 if (!test_bit(pnum, ctx->pregs_written)) { 140 tcg_gen_mov_tl(hex_new_pred_value[pnum], base_val); 141 } else { 142 tcg_gen_and_tl(hex_new_pred_value[pnum], 143 hex_new_pred_value[pnum], base_val); 144 } 145 tcg_gen_ori_tl(hex_pred_written, hex_pred_written, 1 << pnum); 146 147 tcg_temp_free(zero); 148 tcg_temp_free(base_val); 149 tcg_temp_free(and_val); 150 tcg_temp_free(pred_written); 151 } 152 153 static inline void gen_read_p3_0(TCGv control_reg) 154 { 155 tcg_gen_movi_tl(control_reg, 0); 156 for (int i = 0; i < NUM_PREGS; i++) { 157 tcg_gen_deposit_tl(control_reg, control_reg, hex_pred[i], i * 8, 8); 158 } 159 } 160 161 /* 162 * Certain control registers require special handling on read 163 * HEX_REG_P3_0 aliased to the predicate registers 164 * -> concat the 4 predicate registers together 165 * HEX_REG_PC actual value stored in DisasContext 166 * -> assign from ctx->base.pc_next 167 * HEX_REG_QEMU_*_CNT changes in current TB in DisasContext 168 * -> add current TB changes to existing reg value 169 */ 170 static inline void gen_read_ctrl_reg(DisasContext *ctx, const int reg_num, 171 TCGv dest) 172 { 173 if (reg_num == HEX_REG_P3_0) { 174 gen_read_p3_0(dest); 175 } else if (reg_num == HEX_REG_PC) { 176 tcg_gen_movi_tl(dest, ctx->base.pc_next); 177 } else if (reg_num == HEX_REG_QEMU_PKT_CNT) { 178 tcg_gen_addi_tl(dest, hex_gpr[HEX_REG_QEMU_PKT_CNT], 179 ctx->num_packets); 180 } else if (reg_num == HEX_REG_QEMU_INSN_CNT) { 181 tcg_gen_addi_tl(dest, hex_gpr[HEX_REG_QEMU_INSN_CNT], 182 ctx->num_insns); 183 } else { 184 tcg_gen_mov_tl(dest, hex_gpr[reg_num]); 185 } 186 } 187 188 static inline void gen_read_ctrl_reg_pair(DisasContext *ctx, const int reg_num, 189 TCGv_i64 dest) 190 { 191 if (reg_num == HEX_REG_P3_0) { 192 TCGv p3_0 = tcg_temp_new(); 193 gen_read_p3_0(p3_0); 194 tcg_gen_concat_i32_i64(dest, p3_0, hex_gpr[reg_num + 1]); 195 tcg_temp_free(p3_0); 196 } else if (reg_num == HEX_REG_PC - 1) { 197 TCGv pc = tcg_const_tl(ctx->base.pc_next); 198 tcg_gen_concat_i32_i64(dest, hex_gpr[reg_num], pc); 199 tcg_temp_free(pc); 200 } else if (reg_num == HEX_REG_QEMU_PKT_CNT) { 201 TCGv pkt_cnt = tcg_temp_new(); 202 TCGv insn_cnt = tcg_temp_new(); 203 tcg_gen_addi_tl(pkt_cnt, hex_gpr[HEX_REG_QEMU_PKT_CNT], 204 ctx->num_packets); 205 tcg_gen_addi_tl(insn_cnt, hex_gpr[HEX_REG_QEMU_INSN_CNT], 206 ctx->num_insns); 207 tcg_gen_concat_i32_i64(dest, pkt_cnt, insn_cnt); 208 tcg_temp_free(pkt_cnt); 209 tcg_temp_free(insn_cnt); 210 } else { 211 tcg_gen_concat_i32_i64(dest, 212 hex_gpr[reg_num], 213 hex_gpr[reg_num + 1]); 214 } 215 } 216 217 static inline void gen_write_p3_0(TCGv control_reg) 218 { 219 for (int i = 0; i < NUM_PREGS; i++) { 220 tcg_gen_extract_tl(hex_pred[i], control_reg, i * 8, 8); 221 } 222 } 223 224 /* 225 * Certain control registers require special handling on write 226 * HEX_REG_P3_0 aliased to the predicate registers 227 * -> break the value across 4 predicate registers 228 * HEX_REG_QEMU_*_CNT changes in current TB in DisasContext 229 * -> clear the changes 230 */ 231 static inline void gen_write_ctrl_reg(DisasContext *ctx, int reg_num, 232 TCGv val) 233 { 234 if (reg_num == HEX_REG_P3_0) { 235 gen_write_p3_0(val); 236 } else { 237 gen_log_reg_write(reg_num, val); 238 ctx_log_reg_write(ctx, reg_num); 239 if (reg_num == HEX_REG_QEMU_PKT_CNT) { 240 ctx->num_packets = 0; 241 } 242 if (reg_num == HEX_REG_QEMU_INSN_CNT) { 243 ctx->num_insns = 0; 244 } 245 } 246 } 247 248 static inline void gen_write_ctrl_reg_pair(DisasContext *ctx, int reg_num, 249 TCGv_i64 val) 250 { 251 if (reg_num == HEX_REG_P3_0) { 252 TCGv val32 = tcg_temp_new(); 253 tcg_gen_extrl_i64_i32(val32, val); 254 gen_write_p3_0(val32); 255 tcg_gen_extrh_i64_i32(val32, val); 256 gen_log_reg_write(reg_num + 1, val32); 257 tcg_temp_free(val32); 258 ctx_log_reg_write(ctx, reg_num + 1); 259 } else { 260 gen_log_reg_write_pair(reg_num, val); 261 ctx_log_reg_write_pair(ctx, reg_num); 262 if (reg_num == HEX_REG_QEMU_PKT_CNT) { 263 ctx->num_packets = 0; 264 ctx->num_insns = 0; 265 } 266 } 267 } 268 269 static TCGv gen_get_byte(TCGv result, int N, TCGv src, bool sign) 270 { 271 if (sign) { 272 tcg_gen_sextract_tl(result, src, N * 8, 8); 273 } else { 274 tcg_gen_extract_tl(result, src, N * 8, 8); 275 } 276 return result; 277 } 278 279 static TCGv gen_get_byte_i64(TCGv result, int N, TCGv_i64 src, bool sign) 280 { 281 TCGv_i64 res64 = tcg_temp_new_i64(); 282 if (sign) { 283 tcg_gen_sextract_i64(res64, src, N * 8, 8); 284 } else { 285 tcg_gen_extract_i64(res64, src, N * 8, 8); 286 } 287 tcg_gen_extrl_i64_i32(result, res64); 288 tcg_temp_free_i64(res64); 289 290 return result; 291 } 292 293 static inline TCGv gen_get_half(TCGv result, int N, TCGv src, bool sign) 294 { 295 if (sign) { 296 tcg_gen_sextract_tl(result, src, N * 16, 16); 297 } else { 298 tcg_gen_extract_tl(result, src, N * 16, 16); 299 } 300 return result; 301 } 302 303 static inline void gen_set_half(int N, TCGv result, TCGv src) 304 { 305 tcg_gen_deposit_tl(result, result, src, N * 16, 16); 306 } 307 308 static inline void gen_set_half_i64(int N, TCGv_i64 result, TCGv src) 309 { 310 TCGv_i64 src64 = tcg_temp_new_i64(); 311 tcg_gen_extu_i32_i64(src64, src); 312 tcg_gen_deposit_i64(result, result, src64, N * 16, 16); 313 tcg_temp_free_i64(src64); 314 } 315 316 static void gen_set_byte_i64(int N, TCGv_i64 result, TCGv src) 317 { 318 TCGv_i64 src64 = tcg_temp_new_i64(); 319 tcg_gen_extu_i32_i64(src64, src); 320 tcg_gen_deposit_i64(result, result, src64, N * 8, 8); 321 tcg_temp_free_i64(src64); 322 } 323 324 static inline void gen_load_locked4u(TCGv dest, TCGv vaddr, int mem_index) 325 { 326 tcg_gen_qemu_ld32u(dest, vaddr, mem_index); 327 tcg_gen_mov_tl(hex_llsc_addr, vaddr); 328 tcg_gen_mov_tl(hex_llsc_val, dest); 329 } 330 331 static inline void gen_load_locked8u(TCGv_i64 dest, TCGv vaddr, int mem_index) 332 { 333 tcg_gen_qemu_ld64(dest, vaddr, mem_index); 334 tcg_gen_mov_tl(hex_llsc_addr, vaddr); 335 tcg_gen_mov_i64(hex_llsc_val_i64, dest); 336 } 337 338 static inline void gen_store_conditional4(CPUHexagonState *env, 339 DisasContext *ctx, int prednum, 340 TCGv pred, TCGv vaddr, TCGv src) 341 { 342 TCGLabel *fail = gen_new_label(); 343 TCGLabel *done = gen_new_label(); 344 TCGv one, zero, tmp; 345 346 tcg_gen_brcond_tl(TCG_COND_NE, vaddr, hex_llsc_addr, fail); 347 348 one = tcg_const_tl(0xff); 349 zero = tcg_const_tl(0); 350 tmp = tcg_temp_new(); 351 tcg_gen_atomic_cmpxchg_tl(tmp, hex_llsc_addr, hex_llsc_val, src, 352 ctx->mem_idx, MO_32); 353 tcg_gen_movcond_tl(TCG_COND_EQ, hex_pred[prednum], tmp, hex_llsc_val, 354 one, zero); 355 tcg_temp_free(one); 356 tcg_temp_free(zero); 357 tcg_temp_free(tmp); 358 tcg_gen_br(done); 359 360 gen_set_label(fail); 361 tcg_gen_movi_tl(pred, 0); 362 363 gen_set_label(done); 364 tcg_gen_movi_tl(hex_llsc_addr, ~0); 365 } 366 367 static inline void gen_store_conditional8(CPUHexagonState *env, 368 DisasContext *ctx, int prednum, 369 TCGv pred, TCGv vaddr, TCGv_i64 src) 370 { 371 TCGLabel *fail = gen_new_label(); 372 TCGLabel *done = gen_new_label(); 373 TCGv_i64 one, zero, tmp; 374 375 tcg_gen_brcond_tl(TCG_COND_NE, vaddr, hex_llsc_addr, fail); 376 377 one = tcg_const_i64(0xff); 378 zero = tcg_const_i64(0); 379 tmp = tcg_temp_new_i64(); 380 tcg_gen_atomic_cmpxchg_i64(tmp, hex_llsc_addr, hex_llsc_val_i64, src, 381 ctx->mem_idx, MO_64); 382 tcg_gen_movcond_i64(TCG_COND_EQ, tmp, tmp, hex_llsc_val_i64, 383 one, zero); 384 tcg_gen_extrl_i64_i32(hex_pred[prednum], tmp); 385 tcg_temp_free_i64(one); 386 tcg_temp_free_i64(zero); 387 tcg_temp_free_i64(tmp); 388 tcg_gen_br(done); 389 390 gen_set_label(fail); 391 tcg_gen_movi_tl(pred, 0); 392 393 gen_set_label(done); 394 tcg_gen_movi_tl(hex_llsc_addr, ~0); 395 } 396 397 static inline void gen_store32(TCGv vaddr, TCGv src, int width, int slot) 398 { 399 tcg_gen_mov_tl(hex_store_addr[slot], vaddr); 400 tcg_gen_movi_tl(hex_store_width[slot], width); 401 tcg_gen_mov_tl(hex_store_val32[slot], src); 402 } 403 404 static inline void gen_store1(TCGv_env cpu_env, TCGv vaddr, TCGv src, 405 DisasContext *ctx, int slot) 406 { 407 gen_store32(vaddr, src, 1, slot); 408 ctx->store_width[slot] = 1; 409 } 410 411 static inline void gen_store1i(TCGv_env cpu_env, TCGv vaddr, int32_t src, 412 DisasContext *ctx, int slot) 413 { 414 TCGv tmp = tcg_const_tl(src); 415 gen_store1(cpu_env, vaddr, tmp, ctx, slot); 416 tcg_temp_free(tmp); 417 } 418 419 static inline void gen_store2(TCGv_env cpu_env, TCGv vaddr, TCGv src, 420 DisasContext *ctx, int slot) 421 { 422 gen_store32(vaddr, src, 2, slot); 423 ctx->store_width[slot] = 2; 424 } 425 426 static inline void gen_store2i(TCGv_env cpu_env, TCGv vaddr, int32_t src, 427 DisasContext *ctx, int slot) 428 { 429 TCGv tmp = tcg_const_tl(src); 430 gen_store2(cpu_env, vaddr, tmp, ctx, slot); 431 tcg_temp_free(tmp); 432 } 433 434 static inline void gen_store4(TCGv_env cpu_env, TCGv vaddr, TCGv src, 435 DisasContext *ctx, int slot) 436 { 437 gen_store32(vaddr, src, 4, slot); 438 ctx->store_width[slot] = 4; 439 } 440 441 static inline void gen_store4i(TCGv_env cpu_env, TCGv vaddr, int32_t src, 442 DisasContext *ctx, int slot) 443 { 444 TCGv tmp = tcg_const_tl(src); 445 gen_store4(cpu_env, vaddr, tmp, ctx, slot); 446 tcg_temp_free(tmp); 447 } 448 449 static inline void gen_store8(TCGv_env cpu_env, TCGv vaddr, TCGv_i64 src, 450 DisasContext *ctx, int slot) 451 { 452 tcg_gen_mov_tl(hex_store_addr[slot], vaddr); 453 tcg_gen_movi_tl(hex_store_width[slot], 8); 454 tcg_gen_mov_i64(hex_store_val64[slot], src); 455 ctx->store_width[slot] = 8; 456 } 457 458 static inline void gen_store8i(TCGv_env cpu_env, TCGv vaddr, int64_t src, 459 DisasContext *ctx, int slot) 460 { 461 TCGv_i64 tmp = tcg_const_i64(src); 462 gen_store8(cpu_env, vaddr, tmp, ctx, slot); 463 tcg_temp_free_i64(tmp); 464 } 465 466 static TCGv gen_8bitsof(TCGv result, TCGv value) 467 { 468 TCGv zero = tcg_const_tl(0); 469 TCGv ones = tcg_const_tl(0xff); 470 tcg_gen_movcond_tl(TCG_COND_NE, result, value, zero, ones, zero); 471 tcg_temp_free(zero); 472 tcg_temp_free(ones); 473 474 return result; 475 } 476 477 #include "tcg_funcs_generated.c.inc" 478 #include "tcg_func_table_generated.c.inc" 479