1 /* 2 * Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #define QEMU_GENERATE 19 #include "qemu/osdep.h" 20 #include "qemu/log.h" 21 #include "cpu.h" 22 #include "internal.h" 23 #include "tcg/tcg-op.h" 24 #include "insn.h" 25 #include "opcodes.h" 26 #include "translate.h" 27 #include "macros.h" 28 #include "gen_tcg.h" 29 30 static inline TCGv gen_read_preg(TCGv pred, uint8_t num) 31 { 32 tcg_gen_mov_tl(pred, hex_pred[num]); 33 return pred; 34 } 35 36 static inline void gen_log_predicated_reg_write(int rnum, TCGv val, int slot) 37 { 38 TCGv one = tcg_const_tl(1); 39 TCGv zero = tcg_const_tl(0); 40 TCGv slot_mask = tcg_temp_new(); 41 42 tcg_gen_andi_tl(slot_mask, hex_slot_cancelled, 1 << slot); 43 tcg_gen_movcond_tl(TCG_COND_EQ, hex_new_value[rnum], slot_mask, zero, 44 val, hex_new_value[rnum]); 45 #if HEX_DEBUG 46 /* Do this so HELPER(debug_commit_end) will know */ 47 tcg_gen_movcond_tl(TCG_COND_EQ, hex_reg_written[rnum], slot_mask, zero, 48 one, hex_reg_written[rnum]); 49 #endif 50 51 tcg_temp_free(one); 52 tcg_temp_free(zero); 53 tcg_temp_free(slot_mask); 54 } 55 56 static inline void gen_log_reg_write(int rnum, TCGv val) 57 { 58 tcg_gen_mov_tl(hex_new_value[rnum], val); 59 #if HEX_DEBUG 60 /* Do this so HELPER(debug_commit_end) will know */ 61 tcg_gen_movi_tl(hex_reg_written[rnum], 1); 62 #endif 63 } 64 65 static void gen_log_predicated_reg_write_pair(int rnum, TCGv_i64 val, int slot) 66 { 67 TCGv val32 = tcg_temp_new(); 68 TCGv one = tcg_const_tl(1); 69 TCGv zero = tcg_const_tl(0); 70 TCGv slot_mask = tcg_temp_new(); 71 72 tcg_gen_andi_tl(slot_mask, hex_slot_cancelled, 1 << slot); 73 /* Low word */ 74 tcg_gen_extrl_i64_i32(val32, val); 75 tcg_gen_movcond_tl(TCG_COND_EQ, hex_new_value[rnum], slot_mask, zero, 76 val32, hex_new_value[rnum]); 77 #if HEX_DEBUG 78 /* Do this so HELPER(debug_commit_end) will know */ 79 tcg_gen_movcond_tl(TCG_COND_EQ, hex_reg_written[rnum], 80 slot_mask, zero, 81 one, hex_reg_written[rnum]); 82 #endif 83 84 /* High word */ 85 tcg_gen_extrh_i64_i32(val32, val); 86 tcg_gen_movcond_tl(TCG_COND_EQ, hex_new_value[rnum + 1], 87 slot_mask, zero, 88 val32, hex_new_value[rnum + 1]); 89 #if HEX_DEBUG 90 /* Do this so HELPER(debug_commit_end) will know */ 91 tcg_gen_movcond_tl(TCG_COND_EQ, hex_reg_written[rnum + 1], 92 slot_mask, zero, 93 one, hex_reg_written[rnum + 1]); 94 #endif 95 96 tcg_temp_free(val32); 97 tcg_temp_free(one); 98 tcg_temp_free(zero); 99 tcg_temp_free(slot_mask); 100 } 101 102 static void gen_log_reg_write_pair(int rnum, TCGv_i64 val) 103 { 104 /* Low word */ 105 tcg_gen_extrl_i64_i32(hex_new_value[rnum], val); 106 #if HEX_DEBUG 107 /* Do this so HELPER(debug_commit_end) will know */ 108 tcg_gen_movi_tl(hex_reg_written[rnum], 1); 109 #endif 110 111 /* High word */ 112 tcg_gen_extrh_i64_i32(hex_new_value[rnum + 1], val); 113 #if HEX_DEBUG 114 /* Do this so HELPER(debug_commit_end) will know */ 115 tcg_gen_movi_tl(hex_reg_written[rnum + 1], 1); 116 #endif 117 } 118 119 static inline void gen_log_pred_write(int pnum, TCGv val) 120 { 121 TCGv zero = tcg_const_tl(0); 122 TCGv base_val = tcg_temp_new(); 123 TCGv and_val = tcg_temp_new(); 124 TCGv pred_written = tcg_temp_new(); 125 126 /* Multiple writes to the same preg are and'ed together */ 127 tcg_gen_andi_tl(base_val, val, 0xff); 128 tcg_gen_and_tl(and_val, base_val, hex_new_pred_value[pnum]); 129 tcg_gen_andi_tl(pred_written, hex_pred_written, 1 << pnum); 130 tcg_gen_movcond_tl(TCG_COND_NE, hex_new_pred_value[pnum], 131 pred_written, zero, 132 and_val, base_val); 133 tcg_gen_ori_tl(hex_pred_written, hex_pred_written, 1 << pnum); 134 135 tcg_temp_free(zero); 136 tcg_temp_free(base_val); 137 tcg_temp_free(and_val); 138 tcg_temp_free(pred_written); 139 } 140 141 static inline void gen_read_p3_0(TCGv control_reg) 142 { 143 tcg_gen_movi_tl(control_reg, 0); 144 for (int i = 0; i < NUM_PREGS; i++) { 145 tcg_gen_deposit_tl(control_reg, control_reg, hex_pred[i], i * 8, 8); 146 } 147 } 148 149 /* 150 * Certain control registers require special handling on read 151 * HEX_REG_P3_0 aliased to the predicate registers 152 * -> concat the 4 predicate registers together 153 * HEX_REG_PC actual value stored in DisasContext 154 * -> assign from ctx->base.pc_next 155 * HEX_REG_QEMU_*_CNT changes in current TB in DisasContext 156 * -> add current TB changes to existing reg value 157 */ 158 static inline void gen_read_ctrl_reg(DisasContext *ctx, const int reg_num, 159 TCGv dest) 160 { 161 if (reg_num == HEX_REG_P3_0) { 162 gen_read_p3_0(dest); 163 } else if (reg_num == HEX_REG_PC) { 164 tcg_gen_movi_tl(dest, ctx->base.pc_next); 165 } else if (reg_num == HEX_REG_QEMU_PKT_CNT) { 166 tcg_gen_addi_tl(dest, hex_gpr[HEX_REG_QEMU_PKT_CNT], 167 ctx->num_packets); 168 } else if (reg_num == HEX_REG_QEMU_INSN_CNT) { 169 tcg_gen_addi_tl(dest, hex_gpr[HEX_REG_QEMU_INSN_CNT], 170 ctx->num_insns); 171 } else { 172 tcg_gen_mov_tl(dest, hex_gpr[reg_num]); 173 } 174 } 175 176 static inline void gen_read_ctrl_reg_pair(DisasContext *ctx, const int reg_num, 177 TCGv_i64 dest) 178 { 179 if (reg_num == HEX_REG_P3_0) { 180 TCGv p3_0 = tcg_temp_new(); 181 gen_read_p3_0(p3_0); 182 tcg_gen_concat_i32_i64(dest, p3_0, hex_gpr[reg_num + 1]); 183 tcg_temp_free(p3_0); 184 } else if (reg_num == HEX_REG_PC - 1) { 185 TCGv pc = tcg_const_tl(ctx->base.pc_next); 186 tcg_gen_concat_i32_i64(dest, hex_gpr[reg_num], pc); 187 tcg_temp_free(pc); 188 } else if (reg_num == HEX_REG_QEMU_PKT_CNT) { 189 TCGv pkt_cnt = tcg_temp_new(); 190 TCGv insn_cnt = tcg_temp_new(); 191 tcg_gen_addi_tl(pkt_cnt, hex_gpr[HEX_REG_QEMU_PKT_CNT], 192 ctx->num_packets); 193 tcg_gen_addi_tl(insn_cnt, hex_gpr[HEX_REG_QEMU_INSN_CNT], 194 ctx->num_insns); 195 tcg_gen_concat_i32_i64(dest, pkt_cnt, insn_cnt); 196 tcg_temp_free(pkt_cnt); 197 tcg_temp_free(insn_cnt); 198 } else { 199 tcg_gen_concat_i32_i64(dest, 200 hex_gpr[reg_num], 201 hex_gpr[reg_num + 1]); 202 } 203 } 204 205 static inline void gen_write_p3_0(TCGv control_reg) 206 { 207 for (int i = 0; i < NUM_PREGS; i++) { 208 tcg_gen_extract_tl(hex_pred[i], control_reg, i * 8, 8); 209 } 210 } 211 212 /* 213 * Certain control registers require special handling on write 214 * HEX_REG_P3_0 aliased to the predicate registers 215 * -> break the value across 4 predicate registers 216 * HEX_REG_QEMU_*_CNT changes in current TB in DisasContext 217 * -> clear the changes 218 */ 219 static inline void gen_write_ctrl_reg(DisasContext *ctx, int reg_num, 220 TCGv val) 221 { 222 if (reg_num == HEX_REG_P3_0) { 223 gen_write_p3_0(val); 224 } else { 225 gen_log_reg_write(reg_num, val); 226 ctx_log_reg_write(ctx, reg_num); 227 if (reg_num == HEX_REG_QEMU_PKT_CNT) { 228 ctx->num_packets = 0; 229 } 230 if (reg_num == HEX_REG_QEMU_INSN_CNT) { 231 ctx->num_insns = 0; 232 } 233 } 234 } 235 236 static inline void gen_write_ctrl_reg_pair(DisasContext *ctx, int reg_num, 237 TCGv_i64 val) 238 { 239 if (reg_num == HEX_REG_P3_0) { 240 TCGv val32 = tcg_temp_new(); 241 tcg_gen_extrl_i64_i32(val32, val); 242 gen_write_p3_0(val32); 243 tcg_gen_extrh_i64_i32(val32, val); 244 gen_log_reg_write(reg_num + 1, val32); 245 tcg_temp_free(val32); 246 ctx_log_reg_write(ctx, reg_num + 1); 247 } else { 248 gen_log_reg_write_pair(reg_num, val); 249 ctx_log_reg_write_pair(ctx, reg_num); 250 if (reg_num == HEX_REG_QEMU_PKT_CNT) { 251 ctx->num_packets = 0; 252 ctx->num_insns = 0; 253 } 254 } 255 } 256 257 static inline void gen_load_locked4u(TCGv dest, TCGv vaddr, int mem_index) 258 { 259 tcg_gen_qemu_ld32u(dest, vaddr, mem_index); 260 tcg_gen_mov_tl(hex_llsc_addr, vaddr); 261 tcg_gen_mov_tl(hex_llsc_val, dest); 262 } 263 264 static inline void gen_load_locked8u(TCGv_i64 dest, TCGv vaddr, int mem_index) 265 { 266 tcg_gen_qemu_ld64(dest, vaddr, mem_index); 267 tcg_gen_mov_tl(hex_llsc_addr, vaddr); 268 tcg_gen_mov_i64(hex_llsc_val_i64, dest); 269 } 270 271 static inline void gen_store_conditional4(CPUHexagonState *env, 272 DisasContext *ctx, int prednum, 273 TCGv pred, TCGv vaddr, TCGv src) 274 { 275 TCGLabel *fail = gen_new_label(); 276 TCGLabel *done = gen_new_label(); 277 TCGv one, zero, tmp; 278 279 tcg_gen_brcond_tl(TCG_COND_NE, vaddr, hex_llsc_addr, fail); 280 281 one = tcg_const_tl(0xff); 282 zero = tcg_const_tl(0); 283 tmp = tcg_temp_new(); 284 tcg_gen_atomic_cmpxchg_tl(tmp, hex_llsc_addr, hex_llsc_val, src, 285 ctx->mem_idx, MO_32); 286 tcg_gen_movcond_tl(TCG_COND_EQ, hex_pred[prednum], tmp, hex_llsc_val, 287 one, zero); 288 tcg_temp_free(one); 289 tcg_temp_free(zero); 290 tcg_temp_free(tmp); 291 tcg_gen_br(done); 292 293 gen_set_label(fail); 294 tcg_gen_movi_tl(pred, 0); 295 296 gen_set_label(done); 297 tcg_gen_movi_tl(hex_llsc_addr, ~0); 298 } 299 300 static inline void gen_store_conditional8(CPUHexagonState *env, 301 DisasContext *ctx, int prednum, 302 TCGv pred, TCGv vaddr, TCGv_i64 src) 303 { 304 TCGLabel *fail = gen_new_label(); 305 TCGLabel *done = gen_new_label(); 306 TCGv_i64 one, zero, tmp; 307 308 tcg_gen_brcond_tl(TCG_COND_NE, vaddr, hex_llsc_addr, fail); 309 310 one = tcg_const_i64(0xff); 311 zero = tcg_const_i64(0); 312 tmp = tcg_temp_new_i64(); 313 tcg_gen_atomic_cmpxchg_i64(tmp, hex_llsc_addr, hex_llsc_val_i64, src, 314 ctx->mem_idx, MO_64); 315 tcg_gen_movcond_i64(TCG_COND_EQ, tmp, tmp, hex_llsc_val_i64, 316 one, zero); 317 tcg_gen_extrl_i64_i32(hex_pred[prednum], tmp); 318 tcg_temp_free_i64(one); 319 tcg_temp_free_i64(zero); 320 tcg_temp_free_i64(tmp); 321 tcg_gen_br(done); 322 323 gen_set_label(fail); 324 tcg_gen_movi_tl(pred, 0); 325 326 gen_set_label(done); 327 tcg_gen_movi_tl(hex_llsc_addr, ~0); 328 } 329 330 #include "tcg_funcs_generated.c.inc" 331 #include "tcg_func_table_generated.c.inc" 332