1 /* 2 * Copyright(c) 2019-2022 Qualcomm Innovation Center, Inc. All Rights Reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #ifndef HEXAGON_GEN_TCG_H 19 #define HEXAGON_GEN_TCG_H 20 21 /* 22 * Here is a primer to understand the tag names for load/store instructions 23 * 24 * Data types 25 * b signed byte r0 = memb(r2+#0) 26 * ub unsigned byte r0 = memub(r2+#0) 27 * h signed half word (16 bits) r0 = memh(r2+#0) 28 * uh unsigned half word r0 = memuh(r2+#0) 29 * i integer (32 bits) r0 = memw(r2+#0) 30 * d double word (64 bits) r1:0 = memd(r2+#0) 31 * 32 * Addressing modes 33 * _io indirect with offset r0 = memw(r1+#4) 34 * _ur absolute with register offset r0 = memw(r1<<#4+##variable) 35 * _rr indirect with register offset r0 = memw(r1+r4<<#2) 36 * gp global pointer relative r0 = memw(gp+#200) 37 * _sp stack pointer relative r0 = memw(r29+#12) 38 * _ap absolute set r0 = memw(r1=##variable) 39 * _pr post increment register r0 = memw(r1++m1) 40 * _pbr post increment bit reverse r0 = memw(r1++m1:brev) 41 * _pi post increment immediate r0 = memb(r1++#1) 42 * _pci post increment circular immediate r0 = memw(r1++#4:circ(m0)) 43 * _pcr post increment circular register r0 = memw(r1++I:circ(m0)) 44 */ 45 46 /* Macros for complex addressing modes */ 47 #define GET_EA_ap \ 48 do { \ 49 fEA_IMM(UiV); \ 50 tcg_gen_movi_tl(ReV, UiV); \ 51 } while (0) 52 #define GET_EA_pr \ 53 do { \ 54 fEA_REG(RxV); \ 55 fPM_M(RxV, MuV); \ 56 } while (0) 57 #define GET_EA_pbr \ 58 do { \ 59 gen_helper_fbrev(EA, RxV); \ 60 tcg_gen_add_tl(RxV, RxV, MuV); \ 61 } while (0) 62 #define GET_EA_pi \ 63 do { \ 64 fEA_REG(RxV); \ 65 fPM_I(RxV, siV); \ 66 } while (0) 67 #define GET_EA_pci \ 68 do { \ 69 TCGv tcgv_siV = tcg_constant_tl(siV); \ 70 tcg_gen_mov_tl(EA, RxV); \ 71 gen_helper_fcircadd(RxV, RxV, tcgv_siV, MuV, \ 72 hex_gpr[HEX_REG_CS0 + MuN]); \ 73 } while (0) 74 #define GET_EA_pcr(SHIFT) \ 75 do { \ 76 TCGv ireg = tcg_temp_new(); \ 77 tcg_gen_mov_tl(EA, RxV); \ 78 gen_read_ireg(ireg, MuV, (SHIFT)); \ 79 gen_helper_fcircadd(RxV, RxV, ireg, MuV, hex_gpr[HEX_REG_CS0 + MuN]); \ 80 } while (0) 81 82 /* Instructions with multiple definitions */ 83 #define fGEN_TCG_LOAD_AP(RES, SIZE, SIGN) \ 84 do { \ 85 fMUST_IMMEXT(UiV); \ 86 fEA_IMM(UiV); \ 87 fLOAD(1, SIZE, SIGN, EA, RES); \ 88 tcg_gen_movi_tl(ReV, UiV); \ 89 } while (0) 90 91 #define fGEN_TCG_L4_loadrub_ap(SHORTCODE) \ 92 fGEN_TCG_LOAD_AP(RdV, 1, u) 93 #define fGEN_TCG_L4_loadrb_ap(SHORTCODE) \ 94 fGEN_TCG_LOAD_AP(RdV, 1, s) 95 #define fGEN_TCG_L4_loadruh_ap(SHORTCODE) \ 96 fGEN_TCG_LOAD_AP(RdV, 2, u) 97 #define fGEN_TCG_L4_loadrh_ap(SHORTCODE) \ 98 fGEN_TCG_LOAD_AP(RdV, 2, s) 99 #define fGEN_TCG_L4_loadri_ap(SHORTCODE) \ 100 fGEN_TCG_LOAD_AP(RdV, 4, u) 101 #define fGEN_TCG_L4_loadrd_ap(SHORTCODE) \ 102 fGEN_TCG_LOAD_AP(RddV, 8, u) 103 104 #define fGEN_TCG_L2_loadrub_pci(SHORTCODE) SHORTCODE 105 #define fGEN_TCG_L2_loadrb_pci(SHORTCODE) SHORTCODE 106 #define fGEN_TCG_L2_loadruh_pci(SHORTCODE) SHORTCODE 107 #define fGEN_TCG_L2_loadrh_pci(SHORTCODE) SHORTCODE 108 #define fGEN_TCG_L2_loadri_pci(SHORTCODE) SHORTCODE 109 #define fGEN_TCG_L2_loadrd_pci(SHORTCODE) SHORTCODE 110 111 #define fGEN_TCG_LOAD_pcr(SHIFT, LOAD) \ 112 do { \ 113 TCGv ireg = tcg_temp_new(); \ 114 tcg_gen_mov_tl(EA, RxV); \ 115 gen_read_ireg(ireg, MuV, SHIFT); \ 116 gen_helper_fcircadd(RxV, RxV, ireg, MuV, hex_gpr[HEX_REG_CS0 + MuN]); \ 117 LOAD; \ 118 } while (0) 119 120 #define fGEN_TCG_L2_loadrub_pcr(SHORTCODE) \ 121 fGEN_TCG_LOAD_pcr(0, fLOAD(1, 1, u, EA, RdV)) 122 #define fGEN_TCG_L2_loadrb_pcr(SHORTCODE) \ 123 fGEN_TCG_LOAD_pcr(0, fLOAD(1, 1, s, EA, RdV)) 124 #define fGEN_TCG_L2_loadruh_pcr(SHORTCODE) \ 125 fGEN_TCG_LOAD_pcr(1, fLOAD(1, 2, u, EA, RdV)) 126 #define fGEN_TCG_L2_loadrh_pcr(SHORTCODE) \ 127 fGEN_TCG_LOAD_pcr(1, fLOAD(1, 2, s, EA, RdV)) 128 #define fGEN_TCG_L2_loadri_pcr(SHORTCODE) \ 129 fGEN_TCG_LOAD_pcr(2, fLOAD(1, 4, u, EA, RdV)) 130 #define fGEN_TCG_L2_loadrd_pcr(SHORTCODE) \ 131 fGEN_TCG_LOAD_pcr(3, fLOAD(1, 8, u, EA, RddV)) 132 133 #define fGEN_TCG_L2_loadrub_pr(SHORTCODE) SHORTCODE 134 #define fGEN_TCG_L2_loadrub_pbr(SHORTCODE) SHORTCODE 135 #define fGEN_TCG_L2_loadrub_pi(SHORTCODE) SHORTCODE 136 #define fGEN_TCG_L2_loadrb_pr(SHORTCODE) SHORTCODE 137 #define fGEN_TCG_L2_loadrb_pbr(SHORTCODE) SHORTCODE 138 #define fGEN_TCG_L2_loadrb_pi(SHORTCODE) SHORTCODE 139 #define fGEN_TCG_L2_loadruh_pr(SHORTCODE) SHORTCODE 140 #define fGEN_TCG_L2_loadruh_pbr(SHORTCODE) SHORTCODE 141 #define fGEN_TCG_L2_loadruh_pi(SHORTCODE) SHORTCODE 142 #define fGEN_TCG_L2_loadrh_pr(SHORTCODE) SHORTCODE 143 #define fGEN_TCG_L2_loadrh_pbr(SHORTCODE) SHORTCODE 144 #define fGEN_TCG_L2_loadrh_pi(SHORTCODE) SHORTCODE 145 #define fGEN_TCG_L2_loadri_pr(SHORTCODE) SHORTCODE 146 #define fGEN_TCG_L2_loadri_pbr(SHORTCODE) SHORTCODE 147 #define fGEN_TCG_L2_loadri_pi(SHORTCODE) SHORTCODE 148 #define fGEN_TCG_L2_loadrd_pr(SHORTCODE) SHORTCODE 149 #define fGEN_TCG_L2_loadrd_pbr(SHORTCODE) SHORTCODE 150 #define fGEN_TCG_L2_loadrd_pi(SHORTCODE) SHORTCODE 151 152 /* 153 * These instructions load 2 bytes and places them in 154 * two halves of the destination register. 155 * The GET_EA macro determines the addressing mode. 156 * The SIGN argument determines whether to zero-extend or 157 * sign-extend. 158 */ 159 #define fGEN_TCG_loadbXw2(GET_EA, SIGN) \ 160 do { \ 161 TCGv tmp = tcg_temp_new(); \ 162 TCGv byte = tcg_temp_new(); \ 163 GET_EA; \ 164 fLOAD(1, 2, u, EA, tmp); \ 165 tcg_gen_movi_tl(RdV, 0); \ 166 for (int i = 0; i < 2; i++) { \ 167 gen_set_half(i, RdV, gen_get_byte(byte, i, tmp, (SIGN))); \ 168 } \ 169 } while (0) 170 171 #define fGEN_TCG_L2_loadbzw2_io(SHORTCODE) \ 172 fGEN_TCG_loadbXw2(fEA_RI(RsV, siV), false) 173 #define fGEN_TCG_L4_loadbzw2_ur(SHORTCODE) \ 174 fGEN_TCG_loadbXw2(fEA_IRs(UiV, RtV, uiV), false) 175 #define fGEN_TCG_L2_loadbsw2_io(SHORTCODE) \ 176 fGEN_TCG_loadbXw2(fEA_RI(RsV, siV), true) 177 #define fGEN_TCG_L4_loadbsw2_ur(SHORTCODE) \ 178 fGEN_TCG_loadbXw2(fEA_IRs(UiV, RtV, uiV), true) 179 #define fGEN_TCG_L4_loadbzw2_ap(SHORTCODE) \ 180 fGEN_TCG_loadbXw2(GET_EA_ap, false) 181 #define fGEN_TCG_L2_loadbzw2_pr(SHORTCODE) \ 182 fGEN_TCG_loadbXw2(GET_EA_pr, false) 183 #define fGEN_TCG_L2_loadbzw2_pbr(SHORTCODE) \ 184 fGEN_TCG_loadbXw2(GET_EA_pbr, false) 185 #define fGEN_TCG_L2_loadbzw2_pi(SHORTCODE) \ 186 fGEN_TCG_loadbXw2(GET_EA_pi, false) 187 #define fGEN_TCG_L4_loadbsw2_ap(SHORTCODE) \ 188 fGEN_TCG_loadbXw2(GET_EA_ap, true) 189 #define fGEN_TCG_L2_loadbsw2_pr(SHORTCODE) \ 190 fGEN_TCG_loadbXw2(GET_EA_pr, true) 191 #define fGEN_TCG_L2_loadbsw2_pbr(SHORTCODE) \ 192 fGEN_TCG_loadbXw2(GET_EA_pbr, true) 193 #define fGEN_TCG_L2_loadbsw2_pi(SHORTCODE) \ 194 fGEN_TCG_loadbXw2(GET_EA_pi, true) 195 #define fGEN_TCG_L2_loadbzw2_pci(SHORTCODE) \ 196 fGEN_TCG_loadbXw2(GET_EA_pci, false) 197 #define fGEN_TCG_L2_loadbsw2_pci(SHORTCODE) \ 198 fGEN_TCG_loadbXw2(GET_EA_pci, true) 199 #define fGEN_TCG_L2_loadbzw2_pcr(SHORTCODE) \ 200 fGEN_TCG_loadbXw2(GET_EA_pcr(1), false) 201 #define fGEN_TCG_L2_loadbsw2_pcr(SHORTCODE) \ 202 fGEN_TCG_loadbXw2(GET_EA_pcr(1), true) 203 204 /* 205 * These instructions load 4 bytes and places them in 206 * four halves of the destination register pair. 207 * The GET_EA macro determines the addressing mode. 208 * The SIGN argument determines whether to zero-extend or 209 * sign-extend. 210 */ 211 #define fGEN_TCG_loadbXw4(GET_EA, SIGN) \ 212 do { \ 213 TCGv tmp = tcg_temp_new(); \ 214 TCGv byte = tcg_temp_new(); \ 215 GET_EA; \ 216 fLOAD(1, 4, u, EA, tmp); \ 217 tcg_gen_movi_i64(RddV, 0); \ 218 for (int i = 0; i < 4; i++) { \ 219 gen_set_half_i64(i, RddV, gen_get_byte(byte, i, tmp, (SIGN))); \ 220 } \ 221 } while (0) 222 223 #define fGEN_TCG_L2_loadbzw4_io(SHORTCODE) \ 224 fGEN_TCG_loadbXw4(fEA_RI(RsV, siV), false) 225 #define fGEN_TCG_L4_loadbzw4_ur(SHORTCODE) \ 226 fGEN_TCG_loadbXw4(fEA_IRs(UiV, RtV, uiV), false) 227 #define fGEN_TCG_L2_loadbsw4_io(SHORTCODE) \ 228 fGEN_TCG_loadbXw4(fEA_RI(RsV, siV), true) 229 #define fGEN_TCG_L4_loadbsw4_ur(SHORTCODE) \ 230 fGEN_TCG_loadbXw4(fEA_IRs(UiV, RtV, uiV), true) 231 #define fGEN_TCG_L2_loadbzw4_pci(SHORTCODE) \ 232 fGEN_TCG_loadbXw4(GET_EA_pci, false) 233 #define fGEN_TCG_L2_loadbsw4_pci(SHORTCODE) \ 234 fGEN_TCG_loadbXw4(GET_EA_pci, true) 235 #define fGEN_TCG_L2_loadbzw4_pcr(SHORTCODE) \ 236 fGEN_TCG_loadbXw4(GET_EA_pcr(2), false) 237 #define fGEN_TCG_L2_loadbsw4_pcr(SHORTCODE) \ 238 fGEN_TCG_loadbXw4(GET_EA_pcr(2), true) 239 #define fGEN_TCG_L4_loadbzw4_ap(SHORTCODE) \ 240 fGEN_TCG_loadbXw4(GET_EA_ap, false) 241 #define fGEN_TCG_L2_loadbzw4_pr(SHORTCODE) \ 242 fGEN_TCG_loadbXw4(GET_EA_pr, false) 243 #define fGEN_TCG_L2_loadbzw4_pbr(SHORTCODE) \ 244 fGEN_TCG_loadbXw4(GET_EA_pbr, false) 245 #define fGEN_TCG_L2_loadbzw4_pi(SHORTCODE) \ 246 fGEN_TCG_loadbXw4(GET_EA_pi, false) 247 #define fGEN_TCG_L4_loadbsw4_ap(SHORTCODE) \ 248 fGEN_TCG_loadbXw4(GET_EA_ap, true) 249 #define fGEN_TCG_L2_loadbsw4_pr(SHORTCODE) \ 250 fGEN_TCG_loadbXw4(GET_EA_pr, true) 251 #define fGEN_TCG_L2_loadbsw4_pbr(SHORTCODE) \ 252 fGEN_TCG_loadbXw4(GET_EA_pbr, true) 253 #define fGEN_TCG_L2_loadbsw4_pi(SHORTCODE) \ 254 fGEN_TCG_loadbXw4(GET_EA_pi, true) 255 256 /* 257 * These instructions load a half word, shift the destination right by 16 bits 258 * and place the loaded value in the high half word of the destination pair. 259 * The GET_EA macro determines the addressing mode. 260 */ 261 #define fGEN_TCG_loadalignh(GET_EA) \ 262 do { \ 263 TCGv tmp = tcg_temp_new(); \ 264 TCGv_i64 tmp_i64 = tcg_temp_new_i64(); \ 265 GET_EA; \ 266 fLOAD(1, 2, u, EA, tmp); \ 267 tcg_gen_extu_i32_i64(tmp_i64, tmp); \ 268 tcg_gen_shri_i64(RyyV, RyyV, 16); \ 269 tcg_gen_deposit_i64(RyyV, RyyV, tmp_i64, 48, 16); \ 270 } while (0) 271 272 #define fGEN_TCG_L4_loadalignh_ur(SHORTCODE) \ 273 fGEN_TCG_loadalignh(fEA_IRs(UiV, RtV, uiV)) 274 #define fGEN_TCG_L2_loadalignh_io(SHORTCODE) \ 275 fGEN_TCG_loadalignh(fEA_RI(RsV, siV)) 276 #define fGEN_TCG_L2_loadalignh_pci(SHORTCODE) \ 277 fGEN_TCG_loadalignh(GET_EA_pci) 278 #define fGEN_TCG_L2_loadalignh_pcr(SHORTCODE) \ 279 fGEN_TCG_loadalignh(GET_EA_pcr(1)) 280 #define fGEN_TCG_L4_loadalignh_ap(SHORTCODE) \ 281 fGEN_TCG_loadalignh(GET_EA_ap) 282 #define fGEN_TCG_L2_loadalignh_pr(SHORTCODE) \ 283 fGEN_TCG_loadalignh(GET_EA_pr) 284 #define fGEN_TCG_L2_loadalignh_pbr(SHORTCODE) \ 285 fGEN_TCG_loadalignh(GET_EA_pbr) 286 #define fGEN_TCG_L2_loadalignh_pi(SHORTCODE) \ 287 fGEN_TCG_loadalignh(GET_EA_pi) 288 289 /* Same as above, but loads a byte instead of half word */ 290 #define fGEN_TCG_loadalignb(GET_EA) \ 291 do { \ 292 TCGv tmp = tcg_temp_new(); \ 293 TCGv_i64 tmp_i64 = tcg_temp_new_i64(); \ 294 GET_EA; \ 295 fLOAD(1, 1, u, EA, tmp); \ 296 tcg_gen_extu_i32_i64(tmp_i64, tmp); \ 297 tcg_gen_shri_i64(RyyV, RyyV, 8); \ 298 tcg_gen_deposit_i64(RyyV, RyyV, tmp_i64, 56, 8); \ 299 } while (0) 300 301 #define fGEN_TCG_L2_loadalignb_io(SHORTCODE) \ 302 fGEN_TCG_loadalignb(fEA_RI(RsV, siV)) 303 #define fGEN_TCG_L4_loadalignb_ur(SHORTCODE) \ 304 fGEN_TCG_loadalignb(fEA_IRs(UiV, RtV, uiV)) 305 #define fGEN_TCG_L2_loadalignb_pci(SHORTCODE) \ 306 fGEN_TCG_loadalignb(GET_EA_pci) 307 #define fGEN_TCG_L2_loadalignb_pcr(SHORTCODE) \ 308 fGEN_TCG_loadalignb(GET_EA_pcr(0)) 309 #define fGEN_TCG_L4_loadalignb_ap(SHORTCODE) \ 310 fGEN_TCG_loadalignb(GET_EA_ap) 311 #define fGEN_TCG_L2_loadalignb_pr(SHORTCODE) \ 312 fGEN_TCG_loadalignb(GET_EA_pr) 313 #define fGEN_TCG_L2_loadalignb_pbr(SHORTCODE) \ 314 fGEN_TCG_loadalignb(GET_EA_pbr) 315 #define fGEN_TCG_L2_loadalignb_pi(SHORTCODE) \ 316 fGEN_TCG_loadalignb(GET_EA_pi) 317 318 /* 319 * Predicated loads 320 * Here is a primer to understand the tag names 321 * 322 * Predicate used 323 * t true "old" value if (p0) r0 = memb(r2+#0) 324 * f false "old" value if (!p0) r0 = memb(r2+#0) 325 * tnew true "new" value if (p0.new) r0 = memb(r2+#0) 326 * fnew false "new" value if (!p0.new) r0 = memb(r2+#0) 327 */ 328 #define fGEN_TCG_PRED_LOAD(GET_EA, PRED, SIZE, SIGN) \ 329 do { \ 330 TCGv LSB = tcg_temp_new(); \ 331 TCGLabel *label = gen_new_label(); \ 332 tcg_gen_movi_tl(EA, 0); \ 333 PRED; \ 334 CHECK_NOSHUF_PRED(GET_EA, SIZE, LSB); \ 335 PRED_LOAD_CANCEL(LSB, EA); \ 336 tcg_gen_movi_tl(RdV, 0); \ 337 tcg_gen_brcondi_tl(TCG_COND_EQ, LSB, 0, label); \ 338 fLOAD(1, SIZE, SIGN, EA, RdV); \ 339 gen_set_label(label); \ 340 } while (0) 341 342 #define fGEN_TCG_L2_ploadrubt_pi(SHORTCODE) \ 343 fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLD(PtV), 1, u) 344 #define fGEN_TCG_L2_ploadrubf_pi(SHORTCODE) \ 345 fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLDNOT(PtV), 1, u) 346 #define fGEN_TCG_L2_ploadrubtnew_pi(SHORTCODE) \ 347 fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBNEW(PtN), 1, u) 348 #define fGEN_TCG_L2_ploadrubfnew_pi(SHORTCODE) \ 349 fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBNEWNOT(PtN), 1, u) 350 #define fGEN_TCG_L2_ploadrbt_pi(SHORTCODE) \ 351 fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLD(PtV), 1, s) 352 #define fGEN_TCG_L2_ploadrbf_pi(SHORTCODE) \ 353 fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLDNOT(PtV), 1, s) 354 #define fGEN_TCG_L2_ploadrbtnew_pi(SHORTCODE) \ 355 fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBNEW(PtN), 1, s) 356 #define fGEN_TCG_L2_ploadrbfnew_pi(SHORTCODE) \ 357 fGEN_TCG_PRED_LOAD({ fEA_REG(RxV); fPM_I(RxV, siV); }, \ 358 fLSBNEWNOT(PtN), 1, s) 359 360 #define fGEN_TCG_L2_ploadruht_pi(SHORTCODE) \ 361 fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLD(PtV), 2, u) 362 #define fGEN_TCG_L2_ploadruhf_pi(SHORTCODE) \ 363 fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLDNOT(PtV), 2, u) 364 #define fGEN_TCG_L2_ploadruhtnew_pi(SHORTCODE) \ 365 fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBNEW(PtN), 2, u) 366 #define fGEN_TCG_L2_ploadruhfnew_pi(SHORTCODE) \ 367 fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBNEWNOT(PtN), 2, u) 368 #define fGEN_TCG_L2_ploadrht_pi(SHORTCODE) \ 369 fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLD(PtV), 2, s) 370 #define fGEN_TCG_L2_ploadrhf_pi(SHORTCODE) \ 371 fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLDNOT(PtV), 2, s) 372 #define fGEN_TCG_L2_ploadrhtnew_pi(SHORTCODE) \ 373 fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBNEW(PtN), 2, s) 374 #define fGEN_TCG_L2_ploadrhfnew_pi(SHORTCODE) \ 375 fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBNEWNOT(PtN), 2, s) 376 377 #define fGEN_TCG_L2_ploadrit_pi(SHORTCODE) \ 378 fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLD(PtV), 4, u) 379 #define fGEN_TCG_L2_ploadrif_pi(SHORTCODE) \ 380 fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLDNOT(PtV), 4, u) 381 #define fGEN_TCG_L2_ploadritnew_pi(SHORTCODE) \ 382 fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBNEW(PtN), 4, u) 383 #define fGEN_TCG_L2_ploadrifnew_pi(SHORTCODE) \ 384 fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBNEWNOT(PtN), 4, u) 385 386 /* Predicated loads into a register pair */ 387 #define fGEN_TCG_PRED_LOAD_PAIR(GET_EA, PRED) \ 388 do { \ 389 TCGv LSB = tcg_temp_new(); \ 390 TCGLabel *label = gen_new_label(); \ 391 tcg_gen_movi_tl(EA, 0); \ 392 PRED; \ 393 CHECK_NOSHUF_PRED(GET_EA, 8, LSB); \ 394 PRED_LOAD_CANCEL(LSB, EA); \ 395 tcg_gen_movi_i64(RddV, 0); \ 396 tcg_gen_brcondi_tl(TCG_COND_EQ, LSB, 0, label); \ 397 fLOAD(1, 8, u, EA, RddV); \ 398 gen_set_label(label); \ 399 } while (0) 400 401 #define fGEN_TCG_L2_ploadrdt_pi(SHORTCODE) \ 402 fGEN_TCG_PRED_LOAD_PAIR(GET_EA_pi, fLSBOLD(PtV)) 403 #define fGEN_TCG_L2_ploadrdf_pi(SHORTCODE) \ 404 fGEN_TCG_PRED_LOAD_PAIR(GET_EA_pi, fLSBOLDNOT(PtV)) 405 #define fGEN_TCG_L2_ploadrdtnew_pi(SHORTCODE) \ 406 fGEN_TCG_PRED_LOAD_PAIR(GET_EA_pi, fLSBNEW(PtN)) 407 #define fGEN_TCG_L2_ploadrdfnew_pi(SHORTCODE) \ 408 fGEN_TCG_PRED_LOAD_PAIR(GET_EA_pi, fLSBNEWNOT(PtN)) 409 410 /* load-locked and store-locked */ 411 #define fGEN_TCG_L2_loadw_locked(SHORTCODE) \ 412 SHORTCODE 413 #define fGEN_TCG_L4_loadd_locked(SHORTCODE) \ 414 SHORTCODE 415 #define fGEN_TCG_S2_storew_locked(SHORTCODE) \ 416 SHORTCODE 417 #define fGEN_TCG_S4_stored_locked(SHORTCODE) \ 418 SHORTCODE 419 420 #define fGEN_TCG_STORE(SHORTCODE) \ 421 do { \ 422 TCGv HALF = tcg_temp_new(); \ 423 TCGv BYTE = tcg_temp_new(); \ 424 SHORTCODE; \ 425 } while (0) 426 427 #define fGEN_TCG_STORE_pcr(SHIFT, STORE) \ 428 do { \ 429 TCGv ireg = tcg_temp_new(); \ 430 TCGv HALF = tcg_temp_new(); \ 431 TCGv BYTE = tcg_temp_new(); \ 432 tcg_gen_mov_tl(EA, RxV); \ 433 gen_read_ireg(ireg, MuV, SHIFT); \ 434 gen_helper_fcircadd(RxV, RxV, ireg, MuV, hex_gpr[HEX_REG_CS0 + MuN]); \ 435 STORE; \ 436 } while (0) 437 438 #define fGEN_TCG_S2_storerb_pbr(SHORTCODE) \ 439 fGEN_TCG_STORE(SHORTCODE) 440 #define fGEN_TCG_S2_storerb_pci(SHORTCODE) \ 441 fGEN_TCG_STORE(SHORTCODE) 442 #define fGEN_TCG_S2_storerb_pcr(SHORTCODE) \ 443 fGEN_TCG_STORE_pcr(0, fSTORE(1, 1, EA, fGETBYTE(0, RtV))) 444 445 #define fGEN_TCG_S2_storerh_pbr(SHORTCODE) \ 446 fGEN_TCG_STORE(SHORTCODE) 447 #define fGEN_TCG_S2_storerh_pci(SHORTCODE) \ 448 fGEN_TCG_STORE(SHORTCODE) 449 #define fGEN_TCG_S2_storerh_pcr(SHORTCODE) \ 450 fGEN_TCG_STORE_pcr(1, fSTORE(1, 2, EA, fGETHALF(0, RtV))) 451 452 #define fGEN_TCG_S2_storerf_pbr(SHORTCODE) \ 453 fGEN_TCG_STORE(SHORTCODE) 454 #define fGEN_TCG_S2_storerf_pci(SHORTCODE) \ 455 fGEN_TCG_STORE(SHORTCODE) 456 #define fGEN_TCG_S2_storerf_pcr(SHORTCODE) \ 457 fGEN_TCG_STORE_pcr(1, fSTORE(1, 2, EA, fGETHALF(1, RtV))) 458 459 #define fGEN_TCG_S2_storeri_pbr(SHORTCODE) \ 460 fGEN_TCG_STORE(SHORTCODE) 461 #define fGEN_TCG_S2_storeri_pci(SHORTCODE) \ 462 fGEN_TCG_STORE(SHORTCODE) 463 #define fGEN_TCG_S2_storeri_pcr(SHORTCODE) \ 464 fGEN_TCG_STORE_pcr(2, fSTORE(1, 4, EA, RtV)) 465 466 #define fGEN_TCG_S2_storerd_pbr(SHORTCODE) \ 467 fGEN_TCG_STORE(SHORTCODE) 468 #define fGEN_TCG_S2_storerd_pci(SHORTCODE) \ 469 fGEN_TCG_STORE(SHORTCODE) 470 #define fGEN_TCG_S2_storerd_pcr(SHORTCODE) \ 471 fGEN_TCG_STORE_pcr(3, fSTORE(1, 8, EA, RttV)) 472 473 #define fGEN_TCG_S2_storerbnew_pbr(SHORTCODE) \ 474 fGEN_TCG_STORE(SHORTCODE) 475 #define fGEN_TCG_S2_storerbnew_pci(SHORTCODE) \ 476 fGEN_TCG_STORE(SHORTCODE) 477 #define fGEN_TCG_S2_storerbnew_pcr(SHORTCODE) \ 478 fGEN_TCG_STORE_pcr(0, fSTORE(1, 1, EA, fGETBYTE(0, NtN))) 479 480 #define fGEN_TCG_S2_storerhnew_pbr(SHORTCODE) \ 481 fGEN_TCG_STORE(SHORTCODE) 482 #define fGEN_TCG_S2_storerhnew_pci(SHORTCODE) \ 483 fGEN_TCG_STORE(SHORTCODE) 484 #define fGEN_TCG_S2_storerhnew_pcr(SHORTCODE) \ 485 fGEN_TCG_STORE_pcr(1, fSTORE(1, 2, EA, fGETHALF(0, NtN))) 486 487 #define fGEN_TCG_S2_storerinew_pbr(SHORTCODE) \ 488 fGEN_TCG_STORE(SHORTCODE) 489 #define fGEN_TCG_S2_storerinew_pci(SHORTCODE) \ 490 fGEN_TCG_STORE(SHORTCODE) 491 #define fGEN_TCG_S2_storerinew_pcr(SHORTCODE) \ 492 fGEN_TCG_STORE_pcr(2, fSTORE(1, 4, EA, NtN)) 493 494 /* 495 * Mathematical operations with more than one definition require 496 * special handling 497 */ 498 #define fGEN_TCG_A5_ACS(SHORTCODE) \ 499 do { \ 500 gen_helper_vacsh_pred(PeV, cpu_env, RxxV, RssV, RttV); \ 501 gen_helper_vacsh_val(RxxV, cpu_env, RxxV, RssV, RttV); \ 502 } while (0) 503 504 /* 505 * Approximate reciprocal 506 * r3,p1 = sfrecipa(r0, r1) 507 * 508 * The helper packs the 2 32-bit results into a 64-bit value, 509 * so unpack them into the proper results. 510 */ 511 #define fGEN_TCG_F2_sfrecipa(SHORTCODE) \ 512 do { \ 513 TCGv_i64 tmp = tcg_temp_new_i64(); \ 514 gen_helper_sfrecipa(tmp, cpu_env, RsV, RtV); \ 515 tcg_gen_extrh_i64_i32(RdV, tmp); \ 516 tcg_gen_extrl_i64_i32(PeV, tmp); \ 517 } while (0) 518 519 /* 520 * Approximation of the reciprocal square root 521 * r1,p0 = sfinvsqrta(r0) 522 * 523 * The helper packs the 2 32-bit results into a 64-bit value, 524 * so unpack them into the proper results. 525 */ 526 #define fGEN_TCG_F2_sfinvsqrta(SHORTCODE) \ 527 do { \ 528 TCGv_i64 tmp = tcg_temp_new_i64(); \ 529 gen_helper_sfinvsqrta(tmp, cpu_env, RsV); \ 530 tcg_gen_extrh_i64_i32(RdV, tmp); \ 531 tcg_gen_extrl_i64_i32(PeV, tmp); \ 532 } while (0) 533 534 /* 535 * Add or subtract with carry. 536 * Predicate register is used as an extra input and output. 537 * r5:4 = add(r1:0, r3:2, p1):carry 538 */ 539 #define fGEN_TCG_A4_addp_c(SHORTCODE) \ 540 do { \ 541 TCGv_i64 carry = tcg_temp_new_i64(); \ 542 TCGv_i64 zero = tcg_constant_i64(0); \ 543 tcg_gen_extu_i32_i64(carry, PxV); \ 544 tcg_gen_andi_i64(carry, carry, 1); \ 545 tcg_gen_add2_i64(RddV, carry, RssV, zero, carry, zero); \ 546 tcg_gen_add2_i64(RddV, carry, RddV, carry, RttV, zero); \ 547 tcg_gen_extrl_i64_i32(PxV, carry); \ 548 gen_8bitsof(PxV, PxV); \ 549 } while (0) 550 551 /* r5:4 = sub(r1:0, r3:2, p1):carry */ 552 #define fGEN_TCG_A4_subp_c(SHORTCODE) \ 553 do { \ 554 TCGv_i64 carry = tcg_temp_new_i64(); \ 555 TCGv_i64 zero = tcg_constant_i64(0); \ 556 TCGv_i64 not_RttV = tcg_temp_new_i64(); \ 557 tcg_gen_extu_i32_i64(carry, PxV); \ 558 tcg_gen_andi_i64(carry, carry, 1); \ 559 tcg_gen_not_i64(not_RttV, RttV); \ 560 tcg_gen_add2_i64(RddV, carry, RssV, zero, carry, zero); \ 561 tcg_gen_add2_i64(RddV, carry, RddV, carry, not_RttV, zero); \ 562 tcg_gen_extrl_i64_i32(PxV, carry); \ 563 gen_8bitsof(PxV, PxV); \ 564 } while (0) 565 566 /* 567 * Compare each of the 8 unsigned bytes 568 * The minimum is placed in each byte of the destination. 569 * Each bit of the predicate is set true if the bit from the first operand 570 * is greater than the bit from the second operand. 571 * r5:4,p1 = vminub(r1:0, r3:2) 572 */ 573 #define fGEN_TCG_A6_vminub_RdP(SHORTCODE) \ 574 do { \ 575 TCGv left = tcg_temp_new(); \ 576 TCGv right = tcg_temp_new(); \ 577 TCGv tmp = tcg_temp_new(); \ 578 tcg_gen_movi_tl(PeV, 0); \ 579 tcg_gen_movi_i64(RddV, 0); \ 580 for (int i = 0; i < 8; i++) { \ 581 gen_get_byte_i64(left, i, RttV, false); \ 582 gen_get_byte_i64(right, i, RssV, false); \ 583 tcg_gen_setcond_tl(TCG_COND_GT, tmp, left, right); \ 584 tcg_gen_deposit_tl(PeV, PeV, tmp, i, 1); \ 585 tcg_gen_umin_tl(tmp, left, right); \ 586 gen_set_byte_i64(i, RddV, tmp); \ 587 } \ 588 } while (0) 589 590 #define fGEN_TCG_J2_call(SHORTCODE) \ 591 gen_call(ctx, riV) 592 593 #define fGEN_TCG_J2_callt(SHORTCODE) \ 594 gen_cond_call(ctx, PuV, TCG_COND_EQ, riV) 595 #define fGEN_TCG_J2_callf(SHORTCODE) \ 596 gen_cond_call(ctx, PuV, TCG_COND_NE, riV) 597 598 #define fGEN_TCG_J2_endloop0(SHORTCODE) \ 599 gen_endloop0(ctx) 600 601 /* 602 * Compound compare and jump instructions 603 * Here is a primer to understand the tag names 604 * 605 * Comparison 606 * cmpeqi compare equal to an immediate 607 * cmpgti compare greater than an immediate 608 * cmpgtiu compare greater than an unsigned immediate 609 * cmpeqn1 compare equal to negative 1 610 * cmpgtn1 compare greater than negative 1 611 * cmpeq compare equal (two registers) 612 * cmpgtu compare greater than unsigned (two registers) 613 * tstbit0 test bit zero 614 * 615 * Condition 616 * tp0 p0 is true p0 = cmp.eq(r0,#5); if (p0.new) jump:nt address 617 * fp0 p0 is false p0 = cmp.eq(r0,#5); if (!p0.new) jump:nt address 618 * tp1 p1 is true p1 = cmp.eq(r0,#5); if (p1.new) jump:nt address 619 * fp1 p1 is false p1 = cmp.eq(r0,#5); if (!p1.new) jump:nt address 620 * 621 * Prediction (not modelled in qemu) 622 * _nt not taken 623 * _t taken 624 */ 625 #define fGEN_TCG_J4_cmpeq_tp0_jump_t(SHORTCODE) \ 626 gen_cmpnd_cmp_jmp_t(ctx, 0, TCG_COND_EQ, RsV, RtV, riV) 627 #define fGEN_TCG_J4_cmpeq_tp0_jump_nt(SHORTCODE) \ 628 gen_cmpnd_cmp_jmp_t(ctx, 0, TCG_COND_EQ, RsV, RtV, riV) 629 #define fGEN_TCG_J4_cmpeq_fp0_jump_t(SHORTCODE) \ 630 gen_cmpnd_cmp_jmp_f(ctx, 0, TCG_COND_EQ, RsV, RtV, riV) 631 #define fGEN_TCG_J4_cmpeq_fp0_jump_nt(SHORTCODE) \ 632 gen_cmpnd_cmp_jmp_f(ctx, 0, TCG_COND_EQ, RsV, RtV, riV) 633 #define fGEN_TCG_J4_cmpeq_tp1_jump_t(SHORTCODE) \ 634 gen_cmpnd_cmp_jmp_t(ctx, 1, TCG_COND_EQ, RsV, RtV, riV) 635 #define fGEN_TCG_J4_cmpeq_tp1_jump_nt(SHORTCODE) \ 636 gen_cmpnd_cmp_jmp_t(ctx, 1, TCG_COND_EQ, RsV, RtV, riV) 637 #define fGEN_TCG_J4_cmpeq_fp1_jump_t(SHORTCODE) \ 638 gen_cmpnd_cmp_jmp_f(ctx, 1, TCG_COND_EQ, RsV, RtV, riV) 639 #define fGEN_TCG_J4_cmpeq_fp1_jump_nt(SHORTCODE) \ 640 gen_cmpnd_cmp_jmp_f(ctx, 1, TCG_COND_EQ, RsV, RtV, riV) 641 642 #define fGEN_TCG_J4_cmpgt_tp0_jump_t(SHORTCODE) \ 643 gen_cmpnd_cmp_jmp_t(ctx, 0, TCG_COND_GT, RsV, RtV, riV) 644 #define fGEN_TCG_J4_cmpgt_tp0_jump_nt(SHORTCODE) \ 645 gen_cmpnd_cmp_jmp_t(ctx, 0, TCG_COND_GT, RsV, RtV, riV) 646 #define fGEN_TCG_J4_cmpgt_fp0_jump_t(SHORTCODE) \ 647 gen_cmpnd_cmp_jmp_f(ctx, 0, TCG_COND_GT, RsV, RtV, riV) 648 #define fGEN_TCG_J4_cmpgt_fp0_jump_nt(SHORTCODE) \ 649 gen_cmpnd_cmp_jmp_f(ctx, 0, TCG_COND_GT, RsV, RtV, riV) 650 #define fGEN_TCG_J4_cmpgt_tp1_jump_t(SHORTCODE) \ 651 gen_cmpnd_cmp_jmp_t(ctx, 1, TCG_COND_GT, RsV, RtV, riV) 652 #define fGEN_TCG_J4_cmpgt_tp1_jump_nt(SHORTCODE) \ 653 gen_cmpnd_cmp_jmp_t(ctx, 1, TCG_COND_GT, RsV, RtV, riV) 654 #define fGEN_TCG_J4_cmpgt_fp1_jump_t(SHORTCODE) \ 655 gen_cmpnd_cmp_jmp_f(ctx, 1, TCG_COND_GT, RsV, RtV, riV) 656 #define fGEN_TCG_J4_cmpgt_fp1_jump_nt(SHORTCODE) \ 657 gen_cmpnd_cmp_jmp_f(ctx, 1, TCG_COND_GT, RsV, RtV, riV) 658 659 #define fGEN_TCG_J4_cmpgtu_tp0_jump_t(SHORTCODE) \ 660 gen_cmpnd_cmp_jmp_t(ctx, 0, TCG_COND_GTU, RsV, RtV, riV) 661 #define fGEN_TCG_J4_cmpgtu_tp0_jump_nt(SHORTCODE) \ 662 gen_cmpnd_cmp_jmp_t(ctx, 0, TCG_COND_GTU, RsV, RtV, riV) 663 #define fGEN_TCG_J4_cmpgtu_fp0_jump_t(SHORTCODE) \ 664 gen_cmpnd_cmp_jmp_f(ctx, 0, TCG_COND_GTU, RsV, RtV, riV) 665 #define fGEN_TCG_J4_cmpgtu_fp0_jump_nt(SHORTCODE) \ 666 gen_cmpnd_cmp_jmp_f(ctx, 0, TCG_COND_GTU, RsV, RtV, riV) 667 #define fGEN_TCG_J4_cmpgtu_tp1_jump_t(SHORTCODE) \ 668 gen_cmpnd_cmp_jmp_t(ctx, 1, TCG_COND_GTU, RsV, RtV, riV) 669 #define fGEN_TCG_J4_cmpgtu_tp1_jump_nt(SHORTCODE) \ 670 gen_cmpnd_cmp_jmp_t(ctx, 1, TCG_COND_GTU, RsV, RtV, riV) 671 #define fGEN_TCG_J4_cmpgtu_fp1_jump_t(SHORTCODE) \ 672 gen_cmpnd_cmp_jmp_f(ctx, 1, TCG_COND_GTU, RsV, RtV, riV) 673 #define fGEN_TCG_J4_cmpgtu_fp1_jump_nt(SHORTCODE) \ 674 gen_cmpnd_cmp_jmp_f(ctx, 1, TCG_COND_GTU, RsV, RtV, riV) 675 676 #define fGEN_TCG_J4_cmpeqi_tp0_jump_t(SHORTCODE) \ 677 gen_cmpnd_cmpi_jmp_t(ctx, 0, TCG_COND_EQ, RsV, UiV, riV) 678 #define fGEN_TCG_J4_cmpeqi_tp0_jump_nt(SHORTCODE) \ 679 gen_cmpnd_cmpi_jmp_t(ctx, 0, TCG_COND_EQ, RsV, UiV, riV) 680 #define fGEN_TCG_J4_cmpeqi_fp0_jump_t(SHORTCODE) \ 681 gen_cmpnd_cmpi_jmp_f(ctx, 0, TCG_COND_EQ, RsV, UiV, riV) 682 #define fGEN_TCG_J4_cmpeqi_fp0_jump_nt(SHORTCODE) \ 683 gen_cmpnd_cmpi_jmp_f(ctx, 0, TCG_COND_EQ, RsV, UiV, riV) 684 #define fGEN_TCG_J4_cmpeqi_tp1_jump_t(SHORTCODE) \ 685 gen_cmpnd_cmpi_jmp_t(ctx, 1, TCG_COND_EQ, RsV, UiV, riV) 686 #define fGEN_TCG_J4_cmpeqi_tp1_jump_nt(SHORTCODE) \ 687 gen_cmpnd_cmpi_jmp_t(ctx, 1, TCG_COND_EQ, RsV, UiV, riV) 688 #define fGEN_TCG_J4_cmpeqi_fp1_jump_t(SHORTCODE) \ 689 gen_cmpnd_cmpi_jmp_f(ctx, 1, TCG_COND_EQ, RsV, UiV, riV) 690 #define fGEN_TCG_J4_cmpeqi_fp1_jump_nt(SHORTCODE) \ 691 gen_cmpnd_cmpi_jmp_f(ctx, 1, TCG_COND_EQ, RsV, UiV, riV) 692 693 #define fGEN_TCG_J4_cmpgti_tp0_jump_t(SHORTCODE) \ 694 gen_cmpnd_cmpi_jmp_t(ctx, 0, TCG_COND_GT, RsV, UiV, riV) 695 #define fGEN_TCG_J4_cmpgti_tp0_jump_nt(SHORTCODE) \ 696 gen_cmpnd_cmpi_jmp_t(ctx, 0, TCG_COND_GT, RsV, UiV, riV) 697 #define fGEN_TCG_J4_cmpgti_fp0_jump_t(SHORTCODE) \ 698 gen_cmpnd_cmpi_jmp_f(ctx, 0, TCG_COND_GT, RsV, UiV, riV) 699 #define fGEN_TCG_J4_cmpgti_fp0_jump_nt(SHORTCODE) \ 700 gen_cmpnd_cmpi_jmp_f(ctx, 0, TCG_COND_GT, RsV, UiV, riV) 701 #define fGEN_TCG_J4_cmpgti_tp1_jump_t(SHORTCODE) \ 702 gen_cmpnd_cmpi_jmp_t(ctx, 1, TCG_COND_GT, RsV, UiV, riV) 703 #define fGEN_TCG_J4_cmpgti_tp1_jump_nt(SHORTCODE) \ 704 gen_cmpnd_cmpi_jmp_t(ctx, 1, TCG_COND_GT, RsV, UiV, riV) 705 #define fGEN_TCG_J4_cmpgti_fp1_jump_t(SHORTCODE) \ 706 gen_cmpnd_cmpi_jmp_f(ctx, 1, TCG_COND_GT, RsV, UiV, riV) 707 #define fGEN_TCG_J4_cmpgti_fp1_jump_nt(SHORTCODE) \ 708 gen_cmpnd_cmpi_jmp_f(ctx, 1, TCG_COND_GT, RsV, UiV, riV) 709 710 #define fGEN_TCG_J4_cmpgtui_tp0_jump_t(SHORTCODE) \ 711 gen_cmpnd_cmpi_jmp_t(ctx, 0, TCG_COND_GTU, RsV, UiV, riV) 712 #define fGEN_TCG_J4_cmpgtui_tp0_jump_nt(SHORTCODE) \ 713 gen_cmpnd_cmpi_jmp_t(ctx, 0, TCG_COND_GTU, RsV, UiV, riV) 714 #define fGEN_TCG_J4_cmpgtui_fp0_jump_t(SHORTCODE) \ 715 gen_cmpnd_cmpi_jmp_f(ctx, 0, TCG_COND_GTU, RsV, UiV, riV) 716 #define fGEN_TCG_J4_cmpgtui_fp0_jump_nt(SHORTCODE) \ 717 gen_cmpnd_cmpi_jmp_f(ctx, 0, TCG_COND_GTU, RsV, UiV, riV) 718 #define fGEN_TCG_J4_cmpgtui_tp1_jump_t(SHORTCODE) \ 719 gen_cmpnd_cmpi_jmp_t(ctx, 1, TCG_COND_GTU, RsV, UiV, riV) 720 #define fGEN_TCG_J4_cmpgtui_tp1_jump_nt(SHORTCODE) \ 721 gen_cmpnd_cmpi_jmp_t(ctx, 1, TCG_COND_GTU, RsV, UiV, riV) 722 #define fGEN_TCG_J4_cmpgtui_fp1_jump_t(SHORTCODE) \ 723 gen_cmpnd_cmpi_jmp_f(ctx, 1, TCG_COND_GTU, RsV, UiV, riV) 724 #define fGEN_TCG_J4_cmpgtui_fp1_jump_nt(SHORTCODE) \ 725 gen_cmpnd_cmpi_jmp_f(ctx, 1, TCG_COND_GTU, RsV, UiV, riV) 726 727 #define fGEN_TCG_J4_cmpeqn1_tp0_jump_t(SHORTCODE) \ 728 gen_cmpnd_cmp_n1_jmp_t(ctx, 0, TCG_COND_EQ, RsV, riV) 729 #define fGEN_TCG_J4_cmpeqn1_tp0_jump_nt(SHORTCODE) \ 730 gen_cmpnd_cmp_n1_jmp_t(ctx, 0, TCG_COND_EQ, RsV, riV) 731 #define fGEN_TCG_J4_cmpeqn1_fp0_jump_t(SHORTCODE) \ 732 gen_cmpnd_cmp_n1_jmp_f(ctx, 0, TCG_COND_EQ, RsV, riV) 733 #define fGEN_TCG_J4_cmpeqn1_fp0_jump_nt(SHORTCODE) \ 734 gen_cmpnd_cmp_n1_jmp_f(ctx, 0, TCG_COND_EQ, RsV, riV) 735 #define fGEN_TCG_J4_cmpeqn1_tp1_jump_t(SHORTCODE) \ 736 gen_cmpnd_cmp_n1_jmp_t(ctx, 1, TCG_COND_EQ, RsV, riV) 737 #define fGEN_TCG_J4_cmpeqn1_tp1_jump_nt(SHORTCODE) \ 738 gen_cmpnd_cmp_n1_jmp_t(ctx, 1, TCG_COND_EQ, RsV, riV) 739 #define fGEN_TCG_J4_cmpeqn1_fp1_jump_t(SHORTCODE) \ 740 gen_cmpnd_cmp_n1_jmp_f(ctx, 1, TCG_COND_EQ, RsV, riV) 741 #define fGEN_TCG_J4_cmpeqn1_fp1_jump_nt(SHORTCODE) \ 742 gen_cmpnd_cmp_n1_jmp_f(ctx, 1, TCG_COND_EQ, RsV, riV) 743 744 #define fGEN_TCG_J4_cmpgtn1_tp0_jump_t(SHORTCODE) \ 745 gen_cmpnd_cmp_n1_jmp_t(ctx, 0, TCG_COND_GT, RsV, riV) 746 #define fGEN_TCG_J4_cmpgtn1_tp0_jump_nt(SHORTCODE) \ 747 gen_cmpnd_cmp_n1_jmp_t(ctx, 0, TCG_COND_GT, RsV, riV) 748 #define fGEN_TCG_J4_cmpgtn1_fp0_jump_t(SHORTCODE) \ 749 gen_cmpnd_cmp_n1_jmp_f(ctx, 0, TCG_COND_GT, RsV, riV) 750 #define fGEN_TCG_J4_cmpgtn1_fp0_jump_nt(SHORTCODE) \ 751 gen_cmpnd_cmp_n1_jmp_f(ctx, 0, TCG_COND_GT, RsV, riV) 752 #define fGEN_TCG_J4_cmpgtn1_tp1_jump_t(SHORTCODE) \ 753 gen_cmpnd_cmp_n1_jmp_t(ctx, 1, TCG_COND_GT, RsV, riV) 754 #define fGEN_TCG_J4_cmpgtn1_tp1_jump_nt(SHORTCODE) \ 755 gen_cmpnd_cmp_n1_jmp_t(ctx, 1, TCG_COND_GT, RsV, riV) 756 #define fGEN_TCG_J4_cmpgtn1_fp1_jump_t(SHORTCODE) \ 757 gen_cmpnd_cmp_n1_jmp_f(ctx, 1, TCG_COND_GT, RsV, riV) 758 #define fGEN_TCG_J4_cmpgtn1_fp1_jump_nt(SHORTCODE) \ 759 gen_cmpnd_cmp_n1_jmp_f(ctx, 1, TCG_COND_GT, RsV, riV) 760 761 #define fGEN_TCG_J4_tstbit0_tp0_jump_nt(SHORTCODE) \ 762 gen_cmpnd_tstbit0_jmp(ctx, 0, RsV, TCG_COND_EQ, riV) 763 #define fGEN_TCG_J4_tstbit0_tp0_jump_t(SHORTCODE) \ 764 gen_cmpnd_tstbit0_jmp(ctx, 0, RsV, TCG_COND_EQ, riV) 765 #define fGEN_TCG_J4_tstbit0_fp0_jump_nt(SHORTCODE) \ 766 gen_cmpnd_tstbit0_jmp(ctx, 0, RsV, TCG_COND_NE, riV) 767 #define fGEN_TCG_J4_tstbit0_fp0_jump_t(SHORTCODE) \ 768 gen_cmpnd_tstbit0_jmp(ctx, 0, RsV, TCG_COND_NE, riV) 769 #define fGEN_TCG_J4_tstbit0_tp1_jump_nt(SHORTCODE) \ 770 gen_cmpnd_tstbit0_jmp(ctx, 1, RsV, TCG_COND_EQ, riV) 771 #define fGEN_TCG_J4_tstbit0_tp1_jump_t(SHORTCODE) \ 772 gen_cmpnd_tstbit0_jmp(ctx, 1, RsV, TCG_COND_EQ, riV) 773 #define fGEN_TCG_J4_tstbit0_fp1_jump_nt(SHORTCODE) \ 774 gen_cmpnd_tstbit0_jmp(ctx, 1, RsV, TCG_COND_NE, riV) 775 #define fGEN_TCG_J4_tstbit0_fp1_jump_t(SHORTCODE) \ 776 gen_cmpnd_tstbit0_jmp(ctx, 1, RsV, TCG_COND_NE, riV) 777 778 #define fGEN_TCG_J2_jump(SHORTCODE) \ 779 gen_jump(ctx, riV) 780 #define fGEN_TCG_J2_jumpr(SHORTCODE) \ 781 gen_jumpr(ctx, RsV) 782 #define fGEN_TCG_J4_jumpseti(SHORTCODE) \ 783 do { \ 784 tcg_gen_movi_tl(RdV, UiV); \ 785 gen_jump(ctx, riV); \ 786 } while (0) 787 788 #define fGEN_TCG_cond_jumpt(COND) \ 789 do { \ 790 TCGv LSB = tcg_temp_new(); \ 791 COND; \ 792 gen_cond_jump(ctx, TCG_COND_EQ, LSB, riV); \ 793 } while (0) 794 #define fGEN_TCG_cond_jumpf(COND) \ 795 do { \ 796 TCGv LSB = tcg_temp_new(); \ 797 COND; \ 798 gen_cond_jump(ctx, TCG_COND_NE, LSB, riV); \ 799 } while (0) 800 801 #define fGEN_TCG_J2_jumpt(SHORTCODE) \ 802 fGEN_TCG_cond_jumpt(fLSBOLD(PuV)) 803 #define fGEN_TCG_J2_jumptpt(SHORTCODE) \ 804 fGEN_TCG_cond_jumpt(fLSBOLD(PuV)) 805 #define fGEN_TCG_J2_jumpf(SHORTCODE) \ 806 fGEN_TCG_cond_jumpf(fLSBOLD(PuV)) 807 #define fGEN_TCG_J2_jumpfpt(SHORTCODE) \ 808 fGEN_TCG_cond_jumpf(fLSBOLD(PuV)) 809 #define fGEN_TCG_J2_jumptnew(SHORTCODE) \ 810 gen_cond_jump(ctx, TCG_COND_EQ, PuN, riV) 811 #define fGEN_TCG_J2_jumptnewpt(SHORTCODE) \ 812 gen_cond_jump(ctx, TCG_COND_EQ, PuN, riV) 813 #define fGEN_TCG_J2_jumpfnewpt(SHORTCODE) \ 814 fGEN_TCG_cond_jumpf(fLSBNEW(PuN)) 815 #define fGEN_TCG_J2_jumpfnew(SHORTCODE) \ 816 fGEN_TCG_cond_jumpf(fLSBNEW(PuN)) 817 #define fGEN_TCG_J2_jumprz(SHORTCODE) \ 818 fGEN_TCG_cond_jumpt(tcg_gen_setcondi_tl(TCG_COND_NE, LSB, RsV, 0)) 819 #define fGEN_TCG_J2_jumprzpt(SHORTCODE) \ 820 fGEN_TCG_cond_jumpt(tcg_gen_setcondi_tl(TCG_COND_NE, LSB, RsV, 0)) 821 #define fGEN_TCG_J2_jumprnz(SHORTCODE) \ 822 fGEN_TCG_cond_jumpt(tcg_gen_setcondi_tl(TCG_COND_EQ, LSB, RsV, 0)) 823 #define fGEN_TCG_J2_jumprnzpt(SHORTCODE) \ 824 fGEN_TCG_cond_jumpt(tcg_gen_setcondi_tl(TCG_COND_EQ, LSB, RsV, 0)) 825 #define fGEN_TCG_J2_jumprgtez(SHORTCODE) \ 826 fGEN_TCG_cond_jumpt(tcg_gen_setcondi_tl(TCG_COND_GE, LSB, RsV, 0)) 827 #define fGEN_TCG_J2_jumprgtezpt(SHORTCODE) \ 828 fGEN_TCG_cond_jumpt(tcg_gen_setcondi_tl(TCG_COND_GE, LSB, RsV, 0)) 829 #define fGEN_TCG_J2_jumprltez(SHORTCODE) \ 830 fGEN_TCG_cond_jumpt(tcg_gen_setcondi_tl(TCG_COND_LE, LSB, RsV, 0)) 831 #define fGEN_TCG_J2_jumprltezpt(SHORTCODE) \ 832 fGEN_TCG_cond_jumpt(tcg_gen_setcondi_tl(TCG_COND_LE, LSB, RsV, 0)) 833 834 #define fGEN_TCG_cond_jumprt(COND) \ 835 do { \ 836 TCGv LSB = tcg_temp_new(); \ 837 COND; \ 838 gen_cond_jumpr(ctx, RsV, TCG_COND_EQ, LSB); \ 839 } while (0) 840 #define fGEN_TCG_cond_jumprf(COND) \ 841 do { \ 842 TCGv LSB = tcg_temp_new(); \ 843 COND; \ 844 gen_cond_jumpr(ctx, RsV, TCG_COND_NE, LSB); \ 845 } while (0) 846 847 #define fGEN_TCG_J2_jumprt(SHORTCODE) \ 848 fGEN_TCG_cond_jumprt(fLSBOLD(PuV)) 849 #define fGEN_TCG_J2_jumprtpt(SHORTCODE) \ 850 fGEN_TCG_cond_jumprt(fLSBOLD(PuV)) 851 #define fGEN_TCG_J2_jumprf(SHORTCODE) \ 852 fGEN_TCG_cond_jumprf(fLSBOLD(PuV)) 853 #define fGEN_TCG_J2_jumprfpt(SHORTCODE) \ 854 fGEN_TCG_cond_jumprf(fLSBOLD(PuV)) 855 #define fGEN_TCG_J2_jumprtnew(SHORTCODE) \ 856 fGEN_TCG_cond_jumprt(fLSBNEW(PuN)) 857 #define fGEN_TCG_J2_jumprtnewpt(SHORTCODE) \ 858 fGEN_TCG_cond_jumprt(fLSBNEW(PuN)) 859 #define fGEN_TCG_J2_jumprfnew(SHORTCODE) \ 860 fGEN_TCG_cond_jumprf(fLSBNEW(PuN)) 861 #define fGEN_TCG_J2_jumprfnewpt(SHORTCODE) \ 862 fGEN_TCG_cond_jumprf(fLSBNEW(PuN)) 863 864 /* 865 * New value compare & jump instructions 866 * if ([!]COND(r0.new, r1) jump:t address 867 * if ([!]COND(r0.new, #7) jump:t address 868 */ 869 #define fGEN_TCG_J4_cmpgt_t_jumpnv_t(SHORTCODE) \ 870 gen_cmp_jumpnv(ctx, TCG_COND_GT, NsN, RtV, riV) 871 #define fGEN_TCG_J4_cmpgt_t_jumpnv_nt(SHORTCODE) \ 872 gen_cmp_jumpnv(ctx, TCG_COND_GT, NsN, RtV, riV) 873 #define fGEN_TCG_J4_cmpgt_f_jumpnv_t(SHORTCODE) \ 874 gen_cmp_jumpnv(ctx, TCG_COND_LE, NsN, RtV, riV) 875 #define fGEN_TCG_J4_cmpgt_f_jumpnv_nt(SHORTCODE) \ 876 gen_cmp_jumpnv(ctx, TCG_COND_LE, NsN, RtV, riV) 877 878 #define fGEN_TCG_J4_cmpeq_t_jumpnv_t(SHORTCODE) \ 879 gen_cmp_jumpnv(ctx, TCG_COND_EQ, NsN, RtV, riV) 880 #define fGEN_TCG_J4_cmpeq_t_jumpnv_nt(SHORTCODE) \ 881 gen_cmp_jumpnv(ctx, TCG_COND_EQ, NsN, RtV, riV) 882 #define fGEN_TCG_J4_cmpeq_f_jumpnv_t(SHORTCODE) \ 883 gen_cmp_jumpnv(ctx, TCG_COND_NE, NsN, RtV, riV) 884 #define fGEN_TCG_J4_cmpeq_f_jumpnv_nt(SHORTCODE) \ 885 gen_cmp_jumpnv(ctx, TCG_COND_NE, NsN, RtV, riV) 886 887 #define fGEN_TCG_J4_cmplt_t_jumpnv_t(SHORTCODE) \ 888 gen_cmp_jumpnv(ctx, TCG_COND_LT, NsN, RtV, riV) 889 #define fGEN_TCG_J4_cmplt_t_jumpnv_nt(SHORTCODE) \ 890 gen_cmp_jumpnv(ctx, TCG_COND_LT, NsN, RtV, riV) 891 #define fGEN_TCG_J4_cmplt_f_jumpnv_t(SHORTCODE) \ 892 gen_cmp_jumpnv(ctx, TCG_COND_GE, NsN, RtV, riV) 893 #define fGEN_TCG_J4_cmplt_f_jumpnv_nt(SHORTCODE) \ 894 gen_cmp_jumpnv(ctx, TCG_COND_GE, NsN, RtV, riV) 895 896 #define fGEN_TCG_J4_cmpeqi_t_jumpnv_t(SHORTCODE) \ 897 gen_cmpi_jumpnv(ctx, TCG_COND_EQ, NsN, UiV, riV) 898 #define fGEN_TCG_J4_cmpeqi_t_jumpnv_nt(SHORTCODE) \ 899 gen_cmpi_jumpnv(ctx, TCG_COND_EQ, NsN, UiV, riV) 900 #define fGEN_TCG_J4_cmpeqi_f_jumpnv_t(SHORTCODE) \ 901 gen_cmpi_jumpnv(ctx, TCG_COND_NE, NsN, UiV, riV) 902 #define fGEN_TCG_J4_cmpeqi_f_jumpnv_nt(SHORTCODE) \ 903 gen_cmpi_jumpnv(ctx, TCG_COND_NE, NsN, UiV, riV) 904 905 #define fGEN_TCG_J4_cmpgti_t_jumpnv_t(SHORTCODE) \ 906 gen_cmpi_jumpnv(ctx, TCG_COND_GT, NsN, UiV, riV) 907 #define fGEN_TCG_J4_cmpgti_t_jumpnv_nt(SHORTCODE) \ 908 gen_cmpi_jumpnv(ctx, TCG_COND_GT, NsN, UiV, riV) 909 #define fGEN_TCG_J4_cmpgti_f_jumpnv_t(SHORTCODE) \ 910 gen_cmpi_jumpnv(ctx, TCG_COND_LE, NsN, UiV, riV) 911 #define fGEN_TCG_J4_cmpgti_f_jumpnv_nt(SHORTCODE) \ 912 gen_cmpi_jumpnv(ctx, TCG_COND_LE, NsN, UiV, riV) 913 914 #define fGEN_TCG_J4_cmpltu_t_jumpnv_t(SHORTCODE) \ 915 gen_cmp_jumpnv(ctx, TCG_COND_LTU, NsN, RtV, riV) 916 #define fGEN_TCG_J4_cmpltu_t_jumpnv_nt(SHORTCODE) \ 917 gen_cmp_jumpnv(ctx, TCG_COND_LTU, NsN, RtV, riV) 918 #define fGEN_TCG_J4_cmpltu_f_jumpnv_t(SHORTCODE) \ 919 gen_cmp_jumpnv(ctx, TCG_COND_GEU, NsN, RtV, riV) 920 #define fGEN_TCG_J4_cmpltu_f_jumpnv_nt(SHORTCODE) \ 921 gen_cmp_jumpnv(ctx, TCG_COND_GEU, NsN, RtV, riV) 922 923 #define fGEN_TCG_J4_cmpgtui_t_jumpnv_t(SHORTCODE) \ 924 gen_cmpi_jumpnv(ctx, TCG_COND_GTU, NsN, UiV, riV) 925 #define fGEN_TCG_J4_cmpgtui_t_jumpnv_nt(SHORTCODE) \ 926 gen_cmpi_jumpnv(ctx, TCG_COND_GTU, NsN, UiV, riV) 927 #define fGEN_TCG_J4_cmpgtui_f_jumpnv_t(SHORTCODE) \ 928 gen_cmpi_jumpnv(ctx, TCG_COND_LEU, NsN, UiV, riV) 929 #define fGEN_TCG_J4_cmpgtui_f_jumpnv_nt(SHORTCODE) \ 930 gen_cmpi_jumpnv(ctx, TCG_COND_LEU, NsN, UiV, riV) 931 932 #define fGEN_TCG_J4_cmpgtu_t_jumpnv_t(SHORTCODE) \ 933 gen_cmp_jumpnv(ctx, TCG_COND_GTU, NsN, RtV, riV) 934 #define fGEN_TCG_J4_cmpgtu_t_jumpnv_nt(SHORTCODE) \ 935 gen_cmp_jumpnv(ctx, TCG_COND_GTU, NsN, RtV, riV) 936 #define fGEN_TCG_J4_cmpgtu_f_jumpnv_t(SHORTCODE) \ 937 gen_cmp_jumpnv(ctx, TCG_COND_LEU, NsN, RtV, riV) 938 #define fGEN_TCG_J4_cmpgtu_f_jumpnv_nt(SHORTCODE) \ 939 gen_cmp_jumpnv(ctx, TCG_COND_LEU, NsN, RtV, riV) 940 941 #define fGEN_TCG_J4_cmpeqn1_t_jumpnv_t(SHORTCODE) \ 942 gen_cmpi_jumpnv(ctx, TCG_COND_EQ, NsN, -1, riV) 943 #define fGEN_TCG_J4_cmpeqn1_t_jumpnv_nt(SHORTCODE) \ 944 gen_cmpi_jumpnv(ctx, TCG_COND_EQ, NsN, -1, riV) 945 #define fGEN_TCG_J4_cmpeqn1_f_jumpnv_t(SHORTCODE) \ 946 gen_cmpi_jumpnv(ctx, TCG_COND_NE, NsN, -1, riV) 947 #define fGEN_TCG_J4_cmpeqn1_f_jumpnv_nt(SHORTCODE) \ 948 gen_cmpi_jumpnv(ctx, TCG_COND_NE, NsN, -1, riV) 949 950 #define fGEN_TCG_J4_cmpgtn1_t_jumpnv_t(SHORTCODE) \ 951 gen_cmpi_jumpnv(ctx, TCG_COND_GT, NsN, -1, riV) 952 #define fGEN_TCG_J4_cmpgtn1_t_jumpnv_nt(SHORTCODE) \ 953 gen_cmpi_jumpnv(ctx, TCG_COND_GT, NsN, -1, riV) 954 #define fGEN_TCG_J4_cmpgtn1_f_jumpnv_t(SHORTCODE) \ 955 gen_cmpi_jumpnv(ctx, TCG_COND_LE, NsN, -1, riV) 956 #define fGEN_TCG_J4_cmpgtn1_f_jumpnv_nt(SHORTCODE) \ 957 gen_cmpi_jumpnv(ctx, TCG_COND_LE, NsN, -1, riV) 958 959 #define fGEN_TCG_J4_tstbit0_t_jumpnv_t(SHORTCODE) \ 960 gen_testbit0_jumpnv(ctx, NsN, TCG_COND_EQ, riV) 961 #define fGEN_TCG_J4_tstbit0_t_jumpnv_nt(SHORTCODE) \ 962 gen_testbit0_jumpnv(ctx, NsN, TCG_COND_EQ, riV) 963 #define fGEN_TCG_J4_tstbit0_f_jumpnv_t(SHORTCODE) \ 964 gen_testbit0_jumpnv(ctx, NsN, TCG_COND_NE, riV) 965 #define fGEN_TCG_J4_tstbit0_f_jumpnv_nt(SHORTCODE) \ 966 gen_testbit0_jumpnv(ctx, NsN, TCG_COND_NE, riV) 967 968 /* r0 = r1 ; jump address */ 969 #define fGEN_TCG_J4_jumpsetr(SHORTCODE) \ 970 do { \ 971 tcg_gen_mov_tl(RdV, RsV); \ 972 gen_jump(ctx, riV); \ 973 } while (0) 974 975 #define fGEN_TCG_J2_pause(SHORTCODE) \ 976 do { \ 977 uiV = uiV; \ 978 tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], ctx->next_PC); \ 979 } while (0) 980 981 /* r0 = asr(r1, r2):sat */ 982 #define fGEN_TCG_S2_asr_r_r_sat(SHORTCODE) \ 983 gen_asr_r_r_sat(RdV, RsV, RtV) 984 985 /* r0 = asl(r1, r2):sat */ 986 #define fGEN_TCG_S2_asl_r_r_sat(SHORTCODE) \ 987 gen_asl_r_r_sat(RdV, RsV, RtV) 988 989 /* Floating point */ 990 #define fGEN_TCG_F2_conv_sf2df(SHORTCODE) \ 991 gen_helper_conv_sf2df(RddV, cpu_env, RsV) 992 #define fGEN_TCG_F2_conv_df2sf(SHORTCODE) \ 993 gen_helper_conv_df2sf(RdV, cpu_env, RssV) 994 #define fGEN_TCG_F2_conv_uw2sf(SHORTCODE) \ 995 gen_helper_conv_uw2sf(RdV, cpu_env, RsV) 996 #define fGEN_TCG_F2_conv_uw2df(SHORTCODE) \ 997 gen_helper_conv_uw2df(RddV, cpu_env, RsV) 998 #define fGEN_TCG_F2_conv_w2sf(SHORTCODE) \ 999 gen_helper_conv_w2sf(RdV, cpu_env, RsV) 1000 #define fGEN_TCG_F2_conv_w2df(SHORTCODE) \ 1001 gen_helper_conv_w2df(RddV, cpu_env, RsV) 1002 #define fGEN_TCG_F2_conv_ud2sf(SHORTCODE) \ 1003 gen_helper_conv_ud2sf(RdV, cpu_env, RssV) 1004 #define fGEN_TCG_F2_conv_ud2df(SHORTCODE) \ 1005 gen_helper_conv_ud2df(RddV, cpu_env, RssV) 1006 #define fGEN_TCG_F2_conv_d2sf(SHORTCODE) \ 1007 gen_helper_conv_d2sf(RdV, cpu_env, RssV) 1008 #define fGEN_TCG_F2_conv_d2df(SHORTCODE) \ 1009 gen_helper_conv_d2df(RddV, cpu_env, RssV) 1010 #define fGEN_TCG_F2_conv_sf2uw(SHORTCODE) \ 1011 gen_helper_conv_sf2uw(RdV, cpu_env, RsV) 1012 #define fGEN_TCG_F2_conv_sf2w(SHORTCODE) \ 1013 gen_helper_conv_sf2w(RdV, cpu_env, RsV) 1014 #define fGEN_TCG_F2_conv_sf2ud(SHORTCODE) \ 1015 gen_helper_conv_sf2ud(RddV, cpu_env, RsV) 1016 #define fGEN_TCG_F2_conv_sf2d(SHORTCODE) \ 1017 gen_helper_conv_sf2d(RddV, cpu_env, RsV) 1018 #define fGEN_TCG_F2_conv_df2uw(SHORTCODE) \ 1019 gen_helper_conv_df2uw(RdV, cpu_env, RssV) 1020 #define fGEN_TCG_F2_conv_df2w(SHORTCODE) \ 1021 gen_helper_conv_df2w(RdV, cpu_env, RssV) 1022 #define fGEN_TCG_F2_conv_df2ud(SHORTCODE) \ 1023 gen_helper_conv_df2ud(RddV, cpu_env, RssV) 1024 #define fGEN_TCG_F2_conv_df2d(SHORTCODE) \ 1025 gen_helper_conv_df2d(RddV, cpu_env, RssV) 1026 #define fGEN_TCG_F2_conv_sf2uw_chop(SHORTCODE) \ 1027 gen_helper_conv_sf2uw_chop(RdV, cpu_env, RsV) 1028 #define fGEN_TCG_F2_conv_sf2w_chop(SHORTCODE) \ 1029 gen_helper_conv_sf2w_chop(RdV, cpu_env, RsV) 1030 #define fGEN_TCG_F2_conv_sf2ud_chop(SHORTCODE) \ 1031 gen_helper_conv_sf2ud_chop(RddV, cpu_env, RsV) 1032 #define fGEN_TCG_F2_conv_sf2d_chop(SHORTCODE) \ 1033 gen_helper_conv_sf2d_chop(RddV, cpu_env, RsV) 1034 #define fGEN_TCG_F2_conv_df2uw_chop(SHORTCODE) \ 1035 gen_helper_conv_df2uw_chop(RdV, cpu_env, RssV) 1036 #define fGEN_TCG_F2_conv_df2w_chop(SHORTCODE) \ 1037 gen_helper_conv_df2w_chop(RdV, cpu_env, RssV) 1038 #define fGEN_TCG_F2_conv_df2ud_chop(SHORTCODE) \ 1039 gen_helper_conv_df2ud_chop(RddV, cpu_env, RssV) 1040 #define fGEN_TCG_F2_conv_df2d_chop(SHORTCODE) \ 1041 gen_helper_conv_df2d_chop(RddV, cpu_env, RssV) 1042 #define fGEN_TCG_F2_sfadd(SHORTCODE) \ 1043 gen_helper_sfadd(RdV, cpu_env, RsV, RtV) 1044 #define fGEN_TCG_F2_sfsub(SHORTCODE) \ 1045 gen_helper_sfsub(RdV, cpu_env, RsV, RtV) 1046 #define fGEN_TCG_F2_sfcmpeq(SHORTCODE) \ 1047 gen_helper_sfcmpeq(PdV, cpu_env, RsV, RtV) 1048 #define fGEN_TCG_F2_sfcmpgt(SHORTCODE) \ 1049 gen_helper_sfcmpgt(PdV, cpu_env, RsV, RtV) 1050 #define fGEN_TCG_F2_sfcmpge(SHORTCODE) \ 1051 gen_helper_sfcmpge(PdV, cpu_env, RsV, RtV) 1052 #define fGEN_TCG_F2_sfcmpuo(SHORTCODE) \ 1053 gen_helper_sfcmpuo(PdV, cpu_env, RsV, RtV) 1054 #define fGEN_TCG_F2_sfmax(SHORTCODE) \ 1055 gen_helper_sfmax(RdV, cpu_env, RsV, RtV) 1056 #define fGEN_TCG_F2_sfmin(SHORTCODE) \ 1057 gen_helper_sfmin(RdV, cpu_env, RsV, RtV) 1058 #define fGEN_TCG_F2_sfclass(SHORTCODE) \ 1059 do { \ 1060 TCGv imm = tcg_constant_tl(uiV); \ 1061 gen_helper_sfclass(PdV, cpu_env, RsV, imm); \ 1062 } while (0) 1063 #define fGEN_TCG_F2_sffixupn(SHORTCODE) \ 1064 gen_helper_sffixupn(RdV, cpu_env, RsV, RtV) 1065 #define fGEN_TCG_F2_sffixupd(SHORTCODE) \ 1066 gen_helper_sffixupd(RdV, cpu_env, RsV, RtV) 1067 #define fGEN_TCG_F2_sffixupr(SHORTCODE) \ 1068 gen_helper_sffixupr(RdV, cpu_env, RsV) 1069 #define fGEN_TCG_F2_dfadd(SHORTCODE) \ 1070 gen_helper_dfadd(RddV, cpu_env, RssV, RttV) 1071 #define fGEN_TCG_F2_dfsub(SHORTCODE) \ 1072 gen_helper_dfsub(RddV, cpu_env, RssV, RttV) 1073 #define fGEN_TCG_F2_dfmax(SHORTCODE) \ 1074 gen_helper_dfmax(RddV, cpu_env, RssV, RttV) 1075 #define fGEN_TCG_F2_dfmin(SHORTCODE) \ 1076 gen_helper_dfmin(RddV, cpu_env, RssV, RttV) 1077 #define fGEN_TCG_F2_dfcmpeq(SHORTCODE) \ 1078 gen_helper_dfcmpeq(PdV, cpu_env, RssV, RttV) 1079 #define fGEN_TCG_F2_dfcmpgt(SHORTCODE) \ 1080 gen_helper_dfcmpgt(PdV, cpu_env, RssV, RttV) 1081 #define fGEN_TCG_F2_dfcmpge(SHORTCODE) \ 1082 gen_helper_dfcmpge(PdV, cpu_env, RssV, RttV) 1083 #define fGEN_TCG_F2_dfcmpuo(SHORTCODE) \ 1084 gen_helper_dfcmpuo(PdV, cpu_env, RssV, RttV) 1085 #define fGEN_TCG_F2_dfclass(SHORTCODE) \ 1086 do { \ 1087 TCGv imm = tcg_constant_tl(uiV); \ 1088 gen_helper_dfclass(PdV, cpu_env, RssV, imm); \ 1089 } while (0) 1090 #define fGEN_TCG_F2_sfmpy(SHORTCODE) \ 1091 gen_helper_sfmpy(RdV, cpu_env, RsV, RtV) 1092 #define fGEN_TCG_F2_sffma(SHORTCODE) \ 1093 gen_helper_sffma(RxV, cpu_env, RxV, RsV, RtV) 1094 #define fGEN_TCG_F2_sffma_sc(SHORTCODE) \ 1095 gen_helper_sffma_sc(RxV, cpu_env, RxV, RsV, RtV, PuV) 1096 #define fGEN_TCG_F2_sffms(SHORTCODE) \ 1097 gen_helper_sffms(RxV, cpu_env, RxV, RsV, RtV) 1098 #define fGEN_TCG_F2_sffma_lib(SHORTCODE) \ 1099 gen_helper_sffma_lib(RxV, cpu_env, RxV, RsV, RtV) 1100 #define fGEN_TCG_F2_sffms_lib(SHORTCODE) \ 1101 gen_helper_sffms_lib(RxV, cpu_env, RxV, RsV, RtV) 1102 1103 #define fGEN_TCG_F2_dfmpyfix(SHORTCODE) \ 1104 gen_helper_dfmpyfix(RddV, cpu_env, RssV, RttV) 1105 #define fGEN_TCG_F2_dfmpyhh(SHORTCODE) \ 1106 gen_helper_dfmpyhh(RxxV, cpu_env, RxxV, RssV, RttV) 1107 1108 /* Nothing to do for these in qemu, need to suppress compiler warnings */ 1109 #define fGEN_TCG_Y4_l2fetch(SHORTCODE) \ 1110 do { \ 1111 RsV = RsV; \ 1112 RtV = RtV; \ 1113 } while (0) 1114 #define fGEN_TCG_Y5_l2fetch(SHORTCODE) \ 1115 do { \ 1116 RsV = RsV; \ 1117 } while (0) 1118 1119 #define fGEN_TCG_J2_trap0(SHORTCODE) \ 1120 do { \ 1121 uiV = uiV; \ 1122 tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], ctx->pkt->pc); \ 1123 TCGv excp = tcg_constant_tl(HEX_EXCP_TRAP0); \ 1124 gen_helper_raise_exception(cpu_env, excp); \ 1125 } while (0) 1126 #endif 1127