1 /* 2 * Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 /* 19 * This program generates the semantics file that is processed by 20 * the do_qemu.py script. We use the C preporcessor to manipulate the 21 * files imported from the Hexagon architecture library. 22 */ 23 24 #include <stdio.h> 25 #define STRINGIZE(X) #X 26 27 int main(int argc, char *argv[]) 28 { 29 FILE *outfile; 30 31 if (argc != 2) { 32 fprintf(stderr, "Usage: gen_semantics ouptputfile\n"); 33 return 1; 34 } 35 outfile = fopen(argv[1], "w"); 36 if (outfile == NULL) { 37 fprintf(stderr, "Cannot open %s for writing\n", argv[1]); 38 return 1; 39 } 40 41 /* 42 * Process the instruction definitions 43 * Scalar core instructions have the following form 44 * Q6INSN(A2_add,"Rd32=add(Rs32,Rt32)",ATTRIBS(), 45 * "Add 32-bit registers", 46 * { RdV=RsV+RtV;}) 47 * HVX instructions have the following form 48 * EXTINSN(V6_vinsertwr, "Vx32.w=vinsert(Rt32)", 49 * ATTRIBS(A_EXTENSION,A_CVI,A_CVI_VX), 50 * "Insert Word Scalar into Vector", 51 * VxV.uw[0] = RtV;) 52 */ 53 #define Q6INSN(TAG, BEH, ATTRIBS, DESCR, SEM) \ 54 do { \ 55 fprintf(outfile, "SEMANTICS( \\\n" \ 56 " \"%s\", \\\n" \ 57 " %s, \\\n" \ 58 " \"\"\"%s\"\"\" \\\n" \ 59 ")\n", \ 60 #TAG, STRINGIZE(BEH), STRINGIZE(SEM)); \ 61 fprintf(outfile, "ATTRIBUTES( \\\n" \ 62 " \"%s\", \\\n" \ 63 " \"%s\" \\\n" \ 64 ")\n", \ 65 #TAG, STRINGIZE(ATTRIBS)); \ 66 } while (0); 67 #define EXTINSN(TAG, BEH, ATTRIBS, DESCR, SEM) \ 68 do { \ 69 fprintf(outfile, "SEMANTICS( \\\n" \ 70 " \"%s\", \\\n" \ 71 " %s, \\\n" \ 72 " \"\"\"%s\"\"\" \\\n" \ 73 ")\n", \ 74 #TAG, STRINGIZE(BEH), STRINGIZE(SEM)); \ 75 fprintf(outfile, "ATTRIBUTES( \\\n" \ 76 " \"%s\", \\\n" \ 77 " \"%s\" \\\n" \ 78 ")\n", \ 79 #TAG, STRINGIZE(ATTRIBS)); \ 80 } while (0); 81 #include "imported/allidefs.def" 82 #undef Q6INSN 83 #undef EXTINSN 84 85 /* 86 * Process the macro definitions 87 * Macros definitions have the following form 88 * DEF_MACRO( 89 * fLSBNEW0, 90 * predlog_read(thread,0), 91 * () 92 * ) 93 * The important part here is the attributes. Whenever an instruction 94 * invokes a macro, we add the macro's attributes to the instruction. 95 */ 96 #define DEF_MACRO(MNAME, BEH, ATTRS) \ 97 fprintf(outfile, "MACROATTRIB( \\\n" \ 98 " \"%s\", \\\n" \ 99 " \"\"\"%s\"\"\", \\\n" \ 100 " \"%s\" \\\n" \ 101 ")\n", \ 102 #MNAME, STRINGIZE(BEH), STRINGIZE(ATTRS)); 103 #include "imported/macros.def" 104 #undef DEF_MACRO 105 106 /* 107 * Process the macros for HVX 108 */ 109 #define DEF_MACRO(MNAME, BEH, ATTRS) \ 110 fprintf(outfile, "MACROATTRIB( \\\n" \ 111 " \"%s\", \\\n" \ 112 " \"\"\"%s\"\"\", \\\n" \ 113 " \"%s\" \\\n" \ 114 ")\n", \ 115 #MNAME, STRINGIZE(BEH), STRINGIZE(ATTRS)); 116 #include "imported/allext_macros.def" 117 #undef DEF_MACRO 118 119 fclose(outfile); 120 return 0; 121 } 122