1 /* 2 * Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #ifndef HEXAGON_CPU_H 19 #define HEXAGON_CPU_H 20 21 #include "fpu/softfloat-types.h" 22 23 #include "exec/cpu-defs.h" 24 #include "hex_regs.h" 25 #include "mmvec/mmvec.h" 26 #include "qom/object.h" 27 #include "hw/core/cpu.h" 28 #include "hw/registerfields.h" 29 30 #define NUM_PREGS 4 31 #define TOTAL_PER_THREAD_REGS 64 32 33 #define SLOTS_MAX 4 34 #define STORES_MAX 2 35 #define REG_WRITES_MAX 32 36 #define PRED_WRITES_MAX 5 /* 4 insns + endloop */ 37 #define VSTORES_MAX 2 38 39 #define TYPE_HEXAGON_CPU "hexagon-cpu" 40 41 #define HEXAGON_CPU_TYPE_SUFFIX "-" TYPE_HEXAGON_CPU 42 #define HEXAGON_CPU_TYPE_NAME(name) (name HEXAGON_CPU_TYPE_SUFFIX) 43 #define CPU_RESOLVING_TYPE TYPE_HEXAGON_CPU 44 45 #define TYPE_HEXAGON_CPU_V67 HEXAGON_CPU_TYPE_NAME("v67") 46 #define TYPE_HEXAGON_CPU_V68 HEXAGON_CPU_TYPE_NAME("v68") 47 #define TYPE_HEXAGON_CPU_V69 HEXAGON_CPU_TYPE_NAME("v69") 48 #define TYPE_HEXAGON_CPU_V71 HEXAGON_CPU_TYPE_NAME("v71") 49 #define TYPE_HEXAGON_CPU_V73 HEXAGON_CPU_TYPE_NAME("v73") 50 51 #define MMU_USER_IDX 0 52 53 typedef struct { 54 target_ulong va; 55 uint8_t width; 56 uint32_t data32; 57 uint64_t data64; 58 } MemLog; 59 60 typedef struct { 61 target_ulong va; 62 int size; 63 DECLARE_BITMAP(mask, MAX_VEC_SIZE_BYTES) QEMU_ALIGNED(16); 64 MMVector data QEMU_ALIGNED(16); 65 } VStoreLog; 66 67 #define EXEC_STATUS_OK 0x0000 68 #define EXEC_STATUS_STOP 0x0002 69 #define EXEC_STATUS_REPLAY 0x0010 70 #define EXEC_STATUS_LOCKED 0x0020 71 #define EXEC_STATUS_EXCEPTION 0x0100 72 73 74 #define EXCEPTION_DETECTED (env->status & EXEC_STATUS_EXCEPTION) 75 #define REPLAY_DETECTED (env->status & EXEC_STATUS_REPLAY) 76 #define CLEAR_EXCEPTION (env->status &= (~EXEC_STATUS_EXCEPTION)) 77 #define SET_EXCEPTION (env->status |= EXEC_STATUS_EXCEPTION) 78 79 /* Maximum number of vector temps in a packet */ 80 #define VECTOR_TEMPS_MAX 4 81 82 typedef struct CPUArchState { 83 target_ulong gpr[TOTAL_PER_THREAD_REGS]; 84 target_ulong pred[NUM_PREGS]; 85 target_ulong branch_taken; 86 87 /* For comparing with LLDB on target - see adjust_stack_ptrs function */ 88 target_ulong last_pc_dumped; 89 target_ulong stack_start; 90 91 uint8_t slot_cancelled; 92 target_ulong new_value[TOTAL_PER_THREAD_REGS]; 93 94 /* 95 * Only used when HEX_DEBUG is on, but unconditionally included 96 * to reduce recompile time when turning HEX_DEBUG on/off. 97 */ 98 target_ulong this_PC; 99 target_ulong reg_written[TOTAL_PER_THREAD_REGS]; 100 101 target_ulong new_pred_value[NUM_PREGS]; 102 target_ulong pred_written; 103 104 MemLog mem_log_stores[STORES_MAX]; 105 target_ulong pkt_has_store_s1; 106 target_ulong dczero_addr; 107 108 float_status fp_status; 109 110 target_ulong llsc_addr; 111 target_ulong llsc_val; 112 uint64_t llsc_val_i64; 113 114 MMVector VRegs[NUM_VREGS] QEMU_ALIGNED(16); 115 MMVector future_VRegs[VECTOR_TEMPS_MAX] QEMU_ALIGNED(16); 116 MMVector tmp_VRegs[VECTOR_TEMPS_MAX] QEMU_ALIGNED(16); 117 118 MMQReg QRegs[NUM_QREGS] QEMU_ALIGNED(16); 119 MMQReg future_QRegs[NUM_QREGS] QEMU_ALIGNED(16); 120 121 /* Temporaries used within instructions */ 122 MMVectorPair VuuV QEMU_ALIGNED(16); 123 MMVectorPair VvvV QEMU_ALIGNED(16); 124 MMVectorPair VxxV QEMU_ALIGNED(16); 125 MMVector vtmp QEMU_ALIGNED(16); 126 MMQReg qtmp QEMU_ALIGNED(16); 127 128 VStoreLog vstore[VSTORES_MAX]; 129 target_ulong vstore_pending[VSTORES_MAX]; 130 bool vtcm_pending; 131 VTCMStoreLog vtcm_log; 132 } CPUHexagonState; 133 134 OBJECT_DECLARE_CPU_TYPE(HexagonCPU, HexagonCPUClass, HEXAGON_CPU) 135 136 typedef struct HexagonCPUClass { 137 /*< private >*/ 138 CPUClass parent_class; 139 /*< public >*/ 140 DeviceRealize parent_realize; 141 ResettablePhases parent_phases; 142 } HexagonCPUClass; 143 144 struct ArchCPU { 145 /*< private >*/ 146 CPUState parent_obj; 147 /*< public >*/ 148 CPUNegativeOffsetState neg; 149 CPUHexagonState env; 150 151 bool lldb_compat; 152 target_ulong lldb_stack_adjust; 153 }; 154 155 #include "cpu_bits.h" 156 157 FIELD(TB_FLAGS, IS_TIGHT_LOOP, 0, 1) 158 159 static inline void cpu_get_tb_cpu_state(CPUHexagonState *env, target_ulong *pc, 160 target_ulong *cs_base, uint32_t *flags) 161 { 162 uint32_t hex_flags = 0; 163 *pc = env->gpr[HEX_REG_PC]; 164 *cs_base = 0; 165 if (*pc == env->gpr[HEX_REG_SA0]) { 166 hex_flags = FIELD_DP32(hex_flags, TB_FLAGS, IS_TIGHT_LOOP, 1); 167 } 168 *flags = hex_flags; 169 } 170 171 static inline int cpu_mmu_index(CPUHexagonState *env, bool ifetch) 172 { 173 #ifdef CONFIG_USER_ONLY 174 return MMU_USER_IDX; 175 #else 176 #error System mode not supported on Hexagon yet 177 #endif 178 } 179 180 typedef HexagonCPU ArchCPU; 181 182 void hexagon_translate_init(void); 183 184 #include "exec/cpu-all.h" 185 186 #endif /* HEXAGON_CPU_H */ 187