1 /* 2 * Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #ifndef HEXAGON_CPU_H 19 #define HEXAGON_CPU_H 20 21 /* Forward declaration needed by some of the header files */ 22 typedef struct CPUHexagonState CPUHexagonState; 23 24 #include "fpu/softfloat-types.h" 25 26 #include "exec/cpu-defs.h" 27 #include "hex_regs.h" 28 #include "mmvec/mmvec.h" 29 30 #define NUM_PREGS 4 31 #define TOTAL_PER_THREAD_REGS 64 32 33 #define SLOTS_MAX 4 34 #define STORES_MAX 2 35 #define REG_WRITES_MAX 32 36 #define PRED_WRITES_MAX 5 /* 4 insns + endloop */ 37 #define VSTORES_MAX 2 38 39 #define TYPE_HEXAGON_CPU "hexagon-cpu" 40 41 #define HEXAGON_CPU_TYPE_SUFFIX "-" TYPE_HEXAGON_CPU 42 #define HEXAGON_CPU_TYPE_NAME(name) (name HEXAGON_CPU_TYPE_SUFFIX) 43 #define CPU_RESOLVING_TYPE TYPE_HEXAGON_CPU 44 45 #define TYPE_HEXAGON_CPU_V67 HEXAGON_CPU_TYPE_NAME("v67") 46 47 #define MMU_USER_IDX 0 48 49 typedef struct { 50 target_ulong va; 51 uint8_t width; 52 uint32_t data32; 53 uint64_t data64; 54 } MemLog; 55 56 typedef struct { 57 target_ulong va; 58 int size; 59 DECLARE_BITMAP(mask, MAX_VEC_SIZE_BYTES) QEMU_ALIGNED(16); 60 MMVector data QEMU_ALIGNED(16); 61 } VStoreLog; 62 63 #define EXEC_STATUS_OK 0x0000 64 #define EXEC_STATUS_STOP 0x0002 65 #define EXEC_STATUS_REPLAY 0x0010 66 #define EXEC_STATUS_LOCKED 0x0020 67 #define EXEC_STATUS_EXCEPTION 0x0100 68 69 70 #define EXCEPTION_DETECTED (env->status & EXEC_STATUS_EXCEPTION) 71 #define REPLAY_DETECTED (env->status & EXEC_STATUS_REPLAY) 72 #define CLEAR_EXCEPTION (env->status &= (~EXEC_STATUS_EXCEPTION)) 73 #define SET_EXCEPTION (env->status |= EXEC_STATUS_EXCEPTION) 74 75 /* Maximum number of vector temps in a packet */ 76 #define VECTOR_TEMPS_MAX 4 77 78 struct CPUHexagonState { 79 target_ulong gpr[TOTAL_PER_THREAD_REGS]; 80 target_ulong pred[NUM_PREGS]; 81 target_ulong branch_taken; 82 target_ulong next_PC; 83 84 /* For comparing with LLDB on target - see adjust_stack_ptrs function */ 85 target_ulong last_pc_dumped; 86 target_ulong stack_start; 87 88 uint8_t slot_cancelled; 89 target_ulong new_value[TOTAL_PER_THREAD_REGS]; 90 91 /* 92 * Only used when HEX_DEBUG is on, but unconditionally included 93 * to reduce recompile time when turning HEX_DEBUG on/off. 94 */ 95 target_ulong this_PC; 96 target_ulong reg_written[TOTAL_PER_THREAD_REGS]; 97 98 target_ulong new_pred_value[NUM_PREGS]; 99 target_ulong pred_written; 100 101 MemLog mem_log_stores[STORES_MAX]; 102 target_ulong pkt_has_store_s1; 103 target_ulong dczero_addr; 104 105 float_status fp_status; 106 107 target_ulong llsc_addr; 108 target_ulong llsc_val; 109 uint64_t llsc_val_i64; 110 111 MMVector VRegs[NUM_VREGS] QEMU_ALIGNED(16); 112 MMVector future_VRegs[VECTOR_TEMPS_MAX] QEMU_ALIGNED(16); 113 MMVector tmp_VRegs[VECTOR_TEMPS_MAX] QEMU_ALIGNED(16); 114 115 VRegMask VRegs_updated; 116 117 MMQReg QRegs[NUM_QREGS] QEMU_ALIGNED(16); 118 MMQReg future_QRegs[NUM_QREGS] QEMU_ALIGNED(16); 119 QRegMask QRegs_updated; 120 121 /* Temporaries used within instructions */ 122 MMVectorPair VuuV QEMU_ALIGNED(16); 123 MMVectorPair VvvV QEMU_ALIGNED(16); 124 MMVectorPair VxxV QEMU_ALIGNED(16); 125 MMVector vtmp QEMU_ALIGNED(16); 126 MMQReg qtmp QEMU_ALIGNED(16); 127 128 VStoreLog vstore[VSTORES_MAX]; 129 target_ulong vstore_pending[VSTORES_MAX]; 130 bool vtcm_pending; 131 VTCMStoreLog vtcm_log; 132 }; 133 134 #define HEXAGON_CPU_CLASS(klass) \ 135 OBJECT_CLASS_CHECK(HexagonCPUClass, (klass), TYPE_HEXAGON_CPU) 136 #define HEXAGON_CPU(obj) \ 137 OBJECT_CHECK(HexagonCPU, (obj), TYPE_HEXAGON_CPU) 138 #define HEXAGON_CPU_GET_CLASS(obj) \ 139 OBJECT_GET_CLASS(HexagonCPUClass, (obj), TYPE_HEXAGON_CPU) 140 141 typedef struct HexagonCPUClass { 142 /*< private >*/ 143 CPUClass parent_class; 144 /*< public >*/ 145 DeviceRealize parent_realize; 146 DeviceReset parent_reset; 147 } HexagonCPUClass; 148 149 typedef struct HexagonCPU { 150 /*< private >*/ 151 CPUState parent_obj; 152 /*< public >*/ 153 CPUNegativeOffsetState neg; 154 CPUHexagonState env; 155 156 bool lldb_compat; 157 target_ulong lldb_stack_adjust; 158 } HexagonCPU; 159 160 #include "cpu_bits.h" 161 162 static inline void cpu_get_tb_cpu_state(CPUHexagonState *env, target_ulong *pc, 163 target_ulong *cs_base, uint32_t *flags) 164 { 165 *pc = env->gpr[HEX_REG_PC]; 166 *cs_base = 0; 167 #ifdef CONFIG_USER_ONLY 168 *flags = 0; 169 #else 170 #error System mode not supported on Hexagon yet 171 #endif 172 } 173 174 static inline int cpu_mmu_index(CPUHexagonState *env, bool ifetch) 175 { 176 #ifdef CONFIG_USER_ONLY 177 return MMU_USER_IDX; 178 #else 179 #error System mode not supported on Hexagon yet 180 #endif 181 } 182 183 typedef struct CPUHexagonState CPUArchState; 184 typedef HexagonCPU ArchCPU; 185 186 void hexagon_translate_init(void); 187 188 #include "exec/cpu-all.h" 189 190 #endif /* HEXAGON_CPU_H */ 191