1 /* 2 * Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #ifndef HEXAGON_CPU_H 19 #define HEXAGON_CPU_H 20 21 #include "fpu/softfloat-types.h" 22 23 #include "cpu-qom.h" 24 #include "exec/cpu-defs.h" 25 #include "hex_regs.h" 26 #include "mmvec/mmvec.h" 27 #include "hw/registerfields.h" 28 29 #define NUM_PREGS 4 30 #define TOTAL_PER_THREAD_REGS 64 31 32 #define SLOTS_MAX 4 33 #define STORES_MAX 2 34 #define REG_WRITES_MAX 32 35 #define PRED_WRITES_MAX 5 /* 4 insns + endloop */ 36 #define VSTORES_MAX 2 37 38 #define CPU_RESOLVING_TYPE TYPE_HEXAGON_CPU 39 40 #define MMU_USER_IDX 0 41 42 typedef struct { 43 target_ulong va; 44 uint8_t width; 45 uint32_t data32; 46 uint64_t data64; 47 } MemLog; 48 49 typedef struct { 50 target_ulong va; 51 int size; 52 DECLARE_BITMAP(mask, MAX_VEC_SIZE_BYTES) QEMU_ALIGNED(16); 53 MMVector data QEMU_ALIGNED(16); 54 } VStoreLog; 55 56 #define EXEC_STATUS_OK 0x0000 57 #define EXEC_STATUS_STOP 0x0002 58 #define EXEC_STATUS_REPLAY 0x0010 59 #define EXEC_STATUS_LOCKED 0x0020 60 #define EXEC_STATUS_EXCEPTION 0x0100 61 62 63 #define EXCEPTION_DETECTED (env->status & EXEC_STATUS_EXCEPTION) 64 #define REPLAY_DETECTED (env->status & EXEC_STATUS_REPLAY) 65 #define CLEAR_EXCEPTION (env->status &= (~EXEC_STATUS_EXCEPTION)) 66 #define SET_EXCEPTION (env->status |= EXEC_STATUS_EXCEPTION) 67 68 /* Maximum number of vector temps in a packet */ 69 #define VECTOR_TEMPS_MAX 4 70 71 typedef struct CPUArchState { 72 target_ulong gpr[TOTAL_PER_THREAD_REGS]; 73 target_ulong pred[NUM_PREGS]; 74 75 /* For comparing with LLDB on target - see adjust_stack_ptrs function */ 76 target_ulong last_pc_dumped; 77 target_ulong stack_start; 78 79 uint8_t slot_cancelled; 80 target_ulong new_value_usr; 81 82 /* 83 * Only used when HEX_DEBUG is on, but unconditionally included 84 * to reduce recompile time when turning HEX_DEBUG on/off. 85 */ 86 target_ulong reg_written[TOTAL_PER_THREAD_REGS]; 87 88 MemLog mem_log_stores[STORES_MAX]; 89 90 float_status fp_status; 91 92 target_ulong llsc_addr; 93 target_ulong llsc_val; 94 uint64_t llsc_val_i64; 95 96 MMVector VRegs[NUM_VREGS] QEMU_ALIGNED(16); 97 MMVector future_VRegs[VECTOR_TEMPS_MAX] QEMU_ALIGNED(16); 98 MMVector tmp_VRegs[VECTOR_TEMPS_MAX] QEMU_ALIGNED(16); 99 100 MMQReg QRegs[NUM_QREGS] QEMU_ALIGNED(16); 101 MMQReg future_QRegs[NUM_QREGS] QEMU_ALIGNED(16); 102 103 /* Temporaries used within instructions */ 104 MMVectorPair VuuV QEMU_ALIGNED(16); 105 MMVectorPair VvvV QEMU_ALIGNED(16); 106 MMVectorPair VxxV QEMU_ALIGNED(16); 107 MMVector vtmp QEMU_ALIGNED(16); 108 MMQReg qtmp QEMU_ALIGNED(16); 109 110 VStoreLog vstore[VSTORES_MAX]; 111 target_ulong vstore_pending[VSTORES_MAX]; 112 bool vtcm_pending; 113 VTCMStoreLog vtcm_log; 114 } CPUHexagonState; 115 116 typedef struct HexagonCPUClass { 117 CPUClass parent_class; 118 119 DeviceRealize parent_realize; 120 ResettablePhases parent_phases; 121 } HexagonCPUClass; 122 123 struct ArchCPU { 124 CPUState parent_obj; 125 126 CPUHexagonState env; 127 128 bool lldb_compat; 129 target_ulong lldb_stack_adjust; 130 bool short_circuit; 131 }; 132 133 #include "cpu_bits.h" 134 135 FIELD(TB_FLAGS, IS_TIGHT_LOOP, 0, 1) 136 137 G_NORETURN void hexagon_raise_exception_err(CPUHexagonState *env, 138 uint32_t exception, 139 uintptr_t pc); 140 141 static inline void cpu_get_tb_cpu_state(CPUHexagonState *env, vaddr *pc, 142 uint64_t *cs_base, uint32_t *flags) 143 { 144 uint32_t hex_flags = 0; 145 *pc = env->gpr[HEX_REG_PC]; 146 *cs_base = 0; 147 if (*pc == env->gpr[HEX_REG_SA0]) { 148 hex_flags = FIELD_DP32(hex_flags, TB_FLAGS, IS_TIGHT_LOOP, 1); 149 } 150 *flags = hex_flags; 151 if (*pc & PCALIGN_MASK) { 152 hexagon_raise_exception_err(env, HEX_EXCP_PC_NOT_ALIGNED, 0); 153 } 154 } 155 156 typedef HexagonCPU ArchCPU; 157 158 void hexagon_translate_init(void); 159 160 #include "exec/cpu-all.h" 161 162 #endif /* HEXAGON_CPU_H */ 163